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ath9k: Proper padding/unpadding for the TX/RX path.
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
af03abec 20#include "hw.h"
cfe8cba9 21#include "rc.h"
f078f209
LR		 22#include "initvals.h"
23
4febf7b8
LR		 24#define ATH9K_CLOCK_RATE_CCK 22
25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 27
cbe61d8a 28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
25c56eec 29static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
cbe61d8a 30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072 31 struct ar5416_eeprom_def *pEepData,
f1dc5600 32 u32 reg, u32 value);
f078f209 33
7322fd19
LR		 34MODULE_AUTHOR("Atheros Communications");
35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37MODULE_LICENSE("Dual BSD/GPL");
38
39static int __init ath9k_init(void)
40{
41 return 0;
42}
43module_init(ath9k_init);
44
45static void __exit ath9k_exit(void)
46{
47 return;
48}
49module_exit(ath9k_exit);
50
f1dc5600
S		 51/********************/
52/* Helper Functions */
53/********************/
f078f209 54
cbe61d8a 55static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
f1dc5600 56{
b002a4a9 57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 58
2660b81a 59 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 60 return clks / ATH9K_CLOCK_RATE_CCK;
61 if (conf->channel->band == IEEE80211_BAND_2GHZ)
62 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
cbe61d8a 63
4febf7b8 64 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 65}
f078f209 66
cbe61d8a 67static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
f1dc5600 68{
b002a4a9 69 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 70
4febf7b8 71 if (conf_is_ht40(conf))
f1dc5600
S		 72 return ath9k_hw_mac_usec(ah, clks) / 2;
73 else
74 return ath9k_hw_mac_usec(ah, clks);
75}
f078f209 76
cbe61d8a 77static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 78{
b002a4a9 79 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 80
2660b81a 81 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 82 return usecs *ATH9K_CLOCK_RATE_CCK;
83 if (conf->channel->band == IEEE80211_BAND_2GHZ)
84 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
85 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 86}
87
cbe61d8a 88static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 89{
b002a4a9 90 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 91
4febf7b8 92 if (conf_is_ht40(conf))
f1dc5600
S		 93 return ath9k_hw_mac_clks(ah, usecs) * 2;
94 else
95 return ath9k_hw_mac_clks(ah, usecs);
96}
f078f209 97
0caa7b14 98bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 99{
100 int i;
101
0caa7b14
S		 102 BUG_ON(timeout < AH_TIME_QUANTUM);
103
104 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 105 if ((REG_READ(ah, reg) & mask) == val)
106 return true;
107
108 udelay(AH_TIME_QUANTUM);
109 }
04bd4638 110
c46917bb
LR		 111 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
112 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
113 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 114
f1dc5600 115 return false;
f078f209 116}
7322fd19 117EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 118
119u32 ath9k_hw_reverse_bits(u32 val, u32 n)
120{
121 u32 retval;
122 int i;
123
124 for (i = 0, retval = 0; i < n; i++) {
125 retval = (retval << 1) | (val & 1);
126 val >>= 1;
127 }
128 return retval;
129}
130
cbe61d8a 131bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 132 u16 flags, u16 *low,
133 u16 *high)
f078f209 134{
2660b81a 135 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 136
f1dc5600
S		 137 if (flags & CHANNEL_5GHZ) {
138 *low = pCap->low_5ghz_chan;
139 *high = pCap->high_5ghz_chan;
140 return true;
f078f209 141 }
f1dc5600
S		 142 if ((flags & CHANNEL_2GHZ)) {
143 *low = pCap->low_2ghz_chan;
144 *high = pCap->high_2ghz_chan;
145 return true;
146 }
147 return false;
f078f209
LR		 148}
149
cbe61d8a 150u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 151 u8 phy, int kbps,
f1dc5600
S		 152 u32 frameLen, u16 rateix,
153 bool shortPreamble)
f078f209 154{
f1dc5600 155 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 156
f1dc5600
S		 157 if (kbps == 0)
158 return 0;
f078f209 159
545750d3 160 switch (phy) {
46d14a58 161 case WLAN_RC_PHY_CCK:
f1dc5600 162 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 163 if (shortPreamble)
f1dc5600
S		 164 phyTime >>= 1;
165 numBits = frameLen << 3;
166 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
167 break;
46d14a58 168 case WLAN_RC_PHY_OFDM:
2660b81a 169 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 170 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
171 numBits = OFDM_PLCP_BITS + (frameLen << 3);
172 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
173 txTime = OFDM_SIFS_TIME_QUARTER
174 + OFDM_PREAMBLE_TIME_QUARTER
175 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 176 } else if (ah->curchan &&
177 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 178 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
179 numBits = OFDM_PLCP_BITS + (frameLen << 3);
180 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
181 txTime = OFDM_SIFS_TIME_HALF +
182 OFDM_PREAMBLE_TIME_HALF
183 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
184 } else {
185 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
186 numBits = OFDM_PLCP_BITS + (frameLen << 3);
187 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
188 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
189 + (numSymbols * OFDM_SYMBOL_TIME);
190 }
191 break;
192 default:
c46917bb 193 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 194 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 195 txTime = 0;
196 break;
197 }
f078f209 198
f1dc5600
S		 199 return txTime;
200}
7322fd19 201EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 202
cbe61d8a 203void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 204 struct ath9k_channel *chan,
205 struct chan_centers *centers)
f078f209 206{
f1dc5600 207 int8_t extoff;
f078f209 208
f1dc5600
S		 209 if (!IS_CHAN_HT40(chan)) {
210 centers->ctl_center = centers->ext_center =
211 centers->synth_center = chan->channel;
212 return;
f078f209 213 }
f078f209 214
f1dc5600
S		 215 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
216 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
217 centers->synth_center =
218 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
219 extoff = 1;
220 } else {
221 centers->synth_center =
222 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
223 extoff = -1;
224 }
f078f209 225
f1dc5600
S		 226 centers->ctl_center =
227 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 228 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 229 centers->ext_center =
6420014c 230 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 231}
232
f1dc5600
S		 233/******************/
234/* Chip Revisions */
235/******************/
236
cbe61d8a 237static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 238{
f1dc5600 239 u32 val;
f078f209 240
f1dc5600 241 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 242
f1dc5600
S		 243 if (val == 0xFF) {
244 val = REG_READ(ah, AR_SREV);
d535a42a
S		 245 ah->hw_version.macVersion =
246 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
247 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 248 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 249 } else {
250 if (!AR_SREV_9100(ah))
d535a42a 251 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 252
d535a42a 253 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 254
d535a42a 255 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 256 ah->is_pciexpress = true;
f1dc5600 257 }
f078f209
LR		 258}
259
cbe61d8a 260static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 261{
f1dc5600
S		 262 u32 val;
263 int i;
f078f209 264
f1dc5600 265 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 266
f1dc5600
S		 267 for (i = 0; i < 8; i++)
268 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
269 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
270 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 271
f1dc5600 272 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 273}
274
f1dc5600
S		 275/************************************/
276/* HW Attach, Detach, Init Routines */
277/************************************/
278
cbe61d8a 279static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 280{
feed029c 281 if (AR_SREV_9100(ah))
f1dc5600 282 return;
f078f209 283
f1dc5600
S		 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 293
f1dc5600 294 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 295}
296
cbe61d8a 297static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 298{
c46917bb 299 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 300 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
301 u32 regHold[2];
302 u32 patternData[4] = { 0x55555555,
303 0xaaaaaaaa,
304 0x66666666,
305 0x99999999 };
306 int i, j;
f078f209 307
f1dc5600
S		 308 for (i = 0; i < 2; i++) {
309 u32 addr = regAddr[i];
310 u32 wrData, rdData;
f078f209 311
f1dc5600
S		 312 regHold[i] = REG_READ(ah, addr);
313 for (j = 0; j < 0x100; j++) {
314 wrData = (j << 16) | j;
315 REG_WRITE(ah, addr, wrData);
316 rdData = REG_READ(ah, addr);
317 if (rdData != wrData) {
c46917bb
LR		 318 ath_print(common, ATH_DBG_FATAL,
319 "address test failed "
320 "addr: 0x%08x - wr:0x%08x != "
321 "rd:0x%08x\n",
322 addr, wrData, rdData);
f1dc5600
S		 323 return false;
324 }
325 }
326 for (j = 0; j < 4; j++) {
327 wrData = patternData[j];
328 REG_WRITE(ah, addr, wrData);
329 rdData = REG_READ(ah, addr);
330 if (wrData != rdData) {
c46917bb
LR		 331 ath_print(common, ATH_DBG_FATAL,
332 "address test failed "
333 "addr: 0x%08x - wr:0x%08x != "
334 "rd:0x%08x\n",
335 addr, wrData, rdData);
f1dc5600
S		 336 return false;
337 }
f078f209 338 }
f1dc5600 339 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 340 }
f1dc5600 341 udelay(100);
cbe61d8a 342
f078f209
LR		 343 return true;
344}
345
f1dc5600 346static const char *ath9k_hw_devname(u16 devid)
f078f209 347{
f1dc5600
S		 348 switch (devid) {
349 case AR5416_DEVID_PCI:
f1dc5600 350 return "Atheros 5416";
392dff83
BP		 351 case AR5416_DEVID_PCIE:
352 return "Atheros 5418";
f1dc5600
S		 353 case AR9160_DEVID_PCI:
354 return "Atheros 9160";
0c1aa495
GJ		 355 case AR5416_AR9100_DEVID:
356 return "Atheros 9100";
f1dc5600
S		 357 case AR9280_DEVID_PCI:
358 case AR9280_DEVID_PCIE:
359 return "Atheros 9280";
e7594072
SB		 360 case AR9285_DEVID_PCIE:
361 return "Atheros 9285";
ac88b6ec
VN		 362 case AR5416_DEVID_AR9287_PCI:
363 case AR5416_DEVID_AR9287_PCIE:
364 return "Atheros 9287";
f078f209
LR		 365 }
366
f1dc5600
S		 367 return NULL;
368}
f078f209 369
b8b0f377 370static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 371{
372 int i;
f078f209 373
2660b81a
S		 374 ah->config.dma_beacon_response_time = 2;
375 ah->config.sw_beacon_response_time = 10;
376 ah->config.additional_swba_backoff = 0;
377 ah->config.ack_6mb = 0x0;
378 ah->config.cwm_ignore_extcca = 0;
379 ah->config.pcie_powersave_enable = 0;
2660b81a 380 ah->config.pcie_clock_req = 0;
2660b81a
S		 381 ah->config.pcie_waen = 0;
382 ah->config.analog_shiftreg = 1;
383 ah->config.ht_enable = 1;
384 ah->config.ofdm_trig_low = 200;
385 ah->config.ofdm_trig_high = 500;
386 ah->config.cck_trig_high = 200;
387 ah->config.cck_trig_low = 100;
388 ah->config.enable_ani = 1;
f078f209 389
f1dc5600 390 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 391 ah->config.spurchans[i][0] = AR_NO_SPUR;
392 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 393 }
394
0ef1f168 395 ah->config.intr_mitigation = true;
6158425b
LR		 396
397 /*
398 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
399 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
400 * This means we use it for all AR5416 devices, and the few
401 * minor PCI AR9280 devices out there.
402 *
403 * Serialization is required because these devices do not handle
404 * well the case of two concurrent reads/writes due to the latency
405 * involved. During one read/write another read/write can be issued
406 * on another CPU while the previous read/write may still be working
407 * on our hardware, if we hit this case the hardware poops in a loop.
408 * We prevent this by serializing reads and writes.
409 *
410 * This issue is not present on PCI-Express devices or pre-AR5416
411 * devices (legacy, 802.11abg).
412 */
413 if (num_possible_cpus() > 1)
2d6a5e95 414 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209 415}
7322fd19 416EXPORT_SYMBOL(ath9k_hw_init);
f078f209 417
50aca25b 418static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 419{
608b88cb
LR		 420 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
421
422 regulatory->country_code = CTRY_DEFAULT;
423 regulatory->power_limit = MAX_RATE_POWER;
424 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
425
d535a42a 426 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 427 ah->hw_version.subvendorid = 0;
f078f209
LR		 428
429 ah->ah_flags = 0;
8df5d1b7 430 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
d535a42a 431 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
f078f209
LR		 432 if (!AR_SREV_9100(ah))
433 ah->ah_flags = AH_USE_EEPROM;
434
2660b81a 435 ah->atim_window = 0;
2660b81a
S		 436 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
437 ah->beacon_interval = 100;
438 ah->enable_32kHz_clock = DONT_USE_32KHZ;
439 ah->slottime = (u32) -1;
440 ah->acktimeout = (u32) -1;
441 ah->ctstimeout = (u32) -1;
442 ah->globaltxtimeout = (u32) -1;
cbdec975 443 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 444}
445
cbe61d8a 446static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 447{
f1dc5600
S		 448 u32 val;
449
450 REG_WRITE(ah, AR_PHY(0), 0x00000007);
451
452 val = ath9k_hw_get_radiorev(ah);
453 switch (val & AR_RADIO_SREV_MAJOR) {
454 case 0:
455 val = AR_RAD5133_SREV_MAJOR;
456 break;
457 case AR_RAD5133_SREV_MAJOR:
458 case AR_RAD5122_SREV_MAJOR:
459 case AR_RAD2133_SREV_MAJOR:
460 case AR_RAD2122_SREV_MAJOR:
461 break;
f078f209 462 default:
c46917bb
LR		 463 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
464 "Radio Chip Rev 0x%02X not supported\n",
465 val & AR_RADIO_SREV_MAJOR);
f1dc5600 466 return -EOPNOTSUPP;
f078f209 467 }
f078f209 468
d535a42a 469 ah->hw_version.analog5GhzRev = val;
f078f209 470
f1dc5600 471 return 0;
f078f209
LR		 472}
473
cbe61d8a 474static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 475{
1510718d 476 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 477 u32 sum;
478 int i;
479 u16 eeval;
f078f209
LR		 480
481 sum = 0;
482 for (i = 0; i < 3; i++) {
f74df6fb 483 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 484 sum += eeval;
1510718d
LR		 485 common->macaddr[2 * i] = eeval >> 8;
486 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 487 }
d8baa939 488 if (sum == 0 || sum == 0xffff * 3)
f078f209 489 return -EADDRNOTAVAIL;
f078f209
LR		 490
491 return 0;
492}
493
cbe61d8a 494static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 495{
496 u32 rxgain_type;
9f804202 497
f74df6fb
S		 498 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
499 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 500
501 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 502 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 503 ar9280Modes_backoff_13db_rxgain_9280_2,
504 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
505 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 506 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 507 ar9280Modes_backoff_23db_rxgain_9280_2,
508 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
509 else
2660b81a 510 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 511 ar9280Modes_original_rxgain_9280_2,
512 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 513 } else {
2660b81a 514 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 515 ar9280Modes_original_rxgain_9280_2,
516 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 517 }
9f804202
SB		 518}
519
cbe61d8a 520static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 521{
522 u32 txgain_type;
9f804202 523
f74df6fb
S		 524 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
525 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 526
527 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 528 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 529 ar9280Modes_high_power_tx_gain_9280_2,
530 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
531 else
2660b81a 532 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 533 ar9280Modes_original_tx_gain_9280_2,
534 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 535 } else {
2660b81a 536 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 537 ar9280Modes_original_tx_gain_9280_2,
538 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 539 }
9f804202
SB		 540}
541
f637cfd6 542static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 543{
f1dc5600 544 int ecode;
f078f209 545
d8baa939 546 if (!ath9k_hw_chip_test(ah))
f1dc5600 547 return -ENODEV;
f078f209 548
f1dc5600
S		 549 ecode = ath9k_hw_rf_claim(ah);
550 if (ecode != 0)
f078f209 551 return ecode;
f078f209 552
f637cfd6 553 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 554 if (ecode != 0)
555 return ecode;
7d01b221 556
c46917bb
LR		 557 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
558 "Eeprom VER: %d, REV: %d\n",
559 ah->eep_ops->get_eeprom_ver(ah),
560 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 561
574d6b12
LR		 562 if (!AR_SREV_9280_10_OR_LATER(ah)) {
563 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
564 if (ecode) {
565 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
566 "Failed allocating banks for "
567 "external radio\n");
568 return ecode;
569 }
570 }
f078f209 571
f1dc5600
S		 572 if (!AR_SREV_9100(ah)) {
573 ath9k_hw_ani_setup(ah);
f637cfd6 574 ath9k_hw_ani_init(ah);
f078f209
LR		 575 }
576
f078f209
LR		 577 return 0;
578}
579
ee2bb460
LR		 580static bool ath9k_hw_devid_supported(u16 devid)
581{
582 switch (devid) {
583 case AR5416_DEVID_PCI:
584 case AR5416_DEVID_PCIE:
585 case AR5416_AR9100_DEVID:
586 case AR9160_DEVID_PCI:
587 case AR9280_DEVID_PCI:
588 case AR9280_DEVID_PCIE:
589 case AR9285_DEVID_PCIE:
590 case AR5416_DEVID_AR9287_PCI:
591 case AR5416_DEVID_AR9287_PCIE:
7976b426 592 case AR9271_USB:
ee2bb460
LR		 593 return true;
594 default:
595 break;
596 }
597 return false;
598}
599
f9d4a668
LR		 600static bool ath9k_hw_macversion_supported(u32 macversion)
601{
602 switch (macversion) {
603 case AR_SREV_VERSION_5416_PCI:
604 case AR_SREV_VERSION_5416_PCIE:
605 case AR_SREV_VERSION_9160:
606 case AR_SREV_VERSION_9100:
607 case AR_SREV_VERSION_9280:
608 case AR_SREV_VERSION_9285:
609 case AR_SREV_VERSION_9287:
d7e7d229 610 case AR_SREV_VERSION_9271:
7976b426 611 return true;
f9d4a668
LR		 612 default:
613 break;
614 }
615 return false;
616}
617
aa4058ae 618static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
f078f209 619{
f1dc5600
S		 620 if (AR_SREV_9160_10_OR_LATER(ah)) {
621 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a
S		 622 ah->iq_caldata.calData = &iq_cal_single_sample;
623 ah->adcgain_caldata.calData =
f1dc5600 624 &adc_gain_cal_single_sample;
2660b81a 625 ah->adcdc_caldata.calData =
f1dc5600 626 &adc_dc_cal_single_sample;
2660b81a 627 ah->adcdc_calinitdata.calData =
f1dc5600
S		 628 &adc_init_dc_cal;
629 } else {
2660b81a
S		 630 ah->iq_caldata.calData = &iq_cal_multi_sample;
631 ah->adcgain_caldata.calData =
f1dc5600 632 &adc_gain_cal_multi_sample;
2660b81a 633 ah->adcdc_caldata.calData =
f1dc5600 634 &adc_dc_cal_multi_sample;
2660b81a 635 ah->adcdc_calinitdata.calData =
f1dc5600
S		 636 &adc_init_dc_cal;
637 }
2660b81a 638 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
f1dc5600 639 }
aa4058ae 640}
f078f209 641
aa4058ae
LR		 642static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
643{
d7e7d229 644 if (AR_SREV_9271(ah)) {
8564328d
LR		 645 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
646 ARRAY_SIZE(ar9271Modes_9271), 6);
647 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
648 ARRAY_SIZE(ar9271Common_9271), 2);
649 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
650 ar9271Modes_9271_1_0_only,
651 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
d7e7d229
LR		 652 return;
653 }
654
ac88b6ec
VN		 655 if (AR_SREV_9287_11_OR_LATER(ah)) {
656 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
657 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
658 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
659 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
660 if (ah->config.pcie_clock_req)
661 INIT_INI_ARRAY(&ah->iniPcieSerdes,
662 ar9287PciePhy_clkreq_off_L1_9287_1_1,
663 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
664 else
665 INIT_INI_ARRAY(&ah->iniPcieSerdes,
666 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
667 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
668 2);
669 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
670 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
671 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
672 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
673 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
674
675 if (ah->config.pcie_clock_req)
676 INIT_INI_ARRAY(&ah->iniPcieSerdes,
677 ar9287PciePhy_clkreq_off_L1_9287_1_0,
678 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
679 else
680 INIT_INI_ARRAY(&ah->iniPcieSerdes,
681 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
682 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
683 2);
684 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
f078f209 685
4e845168 686
2660b81a 687 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
e7594072 688 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
2660b81a 689 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
e7594072
SB		 690 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
691
2660b81a
S		 692 if (ah->config.pcie_clock_req) {
693 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 694 ar9285PciePhy_clkreq_off_L1_9285_1_2,
695 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
696 } else {
2660b81a 697 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 698 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
699 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
700 2);
701 }
702 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
2660b81a 703 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
e7594072 704 ARRAY_SIZE(ar9285Modes_9285), 6);
2660b81a 705 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
e7594072
SB		 706 ARRAY_SIZE(ar9285Common_9285), 2);
707
2660b81a
S		 708 if (ah->config.pcie_clock_req) {
709 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 710 ar9285PciePhy_clkreq_off_L1_9285,
711 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
712 } else {
2660b81a 713 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 714 ar9285PciePhy_clkreq_always_on_L1_9285,
715 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
716 }
717 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2660b81a 718 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
f1dc5600 719 ARRAY_SIZE(ar9280Modes_9280_2), 6);
2660b81a 720 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
f1dc5600 721 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 722
2660b81a
S		 723 if (ah->config.pcie_clock_req) {
724 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 725 ar9280PciePhy_clkreq_off_L1_9280,
726 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
727 } else {
2660b81a 728 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 729 ar9280PciePhy_clkreq_always_on_L1_9280,
730 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
731 }
2660b81a 732 INIT_INI_ARRAY(&ah->iniModesAdditional,
f1dc5600
S		 733 ar9280Modes_fast_clock_9280_2,
734 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
735 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 736 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
f1dc5600 737 ARRAY_SIZE(ar9280Modes_9280), 6);
2660b81a 738 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
f1dc5600
S		 739 ARRAY_SIZE(ar9280Common_9280), 2);
740 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2660b81a 741 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
f1dc5600 742 ARRAY_SIZE(ar5416Modes_9160), 6);
2660b81a 743 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
f1dc5600 744 ARRAY_SIZE(ar5416Common_9160), 2);
2660b81a 745 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
f1dc5600 746 ARRAY_SIZE(ar5416Bank0_9160), 2);
2660b81a 747 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
f1dc5600 748 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
2660b81a 749 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
f1dc5600 750 ARRAY_SIZE(ar5416Bank1_9160), 2);
2660b81a 751 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
f1dc5600 752 ARRAY_SIZE(ar5416Bank2_9160), 2);
2660b81a 753 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
f1dc5600 754 ARRAY_SIZE(ar5416Bank3_9160), 3);
2660b81a 755 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
f1dc5600 756 ARRAY_SIZE(ar5416Bank6_9160), 3);
2660b81a 757 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
f1dc5600 758 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
2660b81a 759 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
f1dc5600
S		 760 ARRAY_SIZE(ar5416Bank7_9160), 2);
761 if (AR_SREV_9160_11(ah)) {
2660b81a 762 INIT_INI_ARRAY(&ah->iniAddac,
f1dc5600
S		 763 ar5416Addac_91601_1,
764 ARRAY_SIZE(ar5416Addac_91601_1), 2);
765 } else {
2660b81a 766 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
f1dc5600
S		 767 ARRAY_SIZE(ar5416Addac_9160), 2);
768 }
769 } else if (AR_SREV_9100_OR_LATER(ah)) {
2660b81a 770 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
f1dc5600 771 ARRAY_SIZE(ar5416Modes_9100), 6);
2660b81a 772 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
f1dc5600 773 ARRAY_SIZE(ar5416Common_9100), 2);
2660b81a 774 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
f1dc5600 775 ARRAY_SIZE(ar5416Bank0_9100), 2);
2660b81a 776 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
f1dc5600 777 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
2660b81a 778 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
f1dc5600 779 ARRAY_SIZE(ar5416Bank1_9100), 2);
2660b81a 780 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
f1dc5600 781 ARRAY_SIZE(ar5416Bank2_9100), 2);
2660b81a 782 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
f1dc5600 783 ARRAY_SIZE(ar5416Bank3_9100), 3);
2660b81a 784 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
f1dc5600 785 ARRAY_SIZE(ar5416Bank6_9100), 3);
2660b81a 786 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
f1dc5600 787 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
2660b81a 788 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
f1dc5600 789 ARRAY_SIZE(ar5416Bank7_9100), 2);
2660b81a 790 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
f1dc5600
S		 791 ARRAY_SIZE(ar5416Addac_9100), 2);
792 } else {
2660b81a 793 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
f1dc5600 794 ARRAY_SIZE(ar5416Modes), 6);
2660b81a 795 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
f1dc5600 796 ARRAY_SIZE(ar5416Common), 2);
2660b81a 797 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
f1dc5600 798 ARRAY_SIZE(ar5416Bank0), 2);
2660b81a 799 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
f1dc5600 800 ARRAY_SIZE(ar5416BB_RfGain), 3);
2660b81a 801 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
f1dc5600 802 ARRAY_SIZE(ar5416Bank1), 2);
2660b81a 803 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
f1dc5600 804 ARRAY_SIZE(ar5416Bank2), 2);
2660b81a 805 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
f1dc5600 806 ARRAY_SIZE(ar5416Bank3), 3);
2660b81a 807 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
f1dc5600 808 ARRAY_SIZE(ar5416Bank6), 3);
2660b81a 809 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
f1dc5600 810 ARRAY_SIZE(ar5416Bank6TPC), 3);
2660b81a 811 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
f1dc5600 812 ARRAY_SIZE(ar5416Bank7), 2);
2660b81a 813 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
f1dc5600 814 ARRAY_SIZE(ar5416Addac), 2);
f078f209 815 }
aa4058ae 816}
f078f209 817
aa4058ae
LR		 818static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
819{
b37fa870 820 if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec
VN		 821 INIT_INI_ARRAY(&ah->iniModesRxGain,
822 ar9287Modes_rx_gain_9287_1_1,
823 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
824 else if (AR_SREV_9287_10(ah))
825 INIT_INI_ARRAY(&ah->iniModesRxGain,
826 ar9287Modes_rx_gain_9287_1_0,
827 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
828 else if (AR_SREV_9280_20(ah))
829 ath9k_hw_init_rxgain_ini(ah);
830
b37fa870 831 if (AR_SREV_9287_11_OR_LATER(ah)) {
ac88b6ec
VN		 832 INIT_INI_ARRAY(&ah->iniModesTxGain,
833 ar9287Modes_tx_gain_9287_1_1,
834 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
835 } else if (AR_SREV_9287_10(ah)) {
836 INIT_INI_ARRAY(&ah->iniModesTxGain,
837 ar9287Modes_tx_gain_9287_1_0,
838 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
839 } else if (AR_SREV_9280_20(ah)) {
840 ath9k_hw_init_txgain_ini(ah);
841 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4e845168
SB		 842 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
843
844 /* txgain table */
845 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
846 INIT_INI_ARRAY(&ah->iniModesTxGain,
847 ar9285Modes_high_power_tx_gain_9285_1_2,
848 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
849 } else {
850 INIT_INI_ARRAY(&ah->iniModesTxGain,
851 ar9285Modes_original_tx_gain_9285_1_2,
852 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
853 }
854
855 }
aa4058ae 856}
4e845168 857
aa4058ae
LR		 858static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
859{
860 u32 i, j;
06d0f066
S		 861
862 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
863 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
864
865 /* EEPROM Fixup */
2660b81a
S		 866 for (i = 0; i < ah->iniModes.ia_rows; i++) {
867 u32 reg = INI_RA(&ah->iniModes, i, 0);
f078f209 868
2660b81a
S		 869 for (j = 1; j < ah->iniModes.ia_columns; j++) {
870 u32 val = INI_RA(&ah->iniModes, i, j);
f078f209 871
2660b81a 872 INI_RA(&ah->iniModes, i, j) =
e7594072 873 ath9k_hw_ini_fixup(ah,
2660b81a 874 &ah->eeprom.def,
f1dc5600
S		 875 reg, val);
876 }
f078f209 877 }
f1dc5600 878 }
aa4058ae
LR		 879}
880
f637cfd6 881int ath9k_hw_init(struct ath_hw *ah)
aa4058ae 882{
c46917bb 883 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 884 int r = 0;
aa4058ae 885
3ca34038
LR		 886 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
887 ath_print(common, ATH_DBG_FATAL,
888 "Unsupported device ID: 0x%0x\n",
889 ah->hw_version.devid);
95fafca2 890 return -EOPNOTSUPP;
3ca34038 891 }
aa4058ae
LR		 892
893 ath9k_hw_init_defaults(ah);
894 ath9k_hw_init_config(ah);
895
896 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 897 ath_print(common, ATH_DBG_FATAL,
898 "Couldn't reset chip\n");
95fafca2 899 return -EIO;
aa4058ae
LR		 900 }
901
9ecdef4b 902 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 903 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 904 return -EIO;
aa4058ae
LR		 905 }
906
907 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
908 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
909 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
910 ah->config.serialize_regmode =
911 SER_REG_MODE_ON;
912 } else {
913 ah->config.serialize_regmode =
914 SER_REG_MODE_OFF;
915 }
916 }
917
c46917bb 918 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 919 ah->config.serialize_regmode);
920
921 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
c46917bb
LR		 922 ath_print(common, ATH_DBG_FATAL,
923 "Mac Chip Rev 0x%02x.%x is not supported by "
924 "this driver\n", ah->hw_version.macVersion,
925 ah->hw_version.macRev);
95fafca2 926 return -EOPNOTSUPP;
aa4058ae
LR		 927 }
928
929 if (AR_SREV_9100(ah)) {
930 ah->iq_caldata.calData = &iq_cal_multi_sample;
931 ah->supp_cals = IQ_MISMATCH_CAL;
932 ah->is_pciexpress = false;
933 }
d7e7d229
LR		 934
935 if (AR_SREV_9271(ah))
936 ah->is_pciexpress = false;
937
aa4058ae
LR		 938 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
939
940 ath9k_hw_init_cal_settings(ah);
941
942 ah->ani_function = ATH9K_ANI_ALL;
e68a060b 943 if (AR_SREV_9280_10_OR_LATER(ah)) {
aa4058ae 944 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e68a060b 945 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
ae478cf6
LR		 946 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
947 } else {
e68a060b 948 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
ae478cf6
LR		 949 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
950 }
aa4058ae
LR		 951
952 ath9k_hw_init_mode_regs(ah);
953
954 if (ah->is_pciexpress)
93b1b37f 955 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 956 else
957 ath9k_hw_disablepcie(ah);
958
193cd458
S		 959 /* Support for Japan ch.14 (2484) spread */
960 if (AR_SREV_9287_11_OR_LATER(ah)) {
961 INIT_INI_ARRAY(&ah->iniCckfirNormal,
962 ar9287Common_normal_cck_fir_coeff_92871_1,
963 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
964 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
965 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
966 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
967 }
968
f637cfd6 969 r = ath9k_hw_post_init(ah);
aa4058ae 970 if (r)
95fafca2 971 return r;
aa4058ae
LR		 972
973 ath9k_hw_init_mode_gain_regs(ah);
974 ath9k_hw_fill_cap_info(ah);
975 ath9k_hw_init_11a_eeprom_fix(ah);
f6688cd8 976
4f3acf81
LR		 977 r = ath9k_hw_init_macaddr(ah);
978 if (r) {
c46917bb
LR		 979 ath_print(common, ATH_DBG_FATAL,
980 "Failed to initialize MAC address\n");
95fafca2 981 return r;
f078f209
LR		 982 }
983
d7e7d229 984 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 985 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 986 else
2660b81a 987 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 988
f1dc5600 989 ath9k_init_nfcal_hist_buffer(ah);
f078f209 990
211f5859
LR		 991 common->state = ATH_HW_INITIALIZED;
992
4f3acf81 993 return 0;
f078f209
LR		 994}
995
cbe61d8a 996static void ath9k_hw_init_bb(struct ath_hw *ah,
f1dc5600 997 struct ath9k_channel *chan)
f078f209 998{
f1dc5600 999 u32 synthDelay;
f078f209 1000
f1dc5600 1001 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1002 if (IS_CHAN_B(chan))
f1dc5600
S		 1003 synthDelay = (4 * synthDelay) / 22;
1004 else
1005 synthDelay /= 10;
f078f209 1006
f1dc5600 1007 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 1008
f1dc5600 1009 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 1010}
1011
cbe61d8a 1012static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 1013{
f1dc5600
S		 1014 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1015 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 1016
f1dc5600
S		 1017 REG_WRITE(ah, AR_QOS_NO_ACK,
1018 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1019 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1020 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1021
1022 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1023 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1024 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1025 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1026 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 1027}
1028
c75724d1
LR		 1029static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
1030{
1031 u32 lcr;
1032 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
1033
1034 lcr = REG_READ(ah , 0x5100c);
1035 lcr |= 0x80;
1036
1037 REG_WRITE(ah, 0x5100c, lcr);
1038 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1039 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1040
1041 lcr &= ~0x80;
1042 REG_WRITE(ah, 0x5100c, lcr);
1043}
1044
cbe61d8a 1045static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 1046 struct ath9k_channel *chan)
f078f209 1047{
f1dc5600 1048 u32 pll;
f078f209 1049
f1dc5600
S		 1050 if (AR_SREV_9100(ah)) {
1051 if (chan && IS_CHAN_5GHZ(chan))
1052 pll = 0x1450;
f078f209 1053 else
f1dc5600
S		 1054 pll = 0x1458;
1055 } else {
1056 if (AR_SREV_9280_10_OR_LATER(ah)) {
1057 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1058
f1dc5600
S		 1059 if (chan && IS_CHAN_HALF_RATE(chan))
1060 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1061 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1062 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1063
f1dc5600
S		 1064 if (chan && IS_CHAN_5GHZ(chan)) {
1065 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 1066
f078f209 1067
f1dc5600
S		 1068 if (AR_SREV_9280_20(ah)) {
1069 if (((chan->channel % 20) == 0)
1070 || ((chan->channel % 10) == 0))
1071 pll = 0x2850;
1072 else
1073 pll = 0x142c;
1074 }
1075 } else {
1076 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1077 }
f078f209 1078
f1dc5600 1079 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 1080
f1dc5600 1081 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1082
f1dc5600
S		 1083 if (chan && IS_CHAN_HALF_RATE(chan))
1084 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1085 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1086 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1087
f1dc5600
S		 1088 if (chan && IS_CHAN_5GHZ(chan))
1089 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1090 else
1091 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1092 } else {
1093 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 1094
f1dc5600
S		 1095 if (chan && IS_CHAN_HALF_RATE(chan))
1096 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1097 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1098 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 1099
f1dc5600
S		 1100 if (chan && IS_CHAN_5GHZ(chan))
1101 pll |= SM(0xa, AR_RTC_PLL_DIV);
1102 else
1103 pll |= SM(0xb, AR_RTC_PLL_DIV);
1104 }
1105 }
d03a66c1 1106 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 1107
c75724d1
LR		 1108 /* Switch the core clock for ar9271 to 117Mhz */
1109 if (AR_SREV_9271(ah)) {
1110 if ((pll == 0x142c) || (pll == 0x2850) ) {
1111 udelay(500);
1112 /* set CLKOBS to output AHB clock */
1113 REG_WRITE(ah, 0x7020, 0xe);
1114 /*
1115 * 0x304: 117Mhz, ahb_ratio: 1x1
1116 * 0x306: 40Mhz, ahb_ratio: 1x1
1117 */
1118 REG_WRITE(ah, 0x50040, 0x304);
1119 /*
1120 * makes adjustments for the baud dividor to keep the
1121 * targetted baud rate based on the used core clock.
1122 */
1123 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1124 AR9271_TARGET_BAUD_RATE);
1125 }
1126 }
1127
f1dc5600
S		 1128 udelay(RTC_PLL_SETTLE_DELAY);
1129
1130 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 1131}
1132
cbe61d8a 1133static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
f078f209 1134{
f078f209
LR		 1135 int rx_chainmask, tx_chainmask;
1136
2660b81a
S		 1137 rx_chainmask = ah->rxchainmask;
1138 tx_chainmask = ah->txchainmask;
f078f209
LR		 1139
1140 switch (rx_chainmask) {
1141 case 0x5:
1142 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1143 AR_PHY_SWAP_ALT_CHAIN);
1144 case 0x3:
cb53a150 1145 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
f078f209
LR		 1146 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1147 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1148 break;
1149 }
1150 case 0x1:
1151 case 0x2:
f078f209
LR		 1152 case 0x7:
1153 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1154 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1155 break;
1156 default:
1157 break;
1158 }
1159
1160 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1161 if (tx_chainmask == 0x5) {
1162 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1163 AR_PHY_SWAP_ALT_CHAIN);
1164 }
1165 if (AR_SREV_9100(ah))
1166 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1167 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1168}
1169
cbe61d8a 1170static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 1171 enum nl80211_iftype opmode)
f078f209 1172{
2660b81a 1173 ah->mask_reg = AR_IMR_TXERR |
f1dc5600
S		 1174 AR_IMR_TXURN |
1175 AR_IMR_RXERR |
1176 AR_IMR_RXORN |
1177 AR_IMR_BCNMISC;
f078f209 1178
0ef1f168 1179 if (ah->config.intr_mitigation)
2660b81a 1180 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1181 else
2660b81a 1182 ah->mask_reg |= AR_IMR_RXOK;
f078f209 1183
2660b81a 1184 ah->mask_reg |= AR_IMR_TXOK;
f078f209 1185
d97809db 1186 if (opmode == NL80211_IFTYPE_AP)
2660b81a 1187 ah->mask_reg |= AR_IMR_MIB;
f078f209 1188
2660b81a 1189 REG_WRITE(ah, AR_IMR, ah->mask_reg);
f1dc5600 1190 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1191
f1dc5600
S		 1192 if (!AR_SREV_9100(ah)) {
1193 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1194 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1195 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1196 }
f078f209
LR		 1197}
1198
cbe61d8a 1199static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1200{
f078f209 1201 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
c46917bb
LR		 1202 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1203 "bad ack timeout %u\n", us);
2660b81a 1204 ah->acktimeout = (u32) -1;
f078f209
LR		 1205 return false;
1206 } else {
1207 REG_RMW_FIELD(ah, AR_TIME_OUT,
1208 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1209 ah->acktimeout = us;
f078f209
LR		 1210 return true;
1211 }
1212}
1213
cbe61d8a 1214static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
f078f209 1215{
f078f209 1216 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
c46917bb
LR		 1217 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1218 "bad cts timeout %u\n", us);
2660b81a 1219 ah->ctstimeout = (u32) -1;
f078f209
LR		 1220 return false;
1221 } else {
1222 REG_RMW_FIELD(ah, AR_TIME_OUT,
1223 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1224 ah->ctstimeout = us;
f078f209
LR		 1225 return true;
1226 }
1227}
f1dc5600 1228
cbe61d8a 1229static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1230{
f078f209 1231 if (tu > 0xFFFF) {
c46917bb
LR		 1232 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1233 "bad global tx timeout %u\n", tu);
2660b81a 1234 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1235 return false;
1236 } else {
1237 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1238 ah->globaltxtimeout = tu;
f078f209
LR		 1239 return true;
1240 }
1241}
1242
cbe61d8a 1243static void ath9k_hw_init_user_settings(struct ath_hw *ah)
f078f209 1244{
c46917bb
LR		 1245 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1246 ah->misc_mode);
f078f209 1247
2660b81a 1248 if (ah->misc_mode != 0)
f1dc5600 1249 REG_WRITE(ah, AR_PCU_MISC,
2660b81a
S		 1250 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1251 if (ah->slottime != (u32) -1)
1252 ath9k_hw_setslottime(ah, ah->slottime);
1253 if (ah->acktimeout != (u32) -1)
1254 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1255 if (ah->ctstimeout != (u32) -1)
1256 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1257 if (ah->globaltxtimeout != (u32) -1)
1258 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600
S		 1259}
1260
1261const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1262{
1263 return vendorid == ATHEROS_VENDOR_ID ?
1264 ath9k_hw_devname(devid) : NULL;
1265}
1266
cbe61d8a 1267void ath9k_hw_detach(struct ath_hw *ah)
f1dc5600 1268{
211f5859
LR		 1269 struct ath_common *common = ath9k_hw_common(ah);
1270
1271 if (common->state <= ATH_HW_INITIALIZED)
1272 goto free_hw;
1273
f1dc5600 1274 if (!AR_SREV_9100(ah))
e70c0cfd 1275 ath9k_hw_ani_disable(ah);
f1dc5600 1276
9ecdef4b 1277 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 1278
1279free_hw:
dc51dd50
LR		 1280 if (!AR_SREV_9280_10_OR_LATER(ah))
1281 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 1282 kfree(ah);
9db6b6a2 1283 ah = NULL;
f1dc5600 1284}
7322fd19 1285EXPORT_SYMBOL(ath9k_hw_detach);
f1dc5600 1286
f1dc5600
S		 1287/*******/
1288/* INI */
1289/*******/
1290
cbe61d8a 1291static void ath9k_hw_override_ini(struct ath_hw *ah,
f1dc5600
S		 1292 struct ath9k_channel *chan)
1293{
d7e7d229
LR		 1294 u32 val;
1295
1296 if (AR_SREV_9271(ah)) {
1297 /*
1298 * Enable spectral scan to solution for issues with stuck
1299 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1300 * AR9271 1.1
1301 */
1302 if (AR_SREV_9271_10(ah)) {
ec11bb88
LR		 1303 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1304 AR_PHY_SPECTRAL_SCAN_ENABLE;
d7e7d229
LR		 1305 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1306 }
1307 else if (AR_SREV_9271_11(ah))
1308 /*
1309 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1310 * present on AR9271 1.1
1311 */
1312 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1313 return;
1314 }
1315
8aa15e15
SB		 1316 /*
1317 * Set the RX_ABORT and RX_DIS and clear if off only after
1318 * RXE is set for MAC. This prevents frames with corrupted
1319 * descriptor status.
1320 */
1321 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1322
204d7940
VT		 1323 if (AR_SREV_9280_10_OR_LATER(ah)) {
1324 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1325 (~AR_PCU_MISC_MODE2_HWWAR1);
1326
1327 if (AR_SREV_9287_10_OR_LATER(ah))
1328 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1329
1330 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1331 }
8aa15e15 1332
a8c96d3b 1333 if (!AR_SREV_5416_20_OR_LATER(ah) ||
f1dc5600
S		 1334 AR_SREV_9280_10_OR_LATER(ah))
1335 return;
d7e7d229
LR		 1336 /*
1337 * Disable BB clock gating
1338 * Necessary to avoid issues on AR5416 2.0
1339 */
f1dc5600 1340 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1341}
1342
cbe61d8a 1343static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
e7594072 1344 struct ar5416_eeprom_def *pEepData,
f1dc5600 1345 u32 reg, u32 value)
f078f209 1346{
f1dc5600 1347 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
c46917bb 1348 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1349
d535a42a 1350 switch (ah->hw_version.devid) {
f1dc5600
S		 1351 case AR9280_DEVID_PCI:
1352 if (reg == 0x7894) {
c46917bb 1353 ath_print(common, ATH_DBG_EEPROM,
f1dc5600
S		 1354 "ini VAL: %x EEPROM: %x\n", value,
1355 (pBase->version & 0xff));
1356
1357 if ((pBase->version & 0xff) > 0x0a) {
c46917bb
LR		 1358 ath_print(common, ATH_DBG_EEPROM,
1359 "PWDCLKIND: %d\n",
1360 pBase->pwdclkind);
f1dc5600
S		 1361 value &= ~AR_AN_TOP2_PWDCLKIND;
1362 value |= AR_AN_TOP2_PWDCLKIND &
1363 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1364 } else {
c46917bb
LR		 1365 ath_print(common, ATH_DBG_EEPROM,
1366 "PWDCLKIND Earlier Rev\n");
f1dc5600
S		 1367 }
1368
c46917bb
LR		 1369 ath_print(common, ATH_DBG_EEPROM,
1370 "final ini VAL: %x\n", value);
f1dc5600
S		 1371 }
1372 break;
1373 }
1374
1375 return value;
f078f209
LR		 1376}
1377
cbe61d8a 1378static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072
SB		 1379 struct ar5416_eeprom_def *pEepData,
1380 u32 reg, u32 value)
1381{
2660b81a 1382 if (ah->eep_map == EEP_MAP_4KBITS)
e7594072
SB		 1383 return value;
1384 else
1385 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1386}
1387
8bd1d07f
SB		 1388static void ath9k_olc_init(struct ath_hw *ah)
1389{
1390 u32 i;
1391
db91f2e4
VN		 1392 if (OLC_FOR_AR9287_10_LATER) {
1393 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1394 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1395 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1396 AR9287_AN_TXPC0_TXPCMODE,
1397 AR9287_AN_TXPC0_TXPCMODE_S,
1398 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1399 udelay(100);
1400 } else {
1401 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1402 ah->originalGain[i] =
1403 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1404 AR_PHY_TX_GAIN);
1405 ah->PDADCdelta = 0;
1406 }
8bd1d07f
SB		 1407}
1408
3a702e49
BC		 1409static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1410 struct ath9k_channel *chan)
1411{
1412 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1413
1414 if (IS_CHAN_B(chan))
1415 ctl |= CTL_11B;
1416 else if (IS_CHAN_G(chan))
1417 ctl |= CTL_11G;
1418 else
1419 ctl |= CTL_11A;
1420
1421 return ctl;
1422}
1423
cbe61d8a 1424static int ath9k_hw_process_ini(struct ath_hw *ah,
25c56eec 1425 struct ath9k_channel *chan)
f078f209 1426{
608b88cb 1427 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f078f209 1428 int i, regWrites = 0;
5f8e077c 1429 struct ieee80211_channel *channel = chan->chan;
f078f209 1430 u32 modesIndex, freqIndex;
f078f209
LR		 1431
1432 switch (chan->chanmode) {
1433 case CHANNEL_A:
1434 case CHANNEL_A_HT20:
1435 modesIndex = 1;
1436 freqIndex = 1;
1437 break;
1438 case CHANNEL_A_HT40PLUS:
1439 case CHANNEL_A_HT40MINUS:
1440 modesIndex = 2;
1441 freqIndex = 1;
1442 break;
1443 case CHANNEL_G:
1444 case CHANNEL_G_HT20:
1445 case CHANNEL_B:
1446 modesIndex = 4;
1447 freqIndex = 2;
1448 break;
1449 case CHANNEL_G_HT40PLUS:
1450 case CHANNEL_G_HT40MINUS:
1451 modesIndex = 3;
1452 freqIndex = 2;
1453 break;
1454
1455 default:
1456 return -EINVAL;
1457 }
1458
1459 REG_WRITE(ah, AR_PHY(0), 0x00000007);
f078f209 1460 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
f74df6fb 1461 ah->eep_ops->set_addac(ah, chan);
f078f209 1462
a8c96d3b 1463 if (AR_SREV_5416_22_OR_LATER(ah)) {
2660b81a 1464 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
f078f209
LR		 1465 } else {
1466 struct ar5416IniArray temp;
1467 u32 addacSize =
2660b81a
S		 1468 sizeof(u32) * ah->iniAddac.ia_rows *
1469 ah->iniAddac.ia_columns;
f078f209 1470
2660b81a
S		 1471 memcpy(ah->addac5416_21,
1472 ah->iniAddac.ia_array, addacSize);
f078f209 1473
2660b81a 1474 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
f078f209 1475
2660b81a
S		 1476 temp.ia_array = ah->addac5416_21;
1477 temp.ia_columns = ah->iniAddac.ia_columns;
1478 temp.ia_rows = ah->iniAddac.ia_rows;
f078f209
LR		 1479 REG_WRITE_ARRAY(&temp, 1, regWrites);
1480 }
f1dc5600 1481
f078f209
LR		 1482 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1483
2660b81a
S		 1484 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1485 u32 reg = INI_RA(&ah->iniModes, i, 0);
1486 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
f078f209 1487
f078f209
LR		 1488 REG_WRITE(ah, reg, val);
1489
1490 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1491 && ah->config.analog_shiftreg) {
f078f209
LR		 1492 udelay(100);
1493 }
1494
1495 DO_DELAY(regWrites);
1496 }
1497
ac88b6ec 1498 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1499 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
9f804202 1500
ac88b6ec
VN		 1501 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1502 AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1503 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
9f804202 1504
2660b81a
S		 1505 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1506 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1507 u32 val = INI_RA(&ah->iniCommon, i, 1);
f078f209
LR		 1508
1509 REG_WRITE(ah, reg, val);
1510
1511 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1512 && ah->config.analog_shiftreg) {
f078f209
LR		 1513 udelay(100);
1514 }
1515
1516 DO_DELAY(regWrites);
1517 }
1518
896ff260 1519 ath9k_hw_write_regs(ah, freqIndex, regWrites);
f078f209 1520
8564328d
LR		 1521 if (AR_SREV_9271_10(ah))
1522 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1523 modesIndex, regWrites);
1524
f078f209 1525 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
2660b81a 1526 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
f078f209
LR		 1527 regWrites);
1528 }
1529
1530 ath9k_hw_override_ini(ah, chan);
25c56eec 1531 ath9k_hw_set_regs(ah, chan);
f078f209
LR		 1532 ath9k_hw_init_chain_masks(ah);
1533
8bd1d07f
SB		 1534 if (OLC_FOR_AR9280_20_LATER)
1535 ath9k_olc_init(ah);
1536
8fbff4b8 1537 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1538 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 1539 channel->max_antenna_gain * 2,
1540 channel->max_power * 2,
1541 min((u32) MAX_RATE_POWER,
608b88cb 1542 (u32) regulatory->power_limit));
f078f209
LR		 1543
1544 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
c46917bb
LR		 1545 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1546 "ar5416SetRfRegs failed\n");
f078f209
LR		 1547 return -EIO;
1548 }
1549
1550 return 0;
1551}
1552
f1dc5600
S		 1553/****************************************/
1554/* Reset and Channel Switching Routines */
1555/****************************************/
1556
cbe61d8a 1557static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1558{
f1dc5600
S		 1559 u32 rfMode = 0;
1560
1561 if (chan == NULL)
1562 return;
1563
1564 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1565 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1566
1567 if (!AR_SREV_9280_10_OR_LATER(ah))
1568 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1569 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1570
1571 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1572 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1573
1574 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1575}
1576
cbe61d8a 1577static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
f1dc5600
S		 1578{
1579 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1580}
1581
cbe61d8a 1582static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 1583{
1584 u32 regval;
1585
d7e7d229
LR		 1586 /*
1587 * set AHB_MODE not to do cacheline prefetches
1588 */
f1dc5600
S		 1589 regval = REG_READ(ah, AR_AHB_MODE);
1590 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1591
d7e7d229
LR		 1592 /*
1593 * let mac dma reads be in 128 byte chunks
1594 */
f1dc5600
S		 1595 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1596 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1597
d7e7d229
LR		 1598 /*
1599 * Restore TX Trigger Level to its pre-reset value.
1600 * The initial value depends on whether aggregation is enabled, and is
1601 * adjusted whenever underruns are detected.
1602 */
2660b81a 1603 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1604
d7e7d229
LR		 1605 /*
1606 * let mac dma writes be in 128 byte chunks
1607 */
f1dc5600
S		 1608 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1609 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1610
d7e7d229
LR		 1611 /*
1612 * Setup receive FIFO threshold to hold off TX activities
1613 */
f1dc5600
S		 1614 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1615
d7e7d229
LR		 1616 /*
1617 * reduce the number of usable entries in PCU TXBUF to avoid
1618 * wrap around issues.
1619 */
f1dc5600 1620 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1621 /* For AR9285 the number of Fifos are reduced to half.
1622 * So set the usable tx buf size also to half to
1623 * avoid data/delimiter underruns
1624 */
f1dc5600
S		 1625 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1626 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1627 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1628 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1629 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1630 }
1631}
1632
cbe61d8a 1633static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1634{
1635 u32 val;
1636
1637 val = REG_READ(ah, AR_STA_ID1);
1638 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1639 switch (opmode) {
d97809db 1640 case NL80211_IFTYPE_AP:
f1dc5600
S		 1641 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1642 | AR_STA_ID1_KSRCH_MODE);
1643 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1644 break;
d97809db 1645 case NL80211_IFTYPE_ADHOC:
9cb5412b 1646 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 1647 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1648 | AR_STA_ID1_KSRCH_MODE);
1649 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1650 break;
d97809db
CM		 1651 case NL80211_IFTYPE_STATION:
1652 case NL80211_IFTYPE_MONITOR:
f1dc5600 1653 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1654 break;
f1dc5600
S		 1655 }
1656}
1657
cbe61d8a 1658static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
f1dc5600
S		 1659 u32 coef_scaled,
1660 u32 *coef_mantissa,
1661 u32 *coef_exponent)
1662{
1663 u32 coef_exp, coef_man;
1664
1665 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1666 if ((coef_scaled >> coef_exp) & 0x1)
1667 break;
1668
1669 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1670
1671 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1672
1673 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1674 *coef_exponent = coef_exp - 16;
1675}
1676
cbe61d8a 1677static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
f1dc5600
S		 1678 struct ath9k_channel *chan)
1679{
1680 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1681 u32 clockMhzScaled = 0x64000000;
1682 struct chan_centers centers;
1683
1684 if (IS_CHAN_HALF_RATE(chan))
1685 clockMhzScaled = clockMhzScaled >> 1;
1686 else if (IS_CHAN_QUARTER_RATE(chan))
1687 clockMhzScaled = clockMhzScaled >> 2;
1688
1689 ath9k_hw_get_channel_centers(ah, chan, &centers);
1690 coef_scaled = clockMhzScaled / centers.synth_center;
1691
1692 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1693 &ds_coef_exp);
1694
1695 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1696 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1697 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1698 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1699
1700 coef_scaled = (9 * coef_scaled) / 10;
1701
1702 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1703 &ds_coef_exp);
1704
1705 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1706 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1707 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1708 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1709}
1710
cbe61d8a 1711static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1712{
1713 u32 rst_flags;
1714 u32 tmpReg;
1715
70768496
S		 1716 if (AR_SREV_9100(ah)) {
1717 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1718 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1719 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1720 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1721 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1722 }
1723
f1dc5600
S		 1724 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1725 AR_RTC_FORCE_WAKE_ON_INT);
1726
1727 if (AR_SREV_9100(ah)) {
1728 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1729 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1730 } else {
1731 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1732 if (tmpReg &
1733 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1734 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1735 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1736 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1737 } else {
1738 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1739 }
1740
1741 rst_flags = AR_RTC_RC_MAC_WARM;
1742 if (type == ATH9K_RESET_COLD)
1743 rst_flags |= AR_RTC_RC_MAC_COLD;
1744 }
1745
d03a66c1 1746 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1747 udelay(50);
1748
d03a66c1 1749 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1750 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1751 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1752 "RTC stuck in MAC reset\n");
f1dc5600
S		 1753 return false;
1754 }
1755
1756 if (!AR_SREV_9100(ah))
1757 REG_WRITE(ah, AR_RC, 0);
1758
f1dc5600
S		 1759 if (AR_SREV_9100(ah))
1760 udelay(50);
1761
1762 return true;
1763}
1764
cbe61d8a 1765static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1766{
1767 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1768 AR_RTC_FORCE_WAKE_ON_INT);
1769
1c29ce67
VT		 1770 if (!AR_SREV_9100(ah))
1771 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1772
d03a66c1 1773 REG_WRITE(ah, AR_RTC_RESET, 0);
8bd1d07f 1774 udelay(2);
1c29ce67
VT		 1775
1776 if (!AR_SREV_9100(ah))
1777 REG_WRITE(ah, AR_RC, 0);
1778
d03a66c1 1779 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1780
1781 if (!ath9k_hw_wait(ah,
1782 AR_RTC_STATUS,
1783 AR_RTC_STATUS_M,
0caa7b14
S		 1784 AR_RTC_STATUS_ON,
1785 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1786 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1787 "RTC not waking up\n");
f1dc5600 1788 return false;
f078f209
LR		 1789 }
1790
f1dc5600
S		 1791 ath9k_hw_read_revisions(ah);
1792
1793 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1794}
1795
cbe61d8a 1796static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1797{
1798 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1799 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1800
1801 switch (type) {
1802 case ATH9K_RESET_POWER_ON:
1803 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1804 case ATH9K_RESET_WARM:
1805 case ATH9K_RESET_COLD:
1806 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1807 default:
1808 return false;
1809 }
f078f209
LR		 1810}
1811
25c56eec 1812static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1813{
f1dc5600 1814 u32 phymode;
e7594072 1815 u32 enableDacFifo = 0;
f078f209 1816
e7594072
SB		 1817 if (AR_SREV_9285_10_OR_LATER(ah))
1818 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1819 AR_PHY_FC_ENABLE_DAC_FIFO);
1820
f1dc5600 1821 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1822 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1823
1824 if (IS_CHAN_HT40(chan)) {
1825 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1826
f1dc5600
S		 1827 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1828 (chan->chanmode == CHANNEL_G_HT40PLUS))
1829 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1830
f078f209 1831 }
f1dc5600
S		 1832 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1833
25c56eec 1834 ath9k_hw_set11nmac2040(ah);
f078f209 1835
f1dc5600
S		 1836 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1837 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1838}
1839
cbe61d8a 1840static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1841 struct ath9k_channel *chan)
f078f209 1842{
42abfbee 1843 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1844 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1845 return false;
1846 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1847 return false;
f078f209 1848
9ecdef4b 1849 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1850 return false;
f078f209 1851
2660b81a 1852 ah->chip_fullsleep = false;
f1dc5600 1853 ath9k_hw_init_pll(ah, chan);
f1dc5600 1854 ath9k_hw_set_rfmode(ah, chan);
f078f209 1855
f1dc5600 1856 return true;
f078f209
LR		 1857}
1858
cbe61d8a 1859static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1860 struct ath9k_channel *chan)
f078f209 1861{
608b88cb 1862 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1863 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1864 struct ieee80211_channel *channel = chan->chan;
f078f209 1865 u32 synthDelay, qnum;
0a3b7bac 1866 int r;
f078f209
LR		 1867
1868 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1869 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1870 ath_print(common, ATH_DBG_QUEUE,
1871 "Transmit frames pending on "
1872 "queue %d\n", qnum);
f078f209
LR		 1873 return false;
1874 }
1875 }
1876
1877 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1878 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
0caa7b14 1879 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1880 ath_print(common, ATH_DBG_FATAL,
1881 "Could not kill baseband RX\n");
f078f209
LR		 1882 return false;
1883 }
1884
25c56eec 1885 ath9k_hw_set_regs(ah, chan);
f078f209 1886
e68a060b 1887 r = ah->ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1888 if (r) {
1889 ath_print(common, ATH_DBG_FATAL,
1890 "Failed to set channel\n");
1891 return false;
f078f209
LR		 1892 }
1893
8fbff4b8 1894 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1895 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1896 channel->max_antenna_gain * 2,
1897 channel->max_power * 2,
1898 min((u32) MAX_RATE_POWER,
608b88cb 1899 (u32) regulatory->power_limit));
f078f209
LR		 1900
1901 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1902 if (IS_CHAN_B(chan))
f078f209
LR		 1903 synthDelay = (4 * synthDelay) / 22;
1904 else
1905 synthDelay /= 10;
1906
1907 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1908
1909 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1910
f1dc5600
S		 1911 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1912 ath9k_hw_set_delta_slope(ah, chan);
1913
ae478cf6 1914 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600
S		 1915
1916 if (!chan->oneTimeCalsDone)
1917 chan->oneTimeCalsDone = true;
1918
1919 return true;
1920}
1921
3b319aae
JB		 1922static void ath9k_enable_rfkill(struct ath_hw *ah)
1923{
1924 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1925 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1926
1927 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1928 AR_GPIO_INPUT_MUX2_RFSILENT);
1929
1930 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1931 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1932}
1933
cbe61d8a 1934int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 1935 bool bChannelChange)
f078f209 1936{
1510718d 1937 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1938 u32 saveLedState;
2660b81a 1939 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1940 u32 saveDefAntenna;
1941 u32 macStaId1;
46fe782c 1942 u64 tsf = 0;
ae8d2858 1943 int i, rx_chainmask, r;
f078f209 1944
43c27613
LR		 1945 ah->txchainmask = common->tx_chainmask;
1946 ah->rxchainmask = common->rx_chainmask;
f078f209 1947
9ecdef4b 1948 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1949 return -EIO;
f078f209 1950
9ebef799 1951 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1952 ath9k_hw_getnf(ah, curchan);
1953
1954 if (bChannelChange &&
2660b81a
S		 1955 (ah->chip_fullsleep != true) &&
1956 (ah->curchan != NULL) &&
1957 (chan->channel != ah->curchan->channel) &&
f078f209 1958 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1959 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
0a475cc6
VT		 1960 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1961 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
f078f209 1962
25c56eec 1963 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1964 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 1965 ath9k_hw_start_nfcal(ah);
ae8d2858 1966 return 0;
f078f209
LR		 1967 }
1968 }
1969
1970 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1971 if (saveDefAntenna == 0)
1972 saveDefAntenna = 1;
1973
1974 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1975
46fe782c
S		 1976 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1977 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1978 tsf = ath9k_hw_gettsf64(ah);
1979
f078f209
LR		 1980 saveLedState = REG_READ(ah, AR_CFG_LED) &
1981 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1982 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1983
1984 ath9k_hw_mark_phy_inactive(ah);
1985
d7e7d229
LR		 1986 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1987 REG_WRITE(ah,
1988 AR9271_RESET_POWER_DOWN_CONTROL,
1989 AR9271_RADIO_RF_RST);
1990 udelay(50);
1991 }
1992
f078f209 1993 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1994 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1995 return -EINVAL;
f078f209
LR		 1996 }
1997
d7e7d229
LR		 1998 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1999 ah->htc_reset_init = false;
2000 REG_WRITE(ah,
2001 AR9271_RESET_POWER_DOWN_CONTROL,
2002 AR9271_GATE_MAC_CTL);
2003 udelay(50);
2004 }
2005
46fe782c
S		 2006 /* Restore TSF */
2007 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2008 ath9k_hw_settsf64(ah, tsf);
2009
369391db
VT		 2010 if (AR_SREV_9280_10_OR_LATER(ah))
2011 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 2012
326bebbc 2013 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2014 /* Enable ASYNC FIFO */
2015 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2016 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2017 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2018 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2019 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2020 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2021 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2022 }
25c56eec 2023 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 2024 if (r)
2025 return r;
f078f209 2026
0ced0e17
JM		 2027 /* Setup MFP options for CCMP */
2028 if (AR_SREV_9280_20_OR_LATER(ah)) {
2029 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2030 * frames when constructing CCMP AAD. */
2031 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2032 0xc7ff);
2033 ah->sw_mgmt_crypto = false;
2034 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2035 /* Disable hardware crypto for management frames */
2036 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2037 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2038 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2039 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2040 ah->sw_mgmt_crypto = true;
2041 } else
2042 ah->sw_mgmt_crypto = true;
2043
f078f209
LR		 2044 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2045 ath9k_hw_set_delta_slope(ah, chan);
2046
ae478cf6 2047 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 2048 ah->eep_ops->set_board_values(ah, chan);
a7765828 2049
1510718d
LR		 2050 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2051 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 2052 | macStaId1
2053 | AR_STA_ID1_RTS_USE_DEF
2660b81a 2054 | (ah->config.
60b67f51 2055 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 2056 | ah->sta_id1_defaults);
2057 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2058
13b81559 2059 ath_hw_setbssidmask(common);
f078f209
LR		 2060
2061 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2062
3453ad88 2063 ath9k_hw_write_associd(ah);
f078f209
LR		 2064
2065 REG_WRITE(ah, AR_ISR, ~0);
2066
2067 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2068
e68a060b 2069 r = ah->ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 2070 if (r)
2071 return r;
f078f209
LR		 2072
2073 for (i = 0; i < AR_NUM_DCU; i++)
2074 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2075
2660b81a
S		 2076 ah->intr_txqs = 0;
2077 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 2078 ath9k_hw_resettxqueue(ah, i);
2079
2660b81a 2080 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 2081 ath9k_hw_init_qos(ah);
2082
2660b81a 2083 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 2084 ath9k_enable_rfkill(ah);
3b319aae 2085
f078f209
LR		 2086 ath9k_hw_init_user_settings(ah);
2087
326bebbc 2088 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2089 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2090 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2091 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2092 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2093 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2094 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2095
2096 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2097 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2098
2099 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2100 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2101 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2102 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2103 }
326bebbc 2104 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2105 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2106 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2107 }
2108
f078f209
LR		 2109 REG_WRITE(ah, AR_STA_ID1,
2110 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2111
2112 ath9k_hw_set_dma(ah);
2113
2114 REG_WRITE(ah, AR_OBS, 8);
2115
0ef1f168 2116 if (ah->config.intr_mitigation) {
f078f209
LR		 2117 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2118 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2119 }
2120
2121 ath9k_hw_init_bb(ah, chan);
2122
ae8d2858 2123 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2124 return -EIO;
f078f209 2125
2660b81a 2126 rx_chainmask = ah->rxchainmask;
f078f209
LR		 2127 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2128 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2129 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2130 }
2131
2132 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2133
d7e7d229
LR		 2134 /*
2135 * For big endian systems turn on swapping for descriptors
2136 */
f078f209
LR		 2137 if (AR_SREV_9100(ah)) {
2138 u32 mask;
2139 mask = REG_READ(ah, AR_CFG);
2140 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 2141 ath_print(common, ATH_DBG_RESET,
04bd4638 2142 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2143 } else {
2144 mask =
2145 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2146 REG_WRITE(ah, AR_CFG, mask);
c46917bb 2147 ath_print(common, ATH_DBG_RESET,
04bd4638 2148 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2149 }
2150 } else {
d7e7d229
LR		 2151 /* Configure AR9271 target WLAN */
2152 if (AR_SREV_9271(ah))
2153 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 2154#ifdef __BIG_ENDIAN
d7e7d229
LR		 2155 else
2156 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 2157#endif
2158 }
2159
766ec4a9 2160 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 2161 ath9k_hw_btcoex_enable(ah);
2162
ae8d2858 2163 return 0;
f078f209 2164}
7322fd19 2165EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2166
f1dc5600
S		 2167/************************/
2168/* Key Cache Management */
2169/************************/
f078f209 2170
cbe61d8a 2171bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 2172{
f1dc5600 2173 u32 keyType;
f078f209 2174
2660b81a 2175 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 2176 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2177 "keychache entry %u out of range\n", entry);
f078f209
LR		 2178 return false;
2179 }
2180
f1dc5600 2181 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2182
f1dc5600
S		 2183 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2184 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2185 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2186 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2187 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2188 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2189 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2190 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2191
f1dc5600
S		 2192 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2193 u16 micentry = entry + 64;
f078f209 2194
f1dc5600
S		 2195 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2196 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2197 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2198 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2199
f078f209
LR		 2200 }
2201
f078f209
LR		 2202 return true;
2203}
7322fd19 2204EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 2205
cbe61d8a 2206bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 2207{
f1dc5600 2208 u32 macHi, macLo;
f078f209 2209
2660b81a 2210 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 2211 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2212 "keychache entry %u out of range\n", entry);
f1dc5600 2213 return false;
f078f209
LR		 2214 }
2215
f1dc5600
S		 2216 if (mac != NULL) {
2217 macHi = (mac[5] << 8) | mac[4];
2218 macLo = (mac[3] << 24) |
2219 (mac[2] << 16) |
2220 (mac[1] << 8) |
2221 mac[0];
2222 macLo >>= 1;
2223 macLo |= (macHi & 1) << 31;
2224 macHi >>= 1;
f078f209 2225 } else {
f1dc5600 2226 macLo = macHi = 0;
f078f209 2227 }
f1dc5600
S		 2228 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2229 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2230
f1dc5600 2231 return true;
f078f209 2232}
7322fd19 2233EXPORT_SYMBOL(ath9k_hw_keysetmac);
f078f209 2234
cbe61d8a 2235bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 2236 const struct ath9k_keyval *k,
e0caf9ea 2237 const u8 *mac)
f078f209 2238{
2660b81a 2239 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2240 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 2241 u32 key0, key1, key2, key3, key4;
2242 u32 keyType;
f078f209 2243
f1dc5600 2244 if (entry >= pCap->keycache_size) {
c46917bb
LR		 2245 ath_print(common, ATH_DBG_FATAL,
2246 "keycache entry %u out of range\n", entry);
f1dc5600 2247 return false;
f078f209
LR		 2248 }
2249
f1dc5600
S		 2250 switch (k->kv_type) {
2251 case ATH9K_CIPHER_AES_OCB:
2252 keyType = AR_KEYTABLE_TYPE_AES;
2253 break;
2254 case ATH9K_CIPHER_AES_CCM:
2255 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 2256 ath_print(common, ATH_DBG_ANY,
2257 "AES-CCM not supported by mac rev 0x%x\n",
2258 ah->hw_version.macRev);
f1dc5600
S		 2259 return false;
2260 }
2261 keyType = AR_KEYTABLE_TYPE_CCM;
2262 break;
2263 case ATH9K_CIPHER_TKIP:
2264 keyType = AR_KEYTABLE_TYPE_TKIP;
2265 if (ATH9K_IS_MIC_ENABLED(ah)
2266 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 2267 ath_print(common, ATH_DBG_ANY,
2268 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2269 return false;
2270 }
2271 break;
2272 case ATH9K_CIPHER_WEP:
e31a16d6 2273 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 2274 ath_print(common, ATH_DBG_ANY,
2275 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2276 return false;
2277 }
e31a16d6 2278 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 2279 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 2280 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 2281 keyType = AR_KEYTABLE_TYPE_104;
2282 else
2283 keyType = AR_KEYTABLE_TYPE_128;
2284 break;
2285 case ATH9K_CIPHER_CLR:
2286 keyType = AR_KEYTABLE_TYPE_CLR;
2287 break;
2288 default:
c46917bb
LR		 2289 ath_print(common, ATH_DBG_FATAL,
2290 "cipher %u not supported\n", k->kv_type);
f1dc5600 2291 return false;
f078f209
LR		 2292 }
2293
e0caf9ea
JM		 2294 key0 = get_unaligned_le32(k->kv_val + 0);
2295 key1 = get_unaligned_le16(k->kv_val + 4);
2296 key2 = get_unaligned_le32(k->kv_val + 6);
2297 key3 = get_unaligned_le16(k->kv_val + 10);
2298 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 2299 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 2300 key4 &= 0xff;
f078f209 2301
672903b3
JM		 2302 /*
2303 * Note: Key cache registers access special memory area that requires
2304 * two 32-bit writes to actually update the values in the internal
2305 * memory. Consequently, the exact order and pairs used here must be
2306 * maintained.
2307 */
2308
f1dc5600
S		 2309 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2310 u16 micentry = entry + 64;
f078f209 2311
672903b3
JM		 2312 /*
2313 * Write inverted key[47:0] first to avoid Michael MIC errors
2314 * on frames that could be sent or received at the same time.
2315 * The correct key will be written in the end once everything
2316 * else is ready.
2317 */
f1dc5600
S		 2318 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2319 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 2320
2321 /* Write key[95:48] */
f1dc5600
S		 2322 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2323 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2324
2325 /* Write key[127:96] and key type */
f1dc5600
S		 2326 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2327 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 2328
2329 /* Write MAC address for the entry */
f1dc5600 2330 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2331
2660b81a 2332 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 2333 /*
2334 * TKIP uses two key cache entries:
2335 * Michael MIC TX/RX keys in the same key cache entry
2336 * (idx = main index + 64):
2337 * key0 [31:0] = RX key [31:0]
2338 * key1 [15:0] = TX key [31:16]
2339 * key1 [31:16] = reserved
2340 * key2 [31:0] = RX key [63:32]
2341 * key3 [15:0] = TX key [15:0]
2342 * key3 [31:16] = reserved
2343 * key4 [31:0] = TX key [63:32]
2344 */
f1dc5600 2345 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2346
f1dc5600
S		 2347 mic0 = get_unaligned_le32(k->kv_mic + 0);
2348 mic2 = get_unaligned_le32(k->kv_mic + 4);
2349 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2350 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2351 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 2352
2353 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 2354 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2355 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 2356
2357 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 2358 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2359 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 2360
2361 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2362 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2363 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2364 AR_KEYTABLE_TYPE_CLR);
f078f209 2365
f1dc5600 2366 } else {
672903b3
JM		 2367 /*
2368 * TKIP uses four key cache entries (two for group
2369 * keys):
2370 * Michael MIC TX/RX keys are in different key cache
2371 * entries (idx = main index + 64 for TX and
2372 * main index + 32 + 96 for RX):
2373 * key0 [31:0] = TX/RX MIC key [31:0]
2374 * key1 [31:0] = reserved
2375 * key2 [31:0] = TX/RX MIC key [63:32]
2376 * key3 [31:0] = reserved
2377 * key4 [31:0] = reserved
2378 *
2379 * Upper layer code will call this function separately
2380 * for TX and RX keys when these registers offsets are
2381 * used.
2382 */
f1dc5600 2383 u32 mic0, mic2;
f078f209 2384
f1dc5600
S		 2385 mic0 = get_unaligned_le32(k->kv_mic + 0);
2386 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 2387
2388 /* Write MIC key[31:0] */
f1dc5600
S		 2389 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2390 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 2391
2392 /* Write MIC key[63:32] */
f1dc5600
S		 2393 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2394 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 2395
2396 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2397 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2398 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2399 AR_KEYTABLE_TYPE_CLR);
2400 }
672903b3
JM		 2401
2402 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 2403 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2404 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 2405
2406 /*
2407 * Write the correct (un-inverted) key[47:0] last to enable
2408 * TKIP now that all other registers are set with correct
2409 * values.
2410 */
f1dc5600
S		 2411 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2412 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2413 } else {
672903b3 2414 /* Write key[47:0] */
f1dc5600
S		 2415 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2416 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 2417
2418 /* Write key[95:48] */
f1dc5600
S		 2419 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2420 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2421
2422 /* Write key[127:96] and key type */
f1dc5600
S		 2423 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2424 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2425
672903b3 2426 /* Write MAC address for the entry */
f1dc5600
S		 2427 (void) ath9k_hw_keysetmac(ah, entry, mac);
2428 }
f078f209 2429
f078f209
LR		 2430 return true;
2431}
7322fd19 2432EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 2433
cbe61d8a 2434bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 2435{
2660b81a 2436 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 2437 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2438 if (val & AR_KEYTABLE_VALID)
2439 return true;
2440 }
2441 return false;
f078f209 2442}
7322fd19 2443EXPORT_SYMBOL(ath9k_hw_keyisvalid);
f078f209 2444
f1dc5600
S		 2445/******************************/
2446/* Power Management (Chipset) */
2447/******************************/
2448
cbe61d8a 2449static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2450{
f1dc5600
S		 2451 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2452 if (setChip) {
2453 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2454 AR_RTC_FORCE_WAKE_EN);
2455 if (!AR_SREV_9100(ah))
2456 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2457
4921be80
S		 2458 if(!AR_SREV_5416(ah))
2459 REG_CLR_BIT(ah, (AR_RTC_RESET),
2460 AR_RTC_RESET_EN);
f1dc5600 2461 }
f078f209
LR		 2462}
2463
cbe61d8a 2464static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2465{
f1dc5600
S		 2466 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2467 if (setChip) {
2660b81a 2468 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2469
f1dc5600
S		 2470 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2471 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2472 AR_RTC_FORCE_WAKE_ON_INT);
2473 } else {
2474 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2475 AR_RTC_FORCE_WAKE_EN);
f078f209 2476 }
f078f209 2477 }
f078f209
LR		 2478}
2479
cbe61d8a 2480static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2481{
f1dc5600
S		 2482 u32 val;
2483 int i;
f078f209 2484
f1dc5600
S		 2485 if (setChip) {
2486 if ((REG_READ(ah, AR_RTC_STATUS) &
2487 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2488 if (ath9k_hw_set_reset_reg(ah,
2489 ATH9K_RESET_POWER_ON) != true) {
2490 return false;
2491 }
63a75b91 2492 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 2493 }
2494 if (AR_SREV_9100(ah))
2495 REG_SET_BIT(ah, AR_RTC_RESET,
2496 AR_RTC_RESET_EN);
f078f209 2497
f1dc5600
S		 2498 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2499 AR_RTC_FORCE_WAKE_EN);
2500 udelay(50);
f078f209 2501
f1dc5600
S		 2502 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2503 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2504 if (val == AR_RTC_STATUS_ON)
2505 break;
2506 udelay(50);
2507 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2508 AR_RTC_FORCE_WAKE_EN);
f078f209 2509 }
f1dc5600 2510 if (i == 0) {
c46917bb
LR		 2511 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2512 "Failed to wakeup in %uus\n",
2513 POWER_UP_TIME / 20);
f1dc5600 2514 return false;
f078f209 2515 }
f078f209
LR		 2516 }
2517
f1dc5600 2518 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2519
f1dc5600 2520 return true;
f078f209
LR		 2521}
2522
9ecdef4b 2523bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2524{
c46917bb 2525 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 2526 int status = true, setChip = true;
f1dc5600
S		 2527 static const char *modes[] = {
2528 "AWAKE",
2529 "FULL-SLEEP",
2530 "NETWORK SLEEP",
2531 "UNDEFINED"
2532 };
f1dc5600 2533
cbdec975
GJ		 2534 if (ah->power_mode == mode)
2535 return status;
2536
c46917bb
LR		 2537 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2538 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2539
2540 switch (mode) {
2541 case ATH9K_PM_AWAKE:
2542 status = ath9k_hw_set_power_awake(ah, setChip);
2543 break;
2544 case ATH9K_PM_FULL_SLEEP:
2545 ath9k_set_power_sleep(ah, setChip);
2660b81a 2546 ah->chip_fullsleep = true;
f1dc5600
S		 2547 break;
2548 case ATH9K_PM_NETWORK_SLEEP:
2549 ath9k_set_power_network_sleep(ah, setChip);
2550 break;
f078f209 2551 default:
c46917bb
LR		 2552 ath_print(common, ATH_DBG_FATAL,
2553 "Unknown power mode %u\n", mode);
f078f209
LR		 2554 return false;
2555 }
2660b81a 2556 ah->power_mode = mode;
f1dc5600
S		 2557
2558 return status;
f078f209 2559}
7322fd19 2560EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2561
24c1a280
LR		 2562/*
2563 * Helper for ASPM support.
2564 *
2565 * Disable PLL when in L0s as well as receiver clock when in L1.
2566 * This power saving option must be enabled through the SerDes.
2567 *
2568 * Programming the SerDes must go through the same 288 bit serial shift
2569 * register as the other analog registers. Hence the 9 writes.
2570 */
93b1b37f 2571void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
f078f209 2572{
f1dc5600 2573 u8 i;
93b1b37f 2574 u32 val;
f078f209 2575
2660b81a 2576 if (ah->is_pciexpress != true)
f1dc5600 2577 return;
f078f209 2578
24c1a280 2579 /* Do not touch SerDes registers */
2660b81a 2580 if (ah->config.pcie_powersave_enable == 2)
f1dc5600
S		 2581 return;
2582
24c1a280 2583 /* Nothing to do on restore for 11N */
93b1b37f
VN		 2584 if (!restore) {
2585 if (AR_SREV_9280_20_OR_LATER(ah)) {
2586 /*
2587 * AR9280 2.0 or later chips use SerDes values from the
2588 * initvals.h initialized depending on chipset during
2589 * ath9k_hw_init()
2590 */
2591 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2592 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2593 INI_RA(&ah->iniPcieSerdes, i, 1));
2594 }
2595 } else if (AR_SREV_9280(ah) &&
2596 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2597 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2598 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2599
2600 /* RX shut off when elecidle is asserted */
2601 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2602 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2603 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2604
2605 /* Shut off CLKREQ active in L1 */
2606 if (ah->config.pcie_clock_req)
2607 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2608 else
2609 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
f1dc5600 2610
93b1b37f
VN		 2611 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2612 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2613 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
f1dc5600 2614
93b1b37f
VN		 2615 /* Load the new settings */
2616 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f1dc5600 2617
93b1b37f
VN		 2618 } else {
2619 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2620 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
f1dc5600 2621
93b1b37f
VN		 2622 /* RX shut off when elecidle is asserted */
2623 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2624 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2625 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
f1dc5600 2626
93b1b37f
VN		 2627 /*
2628 * Ignore ah->ah_config.pcie_clock_req setting for
2629 * pre-AR9280 11n
2630 */
2631 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
24c1a280 2632
93b1b37f
VN		 2633 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2634 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2635 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
24c1a280 2636
93b1b37f
VN		 2637 /* Load the new settings */
2638 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2639 }
24c1a280 2640
93b1b37f 2641 udelay(1000);
24c1a280 2642
93b1b37f
VN		 2643 /* set bit 19 to allow forcing of pcie core into L1 state */
2644 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
f078f209 2645
93b1b37f
VN		 2646 /* Several PCIe massages to ensure proper behaviour */
2647 if (ah->config.pcie_waen) {
2648 val = ah->config.pcie_waen;
2649 if (!power_off)
2650 val &= (~AR_WA_D3_L1_DISABLE);
2651 } else {
2652 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2653 AR_SREV_9287(ah)) {
2654 val = AR9285_WA_DEFAULT;
2655 if (!power_off)
2656 val &= (~AR_WA_D3_L1_DISABLE);
2657 } else if (AR_SREV_9280(ah)) {
2658 /*
2659 * On AR9280 chips bit 22 of 0x4004 needs to be
2660 * set otherwise card may disappear.
2661 */
2662 val = AR9280_WA_DEFAULT;
2663 if (!power_off)
2664 val &= (~AR_WA_D3_L1_DISABLE);
2665 } else
2666 val = AR_WA_DEFAULT;
2667 }
6d08b9b9 2668
93b1b37f
VN		 2669 REG_WRITE(ah, AR_WA, val);
2670 }
f1dc5600 2671
93b1b37f 2672 if (power_off) {
24c1a280 2673 /*
93b1b37f
VN		 2674 * Set PCIe workaround bits
2675 * bit 14 in WA register (disable L1) should only
2676 * be set when device enters D3 and be cleared
2677 * when device comes back to D0.
24c1a280 2678 */
93b1b37f
VN		 2679 if (ah->config.pcie_waen) {
2680 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2681 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2682 } else {
2683 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2684 AR_SREV_9287(ah)) &&
2685 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2686 (AR_SREV_9280(ah) &&
2687 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2688 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2689 }
2690 }
f1dc5600 2691 }
f078f209 2692}
7322fd19 2693EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
f078f209 2694
f1dc5600
S		 2695/**********************/
2696/* Interrupt Handling */
2697/**********************/
2698
cbe61d8a 2699bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 2700{
2701 u32 host_isr;
2702
2703 if (AR_SREV_9100(ah))
2704 return true;
2705
2706 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2707 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2708 return true;
2709
2710 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2711 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2712 && (host_isr != AR_INTR_SPURIOUS))
2713 return true;
2714
2715 return false;
2716}
7322fd19 2717EXPORT_SYMBOL(ath9k_hw_intrpend);
f078f209 2718
cbe61d8a 2719bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 2720{
2721 u32 isr = 0;
2722 u32 mask2 = 0;
2660b81a 2723 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 2724 u32 sync_cause = 0;
2725 bool fatal_int = false;
c46917bb 2726 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 2727
2728 if (!AR_SREV_9100(ah)) {
2729 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2730 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2731 == AR_RTC_STATUS_ON) {
2732 isr = REG_READ(ah, AR_ISR);
2733 }
2734 }
2735
f1dc5600
S		 2736 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2737 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 2738
2739 *masked = 0;
2740
2741 if (!isr && !sync_cause)
2742 return false;
2743 } else {
2744 *masked = 0;
2745 isr = REG_READ(ah, AR_ISR);
2746 }
2747
2748 if (isr) {
f078f209
LR		 2749 if (isr & AR_ISR_BCNMISC) {
2750 u32 isr2;
2751 isr2 = REG_READ(ah, AR_ISR_S2);
2752 if (isr2 & AR_ISR_S2_TIM)
2753 mask2 |= ATH9K_INT_TIM;
2754 if (isr2 & AR_ISR_S2_DTIM)
2755 mask2 |= ATH9K_INT_DTIM;
2756 if (isr2 & AR_ISR_S2_DTIMSYNC)
2757 mask2 |= ATH9K_INT_DTIMSYNC;
2758 if (isr2 & (AR_ISR_S2_CABEND))
2759 mask2 |= ATH9K_INT_CABEND;
2760 if (isr2 & AR_ISR_S2_GTT)
2761 mask2 |= ATH9K_INT_GTT;
2762 if (isr2 & AR_ISR_S2_CST)
2763 mask2 |= ATH9K_INT_CST;
4af9cf4f
S		 2764 if (isr2 & AR_ISR_S2_TSFOOR)
2765 mask2 |= ATH9K_INT_TSFOOR;
f078f209
LR		 2766 }
2767
2768 isr = REG_READ(ah, AR_ISR_RAC);
2769 if (isr == 0xffffffff) {
2770 *masked = 0;
2771 return false;
2772 }
2773
2774 *masked = isr & ATH9K_INT_COMMON;
2775
0ef1f168 2776 if (ah->config.intr_mitigation) {
f078f209
LR		 2777 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2778 *masked |= ATH9K_INT_RX;
2779 }
2780
2781 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2782 *masked |= ATH9K_INT_RX;
2783 if (isr &
2784 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2785 AR_ISR_TXEOL)) {
2786 u32 s0_s, s1_s;
2787
2788 *masked |= ATH9K_INT_TX;
2789
2790 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 2791 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2792 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 2793
2794 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 2795 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2796 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 2797 }
2798
2799 if (isr & AR_ISR_RXORN) {
c46917bb
LR		 2800 ath_print(common, ATH_DBG_INTERRUPT,
2801 "receive FIFO overrun interrupt\n");
f078f209
LR		 2802 }
2803
2804 if (!AR_SREV_9100(ah)) {
60b67f51 2805 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2806 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2807 if (isr5 & AR_ISR_S5_TIM_TIMER)
2808 *masked |= ATH9K_INT_TIM_TIMER;
2809 }
2810 }
2811
2812 *masked |= mask2;
2813 }
f1dc5600 2814
f078f209
LR		 2815 if (AR_SREV_9100(ah))
2816 return true;
f1dc5600 2817
ff155a45
VT		 2818 if (isr & AR_ISR_GENTMR) {
2819 u32 s5_s;
2820
2821 s5_s = REG_READ(ah, AR_ISR_S5_S);
2822 if (isr & AR_ISR_GENTMR) {
2823 ah->intr_gen_timer_trigger =
2824 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2825
2826 ah->intr_gen_timer_thresh =
2827 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2828
2829 if (ah->intr_gen_timer_trigger)
2830 *masked |= ATH9K_INT_GENTIMER;
2831
2832 }
2833 }
2834
f078f209
LR		 2835 if (sync_cause) {
2836 fatal_int =
2837 (sync_cause &
2838 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2839 ? true : false;
2840
2841 if (fatal_int) {
2842 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
c46917bb
LR		 2843 ath_print(common, ATH_DBG_ANY,
2844 "received PCI FATAL interrupt\n");
f078f209
LR		 2845 }
2846 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
c46917bb
LR		 2847 ath_print(common, ATH_DBG_ANY,
2848 "received PCI PERR interrupt\n");
f078f209 2849 }
a89bff9a 2850 *masked |= ATH9K_INT_FATAL;
f078f209
LR		 2851 }
2852 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
c46917bb
LR		 2853 ath_print(common, ATH_DBG_INTERRUPT,
2854 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 2855 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2856 REG_WRITE(ah, AR_RC, 0);
2857 *masked |= ATH9K_INT_FATAL;
2858 }
2859 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
c46917bb
LR		 2860 ath_print(common, ATH_DBG_INTERRUPT,
2861 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 2862 }
2863
2864 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2865 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2866 }
f1dc5600 2867
f078f209
LR		 2868 return true;
2869}
7322fd19 2870EXPORT_SYMBOL(ath9k_hw_getisr);
f078f209 2871
cbe61d8a 2872enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 2873{
2660b81a 2874 u32 omask = ah->mask_reg;
f078f209 2875 u32 mask, mask2;
2660b81a 2876 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2877 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2878
c46917bb 2879 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 2880
2881 if (omask & ATH9K_INT_GLOBAL) {
c46917bb 2882 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 2883 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2884 (void) REG_READ(ah, AR_IER);
2885 if (!AR_SREV_9100(ah)) {
2886 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2887 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2888
2889 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2890 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2891 }
2892 }
2893
2894 mask = ints & ATH9K_INT_COMMON;
2895 mask2 = 0;
2896
2897 if (ints & ATH9K_INT_TX) {
2660b81a 2898 if (ah->txok_interrupt_mask)
f078f209 2899 mask |= AR_IMR_TXOK;
2660b81a 2900 if (ah->txdesc_interrupt_mask)
f078f209 2901 mask |= AR_IMR_TXDESC;
2660b81a 2902 if (ah->txerr_interrupt_mask)
f078f209 2903 mask |= AR_IMR_TXERR;
2660b81a 2904 if (ah->txeol_interrupt_mask)
f078f209
LR		 2905 mask |= AR_IMR_TXEOL;
2906 }
2907 if (ints & ATH9K_INT_RX) {
2908 mask |= AR_IMR_RXERR;
0ef1f168 2909 if (ah->config.intr_mitigation)
f078f209
LR		 2910 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2911 else
2912 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 2913 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 2914 mask |= AR_IMR_GENTMR;
2915 }
2916
2917 if (ints & (ATH9K_INT_BMISC)) {
2918 mask |= AR_IMR_BCNMISC;
2919 if (ints & ATH9K_INT_TIM)
2920 mask2 |= AR_IMR_S2_TIM;
2921 if (ints & ATH9K_INT_DTIM)
2922 mask2 |= AR_IMR_S2_DTIM;
2923 if (ints & ATH9K_INT_DTIMSYNC)
2924 mask2 |= AR_IMR_S2_DTIMSYNC;
2925 if (ints & ATH9K_INT_CABEND)
4af9cf4f
S		 2926 mask2 |= AR_IMR_S2_CABEND;
2927 if (ints & ATH9K_INT_TSFOOR)
2928 mask2 |= AR_IMR_S2_TSFOOR;
f078f209
LR		 2929 }
2930
2931 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2932 mask |= AR_IMR_BCNMISC;
2933 if (ints & ATH9K_INT_GTT)
2934 mask2 |= AR_IMR_S2_GTT;
2935 if (ints & ATH9K_INT_CST)
2936 mask2 |= AR_IMR_S2_CST;
2937 }
2938
c46917bb 2939 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 2940 REG_WRITE(ah, AR_IMR, mask);
2941 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2942 AR_IMR_S2_DTIM |
2943 AR_IMR_S2_DTIMSYNC |
2944 AR_IMR_S2_CABEND |
2945 AR_IMR_S2_CABTO |
2946 AR_IMR_S2_TSFOOR |
2947 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2948 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2660b81a 2949 ah->mask_reg = ints;
f078f209 2950
60b67f51 2951 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2952 if (ints & ATH9K_INT_TIM_TIMER)
2953 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2954 else
2955 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2956 }
2957
2958 if (ints & ATH9K_INT_GLOBAL) {
c46917bb 2959 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 2960 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2961 if (!AR_SREV_9100(ah)) {
2962 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2963 AR_INTR_MAC_IRQ);
2964 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2965
2966
2967 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2968 AR_INTR_SYNC_DEFAULT);
2969 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2970 AR_INTR_SYNC_DEFAULT);
2971 }
c46917bb
LR		 2972 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2973 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
f078f209
LR		 2974 }
2975
2976 return omask;
2977}
7322fd19 2978EXPORT_SYMBOL(ath9k_hw_set_interrupts);
f078f209 2979
f1dc5600
S		 2980/*******************/
2981/* Beacon Handling */
2982/*******************/
2983
cbe61d8a 2984void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2985{
f078f209
LR		 2986 int flags = 0;
2987
2660b81a 2988 ah->beacon_interval = beacon_period;
f078f209 2989
2660b81a 2990 switch (ah->opmode) {
d97809db
CM		 2991 case NL80211_IFTYPE_STATION:
2992 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 2993 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2994 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2995 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2996 flags |= AR_TBTT_TIMER_EN;
2997 break;
d97809db 2998 case NL80211_IFTYPE_ADHOC:
9cb5412b 2999 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 3000 REG_SET_BIT(ah, AR_TXCFG,
3001 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3002 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3003 TU_TO_USEC(next_beacon +
2660b81a
S		 3004 (ah->atim_window ? ah->
3005 atim_window : 1)));
f078f209 3006 flags |= AR_NDP_TIMER_EN;
d97809db 3007 case NL80211_IFTYPE_AP:
f078f209
LR		 3008 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3009 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3010 TU_TO_USEC(next_beacon -
2660b81a 3011 ah->config.
60b67f51 3012 dma_beacon_response_time));
f078f209
LR		 3013 REG_WRITE(ah, AR_NEXT_SWBA,
3014 TU_TO_USEC(next_beacon -
2660b81a 3015 ah->config.
60b67f51 3016 sw_beacon_response_time));
f078f209
LR		 3017 flags |=
3018 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3019 break;
d97809db 3020 default:
c46917bb
LR		 3021 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3022 "%s: unsupported opmode: %d\n",
3023 __func__, ah->opmode);
d97809db
CM		 3024 return;
3025 break;
f078f209
LR		 3026 }
3027
3028 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3029 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3030 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3031 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3032
3033 beacon_period &= ~ATH9K_BEACON_ENA;
3034 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 3035 ath9k_hw_reset_tsf(ah);
3036 }
3037
3038 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3039}
7322fd19 3040EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 3041
cbe61d8a 3042void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 3043 const struct ath9k_beacon_state *bs)
f078f209
LR		 3044{
3045 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 3046 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 3047 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 3048
3049 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3050
3051 REG_WRITE(ah, AR_BEACON_PERIOD,
3052 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3053 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3054 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3055
3056 REG_RMW_FIELD(ah, AR_RSSI_THR,
3057 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3058
3059 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3060
3061 if (bs->bs_sleepduration > beaconintval)
3062 beaconintval = bs->bs_sleepduration;
3063
3064 dtimperiod = bs->bs_dtimperiod;
3065 if (bs->bs_sleepduration > dtimperiod)
3066 dtimperiod = bs->bs_sleepduration;
3067
3068 if (beaconintval == dtimperiod)
3069 nextTbtt = bs->bs_nextdtim;
3070 else
3071 nextTbtt = bs->bs_nexttbtt;
3072
c46917bb
LR		 3073 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3074 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3075 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3076 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3077
f1dc5600
S		 3078 REG_WRITE(ah, AR_NEXT_DTIM,
3079 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3080 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3081
f1dc5600
S		 3082 REG_WRITE(ah, AR_SLEEP1,
3083 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3084 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3085
f1dc5600
S		 3086 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3087 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3088 else
3089 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3090
f1dc5600
S		 3091 REG_WRITE(ah, AR_SLEEP2,
3092 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3093
f1dc5600
S		 3094 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3095 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3096
f1dc5600
S		 3097 REG_SET_BIT(ah, AR_TIMER_MODE,
3098 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3099 AR_DTIM_TIMER_EN);
f078f209 3100
4af9cf4f
S		 3101 /* TSF Out of Range Threshold */
3102 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 3103}
7322fd19 3104EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 3105
f1dc5600
S		 3106/*******************/
3107/* HW Capabilities */
3108/*******************/
3109
eef7a574 3110void ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 3111{
2660b81a 3112 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 3113 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 3114 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 3115 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 3116
f1dc5600 3117 u16 capField = 0, eeval;
f078f209 3118
f74df6fb 3119 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 3120 regulatory->current_rd = eeval;
f078f209 3121
f74df6fb 3122 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 3123 if (AR_SREV_9285_10_OR_LATER(ah))
3124 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 3125 regulatory->current_rd_ext = eeval;
f078f209 3126
f74df6fb 3127 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 3128
2660b81a 3129 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 3130 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 3131 if (regulatory->current_rd == 0x64 ||
3132 regulatory->current_rd == 0x65)
3133 regulatory->current_rd += 5;
3134 else if (regulatory->current_rd == 0x41)
3135 regulatory->current_rd = 0x43;
c46917bb
LR		 3136 ath_print(common, ATH_DBG_REGULATORY,
3137 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 3138 }
f078f209 3139
f74df6fb 3140 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
f1dc5600 3141 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3142
f1dc5600
S		 3143 if (eeval & AR5416_OPFLAGS_11A) {
3144 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 3145 if (ah->config.ht_enable) {
f1dc5600
S		 3146 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3147 set_bit(ATH9K_MODE_11NA_HT20,
3148 pCap->wireless_modes);
3149 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3150 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3151 pCap->wireless_modes);
3152 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3153 pCap->wireless_modes);
3154 }
f078f209 3155 }
f078f209
LR		 3156 }
3157
f1dc5600 3158 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 3159 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 3160 if (ah->config.ht_enable) {
f1dc5600
S		 3161 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3162 set_bit(ATH9K_MODE_11NG_HT20,
3163 pCap->wireless_modes);
3164 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3165 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3166 pCap->wireless_modes);
3167 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3168 pCap->wireless_modes);
3169 }
3170 }
f078f209 3171 }
f1dc5600 3172
f74df6fb 3173 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 3174 /*
3175 * For AR9271 we will temporarilly uses the rx chainmax as read from
3176 * the EEPROM.
3177 */
8147f5de 3178 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 3179 !(eeval & AR5416_OPFLAGS_11A) &&
3180 !(AR_SREV_9271(ah)))
3181 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 3182 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3183 else
d7e7d229 3184 /* Use rx_chainmask from EEPROM. */
8147f5de 3185 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 3186
d535a42a 3187 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 3188 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3189
f1dc5600
S		 3190 pCap->low_2ghz_chan = 2312;
3191 pCap->high_2ghz_chan = 2732;
f078f209 3192
f1dc5600
S		 3193 pCap->low_5ghz_chan = 4920;
3194 pCap->high_5ghz_chan = 6100;
f078f209 3195
f1dc5600
S		 3196 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3197 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3198 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3199
f1dc5600
S		 3200 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3201 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3202 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3203
2660b81a 3204 if (ah->config.ht_enable)
f1dc5600
S		 3205 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3206 else
3207 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3208
f1dc5600
S		 3209 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3210 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3211 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3212 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3213
f1dc5600
S		 3214 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3215 pCap->total_queues =
3216 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3217 else
3218 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3219
f1dc5600
S		 3220 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3221 pCap->keycache_size =
3222 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3223 else
3224 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3225
f1dc5600 3226 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f1dc5600 3227 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3228
cb33c412
SB		 3229 if (AR_SREV_9285_10_OR_LATER(ah))
3230 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3231 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3232 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3233 else
3234 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3235
f1dc5600
S		 3236 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3237 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3238 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3239 } else {
3240 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3241 }
3242
f1dc5600
S		 3243 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3244
e97275cb 3245#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 3246 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3247 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3248 ah->rfkill_gpio =
3249 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3250 ah->rfkill_polarity =
3251 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 3252
3253 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3254 }
f1dc5600 3255#endif
f078f209 3256
a3ca95fb 3257 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3258
e7594072 3259 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3260 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3261 else
3262 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3263
608b88cb 3264 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 3265 pCap->reg_cap =
3266 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3267 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3268 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3269 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3270 } else {
f1dc5600
S		 3271 pCap->reg_cap =
3272 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3273 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3274 }
f078f209 3275
ebb90cfc
SB		 3276 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3277 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3278 AR_SREV_5416(ah))
3279 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 3280
3281 pCap->num_antcfg_5ghz =
f74df6fb 3282 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3283 pCap->num_antcfg_2ghz =
f74df6fb 3284 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3285
fe12946e 3286 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 3287 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 3288 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3289 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 3290
8c8f9ba7 3291 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 3292 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3293 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 3294 } else {
766ec4a9 3295 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 3296 }
22f25d0d 3297 } else {
766ec4a9 3298 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 3299 }
f078f209
LR		 3300}
3301
cbe61d8a 3302bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3303 u32 capability, u32 *result)
f078f209 3304{
608b88cb 3305 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 3306 switch (type) {
3307 case ATH9K_CAP_CIPHER:
3308 switch (capability) {
3309 case ATH9K_CIPHER_AES_CCM:
3310 case ATH9K_CIPHER_AES_OCB:
3311 case ATH9K_CIPHER_TKIP:
3312 case ATH9K_CIPHER_WEP:
3313 case ATH9K_CIPHER_MIC:
3314 case ATH9K_CIPHER_CLR:
3315 return true;
3316 default:
3317 return false;
3318 }
3319 case ATH9K_CAP_TKIP_MIC:
3320 switch (capability) {
3321 case 0:
3322 return true;
3323 case 1:
2660b81a 3324 return (ah->sta_id1_defaults &
f1dc5600
S		 3325 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3326 false;
3327 }
3328 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 3329 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 3330 false : true;
f1dc5600
S		 3331 case ATH9K_CAP_DIVERSITY:
3332 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3333 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3334 true : false;
f1dc5600
S		 3335 case ATH9K_CAP_MCAST_KEYSRCH:
3336 switch (capability) {
3337 case 0:
3338 return true;
3339 case 1:
3340 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3341 return false;
3342 } else {
2660b81a 3343 return (ah->sta_id1_defaults &
f1dc5600
S		 3344 AR_STA_ID1_MCAST_KSRCH) ? true :
3345 false;
3346 }
3347 }
3348 return false;
f1dc5600
S		 3349 case ATH9K_CAP_TXPOW:
3350 switch (capability) {
3351 case 0:
3352 return 0;
3353 case 1:
608b88cb 3354 *result = regulatory->power_limit;
f1dc5600
S		 3355 return 0;
3356 case 2:
608b88cb 3357 *result = regulatory->max_power_level;
f1dc5600
S		 3358 return 0;
3359 case 3:
608b88cb 3360 *result = regulatory->tp_scale;
f1dc5600
S		 3361 return 0;
3362 }
3363 return false;
8bd1d07f
SB		 3364 case ATH9K_CAP_DS:
3365 return (AR_SREV_9280_20_OR_LATER(ah) &&
3366 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3367 ? false : true;
f1dc5600
S		 3368 default:
3369 return false;
f078f209 3370 }
f078f209 3371}
7322fd19 3372EXPORT_SYMBOL(ath9k_hw_getcapability);
f078f209 3373
cbe61d8a 3374bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3375 u32 capability, u32 setting, int *status)
f078f209 3376{
f1dc5600 3377 u32 v;
f078f209 3378
f1dc5600
S		 3379 switch (type) {
3380 case ATH9K_CAP_TKIP_MIC:
3381 if (setting)
2660b81a 3382 ah->sta_id1_defaults |=
f1dc5600
S		 3383 AR_STA_ID1_CRPT_MIC_ENABLE;
3384 else
2660b81a 3385 ah->sta_id1_defaults &=
f1dc5600
S		 3386 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3387 return true;
3388 case ATH9K_CAP_DIVERSITY:
3389 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3390 if (setting)
3391 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3392 else
3393 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3394 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3395 return true;
3396 case ATH9K_CAP_MCAST_KEYSRCH:
3397 if (setting)
2660b81a 3398 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3399 else
2660b81a 3400 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3401 return true;
f1dc5600
S		 3402 default:
3403 return false;
f078f209
LR		 3404 }
3405}
7322fd19 3406EXPORT_SYMBOL(ath9k_hw_setcapability);
f078f209 3407
f1dc5600
S		 3408/****************************/
3409/* GPIO / RFKILL / Antennae */
3410/****************************/
f078f209 3411
cbe61d8a 3412static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 3413 u32 gpio, u32 type)
3414{
3415 int addr;
3416 u32 gpio_shift, tmp;
f078f209 3417
f1dc5600
S		 3418 if (gpio > 11)
3419 addr = AR_GPIO_OUTPUT_MUX3;
3420 else if (gpio > 5)
3421 addr = AR_GPIO_OUTPUT_MUX2;
3422 else
3423 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3424
f1dc5600 3425 gpio_shift = (gpio % 6) * 5;
f078f209 3426
f1dc5600
S		 3427 if (AR_SREV_9280_20_OR_LATER(ah)
3428 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3429 REG_RMW(ah, addr, (type << gpio_shift),
3430 (0x1f << gpio_shift));
f078f209 3431 } else {
f1dc5600
S		 3432 tmp = REG_READ(ah, addr);
3433 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3434 tmp &= ~(0x1f << gpio_shift);
3435 tmp |= (type << gpio_shift);
3436 REG_WRITE(ah, addr, tmp);
f078f209 3437 }
f078f209
LR		 3438}
3439
cbe61d8a 3440void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 3441{
f1dc5600 3442 u32 gpio_shift;
f078f209 3443
9680e8a3 3444 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 3445
f1dc5600 3446 gpio_shift = gpio << 1;
f078f209 3447
f1dc5600
S		 3448 REG_RMW(ah,
3449 AR_GPIO_OE_OUT,
3450 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3451 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 3452}
7322fd19 3453EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 3454
cbe61d8a 3455u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 3456{
cb33c412
SB		 3457#define MS_REG_READ(x, y) \
3458 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3459
2660b81a 3460 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 3461 return 0xffffffff;
f078f209 3462
ac88b6ec
VN		 3463 if (AR_SREV_9287_10_OR_LATER(ah))
3464 return MS_REG_READ(AR9287, gpio) != 0;
3465 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 3466 return MS_REG_READ(AR9285, gpio) != 0;
3467 else if (AR_SREV_9280_10_OR_LATER(ah))
3468 return MS_REG_READ(AR928X, gpio) != 0;
3469 else
3470 return MS_REG_READ(AR, gpio) != 0;
f078f209 3471}
7322fd19 3472EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 3473
cbe61d8a 3474void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 3475 u32 ah_signal_type)
f078f209 3476{
f1dc5600 3477 u32 gpio_shift;
f078f209 3478
f1dc5600 3479 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3480
f1dc5600 3481 gpio_shift = 2 * gpio;
f078f209 3482
f1dc5600
S		 3483 REG_RMW(ah,
3484 AR_GPIO_OE_OUT,
3485 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3486 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 3487}
7322fd19 3488EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 3489
cbe61d8a 3490void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 3491{
f1dc5600
S		 3492 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3493 AR_GPIO_BIT(gpio));
f078f209 3494}
7322fd19 3495EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 3496
cbe61d8a 3497u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 3498{
f1dc5600 3499 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 3500}
7322fd19 3501EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 3502
cbe61d8a 3503void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 3504{
f1dc5600 3505 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 3506}
7322fd19 3507EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 3508
f1dc5600
S		 3509/*********************/
3510/* General Operation */
3511/*********************/
3512
cbe61d8a 3513u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 3514{
f1dc5600
S		 3515 u32 bits = REG_READ(ah, AR_RX_FILTER);
3516 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3517
f1dc5600
S		 3518 if (phybits & AR_PHY_ERR_RADAR)
3519 bits |= ATH9K_RX_FILTER_PHYRADAR;
3520 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3521 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3522
f1dc5600 3523 return bits;
f078f209 3524}
7322fd19 3525EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 3526
cbe61d8a 3527void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 3528{
f1dc5600 3529 u32 phybits;
f078f209 3530
7ea310be
S		 3531 REG_WRITE(ah, AR_RX_FILTER, bits);
3532
f1dc5600
S		 3533 phybits = 0;
3534 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3535 phybits |= AR_PHY_ERR_RADAR;
3536 if (bits & ATH9K_RX_FILTER_PHYERR)
3537 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3538 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3539
f1dc5600
S		 3540 if (phybits)
3541 REG_WRITE(ah, AR_RXCFG,
3542 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3543 else
3544 REG_WRITE(ah, AR_RXCFG,
3545 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3546}
7322fd19 3547EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 3548
cbe61d8a 3549bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 3550{
63a75b91
SB		 3551 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3552 return false;
3553
3554 ath9k_hw_init_pll(ah, NULL);
3555 return true;
f1dc5600 3556}
7322fd19 3557EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 3558
cbe61d8a 3559bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 3560{
9ecdef4b 3561 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 3562 return false;
f078f209 3563
63a75b91
SB		 3564 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3565 return false;
3566
3567 ath9k_hw_init_pll(ah, NULL);
3568 return true;
f078f209 3569}
7322fd19 3570EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 3571
8fbff4b8 3572void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 3573{
608b88cb 3574 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 3575 struct ath9k_channel *chan = ah->curchan;
5f8e077c 3576 struct ieee80211_channel *channel = chan->chan;
f078f209 3577
608b88cb 3578 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 3579
8fbff4b8 3580 ah->eep_ops->set_txpower(ah, chan,
608b88cb 3581 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 3582 channel->max_antenna_gain * 2,
3583 channel->max_power * 2,
3584 min((u32) MAX_RATE_POWER,
608b88cb 3585 (u32) regulatory->power_limit));
6f255425 3586}
7322fd19 3587EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 3588
cbe61d8a 3589void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 3590{
1510718d 3591 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
f078f209 3592}
7322fd19 3593EXPORT_SYMBOL(ath9k_hw_setmac);
f078f209 3594
cbe61d8a 3595void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 3596{
2660b81a 3597 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 3598}
7322fd19 3599EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 3600
cbe61d8a 3601void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 3602{
f1dc5600
S		 3603 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3604 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 3605}
7322fd19 3606EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 3607
f2b2143e 3608void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 3609{
1510718d
LR		 3610 struct ath_common *common = ath9k_hw_common(ah);
3611
3612 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3613 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3614 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 3615}
7322fd19 3616EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 3617
cbe61d8a 3618u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 3619{
f1dc5600 3620 u64 tsf;
f078f209 3621
f1dc5600
S		 3622 tsf = REG_READ(ah, AR_TSF_U32);
3623 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 3624
f1dc5600
S		 3625 return tsf;
3626}
7322fd19 3627EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 3628
cbe61d8a 3629void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 3630{
27abe060 3631 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 3632 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 3633}
7322fd19 3634EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 3635
cbe61d8a 3636void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 3637{
f9b604f6
GJ		 3638 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3639 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 3640 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3641 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 3642
f1dc5600
S		 3643 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3644}
7322fd19 3645EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 3646
54e4cec6 3647void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 3648{
f1dc5600 3649 if (setting)
2660b81a 3650 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 3651 else
2660b81a 3652 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 3653}
7322fd19 3654EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 3655
30cbd422
LR		 3656/*
3657 * Extend 15-bit time stamp from rx descriptor to
3658 * a full 64-bit TSF using the current h/w TSF.
3659*/
3660u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3661{
3662 u64 tsf;
3663
3664 tsf = ath9k_hw_gettsf64(ah);
3665 if ((tsf & 0x7fff) < rstamp)
3666 tsf -= 0x8000;
3667 return (tsf & ~0x7fff) | rstamp;
3668}
3669EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3670
cbe61d8a 3671bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f1dc5600 3672{
f1dc5600 3673 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
c46917bb
LR		 3674 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3675 "bad slot time %u\n", us);
2660b81a 3676 ah->slottime = (u32) -1;
f1dc5600
S		 3677 return false;
3678 } else {
3679 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
2660b81a 3680 ah->slottime = us;
f1dc5600 3681 return true;
f078f209 3682 }
f1dc5600 3683}
7322fd19 3684EXPORT_SYMBOL(ath9k_hw_setslottime);
f1dc5600 3685
25c56eec 3686void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 3687{
25c56eec 3688 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 3689 u32 macmode;
3690
25c56eec 3691 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 3692 macmode = AR_2040_JOINED_RX_CLEAR;
3693 else
3694 macmode = 0;
f078f209 3695
f1dc5600 3696 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 3697}
ff155a45
VT		 3698
3699/* HW Generic timers configuration */
3700
3701static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3702{
3703 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3704 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3705 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3706 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3707 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3708 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3709 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3710 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3711 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3712 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3713 AR_NDP2_TIMER_MODE, 0x0002},
3714 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3715 AR_NDP2_TIMER_MODE, 0x0004},
3716 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3717 AR_NDP2_TIMER_MODE, 0x0008},
3718 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3719 AR_NDP2_TIMER_MODE, 0x0010},
3720 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3721 AR_NDP2_TIMER_MODE, 0x0020},
3722 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3723 AR_NDP2_TIMER_MODE, 0x0040},
3724 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3725 AR_NDP2_TIMER_MODE, 0x0080}
3726};
3727
3728/* HW generic timer primitives */
3729
3730/* compute and clear index of rightmost 1 */
3731static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3732{
3733 u32 b;
3734
3735 b = *mask;
3736 b &= (0-b);
3737 *mask &= ~b;
3738 b *= debruijn32;
3739 b >>= 27;
3740
3741 return timer_table->gen_timer_index[b];
3742}
3743
1773912b 3744u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 3745{
3746 return REG_READ(ah, AR_TSF_L32);
3747}
7322fd19 3748EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 3749
3750struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3751 void (*trigger)(void *),
3752 void (*overflow)(void *),
3753 void *arg,
3754 u8 timer_index)
3755{
3756 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3757 struct ath_gen_timer *timer;
3758
3759 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3760
3761 if (timer == NULL) {
c46917bb
LR		 3762 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3763 "Failed to allocate memory"
3764 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 3765 return NULL;
3766 }
3767
3768 /* allocate a hardware generic timer slot */
3769 timer_table->timers[timer_index] = timer;
3770 timer->index = timer_index;
3771 timer->trigger = trigger;
3772 timer->overflow = overflow;
3773 timer->arg = arg;
3774
3775 return timer;
3776}
7322fd19 3777EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3778
cd9bf689
LR		 3779void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3780 struct ath_gen_timer *timer,
3781 u32 timer_next,
3782 u32 timer_period)
ff155a45
VT		 3783{
3784 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3785 u32 tsf;
3786
3787 BUG_ON(!timer_period);
3788
3789 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3790
3791 tsf = ath9k_hw_gettsf32(ah);
3792
c46917bb
LR		 3793 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3794 "curent tsf %x period %x"
3795 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 3796
3797 /*
3798 * Pull timer_next forward if the current TSF already passed it
3799 * because of software latency
3800 */
3801 if (timer_next < tsf)
3802 timer_next = tsf + timer_period;
3803
3804 /*
3805 * Program generic timer registers
3806 */
3807 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3808 timer_next);
3809 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3810 timer_period);
3811 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3812 gen_tmr_configuration[timer->index].mode_mask);
3813
3814 /* Enable both trigger and thresh interrupt masks */
3815 REG_SET_BIT(ah, AR_IMR_S5,
3816 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3817 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 3818}
7322fd19 3819EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3820
cd9bf689 3821void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3822{
3823 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3824
3825 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3826 (timer->index >= ATH_MAX_GEN_TIMER)) {
3827 return;
3828 }
3829
3830 /* Clear generic timer enable bits. */
3831 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3832 gen_tmr_configuration[timer->index].mode_mask);
3833
3834 /* Disable both trigger and thresh interrupt masks */
3835 REG_CLR_BIT(ah, AR_IMR_S5,
3836 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3837 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3838
3839 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3840}
7322fd19 3841EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3842
3843void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3844{
3845 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3846
3847 /* free the hardware generic timer slot */
3848 timer_table->timers[timer->index] = NULL;
3849 kfree(timer);
3850}
7322fd19 3851EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3852
3853/*
3854 * Generic Timer Interrupts handling
3855 */
3856void ath_gen_timer_isr(struct ath_hw *ah)
3857{
3858 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3859 struct ath_gen_timer *timer;
c46917bb 3860 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3861 u32 trigger_mask, thresh_mask, index;
3862
3863 /* get hardware generic timer interrupt status */
3864 trigger_mask = ah->intr_gen_timer_trigger;
3865 thresh_mask = ah->intr_gen_timer_thresh;
3866 trigger_mask &= timer_table->timer_mask.val;
3867 thresh_mask &= timer_table->timer_mask.val;
3868
3869 trigger_mask &= ~thresh_mask;
3870
3871 while (thresh_mask) {
3872 index = rightmost_index(timer_table, &thresh_mask);
3873 timer = timer_table->timers[index];
3874 BUG_ON(!timer);
c46917bb
LR		 3875 ath_print(common, ATH_DBG_HWTIMER,
3876 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 3877 timer->overflow(timer->arg);
3878 }
3879
3880 while (trigger_mask) {
3881 index = rightmost_index(timer_table, &trigger_mask);
3882 timer = timer_table->timers[index];
3883 BUG_ON(!timer);
c46917bb
LR		 3884 ath_print(common, ATH_DBG_HWTIMER,
3885 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3886 timer->trigger(timer->arg);
3887 }
3888}
7322fd19 3889EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a
LR		 3890
3891static struct {
3892 u32 version;
3893 const char * name;
3894} ath_mac_bb_names[] = {
3895 /* Devices with external radios */
3896 { AR_SREV_VERSION_5416_PCI, "5416" },
3897 { AR_SREV_VERSION_5416_PCIE, "5418" },
3898 { AR_SREV_VERSION_9100, "9100" },
3899 { AR_SREV_VERSION_9160, "9160" },
3900 /* Single-chip solutions */
3901 { AR_SREV_VERSION_9280, "9280" },
3902 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3903 { AR_SREV_VERSION_9287, "9287" },
3904 { AR_SREV_VERSION_9271, "9271" },
2da4f01a
LR		 3905};
3906
3907/* For devices with external radios */
3908static struct {
3909 u16 version;
3910 const char * name;
3911} ath_rf_names[] = {
3912 { 0, "5133" },
3913 { AR_RAD5133_SREV_MAJOR, "5133" },
3914 { AR_RAD5122_SREV_MAJOR, "5122" },
3915 { AR_RAD2133_SREV_MAJOR, "2133" },
3916 { AR_RAD2122_SREV_MAJOR, "2122" }
3917};
3918
3919/*
3920 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3921 */
f934c4d9 3922static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3923{
3924 int i;
3925
3926 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3927 if (ath_mac_bb_names[i].version == mac_bb_version) {
3928 return ath_mac_bb_names[i].name;
3929 }
3930 }
3931
3932 return "????";
3933}
2da4f01a
LR		 3934
3935/*
3936 * Return the RF name. "????" is returned if the RF is unknown.
3937 * Used for devices with external radios.
3938 */
f934c4d9 3939static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3940{
3941 int i;
3942
3943 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3944 if (ath_rf_names[i].version == rf_version) {
3945 return ath_rf_names[i].name;
3946 }
3947 }
3948
3949 return "????";
3950}
f934c4d9
LR		 3951
3952void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3953{
3954 int used;
3955
3956 /* chipsets >= AR9280 are single-chip */
3957 if (AR_SREV_9280_10_OR_LATER(ah)) {
3958 used = snprintf(hw_name, len,
3959 "Atheros AR%s Rev:%x",
3960 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3961 ah->hw_version.macRev);
3962 }
3963 else {
3964 used = snprintf(hw_name, len,
3965 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3966 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3967 ah->hw_version.macRev,
3968 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3969 AR_RADIO_SREV_MAJOR)),
3970 ah->hw_version.phyRev);
3971 }
3972
3973 hw_name[used] = '\0';
3974}
3975EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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