Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
9d9779e7 | 19 | #include <linux/module.h> |
09d8e315 | 20 | #include <linux/time.h> |
c67ce339 | 21 | #include <linux/bitops.h> |
5ca06ebe | 22 | #include <linux/etherdevice.h> |
f078f209 LR |
23 | #include <asm/unaligned.h> |
24 | ||
af03abec | 25 | #include "hw.h" |
d70357d5 | 26 | #include "hw-ops.h" |
b622a720 | 27 | #include "ar9003_mac.h" |
f4701b5a | 28 | #include "ar9003_mci.h" |
362cd03f | 29 | #include "ar9003_phy.h" |
462e58f2 | 30 | #include "ath9k.h" |
f078f209 | 31 | |
cbe61d8a | 32 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
f078f209 | 33 | |
7322fd19 LR |
34 | MODULE_AUTHOR("Atheros Communications"); |
35 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
36 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
37 | MODULE_LICENSE("Dual BSD/GPL"); | |
38 | ||
dfdac8ac | 39 | static void ath9k_hw_set_clockrate(struct ath_hw *ah) |
f1dc5600 | 40 | { |
dfdac8ac | 41 | struct ath_common *common = ath9k_hw_common(ah); |
e4744ec7 | 42 | struct ath9k_channel *chan = ah->curchan; |
dfdac8ac | 43 | unsigned int clockrate; |
cbe61d8a | 44 | |
087b6ff6 FF |
45 | /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ |
46 | if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) | |
47 | clockrate = 117; | |
e4744ec7 | 48 | else if (!chan) /* should really check for CCK instead */ |
dfdac8ac | 49 | clockrate = ATH9K_CLOCK_RATE_CCK; |
e4744ec7 | 50 | else if (IS_CHAN_2GHZ(chan)) |
dfdac8ac FF |
51 | clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; |
52 | else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) | |
53 | clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; | |
e5553724 | 54 | else |
dfdac8ac FF |
55 | clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; |
56 | ||
beae416b MN |
57 | if (chan) { |
58 | if (IS_CHAN_HT40(chan)) | |
59 | clockrate *= 2; | |
e4744ec7 | 60 | if (IS_CHAN_HALF_RATE(chan)) |
906c7205 | 61 | clockrate /= 2; |
e4744ec7 | 62 | if (IS_CHAN_QUARTER_RATE(chan)) |
906c7205 FF |
63 | clockrate /= 4; |
64 | } | |
65 | ||
dfdac8ac | 66 | common->clockrate = clockrate; |
f1dc5600 S |
67 | } |
68 | ||
cbe61d8a | 69 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
f1dc5600 | 70 | { |
dfdac8ac | 71 | struct ath_common *common = ath9k_hw_common(ah); |
cbe61d8a | 72 | |
dfdac8ac | 73 | return usecs * common->clockrate; |
f1dc5600 | 74 | } |
f078f209 | 75 | |
0caa7b14 | 76 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
f078f209 LR |
77 | { |
78 | int i; | |
79 | ||
0caa7b14 S |
80 | BUG_ON(timeout < AH_TIME_QUANTUM); |
81 | ||
82 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { | |
f078f209 LR |
83 | if ((REG_READ(ah, reg) & mask) == val) |
84 | return true; | |
85 | ||
86 | udelay(AH_TIME_QUANTUM); | |
87 | } | |
04bd4638 | 88 | |
d2182b69 | 89 | ath_dbg(ath9k_hw_common(ah), ANY, |
226afe68 JP |
90 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", |
91 | timeout, reg, REG_READ(ah, reg), mask, val); | |
f078f209 | 92 | |
f1dc5600 | 93 | return false; |
f078f209 | 94 | } |
7322fd19 | 95 | EXPORT_SYMBOL(ath9k_hw_wait); |
f078f209 | 96 | |
7c5adc8d FF |
97 | void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, |
98 | int hw_delay) | |
99 | { | |
1a5e6326 | 100 | hw_delay /= 10; |
7c5adc8d FF |
101 | |
102 | if (IS_CHAN_HALF_RATE(chan)) | |
103 | hw_delay *= 2; | |
104 | else if (IS_CHAN_QUARTER_RATE(chan)) | |
105 | hw_delay *= 4; | |
106 | ||
107 | udelay(hw_delay + BASE_ACTIVATE_DELAY); | |
108 | } | |
109 | ||
0166b4be | 110 | void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, |
a9b6b256 FF |
111 | int column, unsigned int *writecnt) |
112 | { | |
113 | int r; | |
114 | ||
115 | ENABLE_REGWRITE_BUFFER(ah); | |
116 | for (r = 0; r < array->ia_rows; r++) { | |
117 | REG_WRITE(ah, INI_RA(array, r, 0), | |
118 | INI_RA(array, r, column)); | |
119 | DO_DELAY(*writecnt); | |
120 | } | |
121 | REGWRITE_BUFFER_FLUSH(ah); | |
122 | } | |
123 | ||
f078f209 LR |
124 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) |
125 | { | |
126 | u32 retval; | |
127 | int i; | |
128 | ||
129 | for (i = 0, retval = 0; i < n; i++) { | |
130 | retval = (retval << 1) | (val & 1); | |
131 | val >>= 1; | |
132 | } | |
133 | return retval; | |
134 | } | |
135 | ||
cbe61d8a | 136 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 137 | u8 phy, int kbps, |
f1dc5600 S |
138 | u32 frameLen, u16 rateix, |
139 | bool shortPreamble) | |
f078f209 | 140 | { |
f1dc5600 | 141 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
f078f209 | 142 | |
f1dc5600 S |
143 | if (kbps == 0) |
144 | return 0; | |
f078f209 | 145 | |
545750d3 | 146 | switch (phy) { |
46d14a58 | 147 | case WLAN_RC_PHY_CCK: |
f1dc5600 | 148 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
545750d3 | 149 | if (shortPreamble) |
f1dc5600 S |
150 | phyTime >>= 1; |
151 | numBits = frameLen << 3; | |
152 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); | |
153 | break; | |
46d14a58 | 154 | case WLAN_RC_PHY_OFDM: |
2660b81a | 155 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
f1dc5600 S |
156 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
157 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
158 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
159 | txTime = OFDM_SIFS_TIME_QUARTER | |
160 | + OFDM_PREAMBLE_TIME_QUARTER | |
161 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); | |
2660b81a S |
162 | } else if (ah->curchan && |
163 | IS_CHAN_HALF_RATE(ah->curchan)) { | |
f1dc5600 S |
164 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
165 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
166 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
167 | txTime = OFDM_SIFS_TIME_HALF + | |
168 | OFDM_PREAMBLE_TIME_HALF | |
169 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); | |
170 | } else { | |
171 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; | |
172 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
173 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
174 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME | |
175 | + (numSymbols * OFDM_SYMBOL_TIME); | |
176 | } | |
177 | break; | |
178 | default: | |
3800276a JP |
179 | ath_err(ath9k_hw_common(ah), |
180 | "Unknown phy %u (rate ix %u)\n", phy, rateix); | |
f1dc5600 S |
181 | txTime = 0; |
182 | break; | |
183 | } | |
f078f209 | 184 | |
f1dc5600 S |
185 | return txTime; |
186 | } | |
7322fd19 | 187 | EXPORT_SYMBOL(ath9k_hw_computetxtime); |
f078f209 | 188 | |
cbe61d8a | 189 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
f1dc5600 S |
190 | struct ath9k_channel *chan, |
191 | struct chan_centers *centers) | |
f078f209 | 192 | { |
f1dc5600 | 193 | int8_t extoff; |
f078f209 | 194 | |
f1dc5600 S |
195 | if (!IS_CHAN_HT40(chan)) { |
196 | centers->ctl_center = centers->ext_center = | |
197 | centers->synth_center = chan->channel; | |
198 | return; | |
f078f209 | 199 | } |
f078f209 | 200 | |
8896934c | 201 | if (IS_CHAN_HT40PLUS(chan)) { |
f1dc5600 S |
202 | centers->synth_center = |
203 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; | |
204 | extoff = 1; | |
205 | } else { | |
206 | centers->synth_center = | |
207 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; | |
208 | extoff = -1; | |
209 | } | |
f078f209 | 210 | |
f1dc5600 S |
211 | centers->ctl_center = |
212 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); | |
6420014c | 213 | /* 25 MHz spacing is supported by hw but not on upper layers */ |
f1dc5600 | 214 | centers->ext_center = |
6420014c | 215 | centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); |
f078f209 LR |
216 | } |
217 | ||
f1dc5600 S |
218 | /******************/ |
219 | /* Chip Revisions */ | |
220 | /******************/ | |
221 | ||
cbe61d8a | 222 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
f078f209 | 223 | { |
f1dc5600 | 224 | u32 val; |
f078f209 | 225 | |
09c74f7b FF |
226 | if (ah->get_mac_revision) |
227 | ah->hw_version.macRev = ah->get_mac_revision(); | |
228 | ||
ecb1d385 VT |
229 | switch (ah->hw_version.devid) { |
230 | case AR5416_AR9100_DEVID: | |
231 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; | |
232 | break; | |
3762561a GJ |
233 | case AR9300_DEVID_AR9330: |
234 | ah->hw_version.macVersion = AR_SREV_VERSION_9330; | |
09c74f7b | 235 | if (!ah->get_mac_revision) { |
3762561a GJ |
236 | val = REG_READ(ah, AR_SREV); |
237 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | |
238 | } | |
239 | return; | |
ecb1d385 VT |
240 | case AR9300_DEVID_AR9340: |
241 | ah->hw_version.macVersion = AR_SREV_VERSION_9340; | |
ecb1d385 | 242 | return; |
813831dc GJ |
243 | case AR9300_DEVID_QCA955X: |
244 | ah->hw_version.macVersion = AR_SREV_VERSION_9550; | |
245 | return; | |
e6b1e46e SM |
246 | case AR9300_DEVID_AR953X: |
247 | ah->hw_version.macVersion = AR_SREV_VERSION_9531; | |
248 | return; | |
2131fabb MP |
249 | case AR9300_DEVID_QCA956X: |
250 | ah->hw_version.macVersion = AR_SREV_VERSION_9561; | |
ecb1d385 VT |
251 | } |
252 | ||
f1dc5600 | 253 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
f078f209 | 254 | |
f1dc5600 S |
255 | if (val == 0xFF) { |
256 | val = REG_READ(ah, AR_SREV); | |
d535a42a S |
257 | ah->hw_version.macVersion = |
258 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; | |
259 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | |
76ed94be | 260 | |
77fac465 | 261 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) |
76ed94be MSS |
262 | ah->is_pciexpress = true; |
263 | else | |
264 | ah->is_pciexpress = (val & | |
265 | AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; | |
f1dc5600 S |
266 | } else { |
267 | if (!AR_SREV_9100(ah)) | |
d535a42a | 268 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
f078f209 | 269 | |
d535a42a | 270 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
f078f209 | 271 | |
d535a42a | 272 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
2660b81a | 273 | ah->is_pciexpress = true; |
f1dc5600 | 274 | } |
f078f209 LR |
275 | } |
276 | ||
f1dc5600 S |
277 | /************************************/ |
278 | /* HW Attach, Detach, Init Routines */ | |
279 | /************************************/ | |
280 | ||
cbe61d8a | 281 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
f078f209 | 282 | { |
040b74f7 | 283 | if (!AR_SREV_5416(ah)) |
f1dc5600 | 284 | return; |
f078f209 | 285 | |
f1dc5600 S |
286 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
287 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
288 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); | |
289 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); | |
290 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); | |
291 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); | |
292 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | |
293 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
294 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); | |
f078f209 | 295 | |
f1dc5600 | 296 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
f078f209 LR |
297 | } |
298 | ||
1f3f0618 | 299 | /* This should work for all families including legacy */ |
cbe61d8a | 300 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
f078f209 | 301 | { |
c46917bb | 302 | struct ath_common *common = ath9k_hw_common(ah); |
1f3f0618 | 303 | u32 regAddr[2] = { AR_STA_ID0 }; |
f1dc5600 | 304 | u32 regHold[2]; |
07b2fa5a JP |
305 | static const u32 patternData[4] = { |
306 | 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 | |
307 | }; | |
1f3f0618 | 308 | int i, j, loop_max; |
f078f209 | 309 | |
1f3f0618 SB |
310 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
311 | loop_max = 2; | |
312 | regAddr[1] = AR_PHY_BASE + (8 << 2); | |
313 | } else | |
314 | loop_max = 1; | |
315 | ||
316 | for (i = 0; i < loop_max; i++) { | |
f1dc5600 S |
317 | u32 addr = regAddr[i]; |
318 | u32 wrData, rdData; | |
f078f209 | 319 | |
f1dc5600 S |
320 | regHold[i] = REG_READ(ah, addr); |
321 | for (j = 0; j < 0x100; j++) { | |
322 | wrData = (j << 16) | j; | |
323 | REG_WRITE(ah, addr, wrData); | |
324 | rdData = REG_READ(ah, addr); | |
325 | if (rdData != wrData) { | |
3800276a JP |
326 | ath_err(common, |
327 | "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", | |
328 | addr, wrData, rdData); | |
f1dc5600 S |
329 | return false; |
330 | } | |
331 | } | |
332 | for (j = 0; j < 4; j++) { | |
333 | wrData = patternData[j]; | |
334 | REG_WRITE(ah, addr, wrData); | |
335 | rdData = REG_READ(ah, addr); | |
336 | if (wrData != rdData) { | |
3800276a JP |
337 | ath_err(common, |
338 | "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", | |
339 | addr, wrData, rdData); | |
f1dc5600 S |
340 | return false; |
341 | } | |
f078f209 | 342 | } |
f1dc5600 | 343 | REG_WRITE(ah, regAddr[i], regHold[i]); |
f078f209 | 344 | } |
f1dc5600 | 345 | udelay(100); |
cbe61d8a | 346 | |
f078f209 LR |
347 | return true; |
348 | } | |
349 | ||
b8b0f377 | 350 | static void ath9k_hw_init_config(struct ath_hw *ah) |
f1dc5600 | 351 | { |
f57cf939 SM |
352 | struct ath_common *common = ath9k_hw_common(ah); |
353 | ||
689e756f FF |
354 | ah->config.dma_beacon_response_time = 1; |
355 | ah->config.sw_beacon_response_time = 6; | |
2660b81a | 356 | ah->config.cwm_ignore_extcca = 0; |
2660b81a | 357 | ah->config.analog_shiftreg = 1; |
f078f209 | 358 | |
0ce024cb | 359 | ah->config.rx_intr_mitigation = true; |
6158425b | 360 | |
a64e1a45 SM |
361 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
362 | ah->config.rimt_last = 500; | |
363 | ah->config.rimt_first = 2000; | |
364 | } else { | |
365 | ah->config.rimt_last = 250; | |
366 | ah->config.rimt_first = 700; | |
367 | } | |
368 | ||
6158425b LR |
369 | /* |
370 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) | |
371 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). | |
372 | * This means we use it for all AR5416 devices, and the few | |
373 | * minor PCI AR9280 devices out there. | |
374 | * | |
375 | * Serialization is required because these devices do not handle | |
376 | * well the case of two concurrent reads/writes due to the latency | |
377 | * involved. During one read/write another read/write can be issued | |
378 | * on another CPU while the previous read/write may still be working | |
379 | * on our hardware, if we hit this case the hardware poops in a loop. | |
380 | * We prevent this by serializing reads and writes. | |
381 | * | |
382 | * This issue is not present on PCI-Express devices or pre-AR5416 | |
383 | * devices (legacy, 802.11abg). | |
384 | */ | |
385 | if (num_possible_cpus() > 1) | |
2d6a5e95 | 386 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
f57cf939 SM |
387 | |
388 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { | |
389 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || | |
390 | ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && | |
391 | !ah->is_pciexpress)) { | |
392 | ah->config.serialize_regmode = SER_REG_MODE_ON; | |
393 | } else { | |
394 | ah->config.serialize_regmode = SER_REG_MODE_OFF; | |
395 | } | |
396 | } | |
397 | ||
398 | ath_dbg(common, RESET, "serialize_regmode is %d\n", | |
399 | ah->config.serialize_regmode); | |
400 | ||
401 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) | |
402 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; | |
403 | else | |
404 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; | |
f078f209 LR |
405 | } |
406 | ||
50aca25b | 407 | static void ath9k_hw_init_defaults(struct ath_hw *ah) |
f078f209 | 408 | { |
608b88cb LR |
409 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
410 | ||
411 | regulatory->country_code = CTRY_DEFAULT; | |
412 | regulatory->power_limit = MAX_RATE_POWER; | |
608b88cb | 413 | |
d535a42a | 414 | ah->hw_version.magic = AR5416_MAGIC; |
d535a42a | 415 | ah->hw_version.subvendorid = 0; |
f078f209 | 416 | |
f57cf939 SM |
417 | ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | |
418 | AR_STA_ID1_MCAST_KSRCH; | |
f171760c FF |
419 | if (AR_SREV_9100(ah)) |
420 | ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; | |
f57cf939 | 421 | |
e3f2acc7 | 422 | ah->slottime = ATH9K_SLOT_TIME_9; |
2660b81a | 423 | ah->globaltxtimeout = (u32) -1; |
cbdec975 | 424 | ah->power_mode = ATH9K_PM_UNDEFINED; |
8efa7a81 | 425 | ah->htc_reset_init = true; |
f57cf939 | 426 | |
b5939e8c | 427 | ah->tpc_enabled = true; |
a9abe302 | 428 | |
f57cf939 SM |
429 | ah->ani_function = ATH9K_ANI_ALL; |
430 | if (!AR_SREV_9300_20_OR_LATER(ah)) | |
431 | ah->ani_function &= ~ATH9K_ANI_MRC_CCK; | |
432 | ||
433 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) | |
434 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); | |
435 | else | |
436 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); | |
f078f209 LR |
437 | } |
438 | ||
cbe61d8a | 439 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
f078f209 | 440 | { |
1510718d | 441 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
442 | u32 sum; |
443 | int i; | |
444 | u16 eeval; | |
07b2fa5a | 445 | static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; |
f078f209 LR |
446 | |
447 | sum = 0; | |
448 | for (i = 0; i < 3; i++) { | |
49101676 | 449 | eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); |
f078f209 | 450 | sum += eeval; |
1510718d LR |
451 | common->macaddr[2 * i] = eeval >> 8; |
452 | common->macaddr[2 * i + 1] = eeval & 0xff; | |
f078f209 | 453 | } |
5ca06ebe FF |
454 | if (!is_valid_ether_addr(common->macaddr)) { |
455 | ath_err(common, | |
456 | "eeprom contains invalid mac address: %pM\n", | |
457 | common->macaddr); | |
458 | ||
459 | random_ether_addr(common->macaddr); | |
460 | ath_err(common, | |
461 | "random mac address will be used: %pM\n", | |
462 | common->macaddr); | |
463 | } | |
f078f209 LR |
464 | |
465 | return 0; | |
466 | } | |
467 | ||
f637cfd6 | 468 | static int ath9k_hw_post_init(struct ath_hw *ah) |
f078f209 | 469 | { |
6cae913d | 470 | struct ath_common *common = ath9k_hw_common(ah); |
f1dc5600 | 471 | int ecode; |
f078f209 | 472 | |
6cae913d | 473 | if (common->bus_ops->ath_bus_type != ATH_USB) { |
527d485f S |
474 | if (!ath9k_hw_chip_test(ah)) |
475 | return -ENODEV; | |
476 | } | |
f078f209 | 477 | |
ebd5a14a LR |
478 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
479 | ecode = ar9002_hw_rf_claim(ah); | |
480 | if (ecode != 0) | |
481 | return ecode; | |
482 | } | |
f078f209 | 483 | |
f637cfd6 | 484 | ecode = ath9k_hw_eeprom_init(ah); |
f1dc5600 S |
485 | if (ecode != 0) |
486 | return ecode; | |
7d01b221 | 487 | |
d2182b69 | 488 | ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", |
226afe68 JP |
489 | ah->eep_ops->get_eeprom_ver(ah), |
490 | ah->eep_ops->get_eeprom_rev(ah)); | |
7d01b221 | 491 | |
e323300d | 492 | ath9k_hw_ani_init(ah); |
f078f209 | 493 | |
d3b371cb SM |
494 | /* |
495 | * EEPROM needs to be initialized before we do this. | |
496 | * This is required for regulatory compliance. | |
497 | */ | |
0c7c2bb4 | 498 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
d3b371cb SM |
499 | u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
500 | if ((regdmn & 0xF0) == CTL_FCC) { | |
0c7c2bb4 SM |
501 | ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; |
502 | ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; | |
d3b371cb SM |
503 | } |
504 | } | |
505 | ||
f078f209 LR |
506 | return 0; |
507 | } | |
508 | ||
c1b976d2 | 509 | static int ath9k_hw_attach_ops(struct ath_hw *ah) |
ee2bb460 | 510 | { |
c1b976d2 FF |
511 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
512 | return ar9002_hw_attach_ops(ah); | |
513 | ||
514 | ar9003_hw_attach_ops(ah); | |
515 | return 0; | |
aa4058ae LR |
516 | } |
517 | ||
d70357d5 LR |
518 | /* Called for all hardware families */ |
519 | static int __ath9k_hw_init(struct ath_hw *ah) | |
aa4058ae | 520 | { |
c46917bb | 521 | struct ath_common *common = ath9k_hw_common(ah); |
95fafca2 | 522 | int r = 0; |
aa4058ae | 523 | |
ac45c12d SB |
524 | ath9k_hw_read_revisions(ah); |
525 | ||
de82582b SM |
526 | switch (ah->hw_version.macVersion) { |
527 | case AR_SREV_VERSION_5416_PCI: | |
528 | case AR_SREV_VERSION_5416_PCIE: | |
529 | case AR_SREV_VERSION_9160: | |
530 | case AR_SREV_VERSION_9100: | |
531 | case AR_SREV_VERSION_9280: | |
532 | case AR_SREV_VERSION_9285: | |
533 | case AR_SREV_VERSION_9287: | |
534 | case AR_SREV_VERSION_9271: | |
535 | case AR_SREV_VERSION_9300: | |
536 | case AR_SREV_VERSION_9330: | |
537 | case AR_SREV_VERSION_9485: | |
538 | case AR_SREV_VERSION_9340: | |
539 | case AR_SREV_VERSION_9462: | |
540 | case AR_SREV_VERSION_9550: | |
541 | case AR_SREV_VERSION_9565: | |
e6b1e46e | 542 | case AR_SREV_VERSION_9531: |
2131fabb | 543 | case AR_SREV_VERSION_9561: |
de82582b SM |
544 | break; |
545 | default: | |
546 | ath_err(common, | |
547 | "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", | |
548 | ah->hw_version.macVersion, ah->hw_version.macRev); | |
549 | return -EOPNOTSUPP; | |
550 | } | |
551 | ||
0a8d7cb0 SB |
552 | /* |
553 | * Read back AR_WA into a permanent copy and set bits 14 and 17. | |
554 | * We need to do this to avoid RMW of this register. We cannot | |
555 | * read the reg when chip is asleep. | |
556 | */ | |
27251e00 SM |
557 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
558 | ah->WARegVal = REG_READ(ah, AR_WA); | |
559 | ah->WARegVal |= (AR_WA_D3_L1_DISABLE | | |
560 | AR_WA_ASPM_TIMER_BASED_DISABLE); | |
561 | } | |
0a8d7cb0 | 562 | |
aa4058ae | 563 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { |
3800276a | 564 | ath_err(common, "Couldn't reset chip\n"); |
95fafca2 | 565 | return -EIO; |
aa4058ae LR |
566 | } |
567 | ||
a4a2954f SM |
568 | if (AR_SREV_9565(ah)) { |
569 | ah->WARegVal |= AR_WA_BIT22; | |
570 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
571 | } | |
572 | ||
bab1f62e LR |
573 | ath9k_hw_init_defaults(ah); |
574 | ath9k_hw_init_config(ah); | |
575 | ||
c1b976d2 FF |
576 | r = ath9k_hw_attach_ops(ah); |
577 | if (r) | |
578 | return r; | |
d70357d5 | 579 | |
9ecdef4b | 580 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
3800276a | 581 | ath_err(common, "Couldn't wakeup chip\n"); |
95fafca2 | 582 | return -EIO; |
aa4058ae LR |
583 | } |
584 | ||
2c8e5937 | 585 | if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || |
c95b584b | 586 | AR_SREV_9330(ah) || AR_SREV_9550(ah)) |
d7e7d229 LR |
587 | ah->is_pciexpress = false; |
588 | ||
aa4058ae | 589 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
aa4058ae LR |
590 | ath9k_hw_init_cal_settings(ah); |
591 | ||
69ce674b | 592 | if (!ah->is_pciexpress) |
aa4058ae LR |
593 | ath9k_hw_disablepcie(ah); |
594 | ||
f637cfd6 | 595 | r = ath9k_hw_post_init(ah); |
aa4058ae | 596 | if (r) |
95fafca2 | 597 | return r; |
aa4058ae LR |
598 | |
599 | ath9k_hw_init_mode_gain_regs(ah); | |
a9a29ce6 GJ |
600 | r = ath9k_hw_fill_cap_info(ah); |
601 | if (r) | |
602 | return r; | |
603 | ||
4f3acf81 LR |
604 | r = ath9k_hw_init_macaddr(ah); |
605 | if (r) { | |
3800276a | 606 | ath_err(common, "Failed to initialize MAC address\n"); |
95fafca2 | 607 | return r; |
f078f209 LR |
608 | } |
609 | ||
4598702d | 610 | ath9k_hw_init_hang_checks(ah); |
f078f209 | 611 | |
211f5859 LR |
612 | common->state = ATH_HW_INITIALIZED; |
613 | ||
4f3acf81 | 614 | return 0; |
f078f209 LR |
615 | } |
616 | ||
d70357d5 | 617 | int ath9k_hw_init(struct ath_hw *ah) |
f078f209 | 618 | { |
d70357d5 LR |
619 | int ret; |
620 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 621 | |
77fac465 | 622 | /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ |
d70357d5 LR |
623 | switch (ah->hw_version.devid) { |
624 | case AR5416_DEVID_PCI: | |
625 | case AR5416_DEVID_PCIE: | |
626 | case AR5416_AR9100_DEVID: | |
627 | case AR9160_DEVID_PCI: | |
628 | case AR9280_DEVID_PCI: | |
629 | case AR9280_DEVID_PCIE: | |
630 | case AR9285_DEVID_PCIE: | |
db3cc53a SB |
631 | case AR9287_DEVID_PCI: |
632 | case AR9287_DEVID_PCIE: | |
d70357d5 | 633 | case AR2427_DEVID_PCIE: |
db3cc53a | 634 | case AR9300_DEVID_PCIE: |
3050c914 | 635 | case AR9300_DEVID_AR9485_PCIE: |
999a7a88 | 636 | case AR9300_DEVID_AR9330: |
bca04689 | 637 | case AR9300_DEVID_AR9340: |
2b943a33 | 638 | case AR9300_DEVID_QCA955X: |
5a63ef0f | 639 | case AR9300_DEVID_AR9580: |
423e38e8 | 640 | case AR9300_DEVID_AR9462: |
d4e5979c | 641 | case AR9485_DEVID_AR1111: |
77fac465 | 642 | case AR9300_DEVID_AR9565: |
e6b1e46e | 643 | case AR9300_DEVID_AR953X: |
2131fabb | 644 | case AR9300_DEVID_QCA956X: |
d70357d5 LR |
645 | break; |
646 | default: | |
647 | if (common->bus_ops->ath_bus_type == ATH_USB) | |
648 | break; | |
3800276a JP |
649 | ath_err(common, "Hardware device ID 0x%04x not supported\n", |
650 | ah->hw_version.devid); | |
d70357d5 LR |
651 | return -EOPNOTSUPP; |
652 | } | |
f078f209 | 653 | |
d70357d5 LR |
654 | ret = __ath9k_hw_init(ah); |
655 | if (ret) { | |
3800276a JP |
656 | ath_err(common, |
657 | "Unable to initialize hardware; initialization status: %d\n", | |
658 | ret); | |
d70357d5 LR |
659 | return ret; |
660 | } | |
f078f209 | 661 | |
c774d57f LB |
662 | ath_dynack_init(ah); |
663 | ||
d70357d5 | 664 | return 0; |
f078f209 | 665 | } |
d70357d5 | 666 | EXPORT_SYMBOL(ath9k_hw_init); |
f078f209 | 667 | |
cbe61d8a | 668 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
f078f209 | 669 | { |
7d0d0df0 S |
670 | ENABLE_REGWRITE_BUFFER(ah); |
671 | ||
f1dc5600 S |
672 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
673 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); | |
f078f209 | 674 | |
f1dc5600 S |
675 | REG_WRITE(ah, AR_QOS_NO_ACK, |
676 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | | |
677 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | | |
678 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); | |
679 | ||
680 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); | |
681 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); | |
682 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); | |
683 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); | |
684 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); | |
7d0d0df0 S |
685 | |
686 | REGWRITE_BUFFER_FLUSH(ah); | |
f078f209 LR |
687 | } |
688 | ||
b84628eb | 689 | u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) |
b1415819 | 690 | { |
f18e3c6b MSS |
691 | struct ath_common *common = ath9k_hw_common(ah); |
692 | int i = 0; | |
693 | ||
ca7a4deb FF |
694 | REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); |
695 | udelay(100); | |
696 | REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); | |
b1415819 | 697 | |
f18e3c6b MSS |
698 | while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { |
699 | ||
ca7a4deb | 700 | udelay(100); |
b1415819 | 701 | |
f18e3c6b MSS |
702 | if (WARN_ON_ONCE(i >= 100)) { |
703 | ath_err(common, "PLL4 meaurement not done\n"); | |
704 | break; | |
705 | } | |
706 | ||
707 | i++; | |
708 | } | |
709 | ||
ca7a4deb | 710 | return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; |
b1415819 VN |
711 | } |
712 | EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); | |
713 | ||
cbe61d8a | 714 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
f1dc5600 | 715 | struct ath9k_channel *chan) |
f078f209 | 716 | { |
d09b17f7 VT |
717 | u32 pll; |
718 | ||
5fb9b1b9 FF |
719 | pll = ath9k_hw_compute_pll_control(ah, chan); |
720 | ||
a4a2954f | 721 | if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { |
3dfd7f60 VT |
722 | /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ |
723 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
724 | AR_CH0_BB_DPLL2_PLL_PWD, 0x1); | |
725 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
726 | AR_CH0_DPLL2_KD, 0x40); | |
727 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
728 | AR_CH0_DPLL2_KI, 0x4); | |
22983c30 | 729 | |
3dfd7f60 VT |
730 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, |
731 | AR_CH0_BB_DPLL1_REFDIV, 0x5); | |
732 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, | |
733 | AR_CH0_BB_DPLL1_NINI, 0x58); | |
734 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, | |
735 | AR_CH0_BB_DPLL1_NFRAC, 0x0); | |
22983c30 VN |
736 | |
737 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
3dfd7f60 VT |
738 | AR_CH0_BB_DPLL2_OUTDIV, 0x1); |
739 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
740 | AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); | |
22983c30 | 741 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
3dfd7f60 | 742 | AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); |
22983c30 | 743 | |
3dfd7f60 | 744 | /* program BB PLL phase_shift to 0x6 */ |
22983c30 | 745 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, |
3dfd7f60 VT |
746 | AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); |
747 | ||
748 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
749 | AR_CH0_BB_DPLL2_PLL_PWD, 0x0); | |
75e03512 | 750 | udelay(1000); |
a5415d62 GJ |
751 | } else if (AR_SREV_9330(ah)) { |
752 | u32 ddr_dpll2, pll_control2, kd; | |
753 | ||
754 | if (ah->is_clk_25mhz) { | |
755 | ddr_dpll2 = 0x18e82f01; | |
756 | pll_control2 = 0xe04a3d; | |
757 | kd = 0x1d; | |
758 | } else { | |
759 | ddr_dpll2 = 0x19e82f01; | |
760 | pll_control2 = 0x886666; | |
761 | kd = 0x3d; | |
762 | } | |
763 | ||
764 | /* program DDR PLL ki and kd value */ | |
765 | REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); | |
766 | ||
767 | /* program DDR PLL phase_shift */ | |
768 | REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, | |
769 | AR_CH0_DPLL3_PHASE_SHIFT, 0x1); | |
770 | ||
5fb9b1b9 FF |
771 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, |
772 | pll | AR_RTC_9300_PLL_BYPASS); | |
a5415d62 GJ |
773 | udelay(1000); |
774 | ||
775 | /* program refdiv, nint, frac to RTC register */ | |
776 | REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); | |
777 | ||
778 | /* program BB PLL kd and ki value */ | |
779 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); | |
780 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); | |
781 | ||
782 | /* program BB PLL phase_shift */ | |
783 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, | |
784 | AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); | |
ede6a5e7 MP |
785 | } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || |
786 | AR_SREV_9561(ah)) { | |
0b488ac6 VT |
787 | u32 regval, pll2_divint, pll2_divfrac, refdiv; |
788 | ||
5fb9b1b9 FF |
789 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, |
790 | pll | AR_RTC_9300_SOC_PLL_BYPASS); | |
0b488ac6 VT |
791 | udelay(1000); |
792 | ||
793 | REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); | |
794 | udelay(100); | |
795 | ||
796 | if (ah->is_clk_25mhz) { | |
ede6a5e7 | 797 | if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { |
2c323058 SM |
798 | pll2_divint = 0x1c; |
799 | pll2_divfrac = 0xa3d2; | |
800 | refdiv = 1; | |
801 | } else { | |
802 | pll2_divint = 0x54; | |
803 | pll2_divfrac = 0x1eb85; | |
804 | refdiv = 3; | |
805 | } | |
0b488ac6 | 806 | } else { |
fc05a317 GJ |
807 | if (AR_SREV_9340(ah)) { |
808 | pll2_divint = 88; | |
809 | pll2_divfrac = 0; | |
810 | refdiv = 5; | |
811 | } else { | |
812 | pll2_divint = 0x11; | |
ede6a5e7 MP |
813 | pll2_divfrac = (AR_SREV_9531(ah) || |
814 | AR_SREV_9561(ah)) ? | |
815 | 0x26665 : 0x26666; | |
fc05a317 GJ |
816 | refdiv = 1; |
817 | } | |
0b488ac6 VT |
818 | } |
819 | ||
820 | regval = REG_READ(ah, AR_PHY_PLL_MODE); | |
ede6a5e7 | 821 | if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) |
2c323058 SM |
822 | regval |= (0x1 << 22); |
823 | else | |
824 | regval |= (0x1 << 16); | |
0b488ac6 VT |
825 | REG_WRITE(ah, AR_PHY_PLL_MODE, regval); |
826 | udelay(100); | |
827 | ||
828 | REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | | |
829 | (pll2_divint << 18) | pll2_divfrac); | |
830 | udelay(100); | |
831 | ||
832 | regval = REG_READ(ah, AR_PHY_PLL_MODE); | |
fc05a317 | 833 | if (AR_SREV_9340(ah)) |
2c323058 SM |
834 | regval = (regval & 0x80071fff) | |
835 | (0x1 << 30) | | |
836 | (0x1 << 13) | | |
837 | (0x4 << 26) | | |
838 | (0x18 << 19); | |
ede6a5e7 | 839 | else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { |
2c323058 SM |
840 | regval = (regval & 0x01c00fff) | |
841 | (0x1 << 31) | | |
842 | (0x2 << 29) | | |
843 | (0xa << 25) | | |
ede6a5e7 MP |
844 | (0x1 << 19); |
845 | ||
846 | if (AR_SREV_9531(ah)) | |
847 | regval |= (0x6 << 12); | |
848 | } else | |
2c323058 SM |
849 | regval = (regval & 0x80071fff) | |
850 | (0x3 << 30) | | |
851 | (0x1 << 13) | | |
852 | (0x4 << 26) | | |
853 | (0x60 << 19); | |
0b488ac6 | 854 | REG_WRITE(ah, AR_PHY_PLL_MODE, regval); |
2c323058 | 855 | |
ede6a5e7 | 856 | if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) |
2c323058 SM |
857 | REG_WRITE(ah, AR_PHY_PLL_MODE, |
858 | REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); | |
859 | else | |
860 | REG_WRITE(ah, AR_PHY_PLL_MODE, | |
861 | REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); | |
862 | ||
0b488ac6 | 863 | udelay(1000); |
22983c30 | 864 | } |
d09b17f7 | 865 | |
8565f8bf SM |
866 | if (AR_SREV_9565(ah)) |
867 | pll |= 0x40000; | |
d03a66c1 | 868 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
f078f209 | 869 | |
fc05a317 GJ |
870 | if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || |
871 | AR_SREV_9550(ah)) | |
3dfd7f60 VT |
872 | udelay(1000); |
873 | ||
c75724d1 LR |
874 | /* Switch the core clock for ar9271 to 117Mhz */ |
875 | if (AR_SREV_9271(ah)) { | |
25e2ab17 S |
876 | udelay(500); |
877 | REG_WRITE(ah, 0x50040, 0x304); | |
c75724d1 LR |
878 | } |
879 | ||
f1dc5600 S |
880 | udelay(RTC_PLL_SETTLE_DELAY); |
881 | ||
882 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); | |
f078f209 LR |
883 | } |
884 | ||
cbe61d8a | 885 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
d97809db | 886 | enum nl80211_iftype opmode) |
f078f209 | 887 | { |
79d1d2b8 | 888 | u32 sync_default = AR_INTR_SYNC_DEFAULT; |
152d530d | 889 | u32 imr_reg = AR_IMR_TXERR | |
f1dc5600 S |
890 | AR_IMR_TXURN | |
891 | AR_IMR_RXERR | | |
892 | AR_IMR_RXORN | | |
893 | AR_IMR_BCNMISC; | |
f078f209 | 894 | |
ede6a5e7 MP |
895 | if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || |
896 | AR_SREV_9561(ah)) | |
79d1d2b8 VT |
897 | sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; |
898 | ||
66860240 VT |
899 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
900 | imr_reg |= AR_IMR_RXOK_HP; | |
901 | if (ah->config.rx_intr_mitigation) | |
902 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | |
903 | else | |
904 | imr_reg |= AR_IMR_RXOK_LP; | |
f078f209 | 905 | |
66860240 VT |
906 | } else { |
907 | if (ah->config.rx_intr_mitigation) | |
908 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | |
909 | else | |
910 | imr_reg |= AR_IMR_RXOK; | |
911 | } | |
f078f209 | 912 | |
66860240 VT |
913 | if (ah->config.tx_intr_mitigation) |
914 | imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; | |
915 | else | |
916 | imr_reg |= AR_IMR_TXOK; | |
f078f209 | 917 | |
7d0d0df0 S |
918 | ENABLE_REGWRITE_BUFFER(ah); |
919 | ||
152d530d | 920 | REG_WRITE(ah, AR_IMR, imr_reg); |
74bad5cb PR |
921 | ah->imrs2_reg |= AR_IMR_S2_GTT; |
922 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); | |
f078f209 | 923 | |
f1dc5600 S |
924 | if (!AR_SREV_9100(ah)) { |
925 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); | |
79d1d2b8 | 926 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); |
f1dc5600 S |
927 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); |
928 | } | |
66860240 | 929 | |
7d0d0df0 | 930 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 931 | |
66860240 VT |
932 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
933 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); | |
934 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); | |
935 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); | |
936 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); | |
937 | } | |
f078f209 LR |
938 | } |
939 | ||
b6ba41bb FF |
940 | static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) |
941 | { | |
942 | u32 val = ath9k_hw_mac_to_clks(ah, us - 2); | |
943 | val = min(val, (u32) 0xFFFF); | |
944 | REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); | |
945 | } | |
946 | ||
8e15e094 | 947 | void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
f078f209 | 948 | { |
0005baf4 FF |
949 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
950 | val = min(val, (u32) 0xFFFF); | |
951 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); | |
f078f209 LR |
952 | } |
953 | ||
8e15e094 | 954 | void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
f078f209 | 955 | { |
0005baf4 FF |
956 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
957 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); | |
958 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); | |
959 | } | |
960 | ||
8e15e094 | 961 | void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) |
0005baf4 FF |
962 | { |
963 | u32 val = ath9k_hw_mac_to_clks(ah, us); | |
964 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); | |
965 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); | |
f078f209 | 966 | } |
f1dc5600 | 967 | |
cbe61d8a | 968 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
f078f209 | 969 | { |
f078f209 | 970 | if (tu > 0xFFFF) { |
d2182b69 JP |
971 | ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", |
972 | tu); | |
2660b81a | 973 | ah->globaltxtimeout = (u32) -1; |
f078f209 LR |
974 | return false; |
975 | } else { | |
976 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); | |
2660b81a | 977 | ah->globaltxtimeout = tu; |
f078f209 LR |
978 | return true; |
979 | } | |
980 | } | |
981 | ||
0005baf4 | 982 | void ath9k_hw_init_global_settings(struct ath_hw *ah) |
f078f209 | 983 | { |
b6ba41bb | 984 | struct ath_common *common = ath9k_hw_common(ah); |
b6ba41bb | 985 | const struct ath9k_channel *chan = ah->curchan; |
e115b7ec | 986 | int acktimeout, ctstimeout, ack_offset = 0; |
e239d859 | 987 | int slottime; |
0005baf4 | 988 | int sifstime; |
b6ba41bb FF |
989 | int rx_lat = 0, tx_lat = 0, eifs = 0; |
990 | u32 reg; | |
0005baf4 | 991 | |
d2182b69 | 992 | ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", |
226afe68 | 993 | ah->misc_mode); |
f078f209 | 994 | |
b6ba41bb FF |
995 | if (!chan) |
996 | return; | |
997 | ||
2660b81a | 998 | if (ah->misc_mode != 0) |
ca7a4deb | 999 | REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); |
0005baf4 | 1000 | |
81a91d57 RM |
1001 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
1002 | rx_lat = 41; | |
1003 | else | |
1004 | rx_lat = 37; | |
b6ba41bb FF |
1005 | tx_lat = 54; |
1006 | ||
e88e4861 FF |
1007 | if (IS_CHAN_5GHZ(chan)) |
1008 | sifstime = 16; | |
1009 | else | |
1010 | sifstime = 10; | |
1011 | ||
b6ba41bb FF |
1012 | if (IS_CHAN_HALF_RATE(chan)) { |
1013 | eifs = 175; | |
1014 | rx_lat *= 2; | |
1015 | tx_lat *= 2; | |
1016 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) | |
1017 | tx_lat += 11; | |
1018 | ||
92367fe7 | 1019 | sifstime = 32; |
e115b7ec | 1020 | ack_offset = 16; |
b6ba41bb | 1021 | slottime = 13; |
b6ba41bb FF |
1022 | } else if (IS_CHAN_QUARTER_RATE(chan)) { |
1023 | eifs = 340; | |
81a91d57 | 1024 | rx_lat = (rx_lat * 4) - 1; |
b6ba41bb FF |
1025 | tx_lat *= 4; |
1026 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) | |
1027 | tx_lat += 22; | |
1028 | ||
92367fe7 | 1029 | sifstime = 64; |
e115b7ec | 1030 | ack_offset = 32; |
b6ba41bb | 1031 | slottime = 21; |
b6ba41bb | 1032 | } else { |
a7be039d RM |
1033 | if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { |
1034 | eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; | |
1035 | reg = AR_USEC_ASYNC_FIFO; | |
1036 | } else { | |
1037 | eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ | |
1038 | common->clockrate; | |
1039 | reg = REG_READ(ah, AR_USEC); | |
1040 | } | |
b6ba41bb FF |
1041 | rx_lat = MS(reg, AR_USEC_RX_LAT); |
1042 | tx_lat = MS(reg, AR_USEC_TX_LAT); | |
1043 | ||
1044 | slottime = ah->slottime; | |
b6ba41bb | 1045 | } |
0005baf4 | 1046 | |
e239d859 | 1047 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ |
f77f8234 MK |
1048 | slottime += 3 * ah->coverage_class; |
1049 | acktimeout = slottime + sifstime + ack_offset; | |
adb5066a | 1050 | ctstimeout = acktimeout; |
42c4568a FF |
1051 | |
1052 | /* | |
1053 | * Workaround for early ACK timeouts, add an offset to match the | |
55a2bb4a | 1054 | * initval's 64us ack timeout value. Use 48us for the CTS timeout. |
42c4568a FF |
1055 | * This was initially only meant to work around an issue with delayed |
1056 | * BA frames in some implementations, but it has been found to fix ACK | |
1057 | * timeout issues in other cases as well. | |
1058 | */ | |
e4744ec7 | 1059 | if (IS_CHAN_2GHZ(chan) && |
e115b7ec | 1060 | !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { |
42c4568a | 1061 | acktimeout += 64 - sifstime - ah->slottime; |
55a2bb4a FF |
1062 | ctstimeout += 48 - sifstime - ah->slottime; |
1063 | } | |
1064 | ||
7aefa8aa LB |
1065 | if (ah->dynack.enabled) { |
1066 | acktimeout = ah->dynack.ackto; | |
1067 | ctstimeout = acktimeout; | |
1068 | slottime = (acktimeout - 3) / 2; | |
1069 | } else { | |
1070 | ah->dynack.ackto = acktimeout; | |
1071 | } | |
1072 | ||
b6ba41bb FF |
1073 | ath9k_hw_set_sifs_time(ah, sifstime); |
1074 | ath9k_hw_setslottime(ah, slottime); | |
0005baf4 | 1075 | ath9k_hw_set_ack_timeout(ah, acktimeout); |
adb5066a | 1076 | ath9k_hw_set_cts_timeout(ah, ctstimeout); |
2660b81a S |
1077 | if (ah->globaltxtimeout != (u32) -1) |
1078 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); | |
b6ba41bb FF |
1079 | |
1080 | REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); | |
1081 | REG_RMW(ah, AR_USEC, | |
1082 | (common->clockrate - 1) | | |
1083 | SM(rx_lat, AR_USEC_RX_LAT) | | |
1084 | SM(tx_lat, AR_USEC_TX_LAT), | |
1085 | AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); | |
1086 | ||
f1dc5600 | 1087 | } |
0005baf4 | 1088 | EXPORT_SYMBOL(ath9k_hw_init_global_settings); |
f1dc5600 | 1089 | |
285f2dda | 1090 | void ath9k_hw_deinit(struct ath_hw *ah) |
f1dc5600 | 1091 | { |
211f5859 LR |
1092 | struct ath_common *common = ath9k_hw_common(ah); |
1093 | ||
736b3a27 | 1094 | if (common->state < ATH_HW_INITIALIZED) |
c1b976d2 | 1095 | return; |
211f5859 | 1096 | |
9ecdef4b | 1097 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
f1dc5600 | 1098 | } |
285f2dda | 1099 | EXPORT_SYMBOL(ath9k_hw_deinit); |
f1dc5600 | 1100 | |
f1dc5600 S |
1101 | /*******/ |
1102 | /* INI */ | |
1103 | /*******/ | |
1104 | ||
8fe65368 | 1105 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) |
3a702e49 BC |
1106 | { |
1107 | u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); | |
1108 | ||
6b21fd20 | 1109 | if (IS_CHAN_2GHZ(chan)) |
3a702e49 BC |
1110 | ctl |= CTL_11G; |
1111 | else | |
1112 | ctl |= CTL_11A; | |
1113 | ||
1114 | return ctl; | |
1115 | } | |
1116 | ||
f1dc5600 S |
1117 | /****************************************/ |
1118 | /* Reset and Channel Switching Routines */ | |
1119 | /****************************************/ | |
f1dc5600 | 1120 | |
cbe61d8a | 1121 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
f1dc5600 | 1122 | { |
57b32227 | 1123 | struct ath_common *common = ath9k_hw_common(ah); |
86c157b3 | 1124 | int txbuf_size; |
f1dc5600 | 1125 | |
7d0d0df0 S |
1126 | ENABLE_REGWRITE_BUFFER(ah); |
1127 | ||
d7e7d229 LR |
1128 | /* |
1129 | * set AHB_MODE not to do cacheline prefetches | |
1130 | */ | |
ca7a4deb FF |
1131 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1132 | REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); | |
f1dc5600 | 1133 | |
d7e7d229 LR |
1134 | /* |
1135 | * let mac dma reads be in 128 byte chunks | |
1136 | */ | |
ca7a4deb | 1137 | REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); |
f1dc5600 | 1138 | |
7d0d0df0 | 1139 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1140 | |
d7e7d229 LR |
1141 | /* |
1142 | * Restore TX Trigger Level to its pre-reset value. | |
1143 | * The initial value depends on whether aggregation is enabled, and is | |
1144 | * adjusted whenever underruns are detected. | |
1145 | */ | |
57b32227 FF |
1146 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1147 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); | |
f1dc5600 | 1148 | |
7d0d0df0 | 1149 | ENABLE_REGWRITE_BUFFER(ah); |
f1dc5600 | 1150 | |
d7e7d229 LR |
1151 | /* |
1152 | * let mac dma writes be in 128 byte chunks | |
1153 | */ | |
ca7a4deb | 1154 | REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); |
f1dc5600 | 1155 | |
d7e7d229 LR |
1156 | /* |
1157 | * Setup receive FIFO threshold to hold off TX activities | |
1158 | */ | |
f1dc5600 S |
1159 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
1160 | ||
57b32227 FF |
1161 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1162 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); | |
1163 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); | |
1164 | ||
1165 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - | |
1166 | ah->caps.rx_status_len); | |
1167 | } | |
1168 | ||
d7e7d229 LR |
1169 | /* |
1170 | * reduce the number of usable entries in PCU TXBUF to avoid | |
1171 | * wrap around issues. | |
1172 | */ | |
f1dc5600 | 1173 | if (AR_SREV_9285(ah)) { |
d7e7d229 LR |
1174 | /* For AR9285 the number of Fifos are reduced to half. |
1175 | * So set the usable tx buf size also to half to | |
1176 | * avoid data/delimiter underruns | |
1177 | */ | |
86c157b3 FF |
1178 | txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; |
1179 | } else if (AR_SREV_9340_13_OR_LATER(ah)) { | |
1180 | /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ | |
1181 | txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; | |
1182 | } else { | |
1183 | txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; | |
f1dc5600 | 1184 | } |
744d4025 | 1185 | |
86c157b3 FF |
1186 | if (!AR_SREV_9271(ah)) |
1187 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); | |
1188 | ||
7d0d0df0 | 1189 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1190 | |
744d4025 VT |
1191 | if (AR_SREV_9300_20_OR_LATER(ah)) |
1192 | ath9k_hw_reset_txstatus_ring(ah); | |
f1dc5600 S |
1193 | } |
1194 | ||
cbe61d8a | 1195 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
f1dc5600 | 1196 | { |
ca7a4deb FF |
1197 | u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; |
1198 | u32 set = AR_STA_ID1_KSRCH_MODE; | |
f1dc5600 | 1199 | |
f1dc5600 | 1200 | switch (opmode) { |
d97809db | 1201 | case NL80211_IFTYPE_ADHOC: |
83322eb8 FF |
1202 | if (!AR_SREV_9340_13(ah)) { |
1203 | set |= AR_STA_ID1_ADHOC; | |
1204 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
1205 | break; | |
1206 | } | |
1207 | /* fall through */ | |
2664d666 | 1208 | case NL80211_IFTYPE_MESH_POINT: |
ca7a4deb FF |
1209 | case NL80211_IFTYPE_AP: |
1210 | set |= AR_STA_ID1_STA_AP; | |
1211 | /* fall through */ | |
d97809db | 1212 | case NL80211_IFTYPE_STATION: |
ca7a4deb | 1213 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
f078f209 | 1214 | break; |
5f841b41 | 1215 | default: |
ca7a4deb FF |
1216 | if (!ah->is_monitoring) |
1217 | set = 0; | |
5f841b41 | 1218 | break; |
f1dc5600 | 1219 | } |
ca7a4deb | 1220 | REG_RMW(ah, AR_STA_ID1, set, mask); |
f1dc5600 S |
1221 | } |
1222 | ||
8fe65368 LR |
1223 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
1224 | u32 *coef_mantissa, u32 *coef_exponent) | |
f1dc5600 S |
1225 | { |
1226 | u32 coef_exp, coef_man; | |
1227 | ||
1228 | for (coef_exp = 31; coef_exp > 0; coef_exp--) | |
1229 | if ((coef_scaled >> coef_exp) & 0x1) | |
1230 | break; | |
1231 | ||
1232 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); | |
1233 | ||
1234 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); | |
1235 | ||
1236 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); | |
1237 | *coef_exponent = coef_exp - 16; | |
1238 | } | |
1239 | ||
d7df7a55 SM |
1240 | /* AR9330 WAR: |
1241 | * call external reset function to reset WMAC if: | |
1242 | * - doing a cold reset | |
1243 | * - we have pending frames in the TX queues. | |
1244 | */ | |
1245 | static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) | |
1246 | { | |
1247 | int i, npend = 0; | |
1248 | ||
1249 | for (i = 0; i < AR_NUM_QCU; i++) { | |
1250 | npend = ath9k_hw_numtxpending(ah, i); | |
1251 | if (npend) | |
1252 | break; | |
1253 | } | |
1254 | ||
1255 | if (ah->external_reset && | |
1256 | (npend || type == ATH9K_RESET_COLD)) { | |
1257 | int reset_err = 0; | |
1258 | ||
1259 | ath_dbg(ath9k_hw_common(ah), RESET, | |
1260 | "reset MAC via external reset\n"); | |
1261 | ||
1262 | reset_err = ah->external_reset(); | |
1263 | if (reset_err) { | |
1264 | ath_err(ath9k_hw_common(ah), | |
1265 | "External reset failed, err=%d\n", | |
1266 | reset_err); | |
1267 | return false; | |
1268 | } | |
1269 | ||
1270 | REG_WRITE(ah, AR_RTC_RESET, 1); | |
1271 | } | |
1272 | ||
1273 | return true; | |
1274 | } | |
1275 | ||
cbe61d8a | 1276 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
f1dc5600 S |
1277 | { |
1278 | u32 rst_flags; | |
1279 | u32 tmpReg; | |
1280 | ||
70768496 | 1281 | if (AR_SREV_9100(ah)) { |
ca7a4deb FF |
1282 | REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, |
1283 | AR_RTC_DERIVED_CLK_PERIOD, 1); | |
70768496 S |
1284 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); |
1285 | } | |
1286 | ||
7d0d0df0 S |
1287 | ENABLE_REGWRITE_BUFFER(ah); |
1288 | ||
9a658d2b LR |
1289 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1290 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1291 | udelay(10); | |
1292 | } | |
1293 | ||
f1dc5600 S |
1294 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
1295 | AR_RTC_FORCE_WAKE_ON_INT); | |
1296 | ||
1297 | if (AR_SREV_9100(ah)) { | |
1298 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | | |
1299 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; | |
1300 | } else { | |
1301 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
a37a9910 FF |
1302 | if (AR_SREV_9340(ah)) |
1303 | tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; | |
1304 | else | |
1305 | tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | | |
1306 | AR_INTR_SYNC_RADM_CPL_TIMEOUT; | |
1307 | ||
1308 | if (tmpReg) { | |
42d5bc3f | 1309 | u32 val; |
f1dc5600 | 1310 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
42d5bc3f LR |
1311 | |
1312 | val = AR_RC_HOSTIF; | |
1313 | if (!AR_SREV_9300_20_OR_LATER(ah)) | |
1314 | val |= AR_RC_AHB; | |
1315 | REG_WRITE(ah, AR_RC, val); | |
1316 | ||
1317 | } else if (!AR_SREV_9300_20_OR_LATER(ah)) | |
f1dc5600 | 1318 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
f1dc5600 S |
1319 | |
1320 | rst_flags = AR_RTC_RC_MAC_WARM; | |
1321 | if (type == ATH9K_RESET_COLD) | |
1322 | rst_flags |= AR_RTC_RC_MAC_COLD; | |
1323 | } | |
1324 | ||
7d95847c | 1325 | if (AR_SREV_9330(ah)) { |
d7df7a55 SM |
1326 | if (!ath9k_hw_ar9330_reset_war(ah, type)) |
1327 | return false; | |
7d95847c GJ |
1328 | } |
1329 | ||
3863495b | 1330 | if (ath9k_hw_mci_is_enabled(ah)) |
506847ad | 1331 | ar9003_mci_check_gpm_offset(ah); |
3863495b | 1332 | |
d03a66c1 | 1333 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
7d0d0df0 S |
1334 | |
1335 | REGWRITE_BUFFER_FLUSH(ah); | |
7d0d0df0 | 1336 | |
4dc78c43 SM |
1337 | if (AR_SREV_9300_20_OR_LATER(ah)) |
1338 | udelay(50); | |
1339 | else if (AR_SREV_9100(ah)) | |
3683a07b | 1340 | mdelay(10); |
4dc78c43 SM |
1341 | else |
1342 | udelay(100); | |
f1dc5600 | 1343 | |
d03a66c1 | 1344 | REG_WRITE(ah, AR_RTC_RC, 0); |
0caa7b14 | 1345 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
d2182b69 | 1346 | ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); |
f1dc5600 S |
1347 | return false; |
1348 | } | |
1349 | ||
1350 | if (!AR_SREV_9100(ah)) | |
1351 | REG_WRITE(ah, AR_RC, 0); | |
1352 | ||
f1dc5600 S |
1353 | if (AR_SREV_9100(ah)) |
1354 | udelay(50); | |
1355 | ||
1356 | return true; | |
1357 | } | |
1358 | ||
cbe61d8a | 1359 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
f1dc5600 | 1360 | { |
7d0d0df0 S |
1361 | ENABLE_REGWRITE_BUFFER(ah); |
1362 | ||
9a658d2b LR |
1363 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1364 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1365 | udelay(10); | |
1366 | } | |
1367 | ||
f1dc5600 S |
1368 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
1369 | AR_RTC_FORCE_WAKE_ON_INT); | |
1370 | ||
42d5bc3f | 1371 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
1c29ce67 VT |
1372 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
1373 | ||
d03a66c1 | 1374 | REG_WRITE(ah, AR_RTC_RESET, 0); |
1c29ce67 | 1375 | |
7d0d0df0 | 1376 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1377 | |
afe36533 | 1378 | udelay(2); |
84e2169b SB |
1379 | |
1380 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) | |
1c29ce67 VT |
1381 | REG_WRITE(ah, AR_RC, 0); |
1382 | ||
d03a66c1 | 1383 | REG_WRITE(ah, AR_RTC_RESET, 1); |
f1dc5600 S |
1384 | |
1385 | if (!ath9k_hw_wait(ah, | |
1386 | AR_RTC_STATUS, | |
1387 | AR_RTC_STATUS_M, | |
0caa7b14 S |
1388 | AR_RTC_STATUS_ON, |
1389 | AH_WAIT_TIMEOUT)) { | |
d2182b69 | 1390 | ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); |
f1dc5600 | 1391 | return false; |
f078f209 LR |
1392 | } |
1393 | ||
f1dc5600 S |
1394 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); |
1395 | } | |
1396 | ||
cbe61d8a | 1397 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
f1dc5600 | 1398 | { |
7a9233ff | 1399 | bool ret = false; |
2577c6e8 | 1400 | |
9a658d2b LR |
1401 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1402 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1403 | udelay(10); | |
1404 | } | |
1405 | ||
f1dc5600 S |
1406 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
1407 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); | |
1408 | ||
ceb26a60 FF |
1409 | if (!ah->reset_power_on) |
1410 | type = ATH9K_RESET_POWER_ON; | |
1411 | ||
f1dc5600 S |
1412 | switch (type) { |
1413 | case ATH9K_RESET_POWER_ON: | |
7a9233ff | 1414 | ret = ath9k_hw_set_reset_power_on(ah); |
da8fb123 | 1415 | if (ret) |
ceb26a60 | 1416 | ah->reset_power_on = true; |
7a9233ff | 1417 | break; |
f1dc5600 S |
1418 | case ATH9K_RESET_WARM: |
1419 | case ATH9K_RESET_COLD: | |
7a9233ff MSS |
1420 | ret = ath9k_hw_set_reset(ah, type); |
1421 | break; | |
f1dc5600 | 1422 | default: |
7a9233ff | 1423 | break; |
f1dc5600 | 1424 | } |
7a9233ff | 1425 | |
7a9233ff | 1426 | return ret; |
f078f209 LR |
1427 | } |
1428 | ||
cbe61d8a | 1429 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
f1dc5600 | 1430 | struct ath9k_channel *chan) |
f078f209 | 1431 | { |
9c083af8 FF |
1432 | int reset_type = ATH9K_RESET_WARM; |
1433 | ||
1434 | if (AR_SREV_9280(ah)) { | |
1435 | if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) | |
1436 | reset_type = ATH9K_RESET_POWER_ON; | |
1437 | else | |
1438 | reset_type = ATH9K_RESET_COLD; | |
3412f2f0 FF |
1439 | } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || |
1440 | (REG_READ(ah, AR_CR) & AR_CR_RXE)) | |
1441 | reset_type = ATH9K_RESET_COLD; | |
9c083af8 FF |
1442 | |
1443 | if (!ath9k_hw_set_reset_reg(ah, reset_type)) | |
f1dc5600 | 1444 | return false; |
f078f209 | 1445 | |
9ecdef4b | 1446 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 1447 | return false; |
f078f209 | 1448 | |
2660b81a | 1449 | ah->chip_fullsleep = false; |
bfc441a4 FF |
1450 | |
1451 | if (AR_SREV_9330(ah)) | |
1452 | ar9003_hw_internal_regulator_apply(ah); | |
f1dc5600 | 1453 | ath9k_hw_init_pll(ah, chan); |
f078f209 | 1454 | |
f1dc5600 | 1455 | return true; |
f078f209 LR |
1456 | } |
1457 | ||
cbe61d8a | 1458 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
25c56eec | 1459 | struct ath9k_channel *chan) |
f078f209 | 1460 | { |
c46917bb | 1461 | struct ath_common *common = ath9k_hw_common(ah); |
b840cffe SM |
1462 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
1463 | bool band_switch = false, mode_diff = false; | |
70e89a71 | 1464 | u8 ini_reloaded = 0; |
8fe65368 | 1465 | u32 qnum; |
0a3b7bac | 1466 | int r; |
5f0c04ea | 1467 | |
b840cffe | 1468 | if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { |
af02efb3 FF |
1469 | u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; |
1470 | band_switch = !!(flags_diff & CHANNEL_5GHZ); | |
1471 | mode_diff = !!(flags_diff & ~CHANNEL_HT); | |
b840cffe | 1472 | } |
f078f209 LR |
1473 | |
1474 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { | |
1475 | if (ath9k_hw_numtxpending(ah, qnum)) { | |
d2182b69 | 1476 | ath_dbg(common, QUEUE, |
226afe68 | 1477 | "Transmit frames pending on queue %d\n", qnum); |
f078f209 LR |
1478 | return false; |
1479 | } | |
1480 | } | |
1481 | ||
8fe65368 | 1482 | if (!ath9k_hw_rfbus_req(ah)) { |
3800276a | 1483 | ath_err(common, "Could not kill baseband RX\n"); |
f078f209 LR |
1484 | return false; |
1485 | } | |
1486 | ||
b840cffe | 1487 | if (band_switch || mode_diff) { |
5f0c04ea RM |
1488 | ath9k_hw_mark_phy_inactive(ah); |
1489 | udelay(5); | |
1490 | ||
5f35c0fa SM |
1491 | if (band_switch) |
1492 | ath9k_hw_init_pll(ah, chan); | |
5f0c04ea RM |
1493 | |
1494 | if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { | |
1495 | ath_err(common, "Failed to do fast channel change\n"); | |
1496 | return false; | |
1497 | } | |
1498 | } | |
1499 | ||
8fe65368 | 1500 | ath9k_hw_set_channel_regs(ah, chan); |
f078f209 | 1501 | |
8fe65368 | 1502 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac | 1503 | if (r) { |
3800276a | 1504 | ath_err(common, "Failed to set channel\n"); |
0a3b7bac | 1505 | return false; |
f078f209 | 1506 | } |
dfdac8ac | 1507 | ath9k_hw_set_clockrate(ah); |
64ea57d0 | 1508 | ath9k_hw_apply_txpower(ah, chan, false); |
f078f209 | 1509 | |
81c507a8 | 1510 | ath9k_hw_set_delta_slope(ah, chan); |
8fe65368 | 1511 | ath9k_hw_spur_mitigate_freq(ah, chan); |
f1dc5600 | 1512 | |
70e89a71 SM |
1513 | if (band_switch || ini_reloaded) |
1514 | ah->eep_ops->set_board_values(ah, chan); | |
5f0c04ea | 1515 | |
70e89a71 SM |
1516 | ath9k_hw_init_bb(ah, chan); |
1517 | ath9k_hw_rfbus_done(ah); | |
5f0c04ea | 1518 | |
70e89a71 SM |
1519 | if (band_switch || ini_reloaded) { |
1520 | ah->ah_flags |= AH_FASTCC; | |
1521 | ath9k_hw_init_cal(ah, chan); | |
a126ff51 | 1522 | ah->ah_flags &= ~AH_FASTCC; |
5f0c04ea RM |
1523 | } |
1524 | ||
f1dc5600 S |
1525 | return true; |
1526 | } | |
1527 | ||
691680b8 FF |
1528 | static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) |
1529 | { | |
1530 | u32 gpio_mask = ah->gpio_mask; | |
1531 | int i; | |
1532 | ||
1533 | for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { | |
1534 | if (!(gpio_mask & 1)) | |
1535 | continue; | |
1536 | ||
1537 | ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
1538 | ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); | |
1539 | } | |
1540 | } | |
1541 | ||
1e516ca7 SM |
1542 | void ath9k_hw_check_nav(struct ath_hw *ah) |
1543 | { | |
1544 | struct ath_common *common = ath9k_hw_common(ah); | |
1545 | u32 val; | |
1546 | ||
1547 | val = REG_READ(ah, AR_NAV); | |
1548 | if (val != 0xdeadbeef && val > 0x7fff) { | |
1549 | ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); | |
1550 | REG_WRITE(ah, AR_NAV, 0); | |
1551 | } | |
1552 | } | |
1553 | EXPORT_SYMBOL(ath9k_hw_check_nav); | |
1554 | ||
c9c99e5e | 1555 | bool ath9k_hw_check_alive(struct ath_hw *ah) |
3b319aae | 1556 | { |
c9c99e5e | 1557 | int count = 50; |
d31a36a6 | 1558 | u32 reg, last_val; |
c9c99e5e | 1559 | |
01e18918 RM |
1560 | if (AR_SREV_9300(ah)) |
1561 | return !ath9k_hw_detect_mac_hang(ah); | |
1562 | ||
e17f83ea | 1563 | if (AR_SREV_9285_12_OR_LATER(ah)) |
c9c99e5e FF |
1564 | return true; |
1565 | ||
d31a36a6 | 1566 | last_val = REG_READ(ah, AR_OBS_BUS_1); |
c9c99e5e FF |
1567 | do { |
1568 | reg = REG_READ(ah, AR_OBS_BUS_1); | |
d31a36a6 FF |
1569 | if (reg != last_val) |
1570 | return true; | |
3b319aae | 1571 | |
105ff411 | 1572 | udelay(1); |
d31a36a6 | 1573 | last_val = reg; |
c9c99e5e FF |
1574 | if ((reg & 0x7E7FFFEF) == 0x00702400) |
1575 | continue; | |
1576 | ||
1577 | switch (reg & 0x7E000B00) { | |
1578 | case 0x1E000000: | |
1579 | case 0x52000B00: | |
1580 | case 0x18000B00: | |
1581 | continue; | |
1582 | default: | |
1583 | return true; | |
1584 | } | |
1585 | } while (count-- > 0); | |
3b319aae | 1586 | |
c9c99e5e | 1587 | return false; |
3b319aae | 1588 | } |
c9c99e5e | 1589 | EXPORT_SYMBOL(ath9k_hw_check_alive); |
3b319aae | 1590 | |
15d2b585 SM |
1591 | static void ath9k_hw_init_mfp(struct ath_hw *ah) |
1592 | { | |
1593 | /* Setup MFP options for CCMP */ | |
1594 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
1595 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt | |
1596 | * frames when constructing CCMP AAD. */ | |
1597 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, | |
1598 | 0xc7ff); | |
60fc4962 CYY |
1599 | if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) |
1600 | ah->sw_mgmt_crypto_tx = true; | |
1601 | else | |
1602 | ah->sw_mgmt_crypto_tx = false; | |
e6510b11 | 1603 | ah->sw_mgmt_crypto_rx = false; |
15d2b585 SM |
1604 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
1605 | /* Disable hardware crypto for management frames */ | |
1606 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, | |
1607 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); | |
1608 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, | |
1609 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); | |
e6510b11 CYY |
1610 | ah->sw_mgmt_crypto_tx = true; |
1611 | ah->sw_mgmt_crypto_rx = true; | |
15d2b585 | 1612 | } else { |
e6510b11 CYY |
1613 | ah->sw_mgmt_crypto_tx = true; |
1614 | ah->sw_mgmt_crypto_rx = true; | |
15d2b585 SM |
1615 | } |
1616 | } | |
1617 | ||
1618 | static void ath9k_hw_reset_opmode(struct ath_hw *ah, | |
1619 | u32 macStaId1, u32 saveDefAntenna) | |
1620 | { | |
1621 | struct ath_common *common = ath9k_hw_common(ah); | |
1622 | ||
1623 | ENABLE_REGWRITE_BUFFER(ah); | |
1624 | ||
ecbbed32 | 1625 | REG_RMW(ah, AR_STA_ID1, macStaId1 |
15d2b585 | 1626 | | AR_STA_ID1_RTS_USE_DEF |
ecbbed32 FF |
1627 | | ah->sta_id1_defaults, |
1628 | ~AR_STA_ID1_SADH_MASK); | |
15d2b585 SM |
1629 | ath_hw_setbssidmask(common); |
1630 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); | |
1631 | ath9k_hw_write_associd(ah); | |
1632 | REG_WRITE(ah, AR_ISR, ~0); | |
1633 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); | |
1634 | ||
1635 | REGWRITE_BUFFER_FLUSH(ah); | |
1636 | ||
1637 | ath9k_hw_set_operating_mode(ah, ah->opmode); | |
1638 | } | |
1639 | ||
1640 | static void ath9k_hw_init_queues(struct ath_hw *ah) | |
1641 | { | |
1642 | int i; | |
1643 | ||
1644 | ENABLE_REGWRITE_BUFFER(ah); | |
1645 | ||
1646 | for (i = 0; i < AR_NUM_DCU; i++) | |
1647 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); | |
1648 | ||
1649 | REGWRITE_BUFFER_FLUSH(ah); | |
1650 | ||
1651 | ah->intr_txqs = 0; | |
1652 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1653 | ath9k_hw_resettxqueue(ah, i); | |
1654 | } | |
1655 | ||
1656 | /* | |
1657 | * For big endian systems turn on swapping for descriptors | |
1658 | */ | |
1659 | static void ath9k_hw_init_desc(struct ath_hw *ah) | |
1660 | { | |
1661 | struct ath_common *common = ath9k_hw_common(ah); | |
1662 | ||
1663 | if (AR_SREV_9100(ah)) { | |
1664 | u32 mask; | |
1665 | mask = REG_READ(ah, AR_CFG); | |
1666 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { | |
1667 | ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", | |
1668 | mask); | |
1669 | } else { | |
1670 | mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; | |
1671 | REG_WRITE(ah, AR_CFG, mask); | |
1672 | ath_dbg(common, RESET, "Setting CFG 0x%x\n", | |
1673 | REG_READ(ah, AR_CFG)); | |
1674 | } | |
1675 | } else { | |
1676 | if (common->bus_ops->ath_bus_type == ATH_USB) { | |
1677 | /* Configure AR9271 target WLAN */ | |
1678 | if (AR_SREV_9271(ah)) | |
1679 | REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); | |
1680 | else | |
1681 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
1682 | } | |
1683 | #ifdef __BIG_ENDIAN | |
1684 | else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || | |
ede6a5e7 MP |
1685 | AR_SREV_9550(ah) || AR_SREV_9531(ah) || |
1686 | AR_SREV_9561(ah)) | |
15d2b585 SM |
1687 | REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); |
1688 | else | |
1689 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
1690 | #endif | |
1691 | } | |
1692 | } | |
1693 | ||
caed6579 SM |
1694 | /* |
1695 | * Fast channel change: | |
1696 | * (Change synthesizer based on channel freq without resetting chip) | |
caed6579 SM |
1697 | */ |
1698 | static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) | |
1699 | { | |
1700 | struct ath_common *common = ath9k_hw_common(ah); | |
b840cffe | 1701 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
caed6579 SM |
1702 | int ret; |
1703 | ||
1704 | if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) | |
1705 | goto fail; | |
1706 | ||
1707 | if (ah->chip_fullsleep) | |
1708 | goto fail; | |
1709 | ||
1710 | if (!ah->curchan) | |
1711 | goto fail; | |
1712 | ||
1713 | if (chan->channel == ah->curchan->channel) | |
1714 | goto fail; | |
1715 | ||
feb7bc99 FF |
1716 | if ((ah->curchan->channelFlags | chan->channelFlags) & |
1717 | (CHANNEL_HALF | CHANNEL_QUARTER)) | |
1718 | goto fail; | |
1719 | ||
b840cffe | 1720 | /* |
6b21fd20 | 1721 | * If cross-band fcc is not supoprted, bail out if channelFlags differ. |
b840cffe | 1722 | */ |
6b21fd20 | 1723 | if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && |
af02efb3 | 1724 | ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) |
6b21fd20 | 1725 | goto fail; |
caed6579 SM |
1726 | |
1727 | if (!ath9k_hw_check_alive(ah)) | |
1728 | goto fail; | |
1729 | ||
1730 | /* | |
1731 | * For AR9462, make sure that calibration data for | |
1732 | * re-using are present. | |
1733 | */ | |
8a90555f | 1734 | if (AR_SREV_9462(ah) && (ah->caldata && |
4b9b42bf SM |
1735 | (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || |
1736 | !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || | |
1737 | !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) | |
caed6579 SM |
1738 | goto fail; |
1739 | ||
1740 | ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", | |
1741 | ah->curchan->channel, chan->channel); | |
1742 | ||
1743 | ret = ath9k_hw_channel_change(ah, chan); | |
1744 | if (!ret) | |
1745 | goto fail; | |
1746 | ||
5955b2b0 | 1747 | if (ath9k_hw_mci_is_enabled(ah)) |
1bde95fa | 1748 | ar9003_mci_2g5g_switch(ah, false); |
caed6579 | 1749 | |
88033318 RM |
1750 | ath9k_hw_loadnf(ah, ah->curchan); |
1751 | ath9k_hw_start_nfcal(ah, true); | |
1752 | ||
caed6579 SM |
1753 | if (AR_SREV_9271(ah)) |
1754 | ar9002_hw_load_ani_reg(ah, chan); | |
1755 | ||
1756 | return 0; | |
1757 | fail: | |
1758 | return -EINVAL; | |
1759 | } | |
1760 | ||
8d7e09dd FF |
1761 | u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur) |
1762 | { | |
1763 | struct timespec ts; | |
1764 | s64 usec; | |
1765 | ||
1766 | if (!cur) { | |
1767 | getrawmonotonic(&ts); | |
1768 | cur = &ts; | |
1769 | } | |
1770 | ||
1771 | usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; | |
1772 | usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; | |
1773 | ||
1774 | return (u32) usec; | |
1775 | } | |
1776 | EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); | |
1777 | ||
cbe61d8a | 1778 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
caed6579 | 1779 | struct ath9k_hw_cal_data *caldata, bool fastcc) |
f078f209 | 1780 | { |
1510718d | 1781 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1782 | u32 saveLedState; |
f078f209 LR |
1783 | u32 saveDefAntenna; |
1784 | u32 macStaId1; | |
46fe782c | 1785 | u64 tsf = 0; |
09d8e315 | 1786 | s64 usec = 0; |
15d2b585 | 1787 | int r; |
caed6579 | 1788 | bool start_mci_reset = false; |
63d32967 MSS |
1789 | bool save_fullsleep = ah->chip_fullsleep; |
1790 | ||
5955b2b0 | 1791 | if (ath9k_hw_mci_is_enabled(ah)) { |
528e5d36 SM |
1792 | start_mci_reset = ar9003_mci_start_reset(ah, chan); |
1793 | if (start_mci_reset) | |
1794 | return 0; | |
63d32967 MSS |
1795 | } |
1796 | ||
9ecdef4b | 1797 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
ae8d2858 | 1798 | return -EIO; |
f078f209 | 1799 | |
caed6579 SM |
1800 | if (ah->curchan && !ah->chip_fullsleep) |
1801 | ath9k_hw_getnf(ah, ah->curchan); | |
f078f209 | 1802 | |
20bd2a09 | 1803 | ah->caldata = caldata; |
fcb9a3de | 1804 | if (caldata && (chan->channel != caldata->channel || |
6b21fd20 | 1805 | chan->channelFlags != caldata->channelFlags)) { |
20bd2a09 FF |
1806 | /* Operating channel changed, reset channel calibration data */ |
1807 | memset(caldata, 0, sizeof(*caldata)); | |
1808 | ath9k_init_nfcal_hist_buffer(ah, chan); | |
51dea9be | 1809 | } else if (caldata) { |
4b9b42bf | 1810 | clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); |
20bd2a09 | 1811 | } |
5bc225ac | 1812 | ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); |
20bd2a09 | 1813 | |
caed6579 SM |
1814 | if (fastcc) { |
1815 | r = ath9k_hw_do_fastcc(ah, chan); | |
1816 | if (!r) | |
1817 | return r; | |
f078f209 LR |
1818 | } |
1819 | ||
5955b2b0 | 1820 | if (ath9k_hw_mci_is_enabled(ah)) |
528e5d36 | 1821 | ar9003_mci_stop_bt(ah, save_fullsleep); |
63d32967 | 1822 | |
f078f209 LR |
1823 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); |
1824 | if (saveDefAntenna == 0) | |
1825 | saveDefAntenna = 1; | |
1826 | ||
1827 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; | |
1828 | ||
09d8e315 FF |
1829 | /* Save TSF before chip reset, a cold reset clears it */ |
1830 | tsf = ath9k_hw_gettsf64(ah); | |
6438e0dd | 1831 | usec = ktime_to_us(ktime_get_raw()); |
46fe782c | 1832 | |
f078f209 LR |
1833 | saveLedState = REG_READ(ah, AR_CFG_LED) & |
1834 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | | |
1835 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); | |
1836 | ||
1837 | ath9k_hw_mark_phy_inactive(ah); | |
1838 | ||
45ef6a0b VT |
1839 | ah->paprd_table_write_done = false; |
1840 | ||
05020d23 | 1841 | /* Only required on the first reset */ |
d7e7d229 LR |
1842 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1843 | REG_WRITE(ah, | |
1844 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1845 | AR9271_RADIO_RF_RST); | |
1846 | udelay(50); | |
1847 | } | |
1848 | ||
f078f209 | 1849 | if (!ath9k_hw_chip_reset(ah, chan)) { |
3800276a | 1850 | ath_err(common, "Chip reset failed\n"); |
ae8d2858 | 1851 | return -EINVAL; |
f078f209 LR |
1852 | } |
1853 | ||
05020d23 | 1854 | /* Only required on the first reset */ |
d7e7d229 LR |
1855 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1856 | ah->htc_reset_init = false; | |
1857 | REG_WRITE(ah, | |
1858 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1859 | AR9271_GATE_MAC_CTL); | |
1860 | udelay(50); | |
1861 | } | |
1862 | ||
46fe782c | 1863 | /* Restore TSF */ |
6438e0dd | 1864 | usec = ktime_to_us(ktime_get_raw()) - usec; |
09d8e315 | 1865 | ath9k_hw_settsf64(ah, tsf + usec); |
46fe782c | 1866 | |
7a37081e | 1867 | if (AR_SREV_9280_20_OR_LATER(ah)) |
369391db | 1868 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); |
f078f209 | 1869 | |
e9141f71 S |
1870 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1871 | ar9002_hw_enable_async_fifo(ah); | |
1872 | ||
25c56eec | 1873 | r = ath9k_hw_process_ini(ah, chan); |
ae8d2858 LR |
1874 | if (r) |
1875 | return r; | |
f078f209 | 1876 | |
935d00cc LB |
1877 | ath9k_hw_set_rfmode(ah, chan); |
1878 | ||
5955b2b0 | 1879 | if (ath9k_hw_mci_is_enabled(ah)) |
63d32967 MSS |
1880 | ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); |
1881 | ||
f860d526 FF |
1882 | /* |
1883 | * Some AR91xx SoC devices frequently fail to accept TSF writes | |
1884 | * right after the chip reset. When that happens, write a new | |
1885 | * value after the initvals have been applied, with an offset | |
1886 | * based on measured time difference | |
1887 | */ | |
1888 | if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { | |
1889 | tsf += 1500; | |
1890 | ath9k_hw_settsf64(ah, tsf); | |
1891 | } | |
1892 | ||
15d2b585 | 1893 | ath9k_hw_init_mfp(ah); |
0ced0e17 | 1894 | |
81c507a8 | 1895 | ath9k_hw_set_delta_slope(ah, chan); |
8fe65368 | 1896 | ath9k_hw_spur_mitigate_freq(ah, chan); |
d6509151 | 1897 | ah->eep_ops->set_board_values(ah, chan); |
a7765828 | 1898 | |
15d2b585 | 1899 | ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); |
00e0003e | 1900 | |
8fe65368 | 1901 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac LR |
1902 | if (r) |
1903 | return r; | |
f078f209 | 1904 | |
dfdac8ac FF |
1905 | ath9k_hw_set_clockrate(ah); |
1906 | ||
15d2b585 | 1907 | ath9k_hw_init_queues(ah); |
2660b81a | 1908 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
e36b27af | 1909 | ath9k_hw_ani_cache_ini_regs(ah); |
f078f209 LR |
1910 | ath9k_hw_init_qos(ah); |
1911 | ||
2660b81a | 1912 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
55821324 | 1913 | ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); |
3b319aae | 1914 | |
0005baf4 | 1915 | ath9k_hw_init_global_settings(ah); |
f078f209 | 1916 | |
fe2b6afb FF |
1917 | if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { |
1918 | REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, | |
1919 | AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); | |
1920 | REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, | |
1921 | AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); | |
1922 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, | |
1923 | AR_PCU_MISC_MODE2_ENABLE_AGGWEP); | |
ac88b6ec VN |
1924 | } |
1925 | ||
ca7a4deb | 1926 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); |
f078f209 LR |
1927 | |
1928 | ath9k_hw_set_dma(ah); | |
1929 | ||
ed6ebd8b RM |
1930 | if (!ath9k_hw_mci_is_enabled(ah)) |
1931 | REG_WRITE(ah, AR_OBS, 8); | |
f078f209 | 1932 | |
0ce024cb | 1933 | if (ah->config.rx_intr_mitigation) { |
a64e1a45 SM |
1934 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); |
1935 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); | |
f078f209 LR |
1936 | } |
1937 | ||
7f62a136 VT |
1938 | if (ah->config.tx_intr_mitigation) { |
1939 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); | |
1940 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); | |
1941 | } | |
1942 | ||
f078f209 LR |
1943 | ath9k_hw_init_bb(ah, chan); |
1944 | ||
77a5a664 | 1945 | if (caldata) { |
4b9b42bf SM |
1946 | clear_bit(TXIQCAL_DONE, &caldata->cal_flags); |
1947 | clear_bit(TXCLCAL_DONE, &caldata->cal_flags); | |
77a5a664 | 1948 | } |
ae8d2858 | 1949 | if (!ath9k_hw_init_cal(ah, chan)) |
6badaaf7 | 1950 | return -EIO; |
f078f209 | 1951 | |
5955b2b0 | 1952 | if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) |
528e5d36 | 1953 | return -EIO; |
63d32967 | 1954 | |
7d0d0df0 | 1955 | ENABLE_REGWRITE_BUFFER(ah); |
f078f209 | 1956 | |
8fe65368 | 1957 | ath9k_hw_restore_chainmask(ah); |
f078f209 LR |
1958 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); |
1959 | ||
7d0d0df0 | 1960 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1961 | |
f4c34af4 SM |
1962 | ath9k_hw_gen_timer_start_tsf2(ah); |
1963 | ||
15d2b585 | 1964 | ath9k_hw_init_desc(ah); |
f078f209 | 1965 | |
dbccdd1d | 1966 | if (ath9k_hw_btcoex_is_enabled(ah)) |
42cc41ed VT |
1967 | ath9k_hw_btcoex_enable(ah); |
1968 | ||
5955b2b0 | 1969 | if (ath9k_hw_mci_is_enabled(ah)) |
528e5d36 | 1970 | ar9003_mci_check_bt(ah); |
63d32967 | 1971 | |
7b89fccf FF |
1972 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1973 | ath9k_hw_loadnf(ah, chan); | |
1974 | ath9k_hw_start_nfcal(ah, true); | |
1975 | } | |
1fe860ed | 1976 | |
a7abaf7d | 1977 | if (AR_SREV_9300_20_OR_LATER(ah)) |
aea702b7 | 1978 | ar9003_hw_bb_watchdog_config(ah); |
a7abaf7d SM |
1979 | |
1980 | if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) | |
51ac8cbb | 1981 | ar9003_hw_disable_phy_restart(ah); |
51ac8cbb | 1982 | |
691680b8 FF |
1983 | ath9k_hw_apply_gpio_override(ah); |
1984 | ||
7bdea96a | 1985 | if (AR_SREV_9565(ah) && common->bt_ant_diversity) |
362cd03f SM |
1986 | REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); |
1987 | ||
4307b0fe LB |
1988 | if (ah->hw->conf.radar_enabled) { |
1989 | /* set HW specific DFS configuration */ | |
7a0a260a | 1990 | ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); |
4307b0fe LB |
1991 | ath9k_hw_set_radar_params(ah); |
1992 | } | |
1993 | ||
ae8d2858 | 1994 | return 0; |
f078f209 | 1995 | } |
7322fd19 | 1996 | EXPORT_SYMBOL(ath9k_hw_reset); |
f078f209 | 1997 | |
f1dc5600 S |
1998 | /******************************/ |
1999 | /* Power Management (Chipset) */ | |
2000 | /******************************/ | |
2001 | ||
42d5bc3f LR |
2002 | /* |
2003 | * Notify Power Mgt is disabled in self-generated frames. | |
2004 | * If requested, force chip to sleep. | |
2005 | */ | |
31604cf0 | 2006 | static void ath9k_set_power_sleep(struct ath_hw *ah) |
f078f209 | 2007 | { |
f1dc5600 | 2008 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
2577c6e8 | 2009 | |
a4a2954f | 2010 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
153dccd4 RM |
2011 | REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); |
2012 | REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); | |
2013 | REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); | |
31604cf0 SM |
2014 | /* xxx Required for WLAN only case ? */ |
2015 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); | |
2016 | udelay(100); | |
2017 | } | |
2577c6e8 | 2018 | |
31604cf0 SM |
2019 | /* |
2020 | * Clear the RTC force wake bit to allow the | |
2021 | * mac to go to sleep. | |
2022 | */ | |
2023 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); | |
2024 | ||
153dccd4 | 2025 | if (ath9k_hw_mci_is_enabled(ah)) |
31604cf0 | 2026 | udelay(100); |
2577c6e8 | 2027 | |
31604cf0 SM |
2028 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
2029 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); | |
f078f209 | 2030 | |
31604cf0 SM |
2031 | /* Shutdown chip. Active low */ |
2032 | if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { | |
2033 | REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); | |
2034 | udelay(2); | |
f1dc5600 | 2035 | } |
9a658d2b LR |
2036 | |
2037 | /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ | |
a7322812 RW |
2038 | if (AR_SREV_9300_20_OR_LATER(ah)) |
2039 | REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); | |
f078f209 LR |
2040 | } |
2041 | ||
bbd79af5 LR |
2042 | /* |
2043 | * Notify Power Management is enabled in self-generating | |
2044 | * frames. If request, set power mode of chip to | |
2045 | * auto/normal. Duration in units of 128us (1/8 TU). | |
2046 | */ | |
31604cf0 | 2047 | static void ath9k_set_power_network_sleep(struct ath_hw *ah) |
f078f209 | 2048 | { |
31604cf0 | 2049 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
2577c6e8 | 2050 | |
f1dc5600 | 2051 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
f078f209 | 2052 | |
31604cf0 SM |
2053 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
2054 | /* Set WakeOnInterrupt bit; clear ForceWake bit */ | |
2055 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, | |
2056 | AR_RTC_FORCE_WAKE_ON_INT); | |
2057 | } else { | |
2577c6e8 | 2058 | |
31604cf0 SM |
2059 | /* When chip goes into network sleep, it could be waken |
2060 | * up by MCI_INT interrupt caused by BT's HW messages | |
2061 | * (LNA_xxx, CONT_xxx) which chould be in a very fast | |
2062 | * rate (~100us). This will cause chip to leave and | |
2063 | * re-enter network sleep mode frequently, which in | |
2064 | * consequence will have WLAN MCI HW to generate lots of | |
2065 | * SYS_WAKING and SYS_SLEEPING messages which will make | |
2066 | * BT CPU to busy to process. | |
2067 | */ | |
153dccd4 RM |
2068 | if (ath9k_hw_mci_is_enabled(ah)) |
2069 | REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, | |
2070 | AR_MCI_INTERRUPT_RX_HW_MSG_MASK); | |
31604cf0 SM |
2071 | /* |
2072 | * Clear the RTC force wake bit to allow the | |
2073 | * mac to go to sleep. | |
2074 | */ | |
153dccd4 | 2075 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); |
31604cf0 | 2076 | |
153dccd4 | 2077 | if (ath9k_hw_mci_is_enabled(ah)) |
31604cf0 | 2078 | udelay(30); |
f078f209 | 2079 | } |
9a658d2b LR |
2080 | |
2081 | /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ | |
2082 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
2083 | REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); | |
f078f209 LR |
2084 | } |
2085 | ||
31604cf0 | 2086 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah) |
f078f209 | 2087 | { |
f1dc5600 S |
2088 | u32 val; |
2089 | int i; | |
f078f209 | 2090 | |
9a658d2b LR |
2091 | /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ |
2092 | if (AR_SREV_9300_20_OR_LATER(ah)) { | |
2093 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
2094 | udelay(10); | |
2095 | } | |
2096 | ||
31604cf0 SM |
2097 | if ((REG_READ(ah, AR_RTC_STATUS) & |
2098 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { | |
2099 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { | |
2100 | return false; | |
f1dc5600 | 2101 | } |
31604cf0 SM |
2102 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
2103 | ath9k_hw_init_pll(ah, NULL); | |
2104 | } | |
2105 | if (AR_SREV_9100(ah)) | |
2106 | REG_SET_BIT(ah, AR_RTC_RESET, | |
2107 | AR_RTC_RESET_EN); | |
2108 | ||
2109 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, | |
2110 | AR_RTC_FORCE_WAKE_EN); | |
04575f21 | 2111 | if (AR_SREV_9100(ah)) |
3683a07b | 2112 | mdelay(10); |
04575f21 SM |
2113 | else |
2114 | udelay(50); | |
f078f209 | 2115 | |
31604cf0 SM |
2116 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
2117 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; | |
2118 | if (val == AR_RTC_STATUS_ON) | |
2119 | break; | |
2120 | udelay(50); | |
f1dc5600 S |
2121 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
2122 | AR_RTC_FORCE_WAKE_EN); | |
31604cf0 SM |
2123 | } |
2124 | if (i == 0) { | |
2125 | ath_err(ath9k_hw_common(ah), | |
2126 | "Failed to wakeup in %uus\n", | |
2127 | POWER_UP_TIME / 20); | |
2128 | return false; | |
f078f209 LR |
2129 | } |
2130 | ||
cdbe408d RM |
2131 | if (ath9k_hw_mci_is_enabled(ah)) |
2132 | ar9003_mci_set_power_awake(ah); | |
2133 | ||
f1dc5600 | 2134 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
f078f209 | 2135 | |
f1dc5600 | 2136 | return true; |
f078f209 LR |
2137 | } |
2138 | ||
9ecdef4b | 2139 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
f078f209 | 2140 | { |
c46917bb | 2141 | struct ath_common *common = ath9k_hw_common(ah); |
31604cf0 | 2142 | int status = true; |
f1dc5600 S |
2143 | static const char *modes[] = { |
2144 | "AWAKE", | |
2145 | "FULL-SLEEP", | |
2146 | "NETWORK SLEEP", | |
2147 | "UNDEFINED" | |
2148 | }; | |
f1dc5600 | 2149 | |
cbdec975 GJ |
2150 | if (ah->power_mode == mode) |
2151 | return status; | |
2152 | ||
d2182b69 | 2153 | ath_dbg(common, RESET, "%s -> %s\n", |
226afe68 | 2154 | modes[ah->power_mode], modes[mode]); |
f1dc5600 S |
2155 | |
2156 | switch (mode) { | |
2157 | case ATH9K_PM_AWAKE: | |
31604cf0 | 2158 | status = ath9k_hw_set_power_awake(ah); |
f1dc5600 S |
2159 | break; |
2160 | case ATH9K_PM_FULL_SLEEP: | |
5955b2b0 | 2161 | if (ath9k_hw_mci_is_enabled(ah)) |
d1ca8b8e | 2162 | ar9003_mci_set_full_sleep(ah); |
1010911e | 2163 | |
31604cf0 | 2164 | ath9k_set_power_sleep(ah); |
2660b81a | 2165 | ah->chip_fullsleep = true; |
f1dc5600 S |
2166 | break; |
2167 | case ATH9K_PM_NETWORK_SLEEP: | |
31604cf0 | 2168 | ath9k_set_power_network_sleep(ah); |
f1dc5600 | 2169 | break; |
f078f209 | 2170 | default: |
3800276a | 2171 | ath_err(common, "Unknown power mode %u\n", mode); |
f078f209 LR |
2172 | return false; |
2173 | } | |
2660b81a | 2174 | ah->power_mode = mode; |
f1dc5600 | 2175 | |
69f4aab1 LR |
2176 | /* |
2177 | * XXX: If this warning never comes up after a while then | |
2178 | * simply keep the ATH_DBG_WARN_ON_ONCE() but make | |
2179 | * ath9k_hw_setpower() return type void. | |
2180 | */ | |
97dcec57 SM |
2181 | |
2182 | if (!(ah->ah_flags & AH_UNPLUGGED)) | |
2183 | ATH_DBG_WARN_ON_ONCE(!status); | |
69f4aab1 | 2184 | |
f1dc5600 | 2185 | return status; |
f078f209 | 2186 | } |
7322fd19 | 2187 | EXPORT_SYMBOL(ath9k_hw_setpower); |
f078f209 | 2188 | |
f1dc5600 S |
2189 | /*******************/ |
2190 | /* Beacon Handling */ | |
2191 | /*******************/ | |
2192 | ||
cbe61d8a | 2193 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
f078f209 | 2194 | { |
f078f209 LR |
2195 | int flags = 0; |
2196 | ||
7d0d0df0 S |
2197 | ENABLE_REGWRITE_BUFFER(ah); |
2198 | ||
2660b81a | 2199 | switch (ah->opmode) { |
d97809db | 2200 | case NL80211_IFTYPE_ADHOC: |
f078f209 LR |
2201 | REG_SET_BIT(ah, AR_TXCFG, |
2202 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); | |
2664d666 | 2203 | case NL80211_IFTYPE_MESH_POINT: |
d97809db | 2204 | case NL80211_IFTYPE_AP: |
dd347f2f FF |
2205 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); |
2206 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - | |
2207 | TU_TO_USEC(ah->config.dma_beacon_response_time)); | |
2208 | REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - | |
2209 | TU_TO_USEC(ah->config.sw_beacon_response_time)); | |
f078f209 LR |
2210 | flags |= |
2211 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; | |
2212 | break; | |
d97809db | 2213 | default: |
d2182b69 JP |
2214 | ath_dbg(ath9k_hw_common(ah), BEACON, |
2215 | "%s: unsupported opmode: %d\n", __func__, ah->opmode); | |
d97809db CM |
2216 | return; |
2217 | break; | |
f078f209 LR |
2218 | } |
2219 | ||
dd347f2f FF |
2220 | REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); |
2221 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); | |
2222 | REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); | |
f078f209 | 2223 | |
7d0d0df0 | 2224 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 2225 | |
f078f209 LR |
2226 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); |
2227 | } | |
7322fd19 | 2228 | EXPORT_SYMBOL(ath9k_hw_beaconinit); |
f078f209 | 2229 | |
cbe61d8a | 2230 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
f1dc5600 | 2231 | const struct ath9k_beacon_state *bs) |
f078f209 LR |
2232 | { |
2233 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; | |
2660b81a | 2234 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
c46917bb | 2235 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 2236 | |
7d0d0df0 S |
2237 | ENABLE_REGWRITE_BUFFER(ah); |
2238 | ||
4ed15762 FF |
2239 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); |
2240 | REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); | |
2241 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); | |
f078f209 | 2242 | |
7d0d0df0 | 2243 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 2244 | |
f078f209 LR |
2245 | REG_RMW_FIELD(ah, AR_RSSI_THR, |
2246 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); | |
2247 | ||
f29f5c08 | 2248 | beaconintval = bs->bs_intval; |
f078f209 LR |
2249 | |
2250 | if (bs->bs_sleepduration > beaconintval) | |
2251 | beaconintval = bs->bs_sleepduration; | |
2252 | ||
2253 | dtimperiod = bs->bs_dtimperiod; | |
2254 | if (bs->bs_sleepduration > dtimperiod) | |
2255 | dtimperiod = bs->bs_sleepduration; | |
2256 | ||
2257 | if (beaconintval == dtimperiod) | |
2258 | nextTbtt = bs->bs_nextdtim; | |
2259 | else | |
2260 | nextTbtt = bs->bs_nexttbtt; | |
2261 | ||
d2182b69 JP |
2262 | ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
2263 | ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); | |
2264 | ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); | |
2265 | ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); | |
f078f209 | 2266 | |
7d0d0df0 S |
2267 | ENABLE_REGWRITE_BUFFER(ah); |
2268 | ||
4ed15762 FF |
2269 | REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); |
2270 | REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); | |
f078f209 | 2271 | |
f1dc5600 S |
2272 | REG_WRITE(ah, AR_SLEEP1, |
2273 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) | |
2274 | | AR_SLEEP1_ASSUME_DTIM); | |
f078f209 | 2275 | |
f1dc5600 S |
2276 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
2277 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); | |
2278 | else | |
2279 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; | |
f078f209 | 2280 | |
f1dc5600 S |
2281 | REG_WRITE(ah, AR_SLEEP2, |
2282 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); | |
f078f209 | 2283 | |
4ed15762 FF |
2284 | REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); |
2285 | REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); | |
f078f209 | 2286 | |
7d0d0df0 | 2287 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 2288 | |
f1dc5600 S |
2289 | REG_SET_BIT(ah, AR_TIMER_MODE, |
2290 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | | |
2291 | AR_DTIM_TIMER_EN); | |
f078f209 | 2292 | |
4af9cf4f S |
2293 | /* TSF Out of Range Threshold */ |
2294 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); | |
f078f209 | 2295 | } |
7322fd19 | 2296 | EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); |
f078f209 | 2297 | |
f1dc5600 S |
2298 | /*******************/ |
2299 | /* HW Capabilities */ | |
2300 | /*******************/ | |
2301 | ||
6054069a FF |
2302 | static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) |
2303 | { | |
2304 | eeprom_chainmask &= chip_chainmask; | |
2305 | if (eeprom_chainmask) | |
2306 | return eeprom_chainmask; | |
2307 | else | |
2308 | return chip_chainmask; | |
2309 | } | |
2310 | ||
9a66af33 ZK |
2311 | /** |
2312 | * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset | |
2313 | * @ah: the atheros hardware data structure | |
2314 | * | |
2315 | * We enable DFS support upstream on chipsets which have passed a series | |
2316 | * of tests. The testing requirements are going to be documented. Desired | |
2317 | * test requirements are documented at: | |
2318 | * | |
2319 | * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs | |
2320 | * | |
2321 | * Once a new chipset gets properly tested an individual commit can be used | |
2322 | * to document the testing for DFS for that chipset. | |
2323 | */ | |
2324 | static bool ath9k_hw_dfs_tested(struct ath_hw *ah) | |
2325 | { | |
2326 | ||
2327 | switch (ah->hw_version.macVersion) { | |
73e4937d ZK |
2328 | /* for temporary testing DFS with 9280 */ |
2329 | case AR_SREV_VERSION_9280: | |
9a66af33 ZK |
2330 | /* AR9580 will likely be our first target to get testing on */ |
2331 | case AR_SREV_VERSION_9580: | |
73e4937d | 2332 | return true; |
9a66af33 ZK |
2333 | default: |
2334 | return false; | |
2335 | } | |
2336 | } | |
2337 | ||
a9a29ce6 | 2338 | int ath9k_hw_fill_cap_info(struct ath_hw *ah) |
f078f209 | 2339 | { |
2660b81a | 2340 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
608b88cb | 2341 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
c46917bb | 2342 | struct ath_common *common = ath9k_hw_common(ah); |
608b88cb | 2343 | |
0ff2b5c0 | 2344 | u16 eeval; |
47c80de6 | 2345 | u8 ant_div_ctl1, tx_chainmask, rx_chainmask; |
f078f209 | 2346 | |
f74df6fb | 2347 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
608b88cb | 2348 | regulatory->current_rd = eeval; |
f078f209 | 2349 | |
2660b81a | 2350 | if (ah->opmode != NL80211_IFTYPE_AP && |
d535a42a | 2351 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
608b88cb LR |
2352 | if (regulatory->current_rd == 0x64 || |
2353 | regulatory->current_rd == 0x65) | |
2354 | regulatory->current_rd += 5; | |
2355 | else if (regulatory->current_rd == 0x41) | |
2356 | regulatory->current_rd = 0x43; | |
d2182b69 JP |
2357 | ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", |
2358 | regulatory->current_rd); | |
f1dc5600 | 2359 | } |
f078f209 | 2360 | |
f74df6fb | 2361 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
3468968e FF |
2362 | |
2363 | if (eeval & AR5416_OPFLAGS_11A) { | |
2364 | if (ah->disable_5ghz) | |
2365 | ath_warn(common, "disabling 5GHz band\n"); | |
2366 | else | |
2367 | pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; | |
a9a29ce6 GJ |
2368 | } |
2369 | ||
3468968e FF |
2370 | if (eeval & AR5416_OPFLAGS_11G) { |
2371 | if (ah->disable_2ghz) | |
2372 | ath_warn(common, "disabling 2GHz band\n"); | |
2373 | else | |
2374 | pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; | |
2375 | } | |
f078f209 | 2376 | |
3468968e FF |
2377 | if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { |
2378 | ath_err(common, "both bands are disabled\n"); | |
2379 | return -EINVAL; | |
2380 | } | |
f1dc5600 | 2381 | |
e41db61d SM |
2382 | if (AR_SREV_9485(ah) || |
2383 | AR_SREV_9285(ah) || | |
2384 | AR_SREV_9330(ah) || | |
2385 | AR_SREV_9565(ah)) | |
ee79ccd9 | 2386 | pCap->chip_chainmask = 1; |
6054069a | 2387 | else if (!AR_SREV_9280_20_OR_LATER(ah)) |
ee79ccd9 SM |
2388 | pCap->chip_chainmask = 7; |
2389 | else if (!AR_SREV_9300_20_OR_LATER(ah) || | |
2390 | AR_SREV_9340(ah) || | |
2391 | AR_SREV_9462(ah) || | |
2392 | AR_SREV_9531(ah)) | |
2393 | pCap->chip_chainmask = 3; | |
6054069a | 2394 | else |
ee79ccd9 | 2395 | pCap->chip_chainmask = 7; |
6054069a | 2396 | |
f74df6fb | 2397 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
d7e7d229 LR |
2398 | /* |
2399 | * For AR9271 we will temporarilly uses the rx chainmax as read from | |
2400 | * the EEPROM. | |
2401 | */ | |
8147f5de | 2402 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
d7e7d229 LR |
2403 | !(eeval & AR5416_OPFLAGS_11A) && |
2404 | !(AR_SREV_9271(ah))) | |
2405 | /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ | |
8147f5de | 2406 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; |
598cdd52 FF |
2407 | else if (AR_SREV_9100(ah)) |
2408 | pCap->rx_chainmask = 0x7; | |
8147f5de | 2409 | else |
d7e7d229 | 2410 | /* Use rx_chainmask from EEPROM. */ |
8147f5de | 2411 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); |
f078f209 | 2412 | |
ee79ccd9 SM |
2413 | pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask); |
2414 | pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask); | |
82b2d334 FF |
2415 | ah->txchainmask = pCap->tx_chainmask; |
2416 | ah->rxchainmask = pCap->rx_chainmask; | |
6054069a | 2417 | |
7a37081e | 2418 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
f078f209 | 2419 | |
02d2ebb2 FF |
2420 | /* enable key search for every frame in an aggregate */ |
2421 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
2422 | ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; | |
2423 | ||
ce2220d1 BR |
2424 | common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; |
2425 | ||
0db156e9 | 2426 | if (ah->hw_version.devid != AR2427_DEVID_PCIE) |
f1dc5600 S |
2427 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
2428 | else | |
2429 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; | |
f078f209 | 2430 | |
5b5fa355 S |
2431 | if (AR_SREV_9271(ah)) |
2432 | pCap->num_gpio_pins = AR9271_NUM_GPIO; | |
88c1f4f6 S |
2433 | else if (AR_DEVID_7010(ah)) |
2434 | pCap->num_gpio_pins = AR7010_NUM_GPIO; | |
6321eb09 MSS |
2435 | else if (AR_SREV_9300_20_OR_LATER(ah)) |
2436 | pCap->num_gpio_pins = AR9300_NUM_GPIO; | |
2437 | else if (AR_SREV_9287_11_OR_LATER(ah)) | |
2438 | pCap->num_gpio_pins = AR9287_NUM_GPIO; | |
e17f83ea | 2439 | else if (AR_SREV_9285_12_OR_LATER(ah)) |
cb33c412 | 2440 | pCap->num_gpio_pins = AR9285_NUM_GPIO; |
7a37081e | 2441 | else if (AR_SREV_9280_20_OR_LATER(ah)) |
f1dc5600 S |
2442 | pCap->num_gpio_pins = AR928X_NUM_GPIO; |
2443 | else | |
2444 | pCap->num_gpio_pins = AR_NUM_GPIO; | |
f078f209 | 2445 | |
1b2538b2 | 2446 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) |
f1dc5600 | 2447 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; |
1b2538b2 | 2448 | else |
f1dc5600 | 2449 | pCap->rts_aggr_limit = (8 * 1024); |
f078f209 | 2450 | |
74e13060 | 2451 | #ifdef CONFIG_ATH9K_RFKILL |
2660b81a S |
2452 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
2453 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { | |
2454 | ah->rfkill_gpio = | |
2455 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); | |
2456 | ah->rfkill_polarity = | |
2457 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); | |
f1dc5600 S |
2458 | |
2459 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; | |
f078f209 | 2460 | } |
f1dc5600 | 2461 | #endif |
d5d1154f | 2462 | if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) |
bde748a4 VN |
2463 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; |
2464 | else | |
2465 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; | |
f078f209 | 2466 | |
e7594072 | 2467 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
f1dc5600 S |
2468 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
2469 | else | |
2470 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; | |
f078f209 | 2471 | |
ceb26445 | 2472 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
784ad503 | 2473 | pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; |
ede6a5e7 MP |
2474 | if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && |
2475 | !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) | |
784ad503 VT |
2476 | pCap->hw_caps |= ATH9K_HW_CAP_LDPC; |
2477 | ||
ceb26445 VT |
2478 | pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; |
2479 | pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; | |
2480 | pCap->rx_status_len = sizeof(struct ar9003_rxs); | |
162c3be3 | 2481 | pCap->tx_desc_len = sizeof(struct ar9003_txc); |
5088c2f1 | 2482 | pCap->txs_len = sizeof(struct ar9003_txs); |
162c3be3 VT |
2483 | } else { |
2484 | pCap->tx_desc_len = sizeof(struct ath_desc); | |
a949b172 | 2485 | if (AR_SREV_9280_20(ah)) |
6b42e8d0 | 2486 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; |
ceb26445 | 2487 | } |
1adf02ff | 2488 | |
6c84ce08 VT |
2489 | if (AR_SREV_9300_20_OR_LATER(ah)) |
2490 | pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; | |
2491 | ||
ede6a5e7 MP |
2492 | if (AR_SREV_9561(ah)) |
2493 | ah->ent_mode = 0x3BDA000; | |
2494 | else if (AR_SREV_9300_20_OR_LATER(ah)) | |
6ee63f55 SB |
2495 | ah->ent_mode = REG_READ(ah, AR_ENT_OTP); |
2496 | ||
a42acef0 | 2497 | if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) |
6473d24d VT |
2498 | pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; |
2499 | ||
f85c3371 | 2500 | if (AR_SREV_9285(ah)) { |
754dc536 VT |
2501 | if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { |
2502 | ant_div_ctl1 = | |
2503 | ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); | |
f85c3371 | 2504 | if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { |
754dc536 | 2505 | pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; |
f85c3371 SM |
2506 | ath_info(common, "Enable LNA combining\n"); |
2507 | } | |
754dc536 | 2508 | } |
f85c3371 SM |
2509 | } |
2510 | ||
ea066d5a MSS |
2511 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
2512 | if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) | |
2513 | pCap->hw_caps |= ATH9K_HW_CAP_APM; | |
2514 | } | |
2515 | ||
06236e53 | 2516 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { |
21d2c63a | 2517 | ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); |
f85c3371 | 2518 | if ((ant_div_ctl1 >> 0x6) == 0x3) { |
21d2c63a | 2519 | pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; |
f85c3371 SM |
2520 | ath_info(common, "Enable LNA combining\n"); |
2521 | } | |
21d2c63a | 2522 | } |
754dc536 | 2523 | |
9a66af33 ZK |
2524 | if (ath9k_hw_dfs_tested(ah)) |
2525 | pCap->hw_caps |= ATH9K_HW_CAP_DFS; | |
2526 | ||
47c80de6 VT |
2527 | tx_chainmask = pCap->tx_chainmask; |
2528 | rx_chainmask = pCap->rx_chainmask; | |
2529 | while (tx_chainmask || rx_chainmask) { | |
2530 | if (tx_chainmask & BIT(0)) | |
2531 | pCap->max_txchains++; | |
2532 | if (rx_chainmask & BIT(0)) | |
2533 | pCap->max_rxchains++; | |
2534 | ||
2535 | tx_chainmask >>= 1; | |
2536 | rx_chainmask >>= 1; | |
2537 | } | |
2538 | ||
a4a2954f | 2539 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
3789d59c MSS |
2540 | if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) |
2541 | pCap->hw_caps |= ATH9K_HW_CAP_MCI; | |
2542 | ||
2b5e54e2 | 2543 | if (AR_SREV_9462_20_OR_LATER(ah)) |
3789d59c | 2544 | pCap->hw_caps |= ATH9K_HW_CAP_RTT; |
3789d59c MSS |
2545 | } |
2546 | ||
0f21ee8d SM |
2547 | if (AR_SREV_9300_20_OR_LATER(ah) && |
2548 | ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) | |
2549 | pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; | |
2550 | ||
12a44422 SM |
2551 | #ifdef CONFIG_ATH9K_WOW |
2552 | if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah)) | |
2553 | ah->wow.max_patterns = MAX_NUM_PATTERN; | |
2554 | else | |
2555 | ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; | |
2556 | #endif | |
2557 | ||
a9a29ce6 | 2558 | return 0; |
f078f209 LR |
2559 | } |
2560 | ||
f1dc5600 S |
2561 | /****************************/ |
2562 | /* GPIO / RFKILL / Antennae */ | |
2563 | /****************************/ | |
f078f209 | 2564 | |
cbe61d8a | 2565 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, |
f1dc5600 S |
2566 | u32 gpio, u32 type) |
2567 | { | |
2568 | int addr; | |
2569 | u32 gpio_shift, tmp; | |
f078f209 | 2570 | |
f1dc5600 S |
2571 | if (gpio > 11) |
2572 | addr = AR_GPIO_OUTPUT_MUX3; | |
2573 | else if (gpio > 5) | |
2574 | addr = AR_GPIO_OUTPUT_MUX2; | |
2575 | else | |
2576 | addr = AR_GPIO_OUTPUT_MUX1; | |
f078f209 | 2577 | |
f1dc5600 | 2578 | gpio_shift = (gpio % 6) * 5; |
f078f209 | 2579 | |
f1dc5600 S |
2580 | if (AR_SREV_9280_20_OR_LATER(ah) |
2581 | || (addr != AR_GPIO_OUTPUT_MUX1)) { | |
2582 | REG_RMW(ah, addr, (type << gpio_shift), | |
2583 | (0x1f << gpio_shift)); | |
f078f209 | 2584 | } else { |
f1dc5600 S |
2585 | tmp = REG_READ(ah, addr); |
2586 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); | |
2587 | tmp &= ~(0x1f << gpio_shift); | |
2588 | tmp |= (type << gpio_shift); | |
2589 | REG_WRITE(ah, addr, tmp); | |
f078f209 | 2590 | } |
f078f209 LR |
2591 | } |
2592 | ||
cbe61d8a | 2593 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) |
f078f209 | 2594 | { |
f1dc5600 | 2595 | u32 gpio_shift; |
f078f209 | 2596 | |
9680e8a3 | 2597 | BUG_ON(gpio >= ah->caps.num_gpio_pins); |
f078f209 | 2598 | |
88c1f4f6 S |
2599 | if (AR_DEVID_7010(ah)) { |
2600 | gpio_shift = gpio; | |
2601 | REG_RMW(ah, AR7010_GPIO_OE, | |
2602 | (AR7010_GPIO_OE_AS_INPUT << gpio_shift), | |
2603 | (AR7010_GPIO_OE_MASK << gpio_shift)); | |
2604 | return; | |
2605 | } | |
f078f209 | 2606 | |
88c1f4f6 | 2607 | gpio_shift = gpio << 1; |
f1dc5600 S |
2608 | REG_RMW(ah, |
2609 | AR_GPIO_OE_OUT, | |
2610 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), | |
2611 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 | 2612 | } |
7322fd19 | 2613 | EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); |
f078f209 | 2614 | |
cbe61d8a | 2615 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
f078f209 | 2616 | { |
cb33c412 SB |
2617 | #define MS_REG_READ(x, y) \ |
2618 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) | |
2619 | ||
2660b81a | 2620 | if (gpio >= ah->caps.num_gpio_pins) |
f1dc5600 | 2621 | return 0xffffffff; |
f078f209 | 2622 | |
88c1f4f6 S |
2623 | if (AR_DEVID_7010(ah)) { |
2624 | u32 val; | |
2625 | val = REG_READ(ah, AR7010_GPIO_IN); | |
2626 | return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; | |
2627 | } else if (AR_SREV_9300_20_OR_LATER(ah)) | |
9306990a VT |
2628 | return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & |
2629 | AR_GPIO_BIT(gpio)) != 0; | |
783dfca1 | 2630 | else if (AR_SREV_9271(ah)) |
5b5fa355 | 2631 | return MS_REG_READ(AR9271, gpio) != 0; |
a42acef0 | 2632 | else if (AR_SREV_9287_11_OR_LATER(ah)) |
ac88b6ec | 2633 | return MS_REG_READ(AR9287, gpio) != 0; |
e17f83ea | 2634 | else if (AR_SREV_9285_12_OR_LATER(ah)) |
cb33c412 | 2635 | return MS_REG_READ(AR9285, gpio) != 0; |
7a37081e | 2636 | else if (AR_SREV_9280_20_OR_LATER(ah)) |
cb33c412 SB |
2637 | return MS_REG_READ(AR928X, gpio) != 0; |
2638 | else | |
2639 | return MS_REG_READ(AR, gpio) != 0; | |
f078f209 | 2640 | } |
7322fd19 | 2641 | EXPORT_SYMBOL(ath9k_hw_gpio_get); |
f078f209 | 2642 | |
cbe61d8a | 2643 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
f1dc5600 | 2644 | u32 ah_signal_type) |
f078f209 | 2645 | { |
f1dc5600 | 2646 | u32 gpio_shift; |
f078f209 | 2647 | |
88c1f4f6 S |
2648 | if (AR_DEVID_7010(ah)) { |
2649 | gpio_shift = gpio; | |
2650 | REG_RMW(ah, AR7010_GPIO_OE, | |
2651 | (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), | |
2652 | (AR7010_GPIO_OE_MASK << gpio_shift)); | |
2653 | return; | |
2654 | } | |
f078f209 | 2655 | |
88c1f4f6 | 2656 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
f1dc5600 | 2657 | gpio_shift = 2 * gpio; |
f1dc5600 S |
2658 | REG_RMW(ah, |
2659 | AR_GPIO_OE_OUT, | |
2660 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), | |
2661 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 | 2662 | } |
7322fd19 | 2663 | EXPORT_SYMBOL(ath9k_hw_cfg_output); |
f078f209 | 2664 | |
cbe61d8a | 2665 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
f078f209 | 2666 | { |
88c1f4f6 S |
2667 | if (AR_DEVID_7010(ah)) { |
2668 | val = val ? 0 : 1; | |
2669 | REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), | |
2670 | AR_GPIO_BIT(gpio)); | |
2671 | return; | |
2672 | } | |
2673 | ||
5b5fa355 S |
2674 | if (AR_SREV_9271(ah)) |
2675 | val = ~val; | |
2676 | ||
f1dc5600 S |
2677 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
2678 | AR_GPIO_BIT(gpio)); | |
f078f209 | 2679 | } |
7322fd19 | 2680 | EXPORT_SYMBOL(ath9k_hw_set_gpio); |
f078f209 | 2681 | |
cbe61d8a | 2682 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
f078f209 | 2683 | { |
f1dc5600 | 2684 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
f078f209 | 2685 | } |
7322fd19 | 2686 | EXPORT_SYMBOL(ath9k_hw_setantenna); |
f078f209 | 2687 | |
f1dc5600 S |
2688 | /*********************/ |
2689 | /* General Operation */ | |
2690 | /*********************/ | |
2691 | ||
cbe61d8a | 2692 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
f078f209 | 2693 | { |
f1dc5600 S |
2694 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
2695 | u32 phybits = REG_READ(ah, AR_PHY_ERR); | |
f078f209 | 2696 | |
f1dc5600 S |
2697 | if (phybits & AR_PHY_ERR_RADAR) |
2698 | bits |= ATH9K_RX_FILTER_PHYRADAR; | |
2699 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) | |
2700 | bits |= ATH9K_RX_FILTER_PHYERR; | |
dc2222a8 | 2701 | |
f1dc5600 | 2702 | return bits; |
f078f209 | 2703 | } |
7322fd19 | 2704 | EXPORT_SYMBOL(ath9k_hw_getrxfilter); |
f078f209 | 2705 | |
cbe61d8a | 2706 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
f078f209 | 2707 | { |
f1dc5600 | 2708 | u32 phybits; |
f078f209 | 2709 | |
7d0d0df0 S |
2710 | ENABLE_REGWRITE_BUFFER(ah); |
2711 | ||
a4a2954f | 2712 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) |
2577c6e8 SB |
2713 | bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; |
2714 | ||
7ea310be S |
2715 | REG_WRITE(ah, AR_RX_FILTER, bits); |
2716 | ||
f1dc5600 S |
2717 | phybits = 0; |
2718 | if (bits & ATH9K_RX_FILTER_PHYRADAR) | |
2719 | phybits |= AR_PHY_ERR_RADAR; | |
2720 | if (bits & ATH9K_RX_FILTER_PHYERR) | |
2721 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; | |
2722 | REG_WRITE(ah, AR_PHY_ERR, phybits); | |
f078f209 | 2723 | |
f1dc5600 | 2724 | if (phybits) |
ca7a4deb | 2725 | REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); |
f1dc5600 | 2726 | else |
ca7a4deb | 2727 | REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); |
7d0d0df0 S |
2728 | |
2729 | REGWRITE_BUFFER_FLUSH(ah); | |
f1dc5600 | 2730 | } |
7322fd19 | 2731 | EXPORT_SYMBOL(ath9k_hw_setrxfilter); |
f078f209 | 2732 | |
cbe61d8a | 2733 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
f1dc5600 | 2734 | { |
99922a45 RM |
2735 | if (ath9k_hw_mci_is_enabled(ah)) |
2736 | ar9003_mci_bt_gain_ctrl(ah); | |
2737 | ||
63a75b91 SB |
2738 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
2739 | return false; | |
2740 | ||
2741 | ath9k_hw_init_pll(ah, NULL); | |
8efa7a81 | 2742 | ah->htc_reset_init = true; |
63a75b91 | 2743 | return true; |
f1dc5600 | 2744 | } |
7322fd19 | 2745 | EXPORT_SYMBOL(ath9k_hw_phy_disable); |
f078f209 | 2746 | |
cbe61d8a | 2747 | bool ath9k_hw_disable(struct ath_hw *ah) |
f1dc5600 | 2748 | { |
9ecdef4b | 2749 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 2750 | return false; |
f078f209 | 2751 | |
63a75b91 SB |
2752 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) |
2753 | return false; | |
2754 | ||
2755 | ath9k_hw_init_pll(ah, NULL); | |
2756 | return true; | |
f078f209 | 2757 | } |
7322fd19 | 2758 | EXPORT_SYMBOL(ath9k_hw_disable); |
f078f209 | 2759 | |
ca2c68cc FF |
2760 | static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) |
2761 | { | |
2762 | enum eeprom_param gain_param; | |
2763 | ||
2764 | if (IS_CHAN_2GHZ(chan)) | |
2765 | gain_param = EEP_ANTENNA_GAIN_2G; | |
2766 | else | |
2767 | gain_param = EEP_ANTENNA_GAIN_5G; | |
2768 | ||
2769 | return ah->eep_ops->get_eeprom(ah, gain_param); | |
2770 | } | |
2771 | ||
64ea57d0 GJ |
2772 | void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, |
2773 | bool test) | |
ca2c68cc FF |
2774 | { |
2775 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
2776 | struct ieee80211_channel *channel; | |
2777 | int chan_pwr, new_pwr, max_gain; | |
2778 | int ant_gain, ant_reduction = 0; | |
2779 | ||
2780 | if (!chan) | |
2781 | return; | |
2782 | ||
2783 | channel = chan->chan; | |
2784 | chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); | |
2785 | new_pwr = min_t(int, chan_pwr, reg->power_limit); | |
2786 | max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; | |
2787 | ||
2788 | ant_gain = get_antenna_gain(ah, chan); | |
2789 | if (ant_gain > max_gain) | |
2790 | ant_reduction = ant_gain - max_gain; | |
2791 | ||
2792 | ah->eep_ops->set_txpower(ah, chan, | |
2793 | ath9k_regd_get_ctl(reg, chan), | |
64ea57d0 | 2794 | ant_reduction, new_pwr, test); |
ca2c68cc FF |
2795 | } |
2796 | ||
de40f316 | 2797 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) |
f078f209 | 2798 | { |
ca2c68cc | 2799 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); |
2660b81a | 2800 | struct ath9k_channel *chan = ah->curchan; |
5f8e077c | 2801 | struct ieee80211_channel *channel = chan->chan; |
9c204b46 | 2802 | |
48ef5c42 | 2803 | reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); |
9c204b46 | 2804 | if (test) |
ca2c68cc | 2805 | channel->max_power = MAX_RATE_POWER / 2; |
f078f209 | 2806 | |
64ea57d0 | 2807 | ath9k_hw_apply_txpower(ah, chan, test); |
6f255425 | 2808 | |
ca2c68cc FF |
2809 | if (test) |
2810 | channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); | |
6f255425 | 2811 | } |
7322fd19 | 2812 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
6f255425 | 2813 | |
cbe61d8a | 2814 | void ath9k_hw_setopmode(struct ath_hw *ah) |
f078f209 | 2815 | { |
2660b81a | 2816 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
f078f209 | 2817 | } |
7322fd19 | 2818 | EXPORT_SYMBOL(ath9k_hw_setopmode); |
f078f209 | 2819 | |
cbe61d8a | 2820 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
f078f209 | 2821 | { |
f1dc5600 S |
2822 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
2823 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); | |
f078f209 | 2824 | } |
7322fd19 | 2825 | EXPORT_SYMBOL(ath9k_hw_setmcastfilter); |
f078f209 | 2826 | |
f2b2143e | 2827 | void ath9k_hw_write_associd(struct ath_hw *ah) |
f078f209 | 2828 | { |
1510718d LR |
2829 | struct ath_common *common = ath9k_hw_common(ah); |
2830 | ||
2831 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); | |
2832 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | | |
2833 | ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); | |
f078f209 | 2834 | } |
7322fd19 | 2835 | EXPORT_SYMBOL(ath9k_hw_write_associd); |
f078f209 | 2836 | |
1c0fc65e BP |
2837 | #define ATH9K_MAX_TSF_READ 10 |
2838 | ||
cbe61d8a | 2839 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
f078f209 | 2840 | { |
1c0fc65e BP |
2841 | u32 tsf_lower, tsf_upper1, tsf_upper2; |
2842 | int i; | |
2843 | ||
2844 | tsf_upper1 = REG_READ(ah, AR_TSF_U32); | |
2845 | for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { | |
2846 | tsf_lower = REG_READ(ah, AR_TSF_L32); | |
2847 | tsf_upper2 = REG_READ(ah, AR_TSF_U32); | |
2848 | if (tsf_upper2 == tsf_upper1) | |
2849 | break; | |
2850 | tsf_upper1 = tsf_upper2; | |
2851 | } | |
f078f209 | 2852 | |
1c0fc65e | 2853 | WARN_ON( i == ATH9K_MAX_TSF_READ ); |
f078f209 | 2854 | |
1c0fc65e | 2855 | return (((u64)tsf_upper1 << 32) | tsf_lower); |
f1dc5600 | 2856 | } |
7322fd19 | 2857 | EXPORT_SYMBOL(ath9k_hw_gettsf64); |
f078f209 | 2858 | |
cbe61d8a | 2859 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
27abe060 | 2860 | { |
27abe060 | 2861 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
b9a16197 | 2862 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
27abe060 | 2863 | } |
7322fd19 | 2864 | EXPORT_SYMBOL(ath9k_hw_settsf64); |
27abe060 | 2865 | |
cbe61d8a | 2866 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
f1dc5600 | 2867 | { |
f9b604f6 GJ |
2868 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
2869 | AH_TSF_WRITE_TIMEOUT)) | |
d2182b69 | 2870 | ath_dbg(ath9k_hw_common(ah), RESET, |
226afe68 | 2871 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); |
f9b604f6 | 2872 | |
f1dc5600 S |
2873 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
2874 | } | |
7322fd19 | 2875 | EXPORT_SYMBOL(ath9k_hw_reset_tsf); |
f078f209 | 2876 | |
60ca9f87 | 2877 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) |
f1dc5600 | 2878 | { |
60ca9f87 | 2879 | if (set) |
2660b81a | 2880 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
f1dc5600 | 2881 | else |
2660b81a | 2882 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
f1dc5600 | 2883 | } |
7322fd19 | 2884 | EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); |
f078f209 | 2885 | |
e4744ec7 | 2886 | void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) |
f1dc5600 S |
2887 | { |
2888 | u32 macmode; | |
2889 | ||
e4744ec7 | 2890 | if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) |
f1dc5600 S |
2891 | macmode = AR_2040_JOINED_RX_CLEAR; |
2892 | else | |
2893 | macmode = 0; | |
f078f209 | 2894 | |
f1dc5600 | 2895 | REG_WRITE(ah, AR_2040_MODE, macmode); |
f078f209 | 2896 | } |
ff155a45 VT |
2897 | |
2898 | /* HW Generic timers configuration */ | |
2899 | ||
2900 | static const struct ath_gen_timer_configuration gen_tmr_configuration[] = | |
2901 | { | |
2902 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2903 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2904 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2905 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2906 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2907 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2908 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2909 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2910 | {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, | |
2911 | {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, | |
2912 | AR_NDP2_TIMER_MODE, 0x0002}, | |
2913 | {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, | |
2914 | AR_NDP2_TIMER_MODE, 0x0004}, | |
2915 | {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, | |
2916 | AR_NDP2_TIMER_MODE, 0x0008}, | |
2917 | {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, | |
2918 | AR_NDP2_TIMER_MODE, 0x0010}, | |
2919 | {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, | |
2920 | AR_NDP2_TIMER_MODE, 0x0020}, | |
2921 | {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, | |
2922 | AR_NDP2_TIMER_MODE, 0x0040}, | |
2923 | {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, | |
2924 | AR_NDP2_TIMER_MODE, 0x0080} | |
2925 | }; | |
2926 | ||
2927 | /* HW generic timer primitives */ | |
2928 | ||
dd347f2f | 2929 | u32 ath9k_hw_gettsf32(struct ath_hw *ah) |
ff155a45 VT |
2930 | { |
2931 | return REG_READ(ah, AR_TSF_L32); | |
2932 | } | |
dd347f2f | 2933 | EXPORT_SYMBOL(ath9k_hw_gettsf32); |
ff155a45 | 2934 | |
f4c34af4 SM |
2935 | void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) |
2936 | { | |
2937 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2938 | ||
2939 | if (timer_table->tsf2_enabled) { | |
2940 | REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); | |
2941 | REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); | |
2942 | } | |
2943 | } | |
2944 | ||
ff155a45 VT |
2945 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, |
2946 | void (*trigger)(void *), | |
2947 | void (*overflow)(void *), | |
2948 | void *arg, | |
2949 | u8 timer_index) | |
2950 | { | |
2951 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2952 | struct ath_gen_timer *timer; | |
2953 | ||
c67ce339 | 2954 | if ((timer_index < AR_FIRST_NDP_TIMER) || |
f4c34af4 SM |
2955 | (timer_index >= ATH_MAX_GEN_TIMER)) |
2956 | return NULL; | |
2957 | ||
2958 | if ((timer_index > AR_FIRST_NDP_TIMER) && | |
2959 | !AR_SREV_9300_20_OR_LATER(ah)) | |
c67ce339 FF |
2960 | return NULL; |
2961 | ||
ff155a45 | 2962 | timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); |
14f8dc49 | 2963 | if (timer == NULL) |
ff155a45 | 2964 | return NULL; |
ff155a45 VT |
2965 | |
2966 | /* allocate a hardware generic timer slot */ | |
2967 | timer_table->timers[timer_index] = timer; | |
2968 | timer->index = timer_index; | |
2969 | timer->trigger = trigger; | |
2970 | timer->overflow = overflow; | |
2971 | timer->arg = arg; | |
2972 | ||
f4c34af4 SM |
2973 | if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) { |
2974 | timer_table->tsf2_enabled = true; | |
2975 | ath9k_hw_gen_timer_start_tsf2(ah); | |
2976 | } | |
2977 | ||
ff155a45 VT |
2978 | return timer; |
2979 | } | |
7322fd19 | 2980 | EXPORT_SYMBOL(ath_gen_timer_alloc); |
ff155a45 | 2981 | |
cd9bf689 LR |
2982 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
2983 | struct ath_gen_timer *timer, | |
c67ce339 | 2984 | u32 timer_next, |
cd9bf689 | 2985 | u32 timer_period) |
ff155a45 VT |
2986 | { |
2987 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
c67ce339 | 2988 | u32 mask = 0; |
788f6875 | 2989 | |
c67ce339 | 2990 | timer_table->timer_mask |= BIT(timer->index); |
ff155a45 | 2991 | |
ff155a45 VT |
2992 | /* |
2993 | * Program generic timer registers | |
2994 | */ | |
2995 | REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, | |
2996 | timer_next); | |
2997 | REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, | |
2998 | timer_period); | |
2999 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
3000 | gen_tmr_configuration[timer->index].mode_mask); | |
3001 | ||
a4a2954f | 3002 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
2577c6e8 | 3003 | /* |
423e38e8 | 3004 | * Starting from AR9462, each generic timer can select which tsf |
2577c6e8 SB |
3005 | * to use. But we still follow the old rule, 0 - 7 use tsf and |
3006 | * 8 - 15 use tsf2. | |
3007 | */ | |
3008 | if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) | |
3009 | REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, | |
3010 | (1 << timer->index)); | |
3011 | else | |
3012 | REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, | |
3013 | (1 << timer->index)); | |
3014 | } | |
3015 | ||
c67ce339 FF |
3016 | if (timer->trigger) |
3017 | mask |= SM(AR_GENTMR_BIT(timer->index), | |
3018 | AR_IMR_S5_GENTIMER_TRIG); | |
3019 | if (timer->overflow) | |
3020 | mask |= SM(AR_GENTMR_BIT(timer->index), | |
3021 | AR_IMR_S5_GENTIMER_THRESH); | |
3022 | ||
3023 | REG_SET_BIT(ah, AR_IMR_S5, mask); | |
3024 | ||
3025 | if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { | |
3026 | ah->imask |= ATH9K_INT_GENTIMER; | |
3027 | ath9k_hw_set_interrupts(ah); | |
3028 | } | |
ff155a45 | 3029 | } |
7322fd19 | 3030 | EXPORT_SYMBOL(ath9k_hw_gen_timer_start); |
ff155a45 | 3031 | |
cd9bf689 | 3032 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) |
ff155a45 VT |
3033 | { |
3034 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3035 | ||
ff155a45 VT |
3036 | /* Clear generic timer enable bits. */ |
3037 | REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
3038 | gen_tmr_configuration[timer->index].mode_mask); | |
3039 | ||
b7f59766 SM |
3040 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
3041 | /* | |
3042 | * Need to switch back to TSF if it was using TSF2. | |
3043 | */ | |
3044 | if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { | |
3045 | REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, | |
3046 | (1 << timer->index)); | |
3047 | } | |
3048 | } | |
3049 | ||
ff155a45 VT |
3050 | /* Disable both trigger and thresh interrupt masks */ |
3051 | REG_CLR_BIT(ah, AR_IMR_S5, | |
3052 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | |
3053 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); | |
3054 | ||
c67ce339 FF |
3055 | timer_table->timer_mask &= ~BIT(timer->index); |
3056 | ||
3057 | if (timer_table->timer_mask == 0) { | |
3058 | ah->imask &= ~ATH9K_INT_GENTIMER; | |
3059 | ath9k_hw_set_interrupts(ah); | |
3060 | } | |
ff155a45 | 3061 | } |
7322fd19 | 3062 | EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); |
ff155a45 VT |
3063 | |
3064 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) | |
3065 | { | |
3066 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3067 | ||
3068 | /* free the hardware generic timer slot */ | |
3069 | timer_table->timers[timer->index] = NULL; | |
3070 | kfree(timer); | |
3071 | } | |
7322fd19 | 3072 | EXPORT_SYMBOL(ath_gen_timer_free); |
ff155a45 VT |
3073 | |
3074 | /* | |
3075 | * Generic Timer Interrupts handling | |
3076 | */ | |
3077 | void ath_gen_timer_isr(struct ath_hw *ah) | |
3078 | { | |
3079 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3080 | struct ath_gen_timer *timer; | |
c67ce339 FF |
3081 | unsigned long trigger_mask, thresh_mask; |
3082 | unsigned int index; | |
ff155a45 VT |
3083 | |
3084 | /* get hardware generic timer interrupt status */ | |
3085 | trigger_mask = ah->intr_gen_timer_trigger; | |
3086 | thresh_mask = ah->intr_gen_timer_thresh; | |
c67ce339 FF |
3087 | trigger_mask &= timer_table->timer_mask; |
3088 | thresh_mask &= timer_table->timer_mask; | |
ff155a45 | 3089 | |
c67ce339 | 3090 | for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { |
ff155a45 | 3091 | timer = timer_table->timers[index]; |
c67ce339 FF |
3092 | if (!timer) |
3093 | continue; | |
3094 | if (!timer->overflow) | |
3095 | continue; | |
a6a172b2 FF |
3096 | |
3097 | trigger_mask &= ~BIT(index); | |
ff155a45 VT |
3098 | timer->overflow(timer->arg); |
3099 | } | |
3100 | ||
c67ce339 | 3101 | for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { |
ff155a45 | 3102 | timer = timer_table->timers[index]; |
c67ce339 FF |
3103 | if (!timer) |
3104 | continue; | |
3105 | if (!timer->trigger) | |
3106 | continue; | |
ff155a45 VT |
3107 | timer->trigger(timer->arg); |
3108 | } | |
3109 | } | |
7322fd19 | 3110 | EXPORT_SYMBOL(ath_gen_timer_isr); |
2da4f01a | 3111 | |
05020d23 S |
3112 | /********/ |
3113 | /* HTC */ | |
3114 | /********/ | |
3115 | ||
2da4f01a LR |
3116 | static struct { |
3117 | u32 version; | |
3118 | const char * name; | |
3119 | } ath_mac_bb_names[] = { | |
3120 | /* Devices with external radios */ | |
3121 | { AR_SREV_VERSION_5416_PCI, "5416" }, | |
3122 | { AR_SREV_VERSION_5416_PCIE, "5418" }, | |
3123 | { AR_SREV_VERSION_9100, "9100" }, | |
3124 | { AR_SREV_VERSION_9160, "9160" }, | |
3125 | /* Single-chip solutions */ | |
3126 | { AR_SREV_VERSION_9280, "9280" }, | |
3127 | { AR_SREV_VERSION_9285, "9285" }, | |
11158472 LR |
3128 | { AR_SREV_VERSION_9287, "9287" }, |
3129 | { AR_SREV_VERSION_9271, "9271" }, | |
ec83903e | 3130 | { AR_SREV_VERSION_9300, "9300" }, |
2c8e5937 | 3131 | { AR_SREV_VERSION_9330, "9330" }, |
397e5d5b | 3132 | { AR_SREV_VERSION_9340, "9340" }, |
8f06ca2c | 3133 | { AR_SREV_VERSION_9485, "9485" }, |
423e38e8 | 3134 | { AR_SREV_VERSION_9462, "9462" }, |
485124cb | 3135 | { AR_SREV_VERSION_9550, "9550" }, |
77fac465 | 3136 | { AR_SREV_VERSION_9565, "9565" }, |
c08148bb | 3137 | { AR_SREV_VERSION_9531, "9531" }, |
2da4f01a LR |
3138 | }; |
3139 | ||
3140 | /* For devices with external radios */ | |
3141 | static struct { | |
3142 | u16 version; | |
3143 | const char * name; | |
3144 | } ath_rf_names[] = { | |
3145 | { 0, "5133" }, | |
3146 | { AR_RAD5133_SREV_MAJOR, "5133" }, | |
3147 | { AR_RAD5122_SREV_MAJOR, "5122" }, | |
3148 | { AR_RAD2133_SREV_MAJOR, "2133" }, | |
3149 | { AR_RAD2122_SREV_MAJOR, "2122" } | |
3150 | }; | |
3151 | ||
3152 | /* | |
3153 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. | |
3154 | */ | |
f934c4d9 | 3155 | static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) |
2da4f01a LR |
3156 | { |
3157 | int i; | |
3158 | ||
3159 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { | |
3160 | if (ath_mac_bb_names[i].version == mac_bb_version) { | |
3161 | return ath_mac_bb_names[i].name; | |
3162 | } | |
3163 | } | |
3164 | ||
3165 | return "????"; | |
3166 | } | |
2da4f01a LR |
3167 | |
3168 | /* | |
3169 | * Return the RF name. "????" is returned if the RF is unknown. | |
3170 | * Used for devices with external radios. | |
3171 | */ | |
f934c4d9 | 3172 | static const char *ath9k_hw_rf_name(u16 rf_version) |
2da4f01a LR |
3173 | { |
3174 | int i; | |
3175 | ||
3176 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { | |
3177 | if (ath_rf_names[i].version == rf_version) { | |
3178 | return ath_rf_names[i].name; | |
3179 | } | |
3180 | } | |
3181 | ||
3182 | return "????"; | |
3183 | } | |
f934c4d9 LR |
3184 | |
3185 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) | |
3186 | { | |
3187 | int used; | |
3188 | ||
3189 | /* chipsets >= AR9280 are single-chip */ | |
7a37081e | 3190 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
5e88ba62 ZK |
3191 | used = scnprintf(hw_name, len, |
3192 | "Atheros AR%s Rev:%x", | |
3193 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
3194 | ah->hw_version.macRev); | |
f934c4d9 LR |
3195 | } |
3196 | else { | |
5e88ba62 ZK |
3197 | used = scnprintf(hw_name, len, |
3198 | "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", | |
3199 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
3200 | ah->hw_version.macRev, | |
3201 | ath9k_hw_rf_name((ah->hw_version.analog5GhzRev | |
3202 | & AR_RADIO_SREV_MAJOR)), | |
3203 | ah->hw_version.phyRev); | |
f934c4d9 LR |
3204 | } |
3205 | ||
3206 | hw_name[used] = '\0'; | |
3207 | } | |
3208 | EXPORT_SYMBOL(ath9k_hw_name); |