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airo: Fix integer overflow warning
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
af03abec 20#include "hw.h"
cfe8cba9 21#include "rc.h"
f078f209
LR		 22#include "initvals.h"
23
4febf7b8
LR		 24#define ATH9K_CLOCK_RATE_CCK 22
25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 27
cbe61d8a 28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
25c56eec 29static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
cbe61d8a 30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072 31 struct ar5416_eeprom_def *pEepData,
f1dc5600 32 u32 reg, u32 value);
f078f209 33
7322fd19
LR		 34MODULE_AUTHOR("Atheros Communications");
35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37MODULE_LICENSE("Dual BSD/GPL");
38
39static int __init ath9k_init(void)
40{
41 return 0;
42}
43module_init(ath9k_init);
44
45static void __exit ath9k_exit(void)
46{
47 return;
48}
49module_exit(ath9k_exit);
50
f1dc5600
S		 51/********************/
52/* Helper Functions */
53/********************/
f078f209 54
cbe61d8a 55static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
f1dc5600 56{
b002a4a9 57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 58
2660b81a 59 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 60 return clks / ATH9K_CLOCK_RATE_CCK;
61 if (conf->channel->band == IEEE80211_BAND_2GHZ)
62 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
cbe61d8a 63
4febf7b8 64 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 65}
f078f209 66
cbe61d8a 67static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
f1dc5600 68{
b002a4a9 69 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 70
4febf7b8 71 if (conf_is_ht40(conf))
f1dc5600
S		 72 return ath9k_hw_mac_usec(ah, clks) / 2;
73 else
74 return ath9k_hw_mac_usec(ah, clks);
75}
f078f209 76
cbe61d8a 77static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 78{
b002a4a9 79 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 80
2660b81a 81 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 82 return usecs *ATH9K_CLOCK_RATE_CCK;
83 if (conf->channel->band == IEEE80211_BAND_2GHZ)
84 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
85 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 86}
87
cbe61d8a 88static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 89{
b002a4a9 90 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 91
4febf7b8 92 if (conf_is_ht40(conf))
f1dc5600
S		 93 return ath9k_hw_mac_clks(ah, usecs) * 2;
94 else
95 return ath9k_hw_mac_clks(ah, usecs);
96}
f078f209 97
0caa7b14 98bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 99{
100 int i;
101
0caa7b14
S		 102 BUG_ON(timeout < AH_TIME_QUANTUM);
103
104 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 105 if ((REG_READ(ah, reg) & mask) == val)
106 return true;
107
108 udelay(AH_TIME_QUANTUM);
109 }
04bd4638 110
c46917bb
LR		 111 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
112 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
113 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 114
f1dc5600 115 return false;
f078f209 116}
7322fd19 117EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 118
119u32 ath9k_hw_reverse_bits(u32 val, u32 n)
120{
121 u32 retval;
122 int i;
123
124 for (i = 0, retval = 0; i < n; i++) {
125 retval = (retval << 1) | (val & 1);
126 val >>= 1;
127 }
128 return retval;
129}
130
cbe61d8a 131bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 132 u16 flags, u16 *low,
133 u16 *high)
f078f209 134{
2660b81a 135 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 136
f1dc5600
S		 137 if (flags & CHANNEL_5GHZ) {
138 *low = pCap->low_5ghz_chan;
139 *high = pCap->high_5ghz_chan;
140 return true;
f078f209 141 }
f1dc5600
S		 142 if ((flags & CHANNEL_2GHZ)) {
143 *low = pCap->low_2ghz_chan;
144 *high = pCap->high_2ghz_chan;
145 return true;
146 }
147 return false;
f078f209
LR		 148}
149
cbe61d8a 150u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 151 u8 phy, int kbps,
f1dc5600
S		 152 u32 frameLen, u16 rateix,
153 bool shortPreamble)
f078f209 154{
f1dc5600 155 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 156
f1dc5600
S		 157 if (kbps == 0)
158 return 0;
f078f209 159
545750d3 160 switch (phy) {
46d14a58 161 case WLAN_RC_PHY_CCK:
f1dc5600 162 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 163 if (shortPreamble)
f1dc5600
S		 164 phyTime >>= 1;
165 numBits = frameLen << 3;
166 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
167 break;
46d14a58 168 case WLAN_RC_PHY_OFDM:
2660b81a 169 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 170 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
171 numBits = OFDM_PLCP_BITS + (frameLen << 3);
172 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
173 txTime = OFDM_SIFS_TIME_QUARTER
174 + OFDM_PREAMBLE_TIME_QUARTER
175 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 176 } else if (ah->curchan &&
177 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 178 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
179 numBits = OFDM_PLCP_BITS + (frameLen << 3);
180 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
181 txTime = OFDM_SIFS_TIME_HALF +
182 OFDM_PREAMBLE_TIME_HALF
183 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
184 } else {
185 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
186 numBits = OFDM_PLCP_BITS + (frameLen << 3);
187 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
188 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
189 + (numSymbols * OFDM_SYMBOL_TIME);
190 }
191 break;
192 default:
c46917bb 193 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 194 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 195 txTime = 0;
196 break;
197 }
f078f209 198
f1dc5600
S		 199 return txTime;
200}
7322fd19 201EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 202
cbe61d8a 203void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 204 struct ath9k_channel *chan,
205 struct chan_centers *centers)
f078f209 206{
f1dc5600 207 int8_t extoff;
f078f209 208
f1dc5600
S		 209 if (!IS_CHAN_HT40(chan)) {
210 centers->ctl_center = centers->ext_center =
211 centers->synth_center = chan->channel;
212 return;
f078f209 213 }
f078f209 214
f1dc5600
S		 215 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
216 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
217 centers->synth_center =
218 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
219 extoff = 1;
220 } else {
221 centers->synth_center =
222 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
223 extoff = -1;
224 }
f078f209 225
f1dc5600
S		 226 centers->ctl_center =
227 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 228 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 229 centers->ext_center =
6420014c 230 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 231}
232
f1dc5600
S		 233/******************/
234/* Chip Revisions */
235/******************/
236
cbe61d8a 237static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 238{
f1dc5600 239 u32 val;
f078f209 240
f1dc5600 241 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 242
f1dc5600
S		 243 if (val == 0xFF) {
244 val = REG_READ(ah, AR_SREV);
d535a42a
S		 245 ah->hw_version.macVersion =
246 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
247 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 248 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 249 } else {
250 if (!AR_SREV_9100(ah))
d535a42a 251 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 252
d535a42a 253 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 254
d535a42a 255 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 256 ah->is_pciexpress = true;
f1dc5600 257 }
f078f209
LR		 258}
259
cbe61d8a 260static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 261{
f1dc5600
S		 262 u32 val;
263 int i;
f078f209 264
f1dc5600 265 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 266
f1dc5600
S		 267 for (i = 0; i < 8; i++)
268 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
269 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
270 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 271
f1dc5600 272 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 273}
274
f1dc5600
S		 275/************************************/
276/* HW Attach, Detach, Init Routines */
277/************************************/
278
cbe61d8a 279static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 280{
feed029c 281 if (AR_SREV_9100(ah))
f1dc5600 282 return;
f078f209 283
f1dc5600
S		 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 293
f1dc5600 294 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 295}
296
cbe61d8a 297static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 298{
c46917bb 299 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 300 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
301 u32 regHold[2];
302 u32 patternData[4] = { 0x55555555,
303 0xaaaaaaaa,
304 0x66666666,
305 0x99999999 };
306 int i, j;
f078f209 307
f1dc5600
S		 308 for (i = 0; i < 2; i++) {
309 u32 addr = regAddr[i];
310 u32 wrData, rdData;
f078f209 311
f1dc5600
S		 312 regHold[i] = REG_READ(ah, addr);
313 for (j = 0; j < 0x100; j++) {
314 wrData = (j << 16) | j;
315 REG_WRITE(ah, addr, wrData);
316 rdData = REG_READ(ah, addr);
317 if (rdData != wrData) {
c46917bb
LR		 318 ath_print(common, ATH_DBG_FATAL,
319 "address test failed "
320 "addr: 0x%08x - wr:0x%08x != "
321 "rd:0x%08x\n",
322 addr, wrData, rdData);
f1dc5600
S		 323 return false;
324 }
325 }
326 for (j = 0; j < 4; j++) {
327 wrData = patternData[j];
328 REG_WRITE(ah, addr, wrData);
329 rdData = REG_READ(ah, addr);
330 if (wrData != rdData) {
c46917bb
LR		 331 ath_print(common, ATH_DBG_FATAL,
332 "address test failed "
333 "addr: 0x%08x - wr:0x%08x != "
334 "rd:0x%08x\n",
335 addr, wrData, rdData);
f1dc5600
S		 336 return false;
337 }
f078f209 338 }
f1dc5600 339 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 340 }
f1dc5600 341 udelay(100);
cbe61d8a 342
f078f209
LR		 343 return true;
344}
345
f1dc5600 346static const char *ath9k_hw_devname(u16 devid)
f078f209 347{
f1dc5600
S		 348 switch (devid) {
349 case AR5416_DEVID_PCI:
f1dc5600 350 return "Atheros 5416";
392dff83
BP		 351 case AR5416_DEVID_PCIE:
352 return "Atheros 5418";
f1dc5600
S		 353 case AR9160_DEVID_PCI:
354 return "Atheros 9160";
0c1aa495
GJ		 355 case AR5416_AR9100_DEVID:
356 return "Atheros 9100";
f1dc5600
S		 357 case AR9280_DEVID_PCI:
358 case AR9280_DEVID_PCIE:
359 return "Atheros 9280";
e7594072
SB		 360 case AR9285_DEVID_PCIE:
361 return "Atheros 9285";
ac88b6ec
VN		 362 case AR5416_DEVID_AR9287_PCI:
363 case AR5416_DEVID_AR9287_PCIE:
364 return "Atheros 9287";
f078f209
LR		 365 }
366
f1dc5600
S		 367 return NULL;
368}
f078f209 369
b8b0f377 370static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 371{
372 int i;
f078f209 373
2660b81a
S		 374 ah->config.dma_beacon_response_time = 2;
375 ah->config.sw_beacon_response_time = 10;
376 ah->config.additional_swba_backoff = 0;
377 ah->config.ack_6mb = 0x0;
378 ah->config.cwm_ignore_extcca = 0;
379 ah->config.pcie_powersave_enable = 0;
2660b81a 380 ah->config.pcie_clock_req = 0;
2660b81a
S		 381 ah->config.pcie_waen = 0;
382 ah->config.analog_shiftreg = 1;
383 ah->config.ht_enable = 1;
384 ah->config.ofdm_trig_low = 200;
385 ah->config.ofdm_trig_high = 500;
386 ah->config.cck_trig_high = 200;
387 ah->config.cck_trig_low = 100;
388 ah->config.enable_ani = 1;
f078f209 389
f1dc5600 390 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 391 ah->config.spurchans[i][0] = AR_NO_SPUR;
392 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 393 }
394
0ef1f168 395 ah->config.intr_mitigation = true;
6158425b
LR		 396
397 /*
398 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
399 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
400 * This means we use it for all AR5416 devices, and the few
401 * minor PCI AR9280 devices out there.
402 *
403 * Serialization is required because these devices do not handle
404 * well the case of two concurrent reads/writes due to the latency
405 * involved. During one read/write another read/write can be issued
406 * on another CPU while the previous read/write may still be working
407 * on our hardware, if we hit this case the hardware poops in a loop.
408 * We prevent this by serializing reads and writes.
409 *
410 * This issue is not present on PCI-Express devices or pre-AR5416
411 * devices (legacy, 802.11abg).
412 */
413 if (num_possible_cpus() > 1)
2d6a5e95 414 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209 415}
7322fd19 416EXPORT_SYMBOL(ath9k_hw_init);
f078f209 417
50aca25b 418static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 419{
608b88cb
LR		 420 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
421
422 regulatory->country_code = CTRY_DEFAULT;
423 regulatory->power_limit = MAX_RATE_POWER;
424 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
425
d535a42a 426 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 427 ah->hw_version.subvendorid = 0;
f078f209
LR		 428
429 ah->ah_flags = 0;
8df5d1b7 430 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
d535a42a 431 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
f078f209
LR		 432 if (!AR_SREV_9100(ah))
433 ah->ah_flags = AH_USE_EEPROM;
434
2660b81a 435 ah->atim_window = 0;
2660b81a
S		 436 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
437 ah->beacon_interval = 100;
438 ah->enable_32kHz_clock = DONT_USE_32KHZ;
439 ah->slottime = (u32) -1;
440 ah->acktimeout = (u32) -1;
441 ah->ctstimeout = (u32) -1;
442 ah->globaltxtimeout = (u32) -1;
cbdec975 443 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 444}
445
cbe61d8a 446static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 447{
f1dc5600
S		 448 u32 val;
449
450 REG_WRITE(ah, AR_PHY(0), 0x00000007);
451
452 val = ath9k_hw_get_radiorev(ah);
453 switch (val & AR_RADIO_SREV_MAJOR) {
454 case 0:
455 val = AR_RAD5133_SREV_MAJOR;
456 break;
457 case AR_RAD5133_SREV_MAJOR:
458 case AR_RAD5122_SREV_MAJOR:
459 case AR_RAD2133_SREV_MAJOR:
460 case AR_RAD2122_SREV_MAJOR:
461 break;
f078f209 462 default:
c46917bb
LR		 463 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
464 "Radio Chip Rev 0x%02X not supported\n",
465 val & AR_RADIO_SREV_MAJOR);
f1dc5600 466 return -EOPNOTSUPP;
f078f209 467 }
f078f209 468
d535a42a 469 ah->hw_version.analog5GhzRev = val;
f078f209 470
f1dc5600 471 return 0;
f078f209
LR		 472}
473
cbe61d8a 474static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 475{
1510718d 476 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 477 u32 sum;
478 int i;
479 u16 eeval;
f078f209
LR		 480
481 sum = 0;
482 for (i = 0; i < 3; i++) {
f74df6fb 483 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 484 sum += eeval;
1510718d
LR		 485 common->macaddr[2 * i] = eeval >> 8;
486 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 487 }
d8baa939 488 if (sum == 0 || sum == 0xffff * 3)
f078f209 489 return -EADDRNOTAVAIL;
f078f209
LR		 490
491 return 0;
492}
493
cbe61d8a 494static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 495{
496 u32 rxgain_type;
9f804202 497
f74df6fb
S		 498 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
499 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 500
501 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 502 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 503 ar9280Modes_backoff_13db_rxgain_9280_2,
504 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
505 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 506 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 507 ar9280Modes_backoff_23db_rxgain_9280_2,
508 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
509 else
2660b81a 510 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 511 ar9280Modes_original_rxgain_9280_2,
512 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 513 } else {
2660b81a 514 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 515 ar9280Modes_original_rxgain_9280_2,
516 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 517 }
9f804202
SB		 518}
519
cbe61d8a 520static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 521{
522 u32 txgain_type;
9f804202 523
f74df6fb
S		 524 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
525 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 526
527 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 528 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 529 ar9280Modes_high_power_tx_gain_9280_2,
530 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
531 else
2660b81a 532 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 533 ar9280Modes_original_tx_gain_9280_2,
534 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 535 } else {
2660b81a 536 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 537 ar9280Modes_original_tx_gain_9280_2,
538 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 539 }
9f804202
SB		 540}
541
f637cfd6 542static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 543{
f1dc5600 544 int ecode;
f078f209 545
d8baa939 546 if (!ath9k_hw_chip_test(ah))
f1dc5600 547 return -ENODEV;
f078f209 548
f1dc5600
S		 549 ecode = ath9k_hw_rf_claim(ah);
550 if (ecode != 0)
f078f209 551 return ecode;
f078f209 552
f637cfd6 553 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 554 if (ecode != 0)
555 return ecode;
7d01b221 556
c46917bb
LR		 557 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
558 "Eeprom VER: %d, REV: %d\n",
559 ah->eep_ops->get_eeprom_ver(ah),
560 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 561
574d6b12
LR		 562 if (!AR_SREV_9280_10_OR_LATER(ah)) {
563 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
564 if (ecode) {
565 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
566 "Failed allocating banks for "
567 "external radio\n");
568 return ecode;
569 }
570 }
f078f209 571
f1dc5600
S		 572 if (!AR_SREV_9100(ah)) {
573 ath9k_hw_ani_setup(ah);
f637cfd6 574 ath9k_hw_ani_init(ah);
f078f209
LR		 575 }
576
f078f209
LR		 577 return 0;
578}
579
ee2bb460
LR		 580static bool ath9k_hw_devid_supported(u16 devid)
581{
582 switch (devid) {
583 case AR5416_DEVID_PCI:
584 case AR5416_DEVID_PCIE:
585 case AR5416_AR9100_DEVID:
586 case AR9160_DEVID_PCI:
587 case AR9280_DEVID_PCI:
588 case AR9280_DEVID_PCIE:
589 case AR9285_DEVID_PCIE:
590 case AR5416_DEVID_AR9287_PCI:
591 case AR5416_DEVID_AR9287_PCIE:
7976b426 592 case AR9271_USB:
ee2bb460
LR		 593 return true;
594 default:
595 break;
596 }
597 return false;
598}
599
f9d4a668
LR		 600static bool ath9k_hw_macversion_supported(u32 macversion)
601{
602 switch (macversion) {
603 case AR_SREV_VERSION_5416_PCI:
604 case AR_SREV_VERSION_5416_PCIE:
605 case AR_SREV_VERSION_9160:
606 case AR_SREV_VERSION_9100:
607 case AR_SREV_VERSION_9280:
608 case AR_SREV_VERSION_9285:
609 case AR_SREV_VERSION_9287:
d7e7d229 610 case AR_SREV_VERSION_9271:
7976b426 611 return true;
f9d4a668
LR		 612 default:
613 break;
614 }
615 return false;
616}
617
aa4058ae 618static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
f078f209 619{
f1dc5600
S		 620 if (AR_SREV_9160_10_OR_LATER(ah)) {
621 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a
S		 622 ah->iq_caldata.calData = &iq_cal_single_sample;
623 ah->adcgain_caldata.calData =
f1dc5600 624 &adc_gain_cal_single_sample;
2660b81a 625 ah->adcdc_caldata.calData =
f1dc5600 626 &adc_dc_cal_single_sample;
2660b81a 627 ah->adcdc_calinitdata.calData =
f1dc5600
S		 628 &adc_init_dc_cal;
629 } else {
2660b81a
S		 630 ah->iq_caldata.calData = &iq_cal_multi_sample;
631 ah->adcgain_caldata.calData =
f1dc5600 632 &adc_gain_cal_multi_sample;
2660b81a 633 ah->adcdc_caldata.calData =
f1dc5600 634 &adc_dc_cal_multi_sample;
2660b81a 635 ah->adcdc_calinitdata.calData =
f1dc5600
S		 636 &adc_init_dc_cal;
637 }
2660b81a 638 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
f1dc5600 639 }
aa4058ae 640}
f078f209 641
aa4058ae
LR		 642static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
643{
d7e7d229 644 if (AR_SREV_9271(ah)) {
8564328d
LR		 645 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
646 ARRAY_SIZE(ar9271Modes_9271), 6);
647 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
648 ARRAY_SIZE(ar9271Common_9271), 2);
649 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
650 ar9271Modes_9271_1_0_only,
651 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
d7e7d229
LR		 652 return;
653 }
654
ac88b6ec
VN		 655 if (AR_SREV_9287_11_OR_LATER(ah)) {
656 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
657 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
658 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
659 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
660 if (ah->config.pcie_clock_req)
661 INIT_INI_ARRAY(&ah->iniPcieSerdes,
662 ar9287PciePhy_clkreq_off_L1_9287_1_1,
663 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
664 else
665 INIT_INI_ARRAY(&ah->iniPcieSerdes,
666 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
667 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
668 2);
669 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
670 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
671 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
672 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
673 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
674
675 if (ah->config.pcie_clock_req)
676 INIT_INI_ARRAY(&ah->iniPcieSerdes,
677 ar9287PciePhy_clkreq_off_L1_9287_1_0,
678 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
679 else
680 INIT_INI_ARRAY(&ah->iniPcieSerdes,
681 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
682 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
683 2);
684 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
f078f209 685
4e845168 686
2660b81a 687 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
e7594072 688 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
2660b81a 689 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
e7594072
SB		 690 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
691
2660b81a
S		 692 if (ah->config.pcie_clock_req) {
693 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 694 ar9285PciePhy_clkreq_off_L1_9285_1_2,
695 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
696 } else {
2660b81a 697 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 698 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
699 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
700 2);
701 }
702 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
2660b81a 703 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
e7594072 704 ARRAY_SIZE(ar9285Modes_9285), 6);
2660b81a 705 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
e7594072
SB		 706 ARRAY_SIZE(ar9285Common_9285), 2);
707
2660b81a
S		 708 if (ah->config.pcie_clock_req) {
709 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 710 ar9285PciePhy_clkreq_off_L1_9285,
711 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
712 } else {
2660b81a 713 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 714 ar9285PciePhy_clkreq_always_on_L1_9285,
715 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
716 }
717 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2660b81a 718 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
f1dc5600 719 ARRAY_SIZE(ar9280Modes_9280_2), 6);
2660b81a 720 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
f1dc5600 721 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 722
2660b81a
S		 723 if (ah->config.pcie_clock_req) {
724 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 725 ar9280PciePhy_clkreq_off_L1_9280,
726 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
727 } else {
2660b81a 728 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 729 ar9280PciePhy_clkreq_always_on_L1_9280,
730 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
731 }
2660b81a 732 INIT_INI_ARRAY(&ah->iniModesAdditional,
f1dc5600
S		 733 ar9280Modes_fast_clock_9280_2,
734 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
735 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 736 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
f1dc5600 737 ARRAY_SIZE(ar9280Modes_9280), 6);
2660b81a 738 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
f1dc5600
S		 739 ARRAY_SIZE(ar9280Common_9280), 2);
740 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2660b81a 741 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
f1dc5600 742 ARRAY_SIZE(ar5416Modes_9160), 6);
2660b81a 743 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
f1dc5600 744 ARRAY_SIZE(ar5416Common_9160), 2);
2660b81a 745 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
f1dc5600 746 ARRAY_SIZE(ar5416Bank0_9160), 2);
2660b81a 747 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
f1dc5600 748 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
2660b81a 749 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
f1dc5600 750 ARRAY_SIZE(ar5416Bank1_9160), 2);
2660b81a 751 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
f1dc5600 752 ARRAY_SIZE(ar5416Bank2_9160), 2);
2660b81a 753 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
f1dc5600 754 ARRAY_SIZE(ar5416Bank3_9160), 3);
2660b81a 755 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
f1dc5600 756 ARRAY_SIZE(ar5416Bank6_9160), 3);
2660b81a 757 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
f1dc5600 758 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
2660b81a 759 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
f1dc5600
S		 760 ARRAY_SIZE(ar5416Bank7_9160), 2);
761 if (AR_SREV_9160_11(ah)) {
2660b81a 762 INIT_INI_ARRAY(&ah->iniAddac,
f1dc5600
S		 763 ar5416Addac_91601_1,
764 ARRAY_SIZE(ar5416Addac_91601_1), 2);
765 } else {
2660b81a 766 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
f1dc5600
S		 767 ARRAY_SIZE(ar5416Addac_9160), 2);
768 }
769 } else if (AR_SREV_9100_OR_LATER(ah)) {
2660b81a 770 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
f1dc5600 771 ARRAY_SIZE(ar5416Modes_9100), 6);
2660b81a 772 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
f1dc5600 773 ARRAY_SIZE(ar5416Common_9100), 2);
2660b81a 774 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
f1dc5600 775 ARRAY_SIZE(ar5416Bank0_9100), 2);
2660b81a 776 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
f1dc5600 777 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
2660b81a 778 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
f1dc5600 779 ARRAY_SIZE(ar5416Bank1_9100), 2);
2660b81a 780 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
f1dc5600 781 ARRAY_SIZE(ar5416Bank2_9100), 2);
2660b81a 782 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
f1dc5600 783 ARRAY_SIZE(ar5416Bank3_9100), 3);
2660b81a 784 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
f1dc5600 785 ARRAY_SIZE(ar5416Bank6_9100), 3);
2660b81a 786 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
f1dc5600 787 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
2660b81a 788 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
f1dc5600 789 ARRAY_SIZE(ar5416Bank7_9100), 2);
2660b81a 790 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
f1dc5600
S		 791 ARRAY_SIZE(ar5416Addac_9100), 2);
792 } else {
2660b81a 793 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
f1dc5600 794 ARRAY_SIZE(ar5416Modes), 6);
2660b81a 795 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
f1dc5600 796 ARRAY_SIZE(ar5416Common), 2);
2660b81a 797 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
f1dc5600 798 ARRAY_SIZE(ar5416Bank0), 2);
2660b81a 799 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
f1dc5600 800 ARRAY_SIZE(ar5416BB_RfGain), 3);
2660b81a 801 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
f1dc5600 802 ARRAY_SIZE(ar5416Bank1), 2);
2660b81a 803 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
f1dc5600 804 ARRAY_SIZE(ar5416Bank2), 2);
2660b81a 805 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
f1dc5600 806 ARRAY_SIZE(ar5416Bank3), 3);
2660b81a 807 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
f1dc5600 808 ARRAY_SIZE(ar5416Bank6), 3);
2660b81a 809 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
f1dc5600 810 ARRAY_SIZE(ar5416Bank6TPC), 3);
2660b81a 811 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
f1dc5600 812 ARRAY_SIZE(ar5416Bank7), 2);
2660b81a 813 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
f1dc5600 814 ARRAY_SIZE(ar5416Addac), 2);
f078f209 815 }
aa4058ae 816}
f078f209 817
aa4058ae
LR		 818static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
819{
b37fa870 820 if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec
VN		 821 INIT_INI_ARRAY(&ah->iniModesRxGain,
822 ar9287Modes_rx_gain_9287_1_1,
823 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
824 else if (AR_SREV_9287_10(ah))
825 INIT_INI_ARRAY(&ah->iniModesRxGain,
826 ar9287Modes_rx_gain_9287_1_0,
827 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
828 else if (AR_SREV_9280_20(ah))
829 ath9k_hw_init_rxgain_ini(ah);
830
b37fa870 831 if (AR_SREV_9287_11_OR_LATER(ah)) {
ac88b6ec
VN		 832 INIT_INI_ARRAY(&ah->iniModesTxGain,
833 ar9287Modes_tx_gain_9287_1_1,
834 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
835 } else if (AR_SREV_9287_10(ah)) {
836 INIT_INI_ARRAY(&ah->iniModesTxGain,
837 ar9287Modes_tx_gain_9287_1_0,
838 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
839 } else if (AR_SREV_9280_20(ah)) {
840 ath9k_hw_init_txgain_ini(ah);
841 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4e845168
SB		 842 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
843
844 /* txgain table */
845 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
846 INIT_INI_ARRAY(&ah->iniModesTxGain,
847 ar9285Modes_high_power_tx_gain_9285_1_2,
848 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
849 } else {
850 INIT_INI_ARRAY(&ah->iniModesTxGain,
851 ar9285Modes_original_tx_gain_9285_1_2,
852 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
853 }
854
855 }
aa4058ae 856}
4e845168 857
aa4058ae
LR		 858static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
859{
860 u32 i, j;
06d0f066
S		 861
862 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
863 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
864
865 /* EEPROM Fixup */
2660b81a
S		 866 for (i = 0; i < ah->iniModes.ia_rows; i++) {
867 u32 reg = INI_RA(&ah->iniModes, i, 0);
f078f209 868
2660b81a
S		 869 for (j = 1; j < ah->iniModes.ia_columns; j++) {
870 u32 val = INI_RA(&ah->iniModes, i, j);
f078f209 871
2660b81a 872 INI_RA(&ah->iniModes, i, j) =
e7594072 873 ath9k_hw_ini_fixup(ah,
2660b81a 874 &ah->eeprom.def,
f1dc5600
S		 875 reg, val);
876 }
f078f209 877 }
f1dc5600 878 }
aa4058ae
LR		 879}
880
f637cfd6 881int ath9k_hw_init(struct ath_hw *ah)
aa4058ae 882{
c46917bb 883 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 884 int r = 0;
aa4058ae 885
3ca34038
LR		 886 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
887 ath_print(common, ATH_DBG_FATAL,
888 "Unsupported device ID: 0x%0x\n",
889 ah->hw_version.devid);
95fafca2 890 return -EOPNOTSUPP;
3ca34038 891 }
aa4058ae
LR		 892
893 ath9k_hw_init_defaults(ah);
894 ath9k_hw_init_config(ah);
895
896 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 897 ath_print(common, ATH_DBG_FATAL,
898 "Couldn't reset chip\n");
95fafca2 899 return -EIO;
aa4058ae
LR		 900 }
901
9ecdef4b 902 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 903 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 904 return -EIO;
aa4058ae
LR		 905 }
906
907 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
908 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
909 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
910 ah->config.serialize_regmode =
911 SER_REG_MODE_ON;
912 } else {
913 ah->config.serialize_regmode =
914 SER_REG_MODE_OFF;
915 }
916 }
917
c46917bb 918 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 919 ah->config.serialize_regmode);
920
f4709fdf
LR		 921 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
922 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
923 else
924 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
925
aa4058ae 926 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
c46917bb
LR		 927 ath_print(common, ATH_DBG_FATAL,
928 "Mac Chip Rev 0x%02x.%x is not supported by "
929 "this driver\n", ah->hw_version.macVersion,
930 ah->hw_version.macRev);
95fafca2 931 return -EOPNOTSUPP;
aa4058ae
LR		 932 }
933
934 if (AR_SREV_9100(ah)) {
935 ah->iq_caldata.calData = &iq_cal_multi_sample;
936 ah->supp_cals = IQ_MISMATCH_CAL;
937 ah->is_pciexpress = false;
938 }
d7e7d229
LR		 939
940 if (AR_SREV_9271(ah))
941 ah->is_pciexpress = false;
942
aa4058ae
LR		 943 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
944
945 ath9k_hw_init_cal_settings(ah);
946
947 ah->ani_function = ATH9K_ANI_ALL;
e68a060b 948 if (AR_SREV_9280_10_OR_LATER(ah)) {
aa4058ae 949 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e68a060b 950 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
ae478cf6
LR		 951 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
952 } else {
e68a060b 953 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
ae478cf6
LR		 954 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
955 }
aa4058ae
LR		 956
957 ath9k_hw_init_mode_regs(ah);
958
959 if (ah->is_pciexpress)
93b1b37f 960 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 961 else
962 ath9k_hw_disablepcie(ah);
963
193cd458
S		 964 /* Support for Japan ch.14 (2484) spread */
965 if (AR_SREV_9287_11_OR_LATER(ah)) {
966 INIT_INI_ARRAY(&ah->iniCckfirNormal,
967 ar9287Common_normal_cck_fir_coeff_92871_1,
968 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
969 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
970 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
971 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
972 }
973
f637cfd6 974 r = ath9k_hw_post_init(ah);
aa4058ae 975 if (r)
95fafca2 976 return r;
aa4058ae
LR		 977
978 ath9k_hw_init_mode_gain_regs(ah);
979 ath9k_hw_fill_cap_info(ah);
980 ath9k_hw_init_11a_eeprom_fix(ah);
f6688cd8 981
4f3acf81
LR		 982 r = ath9k_hw_init_macaddr(ah);
983 if (r) {
c46917bb
LR		 984 ath_print(common, ATH_DBG_FATAL,
985 "Failed to initialize MAC address\n");
95fafca2 986 return r;
f078f209
LR		 987 }
988
d7e7d229 989 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 990 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 991 else
2660b81a 992 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 993
f1dc5600 994 ath9k_init_nfcal_hist_buffer(ah);
f078f209 995
211f5859
LR		 996 common->state = ATH_HW_INITIALIZED;
997
4f3acf81 998 return 0;
f078f209
LR		 999}
1000
cbe61d8a 1001static void ath9k_hw_init_bb(struct ath_hw *ah,
f1dc5600 1002 struct ath9k_channel *chan)
f078f209 1003{
f1dc5600 1004 u32 synthDelay;
f078f209 1005
f1dc5600 1006 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1007 if (IS_CHAN_B(chan))
f1dc5600
S		 1008 synthDelay = (4 * synthDelay) / 22;
1009 else
1010 synthDelay /= 10;
f078f209 1011
f1dc5600 1012 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 1013
f1dc5600 1014 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 1015}
1016
cbe61d8a 1017static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 1018{
f1dc5600
S		 1019 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1020 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 1021
f1dc5600
S		 1022 REG_WRITE(ah, AR_QOS_NO_ACK,
1023 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1024 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1025 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1026
1027 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1028 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1029 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1030 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1031 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 1032}
1033
c75724d1
LR		 1034static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
1035{
1036 u32 lcr;
1037 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
1038
1039 lcr = REG_READ(ah , 0x5100c);
1040 lcr |= 0x80;
1041
1042 REG_WRITE(ah, 0x5100c, lcr);
1043 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1044 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1045
1046 lcr &= ~0x80;
1047 REG_WRITE(ah, 0x5100c, lcr);
1048}
1049
cbe61d8a 1050static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 1051 struct ath9k_channel *chan)
f078f209 1052{
f1dc5600 1053 u32 pll;
f078f209 1054
f1dc5600
S		 1055 if (AR_SREV_9100(ah)) {
1056 if (chan && IS_CHAN_5GHZ(chan))
1057 pll = 0x1450;
f078f209 1058 else
f1dc5600
S		 1059 pll = 0x1458;
1060 } else {
1061 if (AR_SREV_9280_10_OR_LATER(ah)) {
1062 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1063
f1dc5600
S		 1064 if (chan && IS_CHAN_HALF_RATE(chan))
1065 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1066 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1067 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1068
f1dc5600
S		 1069 if (chan && IS_CHAN_5GHZ(chan)) {
1070 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 1071
f078f209 1072
f1dc5600
S		 1073 if (AR_SREV_9280_20(ah)) {
1074 if (((chan->channel % 20) == 0)
1075 || ((chan->channel % 10) == 0))
1076 pll = 0x2850;
1077 else
1078 pll = 0x142c;
1079 }
1080 } else {
1081 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1082 }
f078f209 1083
f1dc5600 1084 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 1085
f1dc5600 1086 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1087
f1dc5600
S		 1088 if (chan && IS_CHAN_HALF_RATE(chan))
1089 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1090 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1091 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1092
f1dc5600
S		 1093 if (chan && IS_CHAN_5GHZ(chan))
1094 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1095 else
1096 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1097 } else {
1098 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 1099
f1dc5600
S		 1100 if (chan && IS_CHAN_HALF_RATE(chan))
1101 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1102 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1103 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 1104
f1dc5600
S		 1105 if (chan && IS_CHAN_5GHZ(chan))
1106 pll |= SM(0xa, AR_RTC_PLL_DIV);
1107 else
1108 pll |= SM(0xb, AR_RTC_PLL_DIV);
1109 }
1110 }
d03a66c1 1111 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 1112
c75724d1
LR		 1113 /* Switch the core clock for ar9271 to 117Mhz */
1114 if (AR_SREV_9271(ah)) {
1115 if ((pll == 0x142c) || (pll == 0x2850) ) {
1116 udelay(500);
1117 /* set CLKOBS to output AHB clock */
1118 REG_WRITE(ah, 0x7020, 0xe);
1119 /*
1120 * 0x304: 117Mhz, ahb_ratio: 1x1
1121 * 0x306: 40Mhz, ahb_ratio: 1x1
1122 */
1123 REG_WRITE(ah, 0x50040, 0x304);
1124 /*
1125 * makes adjustments for the baud dividor to keep the
1126 * targetted baud rate based on the used core clock.
1127 */
1128 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1129 AR9271_TARGET_BAUD_RATE);
1130 }
1131 }
1132
f1dc5600
S		 1133 udelay(RTC_PLL_SETTLE_DELAY);
1134
1135 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 1136}
1137
cbe61d8a 1138static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
f078f209 1139{
f078f209
LR		 1140 int rx_chainmask, tx_chainmask;
1141
2660b81a
S		 1142 rx_chainmask = ah->rxchainmask;
1143 tx_chainmask = ah->txchainmask;
f078f209
LR		 1144
1145 switch (rx_chainmask) {
1146 case 0x5:
1147 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1148 AR_PHY_SWAP_ALT_CHAIN);
1149 case 0x3:
cb53a150 1150 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
f078f209
LR		 1151 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1152 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1153 break;
1154 }
1155 case 0x1:
1156 case 0x2:
f078f209
LR		 1157 case 0x7:
1158 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1159 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1160 break;
1161 default:
1162 break;
1163 }
1164
1165 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1166 if (tx_chainmask == 0x5) {
1167 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1168 AR_PHY_SWAP_ALT_CHAIN);
1169 }
1170 if (AR_SREV_9100(ah))
1171 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1172 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1173}
1174
cbe61d8a 1175static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 1176 enum nl80211_iftype opmode)
f078f209 1177{
2660b81a 1178 ah->mask_reg = AR_IMR_TXERR |
f1dc5600
S		 1179 AR_IMR_TXURN |
1180 AR_IMR_RXERR |
1181 AR_IMR_RXORN |
1182 AR_IMR_BCNMISC;
f078f209 1183
0ef1f168 1184 if (ah->config.intr_mitigation)
2660b81a 1185 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1186 else
2660b81a 1187 ah->mask_reg |= AR_IMR_RXOK;
f078f209 1188
2660b81a 1189 ah->mask_reg |= AR_IMR_TXOK;
f078f209 1190
d97809db 1191 if (opmode == NL80211_IFTYPE_AP)
2660b81a 1192 ah->mask_reg |= AR_IMR_MIB;
f078f209 1193
2660b81a 1194 REG_WRITE(ah, AR_IMR, ah->mask_reg);
f1dc5600 1195 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1196
f1dc5600
S		 1197 if (!AR_SREV_9100(ah)) {
1198 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1199 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1200 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1201 }
f078f209
LR		 1202}
1203
cbe61d8a 1204static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1205{
f078f209 1206 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
c46917bb
LR		 1207 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1208 "bad ack timeout %u\n", us);
2660b81a 1209 ah->acktimeout = (u32) -1;
f078f209
LR		 1210 return false;
1211 } else {
1212 REG_RMW_FIELD(ah, AR_TIME_OUT,
1213 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1214 ah->acktimeout = us;
f078f209
LR		 1215 return true;
1216 }
1217}
1218
cbe61d8a 1219static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
f078f209 1220{
f078f209 1221 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
c46917bb
LR		 1222 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1223 "bad cts timeout %u\n", us);
2660b81a 1224 ah->ctstimeout = (u32) -1;
f078f209
LR		 1225 return false;
1226 } else {
1227 REG_RMW_FIELD(ah, AR_TIME_OUT,
1228 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1229 ah->ctstimeout = us;
f078f209
LR		 1230 return true;
1231 }
1232}
f1dc5600 1233
cbe61d8a 1234static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1235{
f078f209 1236 if (tu > 0xFFFF) {
c46917bb
LR		 1237 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1238 "bad global tx timeout %u\n", tu);
2660b81a 1239 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1240 return false;
1241 } else {
1242 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1243 ah->globaltxtimeout = tu;
f078f209
LR		 1244 return true;
1245 }
1246}
1247
cbe61d8a 1248static void ath9k_hw_init_user_settings(struct ath_hw *ah)
f078f209 1249{
c46917bb
LR		 1250 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1251 ah->misc_mode);
f078f209 1252
2660b81a 1253 if (ah->misc_mode != 0)
f1dc5600 1254 REG_WRITE(ah, AR_PCU_MISC,
2660b81a
S		 1255 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1256 if (ah->slottime != (u32) -1)
1257 ath9k_hw_setslottime(ah, ah->slottime);
1258 if (ah->acktimeout != (u32) -1)
1259 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1260 if (ah->ctstimeout != (u32) -1)
1261 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1262 if (ah->globaltxtimeout != (u32) -1)
1263 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600
S		 1264}
1265
1266const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1267{
1268 return vendorid == ATHEROS_VENDOR_ID ?
1269 ath9k_hw_devname(devid) : NULL;
1270}
1271
cbe61d8a 1272void ath9k_hw_detach(struct ath_hw *ah)
f1dc5600 1273{
211f5859
LR		 1274 struct ath_common *common = ath9k_hw_common(ah);
1275
1276 if (common->state <= ATH_HW_INITIALIZED)
1277 goto free_hw;
1278
f1dc5600 1279 if (!AR_SREV_9100(ah))
e70c0cfd 1280 ath9k_hw_ani_disable(ah);
f1dc5600 1281
9ecdef4b 1282 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 1283
1284free_hw:
dc51dd50
LR		 1285 if (!AR_SREV_9280_10_OR_LATER(ah))
1286 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 1287 kfree(ah);
9db6b6a2 1288 ah = NULL;
f1dc5600 1289}
7322fd19 1290EXPORT_SYMBOL(ath9k_hw_detach);
f1dc5600 1291
f1dc5600
S		 1292/*******/
1293/* INI */
1294/*******/
1295
cbe61d8a 1296static void ath9k_hw_override_ini(struct ath_hw *ah,
f1dc5600
S		 1297 struct ath9k_channel *chan)
1298{
d7e7d229
LR		 1299 u32 val;
1300
1301 if (AR_SREV_9271(ah)) {
1302 /*
1303 * Enable spectral scan to solution for issues with stuck
1304 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1305 * AR9271 1.1
1306 */
1307 if (AR_SREV_9271_10(ah)) {
ec11bb88
LR		 1308 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1309 AR_PHY_SPECTRAL_SCAN_ENABLE;
d7e7d229
LR		 1310 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1311 }
1312 else if (AR_SREV_9271_11(ah))
1313 /*
1314 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1315 * present on AR9271 1.1
1316 */
1317 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1318 return;
1319 }
1320
8aa15e15
SB		 1321 /*
1322 * Set the RX_ABORT and RX_DIS and clear if off only after
1323 * RXE is set for MAC. This prevents frames with corrupted
1324 * descriptor status.
1325 */
1326 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1327
204d7940
VT		 1328 if (AR_SREV_9280_10_OR_LATER(ah)) {
1329 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1330 (~AR_PCU_MISC_MODE2_HWWAR1);
1331
1332 if (AR_SREV_9287_10_OR_LATER(ah))
1333 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1334
1335 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1336 }
8aa15e15 1337
a8c96d3b 1338 if (!AR_SREV_5416_20_OR_LATER(ah) ||
f1dc5600
S		 1339 AR_SREV_9280_10_OR_LATER(ah))
1340 return;
d7e7d229
LR		 1341 /*
1342 * Disable BB clock gating
1343 * Necessary to avoid issues on AR5416 2.0
1344 */
f1dc5600 1345 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1346}
1347
cbe61d8a 1348static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
e7594072 1349 struct ar5416_eeprom_def *pEepData,
f1dc5600 1350 u32 reg, u32 value)
f078f209 1351{
f1dc5600 1352 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
c46917bb 1353 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1354
d535a42a 1355 switch (ah->hw_version.devid) {
f1dc5600
S		 1356 case AR9280_DEVID_PCI:
1357 if (reg == 0x7894) {
c46917bb 1358 ath_print(common, ATH_DBG_EEPROM,
f1dc5600
S		 1359 "ini VAL: %x EEPROM: %x\n", value,
1360 (pBase->version & 0xff));
1361
1362 if ((pBase->version & 0xff) > 0x0a) {
c46917bb
LR		 1363 ath_print(common, ATH_DBG_EEPROM,
1364 "PWDCLKIND: %d\n",
1365 pBase->pwdclkind);
f1dc5600
S		 1366 value &= ~AR_AN_TOP2_PWDCLKIND;
1367 value |= AR_AN_TOP2_PWDCLKIND &
1368 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1369 } else {
c46917bb
LR		 1370 ath_print(common, ATH_DBG_EEPROM,
1371 "PWDCLKIND Earlier Rev\n");
f1dc5600
S		 1372 }
1373
c46917bb
LR		 1374 ath_print(common, ATH_DBG_EEPROM,
1375 "final ini VAL: %x\n", value);
f1dc5600
S		 1376 }
1377 break;
1378 }
1379
1380 return value;
f078f209
LR		 1381}
1382
cbe61d8a 1383static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072
SB		 1384 struct ar5416_eeprom_def *pEepData,
1385 u32 reg, u32 value)
1386{
2660b81a 1387 if (ah->eep_map == EEP_MAP_4KBITS)
e7594072
SB		 1388 return value;
1389 else
1390 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1391}
1392
8bd1d07f
SB		 1393static void ath9k_olc_init(struct ath_hw *ah)
1394{
1395 u32 i;
1396
db91f2e4
VN		 1397 if (OLC_FOR_AR9287_10_LATER) {
1398 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1399 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1400 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1401 AR9287_AN_TXPC0_TXPCMODE,
1402 AR9287_AN_TXPC0_TXPCMODE_S,
1403 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1404 udelay(100);
1405 } else {
1406 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1407 ah->originalGain[i] =
1408 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1409 AR_PHY_TX_GAIN);
1410 ah->PDADCdelta = 0;
1411 }
8bd1d07f
SB		 1412}
1413
3a702e49
BC		 1414static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1415 struct ath9k_channel *chan)
1416{
1417 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1418
1419 if (IS_CHAN_B(chan))
1420 ctl |= CTL_11B;
1421 else if (IS_CHAN_G(chan))
1422 ctl |= CTL_11G;
1423 else
1424 ctl |= CTL_11A;
1425
1426 return ctl;
1427}
1428
cbe61d8a 1429static int ath9k_hw_process_ini(struct ath_hw *ah,
25c56eec 1430 struct ath9k_channel *chan)
f078f209 1431{
608b88cb 1432 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f078f209 1433 int i, regWrites = 0;
5f8e077c 1434 struct ieee80211_channel *channel = chan->chan;
f078f209 1435 u32 modesIndex, freqIndex;
f078f209
LR		 1436
1437 switch (chan->chanmode) {
1438 case CHANNEL_A:
1439 case CHANNEL_A_HT20:
1440 modesIndex = 1;
1441 freqIndex = 1;
1442 break;
1443 case CHANNEL_A_HT40PLUS:
1444 case CHANNEL_A_HT40MINUS:
1445 modesIndex = 2;
1446 freqIndex = 1;
1447 break;
1448 case CHANNEL_G:
1449 case CHANNEL_G_HT20:
1450 case CHANNEL_B:
1451 modesIndex = 4;
1452 freqIndex = 2;
1453 break;
1454 case CHANNEL_G_HT40PLUS:
1455 case CHANNEL_G_HT40MINUS:
1456 modesIndex = 3;
1457 freqIndex = 2;
1458 break;
1459
1460 default:
1461 return -EINVAL;
1462 }
1463
1464 REG_WRITE(ah, AR_PHY(0), 0x00000007);
f078f209 1465 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
f74df6fb 1466 ah->eep_ops->set_addac(ah, chan);
f078f209 1467
a8c96d3b 1468 if (AR_SREV_5416_22_OR_LATER(ah)) {
2660b81a 1469 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
f078f209
LR		 1470 } else {
1471 struct ar5416IniArray temp;
1472 u32 addacSize =
2660b81a
S		 1473 sizeof(u32) * ah->iniAddac.ia_rows *
1474 ah->iniAddac.ia_columns;
f078f209 1475
2660b81a
S		 1476 memcpy(ah->addac5416_21,
1477 ah->iniAddac.ia_array, addacSize);
f078f209 1478
2660b81a 1479 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
f078f209 1480
2660b81a
S		 1481 temp.ia_array = ah->addac5416_21;
1482 temp.ia_columns = ah->iniAddac.ia_columns;
1483 temp.ia_rows = ah->iniAddac.ia_rows;
f078f209
LR		 1484 REG_WRITE_ARRAY(&temp, 1, regWrites);
1485 }
f1dc5600 1486
f078f209
LR		 1487 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1488
2660b81a
S		 1489 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1490 u32 reg = INI_RA(&ah->iniModes, i, 0);
1491 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
f078f209 1492
f078f209
LR		 1493 REG_WRITE(ah, reg, val);
1494
1495 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1496 && ah->config.analog_shiftreg) {
f078f209
LR		 1497 udelay(100);
1498 }
1499
1500 DO_DELAY(regWrites);
1501 }
1502
ac88b6ec 1503 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1504 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
9f804202 1505
ac88b6ec
VN		 1506 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1507 AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1508 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
9f804202 1509
2660b81a
S		 1510 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1511 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1512 u32 val = INI_RA(&ah->iniCommon, i, 1);
f078f209
LR		 1513
1514 REG_WRITE(ah, reg, val);
1515
1516 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1517 && ah->config.analog_shiftreg) {
f078f209
LR		 1518 udelay(100);
1519 }
1520
1521 DO_DELAY(regWrites);
1522 }
1523
896ff260 1524 ath9k_hw_write_regs(ah, freqIndex, regWrites);
f078f209 1525
8564328d
LR		 1526 if (AR_SREV_9271_10(ah))
1527 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1528 modesIndex, regWrites);
1529
f078f209 1530 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
2660b81a 1531 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
f078f209
LR		 1532 regWrites);
1533 }
1534
1535 ath9k_hw_override_ini(ah, chan);
25c56eec 1536 ath9k_hw_set_regs(ah, chan);
f078f209
LR		 1537 ath9k_hw_init_chain_masks(ah);
1538
8bd1d07f
SB		 1539 if (OLC_FOR_AR9280_20_LATER)
1540 ath9k_olc_init(ah);
1541
8fbff4b8 1542 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1543 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 1544 channel->max_antenna_gain * 2,
1545 channel->max_power * 2,
1546 min((u32) MAX_RATE_POWER,
608b88cb 1547 (u32) regulatory->power_limit));
f078f209
LR		 1548
1549 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
c46917bb
LR		 1550 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1551 "ar5416SetRfRegs failed\n");
f078f209
LR		 1552 return -EIO;
1553 }
1554
1555 return 0;
1556}
1557
f1dc5600
S		 1558/****************************************/
1559/* Reset and Channel Switching Routines */
1560/****************************************/
1561
cbe61d8a 1562static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1563{
f1dc5600
S		 1564 u32 rfMode = 0;
1565
1566 if (chan == NULL)
1567 return;
1568
1569 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1570 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1571
1572 if (!AR_SREV_9280_10_OR_LATER(ah))
1573 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1574 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1575
1576 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1577 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1578
1579 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1580}
1581
cbe61d8a 1582static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
f1dc5600
S		 1583{
1584 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1585}
1586
cbe61d8a 1587static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 1588{
1589 u32 regval;
1590
d7e7d229
LR		 1591 /*
1592 * set AHB_MODE not to do cacheline prefetches
1593 */
f1dc5600
S		 1594 regval = REG_READ(ah, AR_AHB_MODE);
1595 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1596
d7e7d229
LR		 1597 /*
1598 * let mac dma reads be in 128 byte chunks
1599 */
f1dc5600
S		 1600 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1601 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1602
d7e7d229
LR		 1603 /*
1604 * Restore TX Trigger Level to its pre-reset value.
1605 * The initial value depends on whether aggregation is enabled, and is
1606 * adjusted whenever underruns are detected.
1607 */
2660b81a 1608 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1609
d7e7d229
LR		 1610 /*
1611 * let mac dma writes be in 128 byte chunks
1612 */
f1dc5600
S		 1613 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1614 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1615
d7e7d229
LR		 1616 /*
1617 * Setup receive FIFO threshold to hold off TX activities
1618 */
f1dc5600
S		 1619 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1620
d7e7d229
LR		 1621 /*
1622 * reduce the number of usable entries in PCU TXBUF to avoid
1623 * wrap around issues.
1624 */
f1dc5600 1625 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1626 /* For AR9285 the number of Fifos are reduced to half.
1627 * So set the usable tx buf size also to half to
1628 * avoid data/delimiter underruns
1629 */
f1dc5600
S		 1630 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1631 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1632 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1633 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1634 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1635 }
1636}
1637
cbe61d8a 1638static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1639{
1640 u32 val;
1641
1642 val = REG_READ(ah, AR_STA_ID1);
1643 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1644 switch (opmode) {
d97809db 1645 case NL80211_IFTYPE_AP:
f1dc5600
S		 1646 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1647 | AR_STA_ID1_KSRCH_MODE);
1648 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1649 break;
d97809db 1650 case NL80211_IFTYPE_ADHOC:
9cb5412b 1651 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 1652 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1653 | AR_STA_ID1_KSRCH_MODE);
1654 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1655 break;
d97809db
CM		 1656 case NL80211_IFTYPE_STATION:
1657 case NL80211_IFTYPE_MONITOR:
f1dc5600 1658 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1659 break;
f1dc5600
S		 1660 }
1661}
1662
cbe61d8a 1663static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
f1dc5600
S		 1664 u32 coef_scaled,
1665 u32 *coef_mantissa,
1666 u32 *coef_exponent)
1667{
1668 u32 coef_exp, coef_man;
1669
1670 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1671 if ((coef_scaled >> coef_exp) & 0x1)
1672 break;
1673
1674 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1675
1676 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1677
1678 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1679 *coef_exponent = coef_exp - 16;
1680}
1681
cbe61d8a 1682static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
f1dc5600
S		 1683 struct ath9k_channel *chan)
1684{
1685 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1686 u32 clockMhzScaled = 0x64000000;
1687 struct chan_centers centers;
1688
1689 if (IS_CHAN_HALF_RATE(chan))
1690 clockMhzScaled = clockMhzScaled >> 1;
1691 else if (IS_CHAN_QUARTER_RATE(chan))
1692 clockMhzScaled = clockMhzScaled >> 2;
1693
1694 ath9k_hw_get_channel_centers(ah, chan, &centers);
1695 coef_scaled = clockMhzScaled / centers.synth_center;
1696
1697 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1698 &ds_coef_exp);
1699
1700 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1701 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1702 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1703 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1704
1705 coef_scaled = (9 * coef_scaled) / 10;
1706
1707 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1708 &ds_coef_exp);
1709
1710 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1711 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1712 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1713 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1714}
1715
cbe61d8a 1716static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1717{
1718 u32 rst_flags;
1719 u32 tmpReg;
1720
70768496
S		 1721 if (AR_SREV_9100(ah)) {
1722 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1723 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1724 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1725 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1726 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1727 }
1728
f1dc5600
S		 1729 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1730 AR_RTC_FORCE_WAKE_ON_INT);
1731
1732 if (AR_SREV_9100(ah)) {
1733 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1734 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1735 } else {
1736 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1737 if (tmpReg &
1738 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1739 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1740 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1741 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1742 } else {
1743 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1744 }
1745
1746 rst_flags = AR_RTC_RC_MAC_WARM;
1747 if (type == ATH9K_RESET_COLD)
1748 rst_flags |= AR_RTC_RC_MAC_COLD;
1749 }
1750
d03a66c1 1751 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1752 udelay(50);
1753
d03a66c1 1754 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1755 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1756 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1757 "RTC stuck in MAC reset\n");
f1dc5600
S		 1758 return false;
1759 }
1760
1761 if (!AR_SREV_9100(ah))
1762 REG_WRITE(ah, AR_RC, 0);
1763
f1dc5600
S		 1764 if (AR_SREV_9100(ah))
1765 udelay(50);
1766
1767 return true;
1768}
1769
cbe61d8a 1770static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1771{
1772 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1773 AR_RTC_FORCE_WAKE_ON_INT);
1774
1c29ce67
VT		 1775 if (!AR_SREV_9100(ah))
1776 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1777
d03a66c1 1778 REG_WRITE(ah, AR_RTC_RESET, 0);
8bd1d07f 1779 udelay(2);
1c29ce67
VT		 1780
1781 if (!AR_SREV_9100(ah))
1782 REG_WRITE(ah, AR_RC, 0);
1783
d03a66c1 1784 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1785
1786 if (!ath9k_hw_wait(ah,
1787 AR_RTC_STATUS,
1788 AR_RTC_STATUS_M,
0caa7b14
S		 1789 AR_RTC_STATUS_ON,
1790 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1791 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1792 "RTC not waking up\n");
f1dc5600 1793 return false;
f078f209
LR		 1794 }
1795
f1dc5600
S		 1796 ath9k_hw_read_revisions(ah);
1797
1798 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1799}
1800
cbe61d8a 1801static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1802{
1803 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1804 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1805
1806 switch (type) {
1807 case ATH9K_RESET_POWER_ON:
1808 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1809 case ATH9K_RESET_WARM:
1810 case ATH9K_RESET_COLD:
1811 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1812 default:
1813 return false;
1814 }
f078f209
LR		 1815}
1816
25c56eec 1817static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1818{
f1dc5600 1819 u32 phymode;
e7594072 1820 u32 enableDacFifo = 0;
f078f209 1821
e7594072
SB		 1822 if (AR_SREV_9285_10_OR_LATER(ah))
1823 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1824 AR_PHY_FC_ENABLE_DAC_FIFO);
1825
f1dc5600 1826 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1827 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1828
1829 if (IS_CHAN_HT40(chan)) {
1830 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1831
f1dc5600
S		 1832 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1833 (chan->chanmode == CHANNEL_G_HT40PLUS))
1834 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1835
f078f209 1836 }
f1dc5600
S		 1837 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1838
25c56eec 1839 ath9k_hw_set11nmac2040(ah);
f078f209 1840
f1dc5600
S		 1841 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1842 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1843}
1844
cbe61d8a 1845static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1846 struct ath9k_channel *chan)
f078f209 1847{
42abfbee 1848 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1849 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1850 return false;
1851 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1852 return false;
f078f209 1853
9ecdef4b 1854 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1855 return false;
f078f209 1856
2660b81a 1857 ah->chip_fullsleep = false;
f1dc5600 1858 ath9k_hw_init_pll(ah, chan);
f1dc5600 1859 ath9k_hw_set_rfmode(ah, chan);
f078f209 1860
f1dc5600 1861 return true;
f078f209
LR		 1862}
1863
cbe61d8a 1864static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1865 struct ath9k_channel *chan)
f078f209 1866{
608b88cb 1867 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1868 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1869 struct ieee80211_channel *channel = chan->chan;
f078f209 1870 u32 synthDelay, qnum;
0a3b7bac 1871 int r;
f078f209
LR		 1872
1873 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1874 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1875 ath_print(common, ATH_DBG_QUEUE,
1876 "Transmit frames pending on "
1877 "queue %d\n", qnum);
f078f209
LR		 1878 return false;
1879 }
1880 }
1881
1882 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1883 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
0caa7b14 1884 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1885 ath_print(common, ATH_DBG_FATAL,
1886 "Could not kill baseband RX\n");
f078f209
LR		 1887 return false;
1888 }
1889
25c56eec 1890 ath9k_hw_set_regs(ah, chan);
f078f209 1891
e68a060b 1892 r = ah->ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1893 if (r) {
1894 ath_print(common, ATH_DBG_FATAL,
1895 "Failed to set channel\n");
1896 return false;
f078f209
LR		 1897 }
1898
8fbff4b8 1899 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1900 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1901 channel->max_antenna_gain * 2,
1902 channel->max_power * 2,
1903 min((u32) MAX_RATE_POWER,
608b88cb 1904 (u32) regulatory->power_limit));
f078f209
LR		 1905
1906 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1907 if (IS_CHAN_B(chan))
f078f209
LR		 1908 synthDelay = (4 * synthDelay) / 22;
1909 else
1910 synthDelay /= 10;
1911
1912 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1913
1914 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1915
f1dc5600
S		 1916 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1917 ath9k_hw_set_delta_slope(ah, chan);
1918
ae478cf6 1919 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600
S		 1920
1921 if (!chan->oneTimeCalsDone)
1922 chan->oneTimeCalsDone = true;
1923
1924 return true;
1925}
1926
3b319aae
JB		 1927static void ath9k_enable_rfkill(struct ath_hw *ah)
1928{
1929 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1930 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1931
1932 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1933 AR_GPIO_INPUT_MUX2_RFSILENT);
1934
1935 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1936 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1937}
1938
cbe61d8a 1939int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 1940 bool bChannelChange)
f078f209 1941{
1510718d 1942 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1943 u32 saveLedState;
2660b81a 1944 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1945 u32 saveDefAntenna;
1946 u32 macStaId1;
46fe782c 1947 u64 tsf = 0;
ae8d2858 1948 int i, rx_chainmask, r;
f078f209 1949
43c27613
LR		 1950 ah->txchainmask = common->tx_chainmask;
1951 ah->rxchainmask = common->rx_chainmask;
f078f209 1952
9ecdef4b 1953 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1954 return -EIO;
f078f209 1955
9ebef799 1956 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1957 ath9k_hw_getnf(ah, curchan);
1958
1959 if (bChannelChange &&
2660b81a
S		 1960 (ah->chip_fullsleep != true) &&
1961 (ah->curchan != NULL) &&
1962 (chan->channel != ah->curchan->channel) &&
f078f209 1963 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1964 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
0a475cc6
VT		 1965 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1966 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
f078f209 1967
25c56eec 1968 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1969 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 1970 ath9k_hw_start_nfcal(ah);
ae8d2858 1971 return 0;
f078f209
LR		 1972 }
1973 }
1974
1975 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1976 if (saveDefAntenna == 0)
1977 saveDefAntenna = 1;
1978
1979 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1980
46fe782c
S		 1981 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1982 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1983 tsf = ath9k_hw_gettsf64(ah);
1984
f078f209
LR		 1985 saveLedState = REG_READ(ah, AR_CFG_LED) &
1986 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1987 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1988
1989 ath9k_hw_mark_phy_inactive(ah);
1990
d7e7d229
LR		 1991 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1992 REG_WRITE(ah,
1993 AR9271_RESET_POWER_DOWN_CONTROL,
1994 AR9271_RADIO_RF_RST);
1995 udelay(50);
1996 }
1997
f078f209 1998 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1999 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 2000 return -EINVAL;
f078f209
LR		 2001 }
2002
d7e7d229
LR		 2003 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2004 ah->htc_reset_init = false;
2005 REG_WRITE(ah,
2006 AR9271_RESET_POWER_DOWN_CONTROL,
2007 AR9271_GATE_MAC_CTL);
2008 udelay(50);
2009 }
2010
46fe782c
S		 2011 /* Restore TSF */
2012 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2013 ath9k_hw_settsf64(ah, tsf);
2014
369391db
VT		 2015 if (AR_SREV_9280_10_OR_LATER(ah))
2016 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 2017
326bebbc 2018 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2019 /* Enable ASYNC FIFO */
2020 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2021 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2022 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2023 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2024 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2025 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2026 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2027 }
25c56eec 2028 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 2029 if (r)
2030 return r;
f078f209 2031
0ced0e17
JM		 2032 /* Setup MFP options for CCMP */
2033 if (AR_SREV_9280_20_OR_LATER(ah)) {
2034 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2035 * frames when constructing CCMP AAD. */
2036 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2037 0xc7ff);
2038 ah->sw_mgmt_crypto = false;
2039 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2040 /* Disable hardware crypto for management frames */
2041 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2042 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2043 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2044 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2045 ah->sw_mgmt_crypto = true;
2046 } else
2047 ah->sw_mgmt_crypto = true;
2048
f078f209
LR		 2049 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2050 ath9k_hw_set_delta_slope(ah, chan);
2051
ae478cf6 2052 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 2053 ah->eep_ops->set_board_values(ah, chan);
a7765828 2054
1510718d
LR		 2055 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2056 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 2057 | macStaId1
2058 | AR_STA_ID1_RTS_USE_DEF
2660b81a 2059 | (ah->config.
60b67f51 2060 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 2061 | ah->sta_id1_defaults);
2062 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2063
13b81559 2064 ath_hw_setbssidmask(common);
f078f209
LR		 2065
2066 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2067
3453ad88 2068 ath9k_hw_write_associd(ah);
f078f209
LR		 2069
2070 REG_WRITE(ah, AR_ISR, ~0);
2071
2072 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2073
e68a060b 2074 r = ah->ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 2075 if (r)
2076 return r;
f078f209
LR		 2077
2078 for (i = 0; i < AR_NUM_DCU; i++)
2079 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2080
2660b81a
S		 2081 ah->intr_txqs = 0;
2082 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 2083 ath9k_hw_resettxqueue(ah, i);
2084
2660b81a 2085 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 2086 ath9k_hw_init_qos(ah);
2087
2660b81a 2088 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 2089 ath9k_enable_rfkill(ah);
3b319aae 2090
f078f209
LR		 2091 ath9k_hw_init_user_settings(ah);
2092
326bebbc 2093 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2094 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2095 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2096 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2097 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2098 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2099 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2100
2101 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2102 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2103
2104 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2105 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2106 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2107 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2108 }
326bebbc 2109 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2110 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2111 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2112 }
2113
f078f209
LR		 2114 REG_WRITE(ah, AR_STA_ID1,
2115 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2116
2117 ath9k_hw_set_dma(ah);
2118
2119 REG_WRITE(ah, AR_OBS, 8);
2120
0ef1f168 2121 if (ah->config.intr_mitigation) {
f078f209
LR		 2122 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2123 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2124 }
2125
2126 ath9k_hw_init_bb(ah, chan);
2127
ae8d2858 2128 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2129 return -EIO;
f078f209 2130
2660b81a 2131 rx_chainmask = ah->rxchainmask;
f078f209
LR		 2132 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2133 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2134 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2135 }
2136
2137 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2138
d7e7d229
LR		 2139 /*
2140 * For big endian systems turn on swapping for descriptors
2141 */
f078f209
LR		 2142 if (AR_SREV_9100(ah)) {
2143 u32 mask;
2144 mask = REG_READ(ah, AR_CFG);
2145 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 2146 ath_print(common, ATH_DBG_RESET,
04bd4638 2147 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2148 } else {
2149 mask =
2150 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2151 REG_WRITE(ah, AR_CFG, mask);
c46917bb 2152 ath_print(common, ATH_DBG_RESET,
04bd4638 2153 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2154 }
2155 } else {
d7e7d229
LR		 2156 /* Configure AR9271 target WLAN */
2157 if (AR_SREV_9271(ah))
2158 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 2159#ifdef __BIG_ENDIAN
d7e7d229
LR		 2160 else
2161 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 2162#endif
2163 }
2164
766ec4a9 2165 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 2166 ath9k_hw_btcoex_enable(ah);
2167
ae8d2858 2168 return 0;
f078f209 2169}
7322fd19 2170EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2171
f1dc5600
S		 2172/************************/
2173/* Key Cache Management */
2174/************************/
f078f209 2175
cbe61d8a 2176bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 2177{
f1dc5600 2178 u32 keyType;
f078f209 2179
2660b81a 2180 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 2181 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2182 "keychache entry %u out of range\n", entry);
f078f209
LR		 2183 return false;
2184 }
2185
f1dc5600 2186 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2187
f1dc5600
S		 2188 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2189 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2190 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2191 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2192 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2193 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2194 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2195 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2196
f1dc5600
S		 2197 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2198 u16 micentry = entry + 64;
f078f209 2199
f1dc5600
S		 2200 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2201 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2202 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2203 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2204
f078f209
LR		 2205 }
2206
f078f209
LR		 2207 return true;
2208}
7322fd19 2209EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 2210
cbe61d8a 2211bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 2212{
f1dc5600 2213 u32 macHi, macLo;
f078f209 2214
2660b81a 2215 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 2216 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2217 "keychache entry %u out of range\n", entry);
f1dc5600 2218 return false;
f078f209
LR		 2219 }
2220
f1dc5600
S		 2221 if (mac != NULL) {
2222 macHi = (mac[5] << 8) | mac[4];
2223 macLo = (mac[3] << 24) |
2224 (mac[2] << 16) |
2225 (mac[1] << 8) |
2226 mac[0];
2227 macLo >>= 1;
2228 macLo |= (macHi & 1) << 31;
2229 macHi >>= 1;
f078f209 2230 } else {
f1dc5600 2231 macLo = macHi = 0;
f078f209 2232 }
f1dc5600
S		 2233 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2234 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2235
f1dc5600 2236 return true;
f078f209 2237}
7322fd19 2238EXPORT_SYMBOL(ath9k_hw_keysetmac);
f078f209 2239
cbe61d8a 2240bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 2241 const struct ath9k_keyval *k,
e0caf9ea 2242 const u8 *mac)
f078f209 2243{
2660b81a 2244 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2245 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 2246 u32 key0, key1, key2, key3, key4;
2247 u32 keyType;
f078f209 2248
f1dc5600 2249 if (entry >= pCap->keycache_size) {
c46917bb
LR		 2250 ath_print(common, ATH_DBG_FATAL,
2251 "keycache entry %u out of range\n", entry);
f1dc5600 2252 return false;
f078f209
LR		 2253 }
2254
f1dc5600
S		 2255 switch (k->kv_type) {
2256 case ATH9K_CIPHER_AES_OCB:
2257 keyType = AR_KEYTABLE_TYPE_AES;
2258 break;
2259 case ATH9K_CIPHER_AES_CCM:
2260 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 2261 ath_print(common, ATH_DBG_ANY,
2262 "AES-CCM not supported by mac rev 0x%x\n",
2263 ah->hw_version.macRev);
f1dc5600
S		 2264 return false;
2265 }
2266 keyType = AR_KEYTABLE_TYPE_CCM;
2267 break;
2268 case ATH9K_CIPHER_TKIP:
2269 keyType = AR_KEYTABLE_TYPE_TKIP;
2270 if (ATH9K_IS_MIC_ENABLED(ah)
2271 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 2272 ath_print(common, ATH_DBG_ANY,
2273 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2274 return false;
2275 }
2276 break;
2277 case ATH9K_CIPHER_WEP:
e31a16d6 2278 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 2279 ath_print(common, ATH_DBG_ANY,
2280 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2281 return false;
2282 }
e31a16d6 2283 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 2284 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 2285 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 2286 keyType = AR_KEYTABLE_TYPE_104;
2287 else
2288 keyType = AR_KEYTABLE_TYPE_128;
2289 break;
2290 case ATH9K_CIPHER_CLR:
2291 keyType = AR_KEYTABLE_TYPE_CLR;
2292 break;
2293 default:
c46917bb
LR		 2294 ath_print(common, ATH_DBG_FATAL,
2295 "cipher %u not supported\n", k->kv_type);
f1dc5600 2296 return false;
f078f209
LR		 2297 }
2298
e0caf9ea
JM		 2299 key0 = get_unaligned_le32(k->kv_val + 0);
2300 key1 = get_unaligned_le16(k->kv_val + 4);
2301 key2 = get_unaligned_le32(k->kv_val + 6);
2302 key3 = get_unaligned_le16(k->kv_val + 10);
2303 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 2304 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 2305 key4 &= 0xff;
f078f209 2306
672903b3
JM		 2307 /*
2308 * Note: Key cache registers access special memory area that requires
2309 * two 32-bit writes to actually update the values in the internal
2310 * memory. Consequently, the exact order and pairs used here must be
2311 * maintained.
2312 */
2313
f1dc5600
S		 2314 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2315 u16 micentry = entry + 64;
f078f209 2316
672903b3
JM		 2317 /*
2318 * Write inverted key[47:0] first to avoid Michael MIC errors
2319 * on frames that could be sent or received at the same time.
2320 * The correct key will be written in the end once everything
2321 * else is ready.
2322 */
f1dc5600
S		 2323 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2324 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 2325
2326 /* Write key[95:48] */
f1dc5600
S		 2327 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2328 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2329
2330 /* Write key[127:96] and key type */
f1dc5600
S		 2331 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2332 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 2333
2334 /* Write MAC address for the entry */
f1dc5600 2335 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2336
2660b81a 2337 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 2338 /*
2339 * TKIP uses two key cache entries:
2340 * Michael MIC TX/RX keys in the same key cache entry
2341 * (idx = main index + 64):
2342 * key0 [31:0] = RX key [31:0]
2343 * key1 [15:0] = TX key [31:16]
2344 * key1 [31:16] = reserved
2345 * key2 [31:0] = RX key [63:32]
2346 * key3 [15:0] = TX key [15:0]
2347 * key3 [31:16] = reserved
2348 * key4 [31:0] = TX key [63:32]
2349 */
f1dc5600 2350 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2351
f1dc5600
S		 2352 mic0 = get_unaligned_le32(k->kv_mic + 0);
2353 mic2 = get_unaligned_le32(k->kv_mic + 4);
2354 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2355 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2356 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 2357
2358 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 2359 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2360 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 2361
2362 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 2363 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2364 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 2365
2366 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2367 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2368 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2369 AR_KEYTABLE_TYPE_CLR);
f078f209 2370
f1dc5600 2371 } else {
672903b3
JM		 2372 /*
2373 * TKIP uses four key cache entries (two for group
2374 * keys):
2375 * Michael MIC TX/RX keys are in different key cache
2376 * entries (idx = main index + 64 for TX and
2377 * main index + 32 + 96 for RX):
2378 * key0 [31:0] = TX/RX MIC key [31:0]
2379 * key1 [31:0] = reserved
2380 * key2 [31:0] = TX/RX MIC key [63:32]
2381 * key3 [31:0] = reserved
2382 * key4 [31:0] = reserved
2383 *
2384 * Upper layer code will call this function separately
2385 * for TX and RX keys when these registers offsets are
2386 * used.
2387 */
f1dc5600 2388 u32 mic0, mic2;
f078f209 2389
f1dc5600
S		 2390 mic0 = get_unaligned_le32(k->kv_mic + 0);
2391 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 2392
2393 /* Write MIC key[31:0] */
f1dc5600
S		 2394 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2395 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 2396
2397 /* Write MIC key[63:32] */
f1dc5600
S		 2398 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2399 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 2400
2401 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2402 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2403 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2404 AR_KEYTABLE_TYPE_CLR);
2405 }
672903b3
JM		 2406
2407 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 2408 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2409 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 2410
2411 /*
2412 * Write the correct (un-inverted) key[47:0] last to enable
2413 * TKIP now that all other registers are set with correct
2414 * values.
2415 */
f1dc5600
S		 2416 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2417 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2418 } else {
672903b3 2419 /* Write key[47:0] */
f1dc5600
S		 2420 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2421 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 2422
2423 /* Write key[95:48] */
f1dc5600
S		 2424 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2425 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2426
2427 /* Write key[127:96] and key type */
f1dc5600
S		 2428 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2429 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2430
672903b3 2431 /* Write MAC address for the entry */
f1dc5600
S		 2432 (void) ath9k_hw_keysetmac(ah, entry, mac);
2433 }
f078f209 2434
f078f209
LR		 2435 return true;
2436}
7322fd19 2437EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 2438
cbe61d8a 2439bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 2440{
2660b81a 2441 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 2442 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2443 if (val & AR_KEYTABLE_VALID)
2444 return true;
2445 }
2446 return false;
f078f209 2447}
7322fd19 2448EXPORT_SYMBOL(ath9k_hw_keyisvalid);
f078f209 2449
f1dc5600
S		 2450/******************************/
2451/* Power Management (Chipset) */
2452/******************************/
2453
cbe61d8a 2454static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2455{
f1dc5600
S		 2456 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2457 if (setChip) {
2458 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2459 AR_RTC_FORCE_WAKE_EN);
2460 if (!AR_SREV_9100(ah))
2461 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2462
4921be80
S		 2463 if(!AR_SREV_5416(ah))
2464 REG_CLR_BIT(ah, (AR_RTC_RESET),
2465 AR_RTC_RESET_EN);
f1dc5600 2466 }
f078f209
LR		 2467}
2468
cbe61d8a 2469static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2470{
f1dc5600
S		 2471 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2472 if (setChip) {
2660b81a 2473 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2474
f1dc5600
S		 2475 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2476 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2477 AR_RTC_FORCE_WAKE_ON_INT);
2478 } else {
2479 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2480 AR_RTC_FORCE_WAKE_EN);
f078f209 2481 }
f078f209 2482 }
f078f209
LR		 2483}
2484
cbe61d8a 2485static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2486{
f1dc5600
S		 2487 u32 val;
2488 int i;
f078f209 2489
f1dc5600
S		 2490 if (setChip) {
2491 if ((REG_READ(ah, AR_RTC_STATUS) &
2492 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2493 if (ath9k_hw_set_reset_reg(ah,
2494 ATH9K_RESET_POWER_ON) != true) {
2495 return false;
2496 }
63a75b91 2497 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 2498 }
2499 if (AR_SREV_9100(ah))
2500 REG_SET_BIT(ah, AR_RTC_RESET,
2501 AR_RTC_RESET_EN);
f078f209 2502
f1dc5600
S		 2503 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2504 AR_RTC_FORCE_WAKE_EN);
2505 udelay(50);
f078f209 2506
f1dc5600
S		 2507 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2508 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2509 if (val == AR_RTC_STATUS_ON)
2510 break;
2511 udelay(50);
2512 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2513 AR_RTC_FORCE_WAKE_EN);
f078f209 2514 }
f1dc5600 2515 if (i == 0) {
c46917bb
LR		 2516 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2517 "Failed to wakeup in %uus\n",
2518 POWER_UP_TIME / 20);
f1dc5600 2519 return false;
f078f209 2520 }
f078f209
LR		 2521 }
2522
f1dc5600 2523 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2524
f1dc5600 2525 return true;
f078f209
LR		 2526}
2527
9ecdef4b 2528bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2529{
c46917bb 2530 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 2531 int status = true, setChip = true;
f1dc5600
S		 2532 static const char *modes[] = {
2533 "AWAKE",
2534 "FULL-SLEEP",
2535 "NETWORK SLEEP",
2536 "UNDEFINED"
2537 };
f1dc5600 2538
cbdec975
GJ		 2539 if (ah->power_mode == mode)
2540 return status;
2541
c46917bb
LR		 2542 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2543 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2544
2545 switch (mode) {
2546 case ATH9K_PM_AWAKE:
2547 status = ath9k_hw_set_power_awake(ah, setChip);
2548 break;
2549 case ATH9K_PM_FULL_SLEEP:
2550 ath9k_set_power_sleep(ah, setChip);
2660b81a 2551 ah->chip_fullsleep = true;
f1dc5600
S		 2552 break;
2553 case ATH9K_PM_NETWORK_SLEEP:
2554 ath9k_set_power_network_sleep(ah, setChip);
2555 break;
f078f209 2556 default:
c46917bb
LR		 2557 ath_print(common, ATH_DBG_FATAL,
2558 "Unknown power mode %u\n", mode);
f078f209
LR		 2559 return false;
2560 }
2660b81a 2561 ah->power_mode = mode;
f1dc5600
S		 2562
2563 return status;
f078f209 2564}
7322fd19 2565EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2566
24c1a280
LR		 2567/*
2568 * Helper for ASPM support.
2569 *
2570 * Disable PLL when in L0s as well as receiver clock when in L1.
2571 * This power saving option must be enabled through the SerDes.
2572 *
2573 * Programming the SerDes must go through the same 288 bit serial shift
2574 * register as the other analog registers. Hence the 9 writes.
2575 */
93b1b37f 2576void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
f078f209 2577{
f1dc5600 2578 u8 i;
93b1b37f 2579 u32 val;
f078f209 2580
2660b81a 2581 if (ah->is_pciexpress != true)
f1dc5600 2582 return;
f078f209 2583
24c1a280 2584 /* Do not touch SerDes registers */
2660b81a 2585 if (ah->config.pcie_powersave_enable == 2)
f1dc5600
S		 2586 return;
2587
24c1a280 2588 /* Nothing to do on restore for 11N */
93b1b37f
VN		 2589 if (!restore) {
2590 if (AR_SREV_9280_20_OR_LATER(ah)) {
2591 /*
2592 * AR9280 2.0 or later chips use SerDes values from the
2593 * initvals.h initialized depending on chipset during
2594 * ath9k_hw_init()
2595 */
2596 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2597 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2598 INI_RA(&ah->iniPcieSerdes, i, 1));
2599 }
2600 } else if (AR_SREV_9280(ah) &&
2601 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2602 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2603 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2604
2605 /* RX shut off when elecidle is asserted */
2606 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2607 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2608 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2609
2610 /* Shut off CLKREQ active in L1 */
2611 if (ah->config.pcie_clock_req)
2612 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2613 else
2614 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
f1dc5600 2615
93b1b37f
VN		 2616 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2617 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2618 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
f1dc5600 2619
93b1b37f
VN		 2620 /* Load the new settings */
2621 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f1dc5600 2622
93b1b37f
VN		 2623 } else {
2624 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2625 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
f1dc5600 2626
93b1b37f
VN		 2627 /* RX shut off when elecidle is asserted */
2628 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2629 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2630 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
f1dc5600 2631
93b1b37f
VN		 2632 /*
2633 * Ignore ah->ah_config.pcie_clock_req setting for
2634 * pre-AR9280 11n
2635 */
2636 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
24c1a280 2637
93b1b37f
VN		 2638 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2639 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2640 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
24c1a280 2641
93b1b37f
VN		 2642 /* Load the new settings */
2643 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2644 }
24c1a280 2645
93b1b37f 2646 udelay(1000);
24c1a280 2647
93b1b37f
VN		 2648 /* set bit 19 to allow forcing of pcie core into L1 state */
2649 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
f078f209 2650
93b1b37f
VN		 2651 /* Several PCIe massages to ensure proper behaviour */
2652 if (ah->config.pcie_waen) {
2653 val = ah->config.pcie_waen;
2654 if (!power_off)
2655 val &= (~AR_WA_D3_L1_DISABLE);
2656 } else {
2657 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2658 AR_SREV_9287(ah)) {
2659 val = AR9285_WA_DEFAULT;
2660 if (!power_off)
2661 val &= (~AR_WA_D3_L1_DISABLE);
2662 } else if (AR_SREV_9280(ah)) {
2663 /*
2664 * On AR9280 chips bit 22 of 0x4004 needs to be
2665 * set otherwise card may disappear.
2666 */
2667 val = AR9280_WA_DEFAULT;
2668 if (!power_off)
2669 val &= (~AR_WA_D3_L1_DISABLE);
2670 } else
2671 val = AR_WA_DEFAULT;
2672 }
6d08b9b9 2673
93b1b37f
VN		 2674 REG_WRITE(ah, AR_WA, val);
2675 }
f1dc5600 2676
93b1b37f 2677 if (power_off) {
24c1a280 2678 /*
93b1b37f
VN		 2679 * Set PCIe workaround bits
2680 * bit 14 in WA register (disable L1) should only
2681 * be set when device enters D3 and be cleared
2682 * when device comes back to D0.
24c1a280 2683 */
93b1b37f
VN		 2684 if (ah->config.pcie_waen) {
2685 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2686 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2687 } else {
2688 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2689 AR_SREV_9287(ah)) &&
2690 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2691 (AR_SREV_9280(ah) &&
2692 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2693 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2694 }
2695 }
f1dc5600 2696 }
f078f209 2697}
7322fd19 2698EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
f078f209 2699
f1dc5600
S		 2700/**********************/
2701/* Interrupt Handling */
2702/**********************/
2703
cbe61d8a 2704bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 2705{
2706 u32 host_isr;
2707
2708 if (AR_SREV_9100(ah))
2709 return true;
2710
2711 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2712 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2713 return true;
2714
2715 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2716 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2717 && (host_isr != AR_INTR_SPURIOUS))
2718 return true;
2719
2720 return false;
2721}
7322fd19 2722EXPORT_SYMBOL(ath9k_hw_intrpend);
f078f209 2723
cbe61d8a 2724bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 2725{
2726 u32 isr = 0;
2727 u32 mask2 = 0;
2660b81a 2728 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 2729 u32 sync_cause = 0;
2730 bool fatal_int = false;
c46917bb 2731 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 2732
2733 if (!AR_SREV_9100(ah)) {
2734 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2735 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2736 == AR_RTC_STATUS_ON) {
2737 isr = REG_READ(ah, AR_ISR);
2738 }
2739 }
2740
f1dc5600
S		 2741 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2742 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 2743
2744 *masked = 0;
2745
2746 if (!isr && !sync_cause)
2747 return false;
2748 } else {
2749 *masked = 0;
2750 isr = REG_READ(ah, AR_ISR);
2751 }
2752
2753 if (isr) {
f078f209
LR		 2754 if (isr & AR_ISR_BCNMISC) {
2755 u32 isr2;
2756 isr2 = REG_READ(ah, AR_ISR_S2);
2757 if (isr2 & AR_ISR_S2_TIM)
2758 mask2 |= ATH9K_INT_TIM;
2759 if (isr2 & AR_ISR_S2_DTIM)
2760 mask2 |= ATH9K_INT_DTIM;
2761 if (isr2 & AR_ISR_S2_DTIMSYNC)
2762 mask2 |= ATH9K_INT_DTIMSYNC;
2763 if (isr2 & (AR_ISR_S2_CABEND))
2764 mask2 |= ATH9K_INT_CABEND;
2765 if (isr2 & AR_ISR_S2_GTT)
2766 mask2 |= ATH9K_INT_GTT;
2767 if (isr2 & AR_ISR_S2_CST)
2768 mask2 |= ATH9K_INT_CST;
4af9cf4f
S		 2769 if (isr2 & AR_ISR_S2_TSFOOR)
2770 mask2 |= ATH9K_INT_TSFOOR;
f078f209
LR		 2771 }
2772
2773 isr = REG_READ(ah, AR_ISR_RAC);
2774 if (isr == 0xffffffff) {
2775 *masked = 0;
2776 return false;
2777 }
2778
2779 *masked = isr & ATH9K_INT_COMMON;
2780
0ef1f168 2781 if (ah->config.intr_mitigation) {
f078f209
LR		 2782 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2783 *masked |= ATH9K_INT_RX;
2784 }
2785
2786 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2787 *masked |= ATH9K_INT_RX;
2788 if (isr &
2789 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2790 AR_ISR_TXEOL)) {
2791 u32 s0_s, s1_s;
2792
2793 *masked |= ATH9K_INT_TX;
2794
2795 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 2796 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2797 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 2798
2799 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 2800 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2801 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 2802 }
2803
2804 if (isr & AR_ISR_RXORN) {
c46917bb
LR		 2805 ath_print(common, ATH_DBG_INTERRUPT,
2806 "receive FIFO overrun interrupt\n");
f078f209
LR		 2807 }
2808
2809 if (!AR_SREV_9100(ah)) {
60b67f51 2810 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2811 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2812 if (isr5 & AR_ISR_S5_TIM_TIMER)
2813 *masked |= ATH9K_INT_TIM_TIMER;
2814 }
2815 }
2816
2817 *masked |= mask2;
2818 }
f1dc5600 2819
f078f209
LR		 2820 if (AR_SREV_9100(ah))
2821 return true;
f1dc5600 2822
ff155a45
VT		 2823 if (isr & AR_ISR_GENTMR) {
2824 u32 s5_s;
2825
2826 s5_s = REG_READ(ah, AR_ISR_S5_S);
2827 if (isr & AR_ISR_GENTMR) {
2828 ah->intr_gen_timer_trigger =
2829 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2830
2831 ah->intr_gen_timer_thresh =
2832 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2833
2834 if (ah->intr_gen_timer_trigger)
2835 *masked |= ATH9K_INT_GENTIMER;
2836
2837 }
2838 }
2839
f078f209
LR		 2840 if (sync_cause) {
2841 fatal_int =
2842 (sync_cause &
2843 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2844 ? true : false;
2845
2846 if (fatal_int) {
2847 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
c46917bb
LR		 2848 ath_print(common, ATH_DBG_ANY,
2849 "received PCI FATAL interrupt\n");
f078f209
LR		 2850 }
2851 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
c46917bb
LR		 2852 ath_print(common, ATH_DBG_ANY,
2853 "received PCI PERR interrupt\n");
f078f209 2854 }
a89bff9a 2855 *masked |= ATH9K_INT_FATAL;
f078f209
LR		 2856 }
2857 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
c46917bb
LR		 2858 ath_print(common, ATH_DBG_INTERRUPT,
2859 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 2860 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2861 REG_WRITE(ah, AR_RC, 0);
2862 *masked |= ATH9K_INT_FATAL;
2863 }
2864 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
c46917bb
LR		 2865 ath_print(common, ATH_DBG_INTERRUPT,
2866 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 2867 }
2868
2869 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2870 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2871 }
f1dc5600 2872
f078f209
LR		 2873 return true;
2874}
7322fd19 2875EXPORT_SYMBOL(ath9k_hw_getisr);
f078f209 2876
cbe61d8a 2877enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 2878{
2660b81a 2879 u32 omask = ah->mask_reg;
f078f209 2880 u32 mask, mask2;
2660b81a 2881 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2882 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2883
c46917bb 2884 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 2885
2886 if (omask & ATH9K_INT_GLOBAL) {
c46917bb 2887 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 2888 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2889 (void) REG_READ(ah, AR_IER);
2890 if (!AR_SREV_9100(ah)) {
2891 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2892 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2893
2894 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2895 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2896 }
2897 }
2898
2899 mask = ints & ATH9K_INT_COMMON;
2900 mask2 = 0;
2901
2902 if (ints & ATH9K_INT_TX) {
2660b81a 2903 if (ah->txok_interrupt_mask)
f078f209 2904 mask |= AR_IMR_TXOK;
2660b81a 2905 if (ah->txdesc_interrupt_mask)
f078f209 2906 mask |= AR_IMR_TXDESC;
2660b81a 2907 if (ah->txerr_interrupt_mask)
f078f209 2908 mask |= AR_IMR_TXERR;
2660b81a 2909 if (ah->txeol_interrupt_mask)
f078f209
LR		 2910 mask |= AR_IMR_TXEOL;
2911 }
2912 if (ints & ATH9K_INT_RX) {
2913 mask |= AR_IMR_RXERR;
0ef1f168 2914 if (ah->config.intr_mitigation)
f078f209
LR		 2915 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2916 else
2917 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 2918 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 2919 mask |= AR_IMR_GENTMR;
2920 }
2921
2922 if (ints & (ATH9K_INT_BMISC)) {
2923 mask |= AR_IMR_BCNMISC;
2924 if (ints & ATH9K_INT_TIM)
2925 mask2 |= AR_IMR_S2_TIM;
2926 if (ints & ATH9K_INT_DTIM)
2927 mask2 |= AR_IMR_S2_DTIM;
2928 if (ints & ATH9K_INT_DTIMSYNC)
2929 mask2 |= AR_IMR_S2_DTIMSYNC;
2930 if (ints & ATH9K_INT_CABEND)
4af9cf4f
S		 2931 mask2 |= AR_IMR_S2_CABEND;
2932 if (ints & ATH9K_INT_TSFOOR)
2933 mask2 |= AR_IMR_S2_TSFOOR;
f078f209
LR		 2934 }
2935
2936 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2937 mask |= AR_IMR_BCNMISC;
2938 if (ints & ATH9K_INT_GTT)
2939 mask2 |= AR_IMR_S2_GTT;
2940 if (ints & ATH9K_INT_CST)
2941 mask2 |= AR_IMR_S2_CST;
2942 }
2943
c46917bb 2944 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 2945 REG_WRITE(ah, AR_IMR, mask);
2946 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2947 AR_IMR_S2_DTIM |
2948 AR_IMR_S2_DTIMSYNC |
2949 AR_IMR_S2_CABEND |
2950 AR_IMR_S2_CABTO |
2951 AR_IMR_S2_TSFOOR |
2952 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2953 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2660b81a 2954 ah->mask_reg = ints;
f078f209 2955
60b67f51 2956 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2957 if (ints & ATH9K_INT_TIM_TIMER)
2958 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2959 else
2960 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2961 }
2962
2963 if (ints & ATH9K_INT_GLOBAL) {
c46917bb 2964 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 2965 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2966 if (!AR_SREV_9100(ah)) {
2967 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2968 AR_INTR_MAC_IRQ);
2969 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2970
2971
2972 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2973 AR_INTR_SYNC_DEFAULT);
2974 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2975 AR_INTR_SYNC_DEFAULT);
2976 }
c46917bb
LR		 2977 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2978 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
f078f209
LR		 2979 }
2980
2981 return omask;
2982}
7322fd19 2983EXPORT_SYMBOL(ath9k_hw_set_interrupts);
f078f209 2984
f1dc5600
S		 2985/*******************/
2986/* Beacon Handling */
2987/*******************/
2988
cbe61d8a 2989void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2990{
f078f209
LR		 2991 int flags = 0;
2992
2660b81a 2993 ah->beacon_interval = beacon_period;
f078f209 2994
2660b81a 2995 switch (ah->opmode) {
d97809db
CM		 2996 case NL80211_IFTYPE_STATION:
2997 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 2998 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2999 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3000 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3001 flags |= AR_TBTT_TIMER_EN;
3002 break;
d97809db 3003 case NL80211_IFTYPE_ADHOC:
9cb5412b 3004 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 3005 REG_SET_BIT(ah, AR_TXCFG,
3006 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3007 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3008 TU_TO_USEC(next_beacon +
2660b81a
S		 3009 (ah->atim_window ? ah->
3010 atim_window : 1)));
f078f209 3011 flags |= AR_NDP_TIMER_EN;
d97809db 3012 case NL80211_IFTYPE_AP:
f078f209
LR		 3013 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3014 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3015 TU_TO_USEC(next_beacon -
2660b81a 3016 ah->config.
60b67f51 3017 dma_beacon_response_time));
f078f209
LR		 3018 REG_WRITE(ah, AR_NEXT_SWBA,
3019 TU_TO_USEC(next_beacon -
2660b81a 3020 ah->config.
60b67f51 3021 sw_beacon_response_time));
f078f209
LR		 3022 flags |=
3023 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3024 break;
d97809db 3025 default:
c46917bb
LR		 3026 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3027 "%s: unsupported opmode: %d\n",
3028 __func__, ah->opmode);
d97809db
CM		 3029 return;
3030 break;
f078f209
LR		 3031 }
3032
3033 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3034 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3035 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3036 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3037
3038 beacon_period &= ~ATH9K_BEACON_ENA;
3039 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 3040 ath9k_hw_reset_tsf(ah);
3041 }
3042
3043 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3044}
7322fd19 3045EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 3046
cbe61d8a 3047void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 3048 const struct ath9k_beacon_state *bs)
f078f209
LR		 3049{
3050 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 3051 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 3052 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 3053
3054 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3055
3056 REG_WRITE(ah, AR_BEACON_PERIOD,
3057 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3058 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3059 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3060
3061 REG_RMW_FIELD(ah, AR_RSSI_THR,
3062 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3063
3064 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3065
3066 if (bs->bs_sleepduration > beaconintval)
3067 beaconintval = bs->bs_sleepduration;
3068
3069 dtimperiod = bs->bs_dtimperiod;
3070 if (bs->bs_sleepduration > dtimperiod)
3071 dtimperiod = bs->bs_sleepduration;
3072
3073 if (beaconintval == dtimperiod)
3074 nextTbtt = bs->bs_nextdtim;
3075 else
3076 nextTbtt = bs->bs_nexttbtt;
3077
c46917bb
LR		 3078 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3079 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3080 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3081 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3082
f1dc5600
S		 3083 REG_WRITE(ah, AR_NEXT_DTIM,
3084 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3085 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3086
f1dc5600
S		 3087 REG_WRITE(ah, AR_SLEEP1,
3088 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3089 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3090
f1dc5600
S		 3091 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3092 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3093 else
3094 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3095
f1dc5600
S		 3096 REG_WRITE(ah, AR_SLEEP2,
3097 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3098
f1dc5600
S		 3099 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3100 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3101
f1dc5600
S		 3102 REG_SET_BIT(ah, AR_TIMER_MODE,
3103 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3104 AR_DTIM_TIMER_EN);
f078f209 3105
4af9cf4f
S		 3106 /* TSF Out of Range Threshold */
3107 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 3108}
7322fd19 3109EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 3110
f1dc5600
S		 3111/*******************/
3112/* HW Capabilities */
3113/*******************/
3114
eef7a574 3115void ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 3116{
2660b81a 3117 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 3118 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 3119 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 3120 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 3121
f1dc5600 3122 u16 capField = 0, eeval;
f078f209 3123
f74df6fb 3124 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 3125 regulatory->current_rd = eeval;
f078f209 3126
f74df6fb 3127 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 3128 if (AR_SREV_9285_10_OR_LATER(ah))
3129 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 3130 regulatory->current_rd_ext = eeval;
f078f209 3131
f74df6fb 3132 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 3133
2660b81a 3134 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 3135 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 3136 if (regulatory->current_rd == 0x64 ||
3137 regulatory->current_rd == 0x65)
3138 regulatory->current_rd += 5;
3139 else if (regulatory->current_rd == 0x41)
3140 regulatory->current_rd = 0x43;
c46917bb
LR		 3141 ath_print(common, ATH_DBG_REGULATORY,
3142 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 3143 }
f078f209 3144
f74df6fb 3145 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
f1dc5600 3146 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3147
f1dc5600
S		 3148 if (eeval & AR5416_OPFLAGS_11A) {
3149 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 3150 if (ah->config.ht_enable) {
f1dc5600
S		 3151 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3152 set_bit(ATH9K_MODE_11NA_HT20,
3153 pCap->wireless_modes);
3154 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3155 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3156 pCap->wireless_modes);
3157 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3158 pCap->wireless_modes);
3159 }
f078f209 3160 }
f078f209
LR		 3161 }
3162
f1dc5600 3163 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 3164 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 3165 if (ah->config.ht_enable) {
f1dc5600
S		 3166 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3167 set_bit(ATH9K_MODE_11NG_HT20,
3168 pCap->wireless_modes);
3169 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3170 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3171 pCap->wireless_modes);
3172 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3173 pCap->wireless_modes);
3174 }
3175 }
f078f209 3176 }
f1dc5600 3177
f74df6fb 3178 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 3179 /*
3180 * For AR9271 we will temporarilly uses the rx chainmax as read from
3181 * the EEPROM.
3182 */
8147f5de 3183 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 3184 !(eeval & AR5416_OPFLAGS_11A) &&
3185 !(AR_SREV_9271(ah)))
3186 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 3187 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3188 else
d7e7d229 3189 /* Use rx_chainmask from EEPROM. */
8147f5de 3190 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 3191
d535a42a 3192 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 3193 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3194
f1dc5600
S		 3195 pCap->low_2ghz_chan = 2312;
3196 pCap->high_2ghz_chan = 2732;
f078f209 3197
f1dc5600
S		 3198 pCap->low_5ghz_chan = 4920;
3199 pCap->high_5ghz_chan = 6100;
f078f209 3200
f1dc5600
S		 3201 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3202 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3203 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3204
f1dc5600
S		 3205 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3206 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3207 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3208
2660b81a 3209 if (ah->config.ht_enable)
f1dc5600
S		 3210 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3211 else
3212 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3213
f1dc5600
S		 3214 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3215 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3216 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3217 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3218
f1dc5600
S		 3219 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3220 pCap->total_queues =
3221 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3222 else
3223 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3224
f1dc5600
S		 3225 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3226 pCap->keycache_size =
3227 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3228 else
3229 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3230
f1dc5600 3231 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f4709fdf
LR		 3232
3233 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3234 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3235 else
3236 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3237
cb33c412
SB		 3238 if (AR_SREV_9285_10_OR_LATER(ah))
3239 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3240 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3241 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3242 else
3243 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3244
f1dc5600
S		 3245 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3246 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3247 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3248 } else {
3249 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3250 }
3251
f1dc5600
S		 3252 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3253
e97275cb 3254#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 3255 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3256 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3257 ah->rfkill_gpio =
3258 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3259 ah->rfkill_polarity =
3260 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 3261
3262 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3263 }
f1dc5600 3264#endif
f078f209 3265
a3ca95fb 3266 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3267
e7594072 3268 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3269 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3270 else
3271 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3272
608b88cb 3273 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 3274 pCap->reg_cap =
3275 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3276 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3277 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3278 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3279 } else {
f1dc5600
S		 3280 pCap->reg_cap =
3281 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3282 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3283 }
f078f209 3284
ebb90cfc
SB		 3285 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3286 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3287 AR_SREV_5416(ah))
3288 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 3289
3290 pCap->num_antcfg_5ghz =
f74df6fb 3291 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3292 pCap->num_antcfg_2ghz =
f74df6fb 3293 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3294
fe12946e 3295 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 3296 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 3297 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3298 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 3299
8c8f9ba7 3300 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 3301 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3302 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 3303 } else {
766ec4a9 3304 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 3305 }
22f25d0d 3306 } else {
766ec4a9 3307 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 3308 }
f078f209
LR		 3309}
3310
cbe61d8a 3311bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3312 u32 capability, u32 *result)
f078f209 3313{
608b88cb 3314 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 3315 switch (type) {
3316 case ATH9K_CAP_CIPHER:
3317 switch (capability) {
3318 case ATH9K_CIPHER_AES_CCM:
3319 case ATH9K_CIPHER_AES_OCB:
3320 case ATH9K_CIPHER_TKIP:
3321 case ATH9K_CIPHER_WEP:
3322 case ATH9K_CIPHER_MIC:
3323 case ATH9K_CIPHER_CLR:
3324 return true;
3325 default:
3326 return false;
3327 }
3328 case ATH9K_CAP_TKIP_MIC:
3329 switch (capability) {
3330 case 0:
3331 return true;
3332 case 1:
2660b81a 3333 return (ah->sta_id1_defaults &
f1dc5600
S		 3334 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3335 false;
3336 }
3337 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 3338 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 3339 false : true;
f1dc5600
S		 3340 case ATH9K_CAP_DIVERSITY:
3341 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3342 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3343 true : false;
f1dc5600
S		 3344 case ATH9K_CAP_MCAST_KEYSRCH:
3345 switch (capability) {
3346 case 0:
3347 return true;
3348 case 1:
3349 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3350 return false;
3351 } else {
2660b81a 3352 return (ah->sta_id1_defaults &
f1dc5600
S		 3353 AR_STA_ID1_MCAST_KSRCH) ? true :
3354 false;
3355 }
3356 }
3357 return false;
f1dc5600
S		 3358 case ATH9K_CAP_TXPOW:
3359 switch (capability) {
3360 case 0:
3361 return 0;
3362 case 1:
608b88cb 3363 *result = regulatory->power_limit;
f1dc5600
S		 3364 return 0;
3365 case 2:
608b88cb 3366 *result = regulatory->max_power_level;
f1dc5600
S		 3367 return 0;
3368 case 3:
608b88cb 3369 *result = regulatory->tp_scale;
f1dc5600
S		 3370 return 0;
3371 }
3372 return false;
8bd1d07f
SB		 3373 case ATH9K_CAP_DS:
3374 return (AR_SREV_9280_20_OR_LATER(ah) &&
3375 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3376 ? false : true;
f1dc5600
S		 3377 default:
3378 return false;
f078f209 3379 }
f078f209 3380}
7322fd19 3381EXPORT_SYMBOL(ath9k_hw_getcapability);
f078f209 3382
cbe61d8a 3383bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3384 u32 capability, u32 setting, int *status)
f078f209 3385{
f1dc5600 3386 u32 v;
f078f209 3387
f1dc5600
S		 3388 switch (type) {
3389 case ATH9K_CAP_TKIP_MIC:
3390 if (setting)
2660b81a 3391 ah->sta_id1_defaults |=
f1dc5600
S		 3392 AR_STA_ID1_CRPT_MIC_ENABLE;
3393 else
2660b81a 3394 ah->sta_id1_defaults &=
f1dc5600
S		 3395 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3396 return true;
3397 case ATH9K_CAP_DIVERSITY:
3398 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3399 if (setting)
3400 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3401 else
3402 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3403 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3404 return true;
3405 case ATH9K_CAP_MCAST_KEYSRCH:
3406 if (setting)
2660b81a 3407 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3408 else
2660b81a 3409 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3410 return true;
f1dc5600
S		 3411 default:
3412 return false;
f078f209
LR		 3413 }
3414}
7322fd19 3415EXPORT_SYMBOL(ath9k_hw_setcapability);
f078f209 3416
f1dc5600
S		 3417/****************************/
3418/* GPIO / RFKILL / Antennae */
3419/****************************/
f078f209 3420
cbe61d8a 3421static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 3422 u32 gpio, u32 type)
3423{
3424 int addr;
3425 u32 gpio_shift, tmp;
f078f209 3426
f1dc5600
S		 3427 if (gpio > 11)
3428 addr = AR_GPIO_OUTPUT_MUX3;
3429 else if (gpio > 5)
3430 addr = AR_GPIO_OUTPUT_MUX2;
3431 else
3432 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3433
f1dc5600 3434 gpio_shift = (gpio % 6) * 5;
f078f209 3435
f1dc5600
S		 3436 if (AR_SREV_9280_20_OR_LATER(ah)
3437 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3438 REG_RMW(ah, addr, (type << gpio_shift),
3439 (0x1f << gpio_shift));
f078f209 3440 } else {
f1dc5600
S		 3441 tmp = REG_READ(ah, addr);
3442 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3443 tmp &= ~(0x1f << gpio_shift);
3444 tmp |= (type << gpio_shift);
3445 REG_WRITE(ah, addr, tmp);
f078f209 3446 }
f078f209
LR		 3447}
3448
cbe61d8a 3449void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 3450{
f1dc5600 3451 u32 gpio_shift;
f078f209 3452
9680e8a3 3453 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 3454
f1dc5600 3455 gpio_shift = gpio << 1;
f078f209 3456
f1dc5600
S		 3457 REG_RMW(ah,
3458 AR_GPIO_OE_OUT,
3459 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3460 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 3461}
7322fd19 3462EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 3463
cbe61d8a 3464u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 3465{
cb33c412
SB		 3466#define MS_REG_READ(x, y) \
3467 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3468
2660b81a 3469 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 3470 return 0xffffffff;
f078f209 3471
ac88b6ec
VN		 3472 if (AR_SREV_9287_10_OR_LATER(ah))
3473 return MS_REG_READ(AR9287, gpio) != 0;
3474 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 3475 return MS_REG_READ(AR9285, gpio) != 0;
3476 else if (AR_SREV_9280_10_OR_LATER(ah))
3477 return MS_REG_READ(AR928X, gpio) != 0;
3478 else
3479 return MS_REG_READ(AR, gpio) != 0;
f078f209 3480}
7322fd19 3481EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 3482
cbe61d8a 3483void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 3484 u32 ah_signal_type)
f078f209 3485{
f1dc5600 3486 u32 gpio_shift;
f078f209 3487
f1dc5600 3488 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3489
f1dc5600 3490 gpio_shift = 2 * gpio;
f078f209 3491
f1dc5600
S		 3492 REG_RMW(ah,
3493 AR_GPIO_OE_OUT,
3494 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3495 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 3496}
7322fd19 3497EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 3498
cbe61d8a 3499void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 3500{
f1dc5600
S		 3501 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3502 AR_GPIO_BIT(gpio));
f078f209 3503}
7322fd19 3504EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 3505
cbe61d8a 3506u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 3507{
f1dc5600 3508 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 3509}
7322fd19 3510EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 3511
cbe61d8a 3512void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 3513{
f1dc5600 3514 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 3515}
7322fd19 3516EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 3517
f1dc5600
S		 3518/*********************/
3519/* General Operation */
3520/*********************/
3521
cbe61d8a 3522u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 3523{
f1dc5600
S		 3524 u32 bits = REG_READ(ah, AR_RX_FILTER);
3525 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3526
f1dc5600
S		 3527 if (phybits & AR_PHY_ERR_RADAR)
3528 bits |= ATH9K_RX_FILTER_PHYRADAR;
3529 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3530 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3531
f1dc5600 3532 return bits;
f078f209 3533}
7322fd19 3534EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 3535
cbe61d8a 3536void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 3537{
f1dc5600 3538 u32 phybits;
f078f209 3539
7ea310be
S		 3540 REG_WRITE(ah, AR_RX_FILTER, bits);
3541
f1dc5600
S		 3542 phybits = 0;
3543 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3544 phybits |= AR_PHY_ERR_RADAR;
3545 if (bits & ATH9K_RX_FILTER_PHYERR)
3546 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3547 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3548
f1dc5600
S		 3549 if (phybits)
3550 REG_WRITE(ah, AR_RXCFG,
3551 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3552 else
3553 REG_WRITE(ah, AR_RXCFG,
3554 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3555}
7322fd19 3556EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 3557
cbe61d8a 3558bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 3559{
63a75b91
SB		 3560 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3561 return false;
3562
3563 ath9k_hw_init_pll(ah, NULL);
3564 return true;
f1dc5600 3565}
7322fd19 3566EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 3567
cbe61d8a 3568bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 3569{
9ecdef4b 3570 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 3571 return false;
f078f209 3572
63a75b91
SB		 3573 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3574 return false;
3575
3576 ath9k_hw_init_pll(ah, NULL);
3577 return true;
f078f209 3578}
7322fd19 3579EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 3580
8fbff4b8 3581void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 3582{
608b88cb 3583 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 3584 struct ath9k_channel *chan = ah->curchan;
5f8e077c 3585 struct ieee80211_channel *channel = chan->chan;
f078f209 3586
608b88cb 3587 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 3588
8fbff4b8 3589 ah->eep_ops->set_txpower(ah, chan,
608b88cb 3590 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 3591 channel->max_antenna_gain * 2,
3592 channel->max_power * 2,
3593 min((u32) MAX_RATE_POWER,
608b88cb 3594 (u32) regulatory->power_limit));
6f255425 3595}
7322fd19 3596EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 3597
cbe61d8a 3598void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 3599{
1510718d 3600 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
f078f209 3601}
7322fd19 3602EXPORT_SYMBOL(ath9k_hw_setmac);
f078f209 3603
cbe61d8a 3604void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 3605{
2660b81a 3606 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 3607}
7322fd19 3608EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 3609
cbe61d8a 3610void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 3611{
f1dc5600
S		 3612 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3613 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 3614}
7322fd19 3615EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 3616
f2b2143e 3617void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 3618{
1510718d
LR		 3619 struct ath_common *common = ath9k_hw_common(ah);
3620
3621 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3622 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3623 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 3624}
7322fd19 3625EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 3626
cbe61d8a 3627u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 3628{
f1dc5600 3629 u64 tsf;
f078f209 3630
f1dc5600
S		 3631 tsf = REG_READ(ah, AR_TSF_U32);
3632 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 3633
f1dc5600
S		 3634 return tsf;
3635}
7322fd19 3636EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 3637
cbe61d8a 3638void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 3639{
27abe060 3640 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 3641 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 3642}
7322fd19 3643EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 3644
cbe61d8a 3645void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 3646{
f9b604f6
GJ		 3647 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3648 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 3649 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3650 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 3651
f1dc5600
S		 3652 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3653}
7322fd19 3654EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 3655
54e4cec6 3656void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 3657{
f1dc5600 3658 if (setting)
2660b81a 3659 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 3660 else
2660b81a 3661 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 3662}
7322fd19 3663EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 3664
30cbd422
LR		 3665/*
3666 * Extend 15-bit time stamp from rx descriptor to
3667 * a full 64-bit TSF using the current h/w TSF.
3668*/
3669u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3670{
3671 u64 tsf;
3672
3673 tsf = ath9k_hw_gettsf64(ah);
3674 if ((tsf & 0x7fff) < rstamp)
3675 tsf -= 0x8000;
3676 return (tsf & ~0x7fff) | rstamp;
3677}
3678EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3679
cbe61d8a 3680bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f1dc5600 3681{
f1dc5600 3682 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
c46917bb
LR		 3683 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3684 "bad slot time %u\n", us);
2660b81a 3685 ah->slottime = (u32) -1;
f1dc5600
S		 3686 return false;
3687 } else {
3688 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
2660b81a 3689 ah->slottime = us;
f1dc5600 3690 return true;
f078f209 3691 }
f1dc5600 3692}
7322fd19 3693EXPORT_SYMBOL(ath9k_hw_setslottime);
f1dc5600 3694
25c56eec 3695void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 3696{
25c56eec 3697 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 3698 u32 macmode;
3699
25c56eec 3700 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 3701 macmode = AR_2040_JOINED_RX_CLEAR;
3702 else
3703 macmode = 0;
f078f209 3704
f1dc5600 3705 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 3706}
ff155a45
VT		 3707
3708/* HW Generic timers configuration */
3709
3710static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3711{
3712 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3713 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3714 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3715 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3716 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3717 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3718 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3719 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3720 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3721 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3722 AR_NDP2_TIMER_MODE, 0x0002},
3723 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3724 AR_NDP2_TIMER_MODE, 0x0004},
3725 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3726 AR_NDP2_TIMER_MODE, 0x0008},
3727 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3728 AR_NDP2_TIMER_MODE, 0x0010},
3729 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3730 AR_NDP2_TIMER_MODE, 0x0020},
3731 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3732 AR_NDP2_TIMER_MODE, 0x0040},
3733 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3734 AR_NDP2_TIMER_MODE, 0x0080}
3735};
3736
3737/* HW generic timer primitives */
3738
3739/* compute and clear index of rightmost 1 */
3740static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3741{
3742 u32 b;
3743
3744 b = *mask;
3745 b &= (0-b);
3746 *mask &= ~b;
3747 b *= debruijn32;
3748 b >>= 27;
3749
3750 return timer_table->gen_timer_index[b];
3751}
3752
1773912b 3753u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 3754{
3755 return REG_READ(ah, AR_TSF_L32);
3756}
7322fd19 3757EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 3758
3759struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3760 void (*trigger)(void *),
3761 void (*overflow)(void *),
3762 void *arg,
3763 u8 timer_index)
3764{
3765 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3766 struct ath_gen_timer *timer;
3767
3768 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3769
3770 if (timer == NULL) {
c46917bb
LR		 3771 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3772 "Failed to allocate memory"
3773 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 3774 return NULL;
3775 }
3776
3777 /* allocate a hardware generic timer slot */
3778 timer_table->timers[timer_index] = timer;
3779 timer->index = timer_index;
3780 timer->trigger = trigger;
3781 timer->overflow = overflow;
3782 timer->arg = arg;
3783
3784 return timer;
3785}
7322fd19 3786EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3787
cd9bf689
LR		 3788void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3789 struct ath_gen_timer *timer,
3790 u32 timer_next,
3791 u32 timer_period)
ff155a45
VT		 3792{
3793 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3794 u32 tsf;
3795
3796 BUG_ON(!timer_period);
3797
3798 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3799
3800 tsf = ath9k_hw_gettsf32(ah);
3801
c46917bb
LR		 3802 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3803 "curent tsf %x period %x"
3804 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 3805
3806 /*
3807 * Pull timer_next forward if the current TSF already passed it
3808 * because of software latency
3809 */
3810 if (timer_next < tsf)
3811 timer_next = tsf + timer_period;
3812
3813 /*
3814 * Program generic timer registers
3815 */
3816 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3817 timer_next);
3818 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3819 timer_period);
3820 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3821 gen_tmr_configuration[timer->index].mode_mask);
3822
3823 /* Enable both trigger and thresh interrupt masks */
3824 REG_SET_BIT(ah, AR_IMR_S5,
3825 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3826 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 3827}
7322fd19 3828EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3829
cd9bf689 3830void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3831{
3832 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3833
3834 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3835 (timer->index >= ATH_MAX_GEN_TIMER)) {
3836 return;
3837 }
3838
3839 /* Clear generic timer enable bits. */
3840 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3841 gen_tmr_configuration[timer->index].mode_mask);
3842
3843 /* Disable both trigger and thresh interrupt masks */
3844 REG_CLR_BIT(ah, AR_IMR_S5,
3845 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3846 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3847
3848 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3849}
7322fd19 3850EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3851
3852void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3853{
3854 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3855
3856 /* free the hardware generic timer slot */
3857 timer_table->timers[timer->index] = NULL;
3858 kfree(timer);
3859}
7322fd19 3860EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3861
3862/*
3863 * Generic Timer Interrupts handling
3864 */
3865void ath_gen_timer_isr(struct ath_hw *ah)
3866{
3867 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3868 struct ath_gen_timer *timer;
c46917bb 3869 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3870 u32 trigger_mask, thresh_mask, index;
3871
3872 /* get hardware generic timer interrupt status */
3873 trigger_mask = ah->intr_gen_timer_trigger;
3874 thresh_mask = ah->intr_gen_timer_thresh;
3875 trigger_mask &= timer_table->timer_mask.val;
3876 thresh_mask &= timer_table->timer_mask.val;
3877
3878 trigger_mask &= ~thresh_mask;
3879
3880 while (thresh_mask) {
3881 index = rightmost_index(timer_table, &thresh_mask);
3882 timer = timer_table->timers[index];
3883 BUG_ON(!timer);
c46917bb
LR		 3884 ath_print(common, ATH_DBG_HWTIMER,
3885 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 3886 timer->overflow(timer->arg);
3887 }
3888
3889 while (trigger_mask) {
3890 index = rightmost_index(timer_table, &trigger_mask);
3891 timer = timer_table->timers[index];
3892 BUG_ON(!timer);
c46917bb
LR		 3893 ath_print(common, ATH_DBG_HWTIMER,
3894 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3895 timer->trigger(timer->arg);
3896 }
3897}
7322fd19 3898EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a
LR		 3899
3900static struct {
3901 u32 version;
3902 const char * name;
3903} ath_mac_bb_names[] = {
3904 /* Devices with external radios */
3905 { AR_SREV_VERSION_5416_PCI, "5416" },
3906 { AR_SREV_VERSION_5416_PCIE, "5418" },
3907 { AR_SREV_VERSION_9100, "9100" },
3908 { AR_SREV_VERSION_9160, "9160" },
3909 /* Single-chip solutions */
3910 { AR_SREV_VERSION_9280, "9280" },
3911 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3912 { AR_SREV_VERSION_9287, "9287" },
3913 { AR_SREV_VERSION_9271, "9271" },
2da4f01a
LR		 3914};
3915
3916/* For devices with external radios */
3917static struct {
3918 u16 version;
3919 const char * name;
3920} ath_rf_names[] = {
3921 { 0, "5133" },
3922 { AR_RAD5133_SREV_MAJOR, "5133" },
3923 { AR_RAD5122_SREV_MAJOR, "5122" },
3924 { AR_RAD2133_SREV_MAJOR, "2133" },
3925 { AR_RAD2122_SREV_MAJOR, "2122" }
3926};
3927
3928/*
3929 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3930 */
f934c4d9 3931static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3932{
3933 int i;
3934
3935 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3936 if (ath_mac_bb_names[i].version == mac_bb_version) {
3937 return ath_mac_bb_names[i].name;
3938 }
3939 }
3940
3941 return "????";
3942}
2da4f01a
LR		 3943
3944/*
3945 * Return the RF name. "????" is returned if the RF is unknown.
3946 * Used for devices with external radios.
3947 */
f934c4d9 3948static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3949{
3950 int i;
3951
3952 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3953 if (ath_rf_names[i].version == rf_version) {
3954 return ath_rf_names[i].name;
3955 }
3956 }
3957
3958 return "????";
3959}
f934c4d9
LR		 3960
3961void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3962{
3963 int used;
3964
3965 /* chipsets >= AR9280 are single-chip */
3966 if (AR_SREV_9280_10_OR_LATER(ah)) {
3967 used = snprintf(hw_name, len,
3968 "Atheros AR%s Rev:%x",
3969 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3970 ah->hw_version.macRev);
3971 }
3972 else {
3973 used = snprintf(hw_name, len,
3974 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3975 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3976 ah->hw_version.macRev,
3977 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3978 AR_RADIO_SREV_MAJOR)),
3979 ah->hw_version.phyRev);
3980 }
3981
3982 hw_name[used] = '\0';
3983}
3984EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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