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ath9k: Fix MAC HW hang check for AR9003
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
f078f209
LR		 22#include <asm/unaligned.h>
23
af03abec 24#include "hw.h"
d70357d5 25#include "hw-ops.h"
cfe8cba9 26#include "rc.h"
b622a720 27#include "ar9003_mac.h"
f4701b5a 28#include "ar9003_mci.h"
362cd03f 29#include "ar9003_phy.h"
462e58f2
BG		 30#include "debug.h"
31#include "ath9k.h"
f078f209 32
cbe61d8a 33static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 34
7322fd19
LR		 35MODULE_AUTHOR("Atheros Communications");
36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38MODULE_LICENSE("Dual BSD/GPL");
39
40static int __init ath9k_init(void)
41{
42 return 0;
43}
44module_init(ath9k_init);
45
46static void __exit ath9k_exit(void)
47{
48 return;
49}
50module_exit(ath9k_exit);
51
d70357d5
LR		 52/* Private hardware callbacks */
53
54static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
55{
56 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
57}
58
64773964
LR		 59static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
60 struct ath9k_channel *chan)
61{
62 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
63}
64
991312d8
LR		 65static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
66{
67 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
68 return;
69
70 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
71}
72
e36b27af
LR		 73static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
74{
75 /* You will not have this callback if using the old ANI */
76 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
77 return;
78
79 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
80}
81
f1dc5600
S		 82/********************/
83/* Helper Functions */
84/********************/
f078f209 85
462e58f2
BG		 86#ifdef CONFIG_ATH9K_DEBUGFS
87
462e58f2
BG		 88#endif
89
90
dfdac8ac 91static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 92{
dfdac8ac 93 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 94 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 95 unsigned int clockrate;
cbe61d8a 96
087b6ff6
FF		 97 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
98 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
99 clockrate = 117;
e4744ec7 100 else if (!chan) /* should really check for CCK instead */
dfdac8ac 101 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 102 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 103 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
104 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
105 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 106 else
dfdac8ac
FF		 107 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
108
beae416b
MN		 109 if (chan) {
110 if (IS_CHAN_HT40(chan))
111 clockrate *= 2;
e4744ec7 112 if (IS_CHAN_HALF_RATE(chan))
906c7205 113 clockrate /= 2;
e4744ec7 114 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 115 clockrate /= 4;
116 }
117
dfdac8ac 118 common->clockrate = clockrate;
f1dc5600
S		 119}
120
cbe61d8a 121static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 122{
dfdac8ac 123 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 124
dfdac8ac 125 return usecs * common->clockrate;
f1dc5600 126}
f078f209 127
0caa7b14 128bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 129{
130 int i;
131
0caa7b14
S		 132 BUG_ON(timeout < AH_TIME_QUANTUM);
133
134 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 135 if ((REG_READ(ah, reg) & mask) == val)
136 return true;
137
138 udelay(AH_TIME_QUANTUM);
139 }
04bd4638 140
d2182b69 141 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 142 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
143 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 144
f1dc5600 145 return false;
f078f209 146}
7322fd19 147EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 148
7c5adc8d
FF		 149void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
150 int hw_delay)
151{
1a5e6326 152 hw_delay /= 10;
7c5adc8d
FF		 153
154 if (IS_CHAN_HALF_RATE(chan))
155 hw_delay *= 2;
156 else if (IS_CHAN_QUARTER_RATE(chan))
157 hw_delay *= 4;
158
159 udelay(hw_delay + BASE_ACTIVATE_DELAY);
160}
161
0166b4be 162void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 163 int column, unsigned int *writecnt)
164{
165 int r;
166
167 ENABLE_REGWRITE_BUFFER(ah);
168 for (r = 0; r < array->ia_rows; r++) {
169 REG_WRITE(ah, INI_RA(array, r, 0),
170 INI_RA(array, r, column));
171 DO_DELAY(*writecnt);
172 }
173 REGWRITE_BUFFER_FLUSH(ah);
174}
175
f078f209
LR		 176u32 ath9k_hw_reverse_bits(u32 val, u32 n)
177{
178 u32 retval;
179 int i;
180
181 for (i = 0, retval = 0; i < n; i++) {
182 retval = (retval << 1) | (val & 1);
183 val >>= 1;
184 }
185 return retval;
186}
187
cbe61d8a 188u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 189 u8 phy, int kbps,
f1dc5600
S		 190 u32 frameLen, u16 rateix,
191 bool shortPreamble)
f078f209 192{
f1dc5600 193 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 194
f1dc5600
S		 195 if (kbps == 0)
196 return 0;
f078f209 197
545750d3 198 switch (phy) {
46d14a58 199 case WLAN_RC_PHY_CCK:
f1dc5600 200 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 201 if (shortPreamble)
f1dc5600
S		 202 phyTime >>= 1;
203 numBits = frameLen << 3;
204 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
205 break;
46d14a58 206 case WLAN_RC_PHY_OFDM:
2660b81a 207 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 208 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
209 numBits = OFDM_PLCP_BITS + (frameLen << 3);
210 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
211 txTime = OFDM_SIFS_TIME_QUARTER
212 + OFDM_PREAMBLE_TIME_QUARTER
213 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 214 } else if (ah->curchan &&
215 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 216 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
217 numBits = OFDM_PLCP_BITS + (frameLen << 3);
218 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
219 txTime = OFDM_SIFS_TIME_HALF +
220 OFDM_PREAMBLE_TIME_HALF
221 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
222 } else {
223 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
224 numBits = OFDM_PLCP_BITS + (frameLen << 3);
225 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
226 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
227 + (numSymbols * OFDM_SYMBOL_TIME);
228 }
229 break;
230 default:
3800276a
JP		 231 ath_err(ath9k_hw_common(ah),
232 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 233 txTime = 0;
234 break;
235 }
f078f209 236
f1dc5600
S		 237 return txTime;
238}
7322fd19 239EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 240
cbe61d8a 241void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 242 struct ath9k_channel *chan,
243 struct chan_centers *centers)
f078f209 244{
f1dc5600 245 int8_t extoff;
f078f209 246
f1dc5600
S		 247 if (!IS_CHAN_HT40(chan)) {
248 centers->ctl_center = centers->ext_center =
249 centers->synth_center = chan->channel;
250 return;
f078f209 251 }
f078f209 252
8896934c 253 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 254 centers->synth_center =
255 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
256 extoff = 1;
257 } else {
258 centers->synth_center =
259 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
260 extoff = -1;
261 }
f078f209 262
f1dc5600
S		 263 centers->ctl_center =
264 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 265 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 266 centers->ext_center =
6420014c 267 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 268}
269
f1dc5600
S		 270/******************/
271/* Chip Revisions */
272/******************/
273
cbe61d8a 274static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 275{
f1dc5600 276 u32 val;
f078f209 277
ecb1d385
VT		 278 switch (ah->hw_version.devid) {
279 case AR5416_AR9100_DEVID:
280 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
281 break;
3762561a
GJ		 282 case AR9300_DEVID_AR9330:
283 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
284 if (ah->get_mac_revision) {
285 ah->hw_version.macRev = ah->get_mac_revision();
286 } else {
287 val = REG_READ(ah, AR_SREV);
288 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
289 }
290 return;
ecb1d385
VT		 291 case AR9300_DEVID_AR9340:
292 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
293 val = REG_READ(ah, AR_SREV);
294 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
295 return;
813831dc
GJ		 296 case AR9300_DEVID_QCA955X:
297 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
298 return;
ecb1d385
VT		 299 }
300
f1dc5600 301 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 302
f1dc5600
S		 303 if (val == 0xFF) {
304 val = REG_READ(ah, AR_SREV);
d535a42a
S		 305 ah->hw_version.macVersion =
306 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
307 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 308
77fac465 309 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 310 ah->is_pciexpress = true;
311 else
312 ah->is_pciexpress = (val &
313 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 314 } else {
315 if (!AR_SREV_9100(ah))
d535a42a 316 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 317
d535a42a 318 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 319
d535a42a 320 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 321 ah->is_pciexpress = true;
f1dc5600 322 }
f078f209
LR		 323}
324
f1dc5600
S		 325/************************************/
326/* HW Attach, Detach, Init Routines */
327/************************************/
328
cbe61d8a 329static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 330{
040b74f7 331 if (!AR_SREV_5416(ah))
f1dc5600 332 return;
f078f209 333
f1dc5600
S		 334 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
335 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
336 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
337 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
338 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
339 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
340 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
341 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
342 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 343
f1dc5600 344 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 345}
346
1f3f0618 347/* This should work for all families including legacy */
cbe61d8a 348static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 349{
c46917bb 350 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 351 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 352 u32 regHold[2];
07b2fa5a
JP		 353 static const u32 patternData[4] = {
354 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
355 };
1f3f0618 356 int i, j, loop_max;
f078f209 357
1f3f0618
SB		 358 if (!AR_SREV_9300_20_OR_LATER(ah)) {
359 loop_max = 2;
360 regAddr[1] = AR_PHY_BASE + (8 << 2);
361 } else
362 loop_max = 1;
363
364 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 365 u32 addr = regAddr[i];
366 u32 wrData, rdData;
f078f209 367
f1dc5600
S		 368 regHold[i] = REG_READ(ah, addr);
369 for (j = 0; j < 0x100; j++) {
370 wrData = (j << 16) | j;
371 REG_WRITE(ah, addr, wrData);
372 rdData = REG_READ(ah, addr);
373 if (rdData != wrData) {
3800276a
JP		 374 ath_err(common,
375 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
376 addr, wrData, rdData);
f1dc5600
S		 377 return false;
378 }
379 }
380 for (j = 0; j < 4; j++) {
381 wrData = patternData[j];
382 REG_WRITE(ah, addr, wrData);
383 rdData = REG_READ(ah, addr);
384 if (wrData != rdData) {
3800276a
JP		 385 ath_err(common,
386 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
387 addr, wrData, rdData);
f1dc5600
S		 388 return false;
389 }
f078f209 390 }
f1dc5600 391 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 392 }
f1dc5600 393 udelay(100);
cbe61d8a 394
f078f209
LR		 395 return true;
396}
397
b8b0f377 398static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 399{
689e756f
FF		 400 ah->config.dma_beacon_response_time = 1;
401 ah->config.sw_beacon_response_time = 6;
2660b81a
S		 402 ah->config.ack_6mb = 0x0;
403 ah->config.cwm_ignore_extcca = 0;
2660b81a 404 ah->config.analog_shiftreg = 1;
f078f209 405
0ce024cb 406 ah->config.rx_intr_mitigation = true;
6158425b
LR		 407
408 /*
409 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
410 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
411 * This means we use it for all AR5416 devices, and the few
412 * minor PCI AR9280 devices out there.
413 *
414 * Serialization is required because these devices do not handle
415 * well the case of two concurrent reads/writes due to the latency
416 * involved. During one read/write another read/write can be issued
417 * on another CPU while the previous read/write may still be working
418 * on our hardware, if we hit this case the hardware poops in a loop.
419 * We prevent this by serializing reads and writes.
420 *
421 * This issue is not present on PCI-Express devices or pre-AR5416
422 * devices (legacy, 802.11abg).
423 */
424 if (num_possible_cpus() > 1)
2d6a5e95 425 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 426}
427
50aca25b 428static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 429{
608b88cb
LR		 430 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
431
432 regulatory->country_code = CTRY_DEFAULT;
433 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 434
d535a42a 435 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 436 ah->hw_version.subvendorid = 0;
f078f209 437
16f2411f
FF		 438 ah->sta_id1_defaults =
439 AR_STA_ID1_CRPT_MIC_ENABLE |
440 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 441 if (AR_SREV_9100(ah))
442 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
e3f2acc7 443 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 444 ah->globaltxtimeout = (u32) -1;
cbdec975 445 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 446 ah->htc_reset_init = true;
f078f209
LR		 447}
448
cbe61d8a 449static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 450{
1510718d 451 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 452 u32 sum;
453 int i;
454 u16 eeval;
07b2fa5a 455 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 456
457 sum = 0;
458 for (i = 0; i < 3; i++) {
49101676 459 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 460 sum += eeval;
1510718d
LR		 461 common->macaddr[2 * i] = eeval >> 8;
462 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 463 }
d8baa939 464 if (sum == 0 || sum == 0xffff * 3)
f078f209 465 return -EADDRNOTAVAIL;
f078f209
LR		 466
467 return 0;
468}
469
f637cfd6 470static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 471{
6cae913d 472 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 473 int ecode;
f078f209 474
6cae913d 475 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 476 if (!ath9k_hw_chip_test(ah))
477 return -ENODEV;
478 }
f078f209 479
ebd5a14a
LR		 480 if (!AR_SREV_9300_20_OR_LATER(ah)) {
481 ecode = ar9002_hw_rf_claim(ah);
482 if (ecode != 0)
483 return ecode;
484 }
f078f209 485
f637cfd6 486 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 487 if (ecode != 0)
488 return ecode;
7d01b221 489
d2182b69 490 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 491 ah->eep_ops->get_eeprom_ver(ah),
492 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 493
e323300d 494 ath9k_hw_ani_init(ah);
f078f209 495
d3b371cb
SM		 496 /*
497 * EEPROM needs to be initialized before we do this.
498 * This is required for regulatory compliance.
499 */
0c7c2bb4 500 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 501 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
502 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 503 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
504 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 505 }
506 }
507
f078f209
LR		 508 return 0;
509}
510
c1b976d2 511static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 512{
c1b976d2
FF		 513 if (!AR_SREV_9300_20_OR_LATER(ah))
514 return ar9002_hw_attach_ops(ah);
515
516 ar9003_hw_attach_ops(ah);
517 return 0;
aa4058ae
LR		 518}
519
d70357d5
LR		 520/* Called for all hardware families */
521static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 522{
c46917bb 523 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 524 int r = 0;
aa4058ae 525
ac45c12d
SB		 526 ath9k_hw_read_revisions(ah);
527
0a8d7cb0
SB		 528 /*
529 * Read back AR_WA into a permanent copy and set bits 14 and 17.
530 * We need to do this to avoid RMW of this register. We cannot
531 * read the reg when chip is asleep.
532 */
27251e00
SM		 533 if (AR_SREV_9300_20_OR_LATER(ah)) {
534 ah->WARegVal = REG_READ(ah, AR_WA);
535 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
536 AR_WA_ASPM_TIMER_BASED_DISABLE);
537 }
0a8d7cb0 538
aa4058ae 539 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 540 ath_err(common, "Couldn't reset chip\n");
95fafca2 541 return -EIO;
aa4058ae
LR		 542 }
543
a4a2954f
SM		 544 if (AR_SREV_9565(ah)) {
545 ah->WARegVal |= AR_WA_BIT22;
546 REG_WRITE(ah, AR_WA, ah->WARegVal);
547 }
548
bab1f62e
LR		 549 ath9k_hw_init_defaults(ah);
550 ath9k_hw_init_config(ah);
551
c1b976d2
FF		 552 r = ath9k_hw_attach_ops(ah);
553 if (r)
554 return r;
d70357d5 555
9ecdef4b 556 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 557 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 558 return -EIO;
aa4058ae
LR		 559 }
560
f3eef645 561 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
aa4058ae 562 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
7508b657 563 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
4c85ab11 564 !ah->is_pciexpress)) {
aa4058ae
LR		 565 ah->config.serialize_regmode =
566 SER_REG_MODE_ON;
567 } else {
568 ah->config.serialize_regmode =
569 SER_REG_MODE_OFF;
570 }
571 }
572
d2182b69 573 ath_dbg(common, RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 574 ah->config.serialize_regmode);
575
f4709fdf
LR		 576 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
577 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
578 else
579 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
580
6da5a720
FF		 581 switch (ah->hw_version.macVersion) {
582 case AR_SREV_VERSION_5416_PCI:
583 case AR_SREV_VERSION_5416_PCIE:
584 case AR_SREV_VERSION_9160:
585 case AR_SREV_VERSION_9100:
586 case AR_SREV_VERSION_9280:
587 case AR_SREV_VERSION_9285:
588 case AR_SREV_VERSION_9287:
589 case AR_SREV_VERSION_9271:
590 case AR_SREV_VERSION_9300:
2c8e5937 591 case AR_SREV_VERSION_9330:
6da5a720 592 case AR_SREV_VERSION_9485:
bca04689 593 case AR_SREV_VERSION_9340:
423e38e8 594 case AR_SREV_VERSION_9462:
2b943a33 595 case AR_SREV_VERSION_9550:
77fac465 596 case AR_SREV_VERSION_9565:
6da5a720
FF		 597 break;
598 default:
3800276a
JP		 599 ath_err(common,
600 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
601 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 602 return -EOPNOTSUPP;
aa4058ae
LR		 603 }
604
2c8e5937 605 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 606 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 607 ah->is_pciexpress = false;
608
aa4058ae 609 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 610 ath9k_hw_init_cal_settings(ah);
611
612 ah->ani_function = ATH9K_ANI_ALL;
e36b27af
LR		 613 if (!AR_SREV_9300_20_OR_LATER(ah))
614 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae 615
69ce674b 616 if (!ah->is_pciexpress)
aa4058ae
LR		 617 ath9k_hw_disablepcie(ah);
618
f637cfd6 619 r = ath9k_hw_post_init(ah);
aa4058ae 620 if (r)
95fafca2 621 return r;
aa4058ae
LR		 622
623 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 624 r = ath9k_hw_fill_cap_info(ah);
625 if (r)
626 return r;
627
4f3acf81
LR		 628 r = ath9k_hw_init_macaddr(ah);
629 if (r) {
3800276a 630 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 631 return r;
f078f209
LR		 632 }
633
d7e7d229 634 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 635 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 636 else
2660b81a 637 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 638
4598702d 639 ath9k_hw_init_hang_checks(ah);
f078f209 640
211f5859
LR		 641 common->state = ATH_HW_INITIALIZED;
642
4f3acf81 643 return 0;
f078f209
LR		 644}
645
d70357d5 646int ath9k_hw_init(struct ath_hw *ah)
f078f209 647{
d70357d5
LR		 648 int ret;
649 struct ath_common *common = ath9k_hw_common(ah);
f078f209 650
77fac465 651 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 652 switch (ah->hw_version.devid) {
653 case AR5416_DEVID_PCI:
654 case AR5416_DEVID_PCIE:
655 case AR5416_AR9100_DEVID:
656 case AR9160_DEVID_PCI:
657 case AR9280_DEVID_PCI:
658 case AR9280_DEVID_PCIE:
659 case AR9285_DEVID_PCIE:
db3cc53a
SB		 660 case AR9287_DEVID_PCI:
661 case AR9287_DEVID_PCIE:
d70357d5 662 case AR2427_DEVID_PCIE:
db3cc53a 663 case AR9300_DEVID_PCIE:
3050c914 664 case AR9300_DEVID_AR9485_PCIE:
999a7a88 665 case AR9300_DEVID_AR9330:
bca04689 666 case AR9300_DEVID_AR9340:
2b943a33 667 case AR9300_DEVID_QCA955X:
5a63ef0f 668 case AR9300_DEVID_AR9580:
423e38e8 669 case AR9300_DEVID_AR9462:
d4e5979c 670 case AR9485_DEVID_AR1111:
77fac465 671 case AR9300_DEVID_AR9565:
d70357d5
LR		 672 break;
673 default:
674 if (common->bus_ops->ath_bus_type == ATH_USB)
675 break;
3800276a
JP		 676 ath_err(common, "Hardware device ID 0x%04x not supported\n",
677 ah->hw_version.devid);
d70357d5
LR		 678 return -EOPNOTSUPP;
679 }
f078f209 680
d70357d5
LR		 681 ret = __ath9k_hw_init(ah);
682 if (ret) {
3800276a
JP		 683 ath_err(common,
684 "Unable to initialize hardware; initialization status: %d\n",
685 ret);
d70357d5
LR		 686 return ret;
687 }
f078f209 688
d70357d5 689 return 0;
f078f209 690}
d70357d5 691EXPORT_SYMBOL(ath9k_hw_init);
f078f209 692
cbe61d8a 693static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 694{
7d0d0df0
S		 695 ENABLE_REGWRITE_BUFFER(ah);
696
f1dc5600
S		 697 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
698 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 699
f1dc5600
S		 700 REG_WRITE(ah, AR_QOS_NO_ACK,
701 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
702 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
703 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
704
705 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
706 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
707 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
708 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
709 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 710
711 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 712}
713
b84628eb 714u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 715{
f18e3c6b
MSS		 716 struct ath_common *common = ath9k_hw_common(ah);
717 int i = 0;
718
ca7a4deb
FF		 719 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
720 udelay(100);
721 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 722
f18e3c6b
MSS		 723 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
724
ca7a4deb 725 udelay(100);
b1415819 726
f18e3c6b
MSS		 727 if (WARN_ON_ONCE(i >= 100)) {
728 ath_err(common, "PLL4 meaurement not done\n");
729 break;
730 }
731
732 i++;
733 }
734
ca7a4deb 735 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 736}
737EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
738
cbe61d8a 739static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 740 struct ath9k_channel *chan)
f078f209 741{
d09b17f7
VT		 742 u32 pll;
743
a4a2954f 744 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 745 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
746 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
747 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
748 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
749 AR_CH0_DPLL2_KD, 0x40);
750 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
751 AR_CH0_DPLL2_KI, 0x4);
22983c30 752
3dfd7f60
VT		 753 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
754 AR_CH0_BB_DPLL1_REFDIV, 0x5);
755 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
756 AR_CH0_BB_DPLL1_NINI, 0x58);
757 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
758 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 759
760 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 761 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
763 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 764 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 765 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 766
3dfd7f60 767 /* program BB PLL phase_shift to 0x6 */
22983c30 768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 769 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
770
771 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
772 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 773 udelay(1000);
a5415d62
GJ		 774 } else if (AR_SREV_9330(ah)) {
775 u32 ddr_dpll2, pll_control2, kd;
776
777 if (ah->is_clk_25mhz) {
778 ddr_dpll2 = 0x18e82f01;
779 pll_control2 = 0xe04a3d;
780 kd = 0x1d;
781 } else {
782 ddr_dpll2 = 0x19e82f01;
783 pll_control2 = 0x886666;
784 kd = 0x3d;
785 }
786
787 /* program DDR PLL ki and kd value */
788 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
789
790 /* program DDR PLL phase_shift */
791 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
792 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
793
794 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
795 udelay(1000);
796
797 /* program refdiv, nint, frac to RTC register */
798 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
799
800 /* program BB PLL kd and ki value */
801 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
802 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
803
804 /* program BB PLL phase_shift */
805 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
806 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
fc05a317 807 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 808 u32 regval, pll2_divint, pll2_divfrac, refdiv;
809
810 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
811 udelay(1000);
812
813 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
814 udelay(100);
815
816 if (ah->is_clk_25mhz) {
817 pll2_divint = 0x54;
818 pll2_divfrac = 0x1eb85;
819 refdiv = 3;
820 } else {
fc05a317
GJ		 821 if (AR_SREV_9340(ah)) {
822 pll2_divint = 88;
823 pll2_divfrac = 0;
824 refdiv = 5;
825 } else {
826 pll2_divint = 0x11;
827 pll2_divfrac = 0x26666;
828 refdiv = 1;
829 }
0b488ac6
VT		 830 }
831
832 regval = REG_READ(ah, AR_PHY_PLL_MODE);
833 regval |= (0x1 << 16);
834 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
835 udelay(100);
836
837 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
838 (pll2_divint << 18) | pll2_divfrac);
839 udelay(100);
840
841 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317
GJ		 842 if (AR_SREV_9340(ah))
843 regval = (regval & 0x80071fff) | (0x1 << 30) |
844 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
845 else
846 regval = (regval & 0x80071fff) | (0x3 << 30) |
847 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
0b488ac6
VT		 848 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
849 REG_WRITE(ah, AR_PHY_PLL_MODE,
850 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
851 udelay(1000);
22983c30 852 }
d09b17f7
VT		 853
854 pll = ath9k_hw_compute_pll_control(ah, chan);
8565f8bf
SM		 855 if (AR_SREV_9565(ah))
856 pll |= 0x40000;
d03a66c1 857 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 858
fc05a317
GJ		 859 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
860 AR_SREV_9550(ah))
3dfd7f60
VT		 861 udelay(1000);
862
c75724d1
LR		 863 /* Switch the core clock for ar9271 to 117Mhz */
864 if (AR_SREV_9271(ah)) {
25e2ab17
S		 865 udelay(500);
866 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 867 }
868
f1dc5600
S		 869 udelay(RTC_PLL_SETTLE_DELAY);
870
871 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6 872
fc05a317 873 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 874 if (ah->is_clk_25mhz) {
875 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
876 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
877 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
878 } else {
879 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
880 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
881 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
882 }
883 udelay(100);
884 }
f078f209
LR		 885}
886
cbe61d8a 887static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 888 enum nl80211_iftype opmode)
f078f209 889{
79d1d2b8 890 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 891 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 892 AR_IMR_TXURN |
893 AR_IMR_RXERR |
894 AR_IMR_RXORN |
895 AR_IMR_BCNMISC;
f078f209 896
3b8a0577 897 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
79d1d2b8
VT		 898 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
899
66860240
VT		 900 if (AR_SREV_9300_20_OR_LATER(ah)) {
901 imr_reg |= AR_IMR_RXOK_HP;
902 if (ah->config.rx_intr_mitigation)
903 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
904 else
905 imr_reg |= AR_IMR_RXOK_LP;
f078f209 906
66860240
VT		 907 } else {
908 if (ah->config.rx_intr_mitigation)
909 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
910 else
911 imr_reg |= AR_IMR_RXOK;
912 }
f078f209 913
66860240
VT		 914 if (ah->config.tx_intr_mitigation)
915 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
916 else
917 imr_reg |= AR_IMR_TXOK;
f078f209 918
7d0d0df0
S		 919 ENABLE_REGWRITE_BUFFER(ah);
920
152d530d 921 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 922 ah->imrs2_reg |= AR_IMR_S2_GTT;
923 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 924
f1dc5600
S		 925 if (!AR_SREV_9100(ah)) {
926 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 927 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 928 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
929 }
66860240 930
7d0d0df0 931 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 932
66860240
VT		 933 if (AR_SREV_9300_20_OR_LATER(ah)) {
934 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
935 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
936 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
937 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
938 }
f078f209
LR		 939}
940
b6ba41bb
FF		 941static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
942{
943 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
944 val = min(val, (u32) 0xFFFF);
945 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
946}
947
0005baf4 948static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 949{
0005baf4
FF		 950 u32 val = ath9k_hw_mac_to_clks(ah, us);
951 val = min(val, (u32) 0xFFFF);
952 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 953}
954
0005baf4 955static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 956{
0005baf4
FF		 957 u32 val = ath9k_hw_mac_to_clks(ah, us);
958 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
959 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
960}
961
962static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
963{
964 u32 val = ath9k_hw_mac_to_clks(ah, us);
965 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
966 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 967}
f1dc5600 968
cbe61d8a 969static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 970{
f078f209 971 if (tu > 0xFFFF) {
d2182b69
JP		 972 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
973 tu);
2660b81a 974 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 975 return false;
976 } else {
977 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 978 ah->globaltxtimeout = tu;
f078f209
LR		 979 return true;
980 }
981}
982
0005baf4 983void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 984{
b6ba41bb 985 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 986 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 987 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 988 int slottime;
0005baf4 989 int sifstime;
b6ba41bb
FF		 990 int rx_lat = 0, tx_lat = 0, eifs = 0;
991 u32 reg;
0005baf4 992
d2182b69 993 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 994 ah->misc_mode);
f078f209 995
b6ba41bb
FF		 996 if (!chan)
997 return;
998
2660b81a 999 if (ah->misc_mode != 0)
ca7a4deb 1000 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1001
81a91d57
RM		 1002 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1003 rx_lat = 41;
1004 else
1005 rx_lat = 37;
b6ba41bb
FF		 1006 tx_lat = 54;
1007
e88e4861
FF		 1008 if (IS_CHAN_5GHZ(chan))
1009 sifstime = 16;
1010 else
1011 sifstime = 10;
1012
b6ba41bb
FF		 1013 if (IS_CHAN_HALF_RATE(chan)) {
1014 eifs = 175;
1015 rx_lat *= 2;
1016 tx_lat *= 2;
1017 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1018 tx_lat += 11;
1019
92367fe7 1020 sifstime = 32;
e115b7ec 1021 ack_offset = 16;
b6ba41bb 1022 slottime = 13;
b6ba41bb
FF		 1023 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1024 eifs = 340;
81a91d57 1025 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1026 tx_lat *= 4;
1027 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1028 tx_lat += 22;
1029
92367fe7 1030 sifstime = 64;
e115b7ec 1031 ack_offset = 32;
b6ba41bb 1032 slottime = 21;
b6ba41bb 1033 } else {
a7be039d
RM		 1034 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1035 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1036 reg = AR_USEC_ASYNC_FIFO;
1037 } else {
1038 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1039 common->clockrate;
1040 reg = REG_READ(ah, AR_USEC);
1041 }
b6ba41bb
FF		 1042 rx_lat = MS(reg, AR_USEC_RX_LAT);
1043 tx_lat = MS(reg, AR_USEC_TX_LAT);
1044
1045 slottime = ah->slottime;
b6ba41bb 1046 }
0005baf4 1047
e239d859 1048 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1049 slottime += 3 * ah->coverage_class;
1050 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1051 ctstimeout = acktimeout;
42c4568a
FF		 1052
1053 /*
1054 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1055 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1056 * This was initially only meant to work around an issue with delayed
1057 * BA frames in some implementations, but it has been found to fix ACK
1058 * timeout issues in other cases as well.
1059 */
e4744ec7 1060 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1061 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1062 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1063 ctstimeout += 48 - sifstime - ah->slottime;
1064 }
1065
b6ba41bb
FF		 1066 ath9k_hw_set_sifs_time(ah, sifstime);
1067 ath9k_hw_setslottime(ah, slottime);
0005baf4 1068 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1069 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1070 if (ah->globaltxtimeout != (u32) -1)
1071 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1072
1073 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1074 REG_RMW(ah, AR_USEC,
1075 (common->clockrate - 1) |
1076 SM(rx_lat, AR_USEC_RX_LAT) |
1077 SM(tx_lat, AR_USEC_TX_LAT),
1078 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1079
f1dc5600 1080}
0005baf4 1081EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1082
285f2dda 1083void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1084{
211f5859
LR		 1085 struct ath_common *common = ath9k_hw_common(ah);
1086
736b3a27 1087 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1088 return;
211f5859 1089
9ecdef4b 1090 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1091}
285f2dda 1092EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1093
f1dc5600
S		 1094/*******/
1095/* INI */
1096/*******/
1097
8fe65368 1098u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1099{
1100 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1101
6b21fd20 1102 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1103 ctl |= CTL_11G;
1104 else
1105 ctl |= CTL_11A;
1106
1107 return ctl;
1108}
1109
f1dc5600
S		 1110/****************************************/
1111/* Reset and Channel Switching Routines */
1112/****************************************/
f1dc5600 1113
cbe61d8a 1114static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1115{
57b32227 1116 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1117 int txbuf_size;
f1dc5600 1118
7d0d0df0
S		 1119 ENABLE_REGWRITE_BUFFER(ah);
1120
d7e7d229
LR		 1121 /*
1122 * set AHB_MODE not to do cacheline prefetches
1123 */
ca7a4deb
FF		 1124 if (!AR_SREV_9300_20_OR_LATER(ah))
1125 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1126
d7e7d229
LR		 1127 /*
1128 * let mac dma reads be in 128 byte chunks
1129 */
ca7a4deb 1130 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1131
7d0d0df0 1132 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1133
d7e7d229
LR		 1134 /*
1135 * Restore TX Trigger Level to its pre-reset value.
1136 * The initial value depends on whether aggregation is enabled, and is
1137 * adjusted whenever underruns are detected.
1138 */
57b32227
FF		 1139 if (!AR_SREV_9300_20_OR_LATER(ah))
1140 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1141
7d0d0df0 1142 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1143
d7e7d229
LR		 1144 /*
1145 * let mac dma writes be in 128 byte chunks
1146 */
ca7a4deb 1147 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1148
d7e7d229
LR		 1149 /*
1150 * Setup receive FIFO threshold to hold off TX activities
1151 */
f1dc5600
S		 1152 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1153
57b32227
FF		 1154 if (AR_SREV_9300_20_OR_LATER(ah)) {
1155 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1156 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1157
1158 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1159 ah->caps.rx_status_len);
1160 }
1161
d7e7d229
LR		 1162 /*
1163 * reduce the number of usable entries in PCU TXBUF to avoid
1164 * wrap around issues.
1165 */
f1dc5600 1166 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1167 /* For AR9285 the number of Fifos are reduced to half.
1168 * So set the usable tx buf size also to half to
1169 * avoid data/delimiter underruns
1170 */
86c157b3
FF		 1171 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1172 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1173 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1174 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1175 } else {
1176 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1177 }
744d4025 1178
86c157b3
FF		 1179 if (!AR_SREV_9271(ah))
1180 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1181
7d0d0df0 1182 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1183
744d4025
VT		 1184 if (AR_SREV_9300_20_OR_LATER(ah))
1185 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1186}
1187
cbe61d8a 1188static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1189{
ca7a4deb
FF		 1190 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1191 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1192
f1dc5600 1193 switch (opmode) {
d97809db 1194 case NL80211_IFTYPE_ADHOC:
ca7a4deb 1195 set |= AR_STA_ID1_ADHOC;
f1dc5600 1196 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1197 break;
2664d666 1198 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1199 case NL80211_IFTYPE_AP:
1200 set |= AR_STA_ID1_STA_AP;
1201 /* fall through */
d97809db 1202 case NL80211_IFTYPE_STATION:
ca7a4deb 1203 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1204 break;
5f841b41 1205 default:
ca7a4deb
FF		 1206 if (!ah->is_monitoring)
1207 set = 0;
5f841b41 1208 break;
f1dc5600 1209 }
ca7a4deb 1210 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1211}
1212
8fe65368
LR		 1213void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1214 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1215{
1216 u32 coef_exp, coef_man;
1217
1218 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1219 if ((coef_scaled >> coef_exp) & 0x1)
1220 break;
1221
1222 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1223
1224 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1225
1226 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1227 *coef_exponent = coef_exp - 16;
1228}
1229
d7df7a55
SM		 1230/* AR9330 WAR:
1231 * call external reset function to reset WMAC if:
1232 * - doing a cold reset
1233 * - we have pending frames in the TX queues.
1234 */
1235static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1236{
1237 int i, npend = 0;
1238
1239 for (i = 0; i < AR_NUM_QCU; i++) {
1240 npend = ath9k_hw_numtxpending(ah, i);
1241 if (npend)
1242 break;
1243 }
1244
1245 if (ah->external_reset &&
1246 (npend || type == ATH9K_RESET_COLD)) {
1247 int reset_err = 0;
1248
1249 ath_dbg(ath9k_hw_common(ah), RESET,
1250 "reset MAC via external reset\n");
1251
1252 reset_err = ah->external_reset();
1253 if (reset_err) {
1254 ath_err(ath9k_hw_common(ah),
1255 "External reset failed, err=%d\n",
1256 reset_err);
1257 return false;
1258 }
1259
1260 REG_WRITE(ah, AR_RTC_RESET, 1);
1261 }
1262
1263 return true;
1264}
1265
cbe61d8a 1266static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1267{
1268 u32 rst_flags;
1269 u32 tmpReg;
1270
70768496 1271 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1272 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1273 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1274 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1275 }
1276
7d0d0df0
S		 1277 ENABLE_REGWRITE_BUFFER(ah);
1278
9a658d2b
LR		 1279 if (AR_SREV_9300_20_OR_LATER(ah)) {
1280 REG_WRITE(ah, AR_WA, ah->WARegVal);
1281 udelay(10);
1282 }
1283
f1dc5600
S		 1284 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1285 AR_RTC_FORCE_WAKE_ON_INT);
1286
1287 if (AR_SREV_9100(ah)) {
1288 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1289 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1290 } else {
1291 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1292 if (AR_SREV_9340(ah))
1293 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1294 else
1295 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1296 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1297
1298 if (tmpReg) {
42d5bc3f 1299 u32 val;
f1dc5600 1300 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1301
1302 val = AR_RC_HOSTIF;
1303 if (!AR_SREV_9300_20_OR_LATER(ah))
1304 val |= AR_RC_AHB;
1305 REG_WRITE(ah, AR_RC, val);
1306
1307 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1308 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1309
1310 rst_flags = AR_RTC_RC_MAC_WARM;
1311 if (type == ATH9K_RESET_COLD)
1312 rst_flags |= AR_RTC_RC_MAC_COLD;
1313 }
1314
7d95847c 1315 if (AR_SREV_9330(ah)) {
d7df7a55
SM		 1316 if (!ath9k_hw_ar9330_reset_war(ah, type))
1317 return false;
7d95847c
GJ		 1318 }
1319
3863495b 1320 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1321 ar9003_mci_check_gpm_offset(ah);
3863495b 1322
d03a66c1 1323 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1324
1325 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1326
4dc78c43
SM		 1327 if (AR_SREV_9300_20_OR_LATER(ah))
1328 udelay(50);
1329 else if (AR_SREV_9100(ah))
1330 udelay(10000);
1331 else
1332 udelay(100);
f1dc5600 1333
d03a66c1 1334 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1335 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1336 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1337 return false;
1338 }
1339
1340 if (!AR_SREV_9100(ah))
1341 REG_WRITE(ah, AR_RC, 0);
1342
f1dc5600
S		 1343 if (AR_SREV_9100(ah))
1344 udelay(50);
1345
1346 return true;
1347}
1348
cbe61d8a 1349static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1350{
7d0d0df0
S		 1351 ENABLE_REGWRITE_BUFFER(ah);
1352
9a658d2b
LR		 1353 if (AR_SREV_9300_20_OR_LATER(ah)) {
1354 REG_WRITE(ah, AR_WA, ah->WARegVal);
1355 udelay(10);
1356 }
1357
f1dc5600
S		 1358 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1359 AR_RTC_FORCE_WAKE_ON_INT);
1360
42d5bc3f 1361 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1362 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1363
d03a66c1 1364 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1365
7d0d0df0 1366 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1367
afe36533 1368 udelay(2);
84e2169b
SB		 1369
1370 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1371 REG_WRITE(ah, AR_RC, 0);
1372
d03a66c1 1373 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1374
1375 if (!ath9k_hw_wait(ah,
1376 AR_RTC_STATUS,
1377 AR_RTC_STATUS_M,
0caa7b14
S		 1378 AR_RTC_STATUS_ON,
1379 AH_WAIT_TIMEOUT)) {
d2182b69 1380 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1381 return false;
f078f209
LR		 1382 }
1383
f1dc5600
S		 1384 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1385}
1386
cbe61d8a 1387static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1388{
7a9233ff 1389 bool ret = false;
2577c6e8 1390
9a658d2b
LR		 1391 if (AR_SREV_9300_20_OR_LATER(ah)) {
1392 REG_WRITE(ah, AR_WA, ah->WARegVal);
1393 udelay(10);
1394 }
1395
f1dc5600
S		 1396 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1397 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1398
ceb26a60
FF		 1399 if (!ah->reset_power_on)
1400 type = ATH9K_RESET_POWER_ON;
1401
f1dc5600
S		 1402 switch (type) {
1403 case ATH9K_RESET_POWER_ON:
7a9233ff 1404 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1405 if (ret)
ceb26a60 1406 ah->reset_power_on = true;
7a9233ff 1407 break;
f1dc5600
S		 1408 case ATH9K_RESET_WARM:
1409 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1410 ret = ath9k_hw_set_reset(ah, type);
1411 break;
f1dc5600 1412 default:
7a9233ff 1413 break;
f1dc5600 1414 }
7a9233ff 1415
7a9233ff 1416 return ret;
f078f209
LR		 1417}
1418
cbe61d8a 1419static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1420 struct ath9k_channel *chan)
f078f209 1421{
9c083af8
FF		 1422 int reset_type = ATH9K_RESET_WARM;
1423
1424 if (AR_SREV_9280(ah)) {
1425 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1426 reset_type = ATH9K_RESET_POWER_ON;
1427 else
1428 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1429 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1430 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1431 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1432
1433 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1434 return false;
f078f209 1435
9ecdef4b 1436 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1437 return false;
f078f209 1438
2660b81a 1439 ah->chip_fullsleep = false;
bfc441a4
FF		 1440
1441 if (AR_SREV_9330(ah))
1442 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1443 ath9k_hw_init_pll(ah, chan);
f078f209 1444
f1dc5600 1445 return true;
f078f209
LR		 1446}
1447
cbe61d8a 1448static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1449 struct ath9k_channel *chan)
f078f209 1450{
c46917bb 1451 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1452 struct ath9k_hw_capabilities *pCap = &ah->caps;
1453 bool band_switch = false, mode_diff = false;
70e89a71 1454 u8 ini_reloaded = 0;
8fe65368 1455 u32 qnum;
0a3b7bac 1456 int r;
5f0c04ea 1457
b840cffe 1458 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1459 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1460 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1461 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1462 }
f078f209
LR		 1463
1464 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1465 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1466 ath_dbg(common, QUEUE,
226afe68 1467 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1468 return false;
1469 }
1470 }
1471
8fe65368 1472 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1473 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1474 return false;
1475 }
1476
b840cffe 1477 if (band_switch || mode_diff) {
5f0c04ea
RM		 1478 ath9k_hw_mark_phy_inactive(ah);
1479 udelay(5);
1480
5f35c0fa
SM		 1481 if (band_switch)
1482 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1483
1484 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1485 ath_err(common, "Failed to do fast channel change\n");
1486 return false;
1487 }
1488 }
1489
8fe65368 1490 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1491
8fe65368 1492 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1493 if (r) {
3800276a 1494 ath_err(common, "Failed to set channel\n");
0a3b7bac 1495 return false;
f078f209 1496 }
dfdac8ac 1497 ath9k_hw_set_clockrate(ah);
64ea57d0 1498 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1499
81c507a8 1500 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1501 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1502
70e89a71
SM		 1503 if (band_switch || ini_reloaded)
1504 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1505
70e89a71
SM		 1506 ath9k_hw_init_bb(ah, chan);
1507 ath9k_hw_rfbus_done(ah);
5f0c04ea 1508
70e89a71
SM		 1509 if (band_switch || ini_reloaded) {
1510 ah->ah_flags |= AH_FASTCC;
1511 ath9k_hw_init_cal(ah, chan);
a126ff51 1512 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1513 }
1514
f1dc5600
S		 1515 return true;
1516}
1517
691680b8
FF		 1518static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1519{
1520 u32 gpio_mask = ah->gpio_mask;
1521 int i;
1522
1523 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1524 if (!(gpio_mask & 1))
1525 continue;
1526
1527 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1528 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1529 }
1530}
1531
1e516ca7
SM		 1532void ath9k_hw_check_nav(struct ath_hw *ah)
1533{
1534 struct ath_common *common = ath9k_hw_common(ah);
1535 u32 val;
1536
1537 val = REG_READ(ah, AR_NAV);
1538 if (val != 0xdeadbeef && val > 0x7fff) {
1539 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1540 REG_WRITE(ah, AR_NAV, 0);
1541 }
1542}
1543EXPORT_SYMBOL(ath9k_hw_check_nav);
1544
c9c99e5e 1545bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1546{
c9c99e5e
FF		 1547 int count = 50;
1548 u32 reg;
1549
01e18918
RM		 1550 if (AR_SREV_9300(ah))
1551 return !ath9k_hw_detect_mac_hang(ah);
1552
e17f83ea 1553 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1554 return true;
1555
1556 do {
1557 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1558
c9c99e5e
FF		 1559 if ((reg & 0x7E7FFFEF) == 0x00702400)
1560 continue;
1561
1562 switch (reg & 0x7E000B00) {
1563 case 0x1E000000:
1564 case 0x52000B00:
1565 case 0x18000B00:
1566 continue;
1567 default:
1568 return true;
1569 }
1570 } while (count-- > 0);
3b319aae 1571
c9c99e5e 1572 return false;
3b319aae 1573}
c9c99e5e 1574EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1575
15d2b585
SM		 1576static void ath9k_hw_init_mfp(struct ath_hw *ah)
1577{
1578 /* Setup MFP options for CCMP */
1579 if (AR_SREV_9280_20_OR_LATER(ah)) {
1580 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1581 * frames when constructing CCMP AAD. */
1582 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1583 0xc7ff);
1584 ah->sw_mgmt_crypto = false;
1585 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1586 /* Disable hardware crypto for management frames */
1587 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1588 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1589 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1590 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1591 ah->sw_mgmt_crypto = true;
1592 } else {
1593 ah->sw_mgmt_crypto = true;
1594 }
1595}
1596
1597static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1598 u32 macStaId1, u32 saveDefAntenna)
1599{
1600 struct ath_common *common = ath9k_hw_common(ah);
1601
1602 ENABLE_REGWRITE_BUFFER(ah);
1603
ecbbed32 1604 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585
SM		 1605 | AR_STA_ID1_RTS_USE_DEF
1606 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
ecbbed32
FF		 1607 | ah->sta_id1_defaults,
1608 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1609 ath_hw_setbssidmask(common);
1610 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1611 ath9k_hw_write_associd(ah);
1612 REG_WRITE(ah, AR_ISR, ~0);
1613 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1614
1615 REGWRITE_BUFFER_FLUSH(ah);
1616
1617 ath9k_hw_set_operating_mode(ah, ah->opmode);
1618}
1619
1620static void ath9k_hw_init_queues(struct ath_hw *ah)
1621{
1622 int i;
1623
1624 ENABLE_REGWRITE_BUFFER(ah);
1625
1626 for (i = 0; i < AR_NUM_DCU; i++)
1627 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1628
1629 REGWRITE_BUFFER_FLUSH(ah);
1630
1631 ah->intr_txqs = 0;
1632 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1633 ath9k_hw_resettxqueue(ah, i);
1634}
1635
1636/*
1637 * For big endian systems turn on swapping for descriptors
1638 */
1639static void ath9k_hw_init_desc(struct ath_hw *ah)
1640{
1641 struct ath_common *common = ath9k_hw_common(ah);
1642
1643 if (AR_SREV_9100(ah)) {
1644 u32 mask;
1645 mask = REG_READ(ah, AR_CFG);
1646 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1647 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1648 mask);
1649 } else {
1650 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1651 REG_WRITE(ah, AR_CFG, mask);
1652 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1653 REG_READ(ah, AR_CFG));
1654 }
1655 } else {
1656 if (common->bus_ops->ath_bus_type == ATH_USB) {
1657 /* Configure AR9271 target WLAN */
1658 if (AR_SREV_9271(ah))
1659 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1660 else
1661 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1662 }
1663#ifdef __BIG_ENDIAN
1664 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1665 AR_SREV_9550(ah))
1666 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1667 else
1668 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1669#endif
1670 }
1671}
1672
caed6579
SM		 1673/*
1674 * Fast channel change:
1675 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1676 */
1677static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1678{
1679 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1680 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1681 int ret;
1682
1683 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1684 goto fail;
1685
1686 if (ah->chip_fullsleep)
1687 goto fail;
1688
1689 if (!ah->curchan)
1690 goto fail;
1691
1692 if (chan->channel == ah->curchan->channel)
1693 goto fail;
1694
feb7bc99
FF		 1695 if ((ah->curchan->channelFlags | chan->channelFlags) &
1696 (CHANNEL_HALF | CHANNEL_QUARTER))
1697 goto fail;
1698
b840cffe 1699 /*
6b21fd20 1700 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1701 */
6b21fd20 1702 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1703 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1704 goto fail;
caed6579
SM		 1705
1706 if (!ath9k_hw_check_alive(ah))
1707 goto fail;
1708
1709 /*
1710 * For AR9462, make sure that calibration data for
1711 * re-using are present.
1712 */
8a90555f 1713 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1714 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1715 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1716 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1717 goto fail;
1718
1719 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1720 ah->curchan->channel, chan->channel);
1721
1722 ret = ath9k_hw_channel_change(ah, chan);
1723 if (!ret)
1724 goto fail;
1725
5955b2b0 1726 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1727 ar9003_mci_2g5g_switch(ah, false);
caed6579 1728
88033318
RM		 1729 ath9k_hw_loadnf(ah, ah->curchan);
1730 ath9k_hw_start_nfcal(ah, true);
1731
caed6579
SM		 1732 if (AR_SREV_9271(ah))
1733 ar9002_hw_load_ani_reg(ah, chan);
1734
1735 return 0;
1736fail:
1737 return -EINVAL;
1738}
1739
cbe61d8a 1740int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1741 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1742{
1510718d 1743 struct ath_common *common = ath9k_hw_common(ah);
09d8e315 1744 struct timespec ts;
f078f209 1745 u32 saveLedState;
f078f209
LR		 1746 u32 saveDefAntenna;
1747 u32 macStaId1;
46fe782c 1748 u64 tsf = 0;
09d8e315 1749 s64 usec = 0;
15d2b585 1750 int r;
caed6579 1751 bool start_mci_reset = false;
63d32967
MSS		 1752 bool save_fullsleep = ah->chip_fullsleep;
1753
5955b2b0 1754 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1755 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1756 if (start_mci_reset)
1757 return 0;
63d32967
MSS		 1758 }
1759
9ecdef4b 1760 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1761 return -EIO;
f078f209 1762
caed6579
SM		 1763 if (ah->curchan && !ah->chip_fullsleep)
1764 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1765
20bd2a09 1766 ah->caldata = caldata;
fcb9a3de 1767 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1768 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1769 /* Operating channel changed, reset channel calibration data */
1770 memset(caldata, 0, sizeof(*caldata));
1771 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1772 } else if (caldata) {
4b9b42bf 1773 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1774 }
5bc225ac 1775 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1776
caed6579
SM		 1777 if (fastcc) {
1778 r = ath9k_hw_do_fastcc(ah, chan);
1779 if (!r)
1780 return r;
f078f209
LR		 1781 }
1782
5955b2b0 1783 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1784 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1785
f078f209
LR		 1786 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1787 if (saveDefAntenna == 0)
1788 saveDefAntenna = 1;
1789
1790 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1791
09d8e315
FF		 1792 /* Save TSF before chip reset, a cold reset clears it */
1793 tsf = ath9k_hw_gettsf64(ah);
1794 getrawmonotonic(&ts);
cca213fd 1795 usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000;
46fe782c 1796
f078f209
LR		 1797 saveLedState = REG_READ(ah, AR_CFG_LED) &
1798 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1799 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1800
1801 ath9k_hw_mark_phy_inactive(ah);
1802
45ef6a0b
VT		 1803 ah->paprd_table_write_done = false;
1804
05020d23 1805 /* Only required on the first reset */
d7e7d229
LR		 1806 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1807 REG_WRITE(ah,
1808 AR9271_RESET_POWER_DOWN_CONTROL,
1809 AR9271_RADIO_RF_RST);
1810 udelay(50);
1811 }
1812
f078f209 1813 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1814 ath_err(common, "Chip reset failed\n");
ae8d2858 1815 return -EINVAL;
f078f209
LR		 1816 }
1817
05020d23 1818 /* Only required on the first reset */
d7e7d229
LR		 1819 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1820 ah->htc_reset_init = false;
1821 REG_WRITE(ah,
1822 AR9271_RESET_POWER_DOWN_CONTROL,
1823 AR9271_GATE_MAC_CTL);
1824 udelay(50);
1825 }
1826
46fe782c 1827 /* Restore TSF */
09d8e315 1828 getrawmonotonic(&ts);
cca213fd 1829 usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000 - usec;
09d8e315 1830 ath9k_hw_settsf64(ah, tsf + usec);
46fe782c 1831
7a37081e 1832 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1833 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1834
e9141f71
S		 1835 if (!AR_SREV_9300_20_OR_LATER(ah))
1836 ar9002_hw_enable_async_fifo(ah);
1837
25c56eec 1838 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1839 if (r)
1840 return r;
f078f209 1841
935d00cc
LB		 1842 ath9k_hw_set_rfmode(ah, chan);
1843
5955b2b0 1844 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1845 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1846
f860d526
FF		 1847 /*
1848 * Some AR91xx SoC devices frequently fail to accept TSF writes
1849 * right after the chip reset. When that happens, write a new
1850 * value after the initvals have been applied, with an offset
1851 * based on measured time difference
1852 */
1853 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1854 tsf += 1500;
1855 ath9k_hw_settsf64(ah, tsf);
1856 }
1857
15d2b585 1858 ath9k_hw_init_mfp(ah);
0ced0e17 1859
81c507a8 1860 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1861 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1862 ah->eep_ops->set_board_values(ah, chan);
a7765828 1863
15d2b585 1864 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1865
8fe65368 1866 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1867 if (r)
1868 return r;
f078f209 1869
dfdac8ac
FF		 1870 ath9k_hw_set_clockrate(ah);
1871
15d2b585 1872 ath9k_hw_init_queues(ah);
2660b81a 1873 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1874 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1875 ath9k_hw_init_qos(ah);
1876
2660b81a 1877 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1878 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1879
0005baf4 1880 ath9k_hw_init_global_settings(ah);
f078f209 1881
fe2b6afb
FF		 1882 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1883 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1884 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1885 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1886 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1887 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1888 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1889 }
1890
ca7a4deb 1891 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1892
1893 ath9k_hw_set_dma(ah);
1894
ed6ebd8b
RM		 1895 if (!ath9k_hw_mci_is_enabled(ah))
1896 REG_WRITE(ah, AR_OBS, 8);
f078f209 1897
0ce024cb 1898 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1899 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1900 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1901 }
1902
7f62a136
VT		 1903 if (ah->config.tx_intr_mitigation) {
1904 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1905 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1906 }
1907
f078f209
LR		 1908 ath9k_hw_init_bb(ah, chan);
1909
77a5a664 1910 if (caldata) {
4b9b42bf
SM		 1911 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1912 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 1913 }
ae8d2858 1914 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1915 return -EIO;
f078f209 1916
5955b2b0 1917 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 1918 return -EIO;
63d32967 1919
7d0d0df0 1920 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1921
8fe65368 1922 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1923 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1924
7d0d0df0 1925 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1926
15d2b585 1927 ath9k_hw_init_desc(ah);
f078f209 1928
dbccdd1d 1929 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 1930 ath9k_hw_btcoex_enable(ah);
1931
5955b2b0 1932 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1933 ar9003_mci_check_bt(ah);
63d32967 1934
1fe860ed
RM		 1935 ath9k_hw_loadnf(ah, chan);
1936 ath9k_hw_start_nfcal(ah, true);
1937
51ac8cbb 1938 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 1939 ar9003_hw_bb_watchdog_config(ah);
51ac8cbb
RM		 1940 ar9003_hw_disable_phy_restart(ah);
1941 }
1942
691680b8
FF		 1943 ath9k_hw_apply_gpio_override(ah);
1944
7bdea96a 1945 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 1946 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
1947
ae8d2858 1948 return 0;
f078f209 1949}
7322fd19 1950EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1951
f1dc5600
S		 1952/******************************/
1953/* Power Management (Chipset) */
1954/******************************/
1955
42d5bc3f
LR		 1956/*
1957 * Notify Power Mgt is disabled in self-generated frames.
1958 * If requested, force chip to sleep.
1959 */
31604cf0 1960static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 1961{
f1dc5600 1962 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 1963
a4a2954f 1964 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 1965 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
1966 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
1967 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 1968 /* xxx Required for WLAN only case ? */
1969 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1970 udelay(100);
1971 }
2577c6e8 1972
31604cf0
SM		 1973 /*
1974 * Clear the RTC force wake bit to allow the
1975 * mac to go to sleep.
1976 */
1977 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1978
153dccd4 1979 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 1980 udelay(100);
2577c6e8 1981
31604cf0
SM		 1982 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1983 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1984
31604cf0
SM		 1985 /* Shutdown chip. Active low */
1986 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
1987 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1988 udelay(2);
f1dc5600 1989 }
9a658d2b
LR		 1990
1991 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 1992 if (AR_SREV_9300_20_OR_LATER(ah))
1993 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1994}
1995
bbd79af5
LR		 1996/*
1997 * Notify Power Management is enabled in self-generating
1998 * frames. If request, set power mode of chip to
1999 * auto/normal. Duration in units of 128us (1/8 TU).
2000 */
31604cf0 2001static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2002{
31604cf0 2003 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2004
f1dc5600 2005 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2006
31604cf0
SM		 2007 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2008 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2009 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2010 AR_RTC_FORCE_WAKE_ON_INT);
2011 } else {
2577c6e8 2012
31604cf0
SM		 2013 /* When chip goes into network sleep, it could be waken
2014 * up by MCI_INT interrupt caused by BT's HW messages
2015 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2016 * rate (~100us). This will cause chip to leave and
2017 * re-enter network sleep mode frequently, which in
2018 * consequence will have WLAN MCI HW to generate lots of
2019 * SYS_WAKING and SYS_SLEEPING messages which will make
2020 * BT CPU to busy to process.
2021 */
153dccd4
RM		 2022 if (ath9k_hw_mci_is_enabled(ah))
2023 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2024 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2025 /*
2026 * Clear the RTC force wake bit to allow the
2027 * mac to go to sleep.
2028 */
153dccd4 2029 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2030
153dccd4 2031 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2032 udelay(30);
f078f209 2033 }
9a658d2b
LR		 2034
2035 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2036 if (AR_SREV_9300_20_OR_LATER(ah))
2037 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2038}
2039
31604cf0 2040static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2041{
f1dc5600
S		 2042 u32 val;
2043 int i;
f078f209 2044
9a658d2b
LR		 2045 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2046 if (AR_SREV_9300_20_OR_LATER(ah)) {
2047 REG_WRITE(ah, AR_WA, ah->WARegVal);
2048 udelay(10);
2049 }
2050
31604cf0
SM		 2051 if ((REG_READ(ah, AR_RTC_STATUS) &
2052 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2053 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2054 return false;
f1dc5600 2055 }
31604cf0
SM		 2056 if (!AR_SREV_9300_20_OR_LATER(ah))
2057 ath9k_hw_init_pll(ah, NULL);
2058 }
2059 if (AR_SREV_9100(ah))
2060 REG_SET_BIT(ah, AR_RTC_RESET,
2061 AR_RTC_RESET_EN);
2062
2063 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2064 AR_RTC_FORCE_WAKE_EN);
2065 udelay(50);
f078f209 2066
31604cf0
SM		 2067 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2068 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2069 if (val == AR_RTC_STATUS_ON)
2070 break;
2071 udelay(50);
f1dc5600
S		 2072 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2073 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2074 }
2075 if (i == 0) {
2076 ath_err(ath9k_hw_common(ah),
2077 "Failed to wakeup in %uus\n",
2078 POWER_UP_TIME / 20);
2079 return false;
f078f209
LR		 2080 }
2081
cdbe408d
RM		 2082 if (ath9k_hw_mci_is_enabled(ah))
2083 ar9003_mci_set_power_awake(ah);
2084
f1dc5600 2085 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2086
f1dc5600 2087 return true;
f078f209
LR		 2088}
2089
9ecdef4b 2090bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2091{
c46917bb 2092 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2093 int status = true;
f1dc5600
S		 2094 static const char *modes[] = {
2095 "AWAKE",
2096 "FULL-SLEEP",
2097 "NETWORK SLEEP",
2098 "UNDEFINED"
2099 };
f1dc5600 2100
cbdec975
GJ		 2101 if (ah->power_mode == mode)
2102 return status;
2103
d2182b69 2104 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2105 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2106
2107 switch (mode) {
2108 case ATH9K_PM_AWAKE:
31604cf0 2109 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2110 break;
2111 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2112 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2113 ar9003_mci_set_full_sleep(ah);
1010911e 2114
31604cf0 2115 ath9k_set_power_sleep(ah);
2660b81a 2116 ah->chip_fullsleep = true;
f1dc5600
S		 2117 break;
2118 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2119 ath9k_set_power_network_sleep(ah);
f1dc5600 2120 break;
f078f209 2121 default:
3800276a 2122 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2123 return false;
2124 }
2660b81a 2125 ah->power_mode = mode;
f1dc5600 2126
69f4aab1
LR		 2127 /*
2128 * XXX: If this warning never comes up after a while then
2129 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2130 * ath9k_hw_setpower() return type void.
2131 */
97dcec57
SM		 2132
2133 if (!(ah->ah_flags & AH_UNPLUGGED))
2134 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2135
f1dc5600 2136 return status;
f078f209 2137}
7322fd19 2138EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2139
f1dc5600
S		 2140/*******************/
2141/* Beacon Handling */
2142/*******************/
2143
cbe61d8a 2144void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2145{
f078f209
LR		 2146 int flags = 0;
2147
7d0d0df0
S		 2148 ENABLE_REGWRITE_BUFFER(ah);
2149
2660b81a 2150 switch (ah->opmode) {
d97809db 2151 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2152 REG_SET_BIT(ah, AR_TXCFG,
2153 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2154 case NL80211_IFTYPE_MESH_POINT:
d97809db 2155 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2156 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2157 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2158 TU_TO_USEC(ah->config.dma_beacon_response_time));
2159 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2160 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2161 flags |=
2162 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2163 break;
d97809db 2164 default:
d2182b69
JP		 2165 ath_dbg(ath9k_hw_common(ah), BEACON,
2166 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2167 return;
2168 break;
f078f209
LR		 2169 }
2170
dd347f2f
FF		 2171 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2172 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2173 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2174
7d0d0df0 2175 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2176
f078f209
LR		 2177 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2178}
7322fd19 2179EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2180
cbe61d8a 2181void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2182 const struct ath9k_beacon_state *bs)
f078f209
LR		 2183{
2184 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2185 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2186 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2187
7d0d0df0
S		 2188 ENABLE_REGWRITE_BUFFER(ah);
2189
4ed15762
FF		 2190 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2191 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2192 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2193
7d0d0df0 2194 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2195
f078f209
LR		 2196 REG_RMW_FIELD(ah, AR_RSSI_THR,
2197 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2198
f29f5c08 2199 beaconintval = bs->bs_intval;
f078f209
LR		 2200
2201 if (bs->bs_sleepduration > beaconintval)
2202 beaconintval = bs->bs_sleepduration;
2203
2204 dtimperiod = bs->bs_dtimperiod;
2205 if (bs->bs_sleepduration > dtimperiod)
2206 dtimperiod = bs->bs_sleepduration;
2207
2208 if (beaconintval == dtimperiod)
2209 nextTbtt = bs->bs_nextdtim;
2210 else
2211 nextTbtt = bs->bs_nexttbtt;
2212
d2182b69
JP		 2213 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2214 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2215 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2216 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2217
7d0d0df0
S		 2218 ENABLE_REGWRITE_BUFFER(ah);
2219
4ed15762
FF		 2220 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2221 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2222
f1dc5600
S		 2223 REG_WRITE(ah, AR_SLEEP1,
2224 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2225 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2226
f1dc5600
S		 2227 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2228 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2229 else
2230 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2231
f1dc5600
S		 2232 REG_WRITE(ah, AR_SLEEP2,
2233 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2234
4ed15762
FF		 2235 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2236 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2237
7d0d0df0 2238 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2239
f1dc5600
S		 2240 REG_SET_BIT(ah, AR_TIMER_MODE,
2241 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2242 AR_DTIM_TIMER_EN);
f078f209 2243
4af9cf4f
S		 2244 /* TSF Out of Range Threshold */
2245 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2246}
7322fd19 2247EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2248
f1dc5600
S		 2249/*******************/
2250/* HW Capabilities */
2251/*******************/
2252
6054069a
FF		 2253static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2254{
2255 eeprom_chainmask &= chip_chainmask;
2256 if (eeprom_chainmask)
2257 return eeprom_chainmask;
2258 else
2259 return chip_chainmask;
2260}
2261
9a66af33
ZK		 2262/**
2263 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2264 * @ah: the atheros hardware data structure
2265 *
2266 * We enable DFS support upstream on chipsets which have passed a series
2267 * of tests. The testing requirements are going to be documented. Desired
2268 * test requirements are documented at:
2269 *
2270 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2271 *
2272 * Once a new chipset gets properly tested an individual commit can be used
2273 * to document the testing for DFS for that chipset.
2274 */
2275static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2276{
2277
2278 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2279 /* for temporary testing DFS with 9280 */
2280 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2281 /* AR9580 will likely be our first target to get testing on */
2282 case AR_SREV_VERSION_9580:
73e4937d 2283 return true;
9a66af33
ZK		 2284 default:
2285 return false;
2286 }
2287}
2288
a9a29ce6 2289int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2290{
2660b81a 2291 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2292 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2293 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2294 unsigned int chip_chainmask;
608b88cb 2295
0ff2b5c0 2296 u16 eeval;
47c80de6 2297 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2298
f74df6fb 2299 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2300 regulatory->current_rd = eeval;
f078f209 2301
2660b81a 2302 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2303 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2304 if (regulatory->current_rd == 0x64 ||
2305 regulatory->current_rd == 0x65)
2306 regulatory->current_rd += 5;
2307 else if (regulatory->current_rd == 0x41)
2308 regulatory->current_rd = 0x43;
d2182b69
JP		 2309 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2310 regulatory->current_rd);
f1dc5600 2311 }
f078f209 2312
f74df6fb 2313 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2314 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2315 ath_err(common,
2316 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2317 return -EINVAL;
2318 }
2319
d4659912
FF		 2320 if (eeval & AR5416_OPFLAGS_11A)
2321 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2322
d4659912
FF		 2323 if (eeval & AR5416_OPFLAGS_11G)
2324 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2325
e41db61d
SM		 2326 if (AR_SREV_9485(ah) ||
2327 AR_SREV_9285(ah) ||
2328 AR_SREV_9330(ah) ||
2329 AR_SREV_9565(ah))
6054069a 2330 chip_chainmask = 1;
ba5736a5
MSS		 2331 else if (AR_SREV_9462(ah))
2332 chip_chainmask = 3;
6054069a
FF		 2333 else if (!AR_SREV_9280_20_OR_LATER(ah))
2334 chip_chainmask = 7;
2335 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2336 chip_chainmask = 3;
2337 else
2338 chip_chainmask = 7;
2339
f74df6fb 2340 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2341 /*
2342 * For AR9271 we will temporarilly uses the rx chainmax as read from
2343 * the EEPROM.
2344 */
8147f5de 2345 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2346 !(eeval & AR5416_OPFLAGS_11A) &&
2347 !(AR_SREV_9271(ah)))
2348 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2349 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2350 else if (AR_SREV_9100(ah))
2351 pCap->rx_chainmask = 0x7;
8147f5de 2352 else
d7e7d229 2353 /* Use rx_chainmask from EEPROM. */
8147f5de 2354 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2355
6054069a
FF		 2356 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2357 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2358 ah->txchainmask = pCap->tx_chainmask;
2359 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2360
7a37081e 2361 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2362
02d2ebb2
FF		 2363 /* enable key search for every frame in an aggregate */
2364 if (AR_SREV_9300_20_OR_LATER(ah))
2365 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2366
ce2220d1
BR		 2367 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2368
0db156e9 2369 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2370 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2371 else
2372 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2373
5b5fa355
S		 2374 if (AR_SREV_9271(ah))
2375 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2376 else if (AR_DEVID_7010(ah))
2377 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2378 else if (AR_SREV_9300_20_OR_LATER(ah))
2379 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2380 else if (AR_SREV_9287_11_OR_LATER(ah))
2381 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2382 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2383 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2384 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2385 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2386 else
2387 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2388
1b2538b2 2389 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2390 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2391 else
f1dc5600 2392 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2393
74e13060 2394#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2395 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2396 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2397 ah->rfkill_gpio =
2398 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2399 ah->rfkill_polarity =
2400 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2401
2402 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2403 }
f1dc5600 2404#endif
d5d1154f 2405 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2406 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2407 else
2408 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2409
e7594072 2410 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2411 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2412 else
2413 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2414
ceb26445 2415 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2416 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
a4a2954f 2417 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2418 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2419
ceb26445
VT		 2420 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2421 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2422 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2423 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2424 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2425 } else {
2426 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2427 if (AR_SREV_9280_20(ah))
6b42e8d0 2428 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2429 }
1adf02ff 2430
6c84ce08
VT		 2431 if (AR_SREV_9300_20_OR_LATER(ah))
2432 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2433
6ee63f55
SB		 2434 if (AR_SREV_9300_20_OR_LATER(ah))
2435 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2436
a42acef0 2437 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2438 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2439
f85c3371 2440 if (AR_SREV_9285(ah)) {
754dc536
VT		 2441 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2442 ant_div_ctl1 =
2443 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2444 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2445 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2446 ath_info(common, "Enable LNA combining\n");
2447 }
754dc536 2448 }
f85c3371
SM		 2449 }
2450
ea066d5a
MSS		 2451 if (AR_SREV_9300_20_OR_LATER(ah)) {
2452 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2453 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2454 }
2455
06236e53 2456 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2457 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2458 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2459 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2460 ath_info(common, "Enable LNA combining\n");
2461 }
21d2c63a 2462 }
754dc536 2463
9a66af33
ZK		 2464 if (ath9k_hw_dfs_tested(ah))
2465 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2466
47c80de6
VT		 2467 tx_chainmask = pCap->tx_chainmask;
2468 rx_chainmask = pCap->rx_chainmask;
2469 while (tx_chainmask || rx_chainmask) {
2470 if (tx_chainmask & BIT(0))
2471 pCap->max_txchains++;
2472 if (rx_chainmask & BIT(0))
2473 pCap->max_rxchains++;
2474
2475 tx_chainmask >>= 1;
2476 rx_chainmask >>= 1;
2477 }
2478
a4a2954f 2479 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2480 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2481 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2482
2b5e54e2 2483 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2484 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2485 }
2486
846e438f
SM		 2487 if (AR_SREV_9462(ah))
2488 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
d687809b 2489
0f21ee8d
SM		 2490 if (AR_SREV_9300_20_OR_LATER(ah) &&
2491 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2492 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2493
81dc75b5
SM		 2494 /*
2495 * Fast channel change across bands is available
2496 * only for AR9462 and AR9565.
2497 */
2498 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2499 pCap->hw_caps |= ATH9K_HW_CAP_FCC_BAND_SWITCH;
2500
a9a29ce6 2501 return 0;
f078f209
LR		 2502}
2503
f1dc5600
S		 2504/****************************/
2505/* GPIO / RFKILL / Antennae */
2506/****************************/
f078f209 2507
cbe61d8a 2508static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2509 u32 gpio, u32 type)
2510{
2511 int addr;
2512 u32 gpio_shift, tmp;
f078f209 2513
f1dc5600
S		 2514 if (gpio > 11)
2515 addr = AR_GPIO_OUTPUT_MUX3;
2516 else if (gpio > 5)
2517 addr = AR_GPIO_OUTPUT_MUX2;
2518 else
2519 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2520
f1dc5600 2521 gpio_shift = (gpio % 6) * 5;
f078f209 2522
f1dc5600
S		 2523 if (AR_SREV_9280_20_OR_LATER(ah)
2524 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2525 REG_RMW(ah, addr, (type << gpio_shift),
2526 (0x1f << gpio_shift));
f078f209 2527 } else {
f1dc5600
S		 2528 tmp = REG_READ(ah, addr);
2529 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2530 tmp &= ~(0x1f << gpio_shift);
2531 tmp |= (type << gpio_shift);
2532 REG_WRITE(ah, addr, tmp);
f078f209 2533 }
f078f209
LR		 2534}
2535
cbe61d8a 2536void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2537{
f1dc5600 2538 u32 gpio_shift;
f078f209 2539
9680e8a3 2540 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2541
88c1f4f6
S		 2542 if (AR_DEVID_7010(ah)) {
2543 gpio_shift = gpio;
2544 REG_RMW(ah, AR7010_GPIO_OE,
2545 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2546 (AR7010_GPIO_OE_MASK << gpio_shift));
2547 return;
2548 }
f078f209 2549
88c1f4f6 2550 gpio_shift = gpio << 1;
f1dc5600
S		 2551 REG_RMW(ah,
2552 AR_GPIO_OE_OUT,
2553 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2554 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2555}
7322fd19 2556EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2557
cbe61d8a 2558u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2559{
cb33c412
SB		 2560#define MS_REG_READ(x, y) \
2561 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2562
2660b81a 2563 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2564 return 0xffffffff;
f078f209 2565
88c1f4f6
S		 2566 if (AR_DEVID_7010(ah)) {
2567 u32 val;
2568 val = REG_READ(ah, AR7010_GPIO_IN);
2569 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2570 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2571 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2572 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2573 else if (AR_SREV_9271(ah))
5b5fa355 2574 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2575 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2576 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2577 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2578 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2579 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2580 return MS_REG_READ(AR928X, gpio) != 0;
2581 else
2582 return MS_REG_READ(AR, gpio) != 0;
f078f209 2583}
7322fd19 2584EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2585
cbe61d8a 2586void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2587 u32 ah_signal_type)
f078f209 2588{
f1dc5600 2589 u32 gpio_shift;
f078f209 2590
88c1f4f6
S		 2591 if (AR_DEVID_7010(ah)) {
2592 gpio_shift = gpio;
2593 REG_RMW(ah, AR7010_GPIO_OE,
2594 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2595 (AR7010_GPIO_OE_MASK << gpio_shift));
2596 return;
2597 }
f078f209 2598
88c1f4f6 2599 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2600 gpio_shift = 2 * gpio;
f1dc5600
S		 2601 REG_RMW(ah,
2602 AR_GPIO_OE_OUT,
2603 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2604 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2605}
7322fd19 2606EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2607
cbe61d8a 2608void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2609{
88c1f4f6
S		 2610 if (AR_DEVID_7010(ah)) {
2611 val = val ? 0 : 1;
2612 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2613 AR_GPIO_BIT(gpio));
2614 return;
2615 }
2616
5b5fa355
S		 2617 if (AR_SREV_9271(ah))
2618 val = ~val;
2619
f1dc5600
S		 2620 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2621 AR_GPIO_BIT(gpio));
f078f209 2622}
7322fd19 2623EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2624
cbe61d8a 2625void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2626{
f1dc5600 2627 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2628}
7322fd19 2629EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2630
f1dc5600
S		 2631/*********************/
2632/* General Operation */
2633/*********************/
2634
cbe61d8a 2635u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2636{
f1dc5600
S		 2637 u32 bits = REG_READ(ah, AR_RX_FILTER);
2638 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2639
f1dc5600
S		 2640 if (phybits & AR_PHY_ERR_RADAR)
2641 bits |= ATH9K_RX_FILTER_PHYRADAR;
2642 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2643 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2644
f1dc5600 2645 return bits;
f078f209 2646}
7322fd19 2647EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2648
cbe61d8a 2649void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2650{
f1dc5600 2651 u32 phybits;
f078f209 2652
7d0d0df0
S		 2653 ENABLE_REGWRITE_BUFFER(ah);
2654
a4a2954f 2655 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2577c6e8
SB		 2656 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2657
7ea310be
S		 2658 REG_WRITE(ah, AR_RX_FILTER, bits);
2659
f1dc5600
S		 2660 phybits = 0;
2661 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2662 phybits |= AR_PHY_ERR_RADAR;
2663 if (bits & ATH9K_RX_FILTER_PHYERR)
2664 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2665 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2666
f1dc5600 2667 if (phybits)
ca7a4deb 2668 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2669 else
ca7a4deb 2670 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2671
2672 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2673}
7322fd19 2674EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2675
cbe61d8a 2676bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2677{
99922a45
RM		 2678 if (ath9k_hw_mci_is_enabled(ah))
2679 ar9003_mci_bt_gain_ctrl(ah);
2680
63a75b91
SB		 2681 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2682 return false;
2683
2684 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2685 ah->htc_reset_init = true;
63a75b91 2686 return true;
f1dc5600 2687}
7322fd19 2688EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2689
cbe61d8a 2690bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2691{
9ecdef4b 2692 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2693 return false;
f078f209 2694
63a75b91
SB		 2695 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2696 return false;
2697
2698 ath9k_hw_init_pll(ah, NULL);
2699 return true;
f078f209 2700}
7322fd19 2701EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2702
ca2c68cc
FF		 2703static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2704{
2705 enum eeprom_param gain_param;
2706
2707 if (IS_CHAN_2GHZ(chan))
2708 gain_param = EEP_ANTENNA_GAIN_2G;
2709 else
2710 gain_param = EEP_ANTENNA_GAIN_5G;
2711
2712 return ah->eep_ops->get_eeprom(ah, gain_param);
2713}
2714
64ea57d0
GJ		 2715void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2716 bool test)
ca2c68cc
FF		 2717{
2718 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2719 struct ieee80211_channel *channel;
2720 int chan_pwr, new_pwr, max_gain;
2721 int ant_gain, ant_reduction = 0;
2722
2723 if (!chan)
2724 return;
2725
2726 channel = chan->chan;
2727 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2728 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2729 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2730
2731 ant_gain = get_antenna_gain(ah, chan);
2732 if (ant_gain > max_gain)
2733 ant_reduction = ant_gain - max_gain;
2734
2735 ah->eep_ops->set_txpower(ah, chan,
2736 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2737 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2738}
2739
de40f316 2740void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2741{
ca2c68cc 2742 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2743 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2744 struct ieee80211_channel *channel = chan->chan;
9c204b46 2745
48ef5c42 2746 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2747 if (test)
ca2c68cc 2748 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2749
64ea57d0 2750 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2751
ca2c68cc
FF		 2752 if (test)
2753 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2754}
7322fd19 2755EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2756
cbe61d8a 2757void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2758{
2660b81a 2759 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2760}
7322fd19 2761EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2762
cbe61d8a 2763void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2764{
f1dc5600
S		 2765 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2766 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2767}
7322fd19 2768EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2769
f2b2143e 2770void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2771{
1510718d
LR		 2772 struct ath_common *common = ath9k_hw_common(ah);
2773
2774 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2775 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2776 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2777}
7322fd19 2778EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2779
1c0fc65e
BP		 2780#define ATH9K_MAX_TSF_READ 10
2781
cbe61d8a 2782u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2783{
1c0fc65e
BP		 2784 u32 tsf_lower, tsf_upper1, tsf_upper2;
2785 int i;
2786
2787 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2788 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2789 tsf_lower = REG_READ(ah, AR_TSF_L32);
2790 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2791 if (tsf_upper2 == tsf_upper1)
2792 break;
2793 tsf_upper1 = tsf_upper2;
2794 }
f078f209 2795
1c0fc65e 2796 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2797
1c0fc65e 2798 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2799}
7322fd19 2800EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2801
cbe61d8a 2802void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2803{
27abe060 2804 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2805 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2806}
7322fd19 2807EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2808
cbe61d8a 2809void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2810{
f9b604f6
GJ		 2811 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2812 AH_TSF_WRITE_TIMEOUT))
d2182b69 2813 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2814 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2815
f1dc5600
S		 2816 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2817}
7322fd19 2818EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2819
60ca9f87 2820void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 2821{
60ca9f87 2822 if (set)
2660b81a 2823 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2824 else
2660b81a 2825 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2826}
7322fd19 2827EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2828
e4744ec7 2829void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 2830{
2831 u32 macmode;
2832
e4744ec7 2833 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2834 macmode = AR_2040_JOINED_RX_CLEAR;
2835 else
2836 macmode = 0;
f078f209 2837
f1dc5600 2838 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2839}
ff155a45
VT		 2840
2841/* HW Generic timers configuration */
2842
2843static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2844{
2845 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2846 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2847 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2848 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2849 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2850 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2851 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2852 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2853 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2854 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2855 AR_NDP2_TIMER_MODE, 0x0002},
2856 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2857 AR_NDP2_TIMER_MODE, 0x0004},
2858 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2859 AR_NDP2_TIMER_MODE, 0x0008},
2860 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2861 AR_NDP2_TIMER_MODE, 0x0010},
2862 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2863 AR_NDP2_TIMER_MODE, 0x0020},
2864 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2865 AR_NDP2_TIMER_MODE, 0x0040},
2866 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2867 AR_NDP2_TIMER_MODE, 0x0080}
2868};
2869
2870/* HW generic timer primitives */
2871
dd347f2f 2872u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2873{
2874 return REG_READ(ah, AR_TSF_L32);
2875}
dd347f2f 2876EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2877
2878struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2879 void (*trigger)(void *),
2880 void (*overflow)(void *),
2881 void *arg,
2882 u8 timer_index)
2883{
2884 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2885 struct ath_gen_timer *timer;
2886
c67ce339
FF		 2887 if ((timer_index < AR_FIRST_NDP_TIMER) ||
2888 (timer_index >= ATH_MAX_GEN_TIMER))
2889 return NULL;
2890
ff155a45 2891 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 2892 if (timer == NULL)
ff155a45 2893 return NULL;
ff155a45
VT		 2894
2895 /* allocate a hardware generic timer slot */
2896 timer_table->timers[timer_index] = timer;
2897 timer->index = timer_index;
2898 timer->trigger = trigger;
2899 timer->overflow = overflow;
2900 timer->arg = arg;
2901
2902 return timer;
2903}
7322fd19 2904EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2905
cd9bf689
LR		 2906void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2907 struct ath_gen_timer *timer,
c67ce339 2908 u32 timer_next,
cd9bf689 2909 u32 timer_period)
ff155a45
VT		 2910{
2911 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 2912 u32 mask = 0;
788f6875 2913
c67ce339 2914 timer_table->timer_mask |= BIT(timer->index);
ff155a45 2915
ff155a45
VT		 2916 /*
2917 * Program generic timer registers
2918 */
2919 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2920 timer_next);
2921 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2922 timer_period);
2923 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2924 gen_tmr_configuration[timer->index].mode_mask);
2925
a4a2954f 2926 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 2927 /*
423e38e8 2928 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 2929 * to use. But we still follow the old rule, 0 - 7 use tsf and
2930 * 8 - 15 use tsf2.
2931 */
2932 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2933 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2934 (1 << timer->index));
2935 else
2936 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2937 (1 << timer->index));
2938 }
2939
c67ce339
FF		 2940 if (timer->trigger)
2941 mask |= SM(AR_GENTMR_BIT(timer->index),
2942 AR_IMR_S5_GENTIMER_TRIG);
2943 if (timer->overflow)
2944 mask |= SM(AR_GENTMR_BIT(timer->index),
2945 AR_IMR_S5_GENTIMER_THRESH);
2946
2947 REG_SET_BIT(ah, AR_IMR_S5, mask);
2948
2949 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
2950 ah->imask |= ATH9K_INT_GENTIMER;
2951 ath9k_hw_set_interrupts(ah);
2952 }
ff155a45 2953}
7322fd19 2954EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2955
cd9bf689 2956void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2957{
2958 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2959
ff155a45
VT		 2960 /* Clear generic timer enable bits. */
2961 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2962 gen_tmr_configuration[timer->index].mode_mask);
2963
b7f59766
SM		 2964 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2965 /*
2966 * Need to switch back to TSF if it was using TSF2.
2967 */
2968 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
2969 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2970 (1 << timer->index));
2971 }
2972 }
2973
ff155a45
VT		 2974 /* Disable both trigger and thresh interrupt masks */
2975 REG_CLR_BIT(ah, AR_IMR_S5,
2976 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2977 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2978
c67ce339
FF		 2979 timer_table->timer_mask &= ~BIT(timer->index);
2980
2981 if (timer_table->timer_mask == 0) {
2982 ah->imask &= ~ATH9K_INT_GENTIMER;
2983 ath9k_hw_set_interrupts(ah);
2984 }
ff155a45 2985}
7322fd19 2986EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2987
2988void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2989{
2990 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2991
2992 /* free the hardware generic timer slot */
2993 timer_table->timers[timer->index] = NULL;
2994 kfree(timer);
2995}
7322fd19 2996EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2997
2998/*
2999 * Generic Timer Interrupts handling
3000 */
3001void ath_gen_timer_isr(struct ath_hw *ah)
3002{
3003 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3004 struct ath_gen_timer *timer;
c67ce339
FF		 3005 unsigned long trigger_mask, thresh_mask;
3006 unsigned int index;
ff155a45
VT		 3007
3008 /* get hardware generic timer interrupt status */
3009 trigger_mask = ah->intr_gen_timer_trigger;
3010 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 3011 trigger_mask &= timer_table->timer_mask;
3012 thresh_mask &= timer_table->timer_mask;
ff155a45 3013
c67ce339 3014 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3015 timer = timer_table->timers[index];
c67ce339
FF		 3016 if (!timer)
3017 continue;
3018 if (!timer->overflow)
3019 continue;
a6a172b2
FF		 3020
3021 trigger_mask &= ~BIT(index);
ff155a45
VT		 3022 timer->overflow(timer->arg);
3023 }
3024
c67ce339 3025 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3026 timer = timer_table->timers[index];
c67ce339
FF		 3027 if (!timer)
3028 continue;
3029 if (!timer->trigger)
3030 continue;
ff155a45
VT		 3031 timer->trigger(timer->arg);
3032 }
3033}
7322fd19 3034EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3035
05020d23
S		 3036/********/
3037/* HTC */
3038/********/
3039
2da4f01a
LR		 3040static struct {
3041 u32 version;
3042 const char * name;
3043} ath_mac_bb_names[] = {
3044 /* Devices with external radios */
3045 { AR_SREV_VERSION_5416_PCI, "5416" },
3046 { AR_SREV_VERSION_5416_PCIE, "5418" },
3047 { AR_SREV_VERSION_9100, "9100" },
3048 { AR_SREV_VERSION_9160, "9160" },
3049 /* Single-chip solutions */
3050 { AR_SREV_VERSION_9280, "9280" },
3051 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3052 { AR_SREV_VERSION_9287, "9287" },
3053 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3054 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3055 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3056 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3057 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3058 { AR_SREV_VERSION_9462, "9462" },
485124cb 3059 { AR_SREV_VERSION_9550, "9550" },
77fac465 3060 { AR_SREV_VERSION_9565, "9565" },
2da4f01a
LR		 3061};
3062
3063/* For devices with external radios */
3064static struct {
3065 u16 version;
3066 const char * name;
3067} ath_rf_names[] = {
3068 { 0, "5133" },
3069 { AR_RAD5133_SREV_MAJOR, "5133" },
3070 { AR_RAD5122_SREV_MAJOR, "5122" },
3071 { AR_RAD2133_SREV_MAJOR, "2133" },
3072 { AR_RAD2122_SREV_MAJOR, "2122" }
3073};
3074
3075/*
3076 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3077 */
f934c4d9 3078static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3079{
3080 int i;
3081
3082 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3083 if (ath_mac_bb_names[i].version == mac_bb_version) {
3084 return ath_mac_bb_names[i].name;
3085 }
3086 }
3087
3088 return "????";
3089}
2da4f01a
LR		 3090
3091/*
3092 * Return the RF name. "????" is returned if the RF is unknown.
3093 * Used for devices with external radios.
3094 */
f934c4d9 3095static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3096{
3097 int i;
3098
3099 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3100 if (ath_rf_names[i].version == rf_version) {
3101 return ath_rf_names[i].name;
3102 }
3103 }
3104
3105 return "????";
3106}
f934c4d9
LR		 3107
3108void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3109{
3110 int used;
3111
3112 /* chipsets >= AR9280 are single-chip */
7a37081e 3113 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3114 used = scnprintf(hw_name, len,
3115 "Atheros AR%s Rev:%x",
3116 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3117 ah->hw_version.macRev);
f934c4d9
LR		 3118 }
3119 else {
5e88ba62
ZK		 3120 used = scnprintf(hw_name, len,
3121 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3122 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3123 ah->hw_version.macRev,
3124 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3125 & AR_RADIO_SREV_MAJOR)),
3126 ah->hw_version.phyRev);
f934c4d9
LR		 3127 }
3128
3129 hw_name[used] = '\0';
3130}
3131EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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