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Merge branch 'master' of git://git.infradead.org/users/rafal/b43-next
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
f078f209
LR		 20#include <asm/unaligned.h>
21
af03abec 22#include "hw.h"
d70357d5 23#include "hw-ops.h"
cfe8cba9 24#include "rc.h"
b622a720 25#include "ar9003_mac.h"
f4701b5a 26#include "ar9003_mci.h"
362cd03f 27#include "ar9003_phy.h"
462e58f2
BG		 28#include "debug.h"
29#include "ath9k.h"
f078f209 30
cbe61d8a 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 32
7322fd19
LR		 33MODULE_AUTHOR("Atheros Communications");
34MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36MODULE_LICENSE("Dual BSD/GPL");
37
38static int __init ath9k_init(void)
39{
40 return 0;
41}
42module_init(ath9k_init);
43
44static void __exit ath9k_exit(void)
45{
46 return;
47}
48module_exit(ath9k_exit);
49
d70357d5
LR		 50/* Private hardware callbacks */
51
52static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
55}
56
64773964
LR		 57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59{
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61}
62
991312d8
LR		 63static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64{
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69}
70
e36b27af
LR		 71static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72{
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78}
79
f1dc5600
S		 80/********************/
81/* Helper Functions */
82/********************/
f078f209 83
462e58f2
BG		 84#ifdef CONFIG_ATH9K_DEBUGFS
85
86void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
87{
88 struct ath_softc *sc = common->priv;
89 if (sync_cause)
90 sc->debug.stats.istats.sync_cause_all++;
91 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
92 sc->debug.stats.istats.sync_rtc_irq++;
93 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
94 sc->debug.stats.istats.sync_mac_irq++;
95 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
96 sc->debug.stats.istats.eeprom_illegal_access++;
97 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
98 sc->debug.stats.istats.apb_timeout++;
99 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
100 sc->debug.stats.istats.pci_mode_conflict++;
101 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
102 sc->debug.stats.istats.host1_fatal++;
103 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
104 sc->debug.stats.istats.host1_perr++;
105 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
106 sc->debug.stats.istats.trcv_fifo_perr++;
107 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
108 sc->debug.stats.istats.radm_cpl_ep++;
109 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
110 sc->debug.stats.istats.radm_cpl_dllp_abort++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
112 sc->debug.stats.istats.radm_cpl_tlp_abort++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
114 sc->debug.stats.istats.radm_cpl_ecrc_err++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
116 sc->debug.stats.istats.radm_cpl_timeout++;
117 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
118 sc->debug.stats.istats.local_timeout++;
119 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
120 sc->debug.stats.istats.pm_access++;
121 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
122 sc->debug.stats.istats.mac_awake++;
123 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
124 sc->debug.stats.istats.mac_asleep++;
125 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
126 sc->debug.stats.istats.mac_sleep_access++;
127}
128#endif
129
130
dfdac8ac 131static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 132{
b002a4a9 133 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
dfdac8ac
FF		 134 struct ath_common *common = ath9k_hw_common(ah);
135 unsigned int clockrate;
cbe61d8a 136
087b6ff6
FF		 137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
138 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
139 clockrate = 117;
140 else if (!ah->curchan) /* should really check for CCK instead */
dfdac8ac 141 clockrate = ATH9K_CLOCK_RATE_CCK;
675a0b04 142 else if (conf->chandef.chan->band == IEEE80211_BAND_2GHZ)
dfdac8ac
FF		 143 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
144 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
145 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 146 else
dfdac8ac
FF		 147 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
148
149 if (conf_is_ht40(conf))
150 clockrate *= 2;
151
906c7205
FF		 152 if (ah->curchan) {
153 if (IS_CHAN_HALF_RATE(ah->curchan))
154 clockrate /= 2;
155 if (IS_CHAN_QUARTER_RATE(ah->curchan))
156 clockrate /= 4;
157 }
158
dfdac8ac 159 common->clockrate = clockrate;
f1dc5600
S		 160}
161
cbe61d8a 162static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 163{
dfdac8ac 164 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 165
dfdac8ac 166 return usecs * common->clockrate;
f1dc5600 167}
f078f209 168
0caa7b14 169bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 170{
171 int i;
172
0caa7b14
S		 173 BUG_ON(timeout < AH_TIME_QUANTUM);
174
175 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 176 if ((REG_READ(ah, reg) & mask) == val)
177 return true;
178
179 udelay(AH_TIME_QUANTUM);
180 }
04bd4638 181
d2182b69 182 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 183 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
184 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 185
f1dc5600 186 return false;
f078f209 187}
7322fd19 188EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 189
7c5adc8d
FF		 190void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
191 int hw_delay)
192{
193 if (IS_CHAN_B(chan))
194 hw_delay = (4 * hw_delay) / 22;
195 else
196 hw_delay /= 10;
197
198 if (IS_CHAN_HALF_RATE(chan))
199 hw_delay *= 2;
200 else if (IS_CHAN_QUARTER_RATE(chan))
201 hw_delay *= 4;
202
203 udelay(hw_delay + BASE_ACTIVATE_DELAY);
204}
205
0166b4be 206void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 207 int column, unsigned int *writecnt)
208{
209 int r;
210
211 ENABLE_REGWRITE_BUFFER(ah);
212 for (r = 0; r < array->ia_rows; r++) {
213 REG_WRITE(ah, INI_RA(array, r, 0),
214 INI_RA(array, r, column));
215 DO_DELAY(*writecnt);
216 }
217 REGWRITE_BUFFER_FLUSH(ah);
218}
219
f078f209
LR		 220u32 ath9k_hw_reverse_bits(u32 val, u32 n)
221{
222 u32 retval;
223 int i;
224
225 for (i = 0, retval = 0; i < n; i++) {
226 retval = (retval << 1) | (val & 1);
227 val >>= 1;
228 }
229 return retval;
230}
231
cbe61d8a 232u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 233 u8 phy, int kbps,
f1dc5600
S		 234 u32 frameLen, u16 rateix,
235 bool shortPreamble)
f078f209 236{
f1dc5600 237 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 238
f1dc5600
S		 239 if (kbps == 0)
240 return 0;
f078f209 241
545750d3 242 switch (phy) {
46d14a58 243 case WLAN_RC_PHY_CCK:
f1dc5600 244 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 245 if (shortPreamble)
f1dc5600
S		 246 phyTime >>= 1;
247 numBits = frameLen << 3;
248 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
249 break;
46d14a58 250 case WLAN_RC_PHY_OFDM:
2660b81a 251 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 252 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
253 numBits = OFDM_PLCP_BITS + (frameLen << 3);
254 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
255 txTime = OFDM_SIFS_TIME_QUARTER
256 + OFDM_PREAMBLE_TIME_QUARTER
257 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 258 } else if (ah->curchan &&
259 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 260 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
261 numBits = OFDM_PLCP_BITS + (frameLen << 3);
262 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
263 txTime = OFDM_SIFS_TIME_HALF +
264 OFDM_PREAMBLE_TIME_HALF
265 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
266 } else {
267 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
268 numBits = OFDM_PLCP_BITS + (frameLen << 3);
269 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
270 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
271 + (numSymbols * OFDM_SYMBOL_TIME);
272 }
273 break;
274 default:
3800276a
JP		 275 ath_err(ath9k_hw_common(ah),
276 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 277 txTime = 0;
278 break;
279 }
f078f209 280
f1dc5600
S		 281 return txTime;
282}
7322fd19 283EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 284
cbe61d8a 285void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 286 struct ath9k_channel *chan,
287 struct chan_centers *centers)
f078f209 288{
f1dc5600 289 int8_t extoff;
f078f209 290
f1dc5600
S		 291 if (!IS_CHAN_HT40(chan)) {
292 centers->ctl_center = centers->ext_center =
293 centers->synth_center = chan->channel;
294 return;
f078f209 295 }
f078f209 296
f1dc5600
S		 297 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
298 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
299 centers->synth_center =
300 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
301 extoff = 1;
302 } else {
303 centers->synth_center =
304 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
305 extoff = -1;
306 }
f078f209 307
f1dc5600
S		 308 centers->ctl_center =
309 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 310 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 311 centers->ext_center =
6420014c 312 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 313}
314
f1dc5600
S		 315/******************/
316/* Chip Revisions */
317/******************/
318
cbe61d8a 319static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 320{
f1dc5600 321 u32 val;
f078f209 322
ecb1d385
VT		 323 switch (ah->hw_version.devid) {
324 case AR5416_AR9100_DEVID:
325 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
326 break;
3762561a
GJ		 327 case AR9300_DEVID_AR9330:
328 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
329 if (ah->get_mac_revision) {
330 ah->hw_version.macRev = ah->get_mac_revision();
331 } else {
332 val = REG_READ(ah, AR_SREV);
333 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
334 }
335 return;
ecb1d385
VT		 336 case AR9300_DEVID_AR9340:
337 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
338 val = REG_READ(ah, AR_SREV);
339 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
340 return;
813831dc
GJ		 341 case AR9300_DEVID_QCA955X:
342 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
343 return;
ecb1d385
VT		 344 }
345
f1dc5600 346 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 347
f1dc5600
S		 348 if (val == 0xFF) {
349 val = REG_READ(ah, AR_SREV);
d535a42a
S		 350 ah->hw_version.macVersion =
351 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
352 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 353
77fac465 354 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 355 ah->is_pciexpress = true;
356 else
357 ah->is_pciexpress = (val &
358 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 359 } else {
360 if (!AR_SREV_9100(ah))
d535a42a 361 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 362
d535a42a 363 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 364
d535a42a 365 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 366 ah->is_pciexpress = true;
f1dc5600 367 }
f078f209
LR		 368}
369
f1dc5600
S		 370/************************************/
371/* HW Attach, Detach, Init Routines */
372/************************************/
373
cbe61d8a 374static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 375{
040b74f7 376 if (!AR_SREV_5416(ah))
f1dc5600 377 return;
f078f209 378
f1dc5600
S		 379 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
380 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
384 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
385 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
386 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
387 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 388
f1dc5600 389 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 390}
391
1f3f0618 392/* This should work for all families including legacy */
cbe61d8a 393static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 394{
c46917bb 395 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 396 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 397 u32 regHold[2];
07b2fa5a
JP		 398 static const u32 patternData[4] = {
399 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
400 };
1f3f0618 401 int i, j, loop_max;
f078f209 402
1f3f0618
SB		 403 if (!AR_SREV_9300_20_OR_LATER(ah)) {
404 loop_max = 2;
405 regAddr[1] = AR_PHY_BASE + (8 << 2);
406 } else
407 loop_max = 1;
408
409 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 410 u32 addr = regAddr[i];
411 u32 wrData, rdData;
f078f209 412
f1dc5600
S		 413 regHold[i] = REG_READ(ah, addr);
414 for (j = 0; j < 0x100; j++) {
415 wrData = (j << 16) | j;
416 REG_WRITE(ah, addr, wrData);
417 rdData = REG_READ(ah, addr);
418 if (rdData != wrData) {
3800276a
JP		 419 ath_err(common,
420 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
421 addr, wrData, rdData);
f1dc5600
S		 422 return false;
423 }
424 }
425 for (j = 0; j < 4; j++) {
426 wrData = patternData[j];
427 REG_WRITE(ah, addr, wrData);
428 rdData = REG_READ(ah, addr);
429 if (wrData != rdData) {
3800276a
JP		 430 ath_err(common,
431 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
432 addr, wrData, rdData);
f1dc5600
S		 433 return false;
434 }
f078f209 435 }
f1dc5600 436 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 437 }
f1dc5600 438 udelay(100);
cbe61d8a 439
f078f209
LR		 440 return true;
441}
442
b8b0f377 443static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 444{
445 int i;
f078f209 446
689e756f
FF		 447 ah->config.dma_beacon_response_time = 1;
448 ah->config.sw_beacon_response_time = 6;
2660b81a
S		 449 ah->config.additional_swba_backoff = 0;
450 ah->config.ack_6mb = 0x0;
451 ah->config.cwm_ignore_extcca = 0;
2660b81a 452 ah->config.pcie_clock_req = 0;
2660b81a
S		 453 ah->config.pcie_waen = 0;
454 ah->config.analog_shiftreg = 1;
03c72518 455 ah->config.enable_ani = true;
f078f209 456
f1dc5600 457 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 458 ah->config.spurchans[i][0] = AR_NO_SPUR;
459 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 460 }
461
0ce024cb 462 ah->config.rx_intr_mitigation = true;
6a0ec30a 463 ah->config.pcieSerDesWrite = true;
6158425b
LR		 464
465 /*
466 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
467 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
468 * This means we use it for all AR5416 devices, and the few
469 * minor PCI AR9280 devices out there.
470 *
471 * Serialization is required because these devices do not handle
472 * well the case of two concurrent reads/writes due to the latency
473 * involved. During one read/write another read/write can be issued
474 * on another CPU while the previous read/write may still be working
475 * on our hardware, if we hit this case the hardware poops in a loop.
476 * We prevent this by serializing reads and writes.
477 *
478 * This issue is not present on PCI-Express devices or pre-AR5416
479 * devices (legacy, 802.11abg).
480 */
481 if (num_possible_cpus() > 1)
2d6a5e95 482 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 483}
484
50aca25b 485static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 486{
608b88cb
LR		 487 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
488
489 regulatory->country_code = CTRY_DEFAULT;
490 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 491
d535a42a 492 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 493 ah->hw_version.subvendorid = 0;
f078f209 494
2660b81a 495 ah->atim_window = 0;
16f2411f
FF		 496 ah->sta_id1_defaults =
497 AR_STA_ID1_CRPT_MIC_ENABLE |
498 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 499 if (AR_SREV_9100(ah))
500 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
e3f2acc7 501 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 502 ah->globaltxtimeout = (u32) -1;
cbdec975 503 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 504 ah->htc_reset_init = true;
f078f209
LR		 505}
506
cbe61d8a 507static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 508{
1510718d 509 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 510 u32 sum;
511 int i;
512 u16 eeval;
07b2fa5a 513 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 514
515 sum = 0;
516 for (i = 0; i < 3; i++) {
49101676 517 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 518 sum += eeval;
1510718d
LR		 519 common->macaddr[2 * i] = eeval >> 8;
520 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 521 }
d8baa939 522 if (sum == 0 || sum == 0xffff * 3)
f078f209 523 return -EADDRNOTAVAIL;
f078f209
LR		 524
525 return 0;
526}
527
f637cfd6 528static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 529{
6cae913d 530 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 531 int ecode;
f078f209 532
6cae913d 533 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 534 if (!ath9k_hw_chip_test(ah))
535 return -ENODEV;
536 }
f078f209 537
ebd5a14a
LR		 538 if (!AR_SREV_9300_20_OR_LATER(ah)) {
539 ecode = ar9002_hw_rf_claim(ah);
540 if (ecode != 0)
541 return ecode;
542 }
f078f209 543
f637cfd6 544 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 545 if (ecode != 0)
546 return ecode;
7d01b221 547
d2182b69 548 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 549 ah->eep_ops->get_eeprom_ver(ah),
550 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 551
f5ffe23a 552 if (ah->config.enable_ani)
f637cfd6 553 ath9k_hw_ani_init(ah);
f078f209 554
f078f209
LR		 555 return 0;
556}
557
c1b976d2 558static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 559{
c1b976d2
FF		 560 if (!AR_SREV_9300_20_OR_LATER(ah))
561 return ar9002_hw_attach_ops(ah);
562
563 ar9003_hw_attach_ops(ah);
564 return 0;
aa4058ae
LR		 565}
566
d70357d5
LR		 567/* Called for all hardware families */
568static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 569{
c46917bb 570 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 571 int r = 0;
aa4058ae 572
ac45c12d
SB		 573 ath9k_hw_read_revisions(ah);
574
0a8d7cb0
SB		 575 /*
576 * Read back AR_WA into a permanent copy and set bits 14 and 17.
577 * We need to do this to avoid RMW of this register. We cannot
578 * read the reg when chip is asleep.
579 */
580 ah->WARegVal = REG_READ(ah, AR_WA);
581 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
582 AR_WA_ASPM_TIMER_BASED_DISABLE);
583
aa4058ae 584 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 585 ath_err(common, "Couldn't reset chip\n");
95fafca2 586 return -EIO;
aa4058ae
LR		 587 }
588
423e38e8 589 if (AR_SREV_9462(ah))
eec353c5
RM		 590 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
591
a4a2954f
SM		 592 if (AR_SREV_9565(ah)) {
593 ah->WARegVal |= AR_WA_BIT22;
594 REG_WRITE(ah, AR_WA, ah->WARegVal);
595 }
596
bab1f62e
LR		 597 ath9k_hw_init_defaults(ah);
598 ath9k_hw_init_config(ah);
599
c1b976d2
FF		 600 r = ath9k_hw_attach_ops(ah);
601 if (r)
602 return r;
d70357d5 603
9ecdef4b 604 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 605 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 606 return -EIO;
aa4058ae
LR		 607 }
608
f3eef645 609 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
aa4058ae 610 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
7508b657 611 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
4c85ab11 612 !ah->is_pciexpress)) {
aa4058ae
LR		 613 ah->config.serialize_regmode =
614 SER_REG_MODE_ON;
615 } else {
616 ah->config.serialize_regmode =
617 SER_REG_MODE_OFF;
618 }
619 }
620
d2182b69 621 ath_dbg(common, RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 622 ah->config.serialize_regmode);
623
f4709fdf
LR		 624 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
625 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
626 else
627 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
628
6da5a720
FF		 629 switch (ah->hw_version.macVersion) {
630 case AR_SREV_VERSION_5416_PCI:
631 case AR_SREV_VERSION_5416_PCIE:
632 case AR_SREV_VERSION_9160:
633 case AR_SREV_VERSION_9100:
634 case AR_SREV_VERSION_9280:
635 case AR_SREV_VERSION_9285:
636 case AR_SREV_VERSION_9287:
637 case AR_SREV_VERSION_9271:
638 case AR_SREV_VERSION_9300:
2c8e5937 639 case AR_SREV_VERSION_9330:
6da5a720 640 case AR_SREV_VERSION_9485:
bca04689 641 case AR_SREV_VERSION_9340:
423e38e8 642 case AR_SREV_VERSION_9462:
2b943a33 643 case AR_SREV_VERSION_9550:
77fac465 644 case AR_SREV_VERSION_9565:
6da5a720
FF		 645 break;
646 default:
3800276a
JP		 647 ath_err(common,
648 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
649 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 650 return -EOPNOTSUPP;
aa4058ae
LR		 651 }
652
2c8e5937 653 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 654 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 655 ah->is_pciexpress = false;
656
aa4058ae 657 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 658 ath9k_hw_init_cal_settings(ah);
659
660 ah->ani_function = ATH9K_ANI_ALL;
7a37081e 661 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 662 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 663 if (!AR_SREV_9300_20_OR_LATER(ah))
664 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae 665
69ce674b 666 if (!ah->is_pciexpress)
aa4058ae
LR		 667 ath9k_hw_disablepcie(ah);
668
f637cfd6 669 r = ath9k_hw_post_init(ah);
aa4058ae 670 if (r)
95fafca2 671 return r;
aa4058ae
LR		 672
673 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 674 r = ath9k_hw_fill_cap_info(ah);
675 if (r)
676 return r;
677
4f3acf81
LR		 678 r = ath9k_hw_init_macaddr(ah);
679 if (r) {
3800276a 680 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 681 return r;
f078f209
LR		 682 }
683
d7e7d229 684 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 685 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 686 else
2660b81a 687 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 688
88e641df
GJ		 689 if (AR_SREV_9330(ah))
690 ah->bb_watchdog_timeout_ms = 85;
691 else
692 ah->bb_watchdog_timeout_ms = 25;
f078f209 693
211f5859
LR		 694 common->state = ATH_HW_INITIALIZED;
695
4f3acf81 696 return 0;
f078f209
LR		 697}
698
d70357d5 699int ath9k_hw_init(struct ath_hw *ah)
f078f209 700{
d70357d5
LR		 701 int ret;
702 struct ath_common *common = ath9k_hw_common(ah);
f078f209 703
77fac465 704 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 705 switch (ah->hw_version.devid) {
706 case AR5416_DEVID_PCI:
707 case AR5416_DEVID_PCIE:
708 case AR5416_AR9100_DEVID:
709 case AR9160_DEVID_PCI:
710 case AR9280_DEVID_PCI:
711 case AR9280_DEVID_PCIE:
712 case AR9285_DEVID_PCIE:
db3cc53a
SB		 713 case AR9287_DEVID_PCI:
714 case AR9287_DEVID_PCIE:
d70357d5 715 case AR2427_DEVID_PCIE:
db3cc53a 716 case AR9300_DEVID_PCIE:
3050c914 717 case AR9300_DEVID_AR9485_PCIE:
999a7a88 718 case AR9300_DEVID_AR9330:
bca04689 719 case AR9300_DEVID_AR9340:
2b943a33 720 case AR9300_DEVID_QCA955X:
5a63ef0f 721 case AR9300_DEVID_AR9580:
423e38e8 722 case AR9300_DEVID_AR9462:
d4e5979c 723 case AR9485_DEVID_AR1111:
77fac465 724 case AR9300_DEVID_AR9565:
d70357d5
LR		 725 break;
726 default:
727 if (common->bus_ops->ath_bus_type == ATH_USB)
728 break;
3800276a
JP		 729 ath_err(common, "Hardware device ID 0x%04x not supported\n",
730 ah->hw_version.devid);
d70357d5
LR		 731 return -EOPNOTSUPP;
732 }
f078f209 733
d70357d5
LR		 734 ret = __ath9k_hw_init(ah);
735 if (ret) {
3800276a
JP		 736 ath_err(common,
737 "Unable to initialize hardware; initialization status: %d\n",
738 ret);
d70357d5
LR		 739 return ret;
740 }
f078f209 741
d70357d5 742 return 0;
f078f209 743}
d70357d5 744EXPORT_SYMBOL(ath9k_hw_init);
f078f209 745
cbe61d8a 746static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 747{
7d0d0df0
S		 748 ENABLE_REGWRITE_BUFFER(ah);
749
f1dc5600
S		 750 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
751 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 752
f1dc5600
S		 753 REG_WRITE(ah, AR_QOS_NO_ACK,
754 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
755 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
756 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
757
758 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
759 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
760 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
761 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
762 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 763
764 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 765}
766
b84628eb 767u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 768{
f18e3c6b
MSS		 769 struct ath_common *common = ath9k_hw_common(ah);
770 int i = 0;
771
ca7a4deb
FF		 772 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
773 udelay(100);
774 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 775
f18e3c6b
MSS		 776 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
777
ca7a4deb 778 udelay(100);
b1415819 779
f18e3c6b
MSS		 780 if (WARN_ON_ONCE(i >= 100)) {
781 ath_err(common, "PLL4 meaurement not done\n");
782 break;
783 }
784
785 i++;
786 }
787
ca7a4deb 788 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 789}
790EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
791
cbe61d8a 792static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 793 struct ath9k_channel *chan)
f078f209 794{
d09b17f7
VT		 795 u32 pll;
796
a4a2954f 797 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 798 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
800 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
801 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
802 AR_CH0_DPLL2_KD, 0x40);
803 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
804 AR_CH0_DPLL2_KI, 0x4);
22983c30 805
3dfd7f60
VT		 806 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
807 AR_CH0_BB_DPLL1_REFDIV, 0x5);
808 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
809 AR_CH0_BB_DPLL1_NINI, 0x58);
810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
811 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 812
813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 814 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
816 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 818 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 819
3dfd7f60 820 /* program BB PLL phase_shift to 0x6 */
22983c30 821 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 822 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
823
824 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
825 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 826 udelay(1000);
a5415d62
GJ		 827 } else if (AR_SREV_9330(ah)) {
828 u32 ddr_dpll2, pll_control2, kd;
829
830 if (ah->is_clk_25mhz) {
831 ddr_dpll2 = 0x18e82f01;
832 pll_control2 = 0xe04a3d;
833 kd = 0x1d;
834 } else {
835 ddr_dpll2 = 0x19e82f01;
836 pll_control2 = 0x886666;
837 kd = 0x3d;
838 }
839
840 /* program DDR PLL ki and kd value */
841 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
842
843 /* program DDR PLL phase_shift */
844 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
845 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
846
847 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
848 udelay(1000);
849
850 /* program refdiv, nint, frac to RTC register */
851 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
852
853 /* program BB PLL kd and ki value */
854 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
855 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
856
857 /* program BB PLL phase_shift */
858 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
859 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
fc05a317 860 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 861 u32 regval, pll2_divint, pll2_divfrac, refdiv;
862
863 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
864 udelay(1000);
865
866 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
867 udelay(100);
868
869 if (ah->is_clk_25mhz) {
870 pll2_divint = 0x54;
871 pll2_divfrac = 0x1eb85;
872 refdiv = 3;
873 } else {
fc05a317
GJ		 874 if (AR_SREV_9340(ah)) {
875 pll2_divint = 88;
876 pll2_divfrac = 0;
877 refdiv = 5;
878 } else {
879 pll2_divint = 0x11;
880 pll2_divfrac = 0x26666;
881 refdiv = 1;
882 }
0b488ac6
VT		 883 }
884
885 regval = REG_READ(ah, AR_PHY_PLL_MODE);
886 regval |= (0x1 << 16);
887 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
888 udelay(100);
889
890 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
891 (pll2_divint << 18) | pll2_divfrac);
892 udelay(100);
893
894 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317
GJ		 895 if (AR_SREV_9340(ah))
896 regval = (regval & 0x80071fff) | (0x1 << 30) |
897 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
898 else
899 regval = (regval & 0x80071fff) | (0x3 << 30) |
900 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
0b488ac6
VT		 901 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
902 REG_WRITE(ah, AR_PHY_PLL_MODE,
903 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
904 udelay(1000);
22983c30 905 }
d09b17f7
VT		 906
907 pll = ath9k_hw_compute_pll_control(ah, chan);
8565f8bf
SM		 908 if (AR_SREV_9565(ah))
909 pll |= 0x40000;
d03a66c1 910 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 911
fc05a317
GJ		 912 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
913 AR_SREV_9550(ah))
3dfd7f60
VT		 914 udelay(1000);
915
c75724d1
LR		 916 /* Switch the core clock for ar9271 to 117Mhz */
917 if (AR_SREV_9271(ah)) {
25e2ab17
S		 918 udelay(500);
919 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 920 }
921
f1dc5600
S		 922 udelay(RTC_PLL_SETTLE_DELAY);
923
924 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6 925
fc05a317 926 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 927 if (ah->is_clk_25mhz) {
928 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
929 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
930 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
931 } else {
932 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
933 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
934 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
935 }
936 udelay(100);
937 }
f078f209
LR		 938}
939
cbe61d8a 940static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 941 enum nl80211_iftype opmode)
f078f209 942{
79d1d2b8 943 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 944 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 945 AR_IMR_TXURN |
946 AR_IMR_RXERR |
947 AR_IMR_RXORN |
948 AR_IMR_BCNMISC;
f078f209 949
3b8a0577 950 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
79d1d2b8
VT		 951 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
952
66860240
VT		 953 if (AR_SREV_9300_20_OR_LATER(ah)) {
954 imr_reg |= AR_IMR_RXOK_HP;
955 if (ah->config.rx_intr_mitigation)
956 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
957 else
958 imr_reg |= AR_IMR_RXOK_LP;
f078f209 959
66860240
VT		 960 } else {
961 if (ah->config.rx_intr_mitigation)
962 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
963 else
964 imr_reg |= AR_IMR_RXOK;
965 }
f078f209 966
66860240
VT		 967 if (ah->config.tx_intr_mitigation)
968 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
969 else
970 imr_reg |= AR_IMR_TXOK;
f078f209 971
7d0d0df0
S		 972 ENABLE_REGWRITE_BUFFER(ah);
973
152d530d 974 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 975 ah->imrs2_reg |= AR_IMR_S2_GTT;
976 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 977
f1dc5600
S		 978 if (!AR_SREV_9100(ah)) {
979 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 980 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 981 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
982 }
66860240 983
7d0d0df0 984 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 985
66860240
VT		 986 if (AR_SREV_9300_20_OR_LATER(ah)) {
987 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
988 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
989 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
990 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
991 }
f078f209
LR		 992}
993
b6ba41bb
FF		 994static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
995{
996 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
997 val = min(val, (u32) 0xFFFF);
998 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
999}
1000
0005baf4 1001static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 1002{
0005baf4
FF		 1003 u32 val = ath9k_hw_mac_to_clks(ah, us);
1004 val = min(val, (u32) 0xFFFF);
1005 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 1006}
1007
0005baf4 1008static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1009{
0005baf4
FF		 1010 u32 val = ath9k_hw_mac_to_clks(ah, us);
1011 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1012 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1013}
1014
1015static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1016{
1017 u32 val = ath9k_hw_mac_to_clks(ah, us);
1018 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1019 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 1020}
f1dc5600 1021
cbe61d8a 1022static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1023{
f078f209 1024 if (tu > 0xFFFF) {
d2182b69
JP		 1025 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1026 tu);
2660b81a 1027 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1028 return false;
1029 } else {
1030 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1031 ah->globaltxtimeout = tu;
f078f209
LR		 1032 return true;
1033 }
1034}
1035
0005baf4 1036void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1037{
b6ba41bb
FF		 1038 struct ath_common *common = ath9k_hw_common(ah);
1039 struct ieee80211_conf *conf = &common->hw->conf;
1040 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 1041 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 1042 int slottime;
0005baf4 1043 int sifstime;
b6ba41bb
FF		 1044 int rx_lat = 0, tx_lat = 0, eifs = 0;
1045 u32 reg;
0005baf4 1046
d2182b69 1047 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1048 ah->misc_mode);
f078f209 1049
b6ba41bb
FF		 1050 if (!chan)
1051 return;
1052
2660b81a 1053 if (ah->misc_mode != 0)
ca7a4deb 1054 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1055
81a91d57
RM		 1056 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1057 rx_lat = 41;
1058 else
1059 rx_lat = 37;
b6ba41bb
FF		 1060 tx_lat = 54;
1061
e88e4861
FF		 1062 if (IS_CHAN_5GHZ(chan))
1063 sifstime = 16;
1064 else
1065 sifstime = 10;
1066
b6ba41bb
FF		 1067 if (IS_CHAN_HALF_RATE(chan)) {
1068 eifs = 175;
1069 rx_lat *= 2;
1070 tx_lat *= 2;
1071 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1072 tx_lat += 11;
1073
e88e4861 1074 sifstime *= 2;
e115b7ec 1075 ack_offset = 16;
b6ba41bb 1076 slottime = 13;
b6ba41bb
FF		 1077 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1078 eifs = 340;
81a91d57 1079 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1080 tx_lat *= 4;
1081 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1082 tx_lat += 22;
1083
e88e4861 1084 sifstime *= 4;
e115b7ec 1085 ack_offset = 32;
b6ba41bb 1086 slottime = 21;
b6ba41bb 1087 } else {
a7be039d
RM		 1088 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1089 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1090 reg = AR_USEC_ASYNC_FIFO;
1091 } else {
1092 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1093 common->clockrate;
1094 reg = REG_READ(ah, AR_USEC);
1095 }
b6ba41bb
FF		 1096 rx_lat = MS(reg, AR_USEC_RX_LAT);
1097 tx_lat = MS(reg, AR_USEC_TX_LAT);
1098
1099 slottime = ah->slottime;
b6ba41bb 1100 }
0005baf4 1101
e239d859 1102 /* As defined by IEEE 802.11-2007 17.3.8.6 */
e115b7ec 1103 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset;
adb5066a 1104 ctstimeout = acktimeout;
42c4568a
FF		 1105
1106 /*
1107 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1108 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1109 * This was initially only meant to work around an issue with delayed
1110 * BA frames in some implementations, but it has been found to fix ACK
1111 * timeout issues in other cases as well.
1112 */
675a0b04
KB		 1113 if (conf->chandef.chan &&
1114 conf->chandef.chan->band == IEEE80211_BAND_2GHZ &&
e115b7ec 1115 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1116 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1117 ctstimeout += 48 - sifstime - ah->slottime;
1118 }
1119
42c4568a 1120
b6ba41bb
FF		 1121 ath9k_hw_set_sifs_time(ah, sifstime);
1122 ath9k_hw_setslottime(ah, slottime);
0005baf4 1123 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1124 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1125 if (ah->globaltxtimeout != (u32) -1)
1126 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1127
1128 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1129 REG_RMW(ah, AR_USEC,
1130 (common->clockrate - 1) |
1131 SM(rx_lat, AR_USEC_RX_LAT) |
1132 SM(tx_lat, AR_USEC_TX_LAT),
1133 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1134
f1dc5600 1135}
0005baf4 1136EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1137
285f2dda 1138void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1139{
211f5859
LR		 1140 struct ath_common *common = ath9k_hw_common(ah);
1141
736b3a27 1142 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1143 return;
211f5859 1144
9ecdef4b 1145 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1146}
285f2dda 1147EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1148
f1dc5600
S		 1149/*******/
1150/* INI */
1151/*******/
1152
8fe65368 1153u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1154{
1155 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1156
1157 if (IS_CHAN_B(chan))
1158 ctl |= CTL_11B;
1159 else if (IS_CHAN_G(chan))
1160 ctl |= CTL_11G;
1161 else
1162 ctl |= CTL_11A;
1163
1164 return ctl;
1165}
1166
f1dc5600
S		 1167/****************************************/
1168/* Reset and Channel Switching Routines */
1169/****************************************/
f1dc5600 1170
cbe61d8a 1171static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1172{
57b32227 1173 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 1174
7d0d0df0
S		 1175 ENABLE_REGWRITE_BUFFER(ah);
1176
d7e7d229
LR		 1177 /*
1178 * set AHB_MODE not to do cacheline prefetches
1179 */
ca7a4deb
FF		 1180 if (!AR_SREV_9300_20_OR_LATER(ah))
1181 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1182
d7e7d229
LR		 1183 /*
1184 * let mac dma reads be in 128 byte chunks
1185 */
ca7a4deb 1186 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1187
7d0d0df0 1188 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1189
d7e7d229
LR		 1190 /*
1191 * Restore TX Trigger Level to its pre-reset value.
1192 * The initial value depends on whether aggregation is enabled, and is
1193 * adjusted whenever underruns are detected.
1194 */
57b32227
FF		 1195 if (!AR_SREV_9300_20_OR_LATER(ah))
1196 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1197
7d0d0df0 1198 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1199
d7e7d229
LR		 1200 /*
1201 * let mac dma writes be in 128 byte chunks
1202 */
ca7a4deb 1203 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1204
d7e7d229
LR		 1205 /*
1206 * Setup receive FIFO threshold to hold off TX activities
1207 */
f1dc5600
S		 1208 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1209
57b32227
FF		 1210 if (AR_SREV_9300_20_OR_LATER(ah)) {
1211 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1212 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1213
1214 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1215 ah->caps.rx_status_len);
1216 }
1217
d7e7d229
LR		 1218 /*
1219 * reduce the number of usable entries in PCU TXBUF to avoid
1220 * wrap around issues.
1221 */
f1dc5600 1222 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1223 /* For AR9285 the number of Fifos are reduced to half.
1224 * So set the usable tx buf size also to half to
1225 * avoid data/delimiter underruns
1226 */
f1dc5600
S		 1227 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1228 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1229 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1230 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1231 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1232 }
744d4025 1233
7d0d0df0 1234 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1235
744d4025
VT		 1236 if (AR_SREV_9300_20_OR_LATER(ah))
1237 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1238}
1239
cbe61d8a 1240static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1241{
ca7a4deb
FF		 1242 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1243 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1244
f1dc5600 1245 switch (opmode) {
d97809db 1246 case NL80211_IFTYPE_ADHOC:
9cb5412b 1247 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb 1248 set |= AR_STA_ID1_ADHOC;
f1dc5600 1249 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1250 break;
ca7a4deb
FF		 1251 case NL80211_IFTYPE_AP:
1252 set |= AR_STA_ID1_STA_AP;
1253 /* fall through */
d97809db 1254 case NL80211_IFTYPE_STATION:
ca7a4deb 1255 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1256 break;
5f841b41 1257 default:
ca7a4deb
FF		 1258 if (!ah->is_monitoring)
1259 set = 0;
5f841b41 1260 break;
f1dc5600 1261 }
ca7a4deb 1262 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1263}
1264
8fe65368
LR		 1265void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1266 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1267{
1268 u32 coef_exp, coef_man;
1269
1270 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1271 if ((coef_scaled >> coef_exp) & 0x1)
1272 break;
1273
1274 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1275
1276 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1277
1278 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1279 *coef_exponent = coef_exp - 16;
1280}
1281
cbe61d8a 1282static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1283{
1284 u32 rst_flags;
1285 u32 tmpReg;
1286
70768496 1287 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1288 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1289 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1290 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1291 }
1292
7d0d0df0
S		 1293 ENABLE_REGWRITE_BUFFER(ah);
1294
9a658d2b
LR		 1295 if (AR_SREV_9300_20_OR_LATER(ah)) {
1296 REG_WRITE(ah, AR_WA, ah->WARegVal);
1297 udelay(10);
1298 }
1299
f1dc5600
S		 1300 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1301 AR_RTC_FORCE_WAKE_ON_INT);
1302
1303 if (AR_SREV_9100(ah)) {
1304 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1305 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1306 } else {
1307 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1308 if (tmpReg &
1309 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1310 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1311 u32 val;
f1dc5600 1312 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1313
1314 val = AR_RC_HOSTIF;
1315 if (!AR_SREV_9300_20_OR_LATER(ah))
1316 val |= AR_RC_AHB;
1317 REG_WRITE(ah, AR_RC, val);
1318
1319 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1320 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1321
1322 rst_flags = AR_RTC_RC_MAC_WARM;
1323 if (type == ATH9K_RESET_COLD)
1324 rst_flags |= AR_RTC_RC_MAC_COLD;
1325 }
1326
7d95847c
GJ		 1327 if (AR_SREV_9330(ah)) {
1328 int npend = 0;
1329 int i;
1330
1331 /* AR9330 WAR:
1332 * call external reset function to reset WMAC if:
1333 * - doing a cold reset
1334 * - we have pending frames in the TX queues
1335 */
1336
1337 for (i = 0; i < AR_NUM_QCU; i++) {
1338 npend = ath9k_hw_numtxpending(ah, i);
1339 if (npend)
1340 break;
1341 }
1342
1343 if (ah->external_reset &&
1344 (npend || type == ATH9K_RESET_COLD)) {
1345 int reset_err = 0;
1346
d2182b69 1347 ath_dbg(ath9k_hw_common(ah), RESET,
7d95847c
GJ		 1348 "reset MAC via external reset\n");
1349
1350 reset_err = ah->external_reset();
1351 if (reset_err) {
1352 ath_err(ath9k_hw_common(ah),
1353 "External reset failed, err=%d\n",
1354 reset_err);
1355 return false;
1356 }
1357
1358 REG_WRITE(ah, AR_RTC_RESET, 1);
1359 }
1360 }
1361
3863495b 1362 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1363 ar9003_mci_check_gpm_offset(ah);
3863495b 1364
d03a66c1 1365 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1366
1367 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1368
f1dc5600
S		 1369 udelay(50);
1370
d03a66c1 1371 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1372 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1373 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1374 return false;
1375 }
1376
1377 if (!AR_SREV_9100(ah))
1378 REG_WRITE(ah, AR_RC, 0);
1379
f1dc5600
S		 1380 if (AR_SREV_9100(ah))
1381 udelay(50);
1382
1383 return true;
1384}
1385
cbe61d8a 1386static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1387{
7d0d0df0
S		 1388 ENABLE_REGWRITE_BUFFER(ah);
1389
9a658d2b
LR		 1390 if (AR_SREV_9300_20_OR_LATER(ah)) {
1391 REG_WRITE(ah, AR_WA, ah->WARegVal);
1392 udelay(10);
1393 }
1394
f1dc5600
S		 1395 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1396 AR_RTC_FORCE_WAKE_ON_INT);
1397
42d5bc3f 1398 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1399 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1400
d03a66c1 1401 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1402
7d0d0df0 1403 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1404
84e2169b
SB		 1405 if (!AR_SREV_9300_20_OR_LATER(ah))
1406 udelay(2);
1407
1408 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1409 REG_WRITE(ah, AR_RC, 0);
1410
d03a66c1 1411 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1412
1413 if (!ath9k_hw_wait(ah,
1414 AR_RTC_STATUS,
1415 AR_RTC_STATUS_M,
0caa7b14
S		 1416 AR_RTC_STATUS_ON,
1417 AH_WAIT_TIMEOUT)) {
d2182b69 1418 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1419 return false;
f078f209
LR		 1420 }
1421
f1dc5600
S		 1422 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1423}
1424
cbe61d8a 1425static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1426{
7a9233ff 1427 bool ret = false;
2577c6e8 1428
9a658d2b
LR		 1429 if (AR_SREV_9300_20_OR_LATER(ah)) {
1430 REG_WRITE(ah, AR_WA, ah->WARegVal);
1431 udelay(10);
1432 }
1433
f1dc5600
S		 1434 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1435 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1436
ceb26a60
FF		 1437 if (!ah->reset_power_on)
1438 type = ATH9K_RESET_POWER_ON;
1439
f1dc5600
S		 1440 switch (type) {
1441 case ATH9K_RESET_POWER_ON:
7a9233ff 1442 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1443 if (ret)
ceb26a60 1444 ah->reset_power_on = true;
7a9233ff 1445 break;
f1dc5600
S		 1446 case ATH9K_RESET_WARM:
1447 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1448 ret = ath9k_hw_set_reset(ah, type);
1449 break;
f1dc5600 1450 default:
7a9233ff 1451 break;
f1dc5600 1452 }
7a9233ff 1453
7a9233ff 1454 return ret;
f078f209
LR		 1455}
1456
cbe61d8a 1457static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1458 struct ath9k_channel *chan)
f078f209 1459{
9c083af8
FF		 1460 int reset_type = ATH9K_RESET_WARM;
1461
1462 if (AR_SREV_9280(ah)) {
1463 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1464 reset_type = ATH9K_RESET_POWER_ON;
1465 else
1466 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1467 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1468 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1469 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1470
1471 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1472 return false;
f078f209 1473
9ecdef4b 1474 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1475 return false;
f078f209 1476
2660b81a 1477 ah->chip_fullsleep = false;
bfc441a4
FF		 1478
1479 if (AR_SREV_9330(ah))
1480 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1481 ath9k_hw_init_pll(ah, chan);
f1dc5600 1482 ath9k_hw_set_rfmode(ah, chan);
f078f209 1483
f1dc5600 1484 return true;
f078f209
LR		 1485}
1486
cbe61d8a 1487static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1488 struct ath9k_channel *chan)
f078f209 1489{
c46917bb 1490 struct ath_common *common = ath9k_hw_common(ah);
8fe65368 1491 u32 qnum;
0a3b7bac 1492 int r;
5f0c04ea
RM		 1493 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1494 bool band_switch, mode_diff;
1495 u8 ini_reloaded;
1496
1497 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1498 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1499 CHANNEL_5GHZ));
1500 mode_diff = (chan->chanmode != ah->curchan->chanmode);
f078f209
LR		 1501
1502 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1503 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1504 ath_dbg(common, QUEUE,
226afe68 1505 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1506 return false;
1507 }
1508 }
1509
8fe65368 1510 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1511 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1512 return false;
1513 }
1514
5f0c04ea
RM		 1515 if (edma && (band_switch || mode_diff)) {
1516 ath9k_hw_mark_phy_inactive(ah);
1517 udelay(5);
1518
1519 ath9k_hw_init_pll(ah, NULL);
1520
1521 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1522 ath_err(common, "Failed to do fast channel change\n");
1523 return false;
1524 }
1525 }
1526
8fe65368 1527 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1528
8fe65368 1529 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1530 if (r) {
3800276a 1531 ath_err(common, "Failed to set channel\n");
0a3b7bac 1532 return false;
f078f209 1533 }
dfdac8ac 1534 ath9k_hw_set_clockrate(ah);
64ea57d0 1535 ath9k_hw_apply_txpower(ah, chan, false);
8fe65368 1536 ath9k_hw_rfbus_done(ah);
f078f209 1537
f1dc5600
S		 1538 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1539 ath9k_hw_set_delta_slope(ah, chan);
1540
8fe65368 1541 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1542
5f0c04ea 1543 if (edma && (band_switch || mode_diff)) {
a126ff51 1544 ah->ah_flags |= AH_FASTCC;
5f0c04ea
RM		 1545 if (band_switch || ini_reloaded)
1546 ah->eep_ops->set_board_values(ah, chan);
1547
1548 ath9k_hw_init_bb(ah, chan);
1549
1550 if (band_switch || ini_reloaded)
1551 ath9k_hw_init_cal(ah, chan);
a126ff51 1552 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1553 }
1554
f1dc5600
S		 1555 return true;
1556}
1557
691680b8
FF		 1558static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1559{
1560 u32 gpio_mask = ah->gpio_mask;
1561 int i;
1562
1563 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1564 if (!(gpio_mask & 1))
1565 continue;
1566
1567 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1568 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1569 }
1570}
1571
01e18918
RM		 1572static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1573 int *hang_state, int *hang_pos)
1574{
1575 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1576 u32 chain_state, dcs_pos, i;
1577
1578 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1579 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1580 for (i = 0; i < 3; i++) {
1581 if (chain_state == dcu_chain_state[i]) {
1582 *hang_state = chain_state;
1583 *hang_pos = dcs_pos;
1584 return true;
1585 }
1586 }
1587 }
1588 return false;
1589}
1590
1591#define DCU_COMPLETE_STATE 1
1592#define DCU_COMPLETE_STATE_MASK 0x3
1593#define NUM_STATUS_READS 50
1594static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1595{
1596 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1597 u32 i, hang_pos, hang_state, num_state = 6;
1598
1599 comp_state = REG_READ(ah, AR_DMADBG_6);
1600
1601 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1602 ath_dbg(ath9k_hw_common(ah), RESET,
1603 "MAC Hang signature not found at DCU complete\n");
1604 return false;
1605 }
1606
1607 chain_state = REG_READ(ah, dcs_reg);
1608 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1609 goto hang_check_iter;
1610
1611 dcs_reg = AR_DMADBG_5;
1612 num_state = 4;
1613 chain_state = REG_READ(ah, dcs_reg);
1614 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1615 goto hang_check_iter;
1616
1617 ath_dbg(ath9k_hw_common(ah), RESET,
1618 "MAC Hang signature 1 not found\n");
1619 return false;
1620
1621hang_check_iter:
1622 ath_dbg(ath9k_hw_common(ah), RESET,
1623 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1624 chain_state, comp_state, hang_state, hang_pos);
1625
1626 for (i = 0; i < NUM_STATUS_READS; i++) {
1627 chain_state = REG_READ(ah, dcs_reg);
1628 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1629 comp_state = REG_READ(ah, AR_DMADBG_6);
1630
1631 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1632 DCU_COMPLETE_STATE) ||
1633 (chain_state != hang_state))
1634 return false;
1635 }
1636
1637 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1638
1639 return true;
1640}
1641
c9c99e5e 1642bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1643{
c9c99e5e
FF		 1644 int count = 50;
1645 u32 reg;
1646
01e18918
RM		 1647 if (AR_SREV_9300(ah))
1648 return !ath9k_hw_detect_mac_hang(ah);
1649
e17f83ea 1650 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1651 return true;
1652
1653 do {
1654 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1655
c9c99e5e
FF		 1656 if ((reg & 0x7E7FFFEF) == 0x00702400)
1657 continue;
1658
1659 switch (reg & 0x7E000B00) {
1660 case 0x1E000000:
1661 case 0x52000B00:
1662 case 0x18000B00:
1663 continue;
1664 default:
1665 return true;
1666 }
1667 } while (count-- > 0);
3b319aae 1668
c9c99e5e 1669 return false;
3b319aae 1670}
c9c99e5e 1671EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1672
15d2b585
SM		 1673static void ath9k_hw_init_mfp(struct ath_hw *ah)
1674{
1675 /* Setup MFP options for CCMP */
1676 if (AR_SREV_9280_20_OR_LATER(ah)) {
1677 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1678 * frames when constructing CCMP AAD. */
1679 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1680 0xc7ff);
1681 ah->sw_mgmt_crypto = false;
1682 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1683 /* Disable hardware crypto for management frames */
1684 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1685 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1686 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1687 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1688 ah->sw_mgmt_crypto = true;
1689 } else {
1690 ah->sw_mgmt_crypto = true;
1691 }
1692}
1693
1694static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1695 u32 macStaId1, u32 saveDefAntenna)
1696{
1697 struct ath_common *common = ath9k_hw_common(ah);
1698
1699 ENABLE_REGWRITE_BUFFER(ah);
1700
ecbbed32 1701 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585
SM		 1702 | AR_STA_ID1_RTS_USE_DEF
1703 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
ecbbed32
FF		 1704 | ah->sta_id1_defaults,
1705 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1706 ath_hw_setbssidmask(common);
1707 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1708 ath9k_hw_write_associd(ah);
1709 REG_WRITE(ah, AR_ISR, ~0);
1710 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1711
1712 REGWRITE_BUFFER_FLUSH(ah);
1713
1714 ath9k_hw_set_operating_mode(ah, ah->opmode);
1715}
1716
1717static void ath9k_hw_init_queues(struct ath_hw *ah)
1718{
1719 int i;
1720
1721 ENABLE_REGWRITE_BUFFER(ah);
1722
1723 for (i = 0; i < AR_NUM_DCU; i++)
1724 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1725
1726 REGWRITE_BUFFER_FLUSH(ah);
1727
1728 ah->intr_txqs = 0;
1729 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1730 ath9k_hw_resettxqueue(ah, i);
1731}
1732
1733/*
1734 * For big endian systems turn on swapping for descriptors
1735 */
1736static void ath9k_hw_init_desc(struct ath_hw *ah)
1737{
1738 struct ath_common *common = ath9k_hw_common(ah);
1739
1740 if (AR_SREV_9100(ah)) {
1741 u32 mask;
1742 mask = REG_READ(ah, AR_CFG);
1743 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1744 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1745 mask);
1746 } else {
1747 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1748 REG_WRITE(ah, AR_CFG, mask);
1749 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1750 REG_READ(ah, AR_CFG));
1751 }
1752 } else {
1753 if (common->bus_ops->ath_bus_type == ATH_USB) {
1754 /* Configure AR9271 target WLAN */
1755 if (AR_SREV_9271(ah))
1756 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1757 else
1758 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1759 }
1760#ifdef __BIG_ENDIAN
1761 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1762 AR_SREV_9550(ah))
1763 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1764 else
1765 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1766#endif
1767 }
1768}
1769
caed6579
SM		 1770/*
1771 * Fast channel change:
1772 * (Change synthesizer based on channel freq without resetting chip)
1773 *
1774 * Don't do FCC when
1775 * - Flag is not set
1776 * - Chip is just coming out of full sleep
1777 * - Channel to be set is same as current channel
1778 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1779 */
1780static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1781{
1782 struct ath_common *common = ath9k_hw_common(ah);
1783 int ret;
1784
1785 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1786 goto fail;
1787
1788 if (ah->chip_fullsleep)
1789 goto fail;
1790
1791 if (!ah->curchan)
1792 goto fail;
1793
1794 if (chan->channel == ah->curchan->channel)
1795 goto fail;
1796
feb7bc99
FF		 1797 if ((ah->curchan->channelFlags | chan->channelFlags) &
1798 (CHANNEL_HALF | CHANNEL_QUARTER))
1799 goto fail;
1800
caed6579
SM		 1801 if ((chan->channelFlags & CHANNEL_ALL) !=
1802 (ah->curchan->channelFlags & CHANNEL_ALL))
1803 goto fail;
1804
1805 if (!ath9k_hw_check_alive(ah))
1806 goto fail;
1807
1808 /*
1809 * For AR9462, make sure that calibration data for
1810 * re-using are present.
1811 */
8a90555f
SM		 1812 if (AR_SREV_9462(ah) && (ah->caldata &&
1813 (!ah->caldata->done_txiqcal_once ||
1814 !ah->caldata->done_txclcal_once ||
1815 !ah->caldata->rtt_done)))
caed6579
SM		 1816 goto fail;
1817
1818 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1819 ah->curchan->channel, chan->channel);
1820
1821 ret = ath9k_hw_channel_change(ah, chan);
1822 if (!ret)
1823 goto fail;
1824
5955b2b0 1825 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1826 ar9003_mci_2g5g_switch(ah, false);
caed6579 1827
88033318
RM		 1828 ath9k_hw_loadnf(ah, ah->curchan);
1829 ath9k_hw_start_nfcal(ah, true);
1830
caed6579
SM		 1831 if (AR_SREV_9271(ah))
1832 ar9002_hw_load_ani_reg(ah, chan);
1833
1834 return 0;
1835fail:
1836 return -EINVAL;
1837}
1838
cbe61d8a 1839int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1840 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1841{
1510718d 1842 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1843 u32 saveLedState;
f078f209
LR		 1844 u32 saveDefAntenna;
1845 u32 macStaId1;
46fe782c 1846 u64 tsf = 0;
15d2b585 1847 int r;
caed6579 1848 bool start_mci_reset = false;
63d32967
MSS		 1849 bool save_fullsleep = ah->chip_fullsleep;
1850
5955b2b0 1851 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1852 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1853 if (start_mci_reset)
1854 return 0;
63d32967
MSS		 1855 }
1856
9ecdef4b 1857 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1858 return -EIO;
f078f209 1859
caed6579
SM		 1860 if (ah->curchan && !ah->chip_fullsleep)
1861 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1862
20bd2a09 1863 ah->caldata = caldata;
fcb9a3de
SM		 1864 if (caldata && (chan->channel != caldata->channel ||
1865 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1866 /* Operating channel changed, reset channel calibration data */
1867 memset(caldata, 0, sizeof(*caldata));
1868 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be
FF		 1869 } else if (caldata) {
1870 caldata->paprd_packet_sent = false;
20bd2a09 1871 }
f23fba49 1872 ah->noise = ath9k_hw_getchan_noise(ah, chan);
20bd2a09 1873
caed6579
SM		 1874 if (fastcc) {
1875 r = ath9k_hw_do_fastcc(ah, chan);
1876 if (!r)
1877 return r;
f078f209
LR		 1878 }
1879
5955b2b0 1880 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1881 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1882
f078f209
LR		 1883 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1884 if (saveDefAntenna == 0)
1885 saveDefAntenna = 1;
1886
1887 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1888
46fe782c 1889 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1890 if (AR_SREV_9100(ah) ||
1891 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1892 tsf = ath9k_hw_gettsf64(ah);
1893
f078f209
LR		 1894 saveLedState = REG_READ(ah, AR_CFG_LED) &
1895 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1896 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1897
1898 ath9k_hw_mark_phy_inactive(ah);
1899
45ef6a0b
VT		 1900 ah->paprd_table_write_done = false;
1901
05020d23 1902 /* Only required on the first reset */
d7e7d229
LR		 1903 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1904 REG_WRITE(ah,
1905 AR9271_RESET_POWER_DOWN_CONTROL,
1906 AR9271_RADIO_RF_RST);
1907 udelay(50);
1908 }
1909
f078f209 1910 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1911 ath_err(common, "Chip reset failed\n");
ae8d2858 1912 return -EINVAL;
f078f209
LR		 1913 }
1914
05020d23 1915 /* Only required on the first reset */
d7e7d229
LR		 1916 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1917 ah->htc_reset_init = false;
1918 REG_WRITE(ah,
1919 AR9271_RESET_POWER_DOWN_CONTROL,
1920 AR9271_GATE_MAC_CTL);
1921 udelay(50);
1922 }
1923
46fe782c 1924 /* Restore TSF */
f860d526 1925 if (tsf)
46fe782c
S		 1926 ath9k_hw_settsf64(ah, tsf);
1927
7a37081e 1928 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1929 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1930
e9141f71
S		 1931 if (!AR_SREV_9300_20_OR_LATER(ah))
1932 ar9002_hw_enable_async_fifo(ah);
1933
25c56eec 1934 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1935 if (r)
1936 return r;
f078f209 1937
5955b2b0 1938 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1939 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1940
f860d526
FF		 1941 /*
1942 * Some AR91xx SoC devices frequently fail to accept TSF writes
1943 * right after the chip reset. When that happens, write a new
1944 * value after the initvals have been applied, with an offset
1945 * based on measured time difference
1946 */
1947 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1948 tsf += 1500;
1949 ath9k_hw_settsf64(ah, tsf);
1950 }
1951
15d2b585 1952 ath9k_hw_init_mfp(ah);
0ced0e17 1953
f078f209
LR		 1954 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1955 ath9k_hw_set_delta_slope(ah, chan);
1956
8fe65368 1957 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1958 ah->eep_ops->set_board_values(ah, chan);
a7765828 1959
15d2b585 1960 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1961
8fe65368 1962 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1963 if (r)
1964 return r;
f078f209 1965
dfdac8ac
FF		 1966 ath9k_hw_set_clockrate(ah);
1967
15d2b585 1968 ath9k_hw_init_queues(ah);
2660b81a 1969 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1970 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1971 ath9k_hw_init_qos(ah);
1972
2660b81a 1973 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1974 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1975
0005baf4 1976 ath9k_hw_init_global_settings(ah);
f078f209 1977
fe2b6afb
FF		 1978 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1979 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1980 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1981 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1982 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1983 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1984 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1985 }
1986
ca7a4deb 1987 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1988
1989 ath9k_hw_set_dma(ah);
1990
ed6ebd8b
RM		 1991 if (!ath9k_hw_mci_is_enabled(ah))
1992 REG_WRITE(ah, AR_OBS, 8);
f078f209 1993
0ce024cb 1994 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1995 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1996 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1997 }
1998
7f62a136
VT		 1999 if (ah->config.tx_intr_mitigation) {
2000 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2001 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2002 }
2003
f078f209
LR		 2004 ath9k_hw_init_bb(ah, chan);
2005
77a5a664 2006 if (caldata) {
5f0c04ea 2007 caldata->done_txiqcal_once = false;
77a5a664
RM		 2008 caldata->done_txclcal_once = false;
2009 }
ae8d2858 2010 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2011 return -EIO;
f078f209 2012
5955b2b0 2013 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 2014 return -EIO;
63d32967 2015
7d0d0df0 2016 ENABLE_REGWRITE_BUFFER(ah);
f078f209 2017
8fe65368 2018 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 2019 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2020
7d0d0df0 2021 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2022
15d2b585 2023 ath9k_hw_init_desc(ah);
f078f209 2024
dbccdd1d 2025 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 2026 ath9k_hw_btcoex_enable(ah);
2027
5955b2b0 2028 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 2029 ar9003_mci_check_bt(ah);
63d32967 2030
1fe860ed
RM		 2031 ath9k_hw_loadnf(ah, chan);
2032 ath9k_hw_start_nfcal(ah, true);
2033
51ac8cbb 2034 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 2035 ar9003_hw_bb_watchdog_config(ah);
51ac8cbb
RM		 2036 ar9003_hw_disable_phy_restart(ah);
2037 }
2038
691680b8
FF		 2039 ath9k_hw_apply_gpio_override(ah);
2040
362cd03f
SM		 2041 if (AR_SREV_9565(ah) && ah->shared_chain_lnadiv)
2042 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2043
ae8d2858 2044 return 0;
f078f209 2045}
7322fd19 2046EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2047
f1dc5600
S		 2048/******************************/
2049/* Power Management (Chipset) */
2050/******************************/
2051
42d5bc3f
LR		 2052/*
2053 * Notify Power Mgt is disabled in self-generated frames.
2054 * If requested, force chip to sleep.
2055 */
31604cf0 2056static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 2057{
f1dc5600 2058 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 2059
a4a2954f 2060 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 2061 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2062 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2063 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 2064 /* xxx Required for WLAN only case ? */
2065 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2066 udelay(100);
2067 }
2577c6e8 2068
31604cf0
SM		 2069 /*
2070 * Clear the RTC force wake bit to allow the
2071 * mac to go to sleep.
2072 */
2073 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2074
153dccd4 2075 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2076 udelay(100);
2577c6e8 2077
31604cf0
SM		 2078 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2079 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2080
31604cf0
SM		 2081 /* Shutdown chip. Active low */
2082 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2083 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2084 udelay(2);
f1dc5600 2085 }
9a658d2b
LR		 2086
2087 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2088 if (AR_SREV_9300_20_OR_LATER(ah))
2089 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2090}
2091
bbd79af5
LR		 2092/*
2093 * Notify Power Management is enabled in self-generating
2094 * frames. If request, set power mode of chip to
2095 * auto/normal. Duration in units of 128us (1/8 TU).
2096 */
31604cf0 2097static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2098{
31604cf0 2099 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2100
f1dc5600 2101 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2102
31604cf0
SM		 2103 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2104 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2105 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2106 AR_RTC_FORCE_WAKE_ON_INT);
2107 } else {
2577c6e8 2108
31604cf0
SM		 2109 /* When chip goes into network sleep, it could be waken
2110 * up by MCI_INT interrupt caused by BT's HW messages
2111 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2112 * rate (~100us). This will cause chip to leave and
2113 * re-enter network sleep mode frequently, which in
2114 * consequence will have WLAN MCI HW to generate lots of
2115 * SYS_WAKING and SYS_SLEEPING messages which will make
2116 * BT CPU to busy to process.
2117 */
153dccd4
RM		 2118 if (ath9k_hw_mci_is_enabled(ah))
2119 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2120 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2121 /*
2122 * Clear the RTC force wake bit to allow the
2123 * mac to go to sleep.
2124 */
153dccd4 2125 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2126
153dccd4 2127 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2128 udelay(30);
f078f209 2129 }
9a658d2b
LR		 2130
2131 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2132 if (AR_SREV_9300_20_OR_LATER(ah))
2133 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2134}
2135
31604cf0 2136static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2137{
f1dc5600
S		 2138 u32 val;
2139 int i;
f078f209 2140
9a658d2b
LR		 2141 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2142 if (AR_SREV_9300_20_OR_LATER(ah)) {
2143 REG_WRITE(ah, AR_WA, ah->WARegVal);
2144 udelay(10);
2145 }
2146
31604cf0
SM		 2147 if ((REG_READ(ah, AR_RTC_STATUS) &
2148 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2149 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2150 return false;
f1dc5600 2151 }
31604cf0
SM		 2152 if (!AR_SREV_9300_20_OR_LATER(ah))
2153 ath9k_hw_init_pll(ah, NULL);
2154 }
2155 if (AR_SREV_9100(ah))
2156 REG_SET_BIT(ah, AR_RTC_RESET,
2157 AR_RTC_RESET_EN);
2158
2159 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2160 AR_RTC_FORCE_WAKE_EN);
2161 udelay(50);
f078f209 2162
31604cf0
SM		 2163 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2164 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2165 if (val == AR_RTC_STATUS_ON)
2166 break;
2167 udelay(50);
f1dc5600
S		 2168 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2169 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2170 }
2171 if (i == 0) {
2172 ath_err(ath9k_hw_common(ah),
2173 "Failed to wakeup in %uus\n",
2174 POWER_UP_TIME / 20);
2175 return false;
f078f209
LR		 2176 }
2177
cdbe408d
RM		 2178 if (ath9k_hw_mci_is_enabled(ah))
2179 ar9003_mci_set_power_awake(ah);
2180
f1dc5600 2181 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2182
f1dc5600 2183 return true;
f078f209
LR		 2184}
2185
9ecdef4b 2186bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2187{
c46917bb 2188 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2189 int status = true;
f1dc5600
S		 2190 static const char *modes[] = {
2191 "AWAKE",
2192 "FULL-SLEEP",
2193 "NETWORK SLEEP",
2194 "UNDEFINED"
2195 };
f1dc5600 2196
cbdec975
GJ		 2197 if (ah->power_mode == mode)
2198 return status;
2199
d2182b69 2200 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2201 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2202
2203 switch (mode) {
2204 case ATH9K_PM_AWAKE:
31604cf0 2205 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2206 break;
2207 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2208 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2209 ar9003_mci_set_full_sleep(ah);
1010911e 2210
31604cf0 2211 ath9k_set_power_sleep(ah);
2660b81a 2212 ah->chip_fullsleep = true;
f1dc5600
S		 2213 break;
2214 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2215 ath9k_set_power_network_sleep(ah);
f1dc5600 2216 break;
f078f209 2217 default:
3800276a 2218 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2219 return false;
2220 }
2660b81a 2221 ah->power_mode = mode;
f1dc5600 2222
69f4aab1
LR		 2223 /*
2224 * XXX: If this warning never comes up after a while then
2225 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2226 * ath9k_hw_setpower() return type void.
2227 */
97dcec57
SM		 2228
2229 if (!(ah->ah_flags & AH_UNPLUGGED))
2230 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2231
f1dc5600 2232 return status;
f078f209 2233}
7322fd19 2234EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2235
f1dc5600
S		 2236/*******************/
2237/* Beacon Handling */
2238/*******************/
2239
cbe61d8a 2240void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2241{
f078f209
LR		 2242 int flags = 0;
2243
7d0d0df0
S		 2244 ENABLE_REGWRITE_BUFFER(ah);
2245
2660b81a 2246 switch (ah->opmode) {
d97809db 2247 case NL80211_IFTYPE_ADHOC:
9cb5412b 2248 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 2249 REG_SET_BIT(ah, AR_TXCFG,
2250 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
dd347f2f
FF		 2251 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2252 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
f078f209 2253 flags |= AR_NDP_TIMER_EN;
d97809db 2254 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2255 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2256 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2257 TU_TO_USEC(ah->config.dma_beacon_response_time));
2258 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2259 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2260 flags |=
2261 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2262 break;
d97809db 2263 default:
d2182b69
JP		 2264 ath_dbg(ath9k_hw_common(ah), BEACON,
2265 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2266 return;
2267 break;
f078f209
LR		 2268 }
2269
dd347f2f
FF		 2270 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2271 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2272 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2273 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
f078f209 2274
7d0d0df0 2275 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2276
f078f209
LR		 2277 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2278}
7322fd19 2279EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2280
cbe61d8a 2281void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2282 const struct ath9k_beacon_state *bs)
f078f209
LR		 2283{
2284 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2285 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2286 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2287
7d0d0df0
S		 2288 ENABLE_REGWRITE_BUFFER(ah);
2289
f078f209
LR		 2290 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2291
2292 REG_WRITE(ah, AR_BEACON_PERIOD,
f29f5c08 2293 TU_TO_USEC(bs->bs_intval));
f078f209 2294 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
f29f5c08 2295 TU_TO_USEC(bs->bs_intval));
f078f209 2296
7d0d0df0 2297 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2298
f078f209
LR		 2299 REG_RMW_FIELD(ah, AR_RSSI_THR,
2300 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2301
f29f5c08 2302 beaconintval = bs->bs_intval;
f078f209
LR		 2303
2304 if (bs->bs_sleepduration > beaconintval)
2305 beaconintval = bs->bs_sleepduration;
2306
2307 dtimperiod = bs->bs_dtimperiod;
2308 if (bs->bs_sleepduration > dtimperiod)
2309 dtimperiod = bs->bs_sleepduration;
2310
2311 if (beaconintval == dtimperiod)
2312 nextTbtt = bs->bs_nextdtim;
2313 else
2314 nextTbtt = bs->bs_nexttbtt;
2315
d2182b69
JP		 2316 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2317 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2318 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2319 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2320
7d0d0df0
S		 2321 ENABLE_REGWRITE_BUFFER(ah);
2322
f1dc5600
S		 2323 REG_WRITE(ah, AR_NEXT_DTIM,
2324 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2325 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 2326
f1dc5600
S		 2327 REG_WRITE(ah, AR_SLEEP1,
2328 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2329 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2330
f1dc5600
S		 2331 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2332 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2333 else
2334 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2335
f1dc5600
S		 2336 REG_WRITE(ah, AR_SLEEP2,
2337 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2338
f1dc5600
S		 2339 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2340 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2341
7d0d0df0 2342 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2343
f1dc5600
S		 2344 REG_SET_BIT(ah, AR_TIMER_MODE,
2345 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2346 AR_DTIM_TIMER_EN);
f078f209 2347
4af9cf4f
S		 2348 /* TSF Out of Range Threshold */
2349 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2350}
7322fd19 2351EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2352
f1dc5600
S		 2353/*******************/
2354/* HW Capabilities */
2355/*******************/
2356
6054069a
FF		 2357static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2358{
2359 eeprom_chainmask &= chip_chainmask;
2360 if (eeprom_chainmask)
2361 return eeprom_chainmask;
2362 else
2363 return chip_chainmask;
2364}
2365
9a66af33
ZK		 2366/**
2367 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2368 * @ah: the atheros hardware data structure
2369 *
2370 * We enable DFS support upstream on chipsets which have passed a series
2371 * of tests. The testing requirements are going to be documented. Desired
2372 * test requirements are documented at:
2373 *
2374 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2375 *
2376 * Once a new chipset gets properly tested an individual commit can be used
2377 * to document the testing for DFS for that chipset.
2378 */
2379static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2380{
2381
2382 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2383 /* for temporary testing DFS with 9280 */
2384 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2385 /* AR9580 will likely be our first target to get testing on */
2386 case AR_SREV_VERSION_9580:
73e4937d 2387 return true;
9a66af33
ZK		 2388 default:
2389 return false;
2390 }
2391}
2392
a9a29ce6 2393int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2394{
2660b81a 2395 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2396 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2397 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2398 unsigned int chip_chainmask;
608b88cb 2399
0ff2b5c0 2400 u16 eeval;
47c80de6 2401 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2402
f74df6fb 2403 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2404 regulatory->current_rd = eeval;
f078f209 2405
2660b81a 2406 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2407 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2408 if (regulatory->current_rd == 0x64 ||
2409 regulatory->current_rd == 0x65)
2410 regulatory->current_rd += 5;
2411 else if (regulatory->current_rd == 0x41)
2412 regulatory->current_rd = 0x43;
d2182b69
JP		 2413 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2414 regulatory->current_rd);
f1dc5600 2415 }
f078f209 2416
f74df6fb 2417 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2418 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2419 ath_err(common,
2420 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2421 return -EINVAL;
2422 }
2423
d4659912
FF		 2424 if (eeval & AR5416_OPFLAGS_11A)
2425 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2426
d4659912
FF		 2427 if (eeval & AR5416_OPFLAGS_11G)
2428 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2429
e41db61d
SM		 2430 if (AR_SREV_9485(ah) ||
2431 AR_SREV_9285(ah) ||
2432 AR_SREV_9330(ah) ||
2433 AR_SREV_9565(ah))
6054069a 2434 chip_chainmask = 1;
ba5736a5
MSS		 2435 else if (AR_SREV_9462(ah))
2436 chip_chainmask = 3;
6054069a
FF		 2437 else if (!AR_SREV_9280_20_OR_LATER(ah))
2438 chip_chainmask = 7;
2439 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2440 chip_chainmask = 3;
2441 else
2442 chip_chainmask = 7;
2443
f74df6fb 2444 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2445 /*
2446 * For AR9271 we will temporarilly uses the rx chainmax as read from
2447 * the EEPROM.
2448 */
8147f5de 2449 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2450 !(eeval & AR5416_OPFLAGS_11A) &&
2451 !(AR_SREV_9271(ah)))
2452 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2453 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2454 else if (AR_SREV_9100(ah))
2455 pCap->rx_chainmask = 0x7;
8147f5de 2456 else
d7e7d229 2457 /* Use rx_chainmask from EEPROM. */
8147f5de 2458 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2459
6054069a
FF		 2460 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2461 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2462 ah->txchainmask = pCap->tx_chainmask;
2463 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2464
7a37081e 2465 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2466
02d2ebb2
FF		 2467 /* enable key search for every frame in an aggregate */
2468 if (AR_SREV_9300_20_OR_LATER(ah))
2469 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2470
ce2220d1
BR		 2471 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2472
0db156e9 2473 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2474 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2475 else
2476 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2477
5b5fa355
S		 2478 if (AR_SREV_9271(ah))
2479 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2480 else if (AR_DEVID_7010(ah))
2481 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2482 else if (AR_SREV_9300_20_OR_LATER(ah))
2483 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2484 else if (AR_SREV_9287_11_OR_LATER(ah))
2485 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2486 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2487 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2488 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2489 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2490 else
2491 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2492
1b2538b2 2493 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2494 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2495 else
f1dc5600 2496 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2497
e97275cb 2498#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2499 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2500 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2501 ah->rfkill_gpio =
2502 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2503 ah->rfkill_polarity =
2504 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2505
2506 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2507 }
f1dc5600 2508#endif
d5d1154f 2509 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2510 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2511 else
2512 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2513
e7594072 2514 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2515 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2516 else
2517 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2518
ceb26445 2519 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2520 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
a4a2954f 2521 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2522 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2523
ceb26445
VT		 2524 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2525 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2526 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2527 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2528 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2529 } else {
2530 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2531 if (AR_SREV_9280_20(ah))
6b42e8d0 2532 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2533 }
1adf02ff 2534
6c84ce08
VT		 2535 if (AR_SREV_9300_20_OR_LATER(ah))
2536 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2537
6ee63f55
SB		 2538 if (AR_SREV_9300_20_OR_LATER(ah))
2539 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2540
a42acef0 2541 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2542 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2543
754dc536
VT		 2544 if (AR_SREV_9285(ah))
2545 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2546 ant_div_ctl1 =
2547 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2548 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2549 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2550 }
ea066d5a
MSS		 2551 if (AR_SREV_9300_20_OR_LATER(ah)) {
2552 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2553 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2554 }
2555
2556
06236e53 2557 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a
MSS		 2558 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2559 /*
2560 * enable the diversity-combining algorithm only when
2561 * both enable_lna_div and enable_fast_div are set
2562 * Table for Diversity
2563 * ant_div_alt_lnaconf bit 0-1
2564 * ant_div_main_lnaconf bit 2-3
2565 * ant_div_alt_gaintb bit 4
2566 * ant_div_main_gaintb bit 5
2567 * enable_ant_div_lnadiv bit 6
2568 * enable_ant_fast_div bit 7
2569 */
2570 if ((ant_div_ctl1 >> 0x6) == 0x3)
2571 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2572 }
754dc536 2573
9a66af33
ZK		 2574 if (ath9k_hw_dfs_tested(ah))
2575 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2576
47c80de6
VT		 2577 tx_chainmask = pCap->tx_chainmask;
2578 rx_chainmask = pCap->rx_chainmask;
2579 while (tx_chainmask || rx_chainmask) {
2580 if (tx_chainmask & BIT(0))
2581 pCap->max_txchains++;
2582 if (rx_chainmask & BIT(0))
2583 pCap->max_rxchains++;
2584
2585 tx_chainmask >>= 1;
2586 rx_chainmask >>= 1;
2587 }
2588
a4a2954f 2589 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2590 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2591 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2592
2593 if (AR_SREV_9462_20(ah))
2594 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2595 }
2596
d687809b
MSS		 2597 if (AR_SREV_9280_20_OR_LATER(ah)) {
2598 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE |
2599 ATH9K_HW_WOW_PATTERN_MATCH_EXACT;
2600
2601 if (AR_SREV_9280(ah))
2602 pCap->hw_caps |= ATH9K_HW_WOW_PATTERN_MATCH_DWORD;
2603 }
2604
0f21ee8d
SM		 2605 if (AR_SREV_9300_20_OR_LATER(ah) &&
2606 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2607 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2608
a9a29ce6 2609 return 0;
f078f209
LR		 2610}
2611
f1dc5600
S		 2612/****************************/
2613/* GPIO / RFKILL / Antennae */
2614/****************************/
f078f209 2615
cbe61d8a 2616static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2617 u32 gpio, u32 type)
2618{
2619 int addr;
2620 u32 gpio_shift, tmp;
f078f209 2621
f1dc5600
S		 2622 if (gpio > 11)
2623 addr = AR_GPIO_OUTPUT_MUX3;
2624 else if (gpio > 5)
2625 addr = AR_GPIO_OUTPUT_MUX2;
2626 else
2627 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2628
f1dc5600 2629 gpio_shift = (gpio % 6) * 5;
f078f209 2630
f1dc5600
S		 2631 if (AR_SREV_9280_20_OR_LATER(ah)
2632 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2633 REG_RMW(ah, addr, (type << gpio_shift),
2634 (0x1f << gpio_shift));
f078f209 2635 } else {
f1dc5600
S		 2636 tmp = REG_READ(ah, addr);
2637 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2638 tmp &= ~(0x1f << gpio_shift);
2639 tmp |= (type << gpio_shift);
2640 REG_WRITE(ah, addr, tmp);
f078f209 2641 }
f078f209
LR		 2642}
2643
cbe61d8a 2644void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2645{
f1dc5600 2646 u32 gpio_shift;
f078f209 2647
9680e8a3 2648 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2649
88c1f4f6
S		 2650 if (AR_DEVID_7010(ah)) {
2651 gpio_shift = gpio;
2652 REG_RMW(ah, AR7010_GPIO_OE,
2653 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2654 (AR7010_GPIO_OE_MASK << gpio_shift));
2655 return;
2656 }
f078f209 2657
88c1f4f6 2658 gpio_shift = gpio << 1;
f1dc5600
S		 2659 REG_RMW(ah,
2660 AR_GPIO_OE_OUT,
2661 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2662 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2663}
7322fd19 2664EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2665
cbe61d8a 2666u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2667{
cb33c412
SB		 2668#define MS_REG_READ(x, y) \
2669 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2670
2660b81a 2671 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2672 return 0xffffffff;
f078f209 2673
88c1f4f6
S		 2674 if (AR_DEVID_7010(ah)) {
2675 u32 val;
2676 val = REG_READ(ah, AR7010_GPIO_IN);
2677 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2678 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2679 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2680 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2681 else if (AR_SREV_9271(ah))
5b5fa355 2682 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2683 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2684 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2685 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2686 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2687 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2688 return MS_REG_READ(AR928X, gpio) != 0;
2689 else
2690 return MS_REG_READ(AR, gpio) != 0;
f078f209 2691}
7322fd19 2692EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2693
cbe61d8a 2694void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2695 u32 ah_signal_type)
f078f209 2696{
f1dc5600 2697 u32 gpio_shift;
f078f209 2698
88c1f4f6
S		 2699 if (AR_DEVID_7010(ah)) {
2700 gpio_shift = gpio;
2701 REG_RMW(ah, AR7010_GPIO_OE,
2702 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2703 (AR7010_GPIO_OE_MASK << gpio_shift));
2704 return;
2705 }
f078f209 2706
88c1f4f6 2707 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2708 gpio_shift = 2 * gpio;
f1dc5600
S		 2709 REG_RMW(ah,
2710 AR_GPIO_OE_OUT,
2711 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2712 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2713}
7322fd19 2714EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2715
cbe61d8a 2716void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2717{
88c1f4f6
S		 2718 if (AR_DEVID_7010(ah)) {
2719 val = val ? 0 : 1;
2720 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2721 AR_GPIO_BIT(gpio));
2722 return;
2723 }
2724
5b5fa355
S		 2725 if (AR_SREV_9271(ah))
2726 val = ~val;
2727
f1dc5600
S		 2728 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2729 AR_GPIO_BIT(gpio));
f078f209 2730}
7322fd19 2731EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2732
cbe61d8a 2733void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2734{
f1dc5600 2735 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2736}
7322fd19 2737EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2738
f1dc5600
S		 2739/*********************/
2740/* General Operation */
2741/*********************/
2742
cbe61d8a 2743u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2744{
f1dc5600
S		 2745 u32 bits = REG_READ(ah, AR_RX_FILTER);
2746 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2747
f1dc5600
S		 2748 if (phybits & AR_PHY_ERR_RADAR)
2749 bits |= ATH9K_RX_FILTER_PHYRADAR;
2750 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2751 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2752
f1dc5600 2753 return bits;
f078f209 2754}
7322fd19 2755EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2756
cbe61d8a 2757void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2758{
f1dc5600 2759 u32 phybits;
f078f209 2760
7d0d0df0
S		 2761 ENABLE_REGWRITE_BUFFER(ah);
2762
a4a2954f 2763 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2577c6e8
SB		 2764 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2765
7ea310be
S		 2766 REG_WRITE(ah, AR_RX_FILTER, bits);
2767
f1dc5600
S		 2768 phybits = 0;
2769 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2770 phybits |= AR_PHY_ERR_RADAR;
2771 if (bits & ATH9K_RX_FILTER_PHYERR)
2772 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2773 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2774
f1dc5600 2775 if (phybits)
ca7a4deb 2776 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2777 else
ca7a4deb 2778 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2779
2780 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2781}
7322fd19 2782EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2783
cbe61d8a 2784bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2785{
99922a45
RM		 2786 if (ath9k_hw_mci_is_enabled(ah))
2787 ar9003_mci_bt_gain_ctrl(ah);
2788
63a75b91
SB		 2789 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2790 return false;
2791
2792 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2793 ah->htc_reset_init = true;
63a75b91 2794 return true;
f1dc5600 2795}
7322fd19 2796EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2797
cbe61d8a 2798bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2799{
9ecdef4b 2800 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2801 return false;
f078f209 2802
63a75b91
SB		 2803 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2804 return false;
2805
2806 ath9k_hw_init_pll(ah, NULL);
2807 return true;
f078f209 2808}
7322fd19 2809EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2810
ca2c68cc
FF		 2811static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2812{
2813 enum eeprom_param gain_param;
2814
2815 if (IS_CHAN_2GHZ(chan))
2816 gain_param = EEP_ANTENNA_GAIN_2G;
2817 else
2818 gain_param = EEP_ANTENNA_GAIN_5G;
2819
2820 return ah->eep_ops->get_eeprom(ah, gain_param);
2821}
2822
64ea57d0
GJ		 2823void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2824 bool test)
ca2c68cc
FF		 2825{
2826 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2827 struct ieee80211_channel *channel;
2828 int chan_pwr, new_pwr, max_gain;
2829 int ant_gain, ant_reduction = 0;
2830
2831 if (!chan)
2832 return;
2833
2834 channel = chan->chan;
2835 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2836 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2837 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2838
2839 ant_gain = get_antenna_gain(ah, chan);
2840 if (ant_gain > max_gain)
2841 ant_reduction = ant_gain - max_gain;
2842
2843 ah->eep_ops->set_txpower(ah, chan,
2844 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2845 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2846}
2847
de40f316 2848void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2849{
ca2c68cc 2850 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2851 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2852 struct ieee80211_channel *channel = chan->chan;
9c204b46 2853
48ef5c42 2854 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2855 if (test)
ca2c68cc 2856 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2857
64ea57d0 2858 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2859
ca2c68cc
FF		 2860 if (test)
2861 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2862}
7322fd19 2863EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2864
cbe61d8a 2865void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2866{
2660b81a 2867 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2868}
7322fd19 2869EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2870
cbe61d8a 2871void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2872{
f1dc5600
S		 2873 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2874 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2875}
7322fd19 2876EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2877
f2b2143e 2878void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2879{
1510718d
LR		 2880 struct ath_common *common = ath9k_hw_common(ah);
2881
2882 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2883 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2884 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2885}
7322fd19 2886EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2887
1c0fc65e
BP		 2888#define ATH9K_MAX_TSF_READ 10
2889
cbe61d8a 2890u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2891{
1c0fc65e
BP		 2892 u32 tsf_lower, tsf_upper1, tsf_upper2;
2893 int i;
2894
2895 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2896 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2897 tsf_lower = REG_READ(ah, AR_TSF_L32);
2898 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2899 if (tsf_upper2 == tsf_upper1)
2900 break;
2901 tsf_upper1 = tsf_upper2;
2902 }
f078f209 2903
1c0fc65e 2904 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2905
1c0fc65e 2906 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2907}
7322fd19 2908EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2909
cbe61d8a 2910void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2911{
27abe060 2912 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2913 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2914}
7322fd19 2915EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2916
cbe61d8a 2917void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2918{
f9b604f6
GJ		 2919 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2920 AH_TSF_WRITE_TIMEOUT))
d2182b69 2921 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2922 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2923
f1dc5600
S		 2924 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2925}
7322fd19 2926EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2927
60ca9f87 2928void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 2929{
60ca9f87 2930 if (set)
2660b81a 2931 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2932 else
2660b81a 2933 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2934}
7322fd19 2935EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2936
25c56eec 2937void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2938{
25c56eec 2939 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2940 u32 macmode;
2941
25c56eec 2942 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2943 macmode = AR_2040_JOINED_RX_CLEAR;
2944 else
2945 macmode = 0;
f078f209 2946
f1dc5600 2947 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2948}
ff155a45
VT		 2949
2950/* HW Generic timers configuration */
2951
2952static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2953{
2954 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2955 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2956 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2957 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2958 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2959 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2960 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2961 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2962 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2963 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2964 AR_NDP2_TIMER_MODE, 0x0002},
2965 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2966 AR_NDP2_TIMER_MODE, 0x0004},
2967 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2968 AR_NDP2_TIMER_MODE, 0x0008},
2969 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2970 AR_NDP2_TIMER_MODE, 0x0010},
2971 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2972 AR_NDP2_TIMER_MODE, 0x0020},
2973 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2974 AR_NDP2_TIMER_MODE, 0x0040},
2975 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2976 AR_NDP2_TIMER_MODE, 0x0080}
2977};
2978
2979/* HW generic timer primitives */
2980
2981/* compute and clear index of rightmost 1 */
2982static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2983{
2984 u32 b;
2985
2986 b = *mask;
2987 b &= (0-b);
2988 *mask &= ~b;
2989 b *= debruijn32;
2990 b >>= 27;
2991
2992 return timer_table->gen_timer_index[b];
2993}
2994
dd347f2f 2995u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2996{
2997 return REG_READ(ah, AR_TSF_L32);
2998}
dd347f2f 2999EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 3000
3001struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3002 void (*trigger)(void *),
3003 void (*overflow)(void *),
3004 void *arg,
3005 u8 timer_index)
3006{
3007 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3008 struct ath_gen_timer *timer;
3009
3010 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 3011 if (timer == NULL)
ff155a45 3012 return NULL;
ff155a45
VT		 3013
3014 /* allocate a hardware generic timer slot */
3015 timer_table->timers[timer_index] = timer;
3016 timer->index = timer_index;
3017 timer->trigger = trigger;
3018 timer->overflow = overflow;
3019 timer->arg = arg;
3020
3021 return timer;
3022}
7322fd19 3023EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3024
cd9bf689
LR		 3025void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3026 struct ath_gen_timer *timer,
788f6875 3027 u32 trig_timeout,
cd9bf689 3028 u32 timer_period)
ff155a45
VT		 3029{
3030 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
788f6875 3031 u32 tsf, timer_next;
ff155a45
VT		 3032
3033 BUG_ON(!timer_period);
3034
3035 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3036
3037 tsf = ath9k_hw_gettsf32(ah);
3038
788f6875
VT		 3039 timer_next = tsf + trig_timeout;
3040
d2182b69 3041 ath_dbg(ath9k_hw_common(ah), HWTIMER,
226afe68
JP		 3042 "current tsf %x period %x timer_next %x\n",
3043 tsf, timer_period, timer_next);
ff155a45 3044
ff155a45
VT		 3045 /*
3046 * Program generic timer registers
3047 */
3048 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3049 timer_next);
3050 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3051 timer_period);
3052 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3053 gen_tmr_configuration[timer->index].mode_mask);
3054
a4a2954f 3055 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 3056 /*
423e38e8 3057 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3058 * to use. But we still follow the old rule, 0 - 7 use tsf and
3059 * 8 - 15 use tsf2.
3060 */
3061 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3062 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3063 (1 << timer->index));
3064 else
3065 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3066 (1 << timer->index));
3067 }
3068
ff155a45
VT		 3069 /* Enable both trigger and thresh interrupt masks */
3070 REG_SET_BIT(ah, AR_IMR_S5,
3071 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3072 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 3073}
7322fd19 3074EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3075
cd9bf689 3076void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3077{
3078 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3079
3080 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3081 (timer->index >= ATH_MAX_GEN_TIMER)) {
3082 return;
3083 }
3084
3085 /* Clear generic timer enable bits. */
3086 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3087 gen_tmr_configuration[timer->index].mode_mask);
3088
b7f59766
SM		 3089 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3090 /*
3091 * Need to switch back to TSF if it was using TSF2.
3092 */
3093 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3094 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3095 (1 << timer->index));
3096 }
3097 }
3098
ff155a45
VT		 3099 /* Disable both trigger and thresh interrupt masks */
3100 REG_CLR_BIT(ah, AR_IMR_S5,
3101 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3102 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3103
3104 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3105}
7322fd19 3106EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3107
3108void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3109{
3110 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3111
3112 /* free the hardware generic timer slot */
3113 timer_table->timers[timer->index] = NULL;
3114 kfree(timer);
3115}
7322fd19 3116EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3117
3118/*
3119 * Generic Timer Interrupts handling
3120 */
3121void ath_gen_timer_isr(struct ath_hw *ah)
3122{
3123 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3124 struct ath_gen_timer *timer;
c46917bb 3125 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3126 u32 trigger_mask, thresh_mask, index;
3127
3128 /* get hardware generic timer interrupt status */
3129 trigger_mask = ah->intr_gen_timer_trigger;
3130 thresh_mask = ah->intr_gen_timer_thresh;
3131 trigger_mask &= timer_table->timer_mask.val;
3132 thresh_mask &= timer_table->timer_mask.val;
3133
3134 trigger_mask &= ~thresh_mask;
3135
3136 while (thresh_mask) {
3137 index = rightmost_index(timer_table, &thresh_mask);
3138 timer = timer_table->timers[index];
3139 BUG_ON(!timer);
d2182b69
JP		 3140 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3141 index);
ff155a45
VT		 3142 timer->overflow(timer->arg);
3143 }
3144
3145 while (trigger_mask) {
3146 index = rightmost_index(timer_table, &trigger_mask);
3147 timer = timer_table->timers[index];
3148 BUG_ON(!timer);
d2182b69 3149 ath_dbg(common, HWTIMER,
226afe68 3150 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3151 timer->trigger(timer->arg);
3152 }
3153}
7322fd19 3154EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3155
05020d23
S		 3156/********/
3157/* HTC */
3158/********/
3159
2da4f01a
LR		 3160static struct {
3161 u32 version;
3162 const char * name;
3163} ath_mac_bb_names[] = {
3164 /* Devices with external radios */
3165 { AR_SREV_VERSION_5416_PCI, "5416" },
3166 { AR_SREV_VERSION_5416_PCIE, "5418" },
3167 { AR_SREV_VERSION_9100, "9100" },
3168 { AR_SREV_VERSION_9160, "9160" },
3169 /* Single-chip solutions */
3170 { AR_SREV_VERSION_9280, "9280" },
3171 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3172 { AR_SREV_VERSION_9287, "9287" },
3173 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3174 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3175 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3176 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3177 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3178 { AR_SREV_VERSION_9462, "9462" },
485124cb 3179 { AR_SREV_VERSION_9550, "9550" },
77fac465 3180 { AR_SREV_VERSION_9565, "9565" },
2da4f01a
LR		 3181};
3182
3183/* For devices with external radios */
3184static struct {
3185 u16 version;
3186 const char * name;
3187} ath_rf_names[] = {
3188 { 0, "5133" },
3189 { AR_RAD5133_SREV_MAJOR, "5133" },
3190 { AR_RAD5122_SREV_MAJOR, "5122" },
3191 { AR_RAD2133_SREV_MAJOR, "2133" },
3192 { AR_RAD2122_SREV_MAJOR, "2122" }
3193};
3194
3195/*
3196 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3197 */
f934c4d9 3198static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3199{
3200 int i;
3201
3202 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3203 if (ath_mac_bb_names[i].version == mac_bb_version) {
3204 return ath_mac_bb_names[i].name;
3205 }
3206 }
3207
3208 return "????";
3209}
2da4f01a
LR		 3210
3211/*
3212 * Return the RF name. "????" is returned if the RF is unknown.
3213 * Used for devices with external radios.
3214 */
f934c4d9 3215static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3216{
3217 int i;
3218
3219 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3220 if (ath_rf_names[i].version == rf_version) {
3221 return ath_rf_names[i].name;
3222 }
3223 }
3224
3225 return "????";
3226}
f934c4d9
LR		 3227
3228void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3229{
3230 int used;
3231
3232 /* chipsets >= AR9280 are single-chip */
7a37081e 3233 if (AR_SREV_9280_20_OR_LATER(ah)) {
f934c4d9
LR		 3234 used = snprintf(hw_name, len,
3235 "Atheros AR%s Rev:%x",
3236 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3237 ah->hw_version.macRev);
3238 }
3239 else {
3240 used = snprintf(hw_name, len,
3241 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3242 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3243 ah->hw_version.macRev,
3244 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3245 AR_RADIO_SREV_MAJOR)),
3246 ah->hw_version.phyRev);
3247 }
3248
3249 hw_name[used] = '\0';
3250}
3251EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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