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mac80211: Defer tranmission of mesh path errors
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
f078f209
LR		 19#include <asm/unaligned.h>
20
af03abec 21#include "hw.h"
d70357d5 22#include "hw-ops.h"
cfe8cba9 23#include "rc.h"
b622a720 24#include "ar9003_mac.h"
f078f209 25
cbe61d8a 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 27
7322fd19
LR		 28MODULE_AUTHOR("Atheros Communications");
29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31MODULE_LICENSE("Dual BSD/GPL");
32
33static int __init ath9k_init(void)
34{
35 return 0;
36}
37module_init(ath9k_init);
38
39static void __exit ath9k_exit(void)
40{
41 return;
42}
43module_exit(ath9k_exit);
44
d70357d5
LR		 45/* Private hardware callbacks */
46
47static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48{
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50}
51
52static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55}
56
64773964
LR		 57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59{
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61}
62
991312d8
LR		 63static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64{
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69}
70
e36b27af
LR		 71static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72{
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78}
79
f1dc5600
S		 80/********************/
81/* Helper Functions */
82/********************/
f078f209 83
dfdac8ac 84static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 85{
b002a4a9 86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
dfdac8ac
FF		 87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
cbe61d8a 89
087b6ff6
FF		 90 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
91 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
92 clockrate = 117;
93 else if (!ah->curchan) /* should really check for CCK instead */
dfdac8ac
FF		 94 clockrate = ATH9K_CLOCK_RATE_CCK;
95 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
96 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
97 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
98 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 99 else
dfdac8ac
FF		 100 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
101
102 if (conf_is_ht40(conf))
103 clockrate *= 2;
104
906c7205
FF		 105 if (ah->curchan) {
106 if (IS_CHAN_HALF_RATE(ah->curchan))
107 clockrate /= 2;
108 if (IS_CHAN_QUARTER_RATE(ah->curchan))
109 clockrate /= 4;
110 }
111
dfdac8ac 112 common->clockrate = clockrate;
f1dc5600
S		 113}
114
cbe61d8a 115static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 116{
dfdac8ac 117 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 118
dfdac8ac 119 return usecs * common->clockrate;
f1dc5600 120}
f078f209 121
0caa7b14 122bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 123{
124 int i;
125
0caa7b14
S		 126 BUG_ON(timeout < AH_TIME_QUANTUM);
127
128 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 129 if ((REG_READ(ah, reg) & mask) == val)
130 return true;
131
132 udelay(AH_TIME_QUANTUM);
133 }
04bd4638 134
226afe68
JP		 135 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
136 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
137 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 138
f1dc5600 139 return false;
f078f209 140}
7322fd19 141EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 142
a9b6b256
FF		 143void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
144 int column, unsigned int *writecnt)
145{
146 int r;
147
148 ENABLE_REGWRITE_BUFFER(ah);
149 for (r = 0; r < array->ia_rows; r++) {
150 REG_WRITE(ah, INI_RA(array, r, 0),
151 INI_RA(array, r, column));
152 DO_DELAY(*writecnt);
153 }
154 REGWRITE_BUFFER_FLUSH(ah);
155}
156
f078f209
LR		 157u32 ath9k_hw_reverse_bits(u32 val, u32 n)
158{
159 u32 retval;
160 int i;
161
162 for (i = 0, retval = 0; i < n; i++) {
163 retval = (retval << 1) | (val & 1);
164 val >>= 1;
165 }
166 return retval;
167}
168
cbe61d8a 169u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 170 u8 phy, int kbps,
f1dc5600
S		 171 u32 frameLen, u16 rateix,
172 bool shortPreamble)
f078f209 173{
f1dc5600 174 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 175
f1dc5600
S		 176 if (kbps == 0)
177 return 0;
f078f209 178
545750d3 179 switch (phy) {
46d14a58 180 case WLAN_RC_PHY_CCK:
f1dc5600 181 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 182 if (shortPreamble)
f1dc5600
S		 183 phyTime >>= 1;
184 numBits = frameLen << 3;
185 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
186 break;
46d14a58 187 case WLAN_RC_PHY_OFDM:
2660b81a 188 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 189 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
190 numBits = OFDM_PLCP_BITS + (frameLen << 3);
191 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
192 txTime = OFDM_SIFS_TIME_QUARTER
193 + OFDM_PREAMBLE_TIME_QUARTER
194 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 195 } else if (ah->curchan &&
196 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 197 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
198 numBits = OFDM_PLCP_BITS + (frameLen << 3);
199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
200 txTime = OFDM_SIFS_TIME_HALF +
201 OFDM_PREAMBLE_TIME_HALF
202 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
203 } else {
204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
205 numBits = OFDM_PLCP_BITS + (frameLen << 3);
206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
208 + (numSymbols * OFDM_SYMBOL_TIME);
209 }
210 break;
211 default:
3800276a
JP		 212 ath_err(ath9k_hw_common(ah),
213 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 214 txTime = 0;
215 break;
216 }
f078f209 217
f1dc5600
S		 218 return txTime;
219}
7322fd19 220EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 221
cbe61d8a 222void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 223 struct ath9k_channel *chan,
224 struct chan_centers *centers)
f078f209 225{
f1dc5600 226 int8_t extoff;
f078f209 227
f1dc5600
S		 228 if (!IS_CHAN_HT40(chan)) {
229 centers->ctl_center = centers->ext_center =
230 centers->synth_center = chan->channel;
231 return;
f078f209 232 }
f078f209 233
f1dc5600
S		 234 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
235 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
236 centers->synth_center =
237 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
238 extoff = 1;
239 } else {
240 centers->synth_center =
241 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
242 extoff = -1;
243 }
f078f209 244
f1dc5600
S		 245 centers->ctl_center =
246 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 247 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 248 centers->ext_center =
6420014c 249 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 250}
251
f1dc5600
S		 252/******************/
253/* Chip Revisions */
254/******************/
255
cbe61d8a 256static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 257{
f1dc5600 258 u32 val;
f078f209 259
ecb1d385
VT		 260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
263 break;
3762561a
GJ		 264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
266 if (ah->get_mac_revision) {
267 ah->hw_version.macRev = ah->get_mac_revision();
268 } else {
269 val = REG_READ(ah, AR_SREV);
270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
271 }
272 return;
ecb1d385
VT		 273 case AR9300_DEVID_AR9340:
274 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
275 val = REG_READ(ah, AR_SREV);
276 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
277 return;
278 }
279
f1dc5600 280 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 281
f1dc5600
S		 282 if (val == 0xFF) {
283 val = REG_READ(ah, AR_SREV);
d535a42a
S		 284 ah->hw_version.macVersion =
285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 287 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 288 } else {
289 if (!AR_SREV_9100(ah))
d535a42a 290 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 291
d535a42a 292 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 293
d535a42a 294 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 295 ah->is_pciexpress = true;
f1dc5600 296 }
f078f209
LR		 297}
298
f1dc5600
S		 299/************************************/
300/* HW Attach, Detach, Init Routines */
301/************************************/
302
cbe61d8a 303static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 304{
040b74f7 305 if (!AR_SREV_5416(ah))
f1dc5600 306 return;
f078f209 307
f1dc5600
S		 308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 317
f1dc5600 318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 319}
320
d4930086
SG		 321static void ath9k_hw_aspm_init(struct ath_hw *ah)
322{
323 struct ath_common *common = ath9k_hw_common(ah);
324
325 if (common->bus_ops->aspm_init)
326 common->bus_ops->aspm_init(common);
327}
328
1f3f0618 329/* This should work for all families including legacy */
cbe61d8a 330static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 331{
c46917bb 332 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 333 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 334 u32 regHold[2];
07b2fa5a
JP		 335 static const u32 patternData[4] = {
336 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
337 };
1f3f0618 338 int i, j, loop_max;
f078f209 339
1f3f0618
SB		 340 if (!AR_SREV_9300_20_OR_LATER(ah)) {
341 loop_max = 2;
342 regAddr[1] = AR_PHY_BASE + (8 << 2);
343 } else
344 loop_max = 1;
345
346 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 347 u32 addr = regAddr[i];
348 u32 wrData, rdData;
f078f209 349
f1dc5600
S		 350 regHold[i] = REG_READ(ah, addr);
351 for (j = 0; j < 0x100; j++) {
352 wrData = (j << 16) | j;
353 REG_WRITE(ah, addr, wrData);
354 rdData = REG_READ(ah, addr);
355 if (rdData != wrData) {
3800276a
JP		 356 ath_err(common,
357 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
358 addr, wrData, rdData);
f1dc5600
S		 359 return false;
360 }
361 }
362 for (j = 0; j < 4; j++) {
363 wrData = patternData[j];
364 REG_WRITE(ah, addr, wrData);
365 rdData = REG_READ(ah, addr);
366 if (wrData != rdData) {
3800276a
JP		 367 ath_err(common,
368 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
369 addr, wrData, rdData);
f1dc5600
S		 370 return false;
371 }
f078f209 372 }
f1dc5600 373 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 374 }
f1dc5600 375 udelay(100);
cbe61d8a 376
f078f209
LR		 377 return true;
378}
379
b8b0f377 380static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 381{
382 int i;
f078f209 383
2660b81a
S		 384 ah->config.dma_beacon_response_time = 2;
385 ah->config.sw_beacon_response_time = 10;
386 ah->config.additional_swba_backoff = 0;
387 ah->config.ack_6mb = 0x0;
388 ah->config.cwm_ignore_extcca = 0;
2660b81a 389 ah->config.pcie_clock_req = 0;
2660b81a
S		 390 ah->config.pcie_waen = 0;
391 ah->config.analog_shiftreg = 1;
03c72518 392 ah->config.enable_ani = true;
f078f209 393
f1dc5600 394 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 395 ah->config.spurchans[i][0] = AR_NO_SPUR;
396 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 397 }
398
6f481010
LR		 399 /* PAPRD needs some more work to be enabled */
400 ah->config.paprd_disable = 1;
401
0ce024cb 402 ah->config.rx_intr_mitigation = true;
6a0ec30a 403 ah->config.pcieSerDesWrite = true;
6158425b
LR		 404
405 /*
406 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
407 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
408 * This means we use it for all AR5416 devices, and the few
409 * minor PCI AR9280 devices out there.
410 *
411 * Serialization is required because these devices do not handle
412 * well the case of two concurrent reads/writes due to the latency
413 * involved. During one read/write another read/write can be issued
414 * on another CPU while the previous read/write may still be working
415 * on our hardware, if we hit this case the hardware poops in a loop.
416 * We prevent this by serializing reads and writes.
417 *
418 * This issue is not present on PCI-Express devices or pre-AR5416
419 * devices (legacy, 802.11abg).
420 */
421 if (num_possible_cpus() > 1)
2d6a5e95 422 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 423}
424
50aca25b 425static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 426{
608b88cb
LR		 427 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
428
429 regulatory->country_code = CTRY_DEFAULT;
430 regulatory->power_limit = MAX_RATE_POWER;
431 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
432
d535a42a 433 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 434 ah->hw_version.subvendorid = 0;
f078f209 435
2660b81a 436 ah->atim_window = 0;
16f2411f
FF		 437 ah->sta_id1_defaults =
438 AR_STA_ID1_CRPT_MIC_ENABLE |
439 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 440 if (AR_SREV_9100(ah))
441 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
2660b81a 442 ah->enable_32kHz_clock = DONT_USE_32KHZ;
e3f2acc7 443 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 444 ah->globaltxtimeout = (u32) -1;
cbdec975 445 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 446}
447
cbe61d8a 448static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 449{
1510718d 450 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 451 u32 sum;
452 int i;
453 u16 eeval;
07b2fa5a 454 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 455
456 sum = 0;
457 for (i = 0; i < 3; i++) {
49101676 458 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 459 sum += eeval;
1510718d
LR		 460 common->macaddr[2 * i] = eeval >> 8;
461 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 462 }
d8baa939 463 if (sum == 0 || sum == 0xffff * 3)
f078f209 464 return -EADDRNOTAVAIL;
f078f209
LR		 465
466 return 0;
467}
468
f637cfd6 469static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 470{
6cae913d 471 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 472 int ecode;
f078f209 473
6cae913d 474 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 475 if (!ath9k_hw_chip_test(ah))
476 return -ENODEV;
477 }
f078f209 478
ebd5a14a
LR		 479 if (!AR_SREV_9300_20_OR_LATER(ah)) {
480 ecode = ar9002_hw_rf_claim(ah);
481 if (ecode != 0)
482 return ecode;
483 }
f078f209 484
f637cfd6 485 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 486 if (ecode != 0)
487 return ecode;
7d01b221 488
226afe68
JP		 489 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
490 "Eeprom VER: %d, REV: %d\n",
491 ah->eep_ops->get_eeprom_ver(ah),
492 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 493
8fe65368
LR		 494 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
495 if (ecode) {
3800276a
JP		 496 ath_err(ath9k_hw_common(ah),
497 "Failed allocating banks for external radio\n");
48a7c3df 498 ath9k_hw_rf_free_ext_banks(ah);
8fe65368 499 return ecode;
574d6b12 500 }
f078f209 501
070c4d50 502 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
f1dc5600 503 ath9k_hw_ani_setup(ah);
f637cfd6 504 ath9k_hw_ani_init(ah);
f078f209
LR		 505 }
506
f078f209
LR		 507 return 0;
508}
509
8525f280 510static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 511{
8525f280
LR		 512 if (AR_SREV_9300_20_OR_LATER(ah))
513 ar9003_hw_attach_ops(ah);
514 else
515 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 516}
517
d70357d5
LR		 518/* Called for all hardware families */
519static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 520{
c46917bb 521 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 522 int r = 0;
aa4058ae 523
ac45c12d
SB		 524 ath9k_hw_read_revisions(ah);
525
0a8d7cb0
SB		 526 /*
527 * Read back AR_WA into a permanent copy and set bits 14 and 17.
528 * We need to do this to avoid RMW of this register. We cannot
529 * read the reg when chip is asleep.
530 */
531 ah->WARegVal = REG_READ(ah, AR_WA);
532 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
533 AR_WA_ASPM_TIMER_BASED_DISABLE);
534
aa4058ae 535 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 536 ath_err(common, "Couldn't reset chip\n");
95fafca2 537 return -EIO;
aa4058ae
LR		 538 }
539
bab1f62e
LR		 540 ath9k_hw_init_defaults(ah);
541 ath9k_hw_init_config(ah);
542
8525f280 543 ath9k_hw_attach_ops(ah);
d70357d5 544
9ecdef4b 545 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 546 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 547 return -EIO;
aa4058ae
LR		 548 }
549
550 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
551 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
4c85ab11
JL		 552 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
553 !ah->is_pciexpress)) {
aa4058ae
LR		 554 ah->config.serialize_regmode =
555 SER_REG_MODE_ON;
556 } else {
557 ah->config.serialize_regmode =
558 SER_REG_MODE_OFF;
559 }
560 }
561
226afe68 562 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 563 ah->config.serialize_regmode);
564
f4709fdf
LR		 565 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
566 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
567 else
568 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
569
6da5a720
FF		 570 switch (ah->hw_version.macVersion) {
571 case AR_SREV_VERSION_5416_PCI:
572 case AR_SREV_VERSION_5416_PCIE:
573 case AR_SREV_VERSION_9160:
574 case AR_SREV_VERSION_9100:
575 case AR_SREV_VERSION_9280:
576 case AR_SREV_VERSION_9285:
577 case AR_SREV_VERSION_9287:
578 case AR_SREV_VERSION_9271:
579 case AR_SREV_VERSION_9300:
2c8e5937 580 case AR_SREV_VERSION_9330:
6da5a720 581 case AR_SREV_VERSION_9485:
bca04689 582 case AR_SREV_VERSION_9340:
6da5a720
FF		 583 break;
584 default:
3800276a
JP		 585 ath_err(common,
586 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
587 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 588 return -EOPNOTSUPP;
aa4058ae
LR		 589 }
590
2c8e5937
GJ		 591 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
592 AR_SREV_9330(ah))
d7e7d229
LR		 593 ah->is_pciexpress = false;
594
aa4058ae 595 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 596 ath9k_hw_init_cal_settings(ah);
597
598 ah->ani_function = ATH9K_ANI_ALL;
7a37081e 599 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 600 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 601 if (!AR_SREV_9300_20_OR_LATER(ah))
602 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae
LR		 603
604 ath9k_hw_init_mode_regs(ah);
605
69ce674b 606 if (!ah->is_pciexpress)
aa4058ae
LR		 607 ath9k_hw_disablepcie(ah);
608
d8f492b7
LR		 609 if (!AR_SREV_9300_20_OR_LATER(ah))
610 ar9002_hw_cck_chan14_spread(ah);
193cd458 611
f637cfd6 612 r = ath9k_hw_post_init(ah);
aa4058ae 613 if (r)
95fafca2 614 return r;
aa4058ae
LR		 615
616 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 617 r = ath9k_hw_fill_cap_info(ah);
618 if (r)
619 return r;
620
69ce674b
SG		 621 if (ah->is_pciexpress)
622 ath9k_hw_aspm_init(ah);
623
4f3acf81
LR		 624 r = ath9k_hw_init_macaddr(ah);
625 if (r) {
3800276a 626 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 627 return r;
f078f209
LR		 628 }
629
d7e7d229 630 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 631 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 632 else
2660b81a 633 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 634
88e641df
GJ		 635 if (AR_SREV_9330(ah))
636 ah->bb_watchdog_timeout_ms = 85;
637 else
638 ah->bb_watchdog_timeout_ms = 25;
f078f209 639
211f5859
LR		 640 common->state = ATH_HW_INITIALIZED;
641
4f3acf81 642 return 0;
f078f209
LR		 643}
644
d70357d5 645int ath9k_hw_init(struct ath_hw *ah)
f078f209 646{
d70357d5
LR		 647 int ret;
648 struct ath_common *common = ath9k_hw_common(ah);
f078f209 649
d70357d5
LR		 650 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
651 switch (ah->hw_version.devid) {
652 case AR5416_DEVID_PCI:
653 case AR5416_DEVID_PCIE:
654 case AR5416_AR9100_DEVID:
655 case AR9160_DEVID_PCI:
656 case AR9280_DEVID_PCI:
657 case AR9280_DEVID_PCIE:
658 case AR9285_DEVID_PCIE:
db3cc53a
SB		 659 case AR9287_DEVID_PCI:
660 case AR9287_DEVID_PCIE:
d70357d5 661 case AR2427_DEVID_PCIE:
db3cc53a 662 case AR9300_DEVID_PCIE:
3050c914 663 case AR9300_DEVID_AR9485_PCIE:
999a7a88 664 case AR9300_DEVID_AR9330:
bca04689 665 case AR9300_DEVID_AR9340:
5a63ef0f 666 case AR9300_DEVID_AR9580:
d70357d5
LR		 667 break;
668 default:
669 if (common->bus_ops->ath_bus_type == ATH_USB)
670 break;
3800276a
JP		 671 ath_err(common, "Hardware device ID 0x%04x not supported\n",
672 ah->hw_version.devid);
d70357d5
LR		 673 return -EOPNOTSUPP;
674 }
f078f209 675
d70357d5
LR		 676 ret = __ath9k_hw_init(ah);
677 if (ret) {
3800276a
JP		 678 ath_err(common,
679 "Unable to initialize hardware; initialization status: %d\n",
680 ret);
d70357d5
LR		 681 return ret;
682 }
f078f209 683
d70357d5 684 return 0;
f078f209 685}
d70357d5 686EXPORT_SYMBOL(ath9k_hw_init);
f078f209 687
cbe61d8a 688static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 689{
7d0d0df0
S		 690 ENABLE_REGWRITE_BUFFER(ah);
691
f1dc5600
S		 692 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
693 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 694
f1dc5600
S		 695 REG_WRITE(ah, AR_QOS_NO_ACK,
696 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
697 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
698 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
699
700 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
701 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
702 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
703 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
704 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 705
706 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 707}
708
b84628eb 709u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 710{
ca7a4deb
FF		 711 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
712 udelay(100);
713 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 714
ca7a4deb
FF		 715 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
716 udelay(100);
b1415819 717
ca7a4deb 718 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 719}
720EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
721
cbe61d8a 722static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 723 struct ath9k_channel *chan)
f078f209 724{
d09b17f7
VT		 725 u32 pll;
726
22983c30 727 if (AR_SREV_9485(ah)) {
22983c30 728
3dfd7f60
VT		 729 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
730 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
731 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
732 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
733 AR_CH0_DPLL2_KD, 0x40);
734 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
735 AR_CH0_DPLL2_KI, 0x4);
22983c30 736
3dfd7f60
VT		 737 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
738 AR_CH0_BB_DPLL1_REFDIV, 0x5);
739 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
740 AR_CH0_BB_DPLL1_NINI, 0x58);
741 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
742 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 743
744 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 745 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
746 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
747 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 748 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 749 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 750
3dfd7f60 751 /* program BB PLL phase_shift to 0x6 */
22983c30 752 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 753 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
754
755 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
756 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 757 udelay(1000);
a5415d62
GJ		 758 } else if (AR_SREV_9330(ah)) {
759 u32 ddr_dpll2, pll_control2, kd;
760
761 if (ah->is_clk_25mhz) {
762 ddr_dpll2 = 0x18e82f01;
763 pll_control2 = 0xe04a3d;
764 kd = 0x1d;
765 } else {
766 ddr_dpll2 = 0x19e82f01;
767 pll_control2 = 0x886666;
768 kd = 0x3d;
769 }
770
771 /* program DDR PLL ki and kd value */
772 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
773
774 /* program DDR PLL phase_shift */
775 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
776 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
777
778 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
779 udelay(1000);
780
781 /* program refdiv, nint, frac to RTC register */
782 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
783
784 /* program BB PLL kd and ki value */
785 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
786 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
787
788 /* program BB PLL phase_shift */
789 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
790 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
0b488ac6
VT		 791 } else if (AR_SREV_9340(ah)) {
792 u32 regval, pll2_divint, pll2_divfrac, refdiv;
793
794 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
795 udelay(1000);
796
797 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
798 udelay(100);
799
800 if (ah->is_clk_25mhz) {
801 pll2_divint = 0x54;
802 pll2_divfrac = 0x1eb85;
803 refdiv = 3;
804 } else {
805 pll2_divint = 88;
806 pll2_divfrac = 0;
807 refdiv = 5;
808 }
809
810 regval = REG_READ(ah, AR_PHY_PLL_MODE);
811 regval |= (0x1 << 16);
812 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
813 udelay(100);
814
815 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
816 (pll2_divint << 18) | pll2_divfrac);
817 udelay(100);
818
819 regval = REG_READ(ah, AR_PHY_PLL_MODE);
820 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
821 (0x4 << 26) | (0x18 << 19);
822 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
823 REG_WRITE(ah, AR_PHY_PLL_MODE,
824 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
825 udelay(1000);
22983c30 826 }
d09b17f7
VT		 827
828 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 829
d03a66c1 830 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 831
a5415d62 832 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
3dfd7f60
VT		 833 udelay(1000);
834
c75724d1
LR		 835 /* Switch the core clock for ar9271 to 117Mhz */
836 if (AR_SREV_9271(ah)) {
25e2ab17
S		 837 udelay(500);
838 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 839 }
840
f1dc5600
S		 841 udelay(RTC_PLL_SETTLE_DELAY);
842
843 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6
VT		 844
845 if (AR_SREV_9340(ah)) {
846 if (ah->is_clk_25mhz) {
847 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
848 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
849 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
850 } else {
851 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
852 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
853 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
854 }
855 udelay(100);
856 }
f078f209
LR		 857}
858
cbe61d8a 859static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 860 enum nl80211_iftype opmode)
f078f209 861{
79d1d2b8 862 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 863 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 864 AR_IMR_TXURN |
865 AR_IMR_RXERR |
866 AR_IMR_RXORN |
867 AR_IMR_BCNMISC;
f078f209 868
79d1d2b8
VT		 869 if (AR_SREV_9340(ah))
870 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
871
66860240
VT		 872 if (AR_SREV_9300_20_OR_LATER(ah)) {
873 imr_reg |= AR_IMR_RXOK_HP;
874 if (ah->config.rx_intr_mitigation)
875 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
876 else
877 imr_reg |= AR_IMR_RXOK_LP;
f078f209 878
66860240
VT		 879 } else {
880 if (ah->config.rx_intr_mitigation)
881 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
882 else
883 imr_reg |= AR_IMR_RXOK;
884 }
f078f209 885
66860240
VT		 886 if (ah->config.tx_intr_mitigation)
887 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
888 else
889 imr_reg |= AR_IMR_TXOK;
f078f209 890
d97809db 891 if (opmode == NL80211_IFTYPE_AP)
152d530d 892 imr_reg |= AR_IMR_MIB;
f078f209 893
7d0d0df0
S		 894 ENABLE_REGWRITE_BUFFER(ah);
895
152d530d 896 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 897 ah->imrs2_reg |= AR_IMR_S2_GTT;
898 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 899
f1dc5600
S		 900 if (!AR_SREV_9100(ah)) {
901 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 902 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 903 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
904 }
66860240 905
7d0d0df0 906 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 907
66860240
VT		 908 if (AR_SREV_9300_20_OR_LATER(ah)) {
909 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
910 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
911 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
912 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
913 }
f078f209
LR		 914}
915
b6ba41bb
FF		 916static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
917{
918 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
919 val = min(val, (u32) 0xFFFF);
920 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
921}
922
0005baf4 923static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 924{
0005baf4
FF		 925 u32 val = ath9k_hw_mac_to_clks(ah, us);
926 val = min(val, (u32) 0xFFFF);
927 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 928}
929
0005baf4 930static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 931{
0005baf4
FF		 932 u32 val = ath9k_hw_mac_to_clks(ah, us);
933 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
934 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
935}
936
937static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
938{
939 u32 val = ath9k_hw_mac_to_clks(ah, us);
940 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
941 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 942}
f1dc5600 943
cbe61d8a 944static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 945{
f078f209 946 if (tu > 0xFFFF) {
226afe68
JP		 947 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
948 "bad global tx timeout %u\n", tu);
2660b81a 949 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 950 return false;
951 } else {
952 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 953 ah->globaltxtimeout = tu;
f078f209
LR		 954 return true;
955 }
956}
957
0005baf4 958void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 959{
b6ba41bb
FF		 960 struct ath_common *common = ath9k_hw_common(ah);
961 struct ieee80211_conf *conf = &common->hw->conf;
962 const struct ath9k_channel *chan = ah->curchan;
0005baf4 963 int acktimeout;
e239d859 964 int slottime;
0005baf4 965 int sifstime;
b6ba41bb
FF		 966 int rx_lat = 0, tx_lat = 0, eifs = 0;
967 u32 reg;
0005baf4 968
226afe68
JP		 969 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
970 ah->misc_mode);
f078f209 971
b6ba41bb
FF		 972 if (!chan)
973 return;
974
2660b81a 975 if (ah->misc_mode != 0)
ca7a4deb 976 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 977
b6ba41bb
FF		 978 rx_lat = 37;
979 tx_lat = 54;
980
981 if (IS_CHAN_HALF_RATE(chan)) {
982 eifs = 175;
983 rx_lat *= 2;
984 tx_lat *= 2;
985 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
986 tx_lat += 11;
987
988 slottime = 13;
989 sifstime = 32;
990 } else if (IS_CHAN_QUARTER_RATE(chan)) {
991 eifs = 340;
992 rx_lat *= 4;
993 tx_lat *= 4;
994 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
995 tx_lat += 22;
996
997 slottime = 21;
998 sifstime = 64;
999 } else {
a7be039d
RM		 1000 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1001 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1002 reg = AR_USEC_ASYNC_FIFO;
1003 } else {
1004 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1005 common->clockrate;
1006 reg = REG_READ(ah, AR_USEC);
1007 }
b6ba41bb
FF		 1008 rx_lat = MS(reg, AR_USEC_RX_LAT);
1009 tx_lat = MS(reg, AR_USEC_TX_LAT);
1010
1011 slottime = ah->slottime;
1012 if (IS_CHAN_5GHZ(chan))
1013 sifstime = 16;
1014 else
1015 sifstime = 10;
1016 }
0005baf4 1017
e239d859 1018 /* As defined by IEEE 802.11-2007 17.3.8.6 */
b6ba41bb 1019 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
42c4568a
FF		 1020
1021 /*
1022 * Workaround for early ACK timeouts, add an offset to match the
1023 * initval's 64us ack timeout value.
1024 * This was initially only meant to work around an issue with delayed
1025 * BA frames in some implementations, but it has been found to fix ACK
1026 * timeout issues in other cases as well.
1027 */
1028 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1029 acktimeout += 64 - sifstime - ah->slottime;
1030
b6ba41bb
FF		 1031 ath9k_hw_set_sifs_time(ah, sifstime);
1032 ath9k_hw_setslottime(ah, slottime);
0005baf4
FF		 1033 ath9k_hw_set_ack_timeout(ah, acktimeout);
1034 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 1035 if (ah->globaltxtimeout != (u32) -1)
1036 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1037
1038 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1039 REG_RMW(ah, AR_USEC,
1040 (common->clockrate - 1) |
1041 SM(rx_lat, AR_USEC_RX_LAT) |
1042 SM(tx_lat, AR_USEC_TX_LAT),
1043 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1044
f1dc5600 1045}
0005baf4 1046EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1047
285f2dda 1048void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1049{
211f5859
LR		 1050 struct ath_common *common = ath9k_hw_common(ah);
1051
736b3a27 1052 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 1053 goto free_hw;
1054
9ecdef4b 1055 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 1056
1057free_hw:
8fe65368 1058 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 1059}
285f2dda 1060EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1061
f1dc5600
S		 1062/*******/
1063/* INI */
1064/*******/
1065
8fe65368 1066u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1067{
1068 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1069
1070 if (IS_CHAN_B(chan))
1071 ctl |= CTL_11B;
1072 else if (IS_CHAN_G(chan))
1073 ctl |= CTL_11G;
1074 else
1075 ctl |= CTL_11A;
1076
1077 return ctl;
1078}
1079
f1dc5600
S		 1080/****************************************/
1081/* Reset and Channel Switching Routines */
1082/****************************************/
f1dc5600 1083
cbe61d8a 1084static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1085{
57b32227 1086 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 1087
7d0d0df0
S		 1088 ENABLE_REGWRITE_BUFFER(ah);
1089
d7e7d229
LR		 1090 /*
1091 * set AHB_MODE not to do cacheline prefetches
1092 */
ca7a4deb
FF		 1093 if (!AR_SREV_9300_20_OR_LATER(ah))
1094 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1095
d7e7d229
LR		 1096 /*
1097 * let mac dma reads be in 128 byte chunks
1098 */
ca7a4deb 1099 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1100
7d0d0df0 1101 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1102
d7e7d229
LR		 1103 /*
1104 * Restore TX Trigger Level to its pre-reset value.
1105 * The initial value depends on whether aggregation is enabled, and is
1106 * adjusted whenever underruns are detected.
1107 */
57b32227
FF		 1108 if (!AR_SREV_9300_20_OR_LATER(ah))
1109 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1110
7d0d0df0 1111 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1112
d7e7d229
LR		 1113 /*
1114 * let mac dma writes be in 128 byte chunks
1115 */
ca7a4deb 1116 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1117
d7e7d229
LR		 1118 /*
1119 * Setup receive FIFO threshold to hold off TX activities
1120 */
f1dc5600
S		 1121 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1122
57b32227
FF		 1123 if (AR_SREV_9300_20_OR_LATER(ah)) {
1124 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1125 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1126
1127 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1128 ah->caps.rx_status_len);
1129 }
1130
d7e7d229
LR		 1131 /*
1132 * reduce the number of usable entries in PCU TXBUF to avoid
1133 * wrap around issues.
1134 */
f1dc5600 1135 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1136 /* For AR9285 the number of Fifos are reduced to half.
1137 * So set the usable tx buf size also to half to
1138 * avoid data/delimiter underruns
1139 */
f1dc5600
S		 1140 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1141 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1142 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1143 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1144 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1145 }
744d4025 1146
7d0d0df0 1147 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1148
744d4025
VT		 1149 if (AR_SREV_9300_20_OR_LATER(ah))
1150 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1151}
1152
cbe61d8a 1153static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1154{
ca7a4deb
FF		 1155 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1156 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1157
f1dc5600 1158 switch (opmode) {
d97809db 1159 case NL80211_IFTYPE_ADHOC:
9cb5412b 1160 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb 1161 set |= AR_STA_ID1_ADHOC;
f1dc5600 1162 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1163 break;
ca7a4deb
FF		 1164 case NL80211_IFTYPE_AP:
1165 set |= AR_STA_ID1_STA_AP;
1166 /* fall through */
d97809db 1167 case NL80211_IFTYPE_STATION:
ca7a4deb 1168 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1169 break;
5f841b41 1170 default:
ca7a4deb
FF		 1171 if (!ah->is_monitoring)
1172 set = 0;
5f841b41 1173 break;
f1dc5600 1174 }
ca7a4deb 1175 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1176}
1177
8fe65368
LR		 1178void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1179 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1180{
1181 u32 coef_exp, coef_man;
1182
1183 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1184 if ((coef_scaled >> coef_exp) & 0x1)
1185 break;
1186
1187 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1188
1189 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1190
1191 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1192 *coef_exponent = coef_exp - 16;
1193}
1194
cbe61d8a 1195static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1196{
1197 u32 rst_flags;
1198 u32 tmpReg;
1199
70768496 1200 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1201 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1202 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1203 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1204 }
1205
7d0d0df0
S		 1206 ENABLE_REGWRITE_BUFFER(ah);
1207
9a658d2b
LR		 1208 if (AR_SREV_9300_20_OR_LATER(ah)) {
1209 REG_WRITE(ah, AR_WA, ah->WARegVal);
1210 udelay(10);
1211 }
1212
f1dc5600
S		 1213 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1214 AR_RTC_FORCE_WAKE_ON_INT);
1215
1216 if (AR_SREV_9100(ah)) {
1217 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1218 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1219 } else {
1220 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1221 if (tmpReg &
1222 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1223 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1224 u32 val;
f1dc5600 1225 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1226
1227 val = AR_RC_HOSTIF;
1228 if (!AR_SREV_9300_20_OR_LATER(ah))
1229 val |= AR_RC_AHB;
1230 REG_WRITE(ah, AR_RC, val);
1231
1232 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1233 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1234
1235 rst_flags = AR_RTC_RC_MAC_WARM;
1236 if (type == ATH9K_RESET_COLD)
1237 rst_flags |= AR_RTC_RC_MAC_COLD;
1238 }
1239
7d95847c
GJ		 1240 if (AR_SREV_9330(ah)) {
1241 int npend = 0;
1242 int i;
1243
1244 /* AR9330 WAR:
1245 * call external reset function to reset WMAC if:
1246 * - doing a cold reset
1247 * - we have pending frames in the TX queues
1248 */
1249
1250 for (i = 0; i < AR_NUM_QCU; i++) {
1251 npend = ath9k_hw_numtxpending(ah, i);
1252 if (npend)
1253 break;
1254 }
1255
1256 if (ah->external_reset &&
1257 (npend || type == ATH9K_RESET_COLD)) {
1258 int reset_err = 0;
1259
1260 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1261 "reset MAC via external reset\n");
1262
1263 reset_err = ah->external_reset();
1264 if (reset_err) {
1265 ath_err(ath9k_hw_common(ah),
1266 "External reset failed, err=%d\n",
1267 reset_err);
1268 return false;
1269 }
1270
1271 REG_WRITE(ah, AR_RTC_RESET, 1);
1272 }
1273 }
1274
d03a66c1 1275 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1276
1277 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1278
f1dc5600
S		 1279 udelay(50);
1280
d03a66c1 1281 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1282 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
226afe68
JP		 1283 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1284 "RTC stuck in MAC reset\n");
f1dc5600
S		 1285 return false;
1286 }
1287
1288 if (!AR_SREV_9100(ah))
1289 REG_WRITE(ah, AR_RC, 0);
1290
f1dc5600
S		 1291 if (AR_SREV_9100(ah))
1292 udelay(50);
1293
1294 return true;
1295}
1296
cbe61d8a 1297static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1298{
7d0d0df0
S		 1299 ENABLE_REGWRITE_BUFFER(ah);
1300
9a658d2b
LR		 1301 if (AR_SREV_9300_20_OR_LATER(ah)) {
1302 REG_WRITE(ah, AR_WA, ah->WARegVal);
1303 udelay(10);
1304 }
1305
f1dc5600
S		 1306 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1307 AR_RTC_FORCE_WAKE_ON_INT);
1308
42d5bc3f 1309 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1310 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1311
d03a66c1 1312 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1313
7d0d0df0 1314 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1315
84e2169b
SB		 1316 if (!AR_SREV_9300_20_OR_LATER(ah))
1317 udelay(2);
1318
1319 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1320 REG_WRITE(ah, AR_RC, 0);
1321
d03a66c1 1322 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1323
1324 if (!ath9k_hw_wait(ah,
1325 AR_RTC_STATUS,
1326 AR_RTC_STATUS_M,
0caa7b14
S		 1327 AR_RTC_STATUS_ON,
1328 AH_WAIT_TIMEOUT)) {
226afe68
JP		 1329 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1330 "RTC not waking up\n");
f1dc5600 1331 return false;
f078f209
LR		 1332 }
1333
f1dc5600
S		 1334 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1335}
1336
cbe61d8a 1337static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1338{
9a658d2b
LR		 1339 if (AR_SREV_9300_20_OR_LATER(ah)) {
1340 REG_WRITE(ah, AR_WA, ah->WARegVal);
1341 udelay(10);
1342 }
1343
f1dc5600
S		 1344 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1345 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1346
1347 switch (type) {
1348 case ATH9K_RESET_POWER_ON:
1349 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1350 case ATH9K_RESET_WARM:
1351 case ATH9K_RESET_COLD:
1352 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1353 default:
1354 return false;
1355 }
f078f209
LR		 1356}
1357
cbe61d8a 1358static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1359 struct ath9k_channel *chan)
f078f209 1360{
42abfbee 1361 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1362 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1363 return false;
1364 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1365 return false;
f078f209 1366
9ecdef4b 1367 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1368 return false;
f078f209 1369
2660b81a 1370 ah->chip_fullsleep = false;
f1dc5600 1371 ath9k_hw_init_pll(ah, chan);
f1dc5600 1372 ath9k_hw_set_rfmode(ah, chan);
f078f209 1373
f1dc5600 1374 return true;
f078f209
LR		 1375}
1376
cbe61d8a 1377static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1378 struct ath9k_channel *chan)
f078f209 1379{
608b88cb 1380 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1381 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1382 struct ieee80211_channel *channel = chan->chan;
8fe65368 1383 u32 qnum;
0a3b7bac 1384 int r;
f078f209
LR		 1385
1386 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1387 if (ath9k_hw_numtxpending(ah, qnum)) {
226afe68
JP		 1388 ath_dbg(common, ATH_DBG_QUEUE,
1389 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1390 return false;
1391 }
1392 }
1393
8fe65368 1394 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1395 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1396 return false;
1397 }
1398
8fe65368 1399 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1400
8fe65368 1401 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1402 if (r) {
3800276a 1403 ath_err(common, "Failed to set channel\n");
0a3b7bac 1404 return false;
f078f209 1405 }
dfdac8ac 1406 ath9k_hw_set_clockrate(ah);
f078f209 1407
8fbff4b8 1408 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1409 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1410 channel->max_antenna_gain * 2,
1411 channel->max_power * 2,
1412 min((u32) MAX_RATE_POWER,
de40f316 1413 (u32) regulatory->power_limit), false);
f078f209 1414
8fe65368 1415 ath9k_hw_rfbus_done(ah);
f078f209 1416
f1dc5600
S		 1417 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1418 ath9k_hw_set_delta_slope(ah, chan);
1419
8fe65368 1420 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1421
f1dc5600
S		 1422 return true;
1423}
1424
691680b8
FF		 1425static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1426{
1427 u32 gpio_mask = ah->gpio_mask;
1428 int i;
1429
1430 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1431 if (!(gpio_mask & 1))
1432 continue;
1433
1434 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1435 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1436 }
1437}
1438
c9c99e5e 1439bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1440{
c9c99e5e
FF		 1441 int count = 50;
1442 u32 reg;
1443
e17f83ea 1444 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1445 return true;
1446
1447 do {
1448 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1449
c9c99e5e
FF		 1450 if ((reg & 0x7E7FFFEF) == 0x00702400)
1451 continue;
1452
1453 switch (reg & 0x7E000B00) {
1454 case 0x1E000000:
1455 case 0x52000B00:
1456 case 0x18000B00:
1457 continue;
1458 default:
1459 return true;
1460 }
1461 } while (count-- > 0);
3b319aae 1462
c9c99e5e 1463 return false;
3b319aae 1464}
c9c99e5e 1465EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1466
cbe61d8a 1467int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 1468 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
f078f209 1469{
1510718d 1470 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1471 u32 saveLedState;
2660b81a 1472 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1473 u32 saveDefAntenna;
1474 u32 macStaId1;
46fe782c 1475 u64 tsf = 0;
8fe65368 1476 int i, r;
f078f209 1477
43c27613
LR		 1478 ah->txchainmask = common->tx_chainmask;
1479 ah->rxchainmask = common->rx_chainmask;
f078f209 1480
9ecdef4b 1481 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1482 return -EIO;
f078f209 1483
d9891c78 1484 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1485 ath9k_hw_getnf(ah, curchan);
1486
20bd2a09
FF		 1487 ah->caldata = caldata;
1488 if (caldata &&
1489 (chan->channel != caldata->channel ||
1490 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1491 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1492 /* Operating channel changed, reset channel calibration data */
1493 memset(caldata, 0, sizeof(*caldata));
1494 ath9k_init_nfcal_hist_buffer(ah, chan);
1495 }
f23fba49 1496 ah->noise = ath9k_hw_getchan_noise(ah, chan);
20bd2a09 1497
f078f209 1498 if (bChannelChange &&
2660b81a
S		 1499 (ah->chip_fullsleep != true) &&
1500 (ah->curchan != NULL) &&
1501 (chan->channel != ah->curchan->channel) &&
f078f209 1502 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1503 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
58d7e0f3 1504 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
f078f209 1505
25c56eec 1506 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1507 ath9k_hw_loadnf(ah, ah->curchan);
00c86590 1508 ath9k_hw_start_nfcal(ah, true);
c2ba3342
RM		 1509 if (AR_SREV_9271(ah))
1510 ar9002_hw_load_ani_reg(ah, chan);
ae8d2858 1511 return 0;
f078f209
LR		 1512 }
1513 }
1514
1515 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1516 if (saveDefAntenna == 0)
1517 saveDefAntenna = 1;
1518
1519 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1520
46fe782c 1521 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1522 if (AR_SREV_9100(ah) ||
1523 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1524 tsf = ath9k_hw_gettsf64(ah);
1525
f078f209
LR		 1526 saveLedState = REG_READ(ah, AR_CFG_LED) &
1527 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1528 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1529
1530 ath9k_hw_mark_phy_inactive(ah);
1531
45ef6a0b
VT		 1532 ah->paprd_table_write_done = false;
1533
05020d23 1534 /* Only required on the first reset */
d7e7d229
LR		 1535 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1536 REG_WRITE(ah,
1537 AR9271_RESET_POWER_DOWN_CONTROL,
1538 AR9271_RADIO_RF_RST);
1539 udelay(50);
1540 }
1541
f078f209 1542 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1543 ath_err(common, "Chip reset failed\n");
ae8d2858 1544 return -EINVAL;
f078f209
LR		 1545 }
1546
05020d23 1547 /* Only required on the first reset */
d7e7d229
LR		 1548 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1549 ah->htc_reset_init = false;
1550 REG_WRITE(ah,
1551 AR9271_RESET_POWER_DOWN_CONTROL,
1552 AR9271_GATE_MAC_CTL);
1553 udelay(50);
1554 }
1555
46fe782c 1556 /* Restore TSF */
f860d526 1557 if (tsf)
46fe782c
S		 1558 ath9k_hw_settsf64(ah, tsf);
1559
7a37081e 1560 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1561 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1562
e9141f71
S		 1563 if (!AR_SREV_9300_20_OR_LATER(ah))
1564 ar9002_hw_enable_async_fifo(ah);
1565
25c56eec 1566 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1567 if (r)
1568 return r;
f078f209 1569
f860d526
FF		 1570 /*
1571 * Some AR91xx SoC devices frequently fail to accept TSF writes
1572 * right after the chip reset. When that happens, write a new
1573 * value after the initvals have been applied, with an offset
1574 * based on measured time difference
1575 */
1576 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1577 tsf += 1500;
1578 ath9k_hw_settsf64(ah, tsf);
1579 }
1580
0ced0e17
JM		 1581 /* Setup MFP options for CCMP */
1582 if (AR_SREV_9280_20_OR_LATER(ah)) {
1583 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1584 * frames when constructing CCMP AAD. */
1585 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1586 0xc7ff);
1587 ah->sw_mgmt_crypto = false;
1588 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1589 /* Disable hardware crypto for management frames */
1590 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1591 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1592 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1593 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1594 ah->sw_mgmt_crypto = true;
1595 } else
1596 ah->sw_mgmt_crypto = true;
1597
f078f209
LR		 1598 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1599 ath9k_hw_set_delta_slope(ah, chan);
1600
8fe65368 1601 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1602 ah->eep_ops->set_board_values(ah, chan);
a7765828 1603
7d0d0df0
S		 1604 ENABLE_REGWRITE_BUFFER(ah);
1605
1510718d
LR		 1606 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1607 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1608 | macStaId1
1609 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1610 | (ah->config.
60b67f51 1611 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1612 | ah->sta_id1_defaults);
13b81559 1613 ath_hw_setbssidmask(common);
f078f209 1614 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1615 ath9k_hw_write_associd(ah);
f078f209 1616 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1617 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1618
7d0d0df0 1619 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1620
00e0003e
SM		 1621 ath9k_hw_set_operating_mode(ah, ah->opmode);
1622
8fe65368 1623 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1624 if (r)
1625 return r;
f078f209 1626
dfdac8ac
FF		 1627 ath9k_hw_set_clockrate(ah);
1628
7d0d0df0
S		 1629 ENABLE_REGWRITE_BUFFER(ah);
1630
f078f209
LR		 1631 for (i = 0; i < AR_NUM_DCU; i++)
1632 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1633
7d0d0df0 1634 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1635
2660b81a 1636 ah->intr_txqs = 0;
f4c607dc 1637 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
f078f209
LR		 1638 ath9k_hw_resettxqueue(ah, i);
1639
2660b81a 1640 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1641 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1642 ath9k_hw_init_qos(ah);
1643
2660b81a 1644 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1645 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1646
0005baf4 1647 ath9k_hw_init_global_settings(ah);
f078f209 1648
fe2b6afb
FF		 1649 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1650 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1651 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1652 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1653 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1654 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1655 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1656 }
1657
ca7a4deb 1658 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1659
1660 ath9k_hw_set_dma(ah);
1661
1662 REG_WRITE(ah, AR_OBS, 8);
1663
0ce024cb 1664 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1665 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1666 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1667 }
1668
7f62a136
VT		 1669 if (ah->config.tx_intr_mitigation) {
1670 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1671 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1672 }
1673
f078f209
LR		 1674 ath9k_hw_init_bb(ah, chan);
1675
ae8d2858 1676 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1677 return -EIO;
f078f209 1678
7d0d0df0 1679 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1680
8fe65368 1681 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1682 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1683
7d0d0df0 1684 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1685
d7e7d229
LR		 1686 /*
1687 * For big endian systems turn on swapping for descriptors
1688 */
f078f209
LR		 1689 if (AR_SREV_9100(ah)) {
1690 u32 mask;
1691 mask = REG_READ(ah, AR_CFG);
1692 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
226afe68 1693 ath_dbg(common, ATH_DBG_RESET,
04bd4638 1694 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1695 } else {
1696 mask =
1697 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1698 REG_WRITE(ah, AR_CFG, mask);
226afe68 1699 ath_dbg(common, ATH_DBG_RESET,
04bd4638 1700 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1701 }
1702 } else {
cbba8cd1
S		 1703 if (common->bus_ops->ath_bus_type == ATH_USB) {
1704 /* Configure AR9271 target WLAN */
1705 if (AR_SREV_9271(ah))
1706 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1707 else
1708 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1709 }
f078f209 1710#ifdef __BIG_ENDIAN
4033bdad 1711 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
2be7bfe0
VT		 1712 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1713 else
d7e7d229 1714 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1715#endif
1716 }
1717
766ec4a9 1718 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1719 ath9k_hw_btcoex_enable(ah);
1720
51ac8cbb 1721 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 1722 ar9003_hw_bb_watchdog_config(ah);
d8903a53 1723
51ac8cbb
RM		 1724 ar9003_hw_disable_phy_restart(ah);
1725 }
1726
691680b8
FF		 1727 ath9k_hw_apply_gpio_override(ah);
1728
ae8d2858 1729 return 0;
f078f209 1730}
7322fd19 1731EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1732
f1dc5600
S		 1733/******************************/
1734/* Power Management (Chipset) */
1735/******************************/
1736
42d5bc3f
LR		 1737/*
1738 * Notify Power Mgt is disabled in self-generated frames.
1739 * If requested, force chip to sleep.
1740 */
cbe61d8a 1741static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1742{
f1dc5600
S		 1743 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1744 if (setChip) {
42d5bc3f
LR		 1745 /*
1746 * Clear the RTC force wake bit to allow the
1747 * mac to go to sleep.
1748 */
f1dc5600
S		 1749 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1750 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1751 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1752 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1753
42d5bc3f 1754 /* Shutdown chip. Active low */
14b3af38 1755 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1756 REG_CLR_BIT(ah, (AR_RTC_RESET),
1757 AR_RTC_RESET_EN);
f1dc5600 1758 }
9a658d2b
LR		 1759
1760 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1761 if (AR_SREV_9300_20_OR_LATER(ah))
1762 REG_WRITE(ah, AR_WA,
1763 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1764}
1765
bbd79af5
LR		 1766/*
1767 * Notify Power Management is enabled in self-generating
1768 * frames. If request, set power mode of chip to
1769 * auto/normal. Duration in units of 128us (1/8 TU).
1770 */
cbe61d8a 1771static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1772{
f1dc5600
S		 1773 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1774 if (setChip) {
2660b81a 1775 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1776
f1dc5600 1777 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1778 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1779 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1780 AR_RTC_FORCE_WAKE_ON_INT);
1781 } else {
bbd79af5
LR		 1782 /*
1783 * Clear the RTC force wake bit to allow the
1784 * mac to go to sleep.
1785 */
f1dc5600
S		 1786 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1787 AR_RTC_FORCE_WAKE_EN);
f078f209 1788 }
f078f209 1789 }
9a658d2b
LR		 1790
1791 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1792 if (AR_SREV_9300_20_OR_LATER(ah))
1793 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1794}
1795
cbe61d8a 1796static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1797{
f1dc5600
S		 1798 u32 val;
1799 int i;
f078f209 1800
9a658d2b
LR		 1801 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1802 if (AR_SREV_9300_20_OR_LATER(ah)) {
1803 REG_WRITE(ah, AR_WA, ah->WARegVal);
1804 udelay(10);
1805 }
1806
f1dc5600
S		 1807 if (setChip) {
1808 if ((REG_READ(ah, AR_RTC_STATUS) &
1809 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1810 if (ath9k_hw_set_reset_reg(ah,
1811 ATH9K_RESET_POWER_ON) != true) {
1812 return false;
1813 }
e041228f
LR		 1814 if (!AR_SREV_9300_20_OR_LATER(ah))
1815 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1816 }
1817 if (AR_SREV_9100(ah))
1818 REG_SET_BIT(ah, AR_RTC_RESET,
1819 AR_RTC_RESET_EN);
f078f209 1820
f1dc5600
S		 1821 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1822 AR_RTC_FORCE_WAKE_EN);
1823 udelay(50);
f078f209 1824
f1dc5600
S		 1825 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1826 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1827 if (val == AR_RTC_STATUS_ON)
1828 break;
1829 udelay(50);
1830 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1831 AR_RTC_FORCE_WAKE_EN);
f078f209 1832 }
f1dc5600 1833 if (i == 0) {
3800276a
JP		 1834 ath_err(ath9k_hw_common(ah),
1835 "Failed to wakeup in %uus\n",
1836 POWER_UP_TIME / 20);
f1dc5600 1837 return false;
f078f209 1838 }
f078f209
LR		 1839 }
1840
f1dc5600 1841 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1842
f1dc5600 1843 return true;
f078f209
LR		 1844}
1845
9ecdef4b 1846bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1847{
c46917bb 1848 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1849 int status = true, setChip = true;
f1dc5600
S		 1850 static const char *modes[] = {
1851 "AWAKE",
1852 "FULL-SLEEP",
1853 "NETWORK SLEEP",
1854 "UNDEFINED"
1855 };
f1dc5600 1856
cbdec975
GJ		 1857 if (ah->power_mode == mode)
1858 return status;
1859
226afe68
JP		 1860 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1861 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1862
1863 switch (mode) {
1864 case ATH9K_PM_AWAKE:
1865 status = ath9k_hw_set_power_awake(ah, setChip);
1866 break;
1867 case ATH9K_PM_FULL_SLEEP:
1868 ath9k_set_power_sleep(ah, setChip);
2660b81a 1869 ah->chip_fullsleep = true;
f1dc5600
S		 1870 break;
1871 case ATH9K_PM_NETWORK_SLEEP:
1872 ath9k_set_power_network_sleep(ah, setChip);
1873 break;
f078f209 1874 default:
3800276a 1875 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 1876 return false;
1877 }
2660b81a 1878 ah->power_mode = mode;
f1dc5600 1879
69f4aab1
LR		 1880 /*
1881 * XXX: If this warning never comes up after a while then
1882 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1883 * ath9k_hw_setpower() return type void.
1884 */
97dcec57
SM		 1885
1886 if (!(ah->ah_flags & AH_UNPLUGGED))
1887 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 1888
f1dc5600 1889 return status;
f078f209 1890}
7322fd19 1891EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1892
f1dc5600
S		 1893/*******************/
1894/* Beacon Handling */
1895/*******************/
1896
cbe61d8a 1897void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 1898{
f078f209
LR		 1899 int flags = 0;
1900
7d0d0df0
S		 1901 ENABLE_REGWRITE_BUFFER(ah);
1902
2660b81a 1903 switch (ah->opmode) {
d97809db 1904 case NL80211_IFTYPE_ADHOC:
9cb5412b 1905 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 1906 REG_SET_BIT(ah, AR_TXCFG,
1907 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
dd347f2f
FF		 1908 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1909 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
f078f209 1910 flags |= AR_NDP_TIMER_EN;
d97809db 1911 case NL80211_IFTYPE_AP:
dd347f2f
FF		 1912 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1913 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1914 TU_TO_USEC(ah->config.dma_beacon_response_time));
1915 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1916 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 1917 flags |=
1918 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1919 break;
d97809db 1920 default:
226afe68
JP		 1921 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1922 "%s: unsupported opmode: %d\n",
1923 __func__, ah->opmode);
d97809db
CM		 1924 return;
1925 break;
f078f209
LR		 1926 }
1927
dd347f2f
FF		 1928 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1929 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1930 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1931 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
f078f209 1932
7d0d0df0 1933 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1934
f078f209
LR		 1935 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1936}
7322fd19 1937EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 1938
cbe61d8a 1939void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 1940 const struct ath9k_beacon_state *bs)
f078f209
LR		 1941{
1942 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 1943 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1944 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1945
7d0d0df0
S		 1946 ENABLE_REGWRITE_BUFFER(ah);
1947
f078f209
LR		 1948 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1949
1950 REG_WRITE(ah, AR_BEACON_PERIOD,
f29f5c08 1951 TU_TO_USEC(bs->bs_intval));
f078f209 1952 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
f29f5c08 1953 TU_TO_USEC(bs->bs_intval));
f078f209 1954
7d0d0df0 1955 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1956
f078f209
LR		 1957 REG_RMW_FIELD(ah, AR_RSSI_THR,
1958 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1959
f29f5c08 1960 beaconintval = bs->bs_intval;
f078f209
LR		 1961
1962 if (bs->bs_sleepduration > beaconintval)
1963 beaconintval = bs->bs_sleepduration;
1964
1965 dtimperiod = bs->bs_dtimperiod;
1966 if (bs->bs_sleepduration > dtimperiod)
1967 dtimperiod = bs->bs_sleepduration;
1968
1969 if (beaconintval == dtimperiod)
1970 nextTbtt = bs->bs_nextdtim;
1971 else
1972 nextTbtt = bs->bs_nexttbtt;
1973
226afe68
JP		 1974 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1975 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1976 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1977 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 1978
7d0d0df0
S		 1979 ENABLE_REGWRITE_BUFFER(ah);
1980
f1dc5600
S		 1981 REG_WRITE(ah, AR_NEXT_DTIM,
1982 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1983 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 1984
f1dc5600
S		 1985 REG_WRITE(ah, AR_SLEEP1,
1986 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1987 | AR_SLEEP1_ASSUME_DTIM);
f078f209 1988
f1dc5600
S		 1989 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1990 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1991 else
1992 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 1993
f1dc5600
S		 1994 REG_WRITE(ah, AR_SLEEP2,
1995 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 1996
f1dc5600
S		 1997 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1998 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 1999
7d0d0df0 2000 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2001
f1dc5600
S		 2002 REG_SET_BIT(ah, AR_TIMER_MODE,
2003 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2004 AR_DTIM_TIMER_EN);
f078f209 2005
4af9cf4f
S		 2006 /* TSF Out of Range Threshold */
2007 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2008}
7322fd19 2009EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2010
f1dc5600
S		 2011/*******************/
2012/* HW Capabilities */
2013/*******************/
2014
6054069a
FF		 2015static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2016{
2017 eeprom_chainmask &= chip_chainmask;
2018 if (eeprom_chainmask)
2019 return eeprom_chainmask;
2020 else
2021 return chip_chainmask;
2022}
2023
a9a29ce6 2024int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2025{
2660b81a 2026 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2027 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2028 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 2029 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
6054069a 2030 unsigned int chip_chainmask;
608b88cb 2031
0ff2b5c0 2032 u16 eeval;
47c80de6 2033 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2034
f74df6fb 2035 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2036 regulatory->current_rd = eeval;
f078f209 2037
f74df6fb 2038 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
e17f83ea 2039 if (AR_SREV_9285_12_OR_LATER(ah))
fec0de11 2040 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 2041 regulatory->current_rd_ext = eeval;
f078f209 2042
2660b81a 2043 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2044 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2045 if (regulatory->current_rd == 0x64 ||
2046 regulatory->current_rd == 0x65)
2047 regulatory->current_rd += 5;
2048 else if (regulatory->current_rd == 0x41)
2049 regulatory->current_rd = 0x43;
226afe68
JP		 2050 ath_dbg(common, ATH_DBG_REGULATORY,
2051 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 2052 }
f078f209 2053
f74df6fb 2054 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2055 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2056 ath_err(common,
2057 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2058 return -EINVAL;
2059 }
2060
d4659912
FF		 2061 if (eeval & AR5416_OPFLAGS_11A)
2062 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2063
d4659912
FF		 2064 if (eeval & AR5416_OPFLAGS_11G)
2065 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2066
6054069a
FF		 2067 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2068 chip_chainmask = 1;
2069 else if (!AR_SREV_9280_20_OR_LATER(ah))
2070 chip_chainmask = 7;
2071 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2072 chip_chainmask = 3;
2073 else
2074 chip_chainmask = 7;
2075
f74df6fb 2076 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2077 /*
2078 * For AR9271 we will temporarilly uses the rx chainmax as read from
2079 * the EEPROM.
2080 */
8147f5de 2081 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2082 !(eeval & AR5416_OPFLAGS_11A) &&
2083 !(AR_SREV_9271(ah)))
2084 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2085 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2086 else if (AR_SREV_9100(ah))
2087 pCap->rx_chainmask = 0x7;
8147f5de 2088 else
d7e7d229 2089 /* Use rx_chainmask from EEPROM. */
8147f5de 2090 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2091
6054069a
FF		 2092 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2093 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2094
7a37081e 2095 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2096
02d2ebb2
FF		 2097 /* enable key search for every frame in an aggregate */
2098 if (AR_SREV_9300_20_OR_LATER(ah))
2099 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2100
ce2220d1
BR		 2101 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2102
0db156e9 2103 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2104 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2105 else
2106 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2107
5b5fa355
S		 2108 if (AR_SREV_9271(ah))
2109 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2110 else if (AR_DEVID_7010(ah))
2111 pCap->num_gpio_pins = AR7010_NUM_GPIO;
e17f83ea 2112 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2113 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2114 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2115 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2116 else
2117 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2118
f1dc5600
S		 2119 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2120 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2121 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2122 } else {
2123 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 2124 }
2125
e97275cb 2126#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2127 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2128 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2129 ah->rfkill_gpio =
2130 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2131 ah->rfkill_polarity =
2132 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2133
2134 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2135 }
f1dc5600 2136#endif
d5d1154f 2137 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2138 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2139 else
2140 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2141
e7594072 2142 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2143 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2144 else
2145 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2146
a6ef530f
VN		 2147 if (common->btcoex_enabled) {
2148 if (AR_SREV_9300_20_OR_LATER(ah)) {
766ec4a9 2149 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
a6ef530f
VN		 2150 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2151 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2152 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
2153 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2154 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
2155 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
2156
2157 if (AR_SREV_9285(ah)) {
2158 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2159 btcoex_hw->btpriority_gpio =
2160 ATH_BTPRIORITY_GPIO_9285;
2161 } else {
2162 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2163 }
8c8f9ba7 2164 }
22f25d0d 2165 } else {
766ec4a9 2166 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 2167 }
a9a29ce6 2168
ceb26445 2169 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2170 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
0e707a94 2171 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
784ad503
VT		 2172 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2173
ceb26445
VT		 2174 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2175 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2176 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2177 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2178 pCap->txs_len = sizeof(struct ar9003_txs);
6f481010
LR		 2179 if (!ah->config.paprd_disable &&
2180 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
4935250a 2181 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 2182 } else {
2183 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2184 if (AR_SREV_9280_20(ah))
6b42e8d0 2185 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2186 }
1adf02ff 2187
6c84ce08
VT		 2188 if (AR_SREV_9300_20_OR_LATER(ah))
2189 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2190
6ee63f55
SB		 2191 if (AR_SREV_9300_20_OR_LATER(ah))
2192 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2193
a42acef0 2194 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2195 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2196
754dc536
VT		 2197 if (AR_SREV_9285(ah))
2198 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2199 ant_div_ctl1 =
2200 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2201 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2202 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2203 }
ea066d5a
MSS		 2204 if (AR_SREV_9300_20_OR_LATER(ah)) {
2205 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2206 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2207 }
2208
2209
431da56a 2210 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
21d2c63a
MSS		 2211 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2212 /*
2213 * enable the diversity-combining algorithm only when
2214 * both enable_lna_div and enable_fast_div are set
2215 * Table for Diversity
2216 * ant_div_alt_lnaconf bit 0-1
2217 * ant_div_main_lnaconf bit 2-3
2218 * ant_div_alt_gaintb bit 4
2219 * ant_div_main_gaintb bit 5
2220 * enable_ant_div_lnadiv bit 6
2221 * enable_ant_fast_div bit 7
2222 */
2223 if ((ant_div_ctl1 >> 0x6) == 0x3)
2224 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2225 }
754dc536 2226
8060e169
VT		 2227 if (AR_SREV_9485_10(ah)) {
2228 pCap->pcie_lcr_extsync_en = true;
2229 pCap->pcie_lcr_offset = 0x80;
2230 }
2231
47c80de6
VT		 2232 tx_chainmask = pCap->tx_chainmask;
2233 rx_chainmask = pCap->rx_chainmask;
2234 while (tx_chainmask || rx_chainmask) {
2235 if (tx_chainmask & BIT(0))
2236 pCap->max_txchains++;
2237 if (rx_chainmask & BIT(0))
2238 pCap->max_rxchains++;
2239
2240 tx_chainmask >>= 1;
2241 rx_chainmask >>= 1;
2242 }
2243
a9a29ce6 2244 return 0;
f078f209
LR		 2245}
2246
f1dc5600
S		 2247/****************************/
2248/* GPIO / RFKILL / Antennae */
2249/****************************/
f078f209 2250
cbe61d8a 2251static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2252 u32 gpio, u32 type)
2253{
2254 int addr;
2255 u32 gpio_shift, tmp;
f078f209 2256
f1dc5600
S		 2257 if (gpio > 11)
2258 addr = AR_GPIO_OUTPUT_MUX3;
2259 else if (gpio > 5)
2260 addr = AR_GPIO_OUTPUT_MUX2;
2261 else
2262 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2263
f1dc5600 2264 gpio_shift = (gpio % 6) * 5;
f078f209 2265
f1dc5600
S		 2266 if (AR_SREV_9280_20_OR_LATER(ah)
2267 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2268 REG_RMW(ah, addr, (type << gpio_shift),
2269 (0x1f << gpio_shift));
f078f209 2270 } else {
f1dc5600
S		 2271 tmp = REG_READ(ah, addr);
2272 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2273 tmp &= ~(0x1f << gpio_shift);
2274 tmp |= (type << gpio_shift);
2275 REG_WRITE(ah, addr, tmp);
f078f209 2276 }
f078f209
LR		 2277}
2278
cbe61d8a 2279void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2280{
f1dc5600 2281 u32 gpio_shift;
f078f209 2282
9680e8a3 2283 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2284
88c1f4f6
S		 2285 if (AR_DEVID_7010(ah)) {
2286 gpio_shift = gpio;
2287 REG_RMW(ah, AR7010_GPIO_OE,
2288 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2289 (AR7010_GPIO_OE_MASK << gpio_shift));
2290 return;
2291 }
f078f209 2292
88c1f4f6 2293 gpio_shift = gpio << 1;
f1dc5600
S		 2294 REG_RMW(ah,
2295 AR_GPIO_OE_OUT,
2296 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2297 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2298}
7322fd19 2299EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2300
cbe61d8a 2301u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2302{
cb33c412
SB		 2303#define MS_REG_READ(x, y) \
2304 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2305
2660b81a 2306 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2307 return 0xffffffff;
f078f209 2308
88c1f4f6
S		 2309 if (AR_DEVID_7010(ah)) {
2310 u32 val;
2311 val = REG_READ(ah, AR7010_GPIO_IN);
2312 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2313 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2314 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2315 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2316 else if (AR_SREV_9271(ah))
5b5fa355 2317 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2318 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2319 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2320 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2321 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2322 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2323 return MS_REG_READ(AR928X, gpio) != 0;
2324 else
2325 return MS_REG_READ(AR, gpio) != 0;
f078f209 2326}
7322fd19 2327EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2328
cbe61d8a 2329void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2330 u32 ah_signal_type)
f078f209 2331{
f1dc5600 2332 u32 gpio_shift;
f078f209 2333
88c1f4f6
S		 2334 if (AR_DEVID_7010(ah)) {
2335 gpio_shift = gpio;
2336 REG_RMW(ah, AR7010_GPIO_OE,
2337 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2338 (AR7010_GPIO_OE_MASK << gpio_shift));
2339 return;
2340 }
f078f209 2341
88c1f4f6 2342 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2343 gpio_shift = 2 * gpio;
f1dc5600
S		 2344 REG_RMW(ah,
2345 AR_GPIO_OE_OUT,
2346 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2347 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2348}
7322fd19 2349EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2350
cbe61d8a 2351void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2352{
88c1f4f6
S		 2353 if (AR_DEVID_7010(ah)) {
2354 val = val ? 0 : 1;
2355 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2356 AR_GPIO_BIT(gpio));
2357 return;
2358 }
2359
5b5fa355
S		 2360 if (AR_SREV_9271(ah))
2361 val = ~val;
2362
f1dc5600
S		 2363 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2364 AR_GPIO_BIT(gpio));
f078f209 2365}
7322fd19 2366EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2367
cbe61d8a 2368u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2369{
f1dc5600 2370 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2371}
7322fd19 2372EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2373
cbe61d8a 2374void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2375{
f1dc5600 2376 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2377}
7322fd19 2378EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2379
f1dc5600
S		 2380/*********************/
2381/* General Operation */
2382/*********************/
2383
cbe61d8a 2384u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2385{
f1dc5600
S		 2386 u32 bits = REG_READ(ah, AR_RX_FILTER);
2387 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2388
f1dc5600
S		 2389 if (phybits & AR_PHY_ERR_RADAR)
2390 bits |= ATH9K_RX_FILTER_PHYRADAR;
2391 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2392 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2393
f1dc5600 2394 return bits;
f078f209 2395}
7322fd19 2396EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2397
cbe61d8a 2398void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2399{
f1dc5600 2400 u32 phybits;
f078f209 2401
7d0d0df0
S		 2402 ENABLE_REGWRITE_BUFFER(ah);
2403
7ea310be
S		 2404 REG_WRITE(ah, AR_RX_FILTER, bits);
2405
f1dc5600
S		 2406 phybits = 0;
2407 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2408 phybits |= AR_PHY_ERR_RADAR;
2409 if (bits & ATH9K_RX_FILTER_PHYERR)
2410 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2411 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2412
f1dc5600 2413 if (phybits)
ca7a4deb 2414 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2415 else
ca7a4deb 2416 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2417
2418 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2419}
7322fd19 2420EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2421
cbe61d8a 2422bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2423{
63a75b91
SB		 2424 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2425 return false;
2426
2427 ath9k_hw_init_pll(ah, NULL);
2428 return true;
f1dc5600 2429}
7322fd19 2430EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2431
cbe61d8a 2432bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2433{
9ecdef4b 2434 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2435 return false;
f078f209 2436
63a75b91
SB		 2437 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2438 return false;
2439
2440 ath9k_hw_init_pll(ah, NULL);
2441 return true;
f078f209 2442}
7322fd19 2443EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2444
de40f316 2445void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2446{
608b88cb 2447 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2448 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2449 struct ieee80211_channel *channel = chan->chan;
9c204b46
FF		 2450 int reg_pwr = min_t(int, MAX_RATE_POWER, regulatory->power_limit);
2451 int chan_pwr = channel->max_power * 2;
2452
2453 if (test)
2454 reg_pwr = chan_pwr = MAX_RATE_POWER;
f078f209 2455
608b88cb 2456 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2457
8fbff4b8 2458 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2459 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8 2460 channel->max_antenna_gain * 2,
9c204b46 2461 chan_pwr, reg_pwr, test);
6f255425 2462}
7322fd19 2463EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2464
cbe61d8a 2465void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2466{
2660b81a 2467 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2468}
7322fd19 2469EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2470
cbe61d8a 2471void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2472{
f1dc5600
S		 2473 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2474 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2475}
7322fd19 2476EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2477
f2b2143e 2478void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2479{
1510718d
LR		 2480 struct ath_common *common = ath9k_hw_common(ah);
2481
2482 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2483 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2484 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2485}
7322fd19 2486EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2487
1c0fc65e
BP		 2488#define ATH9K_MAX_TSF_READ 10
2489
cbe61d8a 2490u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2491{
1c0fc65e
BP		 2492 u32 tsf_lower, tsf_upper1, tsf_upper2;
2493 int i;
2494
2495 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2496 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2497 tsf_lower = REG_READ(ah, AR_TSF_L32);
2498 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2499 if (tsf_upper2 == tsf_upper1)
2500 break;
2501 tsf_upper1 = tsf_upper2;
2502 }
f078f209 2503
1c0fc65e 2504 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2505
1c0fc65e 2506 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2507}
7322fd19 2508EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2509
cbe61d8a 2510void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2511{
27abe060 2512 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2513 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2514}
7322fd19 2515EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2516
cbe61d8a 2517void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2518{
f9b604f6
GJ		 2519 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2520 AH_TSF_WRITE_TIMEOUT))
226afe68
JP		 2521 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2522 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2523
f1dc5600
S		 2524 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2525}
7322fd19 2526EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2527
54e4cec6 2528void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2529{
f1dc5600 2530 if (setting)
2660b81a 2531 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2532 else
2660b81a 2533 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2534}
7322fd19 2535EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2536
25c56eec 2537void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2538{
25c56eec 2539 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2540 u32 macmode;
2541
25c56eec 2542 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2543 macmode = AR_2040_JOINED_RX_CLEAR;
2544 else
2545 macmode = 0;
f078f209 2546
f1dc5600 2547 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2548}
ff155a45
VT		 2549
2550/* HW Generic timers configuration */
2551
2552static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2553{
2554 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2555 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2556 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2557 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2558 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2559 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2560 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2561 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2562 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2563 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2564 AR_NDP2_TIMER_MODE, 0x0002},
2565 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2566 AR_NDP2_TIMER_MODE, 0x0004},
2567 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2568 AR_NDP2_TIMER_MODE, 0x0008},
2569 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2570 AR_NDP2_TIMER_MODE, 0x0010},
2571 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2572 AR_NDP2_TIMER_MODE, 0x0020},
2573 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2574 AR_NDP2_TIMER_MODE, 0x0040},
2575 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2576 AR_NDP2_TIMER_MODE, 0x0080}
2577};
2578
2579/* HW generic timer primitives */
2580
2581/* compute and clear index of rightmost 1 */
2582static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2583{
2584 u32 b;
2585
2586 b = *mask;
2587 b &= (0-b);
2588 *mask &= ~b;
2589 b *= debruijn32;
2590 b >>= 27;
2591
2592 return timer_table->gen_timer_index[b];
2593}
2594
dd347f2f 2595u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2596{
2597 return REG_READ(ah, AR_TSF_L32);
2598}
dd347f2f 2599EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2600
2601struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2602 void (*trigger)(void *),
2603 void (*overflow)(void *),
2604 void *arg,
2605 u8 timer_index)
2606{
2607 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2608 struct ath_gen_timer *timer;
2609
2610 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2611
2612 if (timer == NULL) {
3800276a
JP		 2613 ath_err(ath9k_hw_common(ah),
2614 "Failed to allocate memory for hw timer[%d]\n",
2615 timer_index);
ff155a45
VT		 2616 return NULL;
2617 }
2618
2619 /* allocate a hardware generic timer slot */
2620 timer_table->timers[timer_index] = timer;
2621 timer->index = timer_index;
2622 timer->trigger = trigger;
2623 timer->overflow = overflow;
2624 timer->arg = arg;
2625
2626 return timer;
2627}
7322fd19 2628EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2629
cd9bf689
LR		 2630void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2631 struct ath_gen_timer *timer,
788f6875 2632 u32 trig_timeout,
cd9bf689 2633 u32 timer_period)
ff155a45
VT		 2634{
2635 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
788f6875 2636 u32 tsf, timer_next;
ff155a45
VT		 2637
2638 BUG_ON(!timer_period);
2639
2640 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2641
2642 tsf = ath9k_hw_gettsf32(ah);
2643
788f6875
VT		 2644 timer_next = tsf + trig_timeout;
2645
226afe68
JP		 2646 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2647 "current tsf %x period %x timer_next %x\n",
2648 tsf, timer_period, timer_next);
ff155a45 2649
ff155a45
VT		 2650 /*
2651 * Program generic timer registers
2652 */
2653 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2654 timer_next);
2655 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2656 timer_period);
2657 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2658 gen_tmr_configuration[timer->index].mode_mask);
2659
2660 /* Enable both trigger and thresh interrupt masks */
2661 REG_SET_BIT(ah, AR_IMR_S5,
2662 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2663 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2664}
7322fd19 2665EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2666
cd9bf689 2667void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2668{
2669 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2670
2671 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2672 (timer->index >= ATH_MAX_GEN_TIMER)) {
2673 return;
2674 }
2675
2676 /* Clear generic timer enable bits. */
2677 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2678 gen_tmr_configuration[timer->index].mode_mask);
2679
2680 /* Disable both trigger and thresh interrupt masks */
2681 REG_CLR_BIT(ah, AR_IMR_S5,
2682 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2683 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2684
2685 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 2686}
7322fd19 2687EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2688
2689void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2690{
2691 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2692
2693 /* free the hardware generic timer slot */
2694 timer_table->timers[timer->index] = NULL;
2695 kfree(timer);
2696}
7322fd19 2697EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2698
2699/*
2700 * Generic Timer Interrupts handling
2701 */
2702void ath_gen_timer_isr(struct ath_hw *ah)
2703{
2704 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2705 struct ath_gen_timer *timer;
c46917bb 2706 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 2707 u32 trigger_mask, thresh_mask, index;
2708
2709 /* get hardware generic timer interrupt status */
2710 trigger_mask = ah->intr_gen_timer_trigger;
2711 thresh_mask = ah->intr_gen_timer_thresh;
2712 trigger_mask &= timer_table->timer_mask.val;
2713 thresh_mask &= timer_table->timer_mask.val;
2714
2715 trigger_mask &= ~thresh_mask;
2716
2717 while (thresh_mask) {
2718 index = rightmost_index(timer_table, &thresh_mask);
2719 timer = timer_table->timers[index];
2720 BUG_ON(!timer);
226afe68
JP		 2721 ath_dbg(common, ATH_DBG_HWTIMER,
2722 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 2723 timer->overflow(timer->arg);
2724 }
2725
2726 while (trigger_mask) {
2727 index = rightmost_index(timer_table, &trigger_mask);
2728 timer = timer_table->timers[index];
2729 BUG_ON(!timer);
226afe68
JP		 2730 ath_dbg(common, ATH_DBG_HWTIMER,
2731 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 2732 timer->trigger(timer->arg);
2733 }
2734}
7322fd19 2735EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2736
05020d23
S		 2737/********/
2738/* HTC */
2739/********/
2740
2741void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2742{
2743 ah->htc_reset_init = true;
2744}
2745EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2746
2da4f01a
LR		 2747static struct {
2748 u32 version;
2749 const char * name;
2750} ath_mac_bb_names[] = {
2751 /* Devices with external radios */
2752 { AR_SREV_VERSION_5416_PCI, "5416" },
2753 { AR_SREV_VERSION_5416_PCIE, "5418" },
2754 { AR_SREV_VERSION_9100, "9100" },
2755 { AR_SREV_VERSION_9160, "9160" },
2756 /* Single-chip solutions */
2757 { AR_SREV_VERSION_9280, "9280" },
2758 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 2759 { AR_SREV_VERSION_9287, "9287" },
2760 { AR_SREV_VERSION_9271, "9271" },
ec83903e 2761 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 2762 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 2763 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 2764 { AR_SREV_VERSION_9485, "9485" },
2da4f01a
LR		 2765};
2766
2767/* For devices with external radios */
2768static struct {
2769 u16 version;
2770 const char * name;
2771} ath_rf_names[] = {
2772 { 0, "5133" },
2773 { AR_RAD5133_SREV_MAJOR, "5133" },
2774 { AR_RAD5122_SREV_MAJOR, "5122" },
2775 { AR_RAD2133_SREV_MAJOR, "2133" },
2776 { AR_RAD2122_SREV_MAJOR, "2122" }
2777};
2778
2779/*
2780 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2781 */
f934c4d9 2782static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 2783{
2784 int i;
2785
2786 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2787 if (ath_mac_bb_names[i].version == mac_bb_version) {
2788 return ath_mac_bb_names[i].name;
2789 }
2790 }
2791
2792 return "????";
2793}
2da4f01a
LR		 2794
2795/*
2796 * Return the RF name. "????" is returned if the RF is unknown.
2797 * Used for devices with external radios.
2798 */
f934c4d9 2799static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 2800{
2801 int i;
2802
2803 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2804 if (ath_rf_names[i].version == rf_version) {
2805 return ath_rf_names[i].name;
2806 }
2807 }
2808
2809 return "????";
2810}
f934c4d9
LR		 2811
2812void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2813{
2814 int used;
2815
2816 /* chipsets >= AR9280 are single-chip */
7a37081e 2817 if (AR_SREV_9280_20_OR_LATER(ah)) {
f934c4d9
LR		 2818 used = snprintf(hw_name, len,
2819 "Atheros AR%s Rev:%x",
2820 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2821 ah->hw_version.macRev);
2822 }
2823 else {
2824 used = snprintf(hw_name, len,
2825 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2826 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2827 ah->hw_version.macRev,
2828 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2829 AR_RADIO_SREV_MAJOR)),
2830 ah->hw_version.phyRev);
2831 }
2832
2833 hw_name[used] = '\0';
2834}
2835EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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