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Merge branch 'for-davem' into for-next
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
5ca06ebe 22#include <linux/etherdevice.h>
f078f209
LR		 23#include <asm/unaligned.h>
24
af03abec 25#include "hw.h"
d70357d5 26#include "hw-ops.h"
b622a720 27#include "ar9003_mac.h"
f4701b5a 28#include "ar9003_mci.h"
362cd03f 29#include "ar9003_phy.h"
462e58f2 30#include "ath9k.h"
f078f209 31
cbe61d8a 32static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 33
7322fd19
LR		 34MODULE_AUTHOR("Atheros Communications");
35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37MODULE_LICENSE("Dual BSD/GPL");
38
dfdac8ac 39static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 40{
dfdac8ac 41 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 42 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 43 unsigned int clockrate;
cbe61d8a 44
087b6ff6
FF		 45 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
46 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
47 clockrate = 117;
e4744ec7 48 else if (!chan) /* should really check for CCK instead */
dfdac8ac 49 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 50 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 51 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
52 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
53 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 54 else
dfdac8ac
FF		 55 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
56
beae416b
MN		 57 if (chan) {
58 if (IS_CHAN_HT40(chan))
59 clockrate *= 2;
e4744ec7 60 if (IS_CHAN_HALF_RATE(chan))
906c7205 61 clockrate /= 2;
e4744ec7 62 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 63 clockrate /= 4;
64 }
65
dfdac8ac 66 common->clockrate = clockrate;
f1dc5600
S		 67}
68
cbe61d8a 69static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 70{
dfdac8ac 71 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 72
dfdac8ac 73 return usecs * common->clockrate;
f1dc5600 74}
f078f209 75
0caa7b14 76bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 77{
78 int i;
79
0caa7b14
S		 80 BUG_ON(timeout < AH_TIME_QUANTUM);
81
82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 83 if ((REG_READ(ah, reg) & mask) == val)
84 return true;
85
86 udelay(AH_TIME_QUANTUM);
87 }
04bd4638 88
d2182b69 89 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 92
f1dc5600 93 return false;
f078f209 94}
7322fd19 95EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 96
7c5adc8d
FF		 97void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
98 int hw_delay)
99{
1a5e6326 100 hw_delay /= 10;
7c5adc8d
FF		 101
102 if (IS_CHAN_HALF_RATE(chan))
103 hw_delay *= 2;
104 else if (IS_CHAN_QUARTER_RATE(chan))
105 hw_delay *= 4;
106
107 udelay(hw_delay + BASE_ACTIVATE_DELAY);
108}
109
0166b4be 110void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 111 int column, unsigned int *writecnt)
112{
113 int r;
114
115 ENABLE_REGWRITE_BUFFER(ah);
116 for (r = 0; r < array->ia_rows; r++) {
117 REG_WRITE(ah, INI_RA(array, r, 0),
118 INI_RA(array, r, column));
119 DO_DELAY(*writecnt);
120 }
121 REGWRITE_BUFFER_FLUSH(ah);
122}
123
a57cb45a
OR		 124void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
125{
126 u32 *tmp_reg_list, *tmp_data;
127 int i;
128
129 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL);
130 if (!tmp_reg_list) {
131 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
132 return;
133 }
134
135 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL);
136 if (!tmp_data) {
137 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
138 goto error_tmp_data;
139 }
140
141 for (i = 0; i < size; i++)
142 tmp_reg_list[i] = array[i][0];
143
144 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
145
146 for (i = 0; i < size; i++)
147 array[i][1] = tmp_data[i];
148
149 kfree(tmp_data);
150error_tmp_data:
151 kfree(tmp_reg_list);
152}
153
f078f209
LR		 154u32 ath9k_hw_reverse_bits(u32 val, u32 n)
155{
156 u32 retval;
157 int i;
158
159 for (i = 0, retval = 0; i < n; i++) {
160 retval = (retval << 1) | (val & 1);
161 val >>= 1;
162 }
163 return retval;
164}
165
cbe61d8a 166u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 167 u8 phy, int kbps,
f1dc5600
S		 168 u32 frameLen, u16 rateix,
169 bool shortPreamble)
f078f209 170{
f1dc5600 171 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 172
f1dc5600
S		 173 if (kbps == 0)
174 return 0;
f078f209 175
545750d3 176 switch (phy) {
46d14a58 177 case WLAN_RC_PHY_CCK:
f1dc5600 178 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 179 if (shortPreamble)
f1dc5600
S		 180 phyTime >>= 1;
181 numBits = frameLen << 3;
182 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
183 break;
46d14a58 184 case WLAN_RC_PHY_OFDM:
2660b81a 185 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 186 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
187 numBits = OFDM_PLCP_BITS + (frameLen << 3);
188 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
189 txTime = OFDM_SIFS_TIME_QUARTER
190 + OFDM_PREAMBLE_TIME_QUARTER
191 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 192 } else if (ah->curchan &&
193 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 194 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
195 numBits = OFDM_PLCP_BITS + (frameLen << 3);
196 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
197 txTime = OFDM_SIFS_TIME_HALF +
198 OFDM_PREAMBLE_TIME_HALF
199 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
200 } else {
201 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
202 numBits = OFDM_PLCP_BITS + (frameLen << 3);
203 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
204 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
205 + (numSymbols * OFDM_SYMBOL_TIME);
206 }
207 break;
208 default:
3800276a
JP		 209 ath_err(ath9k_hw_common(ah),
210 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 211 txTime = 0;
212 break;
213 }
f078f209 214
f1dc5600
S		 215 return txTime;
216}
7322fd19 217EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 218
cbe61d8a 219void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 220 struct ath9k_channel *chan,
221 struct chan_centers *centers)
f078f209 222{
f1dc5600 223 int8_t extoff;
f078f209 224
f1dc5600
S		 225 if (!IS_CHAN_HT40(chan)) {
226 centers->ctl_center = centers->ext_center =
227 centers->synth_center = chan->channel;
228 return;
f078f209 229 }
f078f209 230
8896934c 231 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 232 centers->synth_center =
233 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
234 extoff = 1;
235 } else {
236 centers->synth_center =
237 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
238 extoff = -1;
239 }
f078f209 240
f1dc5600
S		 241 centers->ctl_center =
242 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 243 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 244 centers->ext_center =
6420014c 245 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 246}
247
f1dc5600
S		 248/******************/
249/* Chip Revisions */
250/******************/
251
cbe61d8a 252static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 253{
f1dc5600 254 u32 val;
f078f209 255
09c74f7b
FF		 256 if (ah->get_mac_revision)
257 ah->hw_version.macRev = ah->get_mac_revision();
258
ecb1d385
VT		 259 switch (ah->hw_version.devid) {
260 case AR5416_AR9100_DEVID:
261 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
262 break;
3762561a
GJ		 263 case AR9300_DEVID_AR9330:
264 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
09c74f7b 265 if (!ah->get_mac_revision) {
3762561a
GJ		 266 val = REG_READ(ah, AR_SREV);
267 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
268 }
269 return;
ecb1d385
VT		 270 case AR9300_DEVID_AR9340:
271 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
ecb1d385 272 return;
813831dc
GJ		 273 case AR9300_DEVID_QCA955X:
274 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
275 return;
e6b1e46e
SM		 276 case AR9300_DEVID_AR953X:
277 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
278 return;
2131fabb
MP		 279 case AR9300_DEVID_QCA956X:
280 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
ecb1d385
VT		 281 }
282
f1dc5600 283 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 284
f1dc5600
S		 285 if (val == 0xFF) {
286 val = REG_READ(ah, AR_SREV);
d535a42a
S		 287 ah->hw_version.macVersion =
288 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
289 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 290
77fac465 291 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 292 ah->is_pciexpress = true;
293 else
294 ah->is_pciexpress = (val &
295 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 296 } else {
297 if (!AR_SREV_9100(ah))
d535a42a 298 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 299
d535a42a 300 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 301
d535a42a 302 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 303 ah->is_pciexpress = true;
f1dc5600 304 }
f078f209
LR		 305}
306
f1dc5600
S		 307/************************************/
308/* HW Attach, Detach, Init Routines */
309/************************************/
310
cbe61d8a 311static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 312{
040b74f7 313 if (!AR_SREV_5416(ah))
f1dc5600 314 return;
f078f209 315
f1dc5600
S		 316 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
323 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 325
f1dc5600 326 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 327}
328
1f3f0618 329/* This should work for all families including legacy */
cbe61d8a 330static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 331{
c46917bb 332 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 333 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 334 u32 regHold[2];
07b2fa5a
JP		 335 static const u32 patternData[4] = {
336 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
337 };
1f3f0618 338 int i, j, loop_max;
f078f209 339
1f3f0618
SB		 340 if (!AR_SREV_9300_20_OR_LATER(ah)) {
341 loop_max = 2;
342 regAddr[1] = AR_PHY_BASE + (8 << 2);
343 } else
344 loop_max = 1;
345
346 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 347 u32 addr = regAddr[i];
348 u32 wrData, rdData;
f078f209 349
f1dc5600
S		 350 regHold[i] = REG_READ(ah, addr);
351 for (j = 0; j < 0x100; j++) {
352 wrData = (j << 16) | j;
353 REG_WRITE(ah, addr, wrData);
354 rdData = REG_READ(ah, addr);
355 if (rdData != wrData) {
3800276a
JP		 356 ath_err(common,
357 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
358 addr, wrData, rdData);
f1dc5600
S		 359 return false;
360 }
361 }
362 for (j = 0; j < 4; j++) {
363 wrData = patternData[j];
364 REG_WRITE(ah, addr, wrData);
365 rdData = REG_READ(ah, addr);
366 if (wrData != rdData) {
3800276a
JP		 367 ath_err(common,
368 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
369 addr, wrData, rdData);
f1dc5600
S		 370 return false;
371 }
f078f209 372 }
f1dc5600 373 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 374 }
f1dc5600 375 udelay(100);
cbe61d8a 376
f078f209
LR		 377 return true;
378}
379
b8b0f377 380static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 381{
f57cf939
SM		 382 struct ath_common *common = ath9k_hw_common(ah);
383
689e756f
FF		 384 ah->config.dma_beacon_response_time = 1;
385 ah->config.sw_beacon_response_time = 6;
2660b81a 386 ah->config.cwm_ignore_extcca = 0;
2660b81a 387 ah->config.analog_shiftreg = 1;
f078f209 388
0ce024cb 389 ah->config.rx_intr_mitigation = true;
6158425b 390
a64e1a45
SM		 391 if (AR_SREV_9300_20_OR_LATER(ah)) {
392 ah->config.rimt_last = 500;
393 ah->config.rimt_first = 2000;
394 } else {
395 ah->config.rimt_last = 250;
396 ah->config.rimt_first = 700;
397 }
398
656cd75c
SM		 399 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
400 ah->config.pll_pwrsave = 7;
401
6158425b
LR		 402 /*
403 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
404 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
405 * This means we use it for all AR5416 devices, and the few
406 * minor PCI AR9280 devices out there.
407 *
408 * Serialization is required because these devices do not handle
409 * well the case of two concurrent reads/writes due to the latency
410 * involved. During one read/write another read/write can be issued
411 * on another CPU while the previous read/write may still be working
412 * on our hardware, if we hit this case the hardware poops in a loop.
413 * We prevent this by serializing reads and writes.
414 *
415 * This issue is not present on PCI-Express devices or pre-AR5416
416 * devices (legacy, 802.11abg).
417 */
418 if (num_possible_cpus() > 1)
2d6a5e95 419 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f57cf939
SM		 420
421 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
422 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
423 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
424 !ah->is_pciexpress)) {
425 ah->config.serialize_regmode = SER_REG_MODE_ON;
426 } else {
427 ah->config.serialize_regmode = SER_REG_MODE_OFF;
428 }
429 }
430
431 ath_dbg(common, RESET, "serialize_regmode is %d\n",
432 ah->config.serialize_regmode);
433
434 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
435 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
436 else
437 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
f078f209
LR		 438}
439
50aca25b 440static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 441{
608b88cb
LR		 442 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
443
444 regulatory->country_code = CTRY_DEFAULT;
445 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 446
d535a42a 447 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 448 ah->hw_version.subvendorid = 0;
f078f209 449
f57cf939
SM		 450 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
451 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 452 if (AR_SREV_9100(ah))
453 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
f57cf939 454
e3f2acc7 455 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 456 ah->globaltxtimeout = (u32) -1;
cbdec975 457 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 458 ah->htc_reset_init = true;
f57cf939 459
c09396eb 460 ah->tpc_enabled = false;
a9abe302 461
f57cf939
SM		 462 ah->ani_function = ATH9K_ANI_ALL;
463 if (!AR_SREV_9300_20_OR_LATER(ah))
464 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
465
466 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
467 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
468 else
469 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209
LR		 470}
471
cbe61d8a 472static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 473{
1510718d 474 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 475 u32 sum;
476 int i;
477 u16 eeval;
07b2fa5a 478 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 479
480 sum = 0;
481 for (i = 0; i < 3; i++) {
49101676 482 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 483 sum += eeval;
1510718d
LR		 484 common->macaddr[2 * i] = eeval >> 8;
485 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 486 }
5ca06ebe
FF		 487 if (!is_valid_ether_addr(common->macaddr)) {
488 ath_err(common,
489 "eeprom contains invalid mac address: %pM\n",
490 common->macaddr);
491
492 random_ether_addr(common->macaddr);
493 ath_err(common,
494 "random mac address will be used: %pM\n",
495 common->macaddr);
496 }
f078f209
LR		 497
498 return 0;
499}
500
f637cfd6 501static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 502{
6cae913d 503 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 504 int ecode;
f078f209 505
6cae913d 506 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 507 if (!ath9k_hw_chip_test(ah))
508 return -ENODEV;
509 }
f078f209 510
ebd5a14a
LR		 511 if (!AR_SREV_9300_20_OR_LATER(ah)) {
512 ecode = ar9002_hw_rf_claim(ah);
513 if (ecode != 0)
514 return ecode;
515 }
f078f209 516
f637cfd6 517 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 518 if (ecode != 0)
519 return ecode;
7d01b221 520
d2182b69 521 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 522 ah->eep_ops->get_eeprom_ver(ah),
523 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 524
e323300d 525 ath9k_hw_ani_init(ah);
f078f209 526
d3b371cb
SM		 527 /*
528 * EEPROM needs to be initialized before we do this.
529 * This is required for regulatory compliance.
530 */
0c7c2bb4 531 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 532 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
533 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 534 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
535 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 536 }
537 }
538
f078f209
LR		 539 return 0;
540}
541
c1b976d2 542static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 543{
c1b976d2
FF		 544 if (!AR_SREV_9300_20_OR_LATER(ah))
545 return ar9002_hw_attach_ops(ah);
546
547 ar9003_hw_attach_ops(ah);
548 return 0;
aa4058ae
LR		 549}
550
d70357d5
LR		 551/* Called for all hardware families */
552static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 553{
c46917bb 554 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 555 int r = 0;
aa4058ae 556
ac45c12d
SB		 557 ath9k_hw_read_revisions(ah);
558
de82582b
SM		 559 switch (ah->hw_version.macVersion) {
560 case AR_SREV_VERSION_5416_PCI:
561 case AR_SREV_VERSION_5416_PCIE:
562 case AR_SREV_VERSION_9160:
563 case AR_SREV_VERSION_9100:
564 case AR_SREV_VERSION_9280:
565 case AR_SREV_VERSION_9285:
566 case AR_SREV_VERSION_9287:
567 case AR_SREV_VERSION_9271:
568 case AR_SREV_VERSION_9300:
569 case AR_SREV_VERSION_9330:
570 case AR_SREV_VERSION_9485:
571 case AR_SREV_VERSION_9340:
572 case AR_SREV_VERSION_9462:
573 case AR_SREV_VERSION_9550:
574 case AR_SREV_VERSION_9565:
e6b1e46e 575 case AR_SREV_VERSION_9531:
2131fabb 576 case AR_SREV_VERSION_9561:
de82582b
SM		 577 break;
578 default:
579 ath_err(common,
580 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
581 ah->hw_version.macVersion, ah->hw_version.macRev);
582 return -EOPNOTSUPP;
583 }
584
0a8d7cb0
SB		 585 /*
586 * Read back AR_WA into a permanent copy and set bits 14 and 17.
587 * We need to do this to avoid RMW of this register. We cannot
588 * read the reg when chip is asleep.
589 */
27251e00
SM		 590 if (AR_SREV_9300_20_OR_LATER(ah)) {
591 ah->WARegVal = REG_READ(ah, AR_WA);
592 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
593 AR_WA_ASPM_TIMER_BASED_DISABLE);
594 }
0a8d7cb0 595
aa4058ae 596 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 597 ath_err(common, "Couldn't reset chip\n");
95fafca2 598 return -EIO;
aa4058ae
LR		 599 }
600
a4a2954f
SM		 601 if (AR_SREV_9565(ah)) {
602 ah->WARegVal |= AR_WA_BIT22;
603 REG_WRITE(ah, AR_WA, ah->WARegVal);
604 }
605
bab1f62e
LR		 606 ath9k_hw_init_defaults(ah);
607 ath9k_hw_init_config(ah);
608
c1b976d2
FF		 609 r = ath9k_hw_attach_ops(ah);
610 if (r)
611 return r;
d70357d5 612
9ecdef4b 613 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 614 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 615 return -EIO;
aa4058ae
LR		 616 }
617
2c8e5937 618 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 619 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 620 ah->is_pciexpress = false;
621
aa4058ae 622 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 623 ath9k_hw_init_cal_settings(ah);
624
69ce674b 625 if (!ah->is_pciexpress)
aa4058ae
LR		 626 ath9k_hw_disablepcie(ah);
627
f637cfd6 628 r = ath9k_hw_post_init(ah);
aa4058ae 629 if (r)
95fafca2 630 return r;
aa4058ae
LR		 631
632 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 633 r = ath9k_hw_fill_cap_info(ah);
634 if (r)
635 return r;
636
4f3acf81
LR		 637 r = ath9k_hw_init_macaddr(ah);
638 if (r) {
3800276a 639 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 640 return r;
f078f209
LR		 641 }
642
4598702d 643 ath9k_hw_init_hang_checks(ah);
f078f209 644
211f5859
LR		 645 common->state = ATH_HW_INITIALIZED;
646
4f3acf81 647 return 0;
f078f209
LR		 648}
649
d70357d5 650int ath9k_hw_init(struct ath_hw *ah)
f078f209 651{
d70357d5
LR		 652 int ret;
653 struct ath_common *common = ath9k_hw_common(ah);
f078f209 654
77fac465 655 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 656 switch (ah->hw_version.devid) {
657 case AR5416_DEVID_PCI:
658 case AR5416_DEVID_PCIE:
659 case AR5416_AR9100_DEVID:
660 case AR9160_DEVID_PCI:
661 case AR9280_DEVID_PCI:
662 case AR9280_DEVID_PCIE:
663 case AR9285_DEVID_PCIE:
db3cc53a
SB		 664 case AR9287_DEVID_PCI:
665 case AR9287_DEVID_PCIE:
d70357d5 666 case AR2427_DEVID_PCIE:
db3cc53a 667 case AR9300_DEVID_PCIE:
3050c914 668 case AR9300_DEVID_AR9485_PCIE:
999a7a88 669 case AR9300_DEVID_AR9330:
bca04689 670 case AR9300_DEVID_AR9340:
2b943a33 671 case AR9300_DEVID_QCA955X:
5a63ef0f 672 case AR9300_DEVID_AR9580:
423e38e8 673 case AR9300_DEVID_AR9462:
d4e5979c 674 case AR9485_DEVID_AR1111:
77fac465 675 case AR9300_DEVID_AR9565:
e6b1e46e 676 case AR9300_DEVID_AR953X:
2131fabb 677 case AR9300_DEVID_QCA956X:
d70357d5
LR		 678 break;
679 default:
680 if (common->bus_ops->ath_bus_type == ATH_USB)
681 break;
3800276a
JP		 682 ath_err(common, "Hardware device ID 0x%04x not supported\n",
683 ah->hw_version.devid);
d70357d5
LR		 684 return -EOPNOTSUPP;
685 }
f078f209 686
d70357d5
LR		 687 ret = __ath9k_hw_init(ah);
688 if (ret) {
3800276a
JP		 689 ath_err(common,
690 "Unable to initialize hardware; initialization status: %d\n",
691 ret);
d70357d5
LR		 692 return ret;
693 }
f078f209 694
c774d57f
LB		 695 ath_dynack_init(ah);
696
d70357d5 697 return 0;
f078f209 698}
d70357d5 699EXPORT_SYMBOL(ath9k_hw_init);
f078f209 700
cbe61d8a 701static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 702{
7d0d0df0
S		 703 ENABLE_REGWRITE_BUFFER(ah);
704
f1dc5600
S		 705 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
706 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 707
f1dc5600
S		 708 REG_WRITE(ah, AR_QOS_NO_ACK,
709 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
710 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
711 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
712
713 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
714 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
715 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
716 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
717 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 718
719 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 720}
721
b84628eb 722u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 723{
f18e3c6b
MSS		 724 struct ath_common *common = ath9k_hw_common(ah);
725 int i = 0;
726
ca7a4deb
FF		 727 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
728 udelay(100);
729 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 730
f18e3c6b
MSS		 731 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
732
ca7a4deb 733 udelay(100);
b1415819 734
f18e3c6b
MSS		 735 if (WARN_ON_ONCE(i >= 100)) {
736 ath_err(common, "PLL4 meaurement not done\n");
737 break;
738 }
739
740 i++;
741 }
742
ca7a4deb 743 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 744}
745EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
746
cbe61d8a 747static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 748 struct ath9k_channel *chan)
f078f209 749{
d09b17f7
VT		 750 u32 pll;
751
5fb9b1b9
FF		 752 pll = ath9k_hw_compute_pll_control(ah, chan);
753
a4a2954f 754 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 755 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
757 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
759 AR_CH0_DPLL2_KD, 0x40);
760 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
761 AR_CH0_DPLL2_KI, 0x4);
22983c30 762
3dfd7f60
VT		 763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
764 AR_CH0_BB_DPLL1_REFDIV, 0x5);
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
766 AR_CH0_BB_DPLL1_NINI, 0x58);
767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
768 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 769
770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 771 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
773 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 775 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 776
3dfd7f60 777 /* program BB PLL phase_shift to 0x6 */
22983c30 778 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 779 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
780
781 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
782 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 783 udelay(1000);
a5415d62
GJ		 784 } else if (AR_SREV_9330(ah)) {
785 u32 ddr_dpll2, pll_control2, kd;
786
787 if (ah->is_clk_25mhz) {
788 ddr_dpll2 = 0x18e82f01;
789 pll_control2 = 0xe04a3d;
790 kd = 0x1d;
791 } else {
792 ddr_dpll2 = 0x19e82f01;
793 pll_control2 = 0x886666;
794 kd = 0x3d;
795 }
796
797 /* program DDR PLL ki and kd value */
798 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
799
800 /* program DDR PLL phase_shift */
801 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
802 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
803
5fb9b1b9
FF		 804 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
805 pll | AR_RTC_9300_PLL_BYPASS);
a5415d62
GJ		 806 udelay(1000);
807
808 /* program refdiv, nint, frac to RTC register */
809 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
810
811 /* program BB PLL kd and ki value */
812 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
814
815 /* program BB PLL phase_shift */
816 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
817 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
ede6a5e7
MP		 818 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
819 AR_SREV_9561(ah)) {
0b488ac6
VT		 820 u32 regval, pll2_divint, pll2_divfrac, refdiv;
821
5fb9b1b9
FF		 822 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
823 pll | AR_RTC_9300_SOC_PLL_BYPASS);
0b488ac6
VT		 824 udelay(1000);
825
826 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
827 udelay(100);
828
829 if (ah->is_clk_25mhz) {
ede6a5e7 830 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
2c323058
SM		 831 pll2_divint = 0x1c;
832 pll2_divfrac = 0xa3d2;
833 refdiv = 1;
834 } else {
835 pll2_divint = 0x54;
836 pll2_divfrac = 0x1eb85;
837 refdiv = 3;
838 }
0b488ac6 839 } else {
fc05a317
GJ		 840 if (AR_SREV_9340(ah)) {
841 pll2_divint = 88;
842 pll2_divfrac = 0;
843 refdiv = 5;
844 } else {
845 pll2_divint = 0x11;
ede6a5e7
MP		 846 pll2_divfrac = (AR_SREV_9531(ah) ||
847 AR_SREV_9561(ah)) ?
848 0x26665 : 0x26666;
fc05a317
GJ		 849 refdiv = 1;
850 }
0b488ac6
VT		 851 }
852
853 regval = REG_READ(ah, AR_PHY_PLL_MODE);
ede6a5e7 854 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
2c323058
SM		 855 regval |= (0x1 << 22);
856 else
857 regval |= (0x1 << 16);
0b488ac6
VT		 858 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
859 udelay(100);
860
861 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
862 (pll2_divint << 18) | pll2_divfrac);
863 udelay(100);
864
865 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317 866 if (AR_SREV_9340(ah))
2c323058
SM		 867 regval = (regval & 0x80071fff) |
868 (0x1 << 30) |
869 (0x1 << 13) |
870 (0x4 << 26) |
871 (0x18 << 19);
ede6a5e7 872 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
2c323058
SM		 873 regval = (regval & 0x01c00fff) |
874 (0x1 << 31) |
875 (0x2 << 29) |
876 (0xa << 25) |
ede6a5e7
MP		 877 (0x1 << 19);
878
879 if (AR_SREV_9531(ah))
880 regval |= (0x6 << 12);
881 } else
2c323058
SM		 882 regval = (regval & 0x80071fff) |
883 (0x3 << 30) |
884 (0x1 << 13) |
885 (0x4 << 26) |
886 (0x60 << 19);
0b488ac6 887 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
2c323058 888
ede6a5e7 889 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
2c323058
SM		 890 REG_WRITE(ah, AR_PHY_PLL_MODE,
891 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
892 else
893 REG_WRITE(ah, AR_PHY_PLL_MODE,
894 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
895
0b488ac6 896 udelay(1000);
22983c30 897 }
d09b17f7 898
8565f8bf
SM		 899 if (AR_SREV_9565(ah))
900 pll |= 0x40000;
d03a66c1 901 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 902
fc05a317
GJ		 903 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
904 AR_SREV_9550(ah))
3dfd7f60
VT		 905 udelay(1000);
906
c75724d1
LR		 907 /* Switch the core clock for ar9271 to 117Mhz */
908 if (AR_SREV_9271(ah)) {
25e2ab17
S		 909 udelay(500);
910 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 911 }
912
f1dc5600
S		 913 udelay(RTC_PLL_SETTLE_DELAY);
914
915 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 916}
917
cbe61d8a 918static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 919 enum nl80211_iftype opmode)
f078f209 920{
79d1d2b8 921 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 922 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 923 AR_IMR_TXURN |
924 AR_IMR_RXERR |
925 AR_IMR_RXORN |
926 AR_IMR_BCNMISC;
f078f209 927
ede6a5e7
MP		 928 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
929 AR_SREV_9561(ah))
79d1d2b8
VT		 930 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
931
66860240
VT		 932 if (AR_SREV_9300_20_OR_LATER(ah)) {
933 imr_reg |= AR_IMR_RXOK_HP;
934 if (ah->config.rx_intr_mitigation)
935 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
936 else
937 imr_reg |= AR_IMR_RXOK_LP;
f078f209 938
66860240
VT		 939 } else {
940 if (ah->config.rx_intr_mitigation)
941 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
942 else
943 imr_reg |= AR_IMR_RXOK;
944 }
f078f209 945
66860240
VT		 946 if (ah->config.tx_intr_mitigation)
947 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
948 else
949 imr_reg |= AR_IMR_TXOK;
f078f209 950
7d0d0df0
S		 951 ENABLE_REGWRITE_BUFFER(ah);
952
152d530d 953 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 954 ah->imrs2_reg |= AR_IMR_S2_GTT;
955 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 956
f1dc5600
S		 957 if (!AR_SREV_9100(ah)) {
958 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 959 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 960 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
961 }
66860240 962
7d0d0df0 963 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 964
66860240
VT		 965 if (AR_SREV_9300_20_OR_LATER(ah)) {
966 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
967 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
968 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
969 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
970 }
f078f209
LR		 971}
972
b6ba41bb
FF		 973static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
974{
975 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
976 val = min(val, (u32) 0xFFFF);
977 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
978}
979
8e15e094 980void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 981{
0005baf4
FF		 982 u32 val = ath9k_hw_mac_to_clks(ah, us);
983 val = min(val, (u32) 0xFFFF);
984 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 985}
986
8e15e094 987void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 988{
0005baf4
FF		 989 u32 val = ath9k_hw_mac_to_clks(ah, us);
990 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
991 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
992}
993
8e15e094 994void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
0005baf4
FF		 995{
996 u32 val = ath9k_hw_mac_to_clks(ah, us);
997 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
998 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 999}
f1dc5600 1000
cbe61d8a 1001static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1002{
f078f209 1003 if (tu > 0xFFFF) {
d2182b69
JP		 1004 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1005 tu);
2660b81a 1006 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1007 return false;
1008 } else {
1009 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1010 ah->globaltxtimeout = tu;
f078f209
LR		 1011 return true;
1012 }
1013}
1014
0005baf4 1015void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1016{
b6ba41bb 1017 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 1018 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 1019 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 1020 int slottime;
0005baf4 1021 int sifstime;
b6ba41bb
FF		 1022 int rx_lat = 0, tx_lat = 0, eifs = 0;
1023 u32 reg;
0005baf4 1024
d2182b69 1025 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1026 ah->misc_mode);
f078f209 1027
b6ba41bb
FF		 1028 if (!chan)
1029 return;
1030
2660b81a 1031 if (ah->misc_mode != 0)
ca7a4deb 1032 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1033
81a91d57
RM		 1034 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1035 rx_lat = 41;
1036 else
1037 rx_lat = 37;
b6ba41bb
FF		 1038 tx_lat = 54;
1039
e88e4861
FF		 1040 if (IS_CHAN_5GHZ(chan))
1041 sifstime = 16;
1042 else
1043 sifstime = 10;
1044
b6ba41bb
FF		 1045 if (IS_CHAN_HALF_RATE(chan)) {
1046 eifs = 175;
1047 rx_lat *= 2;
1048 tx_lat *= 2;
1049 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1050 tx_lat += 11;
1051
92367fe7 1052 sifstime = 32;
e115b7ec 1053 ack_offset = 16;
b6ba41bb 1054 slottime = 13;
b6ba41bb
FF		 1055 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1056 eifs = 340;
81a91d57 1057 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1058 tx_lat *= 4;
1059 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1060 tx_lat += 22;
1061
92367fe7 1062 sifstime = 64;
e115b7ec 1063 ack_offset = 32;
b6ba41bb 1064 slottime = 21;
b6ba41bb 1065 } else {
a7be039d
RM		 1066 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1067 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1068 reg = AR_USEC_ASYNC_FIFO;
1069 } else {
1070 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1071 common->clockrate;
1072 reg = REG_READ(ah, AR_USEC);
1073 }
b6ba41bb
FF		 1074 rx_lat = MS(reg, AR_USEC_RX_LAT);
1075 tx_lat = MS(reg, AR_USEC_TX_LAT);
1076
1077 slottime = ah->slottime;
b6ba41bb 1078 }
0005baf4 1079
e239d859 1080 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1081 slottime += 3 * ah->coverage_class;
1082 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1083 ctstimeout = acktimeout;
42c4568a
FF		 1084
1085 /*
1086 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1087 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1088 * This was initially only meant to work around an issue with delayed
1089 * BA frames in some implementations, but it has been found to fix ACK
1090 * timeout issues in other cases as well.
1091 */
e4744ec7 1092 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1093 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1094 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1095 ctstimeout += 48 - sifstime - ah->slottime;
1096 }
1097
7aefa8aa
LB		 1098 if (ah->dynack.enabled) {
1099 acktimeout = ah->dynack.ackto;
1100 ctstimeout = acktimeout;
1101 slottime = (acktimeout - 3) / 2;
1102 } else {
1103 ah->dynack.ackto = acktimeout;
1104 }
1105
b6ba41bb
FF		 1106 ath9k_hw_set_sifs_time(ah, sifstime);
1107 ath9k_hw_setslottime(ah, slottime);
0005baf4 1108 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1109 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1110 if (ah->globaltxtimeout != (u32) -1)
1111 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1112
1113 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1114 REG_RMW(ah, AR_USEC,
1115 (common->clockrate - 1) |
1116 SM(rx_lat, AR_USEC_RX_LAT) |
1117 SM(tx_lat, AR_USEC_TX_LAT),
1118 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1119
f1dc5600 1120}
0005baf4 1121EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1122
285f2dda 1123void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1124{
211f5859
LR		 1125 struct ath_common *common = ath9k_hw_common(ah);
1126
736b3a27 1127 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1128 return;
211f5859 1129
9ecdef4b 1130 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1131}
285f2dda 1132EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1133
f1dc5600
S		 1134/*******/
1135/* INI */
1136/*******/
1137
8fe65368 1138u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1139{
1140 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1141
6b21fd20 1142 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1143 ctl |= CTL_11G;
1144 else
1145 ctl |= CTL_11A;
1146
1147 return ctl;
1148}
1149
f1dc5600
S		 1150/****************************************/
1151/* Reset and Channel Switching Routines */
1152/****************************************/
f1dc5600 1153
cbe61d8a 1154static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1155{
57b32227 1156 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1157 int txbuf_size;
f1dc5600 1158
7d0d0df0
S		 1159 ENABLE_REGWRITE_BUFFER(ah);
1160
d7e7d229
LR		 1161 /*
1162 * set AHB_MODE not to do cacheline prefetches
1163 */
ca7a4deb
FF		 1164 if (!AR_SREV_9300_20_OR_LATER(ah))
1165 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1166
d7e7d229
LR		 1167 /*
1168 * let mac dma reads be in 128 byte chunks
1169 */
ca7a4deb 1170 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1171
7d0d0df0 1172 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1173
d7e7d229
LR		 1174 /*
1175 * Restore TX Trigger Level to its pre-reset value.
1176 * The initial value depends on whether aggregation is enabled, and is
1177 * adjusted whenever underruns are detected.
1178 */
57b32227
FF		 1179 if (!AR_SREV_9300_20_OR_LATER(ah))
1180 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1181
7d0d0df0 1182 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1183
d7e7d229
LR		 1184 /*
1185 * let mac dma writes be in 128 byte chunks
1186 */
ca7a4deb 1187 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1188
d7e7d229
LR		 1189 /*
1190 * Setup receive FIFO threshold to hold off TX activities
1191 */
f1dc5600
S		 1192 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1193
57b32227
FF		 1194 if (AR_SREV_9300_20_OR_LATER(ah)) {
1195 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1196 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1197
1198 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1199 ah->caps.rx_status_len);
1200 }
1201
d7e7d229
LR		 1202 /*
1203 * reduce the number of usable entries in PCU TXBUF to avoid
1204 * wrap around issues.
1205 */
f1dc5600 1206 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1207 /* For AR9285 the number of Fifos are reduced to half.
1208 * So set the usable tx buf size also to half to
1209 * avoid data/delimiter underruns
1210 */
86c157b3
FF		 1211 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1212 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1213 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1214 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1215 } else {
1216 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1217 }
744d4025 1218
86c157b3
FF		 1219 if (!AR_SREV_9271(ah))
1220 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1221
7d0d0df0 1222 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1223
744d4025
VT		 1224 if (AR_SREV_9300_20_OR_LATER(ah))
1225 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1226}
1227
cbe61d8a 1228static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1229{
ca7a4deb
FF		 1230 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1231 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1232
7b37e0d4 1233 ENABLE_REG_RMW_BUFFER(ah);
f1dc5600 1234 switch (opmode) {
d97809db 1235 case NL80211_IFTYPE_ADHOC:
83322eb8
FF		 1236 if (!AR_SREV_9340_13(ah)) {
1237 set |= AR_STA_ID1_ADHOC;
1238 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1239 break;
1240 }
1241 /* fall through */
2664d666 1242 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1243 case NL80211_IFTYPE_AP:
1244 set |= AR_STA_ID1_STA_AP;
1245 /* fall through */
d97809db 1246 case NL80211_IFTYPE_STATION:
ca7a4deb 1247 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1248 break;
5f841b41 1249 default:
ca7a4deb
FF		 1250 if (!ah->is_monitoring)
1251 set = 0;
5f841b41 1252 break;
f1dc5600 1253 }
ca7a4deb 1254 REG_RMW(ah, AR_STA_ID1, set, mask);
7b37e0d4 1255 REG_RMW_BUFFER_FLUSH(ah);
f1dc5600
S		 1256}
1257
8fe65368
LR		 1258void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1259 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1260{
1261 u32 coef_exp, coef_man;
1262
1263 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1264 if ((coef_scaled >> coef_exp) & 0x1)
1265 break;
1266
1267 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1268
1269 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1270
1271 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1272 *coef_exponent = coef_exp - 16;
1273}
1274
d7df7a55
SM		 1275/* AR9330 WAR:
1276 * call external reset function to reset WMAC if:
1277 * - doing a cold reset
1278 * - we have pending frames in the TX queues.
1279 */
1280static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1281{
1282 int i, npend = 0;
1283
1284 for (i = 0; i < AR_NUM_QCU; i++) {
1285 npend = ath9k_hw_numtxpending(ah, i);
1286 if (npend)
1287 break;
1288 }
1289
1290 if (ah->external_reset &&
1291 (npend || type == ATH9K_RESET_COLD)) {
1292 int reset_err = 0;
1293
1294 ath_dbg(ath9k_hw_common(ah), RESET,
1295 "reset MAC via external reset\n");
1296
1297 reset_err = ah->external_reset();
1298 if (reset_err) {
1299 ath_err(ath9k_hw_common(ah),
1300 "External reset failed, err=%d\n",
1301 reset_err);
1302 return false;
1303 }
1304
1305 REG_WRITE(ah, AR_RTC_RESET, 1);
1306 }
1307
1308 return true;
1309}
1310
cbe61d8a 1311static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1312{
1313 u32 rst_flags;
1314 u32 tmpReg;
1315
70768496 1316 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1317 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1318 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1319 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1320 }
1321
7d0d0df0
S		 1322 ENABLE_REGWRITE_BUFFER(ah);
1323
9a658d2b
LR		 1324 if (AR_SREV_9300_20_OR_LATER(ah)) {
1325 REG_WRITE(ah, AR_WA, ah->WARegVal);
1326 udelay(10);
1327 }
1328
f1dc5600
S		 1329 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1330 AR_RTC_FORCE_WAKE_ON_INT);
1331
1332 if (AR_SREV_9100(ah)) {
1333 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1334 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1335 } else {
1336 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1337 if (AR_SREV_9340(ah))
1338 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1339 else
1340 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1341 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1342
1343 if (tmpReg) {
42d5bc3f 1344 u32 val;
f1dc5600 1345 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1346
1347 val = AR_RC_HOSTIF;
1348 if (!AR_SREV_9300_20_OR_LATER(ah))
1349 val |= AR_RC_AHB;
1350 REG_WRITE(ah, AR_RC, val);
1351
1352 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1353 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1354
1355 rst_flags = AR_RTC_RC_MAC_WARM;
1356 if (type == ATH9K_RESET_COLD)
1357 rst_flags |= AR_RTC_RC_MAC_COLD;
1358 }
1359
7d95847c 1360 if (AR_SREV_9330(ah)) {
d7df7a55
SM		 1361 if (!ath9k_hw_ar9330_reset_war(ah, type))
1362 return false;
7d95847c
GJ		 1363 }
1364
3863495b 1365 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1366 ar9003_mci_check_gpm_offset(ah);
3863495b 1367
d03a66c1 1368 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1369
1370 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1371
4dc78c43
SM		 1372 if (AR_SREV_9300_20_OR_LATER(ah))
1373 udelay(50);
1374 else if (AR_SREV_9100(ah))
3683a07b 1375 mdelay(10);
4dc78c43
SM		 1376 else
1377 udelay(100);
f1dc5600 1378
d03a66c1 1379 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1380 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1381 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1382 return false;
1383 }
1384
1385 if (!AR_SREV_9100(ah))
1386 REG_WRITE(ah, AR_RC, 0);
1387
f1dc5600
S		 1388 if (AR_SREV_9100(ah))
1389 udelay(50);
1390
1391 return true;
1392}
1393
cbe61d8a 1394static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1395{
7d0d0df0
S		 1396 ENABLE_REGWRITE_BUFFER(ah);
1397
9a658d2b
LR		 1398 if (AR_SREV_9300_20_OR_LATER(ah)) {
1399 REG_WRITE(ah, AR_WA, ah->WARegVal);
1400 udelay(10);
1401 }
1402
f1dc5600
S		 1403 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1404 AR_RTC_FORCE_WAKE_ON_INT);
1405
42d5bc3f 1406 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1407 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1408
d03a66c1 1409 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1410
7d0d0df0 1411 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1412
afe36533 1413 udelay(2);
84e2169b
SB		 1414
1415 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1416 REG_WRITE(ah, AR_RC, 0);
1417
d03a66c1 1418 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1419
1420 if (!ath9k_hw_wait(ah,
1421 AR_RTC_STATUS,
1422 AR_RTC_STATUS_M,
0caa7b14
S		 1423 AR_RTC_STATUS_ON,
1424 AH_WAIT_TIMEOUT)) {
d2182b69 1425 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1426 return false;
f078f209
LR		 1427 }
1428
f1dc5600
S		 1429 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1430}
1431
cbe61d8a 1432static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1433{
7a9233ff 1434 bool ret = false;
2577c6e8 1435
9a658d2b
LR		 1436 if (AR_SREV_9300_20_OR_LATER(ah)) {
1437 REG_WRITE(ah, AR_WA, ah->WARegVal);
1438 udelay(10);
1439 }
1440
f1dc5600
S		 1441 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1442 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1443
ceb26a60
FF		 1444 if (!ah->reset_power_on)
1445 type = ATH9K_RESET_POWER_ON;
1446
f1dc5600
S		 1447 switch (type) {
1448 case ATH9K_RESET_POWER_ON:
7a9233ff 1449 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1450 if (ret)
ceb26a60 1451 ah->reset_power_on = true;
7a9233ff 1452 break;
f1dc5600
S		 1453 case ATH9K_RESET_WARM:
1454 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1455 ret = ath9k_hw_set_reset(ah, type);
1456 break;
f1dc5600 1457 default:
7a9233ff 1458 break;
f1dc5600 1459 }
7a9233ff 1460
7a9233ff 1461 return ret;
f078f209
LR		 1462}
1463
cbe61d8a 1464static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1465 struct ath9k_channel *chan)
f078f209 1466{
9c083af8
FF		 1467 int reset_type = ATH9K_RESET_WARM;
1468
1469 if (AR_SREV_9280(ah)) {
1470 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1471 reset_type = ATH9K_RESET_POWER_ON;
1472 else
1473 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1474 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1475 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1476 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1477
1478 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1479 return false;
f078f209 1480
9ecdef4b 1481 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1482 return false;
f078f209 1483
2660b81a 1484 ah->chip_fullsleep = false;
bfc441a4
FF		 1485
1486 if (AR_SREV_9330(ah))
1487 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1488 ath9k_hw_init_pll(ah, chan);
f078f209 1489
f1dc5600 1490 return true;
f078f209
LR		 1491}
1492
cbe61d8a 1493static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1494 struct ath9k_channel *chan)
f078f209 1495{
c46917bb 1496 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1497 struct ath9k_hw_capabilities *pCap = &ah->caps;
1498 bool band_switch = false, mode_diff = false;
70e89a71 1499 u8 ini_reloaded = 0;
8fe65368 1500 u32 qnum;
0a3b7bac 1501 int r;
5f0c04ea 1502
b840cffe 1503 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1504 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1505 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1506 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1507 }
f078f209
LR		 1508
1509 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1510 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1511 ath_dbg(common, QUEUE,
226afe68 1512 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1513 return false;
1514 }
1515 }
1516
8fe65368 1517 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1518 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1519 return false;
1520 }
1521
b840cffe 1522 if (band_switch || mode_diff) {
5f0c04ea
RM		 1523 ath9k_hw_mark_phy_inactive(ah);
1524 udelay(5);
1525
5f35c0fa
SM		 1526 if (band_switch)
1527 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1528
1529 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1530 ath_err(common, "Failed to do fast channel change\n");
1531 return false;
1532 }
1533 }
1534
8fe65368 1535 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1536
8fe65368 1537 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1538 if (r) {
3800276a 1539 ath_err(common, "Failed to set channel\n");
0a3b7bac 1540 return false;
f078f209 1541 }
dfdac8ac 1542 ath9k_hw_set_clockrate(ah);
64ea57d0 1543 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1544
81c507a8 1545 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1546 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1547
70e89a71
SM		 1548 if (band_switch || ini_reloaded)
1549 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1550
70e89a71
SM		 1551 ath9k_hw_init_bb(ah, chan);
1552 ath9k_hw_rfbus_done(ah);
5f0c04ea 1553
70e89a71
SM		 1554 if (band_switch || ini_reloaded) {
1555 ah->ah_flags |= AH_FASTCC;
1556 ath9k_hw_init_cal(ah, chan);
a126ff51 1557 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1558 }
1559
f1dc5600
S		 1560 return true;
1561}
1562
691680b8
FF		 1563static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1564{
1565 u32 gpio_mask = ah->gpio_mask;
1566 int i;
1567
1568 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1569 if (!(gpio_mask & 1))
1570 continue;
1571
1572 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1573 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1574 }
1575}
1576
1e516ca7
SM		 1577void ath9k_hw_check_nav(struct ath_hw *ah)
1578{
1579 struct ath_common *common = ath9k_hw_common(ah);
1580 u32 val;
1581
1582 val = REG_READ(ah, AR_NAV);
1583 if (val != 0xdeadbeef && val > 0x7fff) {
1584 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1585 REG_WRITE(ah, AR_NAV, 0);
1586 }
1587}
1588EXPORT_SYMBOL(ath9k_hw_check_nav);
1589
c9c99e5e 1590bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1591{
c9c99e5e 1592 int count = 50;
d31a36a6 1593 u32 reg, last_val;
c9c99e5e 1594
01e18918
RM		 1595 if (AR_SREV_9300(ah))
1596 return !ath9k_hw_detect_mac_hang(ah);
1597
e17f83ea 1598 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1599 return true;
1600
d31a36a6 1601 last_val = REG_READ(ah, AR_OBS_BUS_1);
c9c99e5e
FF		 1602 do {
1603 reg = REG_READ(ah, AR_OBS_BUS_1);
d31a36a6
FF		 1604 if (reg != last_val)
1605 return true;
3b319aae 1606
105ff411 1607 udelay(1);
d31a36a6 1608 last_val = reg;
c9c99e5e
FF		 1609 if ((reg & 0x7E7FFFEF) == 0x00702400)
1610 continue;
1611
1612 switch (reg & 0x7E000B00) {
1613 case 0x1E000000:
1614 case 0x52000B00:
1615 case 0x18000B00:
1616 continue;
1617 default:
1618 return true;
1619 }
1620 } while (count-- > 0);
3b319aae 1621
c9c99e5e 1622 return false;
3b319aae 1623}
c9c99e5e 1624EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1625
15d2b585
SM		 1626static void ath9k_hw_init_mfp(struct ath_hw *ah)
1627{
1628 /* Setup MFP options for CCMP */
1629 if (AR_SREV_9280_20_OR_LATER(ah)) {
1630 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1631 * frames when constructing CCMP AAD. */
1632 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1633 0xc7ff);
60fc4962
CYY		 1634 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1635 ah->sw_mgmt_crypto_tx = true;
1636 else
1637 ah->sw_mgmt_crypto_tx = false;
e6510b11 1638 ah->sw_mgmt_crypto_rx = false;
15d2b585
SM		 1639 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1640 /* Disable hardware crypto for management frames */
1641 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1642 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1643 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1644 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
e6510b11
CYY		 1645 ah->sw_mgmt_crypto_tx = true;
1646 ah->sw_mgmt_crypto_rx = true;
15d2b585 1647 } else {
e6510b11
CYY		 1648 ah->sw_mgmt_crypto_tx = true;
1649 ah->sw_mgmt_crypto_rx = true;
15d2b585
SM		 1650 }
1651}
1652
1653static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1654 u32 macStaId1, u32 saveDefAntenna)
1655{
1656 struct ath_common *common = ath9k_hw_common(ah);
1657
1658 ENABLE_REGWRITE_BUFFER(ah);
1659
ecbbed32 1660 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585 1661 | AR_STA_ID1_RTS_USE_DEF
ecbbed32
FF		 1662 | ah->sta_id1_defaults,
1663 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1664 ath_hw_setbssidmask(common);
1665 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1666 ath9k_hw_write_associd(ah);
1667 REG_WRITE(ah, AR_ISR, ~0);
1668 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1669
1670 REGWRITE_BUFFER_FLUSH(ah);
1671
1672 ath9k_hw_set_operating_mode(ah, ah->opmode);
1673}
1674
1675static void ath9k_hw_init_queues(struct ath_hw *ah)
1676{
1677 int i;
1678
1679 ENABLE_REGWRITE_BUFFER(ah);
1680
1681 for (i = 0; i < AR_NUM_DCU; i++)
1682 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1683
1684 REGWRITE_BUFFER_FLUSH(ah);
1685
1686 ah->intr_txqs = 0;
1687 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1688 ath9k_hw_resettxqueue(ah, i);
1689}
1690
1691/*
1692 * For big endian systems turn on swapping for descriptors
1693 */
1694static void ath9k_hw_init_desc(struct ath_hw *ah)
1695{
1696 struct ath_common *common = ath9k_hw_common(ah);
1697
1698 if (AR_SREV_9100(ah)) {
1699 u32 mask;
1700 mask = REG_READ(ah, AR_CFG);
1701 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1702 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1703 mask);
1704 } else {
1705 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1706 REG_WRITE(ah, AR_CFG, mask);
1707 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1708 REG_READ(ah, AR_CFG));
1709 }
1710 } else {
1711 if (common->bus_ops->ath_bus_type == ATH_USB) {
1712 /* Configure AR9271 target WLAN */
1713 if (AR_SREV_9271(ah))
1714 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1715 else
1716 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1717 }
1718#ifdef __BIG_ENDIAN
1719 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
ede6a5e7
MP		 1720 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1721 AR_SREV_9561(ah))
15d2b585
SM		 1722 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1723 else
1724 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1725#endif
1726 }
1727}
1728
caed6579
SM		 1729/*
1730 * Fast channel change:
1731 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1732 */
1733static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1734{
1735 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1736 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1737 int ret;
1738
1739 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1740 goto fail;
1741
1742 if (ah->chip_fullsleep)
1743 goto fail;
1744
1745 if (!ah->curchan)
1746 goto fail;
1747
1748 if (chan->channel == ah->curchan->channel)
1749 goto fail;
1750
feb7bc99
FF		 1751 if ((ah->curchan->channelFlags | chan->channelFlags) &
1752 (CHANNEL_HALF | CHANNEL_QUARTER))
1753 goto fail;
1754
b840cffe 1755 /*
6b21fd20 1756 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1757 */
6b21fd20 1758 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1759 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1760 goto fail;
caed6579
SM		 1761
1762 if (!ath9k_hw_check_alive(ah))
1763 goto fail;
1764
1765 /*
1766 * For AR9462, make sure that calibration data for
1767 * re-using are present.
1768 */
8a90555f 1769 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1770 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1771 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1772 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1773 goto fail;
1774
1775 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1776 ah->curchan->channel, chan->channel);
1777
1778 ret = ath9k_hw_channel_change(ah, chan);
1779 if (!ret)
1780 goto fail;
1781
5955b2b0 1782 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1783 ar9003_mci_2g5g_switch(ah, false);
caed6579 1784
88033318
RM		 1785 ath9k_hw_loadnf(ah, ah->curchan);
1786 ath9k_hw_start_nfcal(ah, true);
1787
caed6579
SM		 1788 if (AR_SREV_9271(ah))
1789 ar9002_hw_load_ani_reg(ah, chan);
1790
1791 return 0;
1792fail:
1793 return -EINVAL;
1794}
1795
8d7e09dd
FF		 1796u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1797{
1798 struct timespec ts;
1799 s64 usec;
1800
1801 if (!cur) {
1802 getrawmonotonic(&ts);
1803 cur = &ts;
1804 }
1805
1806 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1807 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1808
1809 return (u32) usec;
1810}
1811EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1812
cbe61d8a 1813int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1814 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1815{
1510718d 1816 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1817 u32 saveLedState;
f078f209
LR		 1818 u32 saveDefAntenna;
1819 u32 macStaId1;
46fe782c 1820 u64 tsf = 0;
09d8e315 1821 s64 usec = 0;
15d2b585 1822 int r;
caed6579 1823 bool start_mci_reset = false;
63d32967
MSS		 1824 bool save_fullsleep = ah->chip_fullsleep;
1825
5955b2b0 1826 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1827 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1828 if (start_mci_reset)
1829 return 0;
63d32967
MSS		 1830 }
1831
9ecdef4b 1832 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1833 return -EIO;
f078f209 1834
caed6579
SM		 1835 if (ah->curchan && !ah->chip_fullsleep)
1836 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1837
20bd2a09 1838 ah->caldata = caldata;
fcb9a3de 1839 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1840 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1841 /* Operating channel changed, reset channel calibration data */
1842 memset(caldata, 0, sizeof(*caldata));
1843 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1844 } else if (caldata) {
4b9b42bf 1845 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1846 }
5bc225ac 1847 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1848
caed6579
SM		 1849 if (fastcc) {
1850 r = ath9k_hw_do_fastcc(ah, chan);
1851 if (!r)
1852 return r;
f078f209
LR		 1853 }
1854
5955b2b0 1855 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1856 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1857
f078f209
LR		 1858 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1859 if (saveDefAntenna == 0)
1860 saveDefAntenna = 1;
1861
1862 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1863
09d8e315
FF		 1864 /* Save TSF before chip reset, a cold reset clears it */
1865 tsf = ath9k_hw_gettsf64(ah);
6438e0dd 1866 usec = ktime_to_us(ktime_get_raw());
46fe782c 1867
f078f209
LR		 1868 saveLedState = REG_READ(ah, AR_CFG_LED) &
1869 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1870 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1871
1872 ath9k_hw_mark_phy_inactive(ah);
1873
45ef6a0b
VT		 1874 ah->paprd_table_write_done = false;
1875
05020d23 1876 /* Only required on the first reset */
d7e7d229
LR		 1877 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1878 REG_WRITE(ah,
1879 AR9271_RESET_POWER_DOWN_CONTROL,
1880 AR9271_RADIO_RF_RST);
1881 udelay(50);
1882 }
1883
f078f209 1884 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1885 ath_err(common, "Chip reset failed\n");
ae8d2858 1886 return -EINVAL;
f078f209
LR		 1887 }
1888
05020d23 1889 /* Only required on the first reset */
d7e7d229
LR		 1890 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1891 ah->htc_reset_init = false;
1892 REG_WRITE(ah,
1893 AR9271_RESET_POWER_DOWN_CONTROL,
1894 AR9271_GATE_MAC_CTL);
1895 udelay(50);
1896 }
1897
46fe782c 1898 /* Restore TSF */
6438e0dd 1899 usec = ktime_to_us(ktime_get_raw()) - usec;
09d8e315 1900 ath9k_hw_settsf64(ah, tsf + usec);
46fe782c 1901
7a37081e 1902 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1903 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1904
e9141f71
S		 1905 if (!AR_SREV_9300_20_OR_LATER(ah))
1906 ar9002_hw_enable_async_fifo(ah);
1907
25c56eec 1908 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1909 if (r)
1910 return r;
f078f209 1911
935d00cc
LB		 1912 ath9k_hw_set_rfmode(ah, chan);
1913
5955b2b0 1914 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1915 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1916
f860d526
FF		 1917 /*
1918 * Some AR91xx SoC devices frequently fail to accept TSF writes
1919 * right after the chip reset. When that happens, write a new
1920 * value after the initvals have been applied, with an offset
1921 * based on measured time difference
1922 */
1923 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1924 tsf += 1500;
1925 ath9k_hw_settsf64(ah, tsf);
1926 }
1927
15d2b585 1928 ath9k_hw_init_mfp(ah);
0ced0e17 1929
81c507a8 1930 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1931 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1932 ah->eep_ops->set_board_values(ah, chan);
a7765828 1933
15d2b585 1934 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1935
8fe65368 1936 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1937 if (r)
1938 return r;
f078f209 1939
dfdac8ac
FF		 1940 ath9k_hw_set_clockrate(ah);
1941
15d2b585 1942 ath9k_hw_init_queues(ah);
2660b81a 1943 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1944 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1945 ath9k_hw_init_qos(ah);
1946
2660b81a 1947 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1948 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1949
0005baf4 1950 ath9k_hw_init_global_settings(ah);
f078f209 1951
fe2b6afb
FF		 1952 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1953 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1954 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1955 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1956 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1957 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1958 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1959 }
1960
ca7a4deb 1961 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1962
1963 ath9k_hw_set_dma(ah);
1964
ed6ebd8b
RM		 1965 if (!ath9k_hw_mci_is_enabled(ah))
1966 REG_WRITE(ah, AR_OBS, 8);
f078f209 1967
7b37e0d4 1968 ENABLE_REG_RMW_BUFFER(ah);
0ce024cb 1969 if (ah->config.rx_intr_mitigation) {
a64e1a45
SM		 1970 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1971 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
f078f209
LR		 1972 }
1973
7f62a136
VT		 1974 if (ah->config.tx_intr_mitigation) {
1975 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1976 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1977 }
7b37e0d4 1978 REG_RMW_BUFFER_FLUSH(ah);
7f62a136 1979
f078f209
LR		 1980 ath9k_hw_init_bb(ah, chan);
1981
77a5a664 1982 if (caldata) {
4b9b42bf
SM		 1983 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1984 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 1985 }
ae8d2858 1986 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1987 return -EIO;
f078f209 1988
5955b2b0 1989 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 1990 return -EIO;
63d32967 1991
7d0d0df0 1992 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1993
8fe65368 1994 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1995 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1996
7d0d0df0 1997 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1998
f4c34af4
SM		 1999 ath9k_hw_gen_timer_start_tsf2(ah);
2000
15d2b585 2001 ath9k_hw_init_desc(ah);
f078f209 2002
dbccdd1d 2003 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 2004 ath9k_hw_btcoex_enable(ah);
2005
5955b2b0 2006 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 2007 ar9003_mci_check_bt(ah);
63d32967 2008
7b89fccf
FF		 2009 if (AR_SREV_9300_20_OR_LATER(ah)) {
2010 ath9k_hw_loadnf(ah, chan);
2011 ath9k_hw_start_nfcal(ah, true);
2012 }
1fe860ed 2013
a7abaf7d 2014 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 2015 ar9003_hw_bb_watchdog_config(ah);
a7abaf7d
SM		 2016
2017 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
51ac8cbb 2018 ar9003_hw_disable_phy_restart(ah);
51ac8cbb 2019
691680b8
FF		 2020 ath9k_hw_apply_gpio_override(ah);
2021
7bdea96a 2022 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 2023 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2024
4307b0fe
LB		 2025 if (ah->hw->conf.radar_enabled) {
2026 /* set HW specific DFS configuration */
7a0a260a 2027 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
4307b0fe
LB		 2028 ath9k_hw_set_radar_params(ah);
2029 }
2030
ae8d2858 2031 return 0;
f078f209 2032}
7322fd19 2033EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2034
f1dc5600
S		 2035/******************************/
2036/* Power Management (Chipset) */
2037/******************************/
2038
42d5bc3f
LR		 2039/*
2040 * Notify Power Mgt is disabled in self-generated frames.
2041 * If requested, force chip to sleep.
2042 */
31604cf0 2043static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 2044{
f1dc5600 2045 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 2046
a4a2954f 2047 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 2048 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2049 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2050 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 2051 /* xxx Required for WLAN only case ? */
2052 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2053 udelay(100);
2054 }
2577c6e8 2055
31604cf0
SM		 2056 /*
2057 * Clear the RTC force wake bit to allow the
2058 * mac to go to sleep.
2059 */
2060 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2061
153dccd4 2062 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2063 udelay(100);
2577c6e8 2064
31604cf0
SM		 2065 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2066 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2067
31604cf0
SM		 2068 /* Shutdown chip. Active low */
2069 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2070 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2071 udelay(2);
f1dc5600 2072 }
9a658d2b
LR		 2073
2074 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2075 if (AR_SREV_9300_20_OR_LATER(ah))
2076 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2077}
2078
bbd79af5
LR		 2079/*
2080 * Notify Power Management is enabled in self-generating
2081 * frames. If request, set power mode of chip to
2082 * auto/normal. Duration in units of 128us (1/8 TU).
2083 */
31604cf0 2084static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2085{
31604cf0 2086 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2087
f1dc5600 2088 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2089
31604cf0
SM		 2090 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2091 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2092 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2093 AR_RTC_FORCE_WAKE_ON_INT);
2094 } else {
2577c6e8 2095
31604cf0
SM		 2096 /* When chip goes into network sleep, it could be waken
2097 * up by MCI_INT interrupt caused by BT's HW messages
2098 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2099 * rate (~100us). This will cause chip to leave and
2100 * re-enter network sleep mode frequently, which in
2101 * consequence will have WLAN MCI HW to generate lots of
2102 * SYS_WAKING and SYS_SLEEPING messages which will make
2103 * BT CPU to busy to process.
2104 */
153dccd4
RM		 2105 if (ath9k_hw_mci_is_enabled(ah))
2106 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2107 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2108 /*
2109 * Clear the RTC force wake bit to allow the
2110 * mac to go to sleep.
2111 */
153dccd4 2112 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2113
153dccd4 2114 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2115 udelay(30);
f078f209 2116 }
9a658d2b
LR		 2117
2118 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2119 if (AR_SREV_9300_20_OR_LATER(ah))
2120 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2121}
2122
31604cf0 2123static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2124{
f1dc5600
S		 2125 u32 val;
2126 int i;
f078f209 2127
9a658d2b
LR		 2128 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2129 if (AR_SREV_9300_20_OR_LATER(ah)) {
2130 REG_WRITE(ah, AR_WA, ah->WARegVal);
2131 udelay(10);
2132 }
2133
31604cf0
SM		 2134 if ((REG_READ(ah, AR_RTC_STATUS) &
2135 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2136 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2137 return false;
f1dc5600 2138 }
31604cf0
SM		 2139 if (!AR_SREV_9300_20_OR_LATER(ah))
2140 ath9k_hw_init_pll(ah, NULL);
2141 }
2142 if (AR_SREV_9100(ah))
2143 REG_SET_BIT(ah, AR_RTC_RESET,
2144 AR_RTC_RESET_EN);
2145
2146 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2147 AR_RTC_FORCE_WAKE_EN);
04575f21 2148 if (AR_SREV_9100(ah))
3683a07b 2149 mdelay(10);
04575f21
SM		 2150 else
2151 udelay(50);
f078f209 2152
31604cf0
SM		 2153 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2154 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2155 if (val == AR_RTC_STATUS_ON)
2156 break;
2157 udelay(50);
f1dc5600
S		 2158 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2159 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2160 }
2161 if (i == 0) {
2162 ath_err(ath9k_hw_common(ah),
2163 "Failed to wakeup in %uus\n",
2164 POWER_UP_TIME / 20);
2165 return false;
f078f209
LR		 2166 }
2167
cdbe408d
RM		 2168 if (ath9k_hw_mci_is_enabled(ah))
2169 ar9003_mci_set_power_awake(ah);
2170
f1dc5600 2171 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2172
f1dc5600 2173 return true;
f078f209
LR		 2174}
2175
9ecdef4b 2176bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2177{
c46917bb 2178 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2179 int status = true;
f1dc5600
S		 2180 static const char *modes[] = {
2181 "AWAKE",
2182 "FULL-SLEEP",
2183 "NETWORK SLEEP",
2184 "UNDEFINED"
2185 };
f1dc5600 2186
cbdec975
GJ		 2187 if (ah->power_mode == mode)
2188 return status;
2189
d2182b69 2190 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2191 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2192
2193 switch (mode) {
2194 case ATH9K_PM_AWAKE:
31604cf0 2195 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2196 break;
2197 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2198 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2199 ar9003_mci_set_full_sleep(ah);
1010911e 2200
31604cf0 2201 ath9k_set_power_sleep(ah);
2660b81a 2202 ah->chip_fullsleep = true;
f1dc5600
S		 2203 break;
2204 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2205 ath9k_set_power_network_sleep(ah);
f1dc5600 2206 break;
f078f209 2207 default:
3800276a 2208 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2209 return false;
2210 }
2660b81a 2211 ah->power_mode = mode;
f1dc5600 2212
69f4aab1
LR		 2213 /*
2214 * XXX: If this warning never comes up after a while then
2215 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2216 * ath9k_hw_setpower() return type void.
2217 */
97dcec57
SM		 2218
2219 if (!(ah->ah_flags & AH_UNPLUGGED))
2220 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2221
f1dc5600 2222 return status;
f078f209 2223}
7322fd19 2224EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2225
f1dc5600
S		 2226/*******************/
2227/* Beacon Handling */
2228/*******************/
2229
cbe61d8a 2230void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2231{
f078f209
LR		 2232 int flags = 0;
2233
7d0d0df0
S		 2234 ENABLE_REGWRITE_BUFFER(ah);
2235
2660b81a 2236 switch (ah->opmode) {
d97809db 2237 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2238 REG_SET_BIT(ah, AR_TXCFG,
2239 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2240 case NL80211_IFTYPE_MESH_POINT:
d97809db 2241 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2242 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2243 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2244 TU_TO_USEC(ah->config.dma_beacon_response_time));
2245 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2246 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2247 flags |=
2248 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2249 break;
d97809db 2250 default:
d2182b69
JP		 2251 ath_dbg(ath9k_hw_common(ah), BEACON,
2252 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2253 return;
2254 break;
f078f209
LR		 2255 }
2256
dd347f2f
FF		 2257 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2258 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2259 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2260
7d0d0df0 2261 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2262
f078f209
LR		 2263 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2264}
7322fd19 2265EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2266
cbe61d8a 2267void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2268 const struct ath9k_beacon_state *bs)
f078f209
LR		 2269{
2270 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2271 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2272 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2273
7d0d0df0
S		 2274 ENABLE_REGWRITE_BUFFER(ah);
2275
4ed15762
FF		 2276 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2277 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2278 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2279
7d0d0df0 2280 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2281
f078f209
LR		 2282 REG_RMW_FIELD(ah, AR_RSSI_THR,
2283 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2284
f29f5c08 2285 beaconintval = bs->bs_intval;
f078f209
LR		 2286
2287 if (bs->bs_sleepduration > beaconintval)
2288 beaconintval = bs->bs_sleepduration;
2289
2290 dtimperiod = bs->bs_dtimperiod;
2291 if (bs->bs_sleepduration > dtimperiod)
2292 dtimperiod = bs->bs_sleepduration;
2293
2294 if (beaconintval == dtimperiod)
2295 nextTbtt = bs->bs_nextdtim;
2296 else
2297 nextTbtt = bs->bs_nexttbtt;
2298
d2182b69
JP		 2299 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2300 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2301 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2302 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2303
7d0d0df0
S		 2304 ENABLE_REGWRITE_BUFFER(ah);
2305
4ed15762
FF		 2306 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2307 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2308
f1dc5600
S		 2309 REG_WRITE(ah, AR_SLEEP1,
2310 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2311 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2312
f1dc5600
S		 2313 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2314 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2315 else
2316 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2317
f1dc5600
S		 2318 REG_WRITE(ah, AR_SLEEP2,
2319 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2320
4ed15762
FF		 2321 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2322 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2323
7d0d0df0 2324 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2325
f1dc5600
S		 2326 REG_SET_BIT(ah, AR_TIMER_MODE,
2327 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2328 AR_DTIM_TIMER_EN);
f078f209 2329
4af9cf4f
S		 2330 /* TSF Out of Range Threshold */
2331 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2332}
7322fd19 2333EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2334
f1dc5600
S		 2335/*******************/
2336/* HW Capabilities */
2337/*******************/
2338
6054069a
FF		 2339static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2340{
2341 eeprom_chainmask &= chip_chainmask;
2342 if (eeprom_chainmask)
2343 return eeprom_chainmask;
2344 else
2345 return chip_chainmask;
2346}
2347
9a66af33
ZK		 2348/**
2349 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2350 * @ah: the atheros hardware data structure
2351 *
2352 * We enable DFS support upstream on chipsets which have passed a series
2353 * of tests. The testing requirements are going to be documented. Desired
2354 * test requirements are documented at:
2355 *
2356 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2357 *
2358 * Once a new chipset gets properly tested an individual commit can be used
2359 * to document the testing for DFS for that chipset.
2360 */
2361static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2362{
2363
2364 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2365 /* for temporary testing DFS with 9280 */
2366 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2367 /* AR9580 will likely be our first target to get testing on */
2368 case AR_SREV_VERSION_9580:
73e4937d 2369 return true;
9a66af33
ZK		 2370 default:
2371 return false;
2372 }
2373}
2374
a9a29ce6 2375int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2376{
2660b81a 2377 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2378 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2379 struct ath_common *common = ath9k_hw_common(ah);
608b88cb 2380
0ff2b5c0 2381 u16 eeval;
47c80de6 2382 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2383
f74df6fb 2384 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2385 regulatory->current_rd = eeval;
f078f209 2386
2660b81a 2387 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2388 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2389 if (regulatory->current_rd == 0x64 ||
2390 regulatory->current_rd == 0x65)
2391 regulatory->current_rd += 5;
2392 else if (regulatory->current_rd == 0x41)
2393 regulatory->current_rd = 0x43;
d2182b69
JP		 2394 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2395 regulatory->current_rd);
f1dc5600 2396 }
f078f209 2397
f74df6fb 2398 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3468968e
FF		 2399
2400 if (eeval & AR5416_OPFLAGS_11A) {
2401 if (ah->disable_5ghz)
2402 ath_warn(common, "disabling 5GHz band\n");
2403 else
2404 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
a9a29ce6
GJ		 2405 }
2406
3468968e
FF		 2407 if (eeval & AR5416_OPFLAGS_11G) {
2408 if (ah->disable_2ghz)
2409 ath_warn(common, "disabling 2GHz band\n");
2410 else
2411 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2412 }
f078f209 2413
3468968e
FF		 2414 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2415 ath_err(common, "both bands are disabled\n");
2416 return -EINVAL;
2417 }
f1dc5600 2418
e41db61d
SM		 2419 if (AR_SREV_9485(ah) ||
2420 AR_SREV_9285(ah) ||
2421 AR_SREV_9330(ah) ||
2422 AR_SREV_9565(ah))
ee79ccd9 2423 pCap->chip_chainmask = 1;
6054069a 2424 else if (!AR_SREV_9280_20_OR_LATER(ah))
ee79ccd9
SM		 2425 pCap->chip_chainmask = 7;
2426 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2427 AR_SREV_9340(ah) ||
2428 AR_SREV_9462(ah) ||
2429 AR_SREV_9531(ah))
2430 pCap->chip_chainmask = 3;
6054069a 2431 else
ee79ccd9 2432 pCap->chip_chainmask = 7;
6054069a 2433
f74df6fb 2434 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2435 /*
2436 * For AR9271 we will temporarilly uses the rx chainmax as read from
2437 * the EEPROM.
2438 */
8147f5de 2439 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2440 !(eeval & AR5416_OPFLAGS_11A) &&
2441 !(AR_SREV_9271(ah)))
2442 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2443 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2444 else if (AR_SREV_9100(ah))
2445 pCap->rx_chainmask = 0x7;
8147f5de 2446 else
d7e7d229 2447 /* Use rx_chainmask from EEPROM. */
8147f5de 2448 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2449
ee79ccd9
SM		 2450 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2451 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2452 ah->txchainmask = pCap->tx_chainmask;
2453 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2454
7a37081e 2455 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2456
02d2ebb2
FF		 2457 /* enable key search for every frame in an aggregate */
2458 if (AR_SREV_9300_20_OR_LATER(ah))
2459 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2460
ce2220d1
BR		 2461 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2462
0db156e9 2463 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2464 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2465 else
2466 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2467
5b5fa355
S		 2468 if (AR_SREV_9271(ah))
2469 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2470 else if (AR_DEVID_7010(ah))
2471 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2472 else if (AR_SREV_9300_20_OR_LATER(ah))
2473 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2474 else if (AR_SREV_9287_11_OR_LATER(ah))
2475 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2476 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2477 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2478 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2479 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2480 else
2481 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2482
1b2538b2 2483 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2484 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2485 else
f1dc5600 2486 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2487
74e13060 2488#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2489 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2490 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2491 ah->rfkill_gpio =
2492 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2493 ah->rfkill_polarity =
2494 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2495
2496 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2497 }
f1dc5600 2498#endif
d5d1154f 2499 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2500 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2501 else
2502 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2503
e7594072 2504 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2505 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2506 else
2507 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2508
ceb26445 2509 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2510 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
ede6a5e7
MP		 2511 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2512 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2513 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2514
ceb26445
VT		 2515 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2516 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2517 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2518 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2519 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2520 } else {
2521 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2522 if (AR_SREV_9280_20(ah))
6b42e8d0 2523 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2524 }
1adf02ff 2525
6c84ce08
VT		 2526 if (AR_SREV_9300_20_OR_LATER(ah))
2527 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2528
ede6a5e7
MP		 2529 if (AR_SREV_9561(ah))
2530 ah->ent_mode = 0x3BDA000;
2531 else if (AR_SREV_9300_20_OR_LATER(ah))
6ee63f55
SB		 2532 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2533
a42acef0 2534 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2535 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2536
f85c3371 2537 if (AR_SREV_9285(ah)) {
754dc536
VT		 2538 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2539 ant_div_ctl1 =
2540 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2541 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2542 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2543 ath_info(common, "Enable LNA combining\n");
2544 }
754dc536 2545 }
f85c3371
SM		 2546 }
2547
ea066d5a
MSS		 2548 if (AR_SREV_9300_20_OR_LATER(ah)) {
2549 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2550 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2551 }
2552
06236e53 2553 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2554 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2555 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2556 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2557 ath_info(common, "Enable LNA combining\n");
2558 }
21d2c63a 2559 }
754dc536 2560
9a66af33
ZK		 2561 if (ath9k_hw_dfs_tested(ah))
2562 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2563
47c80de6
VT		 2564 tx_chainmask = pCap->tx_chainmask;
2565 rx_chainmask = pCap->rx_chainmask;
2566 while (tx_chainmask || rx_chainmask) {
2567 if (tx_chainmask & BIT(0))
2568 pCap->max_txchains++;
2569 if (rx_chainmask & BIT(0))
2570 pCap->max_rxchains++;
2571
2572 tx_chainmask >>= 1;
2573 rx_chainmask >>= 1;
2574 }
2575
a4a2954f 2576 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2577 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2578 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2579
2b5e54e2 2580 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2581 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2582 }
2583
0f21ee8d
SM		 2584 if (AR_SREV_9300_20_OR_LATER(ah) &&
2585 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2586 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2587
12a44422
SM		 2588#ifdef CONFIG_ATH9K_WOW
2589 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2590 ah->wow.max_patterns = MAX_NUM_PATTERN;
2591 else
2592 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2593#endif
2594
a9a29ce6 2595 return 0;
f078f209
LR		 2596}
2597
f1dc5600
S		 2598/****************************/
2599/* GPIO / RFKILL / Antennae */
2600/****************************/
f078f209 2601
cbe61d8a 2602static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2603 u32 gpio, u32 type)
2604{
2605 int addr;
2606 u32 gpio_shift, tmp;
f078f209 2607
f1dc5600
S		 2608 if (gpio > 11)
2609 addr = AR_GPIO_OUTPUT_MUX3;
2610 else if (gpio > 5)
2611 addr = AR_GPIO_OUTPUT_MUX2;
2612 else
2613 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2614
f1dc5600 2615 gpio_shift = (gpio % 6) * 5;
f078f209 2616
f1dc5600
S		 2617 if (AR_SREV_9280_20_OR_LATER(ah)
2618 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2619 REG_RMW(ah, addr, (type << gpio_shift),
2620 (0x1f << gpio_shift));
f078f209 2621 } else {
f1dc5600
S		 2622 tmp = REG_READ(ah, addr);
2623 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2624 tmp &= ~(0x1f << gpio_shift);
2625 tmp |= (type << gpio_shift);
2626 REG_WRITE(ah, addr, tmp);
f078f209 2627 }
f078f209
LR		 2628}
2629
cbe61d8a 2630void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2631{
f1dc5600 2632 u32 gpio_shift;
f078f209 2633
9680e8a3 2634 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2635
88c1f4f6
S		 2636 if (AR_DEVID_7010(ah)) {
2637 gpio_shift = gpio;
2638 REG_RMW(ah, AR7010_GPIO_OE,
2639 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2640 (AR7010_GPIO_OE_MASK << gpio_shift));
2641 return;
2642 }
f078f209 2643
88c1f4f6 2644 gpio_shift = gpio << 1;
f1dc5600
S		 2645 REG_RMW(ah,
2646 AR_GPIO_OE_OUT,
2647 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2648 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2649}
7322fd19 2650EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2651
cbe61d8a 2652u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2653{
cb33c412
SB		 2654#define MS_REG_READ(x, y) \
2655 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2656
2660b81a 2657 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2658 return 0xffffffff;
f078f209 2659
88c1f4f6
S		 2660 if (AR_DEVID_7010(ah)) {
2661 u32 val;
2662 val = REG_READ(ah, AR7010_GPIO_IN);
2663 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2664 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2665 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2666 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2667 else if (AR_SREV_9271(ah))
5b5fa355 2668 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2669 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2670 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2671 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2672 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2673 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2674 return MS_REG_READ(AR928X, gpio) != 0;
2675 else
2676 return MS_REG_READ(AR, gpio) != 0;
f078f209 2677}
7322fd19 2678EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2679
cbe61d8a 2680void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2681 u32 ah_signal_type)
f078f209 2682{
f1dc5600 2683 u32 gpio_shift;
f078f209 2684
88c1f4f6
S		 2685 if (AR_DEVID_7010(ah)) {
2686 gpio_shift = gpio;
2687 REG_RMW(ah, AR7010_GPIO_OE,
2688 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2689 (AR7010_GPIO_OE_MASK << gpio_shift));
2690 return;
2691 }
f078f209 2692
88c1f4f6 2693 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2694 gpio_shift = 2 * gpio;
f1dc5600
S		 2695 REG_RMW(ah,
2696 AR_GPIO_OE_OUT,
2697 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2698 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2699}
7322fd19 2700EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2701
cbe61d8a 2702void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2703{
88c1f4f6
S		 2704 if (AR_DEVID_7010(ah)) {
2705 val = val ? 0 : 1;
2706 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2707 AR_GPIO_BIT(gpio));
2708 return;
2709 }
2710
5b5fa355
S		 2711 if (AR_SREV_9271(ah))
2712 val = ~val;
2713
f1dc5600
S		 2714 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2715 AR_GPIO_BIT(gpio));
f078f209 2716}
7322fd19 2717EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2718
cbe61d8a 2719void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2720{
f1dc5600 2721 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2722}
7322fd19 2723EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2724
f1dc5600
S		 2725/*********************/
2726/* General Operation */
2727/*********************/
2728
cbe61d8a 2729u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2730{
f1dc5600
S		 2731 u32 bits = REG_READ(ah, AR_RX_FILTER);
2732 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2733
f1dc5600
S		 2734 if (phybits & AR_PHY_ERR_RADAR)
2735 bits |= ATH9K_RX_FILTER_PHYRADAR;
2736 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2737 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2738
f1dc5600 2739 return bits;
f078f209 2740}
7322fd19 2741EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2742
cbe61d8a 2743void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2744{
f1dc5600 2745 u32 phybits;
f078f209 2746
7d0d0df0
S		 2747 ENABLE_REGWRITE_BUFFER(ah);
2748
a4a2954f 2749 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2577c6e8
SB		 2750 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2751
7ea310be
S		 2752 REG_WRITE(ah, AR_RX_FILTER, bits);
2753
f1dc5600
S		 2754 phybits = 0;
2755 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2756 phybits |= AR_PHY_ERR_RADAR;
2757 if (bits & ATH9K_RX_FILTER_PHYERR)
2758 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2759 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2760
f1dc5600 2761 if (phybits)
ca7a4deb 2762 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2763 else
ca7a4deb 2764 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2765
2766 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2767}
7322fd19 2768EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2769
cbe61d8a 2770bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2771{
99922a45
RM		 2772 if (ath9k_hw_mci_is_enabled(ah))
2773 ar9003_mci_bt_gain_ctrl(ah);
2774
63a75b91
SB		 2775 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2776 return false;
2777
2778 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2779 ah->htc_reset_init = true;
63a75b91 2780 return true;
f1dc5600 2781}
7322fd19 2782EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2783
cbe61d8a 2784bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2785{
9ecdef4b 2786 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2787 return false;
f078f209 2788
63a75b91
SB		 2789 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2790 return false;
2791
2792 ath9k_hw_init_pll(ah, NULL);
2793 return true;
f078f209 2794}
7322fd19 2795EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2796
ca2c68cc
FF		 2797static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2798{
2799 enum eeprom_param gain_param;
2800
2801 if (IS_CHAN_2GHZ(chan))
2802 gain_param = EEP_ANTENNA_GAIN_2G;
2803 else
2804 gain_param = EEP_ANTENNA_GAIN_5G;
2805
2806 return ah->eep_ops->get_eeprom(ah, gain_param);
2807}
2808
64ea57d0
GJ		 2809void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2810 bool test)
ca2c68cc
FF		 2811{
2812 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2813 struct ieee80211_channel *channel;
2814 int chan_pwr, new_pwr, max_gain;
2815 int ant_gain, ant_reduction = 0;
2816
2817 if (!chan)
2818 return;
2819
2820 channel = chan->chan;
2821 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2822 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2823 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2824
2825 ant_gain = get_antenna_gain(ah, chan);
2826 if (ant_gain > max_gain)
2827 ant_reduction = ant_gain - max_gain;
2828
2829 ah->eep_ops->set_txpower(ah, chan,
2830 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2831 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2832}
2833
de40f316 2834void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2835{
ca2c68cc 2836 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2837 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2838 struct ieee80211_channel *channel = chan->chan;
9c204b46 2839
48ef5c42 2840 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2841 if (test)
ca2c68cc 2842 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2843
64ea57d0 2844 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2845
ca2c68cc
FF		 2846 if (test)
2847 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2848}
7322fd19 2849EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2850
cbe61d8a 2851void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2852{
2660b81a 2853 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2854}
7322fd19 2855EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2856
cbe61d8a 2857void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2858{
f1dc5600
S		 2859 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2860 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2861}
7322fd19 2862EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2863
f2b2143e 2864void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2865{
1510718d
LR		 2866 struct ath_common *common = ath9k_hw_common(ah);
2867
2868 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2869 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2870 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2871}
7322fd19 2872EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2873
1c0fc65e
BP		 2874#define ATH9K_MAX_TSF_READ 10
2875
cbe61d8a 2876u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2877{
1c0fc65e
BP		 2878 u32 tsf_lower, tsf_upper1, tsf_upper2;
2879 int i;
2880
2881 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2882 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2883 tsf_lower = REG_READ(ah, AR_TSF_L32);
2884 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2885 if (tsf_upper2 == tsf_upper1)
2886 break;
2887 tsf_upper1 = tsf_upper2;
2888 }
f078f209 2889
1c0fc65e 2890 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2891
1c0fc65e 2892 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2893}
7322fd19 2894EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2895
cbe61d8a 2896void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2897{
27abe060 2898 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2899 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2900}
7322fd19 2901EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2902
cbe61d8a 2903void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2904{
f9b604f6
GJ		 2905 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2906 AH_TSF_WRITE_TIMEOUT))
d2182b69 2907 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2908 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2909
f1dc5600
S		 2910 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2911}
7322fd19 2912EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2913
60ca9f87 2914void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 2915{
60ca9f87 2916 if (set)
2660b81a 2917 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2918 else
2660b81a 2919 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2920}
7322fd19 2921EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2922
e4744ec7 2923void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 2924{
2925 u32 macmode;
2926
e4744ec7 2927 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2928 macmode = AR_2040_JOINED_RX_CLEAR;
2929 else
2930 macmode = 0;
f078f209 2931
f1dc5600 2932 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2933}
ff155a45
VT		 2934
2935/* HW Generic timers configuration */
2936
2937static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2938{
2939 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2940 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2941 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2942 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2943 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2944 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2945 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2946 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2947 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2948 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2949 AR_NDP2_TIMER_MODE, 0x0002},
2950 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2951 AR_NDP2_TIMER_MODE, 0x0004},
2952 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2953 AR_NDP2_TIMER_MODE, 0x0008},
2954 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2955 AR_NDP2_TIMER_MODE, 0x0010},
2956 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2957 AR_NDP2_TIMER_MODE, 0x0020},
2958 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2959 AR_NDP2_TIMER_MODE, 0x0040},
2960 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2961 AR_NDP2_TIMER_MODE, 0x0080}
2962};
2963
2964/* HW generic timer primitives */
2965
dd347f2f 2966u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2967{
2968 return REG_READ(ah, AR_TSF_L32);
2969}
dd347f2f 2970EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45 2971
f4c34af4
SM		 2972void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
2973{
2974 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2975
2976 if (timer_table->tsf2_enabled) {
2977 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
2978 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
2979 }
2980}
2981
ff155a45
VT		 2982struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2983 void (*trigger)(void *),
2984 void (*overflow)(void *),
2985 void *arg,
2986 u8 timer_index)
2987{
2988 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2989 struct ath_gen_timer *timer;
2990
c67ce339 2991 if ((timer_index < AR_FIRST_NDP_TIMER) ||
f4c34af4
SM		 2992 (timer_index >= ATH_MAX_GEN_TIMER))
2993 return NULL;
2994
2995 if ((timer_index > AR_FIRST_NDP_TIMER) &&
2996 !AR_SREV_9300_20_OR_LATER(ah))
c67ce339
FF		 2997 return NULL;
2998
ff155a45 2999 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 3000 if (timer == NULL)
ff155a45 3001 return NULL;
ff155a45
VT		 3002
3003 /* allocate a hardware generic timer slot */
3004 timer_table->timers[timer_index] = timer;
3005 timer->index = timer_index;
3006 timer->trigger = trigger;
3007 timer->overflow = overflow;
3008 timer->arg = arg;
3009
f4c34af4
SM		 3010 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
3011 timer_table->tsf2_enabled = true;
3012 ath9k_hw_gen_timer_start_tsf2(ah);
3013 }
3014
ff155a45
VT		 3015 return timer;
3016}
7322fd19 3017EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3018
cd9bf689
LR		 3019void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3020 struct ath_gen_timer *timer,
c67ce339 3021 u32 timer_next,
cd9bf689 3022 u32 timer_period)
ff155a45
VT		 3023{
3024 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 3025 u32 mask = 0;
788f6875 3026
c67ce339 3027 timer_table->timer_mask |= BIT(timer->index);
ff155a45 3028
ff155a45
VT		 3029 /*
3030 * Program generic timer registers
3031 */
3032 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3033 timer_next);
3034 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3035 timer_period);
3036 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3037 gen_tmr_configuration[timer->index].mode_mask);
3038
a4a2954f 3039 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 3040 /*
423e38e8 3041 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3042 * to use. But we still follow the old rule, 0 - 7 use tsf and
3043 * 8 - 15 use tsf2.
3044 */
3045 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3046 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3047 (1 << timer->index));
3048 else
3049 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3050 (1 << timer->index));
3051 }
3052
c67ce339
FF		 3053 if (timer->trigger)
3054 mask |= SM(AR_GENTMR_BIT(timer->index),
3055 AR_IMR_S5_GENTIMER_TRIG);
3056 if (timer->overflow)
3057 mask |= SM(AR_GENTMR_BIT(timer->index),
3058 AR_IMR_S5_GENTIMER_THRESH);
3059
3060 REG_SET_BIT(ah, AR_IMR_S5, mask);
3061
3062 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3063 ah->imask |= ATH9K_INT_GENTIMER;
3064 ath9k_hw_set_interrupts(ah);
3065 }
ff155a45 3066}
7322fd19 3067EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3068
cd9bf689 3069void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3070{
3071 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3072
ff155a45
VT		 3073 /* Clear generic timer enable bits. */
3074 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3075 gen_tmr_configuration[timer->index].mode_mask);
3076
b7f59766
SM		 3077 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3078 /*
3079 * Need to switch back to TSF if it was using TSF2.
3080 */
3081 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3082 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3083 (1 << timer->index));
3084 }
3085 }
3086
ff155a45
VT		 3087 /* Disable both trigger and thresh interrupt masks */
3088 REG_CLR_BIT(ah, AR_IMR_S5,
3089 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3090 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3091
c67ce339
FF		 3092 timer_table->timer_mask &= ~BIT(timer->index);
3093
3094 if (timer_table->timer_mask == 0) {
3095 ah->imask &= ~ATH9K_INT_GENTIMER;
3096 ath9k_hw_set_interrupts(ah);
3097 }
ff155a45 3098}
7322fd19 3099EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3100
3101void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3102{
3103 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3104
3105 /* free the hardware generic timer slot */
3106 timer_table->timers[timer->index] = NULL;
3107 kfree(timer);
3108}
7322fd19 3109EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3110
3111/*
3112 * Generic Timer Interrupts handling
3113 */
3114void ath_gen_timer_isr(struct ath_hw *ah)
3115{
3116 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3117 struct ath_gen_timer *timer;
c67ce339
FF		 3118 unsigned long trigger_mask, thresh_mask;
3119 unsigned int index;
ff155a45
VT		 3120
3121 /* get hardware generic timer interrupt status */
3122 trigger_mask = ah->intr_gen_timer_trigger;
3123 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 3124 trigger_mask &= timer_table->timer_mask;
3125 thresh_mask &= timer_table->timer_mask;
ff155a45 3126
c67ce339 3127 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3128 timer = timer_table->timers[index];
c67ce339
FF		 3129 if (!timer)
3130 continue;
3131 if (!timer->overflow)
3132 continue;
a6a172b2
FF		 3133
3134 trigger_mask &= ~BIT(index);
ff155a45
VT		 3135 timer->overflow(timer->arg);
3136 }
3137
c67ce339 3138 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3139 timer = timer_table->timers[index];
c67ce339
FF		 3140 if (!timer)
3141 continue;
3142 if (!timer->trigger)
3143 continue;
ff155a45
VT		 3144 timer->trigger(timer->arg);
3145 }
3146}
7322fd19 3147EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3148
05020d23
S		 3149/********/
3150/* HTC */
3151/********/
3152
2da4f01a
LR		 3153static struct {
3154 u32 version;
3155 const char * name;
3156} ath_mac_bb_names[] = {
3157 /* Devices with external radios */
3158 { AR_SREV_VERSION_5416_PCI, "5416" },
3159 { AR_SREV_VERSION_5416_PCIE, "5418" },
3160 { AR_SREV_VERSION_9100, "9100" },
3161 { AR_SREV_VERSION_9160, "9160" },
3162 /* Single-chip solutions */
3163 { AR_SREV_VERSION_9280, "9280" },
3164 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3165 { AR_SREV_VERSION_9287, "9287" },
3166 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3167 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3168 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3169 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3170 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3171 { AR_SREV_VERSION_9462, "9462" },
485124cb 3172 { AR_SREV_VERSION_9550, "9550" },
77fac465 3173 { AR_SREV_VERSION_9565, "9565" },
c08148bb 3174 { AR_SREV_VERSION_9531, "9531" },
2da4f01a
LR		 3175};
3176
3177/* For devices with external radios */
3178static struct {
3179 u16 version;
3180 const char * name;
3181} ath_rf_names[] = {
3182 { 0, "5133" },
3183 { AR_RAD5133_SREV_MAJOR, "5133" },
3184 { AR_RAD5122_SREV_MAJOR, "5122" },
3185 { AR_RAD2133_SREV_MAJOR, "2133" },
3186 { AR_RAD2122_SREV_MAJOR, "2122" }
3187};
3188
3189/*
3190 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3191 */
f934c4d9 3192static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3193{
3194 int i;
3195
3196 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3197 if (ath_mac_bb_names[i].version == mac_bb_version) {
3198 return ath_mac_bb_names[i].name;
3199 }
3200 }
3201
3202 return "????";
3203}
2da4f01a
LR		 3204
3205/*
3206 * Return the RF name. "????" is returned if the RF is unknown.
3207 * Used for devices with external radios.
3208 */
f934c4d9 3209static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3210{
3211 int i;
3212
3213 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3214 if (ath_rf_names[i].version == rf_version) {
3215 return ath_rf_names[i].name;
3216 }
3217 }
3218
3219 return "????";
3220}
f934c4d9
LR		 3221
3222void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3223{
3224 int used;
3225
3226 /* chipsets >= AR9280 are single-chip */
7a37081e 3227 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3228 used = scnprintf(hw_name, len,
3229 "Atheros AR%s Rev:%x",
3230 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3231 ah->hw_version.macRev);
f934c4d9
LR		 3232 }
3233 else {
5e88ba62
ZK		 3234 used = scnprintf(hw_name, len,
3235 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3236 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3237 ah->hw_version.macRev,
3238 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3239 & AR_RADIO_SREV_MAJOR)),
3240 ah->hw_version.phyRev);
f934c4d9
LR		 3241 }
3242
3243 hw_name[used] = '\0';
3244}
3245EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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