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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
f078f209
LR		 20#include <asm/unaligned.h>
21
af03abec 22#include "hw.h"
d70357d5 23#include "hw-ops.h"
cfe8cba9 24#include "rc.h"
b622a720 25#include "ar9003_mac.h"
f4701b5a 26#include "ar9003_mci.h"
462e58f2
BG		 27#include "debug.h"
28#include "ath9k.h"
f078f209 29
cbe61d8a 30static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 31
7322fd19
LR		 32MODULE_AUTHOR("Atheros Communications");
33MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
34MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
35MODULE_LICENSE("Dual BSD/GPL");
36
37static int __init ath9k_init(void)
38{
39 return 0;
40}
41module_init(ath9k_init);
42
43static void __exit ath9k_exit(void)
44{
45 return;
46}
47module_exit(ath9k_exit);
48
d70357d5
LR		 49/* Private hardware callbacks */
50
51static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
52{
53 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
54}
55
56static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
57{
58 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
59}
60
64773964
LR		 61static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
62 struct ath9k_channel *chan)
63{
64 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
65}
66
991312d8
LR		 67static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
68{
69 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
70 return;
71
72 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
73}
74
e36b27af
LR		 75static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
76{
77 /* You will not have this callback if using the old ANI */
78 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
79 return;
80
81 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
82}
83
f1dc5600
S		 84/********************/
85/* Helper Functions */
86/********************/
f078f209 87
462e58f2
BG		 88#ifdef CONFIG_ATH9K_DEBUGFS
89
90void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
91{
92 struct ath_softc *sc = common->priv;
93 if (sync_cause)
94 sc->debug.stats.istats.sync_cause_all++;
95 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
96 sc->debug.stats.istats.sync_rtc_irq++;
97 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
98 sc->debug.stats.istats.sync_mac_irq++;
99 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
100 sc->debug.stats.istats.eeprom_illegal_access++;
101 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
102 sc->debug.stats.istats.apb_timeout++;
103 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
104 sc->debug.stats.istats.pci_mode_conflict++;
105 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
106 sc->debug.stats.istats.host1_fatal++;
107 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
108 sc->debug.stats.istats.host1_perr++;
109 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
110 sc->debug.stats.istats.trcv_fifo_perr++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
112 sc->debug.stats.istats.radm_cpl_ep++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
114 sc->debug.stats.istats.radm_cpl_dllp_abort++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
116 sc->debug.stats.istats.radm_cpl_tlp_abort++;
117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
118 sc->debug.stats.istats.radm_cpl_ecrc_err++;
119 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
120 sc->debug.stats.istats.radm_cpl_timeout++;
121 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
122 sc->debug.stats.istats.local_timeout++;
123 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
124 sc->debug.stats.istats.pm_access++;
125 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
126 sc->debug.stats.istats.mac_awake++;
127 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
128 sc->debug.stats.istats.mac_asleep++;
129 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
130 sc->debug.stats.istats.mac_sleep_access++;
131}
132#endif
133
134
dfdac8ac 135static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 136{
b002a4a9 137 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
dfdac8ac
FF		 138 struct ath_common *common = ath9k_hw_common(ah);
139 unsigned int clockrate;
cbe61d8a 140
087b6ff6
FF		 141 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
142 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
143 clockrate = 117;
144 else if (!ah->curchan) /* should really check for CCK instead */
dfdac8ac
FF		 145 clockrate = ATH9K_CLOCK_RATE_CCK;
146 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
147 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
148 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
149 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 150 else
dfdac8ac
FF		 151 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
152
153 if (conf_is_ht40(conf))
154 clockrate *= 2;
155
906c7205
FF		 156 if (ah->curchan) {
157 if (IS_CHAN_HALF_RATE(ah->curchan))
158 clockrate /= 2;
159 if (IS_CHAN_QUARTER_RATE(ah->curchan))
160 clockrate /= 4;
161 }
162
dfdac8ac 163 common->clockrate = clockrate;
f1dc5600
S		 164}
165
cbe61d8a 166static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 167{
dfdac8ac 168 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 169
dfdac8ac 170 return usecs * common->clockrate;
f1dc5600 171}
f078f209 172
0caa7b14 173bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 174{
175 int i;
176
0caa7b14
S		 177 BUG_ON(timeout < AH_TIME_QUANTUM);
178
179 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 180 if ((REG_READ(ah, reg) & mask) == val)
181 return true;
182
183 udelay(AH_TIME_QUANTUM);
184 }
04bd4638 185
d2182b69 186 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 187 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
188 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 189
f1dc5600 190 return false;
f078f209 191}
7322fd19 192EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 193
a9b6b256
FF		 194void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
195 int column, unsigned int *writecnt)
196{
197 int r;
198
199 ENABLE_REGWRITE_BUFFER(ah);
200 for (r = 0; r < array->ia_rows; r++) {
201 REG_WRITE(ah, INI_RA(array, r, 0),
202 INI_RA(array, r, column));
203 DO_DELAY(*writecnt);
204 }
205 REGWRITE_BUFFER_FLUSH(ah);
206}
207
f078f209
LR		 208u32 ath9k_hw_reverse_bits(u32 val, u32 n)
209{
210 u32 retval;
211 int i;
212
213 for (i = 0, retval = 0; i < n; i++) {
214 retval = (retval << 1) | (val & 1);
215 val >>= 1;
216 }
217 return retval;
218}
219
cbe61d8a 220u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 221 u8 phy, int kbps,
f1dc5600
S		 222 u32 frameLen, u16 rateix,
223 bool shortPreamble)
f078f209 224{
f1dc5600 225 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 226
f1dc5600
S		 227 if (kbps == 0)
228 return 0;
f078f209 229
545750d3 230 switch (phy) {
46d14a58 231 case WLAN_RC_PHY_CCK:
f1dc5600 232 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 233 if (shortPreamble)
f1dc5600
S		 234 phyTime >>= 1;
235 numBits = frameLen << 3;
236 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
237 break;
46d14a58 238 case WLAN_RC_PHY_OFDM:
2660b81a 239 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 240 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
241 numBits = OFDM_PLCP_BITS + (frameLen << 3);
242 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
243 txTime = OFDM_SIFS_TIME_QUARTER
244 + OFDM_PREAMBLE_TIME_QUARTER
245 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 246 } else if (ah->curchan &&
247 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 248 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
249 numBits = OFDM_PLCP_BITS + (frameLen << 3);
250 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
251 txTime = OFDM_SIFS_TIME_HALF +
252 OFDM_PREAMBLE_TIME_HALF
253 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
254 } else {
255 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
256 numBits = OFDM_PLCP_BITS + (frameLen << 3);
257 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
258 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
259 + (numSymbols * OFDM_SYMBOL_TIME);
260 }
261 break;
262 default:
3800276a
JP		 263 ath_err(ath9k_hw_common(ah),
264 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 265 txTime = 0;
266 break;
267 }
f078f209 268
f1dc5600
S		 269 return txTime;
270}
7322fd19 271EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 272
cbe61d8a 273void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 274 struct ath9k_channel *chan,
275 struct chan_centers *centers)
f078f209 276{
f1dc5600 277 int8_t extoff;
f078f209 278
f1dc5600
S		 279 if (!IS_CHAN_HT40(chan)) {
280 centers->ctl_center = centers->ext_center =
281 centers->synth_center = chan->channel;
282 return;
f078f209 283 }
f078f209 284
f1dc5600
S		 285 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
286 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
287 centers->synth_center =
288 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
289 extoff = 1;
290 } else {
291 centers->synth_center =
292 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
293 extoff = -1;
294 }
f078f209 295
f1dc5600
S		 296 centers->ctl_center =
297 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 298 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 299 centers->ext_center =
6420014c 300 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 301}
302
f1dc5600
S		 303/******************/
304/* Chip Revisions */
305/******************/
306
cbe61d8a 307static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 308{
f1dc5600 309 u32 val;
f078f209 310
ecb1d385
VT		 311 switch (ah->hw_version.devid) {
312 case AR5416_AR9100_DEVID:
313 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
314 break;
3762561a
GJ		 315 case AR9300_DEVID_AR9330:
316 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
317 if (ah->get_mac_revision) {
318 ah->hw_version.macRev = ah->get_mac_revision();
319 } else {
320 val = REG_READ(ah, AR_SREV);
321 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
322 }
323 return;
ecb1d385
VT		 324 case AR9300_DEVID_AR9340:
325 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
326 val = REG_READ(ah, AR_SREV);
327 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
328 return;
329 }
330
f1dc5600 331 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 332
f1dc5600
S		 333 if (val == 0xFF) {
334 val = REG_READ(ah, AR_SREV);
d535a42a
S		 335 ah->hw_version.macVersion =
336 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
337 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 338
423e38e8 339 if (AR_SREV_9462(ah))
76ed94be
MSS		 340 ah->is_pciexpress = true;
341 else
342 ah->is_pciexpress = (val &
343 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 344 } else {
345 if (!AR_SREV_9100(ah))
d535a42a 346 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 347
d535a42a 348 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 349
d535a42a 350 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 351 ah->is_pciexpress = true;
f1dc5600 352 }
f078f209
LR		 353}
354
f1dc5600
S		 355/************************************/
356/* HW Attach, Detach, Init Routines */
357/************************************/
358
cbe61d8a 359static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 360{
040b74f7 361 if (!AR_SREV_5416(ah))
f1dc5600 362 return;
f078f209 363
f1dc5600
S		 364 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
365 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
366 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
367 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
368 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
369 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
370 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
371 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
372 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 373
f1dc5600 374 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 375}
376
d4930086
SG		 377static void ath9k_hw_aspm_init(struct ath_hw *ah)
378{
379 struct ath_common *common = ath9k_hw_common(ah);
380
381 if (common->bus_ops->aspm_init)
382 common->bus_ops->aspm_init(common);
383}
384
1f3f0618 385/* This should work for all families including legacy */
cbe61d8a 386static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 387{
c46917bb 388 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 389 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 390 u32 regHold[2];
07b2fa5a
JP		 391 static const u32 patternData[4] = {
392 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
393 };
1f3f0618 394 int i, j, loop_max;
f078f209 395
1f3f0618
SB		 396 if (!AR_SREV_9300_20_OR_LATER(ah)) {
397 loop_max = 2;
398 regAddr[1] = AR_PHY_BASE + (8 << 2);
399 } else
400 loop_max = 1;
401
402 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 403 u32 addr = regAddr[i];
404 u32 wrData, rdData;
f078f209 405
f1dc5600
S		 406 regHold[i] = REG_READ(ah, addr);
407 for (j = 0; j < 0x100; j++) {
408 wrData = (j << 16) | j;
409 REG_WRITE(ah, addr, wrData);
410 rdData = REG_READ(ah, addr);
411 if (rdData != wrData) {
3800276a
JP		 412 ath_err(common,
413 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
414 addr, wrData, rdData);
f1dc5600
S		 415 return false;
416 }
417 }
418 for (j = 0; j < 4; j++) {
419 wrData = patternData[j];
420 REG_WRITE(ah, addr, wrData);
421 rdData = REG_READ(ah, addr);
422 if (wrData != rdData) {
3800276a
JP		 423 ath_err(common,
424 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
425 addr, wrData, rdData);
f1dc5600
S		 426 return false;
427 }
f078f209 428 }
f1dc5600 429 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 430 }
f1dc5600 431 udelay(100);
cbe61d8a 432
f078f209
LR		 433 return true;
434}
435
b8b0f377 436static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 437{
438 int i;
f078f209 439
689e756f
FF		 440 ah->config.dma_beacon_response_time = 1;
441 ah->config.sw_beacon_response_time = 6;
2660b81a
S		 442 ah->config.additional_swba_backoff = 0;
443 ah->config.ack_6mb = 0x0;
444 ah->config.cwm_ignore_extcca = 0;
2660b81a 445 ah->config.pcie_clock_req = 0;
2660b81a
S		 446 ah->config.pcie_waen = 0;
447 ah->config.analog_shiftreg = 1;
03c72518 448 ah->config.enable_ani = true;
f078f209 449
f1dc5600 450 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 451 ah->config.spurchans[i][0] = AR_NO_SPUR;
452 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 453 }
454
6f481010
LR		 455 /* PAPRD needs some more work to be enabled */
456 ah->config.paprd_disable = 1;
457
0ce024cb 458 ah->config.rx_intr_mitigation = true;
6a0ec30a 459 ah->config.pcieSerDesWrite = true;
6158425b
LR		 460
461 /*
462 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
463 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
464 * This means we use it for all AR5416 devices, and the few
465 * minor PCI AR9280 devices out there.
466 *
467 * Serialization is required because these devices do not handle
468 * well the case of two concurrent reads/writes due to the latency
469 * involved. During one read/write another read/write can be issued
470 * on another CPU while the previous read/write may still be working
471 * on our hardware, if we hit this case the hardware poops in a loop.
472 * We prevent this by serializing reads and writes.
473 *
474 * This issue is not present on PCI-Express devices or pre-AR5416
475 * devices (legacy, 802.11abg).
476 */
477 if (num_possible_cpus() > 1)
2d6a5e95 478 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 479}
480
50aca25b 481static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 482{
608b88cb
LR		 483 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
484
485 regulatory->country_code = CTRY_DEFAULT;
486 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 487
d535a42a 488 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 489 ah->hw_version.subvendorid = 0;
f078f209 490
2660b81a 491 ah->atim_window = 0;
16f2411f
FF		 492 ah->sta_id1_defaults =
493 AR_STA_ID1_CRPT_MIC_ENABLE |
494 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 495 if (AR_SREV_9100(ah))
496 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
e3f2acc7 497 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 498 ah->globaltxtimeout = (u32) -1;
cbdec975 499 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 500 ah->htc_reset_init = true;
f078f209
LR		 501}
502
cbe61d8a 503static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 504{
1510718d 505 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 506 u32 sum;
507 int i;
508 u16 eeval;
07b2fa5a 509 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 510
511 sum = 0;
512 for (i = 0; i < 3; i++) {
49101676 513 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 514 sum += eeval;
1510718d
LR		 515 common->macaddr[2 * i] = eeval >> 8;
516 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 517 }
d8baa939 518 if (sum == 0 || sum == 0xffff * 3)
f078f209 519 return -EADDRNOTAVAIL;
f078f209
LR		 520
521 return 0;
522}
523
f637cfd6 524static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 525{
6cae913d 526 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 527 int ecode;
f078f209 528
6cae913d 529 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 530 if (!ath9k_hw_chip_test(ah))
531 return -ENODEV;
532 }
f078f209 533
ebd5a14a
LR		 534 if (!AR_SREV_9300_20_OR_LATER(ah)) {
535 ecode = ar9002_hw_rf_claim(ah);
536 if (ecode != 0)
537 return ecode;
538 }
f078f209 539
f637cfd6 540 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 541 if (ecode != 0)
542 return ecode;
7d01b221 543
d2182b69 544 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 545 ah->eep_ops->get_eeprom_ver(ah),
546 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 547
8fe65368
LR		 548 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
549 if (ecode) {
3800276a
JP		 550 ath_err(ath9k_hw_common(ah),
551 "Failed allocating banks for external radio\n");
48a7c3df 552 ath9k_hw_rf_free_ext_banks(ah);
8fe65368 553 return ecode;
574d6b12 554 }
f078f209 555
4279425c 556 if (ah->config.enable_ani) {
f1dc5600 557 ath9k_hw_ani_setup(ah);
f637cfd6 558 ath9k_hw_ani_init(ah);
f078f209
LR		 559 }
560
f078f209
LR		 561 return 0;
562}
563
8525f280 564static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 565{
8525f280
LR		 566 if (AR_SREV_9300_20_OR_LATER(ah))
567 ar9003_hw_attach_ops(ah);
568 else
569 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 570}
571
d70357d5
LR		 572/* Called for all hardware families */
573static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 574{
c46917bb 575 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 576 int r = 0;
aa4058ae 577
ac45c12d
SB		 578 ath9k_hw_read_revisions(ah);
579
0a8d7cb0
SB		 580 /*
581 * Read back AR_WA into a permanent copy and set bits 14 and 17.
582 * We need to do this to avoid RMW of this register. We cannot
583 * read the reg when chip is asleep.
584 */
585 ah->WARegVal = REG_READ(ah, AR_WA);
586 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
587 AR_WA_ASPM_TIMER_BASED_DISABLE);
588
aa4058ae 589 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 590 ath_err(common, "Couldn't reset chip\n");
95fafca2 591 return -EIO;
aa4058ae
LR		 592 }
593
423e38e8 594 if (AR_SREV_9462(ah))
eec353c5
RM		 595 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
596
bab1f62e
LR		 597 ath9k_hw_init_defaults(ah);
598 ath9k_hw_init_config(ah);
599
8525f280 600 ath9k_hw_attach_ops(ah);
d70357d5 601
9ecdef4b 602 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 603 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 604 return -EIO;
aa4058ae
LR		 605 }
606
f3eef645 607 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
aa4058ae 608 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
4c85ab11
JL		 609 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
610 !ah->is_pciexpress)) {
aa4058ae
LR		 611 ah->config.serialize_regmode =
612 SER_REG_MODE_ON;
613 } else {
614 ah->config.serialize_regmode =
615 SER_REG_MODE_OFF;
616 }
617 }
618
d2182b69 619 ath_dbg(common, RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 620 ah->config.serialize_regmode);
621
f4709fdf
LR		 622 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
623 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
624 else
625 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
626
6da5a720
FF		 627 switch (ah->hw_version.macVersion) {
628 case AR_SREV_VERSION_5416_PCI:
629 case AR_SREV_VERSION_5416_PCIE:
630 case AR_SREV_VERSION_9160:
631 case AR_SREV_VERSION_9100:
632 case AR_SREV_VERSION_9280:
633 case AR_SREV_VERSION_9285:
634 case AR_SREV_VERSION_9287:
635 case AR_SREV_VERSION_9271:
636 case AR_SREV_VERSION_9300:
2c8e5937 637 case AR_SREV_VERSION_9330:
6da5a720 638 case AR_SREV_VERSION_9485:
bca04689 639 case AR_SREV_VERSION_9340:
423e38e8 640 case AR_SREV_VERSION_9462:
6da5a720
FF		 641 break;
642 default:
3800276a
JP		 643 ath_err(common,
644 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
645 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 646 return -EOPNOTSUPP;
aa4058ae
LR		 647 }
648
2c8e5937
GJ		 649 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
650 AR_SREV_9330(ah))
d7e7d229
LR		 651 ah->is_pciexpress = false;
652
aa4058ae 653 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 654 ath9k_hw_init_cal_settings(ah);
655
656 ah->ani_function = ATH9K_ANI_ALL;
7a37081e 657 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 658 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 659 if (!AR_SREV_9300_20_OR_LATER(ah))
660 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae 661
4f17c48e
NM		 662 /* disable ANI for 9340 */
663 if (AR_SREV_9340(ah))
4279425c
NM		 664 ah->config.enable_ani = false;
665
aa4058ae
LR		 666 ath9k_hw_init_mode_regs(ah);
667
69ce674b 668 if (!ah->is_pciexpress)
aa4058ae
LR		 669 ath9k_hw_disablepcie(ah);
670
f637cfd6 671 r = ath9k_hw_post_init(ah);
aa4058ae 672 if (r)
95fafca2 673 return r;
aa4058ae
LR		 674
675 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 676 r = ath9k_hw_fill_cap_info(ah);
677 if (r)
678 return r;
679
69ce674b
SG		 680 if (ah->is_pciexpress)
681 ath9k_hw_aspm_init(ah);
682
4f3acf81
LR		 683 r = ath9k_hw_init_macaddr(ah);
684 if (r) {
3800276a 685 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 686 return r;
f078f209
LR		 687 }
688
d7e7d229 689 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 690 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 691 else
2660b81a 692 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 693
88e641df
GJ		 694 if (AR_SREV_9330(ah))
695 ah->bb_watchdog_timeout_ms = 85;
696 else
697 ah->bb_watchdog_timeout_ms = 25;
f078f209 698
211f5859
LR		 699 common->state = ATH_HW_INITIALIZED;
700
4f3acf81 701 return 0;
f078f209
LR		 702}
703
d70357d5 704int ath9k_hw_init(struct ath_hw *ah)
f078f209 705{
d70357d5
LR		 706 int ret;
707 struct ath_common *common = ath9k_hw_common(ah);
f078f209 708
d70357d5
LR		 709 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
710 switch (ah->hw_version.devid) {
711 case AR5416_DEVID_PCI:
712 case AR5416_DEVID_PCIE:
713 case AR5416_AR9100_DEVID:
714 case AR9160_DEVID_PCI:
715 case AR9280_DEVID_PCI:
716 case AR9280_DEVID_PCIE:
717 case AR9285_DEVID_PCIE:
db3cc53a
SB		 718 case AR9287_DEVID_PCI:
719 case AR9287_DEVID_PCIE:
d70357d5 720 case AR2427_DEVID_PCIE:
db3cc53a 721 case AR9300_DEVID_PCIE:
3050c914 722 case AR9300_DEVID_AR9485_PCIE:
999a7a88 723 case AR9300_DEVID_AR9330:
bca04689 724 case AR9300_DEVID_AR9340:
5a63ef0f 725 case AR9300_DEVID_AR9580:
423e38e8 726 case AR9300_DEVID_AR9462:
d70357d5
LR		 727 break;
728 default:
729 if (common->bus_ops->ath_bus_type == ATH_USB)
730 break;
3800276a
JP		 731 ath_err(common, "Hardware device ID 0x%04x not supported\n",
732 ah->hw_version.devid);
d70357d5
LR		 733 return -EOPNOTSUPP;
734 }
f078f209 735
d70357d5
LR		 736 ret = __ath9k_hw_init(ah);
737 if (ret) {
3800276a
JP		 738 ath_err(common,
739 "Unable to initialize hardware; initialization status: %d\n",
740 ret);
d70357d5
LR		 741 return ret;
742 }
f078f209 743
d70357d5 744 return 0;
f078f209 745}
d70357d5 746EXPORT_SYMBOL(ath9k_hw_init);
f078f209 747
cbe61d8a 748static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 749{
7d0d0df0
S		 750 ENABLE_REGWRITE_BUFFER(ah);
751
f1dc5600
S		 752 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
753 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 754
f1dc5600
S		 755 REG_WRITE(ah, AR_QOS_NO_ACK,
756 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
757 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
758 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
759
760 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
761 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
762 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
763 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
764 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 765
766 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 767}
768
b84628eb 769u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 770{
ca7a4deb
FF		 771 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
772 udelay(100);
773 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 774
ca7a4deb
FF		 775 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
776 udelay(100);
b1415819 777
ca7a4deb 778 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 779}
780EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
781
cbe61d8a 782static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 783 struct ath9k_channel *chan)
f078f209 784{
d09b17f7
VT		 785 u32 pll;
786
22983c30 787 if (AR_SREV_9485(ah)) {
22983c30 788
3dfd7f60
VT		 789 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
790 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
791 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
792 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
793 AR_CH0_DPLL2_KD, 0x40);
794 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
795 AR_CH0_DPLL2_KI, 0x4);
22983c30 796
3dfd7f60
VT		 797 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
798 AR_CH0_BB_DPLL1_REFDIV, 0x5);
799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
800 AR_CH0_BB_DPLL1_NINI, 0x58);
801 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
802 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 803
804 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 805 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
806 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
807 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 808 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 809 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 810
3dfd7f60 811 /* program BB PLL phase_shift to 0x6 */
22983c30 812 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 813 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
814
815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
816 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 817 udelay(1000);
a5415d62
GJ		 818 } else if (AR_SREV_9330(ah)) {
819 u32 ddr_dpll2, pll_control2, kd;
820
821 if (ah->is_clk_25mhz) {
822 ddr_dpll2 = 0x18e82f01;
823 pll_control2 = 0xe04a3d;
824 kd = 0x1d;
825 } else {
826 ddr_dpll2 = 0x19e82f01;
827 pll_control2 = 0x886666;
828 kd = 0x3d;
829 }
830
831 /* program DDR PLL ki and kd value */
832 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
833
834 /* program DDR PLL phase_shift */
835 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
836 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
837
838 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
839 udelay(1000);
840
841 /* program refdiv, nint, frac to RTC register */
842 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
843
844 /* program BB PLL kd and ki value */
845 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
846 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
847
848 /* program BB PLL phase_shift */
849 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
850 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
0b488ac6
VT		 851 } else if (AR_SREV_9340(ah)) {
852 u32 regval, pll2_divint, pll2_divfrac, refdiv;
853
854 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
855 udelay(1000);
856
857 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
858 udelay(100);
859
860 if (ah->is_clk_25mhz) {
861 pll2_divint = 0x54;
862 pll2_divfrac = 0x1eb85;
863 refdiv = 3;
864 } else {
865 pll2_divint = 88;
866 pll2_divfrac = 0;
867 refdiv = 5;
868 }
869
870 regval = REG_READ(ah, AR_PHY_PLL_MODE);
871 regval |= (0x1 << 16);
872 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
873 udelay(100);
874
875 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
876 (pll2_divint << 18) | pll2_divfrac);
877 udelay(100);
878
879 regval = REG_READ(ah, AR_PHY_PLL_MODE);
880 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
881 (0x4 << 26) | (0x18 << 19);
882 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
883 REG_WRITE(ah, AR_PHY_PLL_MODE,
884 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
885 udelay(1000);
22983c30 886 }
d09b17f7
VT		 887
888 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 889
d03a66c1 890 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 891
a5415d62 892 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
3dfd7f60
VT		 893 udelay(1000);
894
c75724d1
LR		 895 /* Switch the core clock for ar9271 to 117Mhz */
896 if (AR_SREV_9271(ah)) {
25e2ab17
S		 897 udelay(500);
898 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 899 }
900
f1dc5600
S		 901 udelay(RTC_PLL_SETTLE_DELAY);
902
903 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6
VT		 904
905 if (AR_SREV_9340(ah)) {
906 if (ah->is_clk_25mhz) {
907 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
908 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
909 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
910 } else {
911 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
912 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
913 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
914 }
915 udelay(100);
916 }
f078f209
LR		 917}
918
cbe61d8a 919static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 920 enum nl80211_iftype opmode)
f078f209 921{
79d1d2b8 922 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 923 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 924 AR_IMR_TXURN |
925 AR_IMR_RXERR |
926 AR_IMR_RXORN |
927 AR_IMR_BCNMISC;
f078f209 928
79d1d2b8
VT		 929 if (AR_SREV_9340(ah))
930 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
931
66860240
VT		 932 if (AR_SREV_9300_20_OR_LATER(ah)) {
933 imr_reg |= AR_IMR_RXOK_HP;
934 if (ah->config.rx_intr_mitigation)
935 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
936 else
937 imr_reg |= AR_IMR_RXOK_LP;
f078f209 938
66860240
VT		 939 } else {
940 if (ah->config.rx_intr_mitigation)
941 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
942 else
943 imr_reg |= AR_IMR_RXOK;
944 }
f078f209 945
66860240
VT		 946 if (ah->config.tx_intr_mitigation)
947 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
948 else
949 imr_reg |= AR_IMR_TXOK;
f078f209 950
d97809db 951 if (opmode == NL80211_IFTYPE_AP)
152d530d 952 imr_reg |= AR_IMR_MIB;
f078f209 953
7d0d0df0
S		 954 ENABLE_REGWRITE_BUFFER(ah);
955
152d530d 956 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 957 ah->imrs2_reg |= AR_IMR_S2_GTT;
958 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 959
f1dc5600
S		 960 if (!AR_SREV_9100(ah)) {
961 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 962 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 963 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
964 }
66860240 965
7d0d0df0 966 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 967
66860240
VT		 968 if (AR_SREV_9300_20_OR_LATER(ah)) {
969 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
970 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
971 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
972 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
973 }
f078f209
LR		 974}
975
b6ba41bb
FF		 976static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
977{
978 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
979 val = min(val, (u32) 0xFFFF);
980 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
981}
982
0005baf4 983static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 984{
0005baf4
FF		 985 u32 val = ath9k_hw_mac_to_clks(ah, us);
986 val = min(val, (u32) 0xFFFF);
987 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 988}
989
0005baf4 990static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 991{
0005baf4
FF		 992 u32 val = ath9k_hw_mac_to_clks(ah, us);
993 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
994 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
995}
996
997static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
998{
999 u32 val = ath9k_hw_mac_to_clks(ah, us);
1000 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1001 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 1002}
f1dc5600 1003
cbe61d8a 1004static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1005{
f078f209 1006 if (tu > 0xFFFF) {
d2182b69
JP		 1007 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1008 tu);
2660b81a 1009 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1010 return false;
1011 } else {
1012 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1013 ah->globaltxtimeout = tu;
f078f209
LR		 1014 return true;
1015 }
1016}
1017
0005baf4 1018void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1019{
b6ba41bb
FF		 1020 struct ath_common *common = ath9k_hw_common(ah);
1021 struct ieee80211_conf *conf = &common->hw->conf;
1022 const struct ath9k_channel *chan = ah->curchan;
adb5066a 1023 int acktimeout, ctstimeout;
e239d859 1024 int slottime;
0005baf4 1025 int sifstime;
b6ba41bb
FF		 1026 int rx_lat = 0, tx_lat = 0, eifs = 0;
1027 u32 reg;
0005baf4 1028
d2182b69 1029 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1030 ah->misc_mode);
f078f209 1031
b6ba41bb
FF		 1032 if (!chan)
1033 return;
1034
2660b81a 1035 if (ah->misc_mode != 0)
ca7a4deb 1036 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1037
81a91d57
RM		 1038 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1039 rx_lat = 41;
1040 else
1041 rx_lat = 37;
b6ba41bb
FF		 1042 tx_lat = 54;
1043
1044 if (IS_CHAN_HALF_RATE(chan)) {
1045 eifs = 175;
1046 rx_lat *= 2;
1047 tx_lat *= 2;
1048 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1049 tx_lat += 11;
1050
1051 slottime = 13;
1052 sifstime = 32;
1053 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1054 eifs = 340;
81a91d57 1055 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1056 tx_lat *= 4;
1057 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1058 tx_lat += 22;
1059
1060 slottime = 21;
1061 sifstime = 64;
1062 } else {
a7be039d
RM		 1063 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1064 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1065 reg = AR_USEC_ASYNC_FIFO;
1066 } else {
1067 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1068 common->clockrate;
1069 reg = REG_READ(ah, AR_USEC);
1070 }
b6ba41bb
FF		 1071 rx_lat = MS(reg, AR_USEC_RX_LAT);
1072 tx_lat = MS(reg, AR_USEC_TX_LAT);
1073
1074 slottime = ah->slottime;
1075 if (IS_CHAN_5GHZ(chan))
1076 sifstime = 16;
1077 else
1078 sifstime = 10;
1079 }
0005baf4 1080
e239d859 1081 /* As defined by IEEE 802.11-2007 17.3.8.6 */
b6ba41bb 1082 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
adb5066a 1083 ctstimeout = acktimeout;
42c4568a
FF		 1084
1085 /*
1086 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1087 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1088 * This was initially only meant to work around an issue with delayed
1089 * BA frames in some implementations, but it has been found to fix ACK
1090 * timeout issues in other cases as well.
1091 */
55a2bb4a 1092 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) {
42c4568a 1093 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1094 ctstimeout += 48 - sifstime - ah->slottime;
1095 }
1096
42c4568a 1097
b6ba41bb
FF		 1098 ath9k_hw_set_sifs_time(ah, sifstime);
1099 ath9k_hw_setslottime(ah, slottime);
0005baf4 1100 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1101 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1102 if (ah->globaltxtimeout != (u32) -1)
1103 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1104
1105 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1106 REG_RMW(ah, AR_USEC,
1107 (common->clockrate - 1) |
1108 SM(rx_lat, AR_USEC_RX_LAT) |
1109 SM(tx_lat, AR_USEC_TX_LAT),
1110 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1111
f1dc5600 1112}
0005baf4 1113EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1114
285f2dda 1115void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1116{
211f5859
LR		 1117 struct ath_common *common = ath9k_hw_common(ah);
1118
736b3a27 1119 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 1120 goto free_hw;
1121
9ecdef4b 1122 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 1123
1124free_hw:
8fe65368 1125 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 1126}
285f2dda 1127EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1128
f1dc5600
S		 1129/*******/
1130/* INI */
1131/*******/
1132
8fe65368 1133u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1134{
1135 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1136
1137 if (IS_CHAN_B(chan))
1138 ctl |= CTL_11B;
1139 else if (IS_CHAN_G(chan))
1140 ctl |= CTL_11G;
1141 else
1142 ctl |= CTL_11A;
1143
1144 return ctl;
1145}
1146
f1dc5600
S		 1147/****************************************/
1148/* Reset and Channel Switching Routines */
1149/****************************************/
f1dc5600 1150
cbe61d8a 1151static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1152{
57b32227 1153 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 1154
7d0d0df0
S		 1155 ENABLE_REGWRITE_BUFFER(ah);
1156
d7e7d229
LR		 1157 /*
1158 * set AHB_MODE not to do cacheline prefetches
1159 */
ca7a4deb
FF		 1160 if (!AR_SREV_9300_20_OR_LATER(ah))
1161 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1162
d7e7d229
LR		 1163 /*
1164 * let mac dma reads be in 128 byte chunks
1165 */
ca7a4deb 1166 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1167
7d0d0df0 1168 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1169
d7e7d229
LR		 1170 /*
1171 * Restore TX Trigger Level to its pre-reset value.
1172 * The initial value depends on whether aggregation is enabled, and is
1173 * adjusted whenever underruns are detected.
1174 */
57b32227
FF		 1175 if (!AR_SREV_9300_20_OR_LATER(ah))
1176 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1177
7d0d0df0 1178 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1179
d7e7d229
LR		 1180 /*
1181 * let mac dma writes be in 128 byte chunks
1182 */
ca7a4deb 1183 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1184
d7e7d229
LR		 1185 /*
1186 * Setup receive FIFO threshold to hold off TX activities
1187 */
f1dc5600
S		 1188 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1189
57b32227
FF		 1190 if (AR_SREV_9300_20_OR_LATER(ah)) {
1191 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1192 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1193
1194 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1195 ah->caps.rx_status_len);
1196 }
1197
d7e7d229
LR		 1198 /*
1199 * reduce the number of usable entries in PCU TXBUF to avoid
1200 * wrap around issues.
1201 */
f1dc5600 1202 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1203 /* For AR9285 the number of Fifos are reduced to half.
1204 * So set the usable tx buf size also to half to
1205 * avoid data/delimiter underruns
1206 */
f1dc5600
S		 1207 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1208 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1209 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1210 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1211 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1212 }
744d4025 1213
7d0d0df0 1214 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1215
744d4025
VT		 1216 if (AR_SREV_9300_20_OR_LATER(ah))
1217 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1218}
1219
cbe61d8a 1220static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1221{
ca7a4deb
FF		 1222 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1223 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1224
f1dc5600 1225 switch (opmode) {
d97809db 1226 case NL80211_IFTYPE_ADHOC:
9cb5412b 1227 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb 1228 set |= AR_STA_ID1_ADHOC;
f1dc5600 1229 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1230 break;
ca7a4deb
FF		 1231 case NL80211_IFTYPE_AP:
1232 set |= AR_STA_ID1_STA_AP;
1233 /* fall through */
d97809db 1234 case NL80211_IFTYPE_STATION:
ca7a4deb 1235 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1236 break;
5f841b41 1237 default:
ca7a4deb
FF		 1238 if (!ah->is_monitoring)
1239 set = 0;
5f841b41 1240 break;
f1dc5600 1241 }
ca7a4deb 1242 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1243}
1244
8fe65368
LR		 1245void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1246 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1247{
1248 u32 coef_exp, coef_man;
1249
1250 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1251 if ((coef_scaled >> coef_exp) & 0x1)
1252 break;
1253
1254 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1255
1256 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1257
1258 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1259 *coef_exponent = coef_exp - 16;
1260}
1261
cbe61d8a 1262static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1263{
1264 u32 rst_flags;
1265 u32 tmpReg;
1266
70768496 1267 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1268 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1269 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1270 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1271 }
1272
7d0d0df0
S		 1273 ENABLE_REGWRITE_BUFFER(ah);
1274
9a658d2b
LR		 1275 if (AR_SREV_9300_20_OR_LATER(ah)) {
1276 REG_WRITE(ah, AR_WA, ah->WARegVal);
1277 udelay(10);
1278 }
1279
f1dc5600
S		 1280 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1281 AR_RTC_FORCE_WAKE_ON_INT);
1282
1283 if (AR_SREV_9100(ah)) {
1284 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1285 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1286 } else {
1287 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1288 if (tmpReg &
1289 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1290 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1291 u32 val;
f1dc5600 1292 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1293
1294 val = AR_RC_HOSTIF;
1295 if (!AR_SREV_9300_20_OR_LATER(ah))
1296 val |= AR_RC_AHB;
1297 REG_WRITE(ah, AR_RC, val);
1298
1299 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1300 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1301
1302 rst_flags = AR_RTC_RC_MAC_WARM;
1303 if (type == ATH9K_RESET_COLD)
1304 rst_flags |= AR_RTC_RC_MAC_COLD;
1305 }
1306
7d95847c
GJ		 1307 if (AR_SREV_9330(ah)) {
1308 int npend = 0;
1309 int i;
1310
1311 /* AR9330 WAR:
1312 * call external reset function to reset WMAC if:
1313 * - doing a cold reset
1314 * - we have pending frames in the TX queues
1315 */
1316
1317 for (i = 0; i < AR_NUM_QCU; i++) {
1318 npend = ath9k_hw_numtxpending(ah, i);
1319 if (npend)
1320 break;
1321 }
1322
1323 if (ah->external_reset &&
1324 (npend || type == ATH9K_RESET_COLD)) {
1325 int reset_err = 0;
1326
d2182b69 1327 ath_dbg(ath9k_hw_common(ah), RESET,
7d95847c
GJ		 1328 "reset MAC via external reset\n");
1329
1330 reset_err = ah->external_reset();
1331 if (reset_err) {
1332 ath_err(ath9k_hw_common(ah),
1333 "External reset failed, err=%d\n",
1334 reset_err);
1335 return false;
1336 }
1337
1338 REG_WRITE(ah, AR_RTC_RESET, 1);
1339 }
1340 }
1341
d03a66c1 1342 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1343
1344 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1345
f1dc5600
S		 1346 udelay(50);
1347
d03a66c1 1348 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1349 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1350 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1351 return false;
1352 }
1353
1354 if (!AR_SREV_9100(ah))
1355 REG_WRITE(ah, AR_RC, 0);
1356
f1dc5600
S		 1357 if (AR_SREV_9100(ah))
1358 udelay(50);
1359
1360 return true;
1361}
1362
cbe61d8a 1363static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1364{
7d0d0df0
S		 1365 ENABLE_REGWRITE_BUFFER(ah);
1366
9a658d2b
LR		 1367 if (AR_SREV_9300_20_OR_LATER(ah)) {
1368 REG_WRITE(ah, AR_WA, ah->WARegVal);
1369 udelay(10);
1370 }
1371
f1dc5600
S		 1372 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1373 AR_RTC_FORCE_WAKE_ON_INT);
1374
42d5bc3f 1375 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1376 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1377
d03a66c1 1378 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1379
7d0d0df0 1380 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1381
84e2169b
SB		 1382 if (!AR_SREV_9300_20_OR_LATER(ah))
1383 udelay(2);
1384
1385 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1386 REG_WRITE(ah, AR_RC, 0);
1387
d03a66c1 1388 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1389
1390 if (!ath9k_hw_wait(ah,
1391 AR_RTC_STATUS,
1392 AR_RTC_STATUS_M,
0caa7b14
S		 1393 AR_RTC_STATUS_ON,
1394 AH_WAIT_TIMEOUT)) {
d2182b69 1395 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1396 return false;
f078f209
LR		 1397 }
1398
f1dc5600
S		 1399 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1400}
1401
cbe61d8a 1402static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1403{
7a9233ff 1404 bool ret = false;
2577c6e8 1405
9a658d2b
LR		 1406 if (AR_SREV_9300_20_OR_LATER(ah)) {
1407 REG_WRITE(ah, AR_WA, ah->WARegVal);
1408 udelay(10);
1409 }
1410
f1dc5600
S		 1411 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1412 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1413
1414 switch (type) {
1415 case ATH9K_RESET_POWER_ON:
7a9233ff
MSS		 1416 ret = ath9k_hw_set_reset_power_on(ah);
1417 break;
f1dc5600
S		 1418 case ATH9K_RESET_WARM:
1419 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1420 ret = ath9k_hw_set_reset(ah, type);
1421 break;
f1dc5600 1422 default:
7a9233ff 1423 break;
f1dc5600 1424 }
7a9233ff
MSS		 1425
1426 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1427 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1428
1429 return ret;
f078f209
LR		 1430}
1431
cbe61d8a 1432static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1433 struct ath9k_channel *chan)
f078f209 1434{
9c083af8
FF		 1435 int reset_type = ATH9K_RESET_WARM;
1436
1437 if (AR_SREV_9280(ah)) {
1438 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1439 reset_type = ATH9K_RESET_POWER_ON;
1440 else
1441 reset_type = ATH9K_RESET_COLD;
1442 }
1443
1444 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1445 return false;
f078f209 1446
9ecdef4b 1447 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1448 return false;
f078f209 1449
2660b81a 1450 ah->chip_fullsleep = false;
f1dc5600 1451 ath9k_hw_init_pll(ah, chan);
f1dc5600 1452 ath9k_hw_set_rfmode(ah, chan);
f078f209 1453
f1dc5600 1454 return true;
f078f209
LR		 1455}
1456
cbe61d8a 1457static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1458 struct ath9k_channel *chan)
f078f209 1459{
c46917bb 1460 struct ath_common *common = ath9k_hw_common(ah);
8fe65368 1461 u32 qnum;
0a3b7bac 1462 int r;
5f0c04ea
RM		 1463 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1464 bool band_switch, mode_diff;
1465 u8 ini_reloaded;
1466
1467 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1468 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1469 CHANNEL_5GHZ));
1470 mode_diff = (chan->chanmode != ah->curchan->chanmode);
f078f209
LR		 1471
1472 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1473 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1474 ath_dbg(common, QUEUE,
226afe68 1475 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1476 return false;
1477 }
1478 }
1479
8fe65368 1480 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1481 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1482 return false;
1483 }
1484
5f0c04ea
RM		 1485 if (edma && (band_switch || mode_diff)) {
1486 ath9k_hw_mark_phy_inactive(ah);
1487 udelay(5);
1488
1489 ath9k_hw_init_pll(ah, NULL);
1490
1491 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1492 ath_err(common, "Failed to do fast channel change\n");
1493 return false;
1494 }
1495 }
1496
8fe65368 1497 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1498
8fe65368 1499 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1500 if (r) {
3800276a 1501 ath_err(common, "Failed to set channel\n");
0a3b7bac 1502 return false;
f078f209 1503 }
dfdac8ac 1504 ath9k_hw_set_clockrate(ah);
ca2c68cc 1505 ath9k_hw_apply_txpower(ah, chan);
8fe65368 1506 ath9k_hw_rfbus_done(ah);
f078f209 1507
f1dc5600
S		 1508 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1509 ath9k_hw_set_delta_slope(ah, chan);
1510
8fe65368 1511 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1512
5f0c04ea 1513 if (edma && (band_switch || mode_diff)) {
a126ff51 1514 ah->ah_flags |= AH_FASTCC;
5f0c04ea
RM		 1515 if (band_switch || ini_reloaded)
1516 ah->eep_ops->set_board_values(ah, chan);
1517
1518 ath9k_hw_init_bb(ah, chan);
1519
1520 if (band_switch || ini_reloaded)
1521 ath9k_hw_init_cal(ah, chan);
a126ff51 1522 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1523 }
1524
f1dc5600
S		 1525 return true;
1526}
1527
691680b8
FF		 1528static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1529{
1530 u32 gpio_mask = ah->gpio_mask;
1531 int i;
1532
1533 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1534 if (!(gpio_mask & 1))
1535 continue;
1536
1537 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1538 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1539 }
1540}
1541
01e18918
RM		 1542static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1543 int *hang_state, int *hang_pos)
1544{
1545 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1546 u32 chain_state, dcs_pos, i;
1547
1548 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1549 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1550 for (i = 0; i < 3; i++) {
1551 if (chain_state == dcu_chain_state[i]) {
1552 *hang_state = chain_state;
1553 *hang_pos = dcs_pos;
1554 return true;
1555 }
1556 }
1557 }
1558 return false;
1559}
1560
1561#define DCU_COMPLETE_STATE 1
1562#define DCU_COMPLETE_STATE_MASK 0x3
1563#define NUM_STATUS_READS 50
1564static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1565{
1566 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1567 u32 i, hang_pos, hang_state, num_state = 6;
1568
1569 comp_state = REG_READ(ah, AR_DMADBG_6);
1570
1571 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1572 ath_dbg(ath9k_hw_common(ah), RESET,
1573 "MAC Hang signature not found at DCU complete\n");
1574 return false;
1575 }
1576
1577 chain_state = REG_READ(ah, dcs_reg);
1578 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1579 goto hang_check_iter;
1580
1581 dcs_reg = AR_DMADBG_5;
1582 num_state = 4;
1583 chain_state = REG_READ(ah, dcs_reg);
1584 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1585 goto hang_check_iter;
1586
1587 ath_dbg(ath9k_hw_common(ah), RESET,
1588 "MAC Hang signature 1 not found\n");
1589 return false;
1590
1591hang_check_iter:
1592 ath_dbg(ath9k_hw_common(ah), RESET,
1593 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1594 chain_state, comp_state, hang_state, hang_pos);
1595
1596 for (i = 0; i < NUM_STATUS_READS; i++) {
1597 chain_state = REG_READ(ah, dcs_reg);
1598 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1599 comp_state = REG_READ(ah, AR_DMADBG_6);
1600
1601 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1602 DCU_COMPLETE_STATE) ||
1603 (chain_state != hang_state))
1604 return false;
1605 }
1606
1607 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1608
1609 return true;
1610}
1611
c9c99e5e 1612bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1613{
c9c99e5e
FF		 1614 int count = 50;
1615 u32 reg;
1616
01e18918
RM		 1617 if (AR_SREV_9300(ah))
1618 return !ath9k_hw_detect_mac_hang(ah);
1619
e17f83ea 1620 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1621 return true;
1622
1623 do {
1624 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1625
c9c99e5e
FF		 1626 if ((reg & 0x7E7FFFEF) == 0x00702400)
1627 continue;
1628
1629 switch (reg & 0x7E000B00) {
1630 case 0x1E000000:
1631 case 0x52000B00:
1632 case 0x18000B00:
1633 continue;
1634 default:
1635 return true;
1636 }
1637 } while (count-- > 0);
3b319aae 1638
c9c99e5e 1639 return false;
3b319aae 1640}
c9c99e5e 1641EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1642
caed6579
SM		 1643/*
1644 * Fast channel change:
1645 * (Change synthesizer based on channel freq without resetting chip)
1646 *
1647 * Don't do FCC when
1648 * - Flag is not set
1649 * - Chip is just coming out of full sleep
1650 * - Channel to be set is same as current channel
1651 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1652 */
1653static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1654{
1655 struct ath_common *common = ath9k_hw_common(ah);
1656 int ret;
1657
1658 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1659 goto fail;
1660
1661 if (ah->chip_fullsleep)
1662 goto fail;
1663
1664 if (!ah->curchan)
1665 goto fail;
1666
1667 if (chan->channel == ah->curchan->channel)
1668 goto fail;
1669
1670 if ((chan->channelFlags & CHANNEL_ALL) !=
1671 (ah->curchan->channelFlags & CHANNEL_ALL))
1672 goto fail;
1673
1674 if (!ath9k_hw_check_alive(ah))
1675 goto fail;
1676
1677 /*
1678 * For AR9462, make sure that calibration data for
1679 * re-using are present.
1680 */
1681 if (AR_SREV_9462(ah) && (!ah->caldata ||
1682 !ah->caldata->done_txiqcal_once ||
1683 !ah->caldata->done_txclcal_once ||
1684 !ah->caldata->rtt_hist.num_readings))
1685 goto fail;
1686
1687 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1688 ah->curchan->channel, chan->channel);
1689
1690 ret = ath9k_hw_channel_change(ah, chan);
1691 if (!ret)
1692 goto fail;
1693
1694 ath9k_hw_loadnf(ah, ah->curchan);
1695 ath9k_hw_start_nfcal(ah, true);
1696
1697 if ((ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && ar9003_mci_is_ready(ah))
1698 ar9003_mci_2g5g_switch(ah, true);
1699
1700 if (AR_SREV_9271(ah))
1701 ar9002_hw_load_ani_reg(ah, chan);
1702
1703 return 0;
1704fail:
1705 return -EINVAL;
1706}
1707
cbe61d8a 1708int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1709 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1710{
1510718d 1711 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1712 u32 saveLedState;
f078f209
LR		 1713 u32 saveDefAntenna;
1714 u32 macStaId1;
46fe782c 1715 u64 tsf = 0;
8fe65368 1716 int i, r;
caed6579 1717 bool start_mci_reset = false;
63d32967
MSS		 1718 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1719 bool save_fullsleep = ah->chip_fullsleep;
1720
1721 if (mci) {
528e5d36
SM		 1722 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1723 if (start_mci_reset)
1724 return 0;
63d32967
MSS		 1725 }
1726
9ecdef4b 1727 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1728 return -EIO;
f078f209 1729
caed6579
SM		 1730 if (ah->curchan && !ah->chip_fullsleep)
1731 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1732
20bd2a09
FF		 1733 ah->caldata = caldata;
1734 if (caldata &&
1735 (chan->channel != caldata->channel ||
1736 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1737 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1738 /* Operating channel changed, reset channel calibration data */
1739 memset(caldata, 0, sizeof(*caldata));
1740 ath9k_init_nfcal_hist_buffer(ah, chan);
1741 }
f23fba49 1742 ah->noise = ath9k_hw_getchan_noise(ah, chan);
20bd2a09 1743
caed6579
SM		 1744 if (fastcc) {
1745 r = ath9k_hw_do_fastcc(ah, chan);
1746 if (!r)
1747 return r;
f078f209
LR		 1748 }
1749
528e5d36
SM		 1750 if (mci)
1751 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1752
f078f209
LR		 1753 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1754 if (saveDefAntenna == 0)
1755 saveDefAntenna = 1;
1756
1757 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1758
46fe782c 1759 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1760 if (AR_SREV_9100(ah) ||
1761 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1762 tsf = ath9k_hw_gettsf64(ah);
1763
f078f209
LR		 1764 saveLedState = REG_READ(ah, AR_CFG_LED) &
1765 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1766 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1767
1768 ath9k_hw_mark_phy_inactive(ah);
1769
45ef6a0b
VT		 1770 ah->paprd_table_write_done = false;
1771
05020d23 1772 /* Only required on the first reset */
d7e7d229
LR		 1773 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1774 REG_WRITE(ah,
1775 AR9271_RESET_POWER_DOWN_CONTROL,
1776 AR9271_RADIO_RF_RST);
1777 udelay(50);
1778 }
1779
f078f209 1780 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1781 ath_err(common, "Chip reset failed\n");
ae8d2858 1782 return -EINVAL;
f078f209
LR		 1783 }
1784
05020d23 1785 /* Only required on the first reset */
d7e7d229
LR		 1786 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1787 ah->htc_reset_init = false;
1788 REG_WRITE(ah,
1789 AR9271_RESET_POWER_DOWN_CONTROL,
1790 AR9271_GATE_MAC_CTL);
1791 udelay(50);
1792 }
1793
46fe782c 1794 /* Restore TSF */
f860d526 1795 if (tsf)
46fe782c
S		 1796 ath9k_hw_settsf64(ah, tsf);
1797
7a37081e 1798 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1799 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1800
e9141f71
S		 1801 if (!AR_SREV_9300_20_OR_LATER(ah))
1802 ar9002_hw_enable_async_fifo(ah);
1803
25c56eec 1804 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1805 if (r)
1806 return r;
f078f209 1807
63d32967
MSS		 1808 if (mci)
1809 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1810
f860d526
FF		 1811 /*
1812 * Some AR91xx SoC devices frequently fail to accept TSF writes
1813 * right after the chip reset. When that happens, write a new
1814 * value after the initvals have been applied, with an offset
1815 * based on measured time difference
1816 */
1817 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1818 tsf += 1500;
1819 ath9k_hw_settsf64(ah, tsf);
1820 }
1821
0ced0e17
JM		 1822 /* Setup MFP options for CCMP */
1823 if (AR_SREV_9280_20_OR_LATER(ah)) {
1824 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1825 * frames when constructing CCMP AAD. */
1826 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1827 0xc7ff);
1828 ah->sw_mgmt_crypto = false;
1829 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1830 /* Disable hardware crypto for management frames */
1831 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1832 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1833 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1834 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1835 ah->sw_mgmt_crypto = true;
1836 } else
1837 ah->sw_mgmt_crypto = true;
1838
f078f209
LR		 1839 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1840 ath9k_hw_set_delta_slope(ah, chan);
1841
8fe65368 1842 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1843 ah->eep_ops->set_board_values(ah, chan);
a7765828 1844
7d0d0df0
S		 1845 ENABLE_REGWRITE_BUFFER(ah);
1846
1510718d
LR		 1847 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1848 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1849 | macStaId1
1850 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1851 | (ah->config.
60b67f51 1852 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1853 | ah->sta_id1_defaults);
13b81559 1854 ath_hw_setbssidmask(common);
f078f209 1855 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1856 ath9k_hw_write_associd(ah);
f078f209 1857 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1858 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1859
7d0d0df0 1860 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1861
00e0003e
SM		 1862 ath9k_hw_set_operating_mode(ah, ah->opmode);
1863
8fe65368 1864 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1865 if (r)
1866 return r;
f078f209 1867
dfdac8ac
FF		 1868 ath9k_hw_set_clockrate(ah);
1869
7d0d0df0
S		 1870 ENABLE_REGWRITE_BUFFER(ah);
1871
f078f209
LR		 1872 for (i = 0; i < AR_NUM_DCU; i++)
1873 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1874
7d0d0df0 1875 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1876
2660b81a 1877 ah->intr_txqs = 0;
f4c607dc 1878 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
f078f209
LR		 1879 ath9k_hw_resettxqueue(ah, i);
1880
2660b81a 1881 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1882 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1883 ath9k_hw_init_qos(ah);
1884
2660b81a 1885 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1886 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1887
0005baf4 1888 ath9k_hw_init_global_settings(ah);
f078f209 1889
fe2b6afb
FF		 1890 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1891 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1892 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1893 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1894 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1895 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1896 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1897 }
1898
ca7a4deb 1899 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1900
1901 ath9k_hw_set_dma(ah);
1902
1903 REG_WRITE(ah, AR_OBS, 8);
1904
0ce024cb 1905 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1906 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1907 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1908 }
1909
7f62a136
VT		 1910 if (ah->config.tx_intr_mitigation) {
1911 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1912 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1913 }
1914
f078f209
LR		 1915 ath9k_hw_init_bb(ah, chan);
1916
77a5a664 1917 if (caldata) {
5f0c04ea 1918 caldata->done_txiqcal_once = false;
77a5a664 1919 caldata->done_txclcal_once = false;
324c74ad 1920 caldata->rtt_hist.num_readings = 0;
77a5a664 1921 }
ae8d2858 1922 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1923 return -EIO;
f078f209 1924
93348928
RM		 1925 ath9k_hw_loadnf(ah, chan);
1926 ath9k_hw_start_nfcal(ah, true);
1927
528e5d36
SM		 1928 if (mci && ar9003_mci_end_reset(ah, chan, caldata))
1929 return -EIO;
63d32967 1930
7d0d0df0 1931 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1932
8fe65368 1933 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1934 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1935
7d0d0df0 1936 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1937
d7e7d229
LR		 1938 /*
1939 * For big endian systems turn on swapping for descriptors
1940 */
f078f209
LR		 1941 if (AR_SREV_9100(ah)) {
1942 u32 mask;
1943 mask = REG_READ(ah, AR_CFG);
1944 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
d2182b69
JP		 1945 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1946 mask);
f078f209
LR		 1947 } else {
1948 mask =
1949 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1950 REG_WRITE(ah, AR_CFG, mask);
d2182b69
JP		 1951 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1952 REG_READ(ah, AR_CFG));
f078f209
LR		 1953 }
1954 } else {
cbba8cd1
S		 1955 if (common->bus_ops->ath_bus_type == ATH_USB) {
1956 /* Configure AR9271 target WLAN */
1957 if (AR_SREV_9271(ah))
1958 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1959 else
1960 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1961 }
f078f209 1962#ifdef __BIG_ENDIAN
4033bdad 1963 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
2be7bfe0
VT		 1964 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1965 else
d7e7d229 1966 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1967#endif
1968 }
1969
dbccdd1d 1970 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 1971 ath9k_hw_btcoex_enable(ah);
1972
528e5d36
SM		 1973 if (mci)
1974 ar9003_mci_check_bt(ah);
63d32967 1975
51ac8cbb 1976 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 1977 ar9003_hw_bb_watchdog_config(ah);
d8903a53 1978
51ac8cbb
RM		 1979 ar9003_hw_disable_phy_restart(ah);
1980 }
1981
691680b8
FF		 1982 ath9k_hw_apply_gpio_override(ah);
1983
ae8d2858 1984 return 0;
f078f209 1985}
7322fd19 1986EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1987
f1dc5600
S		 1988/******************************/
1989/* Power Management (Chipset) */
1990/******************************/
1991
42d5bc3f
LR		 1992/*
1993 * Notify Power Mgt is disabled in self-generated frames.
1994 * If requested, force chip to sleep.
1995 */
cbe61d8a 1996static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1997{
f1dc5600
S		 1998 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1999 if (setChip) {
423e38e8 2000 if (AR_SREV_9462(ah)) {
2577c6e8
SB		 2001 REG_WRITE(ah, AR_TIMER_MODE,
2002 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
2003 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
2004 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
2005 REG_WRITE(ah, AR_SLP32_INC,
2006 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
2007 /* xxx Required for WLAN only case ? */
2008 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2009 udelay(100);
2010 }
2011
42d5bc3f
LR		 2012 /*
2013 * Clear the RTC force wake bit to allow the
2014 * mac to go to sleep.
2015 */
2577c6e8
SB		 2016 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2017
423e38e8 2018 if (AR_SREV_9462(ah))
2577c6e8
SB		 2019 udelay(100);
2020
42d5bc3f 2021 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 2022 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2023
42d5bc3f 2024 /* Shutdown chip. Active low */
c91ec465 2025 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2577c6e8
SB		 2026 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2027 udelay(2);
2028 }
f1dc5600 2029 }
9a658d2b
LR		 2030
2031 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2032 if (AR_SREV_9300_20_OR_LATER(ah))
2033 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2034}
2035
bbd79af5
LR		 2036/*
2037 * Notify Power Management is enabled in self-generating
2038 * frames. If request, set power mode of chip to
2039 * auto/normal. Duration in units of 128us (1/8 TU).
2040 */
cbe61d8a 2041static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2042{
2577c6e8
SB		 2043 u32 val;
2044
f1dc5600
S		 2045 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2046 if (setChip) {
2660b81a 2047 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2048
f1dc5600 2049 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 2050 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 2051 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2052 AR_RTC_FORCE_WAKE_ON_INT);
2053 } else {
2577c6e8
SB		 2054
2055 /* When chip goes into network sleep, it could be waken
2056 * up by MCI_INT interrupt caused by BT's HW messages
2057 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2058 * rate (~100us). This will cause chip to leave and
2059 * re-enter network sleep mode frequently, which in
2060 * consequence will have WLAN MCI HW to generate lots of
2061 * SYS_WAKING and SYS_SLEEPING messages which will make
2062 * BT CPU to busy to process.
2063 */
423e38e8 2064 if (AR_SREV_9462(ah)) {
2577c6e8
SB		 2065 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
2066 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
2067 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
2068 }
bbd79af5
LR		 2069 /*
2070 * Clear the RTC force wake bit to allow the
2071 * mac to go to sleep.
2072 */
f1dc5600
S		 2073 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2074 AR_RTC_FORCE_WAKE_EN);
2577c6e8 2075
423e38e8 2076 if (AR_SREV_9462(ah))
2577c6e8 2077 udelay(30);
f078f209 2078 }
f078f209 2079 }
9a658d2b
LR		 2080
2081 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2082 if (AR_SREV_9300_20_OR_LATER(ah))
2083 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2084}
2085
cbe61d8a 2086static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2087{
f1dc5600
S		 2088 u32 val;
2089 int i;
f078f209 2090
9a658d2b
LR		 2091 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2092 if (AR_SREV_9300_20_OR_LATER(ah)) {
2093 REG_WRITE(ah, AR_WA, ah->WARegVal);
2094 udelay(10);
2095 }
2096
f1dc5600
S		 2097 if (setChip) {
2098 if ((REG_READ(ah, AR_RTC_STATUS) &
2099 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
23677ce3 2100 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
f1dc5600
S		 2101 return false;
2102 }
e041228f
LR		 2103 if (!AR_SREV_9300_20_OR_LATER(ah))
2104 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 2105 }
2106 if (AR_SREV_9100(ah))
2107 REG_SET_BIT(ah, AR_RTC_RESET,
2108 AR_RTC_RESET_EN);
f078f209 2109
f1dc5600
S		 2110 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2111 AR_RTC_FORCE_WAKE_EN);
2112 udelay(50);
f078f209 2113
f1dc5600
S		 2114 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2115 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2116 if (val == AR_RTC_STATUS_ON)
2117 break;
2118 udelay(50);
2119 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2120 AR_RTC_FORCE_WAKE_EN);
f078f209 2121 }
f1dc5600 2122 if (i == 0) {
3800276a
JP		 2123 ath_err(ath9k_hw_common(ah),
2124 "Failed to wakeup in %uus\n",
2125 POWER_UP_TIME / 20);
f1dc5600 2126 return false;
f078f209 2127 }
f078f209
LR		 2128 }
2129
f1dc5600 2130 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2131
f1dc5600 2132 return true;
f078f209
LR		 2133}
2134
9ecdef4b 2135bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2136{
c46917bb 2137 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 2138 int status = true, setChip = true;
f1dc5600
S		 2139 static const char *modes[] = {
2140 "AWAKE",
2141 "FULL-SLEEP",
2142 "NETWORK SLEEP",
2143 "UNDEFINED"
2144 };
f1dc5600 2145
cbdec975
GJ		 2146 if (ah->power_mode == mode)
2147 return status;
2148
d2182b69 2149 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2150 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2151
2152 switch (mode) {
2153 case ATH9K_PM_AWAKE:
2154 status = ath9k_hw_set_power_awake(ah, setChip);
1010911e
MSS		 2155
2156 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2157 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2158
f1dc5600
S		 2159 break;
2160 case ATH9K_PM_FULL_SLEEP:
d1ca8b8e
SM		 2161 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2162 ar9003_mci_set_full_sleep(ah);
1010911e 2163
f1dc5600 2164 ath9k_set_power_sleep(ah, setChip);
2660b81a 2165 ah->chip_fullsleep = true;
f1dc5600
S		 2166 break;
2167 case ATH9K_PM_NETWORK_SLEEP:
1010911e
MSS		 2168
2169 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2170 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2171
f1dc5600
S		 2172 ath9k_set_power_network_sleep(ah, setChip);
2173 break;
f078f209 2174 default:
3800276a 2175 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2176 return false;
2177 }
2660b81a 2178 ah->power_mode = mode;
f1dc5600 2179
69f4aab1
LR		 2180 /*
2181 * XXX: If this warning never comes up after a while then
2182 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2183 * ath9k_hw_setpower() return type void.
2184 */
97dcec57
SM		 2185
2186 if (!(ah->ah_flags & AH_UNPLUGGED))
2187 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2188
f1dc5600 2189 return status;
f078f209 2190}
7322fd19 2191EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2192
f1dc5600
S		 2193/*******************/
2194/* Beacon Handling */
2195/*******************/
2196
cbe61d8a 2197void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2198{
f078f209
LR		 2199 int flags = 0;
2200
7d0d0df0
S		 2201 ENABLE_REGWRITE_BUFFER(ah);
2202
2660b81a 2203 switch (ah->opmode) {
d97809db 2204 case NL80211_IFTYPE_ADHOC:
9cb5412b 2205 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 2206 REG_SET_BIT(ah, AR_TXCFG,
2207 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
dd347f2f
FF		 2208 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2209 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
f078f209 2210 flags |= AR_NDP_TIMER_EN;
d97809db 2211 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2212 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2213 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2214 TU_TO_USEC(ah->config.dma_beacon_response_time));
2215 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2216 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2217 flags |=
2218 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2219 break;
d97809db 2220 default:
d2182b69
JP		 2221 ath_dbg(ath9k_hw_common(ah), BEACON,
2222 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2223 return;
2224 break;
f078f209
LR		 2225 }
2226
dd347f2f
FF		 2227 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2228 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2229 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2230 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
f078f209 2231
7d0d0df0 2232 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2233
f078f209
LR		 2234 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2235}
7322fd19 2236EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2237
cbe61d8a 2238void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2239 const struct ath9k_beacon_state *bs)
f078f209
LR		 2240{
2241 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2242 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2243 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2244
7d0d0df0
S		 2245 ENABLE_REGWRITE_BUFFER(ah);
2246
f078f209
LR		 2247 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2248
2249 REG_WRITE(ah, AR_BEACON_PERIOD,
f29f5c08 2250 TU_TO_USEC(bs->bs_intval));
f078f209 2251 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
f29f5c08 2252 TU_TO_USEC(bs->bs_intval));
f078f209 2253
7d0d0df0 2254 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2255
f078f209
LR		 2256 REG_RMW_FIELD(ah, AR_RSSI_THR,
2257 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2258
f29f5c08 2259 beaconintval = bs->bs_intval;
f078f209
LR		 2260
2261 if (bs->bs_sleepduration > beaconintval)
2262 beaconintval = bs->bs_sleepduration;
2263
2264 dtimperiod = bs->bs_dtimperiod;
2265 if (bs->bs_sleepduration > dtimperiod)
2266 dtimperiod = bs->bs_sleepduration;
2267
2268 if (beaconintval == dtimperiod)
2269 nextTbtt = bs->bs_nextdtim;
2270 else
2271 nextTbtt = bs->bs_nexttbtt;
2272
d2182b69
JP		 2273 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2274 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2275 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2276 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2277
7d0d0df0
S		 2278 ENABLE_REGWRITE_BUFFER(ah);
2279
f1dc5600
S		 2280 REG_WRITE(ah, AR_NEXT_DTIM,
2281 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2282 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 2283
f1dc5600
S		 2284 REG_WRITE(ah, AR_SLEEP1,
2285 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2286 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2287
f1dc5600
S		 2288 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2289 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2290 else
2291 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2292
f1dc5600
S		 2293 REG_WRITE(ah, AR_SLEEP2,
2294 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2295
f1dc5600
S		 2296 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2297 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2298
7d0d0df0 2299 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2300
f1dc5600
S		 2301 REG_SET_BIT(ah, AR_TIMER_MODE,
2302 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2303 AR_DTIM_TIMER_EN);
f078f209 2304
4af9cf4f
S		 2305 /* TSF Out of Range Threshold */
2306 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2307}
7322fd19 2308EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2309
f1dc5600
S		 2310/*******************/
2311/* HW Capabilities */
2312/*******************/
2313
6054069a
FF		 2314static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2315{
2316 eeprom_chainmask &= chip_chainmask;
2317 if (eeprom_chainmask)
2318 return eeprom_chainmask;
2319 else
2320 return chip_chainmask;
2321}
2322
9a66af33
ZK		 2323/**
2324 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2325 * @ah: the atheros hardware data structure
2326 *
2327 * We enable DFS support upstream on chipsets which have passed a series
2328 * of tests. The testing requirements are going to be documented. Desired
2329 * test requirements are documented at:
2330 *
2331 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2332 *
2333 * Once a new chipset gets properly tested an individual commit can be used
2334 * to document the testing for DFS for that chipset.
2335 */
2336static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2337{
2338
2339 switch (ah->hw_version.macVersion) {
2340 /* AR9580 will likely be our first target to get testing on */
2341 case AR_SREV_VERSION_9580:
2342 default:
2343 return false;
2344 }
2345}
2346
a9a29ce6 2347int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2348{
2660b81a 2349 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2350 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2351 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2352 unsigned int chip_chainmask;
608b88cb 2353
0ff2b5c0 2354 u16 eeval;
47c80de6 2355 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2356
f74df6fb 2357 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2358 regulatory->current_rd = eeval;
f078f209 2359
2660b81a 2360 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2361 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2362 if (regulatory->current_rd == 0x64 ||
2363 regulatory->current_rd == 0x65)
2364 regulatory->current_rd += 5;
2365 else if (regulatory->current_rd == 0x41)
2366 regulatory->current_rd = 0x43;
d2182b69
JP		 2367 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2368 regulatory->current_rd);
f1dc5600 2369 }
f078f209 2370
f74df6fb 2371 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2372 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2373 ath_err(common,
2374 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2375 return -EINVAL;
2376 }
2377
d4659912
FF		 2378 if (eeval & AR5416_OPFLAGS_11A)
2379 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2380
d4659912
FF		 2381 if (eeval & AR5416_OPFLAGS_11G)
2382 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2383
6054069a
FF		 2384 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2385 chip_chainmask = 1;
ba5736a5
MSS		 2386 else if (AR_SREV_9462(ah))
2387 chip_chainmask = 3;
6054069a
FF		 2388 else if (!AR_SREV_9280_20_OR_LATER(ah))
2389 chip_chainmask = 7;
2390 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2391 chip_chainmask = 3;
2392 else
2393 chip_chainmask = 7;
2394
f74df6fb 2395 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2396 /*
2397 * For AR9271 we will temporarilly uses the rx chainmax as read from
2398 * the EEPROM.
2399 */
8147f5de 2400 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2401 !(eeval & AR5416_OPFLAGS_11A) &&
2402 !(AR_SREV_9271(ah)))
2403 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2404 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2405 else if (AR_SREV_9100(ah))
2406 pCap->rx_chainmask = 0x7;
8147f5de 2407 else
d7e7d229 2408 /* Use rx_chainmask from EEPROM. */
8147f5de 2409 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2410
6054069a
FF		 2411 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2412 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2413 ah->txchainmask = pCap->tx_chainmask;
2414 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2415
7a37081e 2416 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2417
02d2ebb2
FF		 2418 /* enable key search for every frame in an aggregate */
2419 if (AR_SREV_9300_20_OR_LATER(ah))
2420 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2421
ce2220d1
BR		 2422 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2423
0db156e9 2424 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2425 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2426 else
2427 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2428
5b5fa355
S		 2429 if (AR_SREV_9271(ah))
2430 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2431 else if (AR_DEVID_7010(ah))
2432 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2433 else if (AR_SREV_9300_20_OR_LATER(ah))
2434 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2435 else if (AR_SREV_9287_11_OR_LATER(ah))
2436 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2437 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2438 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2439 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2440 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2441 else
2442 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2443
1b2538b2 2444 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2445 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2446 else
f1dc5600 2447 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2448
e97275cb 2449#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2450 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2451 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2452 ah->rfkill_gpio =
2453 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2454 ah->rfkill_polarity =
2455 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2456
2457 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2458 }
f1dc5600 2459#endif
d5d1154f 2460 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2461 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2462 else
2463 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2464
e7594072 2465 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2466 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2467 else
2468 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2469
ceb26445 2470 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2471 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
0e707a94 2472 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
784ad503
VT		 2473 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2474
ceb26445
VT		 2475 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2476 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2477 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2478 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2479 pCap->txs_len = sizeof(struct ar9003_txs);
6f481010
LR		 2480 if (!ah->config.paprd_disable &&
2481 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
4935250a 2482 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 2483 } else {
2484 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2485 if (AR_SREV_9280_20(ah))
6b42e8d0 2486 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2487 }
1adf02ff 2488
6c84ce08
VT		 2489 if (AR_SREV_9300_20_OR_LATER(ah))
2490 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2491
6ee63f55
SB		 2492 if (AR_SREV_9300_20_OR_LATER(ah))
2493 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2494
a42acef0 2495 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2496 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2497
754dc536
VT		 2498 if (AR_SREV_9285(ah))
2499 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2500 ant_div_ctl1 =
2501 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2502 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2503 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2504 }
ea066d5a
MSS		 2505 if (AR_SREV_9300_20_OR_LATER(ah)) {
2506 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2507 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2508 }
2509
2510
431da56a 2511 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
21d2c63a
MSS		 2512 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2513 /*
2514 * enable the diversity-combining algorithm only when
2515 * both enable_lna_div and enable_fast_div are set
2516 * Table for Diversity
2517 * ant_div_alt_lnaconf bit 0-1
2518 * ant_div_main_lnaconf bit 2-3
2519 * ant_div_alt_gaintb bit 4
2520 * ant_div_main_gaintb bit 5
2521 * enable_ant_div_lnadiv bit 6
2522 * enable_ant_fast_div bit 7
2523 */
2524 if ((ant_div_ctl1 >> 0x6) == 0x3)
2525 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2526 }
754dc536 2527
8060e169
VT		 2528 if (AR_SREV_9485_10(ah)) {
2529 pCap->pcie_lcr_extsync_en = true;
2530 pCap->pcie_lcr_offset = 0x80;
2531 }
2532
9a66af33
ZK		 2533 if (ath9k_hw_dfs_tested(ah))
2534 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2535
47c80de6
VT		 2536 tx_chainmask = pCap->tx_chainmask;
2537 rx_chainmask = pCap->rx_chainmask;
2538 while (tx_chainmask || rx_chainmask) {
2539 if (tx_chainmask & BIT(0))
2540 pCap->max_txchains++;
2541 if (rx_chainmask & BIT(0))
2542 pCap->max_rxchains++;
2543
2544 tx_chainmask >>= 1;
2545 rx_chainmask >>= 1;
2546 }
2547
8ad74c4d
RM		 2548 if (AR_SREV_9300_20_OR_LATER(ah)) {
2549 ah->enabled_cals |= TX_IQ_CAL;
6fea593d 2550 if (AR_SREV_9485_OR_LATER(ah))
8ad74c4d
RM		 2551 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2552 }
3789d59c
MSS		 2553
2554 if (AR_SREV_9462(ah)) {
2555
2556 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2557 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2558
2559 if (AR_SREV_9462_20(ah))
2560 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2561
2562 }
2563
324c74ad 2564
a9a29ce6 2565 return 0;
f078f209
LR		 2566}
2567
f1dc5600
S		 2568/****************************/
2569/* GPIO / RFKILL / Antennae */
2570/****************************/
f078f209 2571
cbe61d8a 2572static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2573 u32 gpio, u32 type)
2574{
2575 int addr;
2576 u32 gpio_shift, tmp;
f078f209 2577
f1dc5600
S		 2578 if (gpio > 11)
2579 addr = AR_GPIO_OUTPUT_MUX3;
2580 else if (gpio > 5)
2581 addr = AR_GPIO_OUTPUT_MUX2;
2582 else
2583 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2584
f1dc5600 2585 gpio_shift = (gpio % 6) * 5;
f078f209 2586
f1dc5600
S		 2587 if (AR_SREV_9280_20_OR_LATER(ah)
2588 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2589 REG_RMW(ah, addr, (type << gpio_shift),
2590 (0x1f << gpio_shift));
f078f209 2591 } else {
f1dc5600
S		 2592 tmp = REG_READ(ah, addr);
2593 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2594 tmp &= ~(0x1f << gpio_shift);
2595 tmp |= (type << gpio_shift);
2596 REG_WRITE(ah, addr, tmp);
f078f209 2597 }
f078f209
LR		 2598}
2599
cbe61d8a 2600void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2601{
f1dc5600 2602 u32 gpio_shift;
f078f209 2603
9680e8a3 2604 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2605
88c1f4f6
S		 2606 if (AR_DEVID_7010(ah)) {
2607 gpio_shift = gpio;
2608 REG_RMW(ah, AR7010_GPIO_OE,
2609 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2610 (AR7010_GPIO_OE_MASK << gpio_shift));
2611 return;
2612 }
f078f209 2613
88c1f4f6 2614 gpio_shift = gpio << 1;
f1dc5600
S		 2615 REG_RMW(ah,
2616 AR_GPIO_OE_OUT,
2617 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2618 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2619}
7322fd19 2620EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2621
cbe61d8a 2622u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2623{
cb33c412
SB		 2624#define MS_REG_READ(x, y) \
2625 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2626
2660b81a 2627 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2628 return 0xffffffff;
f078f209 2629
88c1f4f6
S		 2630 if (AR_DEVID_7010(ah)) {
2631 u32 val;
2632 val = REG_READ(ah, AR7010_GPIO_IN);
2633 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2634 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2635 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2636 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2637 else if (AR_SREV_9271(ah))
5b5fa355 2638 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2639 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2640 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2641 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2642 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2643 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2644 return MS_REG_READ(AR928X, gpio) != 0;
2645 else
2646 return MS_REG_READ(AR, gpio) != 0;
f078f209 2647}
7322fd19 2648EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2649
cbe61d8a 2650void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2651 u32 ah_signal_type)
f078f209 2652{
f1dc5600 2653 u32 gpio_shift;
f078f209 2654
88c1f4f6
S		 2655 if (AR_DEVID_7010(ah)) {
2656 gpio_shift = gpio;
2657 REG_RMW(ah, AR7010_GPIO_OE,
2658 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2659 (AR7010_GPIO_OE_MASK << gpio_shift));
2660 return;
2661 }
f078f209 2662
88c1f4f6 2663 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2664 gpio_shift = 2 * gpio;
f1dc5600
S		 2665 REG_RMW(ah,
2666 AR_GPIO_OE_OUT,
2667 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2668 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2669}
7322fd19 2670EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2671
cbe61d8a 2672void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2673{
88c1f4f6
S		 2674 if (AR_DEVID_7010(ah)) {
2675 val = val ? 0 : 1;
2676 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2677 AR_GPIO_BIT(gpio));
2678 return;
2679 }
2680
5b5fa355
S		 2681 if (AR_SREV_9271(ah))
2682 val = ~val;
2683
f1dc5600
S		 2684 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2685 AR_GPIO_BIT(gpio));
f078f209 2686}
7322fd19 2687EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2688
cbe61d8a 2689void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2690{
f1dc5600 2691 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2692}
7322fd19 2693EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2694
f1dc5600
S		 2695/*********************/
2696/* General Operation */
2697/*********************/
2698
cbe61d8a 2699u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2700{
f1dc5600
S		 2701 u32 bits = REG_READ(ah, AR_RX_FILTER);
2702 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2703
f1dc5600
S		 2704 if (phybits & AR_PHY_ERR_RADAR)
2705 bits |= ATH9K_RX_FILTER_PHYRADAR;
2706 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2707 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2708
f1dc5600 2709 return bits;
f078f209 2710}
7322fd19 2711EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2712
cbe61d8a 2713void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2714{
f1dc5600 2715 u32 phybits;
f078f209 2716
7d0d0df0
S		 2717 ENABLE_REGWRITE_BUFFER(ah);
2718
423e38e8 2719 if (AR_SREV_9462(ah))
2577c6e8
SB		 2720 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2721
7ea310be
S		 2722 REG_WRITE(ah, AR_RX_FILTER, bits);
2723
f1dc5600
S		 2724 phybits = 0;
2725 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2726 phybits |= AR_PHY_ERR_RADAR;
2727 if (bits & ATH9K_RX_FILTER_PHYERR)
2728 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2729 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2730
f1dc5600 2731 if (phybits)
ca7a4deb 2732 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2733 else
ca7a4deb 2734 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2735
2736 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2737}
7322fd19 2738EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2739
cbe61d8a 2740bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2741{
63a75b91
SB		 2742 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2743 return false;
2744
2745 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2746 ah->htc_reset_init = true;
63a75b91 2747 return true;
f1dc5600 2748}
7322fd19 2749EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2750
cbe61d8a 2751bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2752{
9ecdef4b 2753 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2754 return false;
f078f209 2755
63a75b91
SB		 2756 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2757 return false;
2758
2759 ath9k_hw_init_pll(ah, NULL);
2760 return true;
f078f209 2761}
7322fd19 2762EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2763
ca2c68cc
FF		 2764static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2765{
2766 enum eeprom_param gain_param;
2767
2768 if (IS_CHAN_2GHZ(chan))
2769 gain_param = EEP_ANTENNA_GAIN_2G;
2770 else
2771 gain_param = EEP_ANTENNA_GAIN_5G;
2772
2773 return ah->eep_ops->get_eeprom(ah, gain_param);
2774}
2775
2776void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
2777{
2778 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2779 struct ieee80211_channel *channel;
2780 int chan_pwr, new_pwr, max_gain;
2781 int ant_gain, ant_reduction = 0;
2782
2783 if (!chan)
2784 return;
2785
2786 channel = chan->chan;
2787 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2788 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2789 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2790
2791 ant_gain = get_antenna_gain(ah, chan);
2792 if (ant_gain > max_gain)
2793 ant_reduction = ant_gain - max_gain;
2794
2795 ah->eep_ops->set_txpower(ah, chan,
2796 ath9k_regd_get_ctl(reg, chan),
2797 ant_reduction, new_pwr, false);
2798}
2799
de40f316 2800void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2801{
ca2c68cc 2802 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2803 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2804 struct ieee80211_channel *channel = chan->chan;
9c204b46 2805
48ef5c42 2806 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2807 if (test)
ca2c68cc 2808 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2809
ca2c68cc 2810 ath9k_hw_apply_txpower(ah, chan);
6f255425 2811
ca2c68cc
FF		 2812 if (test)
2813 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2814}
7322fd19 2815EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2816
cbe61d8a 2817void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2818{
2660b81a 2819 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2820}
7322fd19 2821EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2822
cbe61d8a 2823void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2824{
f1dc5600
S		 2825 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2826 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2827}
7322fd19 2828EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2829
f2b2143e 2830void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2831{
1510718d
LR		 2832 struct ath_common *common = ath9k_hw_common(ah);
2833
2834 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2835 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2836 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2837}
7322fd19 2838EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2839
1c0fc65e
BP		 2840#define ATH9K_MAX_TSF_READ 10
2841
cbe61d8a 2842u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2843{
1c0fc65e
BP		 2844 u32 tsf_lower, tsf_upper1, tsf_upper2;
2845 int i;
2846
2847 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2848 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2849 tsf_lower = REG_READ(ah, AR_TSF_L32);
2850 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2851 if (tsf_upper2 == tsf_upper1)
2852 break;
2853 tsf_upper1 = tsf_upper2;
2854 }
f078f209 2855
1c0fc65e 2856 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2857
1c0fc65e 2858 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2859}
7322fd19 2860EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2861
cbe61d8a 2862void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2863{
27abe060 2864 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2865 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2866}
7322fd19 2867EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2868
cbe61d8a 2869void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2870{
f9b604f6
GJ		 2871 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2872 AH_TSF_WRITE_TIMEOUT))
d2182b69 2873 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2874 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2875
f1dc5600
S		 2876 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2877}
7322fd19 2878EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2879
54e4cec6 2880void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2881{
f1dc5600 2882 if (setting)
2660b81a 2883 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2884 else
2660b81a 2885 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2886}
7322fd19 2887EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2888
25c56eec 2889void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2890{
25c56eec 2891 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2892 u32 macmode;
2893
25c56eec 2894 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2895 macmode = AR_2040_JOINED_RX_CLEAR;
2896 else
2897 macmode = 0;
f078f209 2898
f1dc5600 2899 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2900}
ff155a45
VT		 2901
2902/* HW Generic timers configuration */
2903
2904static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2905{
2906 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2907 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2908 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2909 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2910 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2911 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2912 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2913 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2914 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2915 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2916 AR_NDP2_TIMER_MODE, 0x0002},
2917 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2918 AR_NDP2_TIMER_MODE, 0x0004},
2919 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2920 AR_NDP2_TIMER_MODE, 0x0008},
2921 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2922 AR_NDP2_TIMER_MODE, 0x0010},
2923 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2924 AR_NDP2_TIMER_MODE, 0x0020},
2925 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2926 AR_NDP2_TIMER_MODE, 0x0040},
2927 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2928 AR_NDP2_TIMER_MODE, 0x0080}
2929};
2930
2931/* HW generic timer primitives */
2932
2933/* compute and clear index of rightmost 1 */
2934static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2935{
2936 u32 b;
2937
2938 b = *mask;
2939 b &= (0-b);
2940 *mask &= ~b;
2941 b *= debruijn32;
2942 b >>= 27;
2943
2944 return timer_table->gen_timer_index[b];
2945}
2946
dd347f2f 2947u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2948{
2949 return REG_READ(ah, AR_TSF_L32);
2950}
dd347f2f 2951EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2952
2953struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2954 void (*trigger)(void *),
2955 void (*overflow)(void *),
2956 void *arg,
2957 u8 timer_index)
2958{
2959 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2960 struct ath_gen_timer *timer;
2961
2962 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2963
2964 if (timer == NULL) {
3800276a
JP		 2965 ath_err(ath9k_hw_common(ah),
2966 "Failed to allocate memory for hw timer[%d]\n",
2967 timer_index);
ff155a45
VT		 2968 return NULL;
2969 }
2970
2971 /* allocate a hardware generic timer slot */
2972 timer_table->timers[timer_index] = timer;
2973 timer->index = timer_index;
2974 timer->trigger = trigger;
2975 timer->overflow = overflow;
2976 timer->arg = arg;
2977
2978 return timer;
2979}
7322fd19 2980EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2981
cd9bf689
LR		 2982void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2983 struct ath_gen_timer *timer,
788f6875 2984 u32 trig_timeout,
cd9bf689 2985 u32 timer_period)
ff155a45
VT		 2986{
2987 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
788f6875 2988 u32 tsf, timer_next;
ff155a45
VT		 2989
2990 BUG_ON(!timer_period);
2991
2992 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2993
2994 tsf = ath9k_hw_gettsf32(ah);
2995
788f6875
VT		 2996 timer_next = tsf + trig_timeout;
2997
d2182b69 2998 ath_dbg(ath9k_hw_common(ah), HWTIMER,
226afe68
JP		 2999 "current tsf %x period %x timer_next %x\n",
3000 tsf, timer_period, timer_next);
ff155a45 3001
ff155a45
VT		 3002 /*
3003 * Program generic timer registers
3004 */
3005 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3006 timer_next);
3007 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3008 timer_period);
3009 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3010 gen_tmr_configuration[timer->index].mode_mask);
3011
423e38e8 3012 if (AR_SREV_9462(ah)) {
2577c6e8 3013 /*
423e38e8 3014 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3015 * to use. But we still follow the old rule, 0 - 7 use tsf and
3016 * 8 - 15 use tsf2.
3017 */
3018 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3019 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3020 (1 << timer->index));
3021 else
3022 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3023 (1 << timer->index));
3024 }
3025
ff155a45
VT		 3026 /* Enable both trigger and thresh interrupt masks */
3027 REG_SET_BIT(ah, AR_IMR_S5,
3028 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3029 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 3030}
7322fd19 3031EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3032
cd9bf689 3033void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3034{
3035 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3036
3037 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3038 (timer->index >= ATH_MAX_GEN_TIMER)) {
3039 return;
3040 }
3041
3042 /* Clear generic timer enable bits. */
3043 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3044 gen_tmr_configuration[timer->index].mode_mask);
3045
3046 /* Disable both trigger and thresh interrupt masks */
3047 REG_CLR_BIT(ah, AR_IMR_S5,
3048 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3049 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3050
3051 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3052}
7322fd19 3053EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3054
3055void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3056{
3057 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3058
3059 /* free the hardware generic timer slot */
3060 timer_table->timers[timer->index] = NULL;
3061 kfree(timer);
3062}
7322fd19 3063EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3064
3065/*
3066 * Generic Timer Interrupts handling
3067 */
3068void ath_gen_timer_isr(struct ath_hw *ah)
3069{
3070 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3071 struct ath_gen_timer *timer;
c46917bb 3072 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3073 u32 trigger_mask, thresh_mask, index;
3074
3075 /* get hardware generic timer interrupt status */
3076 trigger_mask = ah->intr_gen_timer_trigger;
3077 thresh_mask = ah->intr_gen_timer_thresh;
3078 trigger_mask &= timer_table->timer_mask.val;
3079 thresh_mask &= timer_table->timer_mask.val;
3080
3081 trigger_mask &= ~thresh_mask;
3082
3083 while (thresh_mask) {
3084 index = rightmost_index(timer_table, &thresh_mask);
3085 timer = timer_table->timers[index];
3086 BUG_ON(!timer);
d2182b69
JP		 3087 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3088 index);
ff155a45
VT		 3089 timer->overflow(timer->arg);
3090 }
3091
3092 while (trigger_mask) {
3093 index = rightmost_index(timer_table, &trigger_mask);
3094 timer = timer_table->timers[index];
3095 BUG_ON(!timer);
d2182b69 3096 ath_dbg(common, HWTIMER,
226afe68 3097 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3098 timer->trigger(timer->arg);
3099 }
3100}
7322fd19 3101EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3102
05020d23
S		 3103/********/
3104/* HTC */
3105/********/
3106
2da4f01a
LR		 3107static struct {
3108 u32 version;
3109 const char * name;
3110} ath_mac_bb_names[] = {
3111 /* Devices with external radios */
3112 { AR_SREV_VERSION_5416_PCI, "5416" },
3113 { AR_SREV_VERSION_5416_PCIE, "5418" },
3114 { AR_SREV_VERSION_9100, "9100" },
3115 { AR_SREV_VERSION_9160, "9160" },
3116 /* Single-chip solutions */
3117 { AR_SREV_VERSION_9280, "9280" },
3118 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3119 { AR_SREV_VERSION_9287, "9287" },
3120 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3121 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3122 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3123 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3124 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3125 { AR_SREV_VERSION_9462, "9462" },
2da4f01a
LR		 3126};
3127
3128/* For devices with external radios */
3129static struct {
3130 u16 version;
3131 const char * name;
3132} ath_rf_names[] = {
3133 { 0, "5133" },
3134 { AR_RAD5133_SREV_MAJOR, "5133" },
3135 { AR_RAD5122_SREV_MAJOR, "5122" },
3136 { AR_RAD2133_SREV_MAJOR, "2133" },
3137 { AR_RAD2122_SREV_MAJOR, "2122" }
3138};
3139
3140/*
3141 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3142 */
f934c4d9 3143static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3144{
3145 int i;
3146
3147 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3148 if (ath_mac_bb_names[i].version == mac_bb_version) {
3149 return ath_mac_bb_names[i].name;
3150 }
3151 }
3152
3153 return "????";
3154}
2da4f01a
LR		 3155
3156/*
3157 * Return the RF name. "????" is returned if the RF is unknown.
3158 * Used for devices with external radios.
3159 */
f934c4d9 3160static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3161{
3162 int i;
3163
3164 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3165 if (ath_rf_names[i].version == rf_version) {
3166 return ath_rf_names[i].name;
3167 }
3168 }
3169
3170 return "????";
3171}
f934c4d9
LR		 3172
3173void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3174{
3175 int used;
3176
3177 /* chipsets >= AR9280 are single-chip */
7a37081e 3178 if (AR_SREV_9280_20_OR_LATER(ah)) {
f934c4d9
LR		 3179 used = snprintf(hw_name, len,
3180 "Atheros AR%s Rev:%x",
3181 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3182 ah->hw_version.macRev);
3183 }
3184 else {
3185 used = snprintf(hw_name, len,
3186 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3187 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3188 ah->hw_version.macRev,
3189 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3190 AR_RADIO_SREV_MAJOR)),
3191 ah->hw_version.phyRev);
3192 }
3193
3194 hw_name[used] = '\0';
3195}
3196EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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