projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ath9k_hw: Use a helper function to get MCI ISR
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
f078f209
LR		 20#include <asm/unaligned.h>
21
af03abec 22#include "hw.h"
d70357d5 23#include "hw-ops.h"
cfe8cba9 24#include "rc.h"
b622a720 25#include "ar9003_mac.h"
f078f209 26
cbe61d8a 27static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 28
7322fd19
LR		 29MODULE_AUTHOR("Atheros Communications");
30MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
31MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
32MODULE_LICENSE("Dual BSD/GPL");
33
34static int __init ath9k_init(void)
35{
36 return 0;
37}
38module_init(ath9k_init);
39
40static void __exit ath9k_exit(void)
41{
42 return;
43}
44module_exit(ath9k_exit);
45
d70357d5
LR		 46/* Private hardware callbacks */
47
48static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
49{
50 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
51}
52
53static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54{
55 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
56}
57
64773964
LR		 58static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
59 struct ath9k_channel *chan)
60{
61 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
62}
63
991312d8
LR		 64static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
65{
66 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
67 return;
68
69 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
70}
71
e36b27af
LR		 72static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
73{
74 /* You will not have this callback if using the old ANI */
75 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
76 return;
77
78 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
79}
80
f1dc5600
S		 81/********************/
82/* Helper Functions */
83/********************/
f078f209 84
dfdac8ac 85static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 86{
b002a4a9 87 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
dfdac8ac
FF		 88 struct ath_common *common = ath9k_hw_common(ah);
89 unsigned int clockrate;
cbe61d8a 90
087b6ff6
FF		 91 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
92 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
93 clockrate = 117;
94 else if (!ah->curchan) /* should really check for CCK instead */
dfdac8ac
FF		 95 clockrate = ATH9K_CLOCK_RATE_CCK;
96 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
97 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
98 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
99 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 100 else
dfdac8ac
FF		 101 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
102
103 if (conf_is_ht40(conf))
104 clockrate *= 2;
105
906c7205
FF		 106 if (ah->curchan) {
107 if (IS_CHAN_HALF_RATE(ah->curchan))
108 clockrate /= 2;
109 if (IS_CHAN_QUARTER_RATE(ah->curchan))
110 clockrate /= 4;
111 }
112
dfdac8ac 113 common->clockrate = clockrate;
f1dc5600
S		 114}
115
cbe61d8a 116static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 117{
dfdac8ac 118 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 119
dfdac8ac 120 return usecs * common->clockrate;
f1dc5600 121}
f078f209 122
0caa7b14 123bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 124{
125 int i;
126
0caa7b14
S		 127 BUG_ON(timeout < AH_TIME_QUANTUM);
128
129 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 130 if ((REG_READ(ah, reg) & mask) == val)
131 return true;
132
133 udelay(AH_TIME_QUANTUM);
134 }
04bd4638 135
d2182b69 136 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 137 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
138 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 139
f1dc5600 140 return false;
f078f209 141}
7322fd19 142EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 143
a9b6b256
FF		 144void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
145 int column, unsigned int *writecnt)
146{
147 int r;
148
149 ENABLE_REGWRITE_BUFFER(ah);
150 for (r = 0; r < array->ia_rows; r++) {
151 REG_WRITE(ah, INI_RA(array, r, 0),
152 INI_RA(array, r, column));
153 DO_DELAY(*writecnt);
154 }
155 REGWRITE_BUFFER_FLUSH(ah);
156}
157
f078f209
LR		 158u32 ath9k_hw_reverse_bits(u32 val, u32 n)
159{
160 u32 retval;
161 int i;
162
163 for (i = 0, retval = 0; i < n; i++) {
164 retval = (retval << 1) | (val & 1);
165 val >>= 1;
166 }
167 return retval;
168}
169
cbe61d8a 170u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 171 u8 phy, int kbps,
f1dc5600
S		 172 u32 frameLen, u16 rateix,
173 bool shortPreamble)
f078f209 174{
f1dc5600 175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 176
f1dc5600
S		 177 if (kbps == 0)
178 return 0;
f078f209 179
545750d3 180 switch (phy) {
46d14a58 181 case WLAN_RC_PHY_CCK:
f1dc5600 182 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 183 if (shortPreamble)
f1dc5600
S		 184 phyTime >>= 1;
185 numBits = frameLen << 3;
186 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
187 break;
46d14a58 188 case WLAN_RC_PHY_OFDM:
2660b81a 189 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 190 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
191 numBits = OFDM_PLCP_BITS + (frameLen << 3);
192 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
193 txTime = OFDM_SIFS_TIME_QUARTER
194 + OFDM_PREAMBLE_TIME_QUARTER
195 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 196 } else if (ah->curchan &&
197 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 198 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
199 numBits = OFDM_PLCP_BITS + (frameLen << 3);
200 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
201 txTime = OFDM_SIFS_TIME_HALF +
202 OFDM_PREAMBLE_TIME_HALF
203 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
204 } else {
205 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
206 numBits = OFDM_PLCP_BITS + (frameLen << 3);
207 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
208 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
209 + (numSymbols * OFDM_SYMBOL_TIME);
210 }
211 break;
212 default:
3800276a
JP		 213 ath_err(ath9k_hw_common(ah),
214 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 215 txTime = 0;
216 break;
217 }
f078f209 218
f1dc5600
S		 219 return txTime;
220}
7322fd19 221EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 222
cbe61d8a 223void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 224 struct ath9k_channel *chan,
225 struct chan_centers *centers)
f078f209 226{
f1dc5600 227 int8_t extoff;
f078f209 228
f1dc5600
S		 229 if (!IS_CHAN_HT40(chan)) {
230 centers->ctl_center = centers->ext_center =
231 centers->synth_center = chan->channel;
232 return;
f078f209 233 }
f078f209 234
f1dc5600
S		 235 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
236 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
237 centers->synth_center =
238 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
239 extoff = 1;
240 } else {
241 centers->synth_center =
242 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
243 extoff = -1;
244 }
f078f209 245
f1dc5600
S		 246 centers->ctl_center =
247 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 248 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 249 centers->ext_center =
6420014c 250 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 251}
252
f1dc5600
S		 253/******************/
254/* Chip Revisions */
255/******************/
256
cbe61d8a 257static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 258{
f1dc5600 259 u32 val;
f078f209 260
ecb1d385
VT		 261 switch (ah->hw_version.devid) {
262 case AR5416_AR9100_DEVID:
263 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
264 break;
3762561a
GJ		 265 case AR9300_DEVID_AR9330:
266 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
267 if (ah->get_mac_revision) {
268 ah->hw_version.macRev = ah->get_mac_revision();
269 } else {
270 val = REG_READ(ah, AR_SREV);
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272 }
273 return;
ecb1d385
VT		 274 case AR9300_DEVID_AR9340:
275 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
276 val = REG_READ(ah, AR_SREV);
277 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
278 return;
279 }
280
f1dc5600 281 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 282
f1dc5600
S		 283 if (val == 0xFF) {
284 val = REG_READ(ah, AR_SREV);
d535a42a
S		 285 ah->hw_version.macVersion =
286 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
287 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 288
423e38e8 289 if (AR_SREV_9462(ah))
76ed94be
MSS		 290 ah->is_pciexpress = true;
291 else
292 ah->is_pciexpress = (val &
293 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 294 } else {
295 if (!AR_SREV_9100(ah))
d535a42a 296 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 297
d535a42a 298 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 299
d535a42a 300 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 301 ah->is_pciexpress = true;
f1dc5600 302 }
f078f209
LR		 303}
304
f1dc5600
S		 305/************************************/
306/* HW Attach, Detach, Init Routines */
307/************************************/
308
cbe61d8a 309static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 310{
040b74f7 311 if (!AR_SREV_5416(ah))
f1dc5600 312 return;
f078f209 313
f1dc5600
S		 314 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 323
f1dc5600 324 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 325}
326
d4930086
SG		 327static void ath9k_hw_aspm_init(struct ath_hw *ah)
328{
329 struct ath_common *common = ath9k_hw_common(ah);
330
331 if (common->bus_ops->aspm_init)
332 common->bus_ops->aspm_init(common);
333}
334
1f3f0618 335/* This should work for all families including legacy */
cbe61d8a 336static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 337{
c46917bb 338 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 339 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 340 u32 regHold[2];
07b2fa5a
JP		 341 static const u32 patternData[4] = {
342 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
343 };
1f3f0618 344 int i, j, loop_max;
f078f209 345
1f3f0618
SB		 346 if (!AR_SREV_9300_20_OR_LATER(ah)) {
347 loop_max = 2;
348 regAddr[1] = AR_PHY_BASE + (8 << 2);
349 } else
350 loop_max = 1;
351
352 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 353 u32 addr = regAddr[i];
354 u32 wrData, rdData;
f078f209 355
f1dc5600
S		 356 regHold[i] = REG_READ(ah, addr);
357 for (j = 0; j < 0x100; j++) {
358 wrData = (j << 16) | j;
359 REG_WRITE(ah, addr, wrData);
360 rdData = REG_READ(ah, addr);
361 if (rdData != wrData) {
3800276a
JP		 362 ath_err(common,
363 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
364 addr, wrData, rdData);
f1dc5600
S		 365 return false;
366 }
367 }
368 for (j = 0; j < 4; j++) {
369 wrData = patternData[j];
370 REG_WRITE(ah, addr, wrData);
371 rdData = REG_READ(ah, addr);
372 if (wrData != rdData) {
3800276a
JP		 373 ath_err(common,
374 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
375 addr, wrData, rdData);
f1dc5600
S		 376 return false;
377 }
f078f209 378 }
f1dc5600 379 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 380 }
f1dc5600 381 udelay(100);
cbe61d8a 382
f078f209
LR		 383 return true;
384}
385
b8b0f377 386static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 387{
388 int i;
f078f209 389
2660b81a
S		 390 ah->config.dma_beacon_response_time = 2;
391 ah->config.sw_beacon_response_time = 10;
392 ah->config.additional_swba_backoff = 0;
393 ah->config.ack_6mb = 0x0;
394 ah->config.cwm_ignore_extcca = 0;
2660b81a 395 ah->config.pcie_clock_req = 0;
2660b81a
S		 396 ah->config.pcie_waen = 0;
397 ah->config.analog_shiftreg = 1;
03c72518 398 ah->config.enable_ani = true;
f078f209 399
f1dc5600 400 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 401 ah->config.spurchans[i][0] = AR_NO_SPUR;
402 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 403 }
404
6f481010
LR		 405 /* PAPRD needs some more work to be enabled */
406 ah->config.paprd_disable = 1;
407
0ce024cb 408 ah->config.rx_intr_mitigation = true;
6a0ec30a 409 ah->config.pcieSerDesWrite = true;
6158425b
LR		 410
411 /*
412 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
413 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
414 * This means we use it for all AR5416 devices, and the few
415 * minor PCI AR9280 devices out there.
416 *
417 * Serialization is required because these devices do not handle
418 * well the case of two concurrent reads/writes due to the latency
419 * involved. During one read/write another read/write can be issued
420 * on another CPU while the previous read/write may still be working
421 * on our hardware, if we hit this case the hardware poops in a loop.
422 * We prevent this by serializing reads and writes.
423 *
424 * This issue is not present on PCI-Express devices or pre-AR5416
425 * devices (legacy, 802.11abg).
426 */
427 if (num_possible_cpus() > 1)
2d6a5e95 428 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 429}
430
50aca25b 431static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 432{
608b88cb
LR		 433 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
434
435 regulatory->country_code = CTRY_DEFAULT;
436 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 437
d535a42a 438 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 439 ah->hw_version.subvendorid = 0;
f078f209 440
2660b81a 441 ah->atim_window = 0;
16f2411f
FF		 442 ah->sta_id1_defaults =
443 AR_STA_ID1_CRPT_MIC_ENABLE |
444 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 445 if (AR_SREV_9100(ah))
446 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
2660b81a 447 ah->enable_32kHz_clock = DONT_USE_32KHZ;
e3f2acc7 448 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 449 ah->globaltxtimeout = (u32) -1;
cbdec975 450 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 451}
452
cbe61d8a 453static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 454{
1510718d 455 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 456 u32 sum;
457 int i;
458 u16 eeval;
07b2fa5a 459 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 460
461 sum = 0;
462 for (i = 0; i < 3; i++) {
49101676 463 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 464 sum += eeval;
1510718d
LR		 465 common->macaddr[2 * i] = eeval >> 8;
466 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 467 }
d8baa939 468 if (sum == 0 || sum == 0xffff * 3)
f078f209 469 return -EADDRNOTAVAIL;
f078f209
LR		 470
471 return 0;
472}
473
f637cfd6 474static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 475{
6cae913d 476 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 477 int ecode;
f078f209 478
6cae913d 479 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 480 if (!ath9k_hw_chip_test(ah))
481 return -ENODEV;
482 }
f078f209 483
ebd5a14a
LR		 484 if (!AR_SREV_9300_20_OR_LATER(ah)) {
485 ecode = ar9002_hw_rf_claim(ah);
486 if (ecode != 0)
487 return ecode;
488 }
f078f209 489
f637cfd6 490 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 491 if (ecode != 0)
492 return ecode;
7d01b221 493
d2182b69 494 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 495 ah->eep_ops->get_eeprom_ver(ah),
496 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 497
8fe65368
LR		 498 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
499 if (ecode) {
3800276a
JP		 500 ath_err(ath9k_hw_common(ah),
501 "Failed allocating banks for external radio\n");
48a7c3df 502 ath9k_hw_rf_free_ext_banks(ah);
8fe65368 503 return ecode;
574d6b12 504 }
f078f209 505
4279425c 506 if (ah->config.enable_ani) {
f1dc5600 507 ath9k_hw_ani_setup(ah);
f637cfd6 508 ath9k_hw_ani_init(ah);
f078f209
LR		 509 }
510
f078f209
LR		 511 return 0;
512}
513
8525f280 514static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 515{
8525f280
LR		 516 if (AR_SREV_9300_20_OR_LATER(ah))
517 ar9003_hw_attach_ops(ah);
518 else
519 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 520}
521
d70357d5
LR		 522/* Called for all hardware families */
523static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 524{
c46917bb 525 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 526 int r = 0;
aa4058ae 527
ac45c12d
SB		 528 ath9k_hw_read_revisions(ah);
529
0a8d7cb0
SB		 530 /*
531 * Read back AR_WA into a permanent copy and set bits 14 and 17.
532 * We need to do this to avoid RMW of this register. We cannot
533 * read the reg when chip is asleep.
534 */
535 ah->WARegVal = REG_READ(ah, AR_WA);
536 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
537 AR_WA_ASPM_TIMER_BASED_DISABLE);
538
aa4058ae 539 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 540 ath_err(common, "Couldn't reset chip\n");
95fafca2 541 return -EIO;
aa4058ae
LR		 542 }
543
423e38e8 544 if (AR_SREV_9462(ah))
eec353c5
RM		 545 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
546
bab1f62e
LR		 547 ath9k_hw_init_defaults(ah);
548 ath9k_hw_init_config(ah);
549
8525f280 550 ath9k_hw_attach_ops(ah);
d70357d5 551
9ecdef4b 552 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 553 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 554 return -EIO;
aa4058ae
LR		 555 }
556
557 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
558 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
4c85ab11
JL		 559 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
560 !ah->is_pciexpress)) {
aa4058ae
LR		 561 ah->config.serialize_regmode =
562 SER_REG_MODE_ON;
563 } else {
564 ah->config.serialize_regmode =
565 SER_REG_MODE_OFF;
566 }
567 }
568
d2182b69 569 ath_dbg(common, RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 570 ah->config.serialize_regmode);
571
f4709fdf
LR		 572 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
573 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
574 else
575 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
576
6da5a720
FF		 577 switch (ah->hw_version.macVersion) {
578 case AR_SREV_VERSION_5416_PCI:
579 case AR_SREV_VERSION_5416_PCIE:
580 case AR_SREV_VERSION_9160:
581 case AR_SREV_VERSION_9100:
582 case AR_SREV_VERSION_9280:
583 case AR_SREV_VERSION_9285:
584 case AR_SREV_VERSION_9287:
585 case AR_SREV_VERSION_9271:
586 case AR_SREV_VERSION_9300:
2c8e5937 587 case AR_SREV_VERSION_9330:
6da5a720 588 case AR_SREV_VERSION_9485:
bca04689 589 case AR_SREV_VERSION_9340:
423e38e8 590 case AR_SREV_VERSION_9462:
6da5a720
FF		 591 break;
592 default:
3800276a
JP		 593 ath_err(common,
594 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
595 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 596 return -EOPNOTSUPP;
aa4058ae
LR		 597 }
598
2c8e5937
GJ		 599 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
600 AR_SREV_9330(ah))
d7e7d229
LR		 601 ah->is_pciexpress = false;
602
aa4058ae 603 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 604 ath9k_hw_init_cal_settings(ah);
605
606 ah->ani_function = ATH9K_ANI_ALL;
7a37081e 607 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 608 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 609 if (!AR_SREV_9300_20_OR_LATER(ah))
610 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae 611
4f17c48e
NM		 612 /* disable ANI for 9340 */
613 if (AR_SREV_9340(ah))
4279425c
NM		 614 ah->config.enable_ani = false;
615
aa4058ae
LR		 616 ath9k_hw_init_mode_regs(ah);
617
69ce674b 618 if (!ah->is_pciexpress)
aa4058ae
LR		 619 ath9k_hw_disablepcie(ah);
620
d8f492b7
LR		 621 if (!AR_SREV_9300_20_OR_LATER(ah))
622 ar9002_hw_cck_chan14_spread(ah);
193cd458 623
f637cfd6 624 r = ath9k_hw_post_init(ah);
aa4058ae 625 if (r)
95fafca2 626 return r;
aa4058ae
LR		 627
628 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 629 r = ath9k_hw_fill_cap_info(ah);
630 if (r)
631 return r;
632
69ce674b
SG		 633 if (ah->is_pciexpress)
634 ath9k_hw_aspm_init(ah);
635
4f3acf81
LR		 636 r = ath9k_hw_init_macaddr(ah);
637 if (r) {
3800276a 638 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 639 return r;
f078f209
LR		 640 }
641
d7e7d229 642 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 643 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 644 else
2660b81a 645 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 646
88e641df
GJ		 647 if (AR_SREV_9330(ah))
648 ah->bb_watchdog_timeout_ms = 85;
649 else
650 ah->bb_watchdog_timeout_ms = 25;
f078f209 651
211f5859
LR		 652 common->state = ATH_HW_INITIALIZED;
653
4f3acf81 654 return 0;
f078f209
LR		 655}
656
d70357d5 657int ath9k_hw_init(struct ath_hw *ah)
f078f209 658{
d70357d5
LR		 659 int ret;
660 struct ath_common *common = ath9k_hw_common(ah);
f078f209 661
d70357d5
LR		 662 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
663 switch (ah->hw_version.devid) {
664 case AR5416_DEVID_PCI:
665 case AR5416_DEVID_PCIE:
666 case AR5416_AR9100_DEVID:
667 case AR9160_DEVID_PCI:
668 case AR9280_DEVID_PCI:
669 case AR9280_DEVID_PCIE:
670 case AR9285_DEVID_PCIE:
db3cc53a
SB		 671 case AR9287_DEVID_PCI:
672 case AR9287_DEVID_PCIE:
d70357d5 673 case AR2427_DEVID_PCIE:
db3cc53a 674 case AR9300_DEVID_PCIE:
3050c914 675 case AR9300_DEVID_AR9485_PCIE:
999a7a88 676 case AR9300_DEVID_AR9330:
bca04689 677 case AR9300_DEVID_AR9340:
5a63ef0f 678 case AR9300_DEVID_AR9580:
423e38e8 679 case AR9300_DEVID_AR9462:
d70357d5
LR		 680 break;
681 default:
682 if (common->bus_ops->ath_bus_type == ATH_USB)
683 break;
3800276a
JP		 684 ath_err(common, "Hardware device ID 0x%04x not supported\n",
685 ah->hw_version.devid);
d70357d5
LR		 686 return -EOPNOTSUPP;
687 }
f078f209 688
d70357d5
LR		 689 ret = __ath9k_hw_init(ah);
690 if (ret) {
3800276a
JP		 691 ath_err(common,
692 "Unable to initialize hardware; initialization status: %d\n",
693 ret);
d70357d5
LR		 694 return ret;
695 }
f078f209 696
d70357d5 697 return 0;
f078f209 698}
d70357d5 699EXPORT_SYMBOL(ath9k_hw_init);
f078f209 700
cbe61d8a 701static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 702{
7d0d0df0
S		 703 ENABLE_REGWRITE_BUFFER(ah);
704
f1dc5600
S		 705 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
706 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 707
f1dc5600
S		 708 REG_WRITE(ah, AR_QOS_NO_ACK,
709 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
710 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
711 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
712
713 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
714 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
715 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
716 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
717 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 718
719 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 720}
721
b84628eb 722u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 723{
ca7a4deb
FF		 724 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
725 udelay(100);
726 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 727
ca7a4deb
FF		 728 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
729 udelay(100);
b1415819 730
ca7a4deb 731 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 732}
733EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
734
cbe61d8a 735static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 736 struct ath9k_channel *chan)
f078f209 737{
d09b17f7
VT		 738 u32 pll;
739
22983c30 740 if (AR_SREV_9485(ah)) {
22983c30 741
3dfd7f60
VT		 742 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
743 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
744 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
745 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
746 AR_CH0_DPLL2_KD, 0x40);
747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
748 AR_CH0_DPLL2_KI, 0x4);
22983c30 749
3dfd7f60
VT		 750 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
751 AR_CH0_BB_DPLL1_REFDIV, 0x5);
752 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
753 AR_CH0_BB_DPLL1_NINI, 0x58);
754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
755 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 756
757 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 758 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
759 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
760 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 762 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 763
3dfd7f60 764 /* program BB PLL phase_shift to 0x6 */
22983c30 765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 766 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
767
768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
769 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 770 udelay(1000);
a5415d62
GJ		 771 } else if (AR_SREV_9330(ah)) {
772 u32 ddr_dpll2, pll_control2, kd;
773
774 if (ah->is_clk_25mhz) {
775 ddr_dpll2 = 0x18e82f01;
776 pll_control2 = 0xe04a3d;
777 kd = 0x1d;
778 } else {
779 ddr_dpll2 = 0x19e82f01;
780 pll_control2 = 0x886666;
781 kd = 0x3d;
782 }
783
784 /* program DDR PLL ki and kd value */
785 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
786
787 /* program DDR PLL phase_shift */
788 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
789 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
790
791 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
792 udelay(1000);
793
794 /* program refdiv, nint, frac to RTC register */
795 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
796
797 /* program BB PLL kd and ki value */
798 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
800
801 /* program BB PLL phase_shift */
802 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
803 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
0b488ac6
VT		 804 } else if (AR_SREV_9340(ah)) {
805 u32 regval, pll2_divint, pll2_divfrac, refdiv;
806
807 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
808 udelay(1000);
809
810 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
811 udelay(100);
812
813 if (ah->is_clk_25mhz) {
814 pll2_divint = 0x54;
815 pll2_divfrac = 0x1eb85;
816 refdiv = 3;
817 } else {
818 pll2_divint = 88;
819 pll2_divfrac = 0;
820 refdiv = 5;
821 }
822
823 regval = REG_READ(ah, AR_PHY_PLL_MODE);
824 regval |= (0x1 << 16);
825 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
826 udelay(100);
827
828 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
829 (pll2_divint << 18) | pll2_divfrac);
830 udelay(100);
831
832 regval = REG_READ(ah, AR_PHY_PLL_MODE);
833 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
834 (0x4 << 26) | (0x18 << 19);
835 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
836 REG_WRITE(ah, AR_PHY_PLL_MODE,
837 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
838 udelay(1000);
22983c30 839 }
d09b17f7
VT		 840
841 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 842
d03a66c1 843 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 844
a5415d62 845 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
3dfd7f60
VT		 846 udelay(1000);
847
c75724d1
LR		 848 /* Switch the core clock for ar9271 to 117Mhz */
849 if (AR_SREV_9271(ah)) {
25e2ab17
S		 850 udelay(500);
851 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 852 }
853
f1dc5600
S		 854 udelay(RTC_PLL_SETTLE_DELAY);
855
856 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6
VT		 857
858 if (AR_SREV_9340(ah)) {
859 if (ah->is_clk_25mhz) {
860 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
861 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
862 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
863 } else {
864 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
865 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
866 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
867 }
868 udelay(100);
869 }
f078f209
LR		 870}
871
cbe61d8a 872static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 873 enum nl80211_iftype opmode)
f078f209 874{
79d1d2b8 875 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 876 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 877 AR_IMR_TXURN |
878 AR_IMR_RXERR |
879 AR_IMR_RXORN |
880 AR_IMR_BCNMISC;
f078f209 881
79d1d2b8
VT		 882 if (AR_SREV_9340(ah))
883 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
884
66860240
VT		 885 if (AR_SREV_9300_20_OR_LATER(ah)) {
886 imr_reg |= AR_IMR_RXOK_HP;
887 if (ah->config.rx_intr_mitigation)
888 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
889 else
890 imr_reg |= AR_IMR_RXOK_LP;
f078f209 891
66860240
VT		 892 } else {
893 if (ah->config.rx_intr_mitigation)
894 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
895 else
896 imr_reg |= AR_IMR_RXOK;
897 }
f078f209 898
66860240
VT		 899 if (ah->config.tx_intr_mitigation)
900 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
901 else
902 imr_reg |= AR_IMR_TXOK;
f078f209 903
d97809db 904 if (opmode == NL80211_IFTYPE_AP)
152d530d 905 imr_reg |= AR_IMR_MIB;
f078f209 906
7d0d0df0
S		 907 ENABLE_REGWRITE_BUFFER(ah);
908
152d530d 909 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 910 ah->imrs2_reg |= AR_IMR_S2_GTT;
911 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 912
f1dc5600
S		 913 if (!AR_SREV_9100(ah)) {
914 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 915 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 916 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
917 }
66860240 918
7d0d0df0 919 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 920
66860240
VT		 921 if (AR_SREV_9300_20_OR_LATER(ah)) {
922 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
923 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
924 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
925 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
926 }
f078f209
LR		 927}
928
b6ba41bb
FF		 929static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
930{
931 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
932 val = min(val, (u32) 0xFFFF);
933 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
934}
935
0005baf4 936static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 937{
0005baf4
FF		 938 u32 val = ath9k_hw_mac_to_clks(ah, us);
939 val = min(val, (u32) 0xFFFF);
940 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 941}
942
0005baf4 943static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 944{
0005baf4
FF		 945 u32 val = ath9k_hw_mac_to_clks(ah, us);
946 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
947 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
948}
949
950static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
951{
952 u32 val = ath9k_hw_mac_to_clks(ah, us);
953 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
954 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 955}
f1dc5600 956
cbe61d8a 957static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 958{
f078f209 959 if (tu > 0xFFFF) {
d2182b69
JP		 960 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
961 tu);
2660b81a 962 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 963 return false;
964 } else {
965 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 966 ah->globaltxtimeout = tu;
f078f209
LR		 967 return true;
968 }
969}
970
0005baf4 971void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 972{
b6ba41bb
FF		 973 struct ath_common *common = ath9k_hw_common(ah);
974 struct ieee80211_conf *conf = &common->hw->conf;
975 const struct ath9k_channel *chan = ah->curchan;
adb5066a 976 int acktimeout, ctstimeout;
e239d859 977 int slottime;
0005baf4 978 int sifstime;
b6ba41bb
FF		 979 int rx_lat = 0, tx_lat = 0, eifs = 0;
980 u32 reg;
0005baf4 981
d2182b69 982 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 983 ah->misc_mode);
f078f209 984
b6ba41bb
FF		 985 if (!chan)
986 return;
987
2660b81a 988 if (ah->misc_mode != 0)
ca7a4deb 989 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 990
81a91d57
RM		 991 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
992 rx_lat = 41;
993 else
994 rx_lat = 37;
b6ba41bb
FF		 995 tx_lat = 54;
996
997 if (IS_CHAN_HALF_RATE(chan)) {
998 eifs = 175;
999 rx_lat *= 2;
1000 tx_lat *= 2;
1001 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1002 tx_lat += 11;
1003
1004 slottime = 13;
1005 sifstime = 32;
1006 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1007 eifs = 340;
81a91d57 1008 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1009 tx_lat *= 4;
1010 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1011 tx_lat += 22;
1012
1013 slottime = 21;
1014 sifstime = 64;
1015 } else {
a7be039d
RM		 1016 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1017 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1018 reg = AR_USEC_ASYNC_FIFO;
1019 } else {
1020 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1021 common->clockrate;
1022 reg = REG_READ(ah, AR_USEC);
1023 }
b6ba41bb
FF		 1024 rx_lat = MS(reg, AR_USEC_RX_LAT);
1025 tx_lat = MS(reg, AR_USEC_TX_LAT);
1026
1027 slottime = ah->slottime;
1028 if (IS_CHAN_5GHZ(chan))
1029 sifstime = 16;
1030 else
1031 sifstime = 10;
1032 }
0005baf4 1033
e239d859 1034 /* As defined by IEEE 802.11-2007 17.3.8.6 */
b6ba41bb 1035 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
adb5066a 1036 ctstimeout = acktimeout;
42c4568a
FF		 1037
1038 /*
1039 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1040 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1041 * This was initially only meant to work around an issue with delayed
1042 * BA frames in some implementations, but it has been found to fix ACK
1043 * timeout issues in other cases as well.
1044 */
55a2bb4a 1045 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) {
42c4568a 1046 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1047 ctstimeout += 48 - sifstime - ah->slottime;
1048 }
1049
42c4568a 1050
b6ba41bb
FF		 1051 ath9k_hw_set_sifs_time(ah, sifstime);
1052 ath9k_hw_setslottime(ah, slottime);
0005baf4 1053 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1054 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1055 if (ah->globaltxtimeout != (u32) -1)
1056 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1057
1058 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1059 REG_RMW(ah, AR_USEC,
1060 (common->clockrate - 1) |
1061 SM(rx_lat, AR_USEC_RX_LAT) |
1062 SM(tx_lat, AR_USEC_TX_LAT),
1063 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1064
f1dc5600 1065}
0005baf4 1066EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1067
285f2dda 1068void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1069{
211f5859
LR		 1070 struct ath_common *common = ath9k_hw_common(ah);
1071
736b3a27 1072 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 1073 goto free_hw;
1074
9ecdef4b 1075 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 1076
1077free_hw:
8fe65368 1078 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 1079}
285f2dda 1080EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1081
f1dc5600
S		 1082/*******/
1083/* INI */
1084/*******/
1085
8fe65368 1086u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1087{
1088 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1089
1090 if (IS_CHAN_B(chan))
1091 ctl |= CTL_11B;
1092 else if (IS_CHAN_G(chan))
1093 ctl |= CTL_11G;
1094 else
1095 ctl |= CTL_11A;
1096
1097 return ctl;
1098}
1099
f1dc5600
S		 1100/****************************************/
1101/* Reset and Channel Switching Routines */
1102/****************************************/
f1dc5600 1103
cbe61d8a 1104static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1105{
57b32227 1106 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 1107
7d0d0df0
S		 1108 ENABLE_REGWRITE_BUFFER(ah);
1109
d7e7d229
LR		 1110 /*
1111 * set AHB_MODE not to do cacheline prefetches
1112 */
ca7a4deb
FF		 1113 if (!AR_SREV_9300_20_OR_LATER(ah))
1114 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1115
d7e7d229
LR		 1116 /*
1117 * let mac dma reads be in 128 byte chunks
1118 */
ca7a4deb 1119 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1120
7d0d0df0 1121 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1122
d7e7d229
LR		 1123 /*
1124 * Restore TX Trigger Level to its pre-reset value.
1125 * The initial value depends on whether aggregation is enabled, and is
1126 * adjusted whenever underruns are detected.
1127 */
57b32227
FF		 1128 if (!AR_SREV_9300_20_OR_LATER(ah))
1129 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1130
7d0d0df0 1131 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1132
d7e7d229
LR		 1133 /*
1134 * let mac dma writes be in 128 byte chunks
1135 */
ca7a4deb 1136 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1137
d7e7d229
LR		 1138 /*
1139 * Setup receive FIFO threshold to hold off TX activities
1140 */
f1dc5600
S		 1141 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1142
57b32227
FF		 1143 if (AR_SREV_9300_20_OR_LATER(ah)) {
1144 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1145 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1146
1147 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1148 ah->caps.rx_status_len);
1149 }
1150
d7e7d229
LR		 1151 /*
1152 * reduce the number of usable entries in PCU TXBUF to avoid
1153 * wrap around issues.
1154 */
f1dc5600 1155 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1156 /* For AR9285 the number of Fifos are reduced to half.
1157 * So set the usable tx buf size also to half to
1158 * avoid data/delimiter underruns
1159 */
f1dc5600
S		 1160 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1161 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1162 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1163 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1164 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1165 }
744d4025 1166
7d0d0df0 1167 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1168
744d4025
VT		 1169 if (AR_SREV_9300_20_OR_LATER(ah))
1170 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1171}
1172
cbe61d8a 1173static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1174{
ca7a4deb
FF		 1175 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1176 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1177
f1dc5600 1178 switch (opmode) {
d97809db 1179 case NL80211_IFTYPE_ADHOC:
9cb5412b 1180 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb 1181 set |= AR_STA_ID1_ADHOC;
f1dc5600 1182 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1183 break;
ca7a4deb
FF		 1184 case NL80211_IFTYPE_AP:
1185 set |= AR_STA_ID1_STA_AP;
1186 /* fall through */
d97809db 1187 case NL80211_IFTYPE_STATION:
ca7a4deb 1188 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1189 break;
5f841b41 1190 default:
ca7a4deb
FF		 1191 if (!ah->is_monitoring)
1192 set = 0;
5f841b41 1193 break;
f1dc5600 1194 }
ca7a4deb 1195 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1196}
1197
8fe65368
LR		 1198void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1199 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1200{
1201 u32 coef_exp, coef_man;
1202
1203 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1204 if ((coef_scaled >> coef_exp) & 0x1)
1205 break;
1206
1207 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1208
1209 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1210
1211 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1212 *coef_exponent = coef_exp - 16;
1213}
1214
cbe61d8a 1215static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1216{
1217 u32 rst_flags;
1218 u32 tmpReg;
1219
70768496 1220 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1221 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1222 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1223 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1224 }
1225
7d0d0df0
S		 1226 ENABLE_REGWRITE_BUFFER(ah);
1227
9a658d2b
LR		 1228 if (AR_SREV_9300_20_OR_LATER(ah)) {
1229 REG_WRITE(ah, AR_WA, ah->WARegVal);
1230 udelay(10);
1231 }
1232
f1dc5600
S		 1233 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1234 AR_RTC_FORCE_WAKE_ON_INT);
1235
1236 if (AR_SREV_9100(ah)) {
1237 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1238 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1239 } else {
1240 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1241 if (tmpReg &
1242 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1243 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1244 u32 val;
f1dc5600 1245 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1246
1247 val = AR_RC_HOSTIF;
1248 if (!AR_SREV_9300_20_OR_LATER(ah))
1249 val |= AR_RC_AHB;
1250 REG_WRITE(ah, AR_RC, val);
1251
1252 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1253 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1254
1255 rst_flags = AR_RTC_RC_MAC_WARM;
1256 if (type == ATH9K_RESET_COLD)
1257 rst_flags |= AR_RTC_RC_MAC_COLD;
1258 }
1259
7d95847c
GJ		 1260 if (AR_SREV_9330(ah)) {
1261 int npend = 0;
1262 int i;
1263
1264 /* AR9330 WAR:
1265 * call external reset function to reset WMAC if:
1266 * - doing a cold reset
1267 * - we have pending frames in the TX queues
1268 */
1269
1270 for (i = 0; i < AR_NUM_QCU; i++) {
1271 npend = ath9k_hw_numtxpending(ah, i);
1272 if (npend)
1273 break;
1274 }
1275
1276 if (ah->external_reset &&
1277 (npend || type == ATH9K_RESET_COLD)) {
1278 int reset_err = 0;
1279
d2182b69 1280 ath_dbg(ath9k_hw_common(ah), RESET,
7d95847c
GJ		 1281 "reset MAC via external reset\n");
1282
1283 reset_err = ah->external_reset();
1284 if (reset_err) {
1285 ath_err(ath9k_hw_common(ah),
1286 "External reset failed, err=%d\n",
1287 reset_err);
1288 return false;
1289 }
1290
1291 REG_WRITE(ah, AR_RTC_RESET, 1);
1292 }
1293 }
1294
d03a66c1 1295 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1296
1297 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1298
f1dc5600
S		 1299 udelay(50);
1300
d03a66c1 1301 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1302 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1303 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1304 return false;
1305 }
1306
1307 if (!AR_SREV_9100(ah))
1308 REG_WRITE(ah, AR_RC, 0);
1309
f1dc5600
S		 1310 if (AR_SREV_9100(ah))
1311 udelay(50);
1312
1313 return true;
1314}
1315
cbe61d8a 1316static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1317{
7d0d0df0
S		 1318 ENABLE_REGWRITE_BUFFER(ah);
1319
9a658d2b
LR		 1320 if (AR_SREV_9300_20_OR_LATER(ah)) {
1321 REG_WRITE(ah, AR_WA, ah->WARegVal);
1322 udelay(10);
1323 }
1324
f1dc5600
S		 1325 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1326 AR_RTC_FORCE_WAKE_ON_INT);
1327
42d5bc3f 1328 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1329 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1330
d03a66c1 1331 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1332
7d0d0df0 1333 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1334
84e2169b
SB		 1335 if (!AR_SREV_9300_20_OR_LATER(ah))
1336 udelay(2);
1337
1338 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1339 REG_WRITE(ah, AR_RC, 0);
1340
d03a66c1 1341 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1342
1343 if (!ath9k_hw_wait(ah,
1344 AR_RTC_STATUS,
1345 AR_RTC_STATUS_M,
0caa7b14
S		 1346 AR_RTC_STATUS_ON,
1347 AH_WAIT_TIMEOUT)) {
d2182b69 1348 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1349 return false;
f078f209
LR		 1350 }
1351
f1dc5600
S		 1352 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1353}
1354
cbe61d8a 1355static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1356{
7a9233ff 1357 bool ret = false;
2577c6e8 1358
9a658d2b
LR		 1359 if (AR_SREV_9300_20_OR_LATER(ah)) {
1360 REG_WRITE(ah, AR_WA, ah->WARegVal);
1361 udelay(10);
1362 }
1363
f1dc5600
S		 1364 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1365 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1366
1367 switch (type) {
1368 case ATH9K_RESET_POWER_ON:
7a9233ff
MSS		 1369 ret = ath9k_hw_set_reset_power_on(ah);
1370 break;
f1dc5600
S		 1371 case ATH9K_RESET_WARM:
1372 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1373 ret = ath9k_hw_set_reset(ah, type);
1374 break;
f1dc5600 1375 default:
7a9233ff 1376 break;
f1dc5600 1377 }
7a9233ff
MSS		 1378
1379 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1380 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1381
1382 return ret;
f078f209
LR		 1383}
1384
cbe61d8a 1385static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1386 struct ath9k_channel *chan)
f078f209 1387{
42abfbee 1388 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1389 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1390 return false;
1391 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1392 return false;
f078f209 1393
9ecdef4b 1394 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1395 return false;
f078f209 1396
2660b81a 1397 ah->chip_fullsleep = false;
f1dc5600 1398 ath9k_hw_init_pll(ah, chan);
f1dc5600 1399 ath9k_hw_set_rfmode(ah, chan);
f078f209 1400
f1dc5600 1401 return true;
f078f209
LR		 1402}
1403
cbe61d8a 1404static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1405 struct ath9k_channel *chan)
f078f209 1406{
c46917bb 1407 struct ath_common *common = ath9k_hw_common(ah);
8fe65368 1408 u32 qnum;
0a3b7bac 1409 int r;
5f0c04ea
RM		 1410 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1411 bool band_switch, mode_diff;
1412 u8 ini_reloaded;
1413
1414 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1415 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1416 CHANNEL_5GHZ));
1417 mode_diff = (chan->chanmode != ah->curchan->chanmode);
f078f209
LR		 1418
1419 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1420 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1421 ath_dbg(common, QUEUE,
226afe68 1422 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1423 return false;
1424 }
1425 }
1426
8fe65368 1427 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1428 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1429 return false;
1430 }
1431
5f0c04ea
RM		 1432 if (edma && (band_switch || mode_diff)) {
1433 ath9k_hw_mark_phy_inactive(ah);
1434 udelay(5);
1435
1436 ath9k_hw_init_pll(ah, NULL);
1437
1438 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1439 ath_err(common, "Failed to do fast channel change\n");
1440 return false;
1441 }
1442 }
1443
8fe65368 1444 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1445
8fe65368 1446 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1447 if (r) {
3800276a 1448 ath_err(common, "Failed to set channel\n");
0a3b7bac 1449 return false;
f078f209 1450 }
dfdac8ac 1451 ath9k_hw_set_clockrate(ah);
ca2c68cc 1452 ath9k_hw_apply_txpower(ah, chan);
8fe65368 1453 ath9k_hw_rfbus_done(ah);
f078f209 1454
f1dc5600
S		 1455 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1456 ath9k_hw_set_delta_slope(ah, chan);
1457
8fe65368 1458 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1459
5f0c04ea 1460 if (edma && (band_switch || mode_diff)) {
a126ff51 1461 ah->ah_flags |= AH_FASTCC;
5f0c04ea
RM		 1462 if (band_switch || ini_reloaded)
1463 ah->eep_ops->set_board_values(ah, chan);
1464
1465 ath9k_hw_init_bb(ah, chan);
1466
1467 if (band_switch || ini_reloaded)
1468 ath9k_hw_init_cal(ah, chan);
a126ff51 1469 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1470 }
1471
f1dc5600
S		 1472 return true;
1473}
1474
691680b8
FF		 1475static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1476{
1477 u32 gpio_mask = ah->gpio_mask;
1478 int i;
1479
1480 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1481 if (!(gpio_mask & 1))
1482 continue;
1483
1484 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1485 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1486 }
1487}
1488
c9c99e5e 1489bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1490{
c9c99e5e
FF		 1491 int count = 50;
1492 u32 reg;
1493
e17f83ea 1494 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1495 return true;
1496
1497 do {
1498 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1499
c9c99e5e
FF		 1500 if ((reg & 0x7E7FFFEF) == 0x00702400)
1501 continue;
1502
1503 switch (reg & 0x7E000B00) {
1504 case 0x1E000000:
1505 case 0x52000B00:
1506 case 0x18000B00:
1507 continue;
1508 default:
1509 return true;
1510 }
1511 } while (count-- > 0);
3b319aae 1512
c9c99e5e 1513 return false;
3b319aae 1514}
c9c99e5e 1515EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1516
cbe61d8a 1517int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 1518 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
f078f209 1519{
1510718d 1520 struct ath_common *common = ath9k_hw_common(ah);
63d32967 1521 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
f078f209 1522 u32 saveLedState;
2660b81a 1523 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1524 u32 saveDefAntenna;
1525 u32 macStaId1;
46fe782c 1526 u64 tsf = 0;
8fe65368 1527 int i, r;
a126ff51 1528 bool allow_fbs = false;
63d32967
MSS		 1529 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1530 bool save_fullsleep = ah->chip_fullsleep;
1531
1532 if (mci) {
1533
1534 ar9003_mci_2g5g_changed(ah, IS_CHAN_2GHZ(chan));
1535
1536 if (mci_hw->bt_state == MCI_BT_CAL_START) {
1537 u32 payload[4] = {0, 0, 0, 0};
1538
d2182b69 1539 ath_dbg(common, MCI, "MCI stop rx for BT CAL\n");
63d32967
MSS		 1540
1541 mci_hw->bt_state = MCI_BT_CAL;
1542
1543 /*
1544 * MCI FIX: disable mci interrupt here. This is to avoid
1545 * SW_MSG_DONE or RX_MSG bits to trigger MCI_INT and
1546 * lead to mci_intr reentry.
1547 */
1548
1549 ar9003_mci_disable_interrupt(ah);
1550
d2182b69 1551 ath_dbg(common, MCI, "send WLAN_CAL_GRANT\n");
63d32967
MSS		 1552 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT);
1553 ar9003_mci_send_message(ah, MCI_GPM, 0, payload,
1554 16, true, false);
1555
d2182b69 1556 ath_dbg(common, MCI, "\nMCI BT is calibrating\n");
63d32967
MSS		 1557
1558 /* Wait BT calibration to be completed for 25ms */
1559
1560 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE,
1561 0, 25000))
d2182b69 1562 ath_dbg(common, MCI,
63d32967
MSS		 1563 "MCI got BT_CAL_DONE\n");
1564 else
d2182b69
JP		 1565 ath_dbg(common, MCI,
1566 "MCI ### BT cal takes to long, force bt_state to be bt_awake\n");
63d32967
MSS		 1567 mci_hw->bt_state = MCI_BT_AWAKE;
1568 /* MCI FIX: enable mci interrupt here */
1569 ar9003_mci_enable_interrupt(ah);
1570
1571 return true;
1572 }
1573 }
1574
f078f209 1575
9ecdef4b 1576 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1577 return -EIO;
f078f209 1578
d9891c78 1579 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1580 ath9k_hw_getnf(ah, curchan);
1581
20bd2a09
FF		 1582 ah->caldata = caldata;
1583 if (caldata &&
1584 (chan->channel != caldata->channel ||
1585 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1586 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1587 /* Operating channel changed, reset channel calibration data */
1588 memset(caldata, 0, sizeof(*caldata));
1589 ath9k_init_nfcal_hist_buffer(ah, chan);
1590 }
f23fba49 1591 ah->noise = ath9k_hw_getchan_noise(ah, chan);
20bd2a09 1592
19787b25 1593 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
7db062ac
RM		 1594 bChannelChange = false;
1595
a126ff51
RM		 1596 if (caldata &&
1597 caldata->done_txiqcal_once &&
1598 caldata->done_txclcal_once &&
1599 caldata->rtt_hist.num_readings)
1600 allow_fbs = true;
1601
f078f209 1602 if (bChannelChange &&
2660b81a
S		 1603 (ah->chip_fullsleep != true) &&
1604 (ah->curchan != NULL) &&
1605 (chan->channel != ah->curchan->channel) &&
a126ff51
RM		 1606 (allow_fbs ||
1607 ((chan->channelFlags & CHANNEL_ALL) ==
1608 (ah->curchan->channelFlags & CHANNEL_ALL)))) {
25c56eec 1609 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1610 ath9k_hw_loadnf(ah, ah->curchan);
00c86590 1611 ath9k_hw_start_nfcal(ah, true);
63d32967
MSS		 1612 if (mci && mci_hw->ready)
1613 ar9003_mci_2g5g_switch(ah, true);
1614
c2ba3342
RM		 1615 if (AR_SREV_9271(ah))
1616 ar9002_hw_load_ani_reg(ah, chan);
ae8d2858 1617 return 0;
f078f209
LR		 1618 }
1619 }
1620
63d32967
MSS		 1621 if (mci) {
1622 ar9003_mci_disable_interrupt(ah);
1623
1624 if (mci_hw->ready && !save_fullsleep) {
1625 ar9003_mci_mute_bt(ah);
1626 udelay(20);
1627 REG_WRITE(ah, AR_BTCOEX_CTRL, 0);
1628 }
1629
1630 mci_hw->bt_state = MCI_BT_SLEEP;
1631 mci_hw->ready = false;
1632 }
1633
1634
f078f209
LR		 1635 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1636 if (saveDefAntenna == 0)
1637 saveDefAntenna = 1;
1638
1639 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1640
46fe782c 1641 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1642 if (AR_SREV_9100(ah) ||
1643 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1644 tsf = ath9k_hw_gettsf64(ah);
1645
f078f209
LR		 1646 saveLedState = REG_READ(ah, AR_CFG_LED) &
1647 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1648 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1649
1650 ath9k_hw_mark_phy_inactive(ah);
1651
45ef6a0b
VT		 1652 ah->paprd_table_write_done = false;
1653
05020d23 1654 /* Only required on the first reset */
d7e7d229
LR		 1655 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1656 REG_WRITE(ah,
1657 AR9271_RESET_POWER_DOWN_CONTROL,
1658 AR9271_RADIO_RF_RST);
1659 udelay(50);
1660 }
1661
f078f209 1662 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1663 ath_err(common, "Chip reset failed\n");
ae8d2858 1664 return -EINVAL;
f078f209
LR		 1665 }
1666
05020d23 1667 /* Only required on the first reset */
d7e7d229
LR		 1668 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1669 ah->htc_reset_init = false;
1670 REG_WRITE(ah,
1671 AR9271_RESET_POWER_DOWN_CONTROL,
1672 AR9271_GATE_MAC_CTL);
1673 udelay(50);
1674 }
1675
46fe782c 1676 /* Restore TSF */
f860d526 1677 if (tsf)
46fe782c
S		 1678 ath9k_hw_settsf64(ah, tsf);
1679
7a37081e 1680 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1681 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1682
e9141f71
S		 1683 if (!AR_SREV_9300_20_OR_LATER(ah))
1684 ar9002_hw_enable_async_fifo(ah);
1685
25c56eec 1686 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1687 if (r)
1688 return r;
f078f209 1689
63d32967
MSS		 1690 if (mci)
1691 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1692
f860d526
FF		 1693 /*
1694 * Some AR91xx SoC devices frequently fail to accept TSF writes
1695 * right after the chip reset. When that happens, write a new
1696 * value after the initvals have been applied, with an offset
1697 * based on measured time difference
1698 */
1699 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1700 tsf += 1500;
1701 ath9k_hw_settsf64(ah, tsf);
1702 }
1703
0ced0e17
JM		 1704 /* Setup MFP options for CCMP */
1705 if (AR_SREV_9280_20_OR_LATER(ah)) {
1706 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1707 * frames when constructing CCMP AAD. */
1708 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1709 0xc7ff);
1710 ah->sw_mgmt_crypto = false;
1711 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1712 /* Disable hardware crypto for management frames */
1713 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1714 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1715 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1716 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1717 ah->sw_mgmt_crypto = true;
1718 } else
1719 ah->sw_mgmt_crypto = true;
1720
f078f209
LR		 1721 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1722 ath9k_hw_set_delta_slope(ah, chan);
1723
8fe65368 1724 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1725 ah->eep_ops->set_board_values(ah, chan);
a7765828 1726
7d0d0df0
S		 1727 ENABLE_REGWRITE_BUFFER(ah);
1728
1510718d
LR		 1729 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1730 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1731 | macStaId1
1732 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1733 | (ah->config.
60b67f51 1734 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1735 | ah->sta_id1_defaults);
13b81559 1736 ath_hw_setbssidmask(common);
f078f209 1737 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1738 ath9k_hw_write_associd(ah);
f078f209 1739 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1740 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1741
7d0d0df0 1742 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1743
00e0003e
SM		 1744 ath9k_hw_set_operating_mode(ah, ah->opmode);
1745
8fe65368 1746 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1747 if (r)
1748 return r;
f078f209 1749
dfdac8ac
FF		 1750 ath9k_hw_set_clockrate(ah);
1751
7d0d0df0
S		 1752 ENABLE_REGWRITE_BUFFER(ah);
1753
f078f209
LR		 1754 for (i = 0; i < AR_NUM_DCU; i++)
1755 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1756
7d0d0df0 1757 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1758
2660b81a 1759 ah->intr_txqs = 0;
f4c607dc 1760 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
f078f209
LR		 1761 ath9k_hw_resettxqueue(ah, i);
1762
2660b81a 1763 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1764 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1765 ath9k_hw_init_qos(ah);
1766
2660b81a 1767 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1768 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1769
0005baf4 1770 ath9k_hw_init_global_settings(ah);
f078f209 1771
fe2b6afb
FF		 1772 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1773 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1774 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1775 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1776 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1777 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1778 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1779 }
1780
ca7a4deb 1781 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1782
1783 ath9k_hw_set_dma(ah);
1784
1785 REG_WRITE(ah, AR_OBS, 8);
1786
0ce024cb 1787 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1788 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1789 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1790 }
1791
7f62a136
VT		 1792 if (ah->config.tx_intr_mitigation) {
1793 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1794 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1795 }
1796
f078f209
LR		 1797 ath9k_hw_init_bb(ah, chan);
1798
77a5a664 1799 if (caldata) {
5f0c04ea 1800 caldata->done_txiqcal_once = false;
77a5a664 1801 caldata->done_txclcal_once = false;
324c74ad 1802 caldata->rtt_hist.num_readings = 0;
77a5a664 1803 }
ae8d2858 1804 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1805 return -EIO;
f078f209 1806
93348928
RM		 1807 ath9k_hw_loadnf(ah, chan);
1808 ath9k_hw_start_nfcal(ah, true);
1809
63d32967
MSS		 1810 if (mci && mci_hw->ready) {
1811
1812 if (IS_CHAN_2GHZ(chan) &&
1813 (mci_hw->bt_state == MCI_BT_SLEEP)) {
1814
1815 if (ar9003_mci_check_int(ah,
1816 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) ||
1817 ar9003_mci_check_int(ah,
1818 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) {
1819
1820 /*
1821 * BT is sleeping. Check if BT wakes up during
1822 * WLAN calibration. If BT wakes up during
1823 * WLAN calibration, need to go through all
1824 * message exchanges again and recal.
1825 */
1826
d2182b69
JP		 1827 ath_dbg(common, MCI,
1828 "MCI BT wakes up during WLAN calibration\n");
63d32967
MSS		 1829
1830 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
1831 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET |
1832 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE);
d2182b69 1833 ath_dbg(common, MCI, "MCI send REMOTE_RESET\n");
63d32967
MSS		 1834 ar9003_mci_remote_reset(ah, true);
1835 ar9003_mci_send_sys_waking(ah, true);
1836 udelay(1);
1837 if (IS_CHAN_2GHZ(chan))
1838 ar9003_mci_send_lna_transfer(ah, true);
1839
1840 mci_hw->bt_state = MCI_BT_AWAKE;
1841
d2182b69 1842 ath_dbg(common, MCI, "MCI re-cal\n");
63d32967
MSS		 1843
1844 if (caldata) {
1845 caldata->done_txiqcal_once = false;
1846 caldata->done_txclcal_once = false;
1847 caldata->rtt_hist.num_readings = 0;
1848 }
1849
1850 if (!ath9k_hw_init_cal(ah, chan))
1851 return -EIO;
1852
1853 }
1854 }
1855 ar9003_mci_enable_interrupt(ah);
1856 }
1857
7d0d0df0 1858 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1859
8fe65368 1860 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1861 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1862
7d0d0df0 1863 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1864
d7e7d229
LR		 1865 /*
1866 * For big endian systems turn on swapping for descriptors
1867 */
f078f209
LR		 1868 if (AR_SREV_9100(ah)) {
1869 u32 mask;
1870 mask = REG_READ(ah, AR_CFG);
1871 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
d2182b69
JP		 1872 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1873 mask);
f078f209
LR		 1874 } else {
1875 mask =
1876 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1877 REG_WRITE(ah, AR_CFG, mask);
d2182b69
JP		 1878 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1879 REG_READ(ah, AR_CFG));
f078f209
LR		 1880 }
1881 } else {
cbba8cd1
S		 1882 if (common->bus_ops->ath_bus_type == ATH_USB) {
1883 /* Configure AR9271 target WLAN */
1884 if (AR_SREV_9271(ah))
1885 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1886 else
1887 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1888 }
f078f209 1889#ifdef __BIG_ENDIAN
4033bdad 1890 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
2be7bfe0
VT		 1891 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1892 else
d7e7d229 1893 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1894#endif
1895 }
1896
8a309305
FF		 1897 if (ah->btcoex_hw.enabled &&
1898 ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE)
42cc41ed
VT		 1899 ath9k_hw_btcoex_enable(ah);
1900
63d32967
MSS		 1901 if (mci && mci_hw->ready) {
1902 /*
1903 * check BT state again to make
1904 * sure it's not changed.
1905 */
1906
1907 ar9003_mci_sync_bt_state(ah);
1908 ar9003_mci_2g5g_switch(ah, true);
1909
1910 if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
1911 (mci_hw->query_bt == true)) {
1912 mci_hw->need_flush_btinfo = true;
1913 }
1914 }
1915
51ac8cbb 1916 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 1917 ar9003_hw_bb_watchdog_config(ah);
d8903a53 1918
51ac8cbb
RM		 1919 ar9003_hw_disable_phy_restart(ah);
1920 }
1921
691680b8
FF		 1922 ath9k_hw_apply_gpio_override(ah);
1923
ae8d2858 1924 return 0;
f078f209 1925}
7322fd19 1926EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1927
f1dc5600
S		 1928/******************************/
1929/* Power Management (Chipset) */
1930/******************************/
1931
42d5bc3f
LR		 1932/*
1933 * Notify Power Mgt is disabled in self-generated frames.
1934 * If requested, force chip to sleep.
1935 */
cbe61d8a 1936static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1937{
f1dc5600
S		 1938 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1939 if (setChip) {
423e38e8 1940 if (AR_SREV_9462(ah)) {
2577c6e8
SB		 1941 REG_WRITE(ah, AR_TIMER_MODE,
1942 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
1943 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
1944 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
1945 REG_WRITE(ah, AR_SLP32_INC,
1946 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
1947 /* xxx Required for WLAN only case ? */
1948 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1949 udelay(100);
1950 }
1951
42d5bc3f
LR		 1952 /*
1953 * Clear the RTC force wake bit to allow the
1954 * mac to go to sleep.
1955 */
2577c6e8
SB		 1956 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1957
423e38e8 1958 if (AR_SREV_9462(ah))
2577c6e8
SB		 1959 udelay(100);
1960
42d5bc3f 1961 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1962 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1963
42d5bc3f 1964 /* Shutdown chip. Active low */
c91ec465 1965 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2577c6e8
SB		 1966 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1967 udelay(2);
1968 }
f1dc5600 1969 }
9a658d2b
LR		 1970
1971 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 1972 if (AR_SREV_9300_20_OR_LATER(ah))
1973 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1974}
1975
bbd79af5
LR		 1976/*
1977 * Notify Power Management is enabled in self-generating
1978 * frames. If request, set power mode of chip to
1979 * auto/normal. Duration in units of 128us (1/8 TU).
1980 */
cbe61d8a 1981static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1982{
2577c6e8
SB		 1983 u32 val;
1984
f1dc5600
S		 1985 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1986 if (setChip) {
2660b81a 1987 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1988
f1dc5600 1989 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1990 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1991 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1992 AR_RTC_FORCE_WAKE_ON_INT);
1993 } else {
2577c6e8
SB		 1994
1995 /* When chip goes into network sleep, it could be waken
1996 * up by MCI_INT interrupt caused by BT's HW messages
1997 * (LNA_xxx, CONT_xxx) which chould be in a very fast
1998 * rate (~100us). This will cause chip to leave and
1999 * re-enter network sleep mode frequently, which in
2000 * consequence will have WLAN MCI HW to generate lots of
2001 * SYS_WAKING and SYS_SLEEPING messages which will make
2002 * BT CPU to busy to process.
2003 */
423e38e8 2004 if (AR_SREV_9462(ah)) {
2577c6e8
SB		 2005 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
2006 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
2007 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
2008 }
bbd79af5
LR		 2009 /*
2010 * Clear the RTC force wake bit to allow the
2011 * mac to go to sleep.
2012 */
f1dc5600
S		 2013 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2014 AR_RTC_FORCE_WAKE_EN);
2577c6e8 2015
423e38e8 2016 if (AR_SREV_9462(ah))
2577c6e8 2017 udelay(30);
f078f209 2018 }
f078f209 2019 }
9a658d2b
LR		 2020
2021 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2022 if (AR_SREV_9300_20_OR_LATER(ah))
2023 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2024}
2025
cbe61d8a 2026static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2027{
f1dc5600
S		 2028 u32 val;
2029 int i;
f078f209 2030
9a658d2b
LR		 2031 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2032 if (AR_SREV_9300_20_OR_LATER(ah)) {
2033 REG_WRITE(ah, AR_WA, ah->WARegVal);
2034 udelay(10);
2035 }
2036
f1dc5600
S		 2037 if (setChip) {
2038 if ((REG_READ(ah, AR_RTC_STATUS) &
2039 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2040 if (ath9k_hw_set_reset_reg(ah,
2041 ATH9K_RESET_POWER_ON) != true) {
2042 return false;
2043 }
e041228f
LR		 2044 if (!AR_SREV_9300_20_OR_LATER(ah))
2045 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 2046 }
2047 if (AR_SREV_9100(ah))
2048 REG_SET_BIT(ah, AR_RTC_RESET,
2049 AR_RTC_RESET_EN);
f078f209 2050
f1dc5600
S		 2051 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2052 AR_RTC_FORCE_WAKE_EN);
2053 udelay(50);
f078f209 2054
f1dc5600
S		 2055 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2056 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2057 if (val == AR_RTC_STATUS_ON)
2058 break;
2059 udelay(50);
2060 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2061 AR_RTC_FORCE_WAKE_EN);
f078f209 2062 }
f1dc5600 2063 if (i == 0) {
3800276a
JP		 2064 ath_err(ath9k_hw_common(ah),
2065 "Failed to wakeup in %uus\n",
2066 POWER_UP_TIME / 20);
f1dc5600 2067 return false;
f078f209 2068 }
f078f209
LR		 2069 }
2070
f1dc5600 2071 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2072
f1dc5600 2073 return true;
f078f209
LR		 2074}
2075
9ecdef4b 2076bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2077{
c46917bb 2078 struct ath_common *common = ath9k_hw_common(ah);
1010911e 2079 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
cbe61d8a 2080 int status = true, setChip = true;
f1dc5600
S		 2081 static const char *modes[] = {
2082 "AWAKE",
2083 "FULL-SLEEP",
2084 "NETWORK SLEEP",
2085 "UNDEFINED"
2086 };
f1dc5600 2087
cbdec975
GJ		 2088 if (ah->power_mode == mode)
2089 return status;
2090
d2182b69 2091 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2092 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2093
2094 switch (mode) {
2095 case ATH9K_PM_AWAKE:
2096 status = ath9k_hw_set_power_awake(ah, setChip);
1010911e
MSS		 2097
2098 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2099 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2100
f1dc5600
S		 2101 break;
2102 case ATH9K_PM_FULL_SLEEP:
1010911e
MSS		 2103
2104 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) {
2105 if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) &&
2106 (mci->bt_state != MCI_BT_SLEEP) &&
2107 !mci->halted_bt_gpm) {
d2182b69
JP		 2108 ath_dbg(common, MCI,
2109 "MCI halt BT GPM (full_sleep)\n");
1010911e
MSS		 2110 ar9003_mci_send_coex_halt_bt_gpm(ah,
2111 true, true);
2112 }
2113
2114 mci->ready = false;
2115 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2116 }
2117
f1dc5600 2118 ath9k_set_power_sleep(ah, setChip);
2660b81a 2119 ah->chip_fullsleep = true;
f1dc5600
S		 2120 break;
2121 case ATH9K_PM_NETWORK_SLEEP:
1010911e
MSS		 2122
2123 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2124 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2125
f1dc5600
S		 2126 ath9k_set_power_network_sleep(ah, setChip);
2127 break;
f078f209 2128 default:
3800276a 2129 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2130 return false;
2131 }
2660b81a 2132 ah->power_mode = mode;
f1dc5600 2133
69f4aab1
LR		 2134 /*
2135 * XXX: If this warning never comes up after a while then
2136 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2137 * ath9k_hw_setpower() return type void.
2138 */
97dcec57
SM		 2139
2140 if (!(ah->ah_flags & AH_UNPLUGGED))
2141 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2142
f1dc5600 2143 return status;
f078f209 2144}
7322fd19 2145EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2146
f1dc5600
S		 2147/*******************/
2148/* Beacon Handling */
2149/*******************/
2150
cbe61d8a 2151void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2152{
f078f209
LR		 2153 int flags = 0;
2154
7d0d0df0
S		 2155 ENABLE_REGWRITE_BUFFER(ah);
2156
2660b81a 2157 switch (ah->opmode) {
d97809db 2158 case NL80211_IFTYPE_ADHOC:
9cb5412b 2159 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 2160 REG_SET_BIT(ah, AR_TXCFG,
2161 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
dd347f2f
FF		 2162 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2163 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
f078f209 2164 flags |= AR_NDP_TIMER_EN;
d97809db 2165 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2166 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2167 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2168 TU_TO_USEC(ah->config.dma_beacon_response_time));
2169 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2170 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2171 flags |=
2172 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2173 break;
d97809db 2174 default:
d2182b69
JP		 2175 ath_dbg(ath9k_hw_common(ah), BEACON,
2176 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2177 return;
2178 break;
f078f209
LR		 2179 }
2180
dd347f2f
FF		 2181 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2182 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2183 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2184 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
f078f209 2185
7d0d0df0 2186 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2187
f078f209
LR		 2188 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2189}
7322fd19 2190EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2191
cbe61d8a 2192void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2193 const struct ath9k_beacon_state *bs)
f078f209
LR		 2194{
2195 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2196 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2197 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2198
7d0d0df0
S		 2199 ENABLE_REGWRITE_BUFFER(ah);
2200
f078f209
LR		 2201 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2202
2203 REG_WRITE(ah, AR_BEACON_PERIOD,
f29f5c08 2204 TU_TO_USEC(bs->bs_intval));
f078f209 2205 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
f29f5c08 2206 TU_TO_USEC(bs->bs_intval));
f078f209 2207
7d0d0df0 2208 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2209
f078f209
LR		 2210 REG_RMW_FIELD(ah, AR_RSSI_THR,
2211 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2212
f29f5c08 2213 beaconintval = bs->bs_intval;
f078f209
LR		 2214
2215 if (bs->bs_sleepduration > beaconintval)
2216 beaconintval = bs->bs_sleepduration;
2217
2218 dtimperiod = bs->bs_dtimperiod;
2219 if (bs->bs_sleepduration > dtimperiod)
2220 dtimperiod = bs->bs_sleepduration;
2221
2222 if (beaconintval == dtimperiod)
2223 nextTbtt = bs->bs_nextdtim;
2224 else
2225 nextTbtt = bs->bs_nexttbtt;
2226
d2182b69
JP		 2227 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2228 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2229 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2230 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2231
7d0d0df0
S		 2232 ENABLE_REGWRITE_BUFFER(ah);
2233
f1dc5600
S		 2234 REG_WRITE(ah, AR_NEXT_DTIM,
2235 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2236 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 2237
f1dc5600
S		 2238 REG_WRITE(ah, AR_SLEEP1,
2239 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2240 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2241
f1dc5600
S		 2242 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2243 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2244 else
2245 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2246
f1dc5600
S		 2247 REG_WRITE(ah, AR_SLEEP2,
2248 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2249
f1dc5600
S		 2250 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2251 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2252
7d0d0df0 2253 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2254
f1dc5600
S		 2255 REG_SET_BIT(ah, AR_TIMER_MODE,
2256 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2257 AR_DTIM_TIMER_EN);
f078f209 2258
4af9cf4f
S		 2259 /* TSF Out of Range Threshold */
2260 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2261}
7322fd19 2262EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2263
f1dc5600
S		 2264/*******************/
2265/* HW Capabilities */
2266/*******************/
2267
6054069a
FF		 2268static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2269{
2270 eeprom_chainmask &= chip_chainmask;
2271 if (eeprom_chainmask)
2272 return eeprom_chainmask;
2273 else
2274 return chip_chainmask;
2275}
2276
9a66af33
ZK		 2277/**
2278 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2279 * @ah: the atheros hardware data structure
2280 *
2281 * We enable DFS support upstream on chipsets which have passed a series
2282 * of tests. The testing requirements are going to be documented. Desired
2283 * test requirements are documented at:
2284 *
2285 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2286 *
2287 * Once a new chipset gets properly tested an individual commit can be used
2288 * to document the testing for DFS for that chipset.
2289 */
2290static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2291{
2292
2293 switch (ah->hw_version.macVersion) {
2294 /* AR9580 will likely be our first target to get testing on */
2295 case AR_SREV_VERSION_9580:
2296 default:
2297 return false;
2298 }
2299}
2300
a9a29ce6 2301int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2302{
2660b81a 2303 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2304 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2305 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2306 unsigned int chip_chainmask;
608b88cb 2307
0ff2b5c0 2308 u16 eeval;
47c80de6 2309 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2310
f74df6fb 2311 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2312 regulatory->current_rd = eeval;
f078f209 2313
2660b81a 2314 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2315 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2316 if (regulatory->current_rd == 0x64 ||
2317 regulatory->current_rd == 0x65)
2318 regulatory->current_rd += 5;
2319 else if (regulatory->current_rd == 0x41)
2320 regulatory->current_rd = 0x43;
d2182b69
JP		 2321 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2322 regulatory->current_rd);
f1dc5600 2323 }
f078f209 2324
f74df6fb 2325 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2326 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2327 ath_err(common,
2328 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2329 return -EINVAL;
2330 }
2331
d4659912
FF		 2332 if (eeval & AR5416_OPFLAGS_11A)
2333 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2334
d4659912
FF		 2335 if (eeval & AR5416_OPFLAGS_11G)
2336 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2337
6054069a
FF		 2338 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2339 chip_chainmask = 1;
ba5736a5
MSS		 2340 else if (AR_SREV_9462(ah))
2341 chip_chainmask = 3;
6054069a
FF		 2342 else if (!AR_SREV_9280_20_OR_LATER(ah))
2343 chip_chainmask = 7;
2344 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2345 chip_chainmask = 3;
2346 else
2347 chip_chainmask = 7;
2348
f74df6fb 2349 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2350 /*
2351 * For AR9271 we will temporarilly uses the rx chainmax as read from
2352 * the EEPROM.
2353 */
8147f5de 2354 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2355 !(eeval & AR5416_OPFLAGS_11A) &&
2356 !(AR_SREV_9271(ah)))
2357 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2358 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2359 else if (AR_SREV_9100(ah))
2360 pCap->rx_chainmask = 0x7;
8147f5de 2361 else
d7e7d229 2362 /* Use rx_chainmask from EEPROM. */
8147f5de 2363 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2364
6054069a
FF		 2365 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2366 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2367 ah->txchainmask = pCap->tx_chainmask;
2368 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2369
7a37081e 2370 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2371
02d2ebb2
FF		 2372 /* enable key search for every frame in an aggregate */
2373 if (AR_SREV_9300_20_OR_LATER(ah))
2374 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2375
ce2220d1
BR		 2376 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2377
0db156e9 2378 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2379 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2380 else
2381 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2382
5b5fa355
S		 2383 if (AR_SREV_9271(ah))
2384 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2385 else if (AR_DEVID_7010(ah))
2386 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2387 else if (AR_SREV_9300_20_OR_LATER(ah))
2388 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2389 else if (AR_SREV_9287_11_OR_LATER(ah))
2390 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2391 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2392 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2393 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2394 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2395 else
2396 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2397
1b2538b2 2398 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2399 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2400 else
f1dc5600 2401 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2402
e97275cb 2403#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2404 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2405 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2406 ah->rfkill_gpio =
2407 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2408 ah->rfkill_polarity =
2409 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2410
2411 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2412 }
f1dc5600 2413#endif
d5d1154f 2414 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2415 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2416 else
2417 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2418
e7594072 2419 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2420 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2421 else
2422 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2423
ceb26445 2424 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2425 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
0e707a94 2426 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
784ad503
VT		 2427 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2428
ceb26445
VT		 2429 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2430 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2431 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2432 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2433 pCap->txs_len = sizeof(struct ar9003_txs);
6f481010
LR		 2434 if (!ah->config.paprd_disable &&
2435 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
4935250a 2436 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 2437 } else {
2438 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2439 if (AR_SREV_9280_20(ah))
6b42e8d0 2440 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2441 }
1adf02ff 2442
6c84ce08
VT		 2443 if (AR_SREV_9300_20_OR_LATER(ah))
2444 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2445
6ee63f55
SB		 2446 if (AR_SREV_9300_20_OR_LATER(ah))
2447 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2448
a42acef0 2449 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2450 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2451
754dc536
VT		 2452 if (AR_SREV_9285(ah))
2453 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2454 ant_div_ctl1 =
2455 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2456 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2457 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2458 }
ea066d5a
MSS		 2459 if (AR_SREV_9300_20_OR_LATER(ah)) {
2460 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2461 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2462 }
2463
2464
431da56a 2465 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
21d2c63a
MSS		 2466 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2467 /*
2468 * enable the diversity-combining algorithm only when
2469 * both enable_lna_div and enable_fast_div are set
2470 * Table for Diversity
2471 * ant_div_alt_lnaconf bit 0-1
2472 * ant_div_main_lnaconf bit 2-3
2473 * ant_div_alt_gaintb bit 4
2474 * ant_div_main_gaintb bit 5
2475 * enable_ant_div_lnadiv bit 6
2476 * enable_ant_fast_div bit 7
2477 */
2478 if ((ant_div_ctl1 >> 0x6) == 0x3)
2479 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2480 }
754dc536 2481
8060e169
VT		 2482 if (AR_SREV_9485_10(ah)) {
2483 pCap->pcie_lcr_extsync_en = true;
2484 pCap->pcie_lcr_offset = 0x80;
2485 }
2486
9a66af33
ZK		 2487 if (ath9k_hw_dfs_tested(ah))
2488 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2489
47c80de6
VT		 2490 tx_chainmask = pCap->tx_chainmask;
2491 rx_chainmask = pCap->rx_chainmask;
2492 while (tx_chainmask || rx_chainmask) {
2493 if (tx_chainmask & BIT(0))
2494 pCap->max_txchains++;
2495 if (rx_chainmask & BIT(0))
2496 pCap->max_rxchains++;
2497
2498 tx_chainmask >>= 1;
2499 rx_chainmask >>= 1;
2500 }
2501
8ad74c4d
RM		 2502 if (AR_SREV_9300_20_OR_LATER(ah)) {
2503 ah->enabled_cals |= TX_IQ_CAL;
6fea593d 2504 if (AR_SREV_9485_OR_LATER(ah))
8ad74c4d
RM		 2505 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2506 }
423e38e8 2507 if (AR_SREV_9462(ah))
7dc181c2 2508 pCap->hw_caps |= ATH9K_HW_CAP_RTT | ATH9K_HW_CAP_MCI;
324c74ad 2509
a9a29ce6 2510 return 0;
f078f209
LR		 2511}
2512
f1dc5600
S		 2513/****************************/
2514/* GPIO / RFKILL / Antennae */
2515/****************************/
f078f209 2516
cbe61d8a 2517static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2518 u32 gpio, u32 type)
2519{
2520 int addr;
2521 u32 gpio_shift, tmp;
f078f209 2522
f1dc5600
S		 2523 if (gpio > 11)
2524 addr = AR_GPIO_OUTPUT_MUX3;
2525 else if (gpio > 5)
2526 addr = AR_GPIO_OUTPUT_MUX2;
2527 else
2528 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2529
f1dc5600 2530 gpio_shift = (gpio % 6) * 5;
f078f209 2531
f1dc5600
S		 2532 if (AR_SREV_9280_20_OR_LATER(ah)
2533 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2534 REG_RMW(ah, addr, (type << gpio_shift),
2535 (0x1f << gpio_shift));
f078f209 2536 } else {
f1dc5600
S		 2537 tmp = REG_READ(ah, addr);
2538 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2539 tmp &= ~(0x1f << gpio_shift);
2540 tmp |= (type << gpio_shift);
2541 REG_WRITE(ah, addr, tmp);
f078f209 2542 }
f078f209
LR		 2543}
2544
cbe61d8a 2545void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2546{
f1dc5600 2547 u32 gpio_shift;
f078f209 2548
9680e8a3 2549 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2550
88c1f4f6
S		 2551 if (AR_DEVID_7010(ah)) {
2552 gpio_shift = gpio;
2553 REG_RMW(ah, AR7010_GPIO_OE,
2554 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2555 (AR7010_GPIO_OE_MASK << gpio_shift));
2556 return;
2557 }
f078f209 2558
88c1f4f6 2559 gpio_shift = gpio << 1;
f1dc5600
S		 2560 REG_RMW(ah,
2561 AR_GPIO_OE_OUT,
2562 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2563 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2564}
7322fd19 2565EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2566
cbe61d8a 2567u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2568{
cb33c412
SB		 2569#define MS_REG_READ(x, y) \
2570 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2571
2660b81a 2572 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2573 return 0xffffffff;
f078f209 2574
88c1f4f6
S		 2575 if (AR_DEVID_7010(ah)) {
2576 u32 val;
2577 val = REG_READ(ah, AR7010_GPIO_IN);
2578 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2579 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2580 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2581 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2582 else if (AR_SREV_9271(ah))
5b5fa355 2583 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2584 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2585 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2586 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2587 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2588 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2589 return MS_REG_READ(AR928X, gpio) != 0;
2590 else
2591 return MS_REG_READ(AR, gpio) != 0;
f078f209 2592}
7322fd19 2593EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2594
cbe61d8a 2595void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2596 u32 ah_signal_type)
f078f209 2597{
f1dc5600 2598 u32 gpio_shift;
f078f209 2599
88c1f4f6
S		 2600 if (AR_DEVID_7010(ah)) {
2601 gpio_shift = gpio;
2602 REG_RMW(ah, AR7010_GPIO_OE,
2603 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2604 (AR7010_GPIO_OE_MASK << gpio_shift));
2605 return;
2606 }
f078f209 2607
88c1f4f6 2608 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2609 gpio_shift = 2 * gpio;
f1dc5600
S		 2610 REG_RMW(ah,
2611 AR_GPIO_OE_OUT,
2612 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2613 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2614}
7322fd19 2615EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2616
cbe61d8a 2617void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2618{
88c1f4f6
S		 2619 if (AR_DEVID_7010(ah)) {
2620 val = val ? 0 : 1;
2621 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2622 AR_GPIO_BIT(gpio));
2623 return;
2624 }
2625
5b5fa355
S		 2626 if (AR_SREV_9271(ah))
2627 val = ~val;
2628
f1dc5600
S		 2629 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2630 AR_GPIO_BIT(gpio));
f078f209 2631}
7322fd19 2632EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2633
cbe61d8a 2634u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2635{
f1dc5600 2636 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2637}
7322fd19 2638EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2639
cbe61d8a 2640void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2641{
f1dc5600 2642 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2643}
7322fd19 2644EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2645
f1dc5600
S		 2646/*********************/
2647/* General Operation */
2648/*********************/
2649
cbe61d8a 2650u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2651{
f1dc5600
S		 2652 u32 bits = REG_READ(ah, AR_RX_FILTER);
2653 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2654
f1dc5600
S		 2655 if (phybits & AR_PHY_ERR_RADAR)
2656 bits |= ATH9K_RX_FILTER_PHYRADAR;
2657 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2658 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2659
f1dc5600 2660 return bits;
f078f209 2661}
7322fd19 2662EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2663
cbe61d8a 2664void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2665{
f1dc5600 2666 u32 phybits;
f078f209 2667
7d0d0df0
S		 2668 ENABLE_REGWRITE_BUFFER(ah);
2669
423e38e8 2670 if (AR_SREV_9462(ah))
2577c6e8
SB		 2671 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2672
7ea310be
S		 2673 REG_WRITE(ah, AR_RX_FILTER, bits);
2674
f1dc5600
S		 2675 phybits = 0;
2676 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2677 phybits |= AR_PHY_ERR_RADAR;
2678 if (bits & ATH9K_RX_FILTER_PHYERR)
2679 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2680 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2681
f1dc5600 2682 if (phybits)
ca7a4deb 2683 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2684 else
ca7a4deb 2685 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2686
2687 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2688}
7322fd19 2689EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2690
cbe61d8a 2691bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2692{
63a75b91
SB		 2693 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2694 return false;
2695
2696 ath9k_hw_init_pll(ah, NULL);
2697 return true;
f1dc5600 2698}
7322fd19 2699EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2700
cbe61d8a 2701bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2702{
9ecdef4b 2703 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2704 return false;
f078f209 2705
63a75b91
SB		 2706 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2707 return false;
2708
2709 ath9k_hw_init_pll(ah, NULL);
2710 return true;
f078f209 2711}
7322fd19 2712EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2713
ca2c68cc
FF		 2714static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2715{
2716 enum eeprom_param gain_param;
2717
2718 if (IS_CHAN_2GHZ(chan))
2719 gain_param = EEP_ANTENNA_GAIN_2G;
2720 else
2721 gain_param = EEP_ANTENNA_GAIN_5G;
2722
2723 return ah->eep_ops->get_eeprom(ah, gain_param);
2724}
2725
2726void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
2727{
2728 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2729 struct ieee80211_channel *channel;
2730 int chan_pwr, new_pwr, max_gain;
2731 int ant_gain, ant_reduction = 0;
2732
2733 if (!chan)
2734 return;
2735
2736 channel = chan->chan;
2737 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2738 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2739 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2740
2741 ant_gain = get_antenna_gain(ah, chan);
2742 if (ant_gain > max_gain)
2743 ant_reduction = ant_gain - max_gain;
2744
2745 ah->eep_ops->set_txpower(ah, chan,
2746 ath9k_regd_get_ctl(reg, chan),
2747 ant_reduction, new_pwr, false);
2748}
2749
de40f316 2750void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2751{
ca2c68cc 2752 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2753 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2754 struct ieee80211_channel *channel = chan->chan;
9c204b46 2755
48ef5c42 2756 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2757 if (test)
ca2c68cc 2758 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2759
ca2c68cc 2760 ath9k_hw_apply_txpower(ah, chan);
6f255425 2761
ca2c68cc
FF		 2762 if (test)
2763 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2764}
7322fd19 2765EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2766
cbe61d8a 2767void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2768{
2660b81a 2769 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2770}
7322fd19 2771EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2772
cbe61d8a 2773void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2774{
f1dc5600
S		 2775 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2776 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2777}
7322fd19 2778EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2779
f2b2143e 2780void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2781{
1510718d
LR		 2782 struct ath_common *common = ath9k_hw_common(ah);
2783
2784 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2785 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2786 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2787}
7322fd19 2788EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2789
1c0fc65e
BP		 2790#define ATH9K_MAX_TSF_READ 10
2791
cbe61d8a 2792u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2793{
1c0fc65e
BP		 2794 u32 tsf_lower, tsf_upper1, tsf_upper2;
2795 int i;
2796
2797 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2798 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2799 tsf_lower = REG_READ(ah, AR_TSF_L32);
2800 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2801 if (tsf_upper2 == tsf_upper1)
2802 break;
2803 tsf_upper1 = tsf_upper2;
2804 }
f078f209 2805
1c0fc65e 2806 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2807
1c0fc65e 2808 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2809}
7322fd19 2810EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2811
cbe61d8a 2812void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2813{
27abe060 2814 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2815 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2816}
7322fd19 2817EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2818
cbe61d8a 2819void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2820{
f9b604f6
GJ		 2821 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2822 AH_TSF_WRITE_TIMEOUT))
d2182b69 2823 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2824 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2825
f1dc5600
S		 2826 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2827}
7322fd19 2828EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2829
54e4cec6 2830void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2831{
f1dc5600 2832 if (setting)
2660b81a 2833 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2834 else
2660b81a 2835 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2836}
7322fd19 2837EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2838
25c56eec 2839void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2840{
25c56eec 2841 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2842 u32 macmode;
2843
25c56eec 2844 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2845 macmode = AR_2040_JOINED_RX_CLEAR;
2846 else
2847 macmode = 0;
f078f209 2848
f1dc5600 2849 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2850}
ff155a45
VT		 2851
2852/* HW Generic timers configuration */
2853
2854static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2855{
2856 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2857 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2858 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2859 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2860 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2861 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2862 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2863 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2864 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2865 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2866 AR_NDP2_TIMER_MODE, 0x0002},
2867 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2868 AR_NDP2_TIMER_MODE, 0x0004},
2869 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2870 AR_NDP2_TIMER_MODE, 0x0008},
2871 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2872 AR_NDP2_TIMER_MODE, 0x0010},
2873 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2874 AR_NDP2_TIMER_MODE, 0x0020},
2875 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2876 AR_NDP2_TIMER_MODE, 0x0040},
2877 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2878 AR_NDP2_TIMER_MODE, 0x0080}
2879};
2880
2881/* HW generic timer primitives */
2882
2883/* compute and clear index of rightmost 1 */
2884static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2885{
2886 u32 b;
2887
2888 b = *mask;
2889 b &= (0-b);
2890 *mask &= ~b;
2891 b *= debruijn32;
2892 b >>= 27;
2893
2894 return timer_table->gen_timer_index[b];
2895}
2896
dd347f2f 2897u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2898{
2899 return REG_READ(ah, AR_TSF_L32);
2900}
dd347f2f 2901EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2902
2903struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2904 void (*trigger)(void *),
2905 void (*overflow)(void *),
2906 void *arg,
2907 u8 timer_index)
2908{
2909 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2910 struct ath_gen_timer *timer;
2911
2912 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2913
2914 if (timer == NULL) {
3800276a
JP		 2915 ath_err(ath9k_hw_common(ah),
2916 "Failed to allocate memory for hw timer[%d]\n",
2917 timer_index);
ff155a45
VT		 2918 return NULL;
2919 }
2920
2921 /* allocate a hardware generic timer slot */
2922 timer_table->timers[timer_index] = timer;
2923 timer->index = timer_index;
2924 timer->trigger = trigger;
2925 timer->overflow = overflow;
2926 timer->arg = arg;
2927
2928 return timer;
2929}
7322fd19 2930EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2931
cd9bf689
LR		 2932void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2933 struct ath_gen_timer *timer,
788f6875 2934 u32 trig_timeout,
cd9bf689 2935 u32 timer_period)
ff155a45
VT		 2936{
2937 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
788f6875 2938 u32 tsf, timer_next;
ff155a45
VT		 2939
2940 BUG_ON(!timer_period);
2941
2942 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2943
2944 tsf = ath9k_hw_gettsf32(ah);
2945
788f6875
VT		 2946 timer_next = tsf + trig_timeout;
2947
d2182b69 2948 ath_dbg(ath9k_hw_common(ah), HWTIMER,
226afe68
JP		 2949 "current tsf %x period %x timer_next %x\n",
2950 tsf, timer_period, timer_next);
ff155a45 2951
ff155a45
VT		 2952 /*
2953 * Program generic timer registers
2954 */
2955 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2956 timer_next);
2957 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2958 timer_period);
2959 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2960 gen_tmr_configuration[timer->index].mode_mask);
2961
423e38e8 2962 if (AR_SREV_9462(ah)) {
2577c6e8 2963 /*
423e38e8 2964 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 2965 * to use. But we still follow the old rule, 0 - 7 use tsf and
2966 * 8 - 15 use tsf2.
2967 */
2968 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2969 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2970 (1 << timer->index));
2971 else
2972 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2973 (1 << timer->index));
2974 }
2975
ff155a45
VT		 2976 /* Enable both trigger and thresh interrupt masks */
2977 REG_SET_BIT(ah, AR_IMR_S5,
2978 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2979 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2980}
7322fd19 2981EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2982
cd9bf689 2983void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2984{
2985 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2986
2987 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2988 (timer->index >= ATH_MAX_GEN_TIMER)) {
2989 return;
2990 }
2991
2992 /* Clear generic timer enable bits. */
2993 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2994 gen_tmr_configuration[timer->index].mode_mask);
2995
2996 /* Disable both trigger and thresh interrupt masks */
2997 REG_CLR_BIT(ah, AR_IMR_S5,
2998 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2999 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3000
3001 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3002}
7322fd19 3003EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3004
3005void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3006{
3007 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3008
3009 /* free the hardware generic timer slot */
3010 timer_table->timers[timer->index] = NULL;
3011 kfree(timer);
3012}
7322fd19 3013EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3014
3015/*
3016 * Generic Timer Interrupts handling
3017 */
3018void ath_gen_timer_isr(struct ath_hw *ah)
3019{
3020 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3021 struct ath_gen_timer *timer;
c46917bb 3022 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3023 u32 trigger_mask, thresh_mask, index;
3024
3025 /* get hardware generic timer interrupt status */
3026 trigger_mask = ah->intr_gen_timer_trigger;
3027 thresh_mask = ah->intr_gen_timer_thresh;
3028 trigger_mask &= timer_table->timer_mask.val;
3029 thresh_mask &= timer_table->timer_mask.val;
3030
3031 trigger_mask &= ~thresh_mask;
3032
3033 while (thresh_mask) {
3034 index = rightmost_index(timer_table, &thresh_mask);
3035 timer = timer_table->timers[index];
3036 BUG_ON(!timer);
d2182b69
JP		 3037 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3038 index);
ff155a45
VT		 3039 timer->overflow(timer->arg);
3040 }
3041
3042 while (trigger_mask) {
3043 index = rightmost_index(timer_table, &trigger_mask);
3044 timer = timer_table->timers[index];
3045 BUG_ON(!timer);
d2182b69 3046 ath_dbg(common, HWTIMER,
226afe68 3047 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3048 timer->trigger(timer->arg);
3049 }
3050}
7322fd19 3051EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3052
05020d23
S		 3053/********/
3054/* HTC */
3055/********/
3056
3057void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3058{
3059 ah->htc_reset_init = true;
3060}
3061EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3062
2da4f01a
LR		 3063static struct {
3064 u32 version;
3065 const char * name;
3066} ath_mac_bb_names[] = {
3067 /* Devices with external radios */
3068 { AR_SREV_VERSION_5416_PCI, "5416" },
3069 { AR_SREV_VERSION_5416_PCIE, "5418" },
3070 { AR_SREV_VERSION_9100, "9100" },
3071 { AR_SREV_VERSION_9160, "9160" },
3072 /* Single-chip solutions */
3073 { AR_SREV_VERSION_9280, "9280" },
3074 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3075 { AR_SREV_VERSION_9287, "9287" },
3076 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3077 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3078 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3079 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3080 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3081 { AR_SREV_VERSION_9462, "9462" },
2da4f01a
LR		 3082};
3083
3084/* For devices with external radios */
3085static struct {
3086 u16 version;
3087 const char * name;
3088} ath_rf_names[] = {
3089 { 0, "5133" },
3090 { AR_RAD5133_SREV_MAJOR, "5133" },
3091 { AR_RAD5122_SREV_MAJOR, "5122" },
3092 { AR_RAD2133_SREV_MAJOR, "2133" },
3093 { AR_RAD2122_SREV_MAJOR, "2122" }
3094};
3095
3096/*
3097 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3098 */
f934c4d9 3099static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3100{
3101 int i;
3102
3103 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3104 if (ath_mac_bb_names[i].version == mac_bb_version) {
3105 return ath_mac_bb_names[i].name;
3106 }
3107 }
3108
3109 return "????";
3110}
2da4f01a
LR		 3111
3112/*
3113 * Return the RF name. "????" is returned if the RF is unknown.
3114 * Used for devices with external radios.
3115 */
f934c4d9 3116static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3117{
3118 int i;
3119
3120 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3121 if (ath_rf_names[i].version == rf_version) {
3122 return ath_rf_names[i].name;
3123 }
3124 }
3125
3126 return "????";
3127}
f934c4d9
LR		 3128
3129void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3130{
3131 int used;
3132
3133 /* chipsets >= AR9280 are single-chip */
7a37081e 3134 if (AR_SREV_9280_20_OR_LATER(ah)) {
f934c4d9
LR		 3135 used = snprintf(hw_name, len,
3136 "Atheros AR%s Rev:%x",
3137 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3138 ah->hw_version.macRev);
3139 }
3140 else {
3141 used = snprintf(hw_name, len,
3142 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3143 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3144 ah->hw_version.macRev,
3145 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3146 AR_RADIO_SREV_MAJOR)),
3147 ah->hw_version.phyRev);
3148 }
3149
3150 hw_name[used] = '\0';
3151}
3152EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
This page took 1.192512 seconds and 5 git commands to generate.