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ath9k_hw: enable PCIe low power mode for AR9003
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
af03abec 20#include "hw.h"
d70357d5 21#include "hw-ops.h"
cfe8cba9 22#include "rc.h"
b622a720 23#include "ar9003_mac.h"
f078f209 24
4febf7b8
LR		 25#define ATH9K_CLOCK_RATE_CCK 22
26#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
e5553724 28#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
f078f209 29
cbe61d8a 30static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 31
7322fd19
LR		 32MODULE_AUTHOR("Atheros Communications");
33MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
34MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
35MODULE_LICENSE("Dual BSD/GPL");
36
37static int __init ath9k_init(void)
38{
39 return 0;
40}
41module_init(ath9k_init);
42
43static void __exit ath9k_exit(void)
44{
45 return;
46}
47module_exit(ath9k_exit);
48
d70357d5
LR		 49/* Private hardware callbacks */
50
51static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
52{
53 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
54}
55
56static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
57{
58 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
59}
60
61static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
62{
63 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
64
65 return priv_ops->macversion_supported(ah->hw_version.macVersion);
66}
67
64773964
LR		 68static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
69 struct ath9k_channel *chan)
70{
71 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
72}
73
991312d8
LR		 74static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
75{
76 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
77 return;
78
79 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
80}
81
f1dc5600
S		 82/********************/
83/* Helper Functions */
84/********************/
f078f209 85
cbe61d8a 86static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 87{
b002a4a9 88 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 89
2660b81a 90 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 91 return usecs *ATH9K_CLOCK_RATE_CCK;
92 if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
e5553724
VT		 94
95 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
96 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
97 else
98 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 99}
100
cbe61d8a 101static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 102{
b002a4a9 103 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 104
4febf7b8 105 if (conf_is_ht40(conf))
f1dc5600
S		 106 return ath9k_hw_mac_clks(ah, usecs) * 2;
107 else
108 return ath9k_hw_mac_clks(ah, usecs);
109}
f078f209 110
0caa7b14 111bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 112{
113 int i;
114
0caa7b14
S		 115 BUG_ON(timeout < AH_TIME_QUANTUM);
116
117 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 118 if ((REG_READ(ah, reg) & mask) == val)
119 return true;
120
121 udelay(AH_TIME_QUANTUM);
122 }
04bd4638 123
c46917bb
LR		 124 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
125 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
126 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 127
f1dc5600 128 return false;
f078f209 129}
7322fd19 130EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 131
132u32 ath9k_hw_reverse_bits(u32 val, u32 n)
133{
134 u32 retval;
135 int i;
136
137 for (i = 0, retval = 0; i < n; i++) {
138 retval = (retval << 1) | (val & 1);
139 val >>= 1;
140 }
141 return retval;
142}
143
cbe61d8a 144bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 145 u16 flags, u16 *low,
146 u16 *high)
f078f209 147{
2660b81a 148 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 149
f1dc5600
S		 150 if (flags & CHANNEL_5GHZ) {
151 *low = pCap->low_5ghz_chan;
152 *high = pCap->high_5ghz_chan;
153 return true;
f078f209 154 }
f1dc5600
S		 155 if ((flags & CHANNEL_2GHZ)) {
156 *low = pCap->low_2ghz_chan;
157 *high = pCap->high_2ghz_chan;
158 return true;
159 }
160 return false;
f078f209
LR		 161}
162
cbe61d8a 163u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 164 u8 phy, int kbps,
f1dc5600
S		 165 u32 frameLen, u16 rateix,
166 bool shortPreamble)
f078f209 167{
f1dc5600 168 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 169
f1dc5600
S		 170 if (kbps == 0)
171 return 0;
f078f209 172
545750d3 173 switch (phy) {
46d14a58 174 case WLAN_RC_PHY_CCK:
f1dc5600 175 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 176 if (shortPreamble)
f1dc5600
S		 177 phyTime >>= 1;
178 numBits = frameLen << 3;
179 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
180 break;
46d14a58 181 case WLAN_RC_PHY_OFDM:
2660b81a 182 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 183 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
184 numBits = OFDM_PLCP_BITS + (frameLen << 3);
185 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
186 txTime = OFDM_SIFS_TIME_QUARTER
187 + OFDM_PREAMBLE_TIME_QUARTER
188 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 189 } else if (ah->curchan &&
190 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 191 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
192 numBits = OFDM_PLCP_BITS + (frameLen << 3);
193 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
194 txTime = OFDM_SIFS_TIME_HALF +
195 OFDM_PREAMBLE_TIME_HALF
196 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
197 } else {
198 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
199 numBits = OFDM_PLCP_BITS + (frameLen << 3);
200 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
201 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
202 + (numSymbols * OFDM_SYMBOL_TIME);
203 }
204 break;
205 default:
c46917bb 206 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 207 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 208 txTime = 0;
209 break;
210 }
f078f209 211
f1dc5600
S		 212 return txTime;
213}
7322fd19 214EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 215
cbe61d8a 216void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 217 struct ath9k_channel *chan,
218 struct chan_centers *centers)
f078f209 219{
f1dc5600 220 int8_t extoff;
f078f209 221
f1dc5600
S		 222 if (!IS_CHAN_HT40(chan)) {
223 centers->ctl_center = centers->ext_center =
224 centers->synth_center = chan->channel;
225 return;
f078f209 226 }
f078f209 227
f1dc5600
S		 228 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
229 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
230 centers->synth_center =
231 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
232 extoff = 1;
233 } else {
234 centers->synth_center =
235 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
236 extoff = -1;
237 }
f078f209 238
f1dc5600
S		 239 centers->ctl_center =
240 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 241 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 242 centers->ext_center =
6420014c 243 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 244}
245
f1dc5600
S		 246/******************/
247/* Chip Revisions */
248/******************/
249
cbe61d8a 250static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 251{
f1dc5600 252 u32 val;
f078f209 253
f1dc5600 254 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 255
f1dc5600
S		 256 if (val == 0xFF) {
257 val = REG_READ(ah, AR_SREV);
d535a42a
S		 258 ah->hw_version.macVersion =
259 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
260 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 261 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 262 } else {
263 if (!AR_SREV_9100(ah))
d535a42a 264 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 265
d535a42a 266 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 267
d535a42a 268 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 269 ah->is_pciexpress = true;
f1dc5600 270 }
f078f209
LR		 271}
272
f1dc5600
S		 273/************************************/
274/* HW Attach, Detach, Init Routines */
275/************************************/
276
cbe61d8a 277static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 278{
feed029c 279 if (AR_SREV_9100(ah))
f1dc5600 280 return;
f078f209 281
7d0d0df0
S		 282 ENABLE_REGWRITE_BUFFER(ah);
283
f1dc5600
S		 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 293
f1dc5600 294 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
7d0d0df0
S		 295
296 REGWRITE_BUFFER_FLUSH(ah);
297 DISABLE_REGWRITE_BUFFER(ah);
f078f209
LR		 298}
299
1f3f0618 300/* This should work for all families including legacy */
cbe61d8a 301static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 302{
c46917bb 303 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 304 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600
S		 305 u32 regHold[2];
306 u32 patternData[4] = { 0x55555555,
307 0xaaaaaaaa,
308 0x66666666,
309 0x99999999 };
1f3f0618 310 int i, j, loop_max;
f078f209 311
1f3f0618
SB		 312 if (!AR_SREV_9300_20_OR_LATER(ah)) {
313 loop_max = 2;
314 regAddr[1] = AR_PHY_BASE + (8 << 2);
315 } else
316 loop_max = 1;
317
318 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 319 u32 addr = regAddr[i];
320 u32 wrData, rdData;
f078f209 321
f1dc5600
S		 322 regHold[i] = REG_READ(ah, addr);
323 for (j = 0; j < 0x100; j++) {
324 wrData = (j << 16) | j;
325 REG_WRITE(ah, addr, wrData);
326 rdData = REG_READ(ah, addr);
327 if (rdData != wrData) {
c46917bb
LR		 328 ath_print(common, ATH_DBG_FATAL,
329 "address test failed "
330 "addr: 0x%08x - wr:0x%08x != "
331 "rd:0x%08x\n",
332 addr, wrData, rdData);
f1dc5600
S		 333 return false;
334 }
335 }
336 for (j = 0; j < 4; j++) {
337 wrData = patternData[j];
338 REG_WRITE(ah, addr, wrData);
339 rdData = REG_READ(ah, addr);
340 if (wrData != rdData) {
c46917bb
LR		 341 ath_print(common, ATH_DBG_FATAL,
342 "address test failed "
343 "addr: 0x%08x - wr:0x%08x != "
344 "rd:0x%08x\n",
345 addr, wrData, rdData);
f1dc5600
S		 346 return false;
347 }
f078f209 348 }
f1dc5600 349 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 350 }
f1dc5600 351 udelay(100);
cbe61d8a 352
f078f209
LR		 353 return true;
354}
355
b8b0f377 356static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 357{
358 int i;
f078f209 359
2660b81a
S		 360 ah->config.dma_beacon_response_time = 2;
361 ah->config.sw_beacon_response_time = 10;
362 ah->config.additional_swba_backoff = 0;
363 ah->config.ack_6mb = 0x0;
364 ah->config.cwm_ignore_extcca = 0;
365 ah->config.pcie_powersave_enable = 0;
2660b81a 366 ah->config.pcie_clock_req = 0;
2660b81a
S		 367 ah->config.pcie_waen = 0;
368 ah->config.analog_shiftreg = 1;
2660b81a
S		 369 ah->config.ofdm_trig_low = 200;
370 ah->config.ofdm_trig_high = 500;
371 ah->config.cck_trig_high = 200;
372 ah->config.cck_trig_low = 100;
31a0bd3c
LR		 373
374 /*
375 * For now ANI is disabled for AR9003, it is still
376 * being tested.
377 */
378 if (!AR_SREV_9300_20_OR_LATER(ah))
379 ah->config.enable_ani = 1;
f078f209 380
f1dc5600 381 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 382 ah->config.spurchans[i][0] = AR_NO_SPUR;
383 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 384 }
385
5ffaf8a3
LR		 386 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
387 ah->config.ht_enable = 1;
388 else
389 ah->config.ht_enable = 0;
390
0ce024cb 391 ah->config.rx_intr_mitigation = true;
6158425b 392
b360a884
LR		 393 /*
394 * Tx IQ Calibration (ah->config.tx_iq_calibration) is only
395 * used by AR9003, but it is showing reliability issues.
396 * It will take a while to fix so this is currently disabled.
397 */
398
6158425b
LR		 399 /*
400 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
401 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
402 * This means we use it for all AR5416 devices, and the few
403 * minor PCI AR9280 devices out there.
404 *
405 * Serialization is required because these devices do not handle
406 * well the case of two concurrent reads/writes due to the latency
407 * involved. During one read/write another read/write can be issued
408 * on another CPU while the previous read/write may still be working
409 * on our hardware, if we hit this case the hardware poops in a loop.
410 * We prevent this by serializing reads and writes.
411 *
412 * This issue is not present on PCI-Express devices or pre-AR5416
413 * devices (legacy, 802.11abg).
414 */
415 if (num_possible_cpus() > 1)
2d6a5e95 416 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 417}
418
50aca25b 419static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 420{
608b88cb
LR		 421 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
422
423 regulatory->country_code = CTRY_DEFAULT;
424 regulatory->power_limit = MAX_RATE_POWER;
425 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
426
d535a42a 427 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 428 ah->hw_version.subvendorid = 0;
f078f209
LR		 429
430 ah->ah_flags = 0;
f078f209
LR		 431 if (!AR_SREV_9100(ah))
432 ah->ah_flags = AH_USE_EEPROM;
433
2660b81a 434 ah->atim_window = 0;
2660b81a
S		 435 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
436 ah->beacon_interval = 100;
437 ah->enable_32kHz_clock = DONT_USE_32KHZ;
438 ah->slottime = (u32) -1;
2660b81a 439 ah->globaltxtimeout = (u32) -1;
cbdec975 440 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 441}
442
cbe61d8a 443static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 444{
1510718d 445 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 446 u32 sum;
447 int i;
448 u16 eeval;
49101676 449 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 450
451 sum = 0;
452 for (i = 0; i < 3; i++) {
49101676 453 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 454 sum += eeval;
1510718d
LR		 455 common->macaddr[2 * i] = eeval >> 8;
456 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 457 }
d8baa939 458 if (sum == 0 || sum == 0xffff * 3)
f078f209 459 return -EADDRNOTAVAIL;
f078f209
LR		 460
461 return 0;
462}
463
f637cfd6 464static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 465{
f1dc5600 466 int ecode;
f078f209 467
527d485f
S		 468 if (!AR_SREV_9271(ah)) {
469 if (!ath9k_hw_chip_test(ah))
470 return -ENODEV;
471 }
f078f209 472
ebd5a14a
LR		 473 if (!AR_SREV_9300_20_OR_LATER(ah)) {
474 ecode = ar9002_hw_rf_claim(ah);
475 if (ecode != 0)
476 return ecode;
477 }
f078f209 478
f637cfd6 479 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 480 if (ecode != 0)
481 return ecode;
7d01b221 482
c46917bb
LR		 483 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
484 "Eeprom VER: %d, REV: %d\n",
485 ah->eep_ops->get_eeprom_ver(ah),
486 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 487
8fe65368
LR		 488 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
489 if (ecode) {
490 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
491 "Failed allocating banks for "
492 "external radio\n");
493 return ecode;
574d6b12 494 }
f078f209 495
f1dc5600
S		 496 if (!AR_SREV_9100(ah)) {
497 ath9k_hw_ani_setup(ah);
f637cfd6 498 ath9k_hw_ani_init(ah);
f078f209
LR		 499 }
500
f078f209
LR		 501 return 0;
502}
503
8525f280
LR		 504static void ath9k_hw_attach_ops(struct ath_hw *ah)
505{
506 if (AR_SREV_9300_20_OR_LATER(ah))
507 ar9003_hw_attach_ops(ah);
508 else
509 ar9002_hw_attach_ops(ah);
510}
511
d70357d5
LR		 512/* Called for all hardware families */
513static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 514{
c46917bb 515 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 516 int r = 0;
aa4058ae 517
bab1f62e
LR		 518 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
519 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
aa4058ae
LR		 520
521 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 522 ath_print(common, ATH_DBG_FATAL,
523 "Couldn't reset chip\n");
95fafca2 524 return -EIO;
aa4058ae
LR		 525 }
526
bab1f62e
LR		 527 ath9k_hw_init_defaults(ah);
528 ath9k_hw_init_config(ah);
529
8525f280 530 ath9k_hw_attach_ops(ah);
d70357d5 531
9ecdef4b 532 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 533 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 534 return -EIO;
aa4058ae
LR		 535 }
536
537 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
538 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
539 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
540 ah->config.serialize_regmode =
541 SER_REG_MODE_ON;
542 } else {
543 ah->config.serialize_regmode =
544 SER_REG_MODE_OFF;
545 }
546 }
547
c46917bb 548 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 549 ah->config.serialize_regmode);
550
f4709fdf
LR		 551 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
552 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
553 else
554 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
555
d70357d5 556 if (!ath9k_hw_macversion_supported(ah)) {
c46917bb
LR		 557 ath_print(common, ATH_DBG_FATAL,
558 "Mac Chip Rev 0x%02x.%x is not supported by "
559 "this driver\n", ah->hw_version.macVersion,
560 ah->hw_version.macRev);
95fafca2 561 return -EOPNOTSUPP;
aa4058ae
LR		 562 }
563
0df13da4 564 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
d7e7d229
LR		 565 ah->is_pciexpress = false;
566
aa4058ae 567 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 568 ath9k_hw_init_cal_settings(ah);
569
570 ah->ani_function = ATH9K_ANI_ALL;
31a0bd3c 571 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae
LR		 572 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
573
574 ath9k_hw_init_mode_regs(ah);
575
5efa3a6b
LR		 576 /*
577 * Configire PCIE after Ini init. SERDES values now come from ini file
578 * This enables PCIe low power mode.
579 */
580 if (AR_SREV_9300_20_OR_LATER(ah)) {
581 u32 regval;
582 unsigned int i;
583
584 /* Set Bits 16 and 17 in the AR_WA register. */
585 regval = REG_READ(ah, AR_WA);
586 regval |= 0x00030000;
587 REG_WRITE(ah, AR_WA, regval);
588
589 for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
590 REG_WRITE(ah,
591 INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
592 INI_RA(&ah->iniPcieSerdesLowPower, i, 1));
593 }
594 }
595
aa4058ae 596 if (ah->is_pciexpress)
93b1b37f 597 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 598 else
599 ath9k_hw_disablepcie(ah);
600
d8f492b7
LR		 601 if (!AR_SREV_9300_20_OR_LATER(ah))
602 ar9002_hw_cck_chan14_spread(ah);
193cd458 603
f637cfd6 604 r = ath9k_hw_post_init(ah);
aa4058ae 605 if (r)
95fafca2 606 return r;
aa4058ae
LR		 607
608 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 609 r = ath9k_hw_fill_cap_info(ah);
610 if (r)
611 return r;
612
4f3acf81
LR		 613 r = ath9k_hw_init_macaddr(ah);
614 if (r) {
c46917bb
LR		 615 ath_print(common, ATH_DBG_FATAL,
616 "Failed to initialize MAC address\n");
95fafca2 617 return r;
f078f209
LR		 618 }
619
d7e7d229 620 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 621 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 622 else
2660b81a 623 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 624
641d9921
FF		 625 if (AR_SREV_9300_20_OR_LATER(ah))
626 ar9003_hw_set_nf_limits(ah);
627
f1dc5600 628 ath9k_init_nfcal_hist_buffer(ah);
f078f209 629
211f5859
LR		 630 common->state = ATH_HW_INITIALIZED;
631
4f3acf81 632 return 0;
f078f209
LR		 633}
634
d70357d5
LR		 635int ath9k_hw_init(struct ath_hw *ah)
636{
637 int ret;
638 struct ath_common *common = ath9k_hw_common(ah);
639
640 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
641 switch (ah->hw_version.devid) {
642 case AR5416_DEVID_PCI:
643 case AR5416_DEVID_PCIE:
644 case AR5416_AR9100_DEVID:
645 case AR9160_DEVID_PCI:
646 case AR9280_DEVID_PCI:
647 case AR9280_DEVID_PCIE:
648 case AR9285_DEVID_PCIE:
db3cc53a
SB		 649 case AR9287_DEVID_PCI:
650 case AR9287_DEVID_PCIE:
d70357d5 651 case AR2427_DEVID_PCIE:
db3cc53a 652 case AR9300_DEVID_PCIE:
d70357d5
LR		 653 break;
654 default:
655 if (common->bus_ops->ath_bus_type == ATH_USB)
656 break;
657 ath_print(common, ATH_DBG_FATAL,
658 "Hardware device ID 0x%04x not supported\n",
659 ah->hw_version.devid);
660 return -EOPNOTSUPP;
661 }
662
663 ret = __ath9k_hw_init(ah);
664 if (ret) {
665 ath_print(common, ATH_DBG_FATAL,
666 "Unable to initialize hardware; "
667 "initialization status: %d\n", ret);
668 return ret;
669 }
670
671 return 0;
672}
673EXPORT_SYMBOL(ath9k_hw_init);
674
cbe61d8a 675static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 676{
7d0d0df0
S		 677 ENABLE_REGWRITE_BUFFER(ah);
678
f1dc5600
S		 679 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
680 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 681
f1dc5600
S		 682 REG_WRITE(ah, AR_QOS_NO_ACK,
683 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
684 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
685 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
686
687 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
688 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
689 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
690 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
691 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 692
693 REGWRITE_BUFFER_FLUSH(ah);
694 DISABLE_REGWRITE_BUFFER(ah);
f078f209
LR		 695}
696
cbe61d8a 697static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 698 struct ath9k_channel *chan)
f078f209 699{
64773964 700 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 701
d03a66c1 702 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 703
c75724d1
LR		 704 /* Switch the core clock for ar9271 to 117Mhz */
705 if (AR_SREV_9271(ah)) {
25e2ab17
S		 706 udelay(500);
707 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 708 }
709
f1dc5600
S		 710 udelay(RTC_PLL_SETTLE_DELAY);
711
712 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 713}
714
cbe61d8a 715static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 716 enum nl80211_iftype opmode)
f078f209 717{
152d530d 718 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 719 AR_IMR_TXURN |
720 AR_IMR_RXERR |
721 AR_IMR_RXORN |
722 AR_IMR_BCNMISC;
f078f209 723
66860240
VT		 724 if (AR_SREV_9300_20_OR_LATER(ah)) {
725 imr_reg |= AR_IMR_RXOK_HP;
726 if (ah->config.rx_intr_mitigation)
727 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
728 else
729 imr_reg |= AR_IMR_RXOK_LP;
f078f209 730
66860240
VT		 731 } else {
732 if (ah->config.rx_intr_mitigation)
733 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
734 else
735 imr_reg |= AR_IMR_RXOK;
736 }
737
738 if (ah->config.tx_intr_mitigation)
739 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
740 else
741 imr_reg |= AR_IMR_TXOK;
f078f209 742
d97809db 743 if (opmode == NL80211_IFTYPE_AP)
152d530d 744 imr_reg |= AR_IMR_MIB;
f078f209 745
7d0d0df0
S		 746 ENABLE_REGWRITE_BUFFER(ah);
747
152d530d 748 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 749 ah->imrs2_reg |= AR_IMR_S2_GTT;
750 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 751
f1dc5600
S		 752 if (!AR_SREV_9100(ah)) {
753 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
754 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
755 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
756 }
66860240 757
7d0d0df0
S		 758 REGWRITE_BUFFER_FLUSH(ah);
759 DISABLE_REGWRITE_BUFFER(ah);
760
66860240
VT		 761 if (AR_SREV_9300_20_OR_LATER(ah)) {
762 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
763 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
764 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
765 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
766 }
f078f209
LR		 767}
768
0005baf4 769static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 770{
0005baf4
FF		 771 u32 val = ath9k_hw_mac_to_clks(ah, us);
772 val = min(val, (u32) 0xFFFF);
773 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 774}
775
0005baf4 776static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 777{
0005baf4
FF		 778 u32 val = ath9k_hw_mac_to_clks(ah, us);
779 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
780 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
781}
782
783static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
784{
785 u32 val = ath9k_hw_mac_to_clks(ah, us);
786 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
787 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 788}
f1dc5600 789
cbe61d8a 790static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 791{
f078f209 792 if (tu > 0xFFFF) {
c46917bb
LR		 793 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
794 "bad global tx timeout %u\n", tu);
2660b81a 795 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 796 return false;
797 } else {
798 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 799 ah->globaltxtimeout = tu;
f078f209
LR		 800 return true;
801 }
802}
803
0005baf4 804void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 805{
0005baf4
FF		 806 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
807 int acktimeout;
e239d859 808 int slottime;
0005baf4
FF		 809 int sifstime;
810
c46917bb
LR		 811 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
812 ah->misc_mode);
f078f209 813
2660b81a 814 if (ah->misc_mode != 0)
f1dc5600 815 REG_WRITE(ah, AR_PCU_MISC,
2660b81a 816 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
0005baf4
FF		 817
818 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
819 sifstime = 16;
820 else
821 sifstime = 10;
822
e239d859
FF		 823 /* As defined by IEEE 802.11-2007 17.3.8.6 */
824 slottime = ah->slottime + 3 * ah->coverage_class;
825 acktimeout = slottime + sifstime;
42c4568a
FF		 826
827 /*
828 * Workaround for early ACK timeouts, add an offset to match the
829 * initval's 64us ack timeout value.
830 * This was initially only meant to work around an issue with delayed
831 * BA frames in some implementations, but it has been found to fix ACK
832 * timeout issues in other cases as well.
833 */
834 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
835 acktimeout += 64 - sifstime - ah->slottime;
836
e239d859 837 ath9k_hw_setslottime(ah, slottime);
0005baf4
FF		 838 ath9k_hw_set_ack_timeout(ah, acktimeout);
839 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 840 if (ah->globaltxtimeout != (u32) -1)
841 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 842}
0005baf4 843EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 844
285f2dda 845void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 846{
211f5859
LR		 847 struct ath_common *common = ath9k_hw_common(ah);
848
736b3a27 849 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 850 goto free_hw;
851
9ecdef4b 852 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 853
854free_hw:
8fe65368 855 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 856}
285f2dda 857EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 858
f1dc5600
S		 859/*******/
860/* INI */
861/*******/
862
8fe65368 863u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 864{
865 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
866
867 if (IS_CHAN_B(chan))
868 ctl |= CTL_11B;
869 else if (IS_CHAN_G(chan))
870 ctl |= CTL_11G;
871 else
872 ctl |= CTL_11A;
873
874 return ctl;
875}
876
f1dc5600
S		 877/****************************************/
878/* Reset and Channel Switching Routines */
879/****************************************/
880
cbe61d8a 881static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 882{
57b32227 883 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 884 u32 regval;
885
7d0d0df0
S		 886 ENABLE_REGWRITE_BUFFER(ah);
887
d7e7d229
LR		 888 /*
889 * set AHB_MODE not to do cacheline prefetches
890 */
57b32227
FF		 891 if (!AR_SREV_9300_20_OR_LATER(ah)) {
892 regval = REG_READ(ah, AR_AHB_MODE);
893 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
894 }
f1dc5600 895
d7e7d229
LR		 896 /*
897 * let mac dma reads be in 128 byte chunks
898 */
f1dc5600
S		 899 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
900 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
901
7d0d0df0
S		 902 REGWRITE_BUFFER_FLUSH(ah);
903 DISABLE_REGWRITE_BUFFER(ah);
904
d7e7d229
LR		 905 /*
906 * Restore TX Trigger Level to its pre-reset value.
907 * The initial value depends on whether aggregation is enabled, and is
908 * adjusted whenever underruns are detected.
909 */
57b32227
FF		 910 if (!AR_SREV_9300_20_OR_LATER(ah))
911 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 912
7d0d0df0
S		 913 ENABLE_REGWRITE_BUFFER(ah);
914
d7e7d229
LR		 915 /*
916 * let mac dma writes be in 128 byte chunks
917 */
f1dc5600
S		 918 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
919 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
920
d7e7d229
LR		 921 /*
922 * Setup receive FIFO threshold to hold off TX activities
923 */
f1dc5600
S		 924 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
925
57b32227
FF		 926 if (AR_SREV_9300_20_OR_LATER(ah)) {
927 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
928 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
929
930 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
931 ah->caps.rx_status_len);
932 }
933
d7e7d229
LR		 934 /*
935 * reduce the number of usable entries in PCU TXBUF to avoid
936 * wrap around issues.
937 */
f1dc5600 938 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 939 /* For AR9285 the number of Fifos are reduced to half.
940 * So set the usable tx buf size also to half to
941 * avoid data/delimiter underruns
942 */
f1dc5600
S		 943 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
944 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 945 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 946 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
947 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
948 }
744d4025 949
7d0d0df0
S		 950 REGWRITE_BUFFER_FLUSH(ah);
951 DISABLE_REGWRITE_BUFFER(ah);
952
744d4025
VT		 953 if (AR_SREV_9300_20_OR_LATER(ah))
954 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 955}
956
cbe61d8a 957static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 958{
959 u32 val;
960
961 val = REG_READ(ah, AR_STA_ID1);
962 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
963 switch (opmode) {
d97809db 964 case NL80211_IFTYPE_AP:
f1dc5600
S		 965 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
966 | AR_STA_ID1_KSRCH_MODE);
967 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 968 break;
d97809db 969 case NL80211_IFTYPE_ADHOC:
9cb5412b 970 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 971 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
972 | AR_STA_ID1_KSRCH_MODE);
973 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 974 break;
d97809db
CM		 975 case NL80211_IFTYPE_STATION:
976 case NL80211_IFTYPE_MONITOR:
f1dc5600 977 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 978 break;
f1dc5600
S		 979 }
980}
981
8fe65368
LR		 982void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
983 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 984{
985 u32 coef_exp, coef_man;
986
987 for (coef_exp = 31; coef_exp > 0; coef_exp--)
988 if ((coef_scaled >> coef_exp) & 0x1)
989 break;
990
991 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
992
993 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
994
995 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
996 *coef_exponent = coef_exp - 16;
997}
998
cbe61d8a 999static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1000{
1001 u32 rst_flags;
1002 u32 tmpReg;
1003
70768496
S		 1004 if (AR_SREV_9100(ah)) {
1005 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1006 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1007 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1008 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1009 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1010 }
1011
7d0d0df0
S		 1012 ENABLE_REGWRITE_BUFFER(ah);
1013
f1dc5600
S		 1014 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1015 AR_RTC_FORCE_WAKE_ON_INT);
1016
1017 if (AR_SREV_9100(ah)) {
1018 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1019 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1020 } else {
1021 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1022 if (tmpReg &
1023 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1024 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1025 u32 val;
f1dc5600 1026 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1027
1028 val = AR_RC_HOSTIF;
1029 if (!AR_SREV_9300_20_OR_LATER(ah))
1030 val |= AR_RC_AHB;
1031 REG_WRITE(ah, AR_RC, val);
1032
1033 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1034 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1035
1036 rst_flags = AR_RTC_RC_MAC_WARM;
1037 if (type == ATH9K_RESET_COLD)
1038 rst_flags |= AR_RTC_RC_MAC_COLD;
1039 }
1040
d03a66c1 1041 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1042
1043 REGWRITE_BUFFER_FLUSH(ah);
1044 DISABLE_REGWRITE_BUFFER(ah);
1045
f1dc5600
S		 1046 udelay(50);
1047
d03a66c1 1048 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1049 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1050 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1051 "RTC stuck in MAC reset\n");
f1dc5600
S		 1052 return false;
1053 }
1054
1055 if (!AR_SREV_9100(ah))
1056 REG_WRITE(ah, AR_RC, 0);
1057
f1dc5600
S		 1058 if (AR_SREV_9100(ah))
1059 udelay(50);
1060
1061 return true;
1062}
1063
cbe61d8a 1064static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1065{
7d0d0df0
S		 1066 ENABLE_REGWRITE_BUFFER(ah);
1067
f1dc5600
S		 1068 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1069 AR_RTC_FORCE_WAKE_ON_INT);
1070
42d5bc3f 1071 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1072 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1073
d03a66c1 1074 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1075
7d0d0df0
S		 1076 REGWRITE_BUFFER_FLUSH(ah);
1077 DISABLE_REGWRITE_BUFFER(ah);
1078
84e2169b
SB		 1079 if (!AR_SREV_9300_20_OR_LATER(ah))
1080 udelay(2);
1081
1082 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1083 REG_WRITE(ah, AR_RC, 0);
1084
d03a66c1 1085 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1086
1087 if (!ath9k_hw_wait(ah,
1088 AR_RTC_STATUS,
1089 AR_RTC_STATUS_M,
0caa7b14
S		 1090 AR_RTC_STATUS_ON,
1091 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1092 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1093 "RTC not waking up\n");
f1dc5600 1094 return false;
f078f209
LR		 1095 }
1096
f1dc5600
S		 1097 ath9k_hw_read_revisions(ah);
1098
1099 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1100}
1101
cbe61d8a 1102static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1103{
1104 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1105 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1106
1107 switch (type) {
1108 case ATH9K_RESET_POWER_ON:
1109 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1110 case ATH9K_RESET_WARM:
1111 case ATH9K_RESET_COLD:
1112 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1113 default:
1114 return false;
1115 }
f078f209
LR		 1116}
1117
cbe61d8a 1118static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1119 struct ath9k_channel *chan)
f078f209 1120{
42abfbee 1121 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1122 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1123 return false;
1124 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1125 return false;
f078f209 1126
9ecdef4b 1127 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1128 return false;
f078f209 1129
2660b81a 1130 ah->chip_fullsleep = false;
f1dc5600 1131 ath9k_hw_init_pll(ah, chan);
f1dc5600 1132 ath9k_hw_set_rfmode(ah, chan);
f078f209 1133
f1dc5600 1134 return true;
f078f209
LR		 1135}
1136
cbe61d8a 1137static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1138 struct ath9k_channel *chan)
f078f209 1139{
608b88cb 1140 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1141 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1142 struct ieee80211_channel *channel = chan->chan;
8fe65368 1143 u32 qnum;
0a3b7bac 1144 int r;
f078f209
LR		 1145
1146 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1147 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1148 ath_print(common, ATH_DBG_QUEUE,
1149 "Transmit frames pending on "
1150 "queue %d\n", qnum);
f078f209
LR		 1151 return false;
1152 }
1153 }
1154
8fe65368 1155 if (!ath9k_hw_rfbus_req(ah)) {
c46917bb
LR		 1156 ath_print(common, ATH_DBG_FATAL,
1157 "Could not kill baseband RX\n");
f078f209
LR		 1158 return false;
1159 }
1160
8fe65368 1161 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1162
8fe65368 1163 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1164 if (r) {
1165 ath_print(common, ATH_DBG_FATAL,
1166 "Failed to set channel\n");
1167 return false;
f078f209
LR		 1168 }
1169
8fbff4b8 1170 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1171 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1172 channel->max_antenna_gain * 2,
1173 channel->max_power * 2,
1174 min((u32) MAX_RATE_POWER,
608b88cb 1175 (u32) regulatory->power_limit));
f078f209 1176
8fe65368 1177 ath9k_hw_rfbus_done(ah);
f078f209 1178
f1dc5600
S		 1179 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1180 ath9k_hw_set_delta_slope(ah, chan);
1181
8fe65368 1182 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600
S		 1183
1184 if (!chan->oneTimeCalsDone)
1185 chan->oneTimeCalsDone = true;
1186
1187 return true;
1188}
1189
c9c99e5e
FF		 1190bool ath9k_hw_check_alive(struct ath_hw *ah)
1191{
1192 int count = 50;
1193 u32 reg;
1194
1195 if (AR_SREV_9285_10_OR_LATER(ah))
1196 return true;
1197
1198 do {
1199 reg = REG_READ(ah, AR_OBS_BUS_1);
1200
1201 if ((reg & 0x7E7FFFEF) == 0x00702400)
1202 continue;
1203
1204 switch (reg & 0x7E000B00) {
1205 case 0x1E000000:
1206 case 0x52000B00:
1207 case 0x18000B00:
1208 continue;
1209 default:
1210 return true;
1211 }
1212 } while (count-- > 0);
1213
1214 return false;
1215}
1216EXPORT_SYMBOL(ath9k_hw_check_alive);
1217
cbe61d8a 1218int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 1219 bool bChannelChange)
f078f209 1220{
1510718d 1221 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1222 u32 saveLedState;
2660b81a 1223 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1224 u32 saveDefAntenna;
1225 u32 macStaId1;
46fe782c 1226 u64 tsf = 0;
8fe65368 1227 int i, r;
f078f209 1228
43c27613
LR		 1229 ah->txchainmask = common->tx_chainmask;
1230 ah->rxchainmask = common->rx_chainmask;
f078f209 1231
9b9cc61c
VT		 1232 if (!ah->chip_fullsleep) {
1233 ath9k_hw_abortpcurecv(ah);
1234 if (!ath9k_hw_stopdmarecv(ah))
1235 ath_print(common, ATH_DBG_XMIT,
1236 "Failed to stop receive dma\n");
1237 }
1238
9ecdef4b 1239 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1240 return -EIO;
f078f209 1241
9ebef799 1242 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1243 ath9k_hw_getnf(ah, curchan);
1244
1245 if (bChannelChange &&
2660b81a
S		 1246 (ah->chip_fullsleep != true) &&
1247 (ah->curchan != NULL) &&
1248 (chan->channel != ah->curchan->channel) &&
f078f209 1249 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1250 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
6b42e8d0 1251 !AR_SREV_9280(ah)) {
f078f209 1252
25c56eec 1253 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1254 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 1255 ath9k_hw_start_nfcal(ah);
ae8d2858 1256 return 0;
f078f209
LR		 1257 }
1258 }
1259
1260 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1261 if (saveDefAntenna == 0)
1262 saveDefAntenna = 1;
1263
1264 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1265
46fe782c
S		 1266 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1267 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1268 tsf = ath9k_hw_gettsf64(ah);
1269
f078f209
LR		 1270 saveLedState = REG_READ(ah, AR_CFG_LED) &
1271 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1272 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1273
1274 ath9k_hw_mark_phy_inactive(ah);
1275
05020d23 1276 /* Only required on the first reset */
d7e7d229
LR		 1277 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1278 REG_WRITE(ah,
1279 AR9271_RESET_POWER_DOWN_CONTROL,
1280 AR9271_RADIO_RF_RST);
1281 udelay(50);
1282 }
1283
f078f209 1284 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1285 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1286 return -EINVAL;
f078f209
LR		 1287 }
1288
05020d23 1289 /* Only required on the first reset */
d7e7d229
LR		 1290 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1291 ah->htc_reset_init = false;
1292 REG_WRITE(ah,
1293 AR9271_RESET_POWER_DOWN_CONTROL,
1294 AR9271_GATE_MAC_CTL);
1295 udelay(50);
1296 }
1297
46fe782c
S		 1298 /* Restore TSF */
1299 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1300 ath9k_hw_settsf64(ah, tsf);
1301
369391db
VT		 1302 if (AR_SREV_9280_10_OR_LATER(ah))
1303 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1304
25c56eec 1305 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1306 if (r)
1307 return r;
f078f209 1308
0ced0e17
JM		 1309 /* Setup MFP options for CCMP */
1310 if (AR_SREV_9280_20_OR_LATER(ah)) {
1311 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1312 * frames when constructing CCMP AAD. */
1313 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1314 0xc7ff);
1315 ah->sw_mgmt_crypto = false;
1316 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1317 /* Disable hardware crypto for management frames */
1318 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1319 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1320 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1321 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1322 ah->sw_mgmt_crypto = true;
1323 } else
1324 ah->sw_mgmt_crypto = true;
1325
f078f209
LR		 1326 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1327 ath9k_hw_set_delta_slope(ah, chan);
1328
8fe65368 1329 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1330 ah->eep_ops->set_board_values(ah, chan);
a7765828 1331
6819d57f
S		 1332 ath9k_hw_set_operating_mode(ah, ah->opmode);
1333
7d0d0df0
S		 1334 ENABLE_REGWRITE_BUFFER(ah);
1335
1510718d
LR		 1336 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1337 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1338 | macStaId1
1339 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1340 | (ah->config.
60b67f51 1341 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1342 | ah->sta_id1_defaults);
13b81559 1343 ath_hw_setbssidmask(common);
f078f209 1344 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1345 ath9k_hw_write_associd(ah);
f078f209 1346 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1347 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1348
7d0d0df0
S		 1349 REGWRITE_BUFFER_FLUSH(ah);
1350 DISABLE_REGWRITE_BUFFER(ah);
1351
8fe65368 1352 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1353 if (r)
1354 return r;
f078f209 1355
7d0d0df0
S		 1356 ENABLE_REGWRITE_BUFFER(ah);
1357
f078f209
LR		 1358 for (i = 0; i < AR_NUM_DCU; i++)
1359 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1360
7d0d0df0
S		 1361 REGWRITE_BUFFER_FLUSH(ah);
1362 DISABLE_REGWRITE_BUFFER(ah);
1363
2660b81a
S		 1364 ah->intr_txqs = 0;
1365 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 1366 ath9k_hw_resettxqueue(ah, i);
1367
2660b81a 1368 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 1369 ath9k_hw_init_qos(ah);
1370
2660b81a 1371 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 1372 ath9k_enable_rfkill(ah);
3b319aae 1373
0005baf4 1374 ath9k_hw_init_global_settings(ah);
f078f209 1375
6c94fdc9 1376 if (!AR_SREV_9300_20_OR_LATER(ah)) {
78ec2677 1377 ar9002_hw_enable_async_fifo(ah);
6c94fdc9 1378 ar9002_hw_enable_wep_aggregation(ah);
ac88b6ec
VN		 1379 }
1380
f078f209
LR		 1381 REG_WRITE(ah, AR_STA_ID1,
1382 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1383
1384 ath9k_hw_set_dma(ah);
1385
1386 REG_WRITE(ah, AR_OBS, 8);
1387
0ce024cb 1388 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1389 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1390 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1391 }
1392
7f62a136
VT		 1393 if (ah->config.tx_intr_mitigation) {
1394 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1395 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1396 }
1397
f078f209
LR		 1398 ath9k_hw_init_bb(ah, chan);
1399
ae8d2858 1400 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1401 return -EIO;
f078f209 1402
7d0d0df0
S		 1403 ENABLE_REGWRITE_BUFFER(ah);
1404
8fe65368 1405 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1406 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1407
7d0d0df0
S		 1408 REGWRITE_BUFFER_FLUSH(ah);
1409 DISABLE_REGWRITE_BUFFER(ah);
1410
d7e7d229
LR		 1411 /*
1412 * For big endian systems turn on swapping for descriptors
1413 */
f078f209
LR		 1414 if (AR_SREV_9100(ah)) {
1415 u32 mask;
1416 mask = REG_READ(ah, AR_CFG);
1417 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 1418 ath_print(common, ATH_DBG_RESET,
04bd4638 1419 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1420 } else {
1421 mask =
1422 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1423 REG_WRITE(ah, AR_CFG, mask);
c46917bb 1424 ath_print(common, ATH_DBG_RESET,
04bd4638 1425 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1426 }
1427 } else {
d7e7d229
LR		 1428 /* Configure AR9271 target WLAN */
1429 if (AR_SREV_9271(ah))
1430 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 1431#ifdef __BIG_ENDIAN
d7e7d229
LR		 1432 else
1433 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1434#endif
1435 }
1436
766ec4a9 1437 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1438 ath9k_hw_btcoex_enable(ah);
1439
d8903a53
VT		 1440 if (AR_SREV_9300_20_OR_LATER(ah)) {
1441 ath9k_hw_loadnf(ah, curchan);
1442 ath9k_hw_start_nfcal(ah);
1443 }
1444
ae8d2858 1445 return 0;
f078f209 1446}
7322fd19 1447EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1448
f1dc5600
S		 1449/************************/
1450/* Key Cache Management */
1451/************************/
f078f209 1452
cbe61d8a 1453bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 1454{
f1dc5600 1455 u32 keyType;
f078f209 1456
2660b81a 1457 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1458 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1459 "keychache entry %u out of range\n", entry);
f078f209
LR		 1460 return false;
1461 }
1462
f1dc5600 1463 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 1464
f1dc5600
S		 1465 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1466 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1467 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1468 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1469 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1470 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1471 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1472 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 1473
f1dc5600
S		 1474 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1475 u16 micentry = entry + 64;
f078f209 1476
f1dc5600
S		 1477 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1478 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1479 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1480 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 1481
f078f209
LR		 1482 }
1483
f078f209
LR		 1484 return true;
1485}
7322fd19 1486EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 1487
cbe61d8a 1488bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 1489{
f1dc5600 1490 u32 macHi, macLo;
f078f209 1491
2660b81a 1492 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1493 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1494 "keychache entry %u out of range\n", entry);
f1dc5600 1495 return false;
f078f209
LR		 1496 }
1497
f1dc5600
S		 1498 if (mac != NULL) {
1499 macHi = (mac[5] << 8) | mac[4];
1500 macLo = (mac[3] << 24) |
1501 (mac[2] << 16) |
1502 (mac[1] << 8) |
1503 mac[0];
1504 macLo >>= 1;
1505 macLo |= (macHi & 1) << 31;
1506 macHi >>= 1;
f078f209 1507 } else {
f1dc5600 1508 macLo = macHi = 0;
f078f209 1509 }
f1dc5600
S		 1510 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1511 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 1512
f1dc5600 1513 return true;
f078f209 1514}
7322fd19 1515EXPORT_SYMBOL(ath9k_hw_keysetmac);
f078f209 1516
cbe61d8a 1517bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 1518 const struct ath9k_keyval *k,
e0caf9ea 1519 const u8 *mac)
f078f209 1520{
2660b81a 1521 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1522 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 1523 u32 key0, key1, key2, key3, key4;
1524 u32 keyType;
f078f209 1525
f1dc5600 1526 if (entry >= pCap->keycache_size) {
c46917bb
LR		 1527 ath_print(common, ATH_DBG_FATAL,
1528 "keycache entry %u out of range\n", entry);
f1dc5600 1529 return false;
f078f209
LR		 1530 }
1531
f1dc5600
S		 1532 switch (k->kv_type) {
1533 case ATH9K_CIPHER_AES_OCB:
1534 keyType = AR_KEYTABLE_TYPE_AES;
1535 break;
1536 case ATH9K_CIPHER_AES_CCM:
1537 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 1538 ath_print(common, ATH_DBG_ANY,
1539 "AES-CCM not supported by mac rev 0x%x\n",
1540 ah->hw_version.macRev);
f1dc5600
S		 1541 return false;
1542 }
1543 keyType = AR_KEYTABLE_TYPE_CCM;
1544 break;
1545 case ATH9K_CIPHER_TKIP:
1546 keyType = AR_KEYTABLE_TYPE_TKIP;
1547 if (ATH9K_IS_MIC_ENABLED(ah)
1548 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 1549 ath_print(common, ATH_DBG_ANY,
1550 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 1551 return false;
1552 }
1553 break;
1554 case ATH9K_CIPHER_WEP:
e31a16d6 1555 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 1556 ath_print(common, ATH_DBG_ANY,
1557 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 1558 return false;
1559 }
e31a16d6 1560 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 1561 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 1562 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 1563 keyType = AR_KEYTABLE_TYPE_104;
1564 else
1565 keyType = AR_KEYTABLE_TYPE_128;
1566 break;
1567 case ATH9K_CIPHER_CLR:
1568 keyType = AR_KEYTABLE_TYPE_CLR;
1569 break;
1570 default:
c46917bb
LR		 1571 ath_print(common, ATH_DBG_FATAL,
1572 "cipher %u not supported\n", k->kv_type);
f1dc5600 1573 return false;
f078f209
LR		 1574 }
1575
e0caf9ea
JM		 1576 key0 = get_unaligned_le32(k->kv_val + 0);
1577 key1 = get_unaligned_le16(k->kv_val + 4);
1578 key2 = get_unaligned_le32(k->kv_val + 6);
1579 key3 = get_unaligned_le16(k->kv_val + 10);
1580 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 1581 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 1582 key4 &= 0xff;
f078f209 1583
672903b3
JM		 1584 /*
1585 * Note: Key cache registers access special memory area that requires
1586 * two 32-bit writes to actually update the values in the internal
1587 * memory. Consequently, the exact order and pairs used here must be
1588 * maintained.
1589 */
1590
f1dc5600
S		 1591 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1592 u16 micentry = entry + 64;
f078f209 1593
672903b3
JM		 1594 /*
1595 * Write inverted key[47:0] first to avoid Michael MIC errors
1596 * on frames that could be sent or received at the same time.
1597 * The correct key will be written in the end once everything
1598 * else is ready.
1599 */
f1dc5600
S		 1600 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1601 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 1602
1603 /* Write key[95:48] */
f1dc5600
S		 1604 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1605 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1606
1607 /* Write key[127:96] and key type */
f1dc5600
S		 1608 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1609 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 1610
1611 /* Write MAC address for the entry */
f1dc5600 1612 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 1613
2660b81a 1614 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 1615 /*
1616 * TKIP uses two key cache entries:
1617 * Michael MIC TX/RX keys in the same key cache entry
1618 * (idx = main index + 64):
1619 * key0 [31:0] = RX key [31:0]
1620 * key1 [15:0] = TX key [31:16]
1621 * key1 [31:16] = reserved
1622 * key2 [31:0] = RX key [63:32]
1623 * key3 [15:0] = TX key [15:0]
1624 * key3 [31:16] = reserved
1625 * key4 [31:0] = TX key [63:32]
1626 */
f1dc5600 1627 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 1628
f1dc5600
S		 1629 mic0 = get_unaligned_le32(k->kv_mic + 0);
1630 mic2 = get_unaligned_le32(k->kv_mic + 4);
1631 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1632 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1633 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 1634
1635 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 1636 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1637 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 1638
1639 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 1640 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1641 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 1642
1643 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1644 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1645 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1646 AR_KEYTABLE_TYPE_CLR);
f078f209 1647
f1dc5600 1648 } else {
672903b3
JM		 1649 /*
1650 * TKIP uses four key cache entries (two for group
1651 * keys):
1652 * Michael MIC TX/RX keys are in different key cache
1653 * entries (idx = main index + 64 for TX and
1654 * main index + 32 + 96 for RX):
1655 * key0 [31:0] = TX/RX MIC key [31:0]
1656 * key1 [31:0] = reserved
1657 * key2 [31:0] = TX/RX MIC key [63:32]
1658 * key3 [31:0] = reserved
1659 * key4 [31:0] = reserved
1660 *
1661 * Upper layer code will call this function separately
1662 * for TX and RX keys when these registers offsets are
1663 * used.
1664 */
f1dc5600 1665 u32 mic0, mic2;
f078f209 1666
f1dc5600
S		 1667 mic0 = get_unaligned_le32(k->kv_mic + 0);
1668 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 1669
1670 /* Write MIC key[31:0] */
f1dc5600
S		 1671 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1672 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 1673
1674 /* Write MIC key[63:32] */
f1dc5600
S		 1675 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1676 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 1677
1678 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1679 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1680 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1681 AR_KEYTABLE_TYPE_CLR);
1682 }
672903b3
JM		 1683
1684 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 1685 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1686 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 1687
1688 /*
1689 * Write the correct (un-inverted) key[47:0] last to enable
1690 * TKIP now that all other registers are set with correct
1691 * values.
1692 */
f1dc5600
S		 1693 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1694 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1695 } else {
672903b3 1696 /* Write key[47:0] */
f1dc5600
S		 1697 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1698 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 1699
1700 /* Write key[95:48] */
f1dc5600
S		 1701 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1702 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1703
1704 /* Write key[127:96] and key type */
f1dc5600
S		 1705 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1706 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 1707
672903b3 1708 /* Write MAC address for the entry */
f1dc5600
S		 1709 (void) ath9k_hw_keysetmac(ah, entry, mac);
1710 }
f078f209 1711
f078f209
LR		 1712 return true;
1713}
7322fd19 1714EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 1715
cbe61d8a 1716bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 1717{
2660b81a 1718 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 1719 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1720 if (val & AR_KEYTABLE_VALID)
1721 return true;
1722 }
1723 return false;
f078f209 1724}
7322fd19 1725EXPORT_SYMBOL(ath9k_hw_keyisvalid);
f078f209 1726
f1dc5600
S		 1727/******************************/
1728/* Power Management (Chipset) */
1729/******************************/
1730
42d5bc3f
LR		 1731/*
1732 * Notify Power Mgt is disabled in self-generated frames.
1733 * If requested, force chip to sleep.
1734 */
cbe61d8a 1735static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1736{
f1dc5600
S		 1737 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1738 if (setChip) {
42d5bc3f
LR		 1739 /*
1740 * Clear the RTC force wake bit to allow the
1741 * mac to go to sleep.
1742 */
f1dc5600
S		 1743 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1744 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1745 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1746 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1747
42d5bc3f 1748 /* Shutdown chip. Active low */
14b3af38 1749 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1750 REG_CLR_BIT(ah, (AR_RTC_RESET),
1751 AR_RTC_RESET_EN);
f1dc5600 1752 }
f078f209
LR		 1753}
1754
bbd79af5
LR		 1755/*
1756 * Notify Power Management is enabled in self-generating
1757 * frames. If request, set power mode of chip to
1758 * auto/normal. Duration in units of 128us (1/8 TU).
1759 */
cbe61d8a 1760static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1761{
f1dc5600
S		 1762 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1763 if (setChip) {
2660b81a 1764 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1765
f1dc5600 1766 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1767 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1768 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1769 AR_RTC_FORCE_WAKE_ON_INT);
1770 } else {
bbd79af5
LR		 1771 /*
1772 * Clear the RTC force wake bit to allow the
1773 * mac to go to sleep.
1774 */
f1dc5600
S		 1775 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1776 AR_RTC_FORCE_WAKE_EN);
f078f209 1777 }
f078f209 1778 }
f078f209
LR		 1779}
1780
cbe61d8a 1781static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1782{
f1dc5600
S		 1783 u32 val;
1784 int i;
f078f209 1785
f1dc5600
S		 1786 if (setChip) {
1787 if ((REG_READ(ah, AR_RTC_STATUS) &
1788 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1789 if (ath9k_hw_set_reset_reg(ah,
1790 ATH9K_RESET_POWER_ON) != true) {
1791 return false;
1792 }
e041228f
LR		 1793 if (!AR_SREV_9300_20_OR_LATER(ah))
1794 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1795 }
1796 if (AR_SREV_9100(ah))
1797 REG_SET_BIT(ah, AR_RTC_RESET,
1798 AR_RTC_RESET_EN);
f078f209 1799
f1dc5600
S		 1800 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1801 AR_RTC_FORCE_WAKE_EN);
1802 udelay(50);
f078f209 1803
f1dc5600
S		 1804 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1805 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1806 if (val == AR_RTC_STATUS_ON)
1807 break;
1808 udelay(50);
1809 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1810 AR_RTC_FORCE_WAKE_EN);
f078f209 1811 }
f1dc5600 1812 if (i == 0) {
c46917bb
LR		 1813 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1814 "Failed to wakeup in %uus\n",
1815 POWER_UP_TIME / 20);
f1dc5600 1816 return false;
f078f209 1817 }
f078f209
LR		 1818 }
1819
f1dc5600 1820 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1821
f1dc5600 1822 return true;
f078f209
LR		 1823}
1824
9ecdef4b 1825bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1826{
c46917bb 1827 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1828 int status = true, setChip = true;
f1dc5600
S		 1829 static const char *modes[] = {
1830 "AWAKE",
1831 "FULL-SLEEP",
1832 "NETWORK SLEEP",
1833 "UNDEFINED"
1834 };
f1dc5600 1835
cbdec975
GJ		 1836 if (ah->power_mode == mode)
1837 return status;
1838
c46917bb
LR		 1839 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1840 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1841
1842 switch (mode) {
1843 case ATH9K_PM_AWAKE:
1844 status = ath9k_hw_set_power_awake(ah, setChip);
1845 break;
1846 case ATH9K_PM_FULL_SLEEP:
1847 ath9k_set_power_sleep(ah, setChip);
2660b81a 1848 ah->chip_fullsleep = true;
f1dc5600
S		 1849 break;
1850 case ATH9K_PM_NETWORK_SLEEP:
1851 ath9k_set_power_network_sleep(ah, setChip);
1852 break;
f078f209 1853 default:
c46917bb
LR		 1854 ath_print(common, ATH_DBG_FATAL,
1855 "Unknown power mode %u\n", mode);
f078f209
LR		 1856 return false;
1857 }
2660b81a 1858 ah->power_mode = mode;
f1dc5600
S		 1859
1860 return status;
f078f209 1861}
7322fd19 1862EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1863
f1dc5600
S		 1864/*******************/
1865/* Beacon Handling */
1866/*******************/
1867
cbe61d8a 1868void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 1869{
f078f209
LR		 1870 int flags = 0;
1871
2660b81a 1872 ah->beacon_interval = beacon_period;
f078f209 1873
7d0d0df0
S		 1874 ENABLE_REGWRITE_BUFFER(ah);
1875
2660b81a 1876 switch (ah->opmode) {
d97809db
CM		 1877 case NL80211_IFTYPE_STATION:
1878 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 1879 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1880 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1881 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1882 flags |= AR_TBTT_TIMER_EN;
1883 break;
d97809db 1884 case NL80211_IFTYPE_ADHOC:
9cb5412b 1885 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 1886 REG_SET_BIT(ah, AR_TXCFG,
1887 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1888 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1889 TU_TO_USEC(next_beacon +
2660b81a
S		 1890 (ah->atim_window ? ah->
1891 atim_window : 1)));
f078f209 1892 flags |= AR_NDP_TIMER_EN;
d97809db 1893 case NL80211_IFTYPE_AP:
f078f209
LR		 1894 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1895 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1896 TU_TO_USEC(next_beacon -
2660b81a 1897 ah->config.
60b67f51 1898 dma_beacon_response_time));
f078f209
LR		 1899 REG_WRITE(ah, AR_NEXT_SWBA,
1900 TU_TO_USEC(next_beacon -
2660b81a 1901 ah->config.
60b67f51 1902 sw_beacon_response_time));
f078f209
LR		 1903 flags |=
1904 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1905 break;
d97809db 1906 default:
c46917bb
LR		 1907 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1908 "%s: unsupported opmode: %d\n",
1909 __func__, ah->opmode);
d97809db
CM		 1910 return;
1911 break;
f078f209
LR		 1912 }
1913
1914 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1915 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1916 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1917 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1918
7d0d0df0
S		 1919 REGWRITE_BUFFER_FLUSH(ah);
1920 DISABLE_REGWRITE_BUFFER(ah);
1921
f078f209
LR		 1922 beacon_period &= ~ATH9K_BEACON_ENA;
1923 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 1924 ath9k_hw_reset_tsf(ah);
1925 }
1926
1927 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1928}
7322fd19 1929EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 1930
cbe61d8a 1931void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 1932 const struct ath9k_beacon_state *bs)
f078f209
LR		 1933{
1934 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 1935 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1936 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1937
7d0d0df0
S		 1938 ENABLE_REGWRITE_BUFFER(ah);
1939
f078f209
LR		 1940 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1941
1942 REG_WRITE(ah, AR_BEACON_PERIOD,
1943 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1944 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1945 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1946
7d0d0df0
S		 1947 REGWRITE_BUFFER_FLUSH(ah);
1948 DISABLE_REGWRITE_BUFFER(ah);
1949
f078f209
LR		 1950 REG_RMW_FIELD(ah, AR_RSSI_THR,
1951 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1952
1953 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1954
1955 if (bs->bs_sleepduration > beaconintval)
1956 beaconintval = bs->bs_sleepduration;
1957
1958 dtimperiod = bs->bs_dtimperiod;
1959 if (bs->bs_sleepduration > dtimperiod)
1960 dtimperiod = bs->bs_sleepduration;
1961
1962 if (beaconintval == dtimperiod)
1963 nextTbtt = bs->bs_nextdtim;
1964 else
1965 nextTbtt = bs->bs_nexttbtt;
1966
c46917bb
LR		 1967 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1968 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1969 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1970 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 1971
7d0d0df0
S		 1972 ENABLE_REGWRITE_BUFFER(ah);
1973
f1dc5600
S		 1974 REG_WRITE(ah, AR_NEXT_DTIM,
1975 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1976 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 1977
f1dc5600
S		 1978 REG_WRITE(ah, AR_SLEEP1,
1979 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1980 | AR_SLEEP1_ASSUME_DTIM);
f078f209 1981
f1dc5600
S		 1982 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1983 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1984 else
1985 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 1986
f1dc5600
S		 1987 REG_WRITE(ah, AR_SLEEP2,
1988 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 1989
f1dc5600
S		 1990 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1991 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 1992
7d0d0df0
S		 1993 REGWRITE_BUFFER_FLUSH(ah);
1994 DISABLE_REGWRITE_BUFFER(ah);
1995
f1dc5600
S		 1996 REG_SET_BIT(ah, AR_TIMER_MODE,
1997 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1998 AR_DTIM_TIMER_EN);
f078f209 1999
4af9cf4f
S		 2000 /* TSF Out of Range Threshold */
2001 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2002}
7322fd19 2003EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2004
f1dc5600
S		 2005/*******************/
2006/* HW Capabilities */
2007/*******************/
2008
a9a29ce6 2009int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2010{
2660b81a 2011 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2012 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2013 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 2014 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 2015
f1dc5600 2016 u16 capField = 0, eeval;
f078f209 2017
f74df6fb 2018 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2019 regulatory->current_rd = eeval;
f078f209 2020
f74df6fb 2021 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 2022 if (AR_SREV_9285_10_OR_LATER(ah))
2023 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 2024 regulatory->current_rd_ext = eeval;
f078f209 2025
f74df6fb 2026 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 2027
2660b81a 2028 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2029 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2030 if (regulatory->current_rd == 0x64 ||
2031 regulatory->current_rd == 0x65)
2032 regulatory->current_rd += 5;
2033 else if (regulatory->current_rd == 0x41)
2034 regulatory->current_rd = 0x43;
c46917bb
LR		 2035 ath_print(common, ATH_DBG_REGULATORY,
2036 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 2037 }
f078f209 2038
f74df6fb 2039 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6
GJ		 2040 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2041 ath_print(common, ATH_DBG_FATAL,
2042 "no band has been marked as supported in EEPROM.\n");
2043 return -EINVAL;
2044 }
2045
f1dc5600 2046 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 2047
f1dc5600
S		 2048 if (eeval & AR5416_OPFLAGS_11A) {
2049 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 2050 if (ah->config.ht_enable) {
f1dc5600
S		 2051 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2052 set_bit(ATH9K_MODE_11NA_HT20,
2053 pCap->wireless_modes);
2054 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2055 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2056 pCap->wireless_modes);
2057 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2058 pCap->wireless_modes);
2059 }
f078f209 2060 }
f078f209
LR		 2061 }
2062
f1dc5600 2063 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 2064 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 2065 if (ah->config.ht_enable) {
f1dc5600
S		 2066 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2067 set_bit(ATH9K_MODE_11NG_HT20,
2068 pCap->wireless_modes);
2069 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2070 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2071 pCap->wireless_modes);
2072 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2073 pCap->wireless_modes);
2074 }
2075 }
f078f209 2076 }
f1dc5600 2077
f74df6fb 2078 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2079 /*
2080 * For AR9271 we will temporarilly uses the rx chainmax as read from
2081 * the EEPROM.
2082 */
8147f5de 2083 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2084 !(eeval & AR5416_OPFLAGS_11A) &&
2085 !(AR_SREV_9271(ah)))
2086 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 2087 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2088 else
d7e7d229 2089 /* Use rx_chainmask from EEPROM. */
8147f5de 2090 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2091
d535a42a 2092 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 2093 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2094
f1dc5600
S		 2095 pCap->low_2ghz_chan = 2312;
2096 pCap->high_2ghz_chan = 2732;
f078f209 2097
f1dc5600
S		 2098 pCap->low_5ghz_chan = 4920;
2099 pCap->high_5ghz_chan = 6100;
f078f209 2100
f1dc5600
S		 2101 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2102 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2103 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 2104
f1dc5600
S		 2105 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2106 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2107 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 2108
2660b81a 2109 if (ah->config.ht_enable)
f1dc5600
S		 2110 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2111 else
2112 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2113
f1dc5600
S		 2114 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2115 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2116 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2117 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 2118
f1dc5600
S		 2119 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2120 pCap->total_queues =
2121 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2122 else
2123 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 2124
f1dc5600
S		 2125 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2126 pCap->keycache_size =
2127 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2128 else
2129 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 2130
f1dc5600 2131 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f4709fdf
LR		 2132
2133 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2134 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2135 else
2136 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 2137
5b5fa355
S		 2138 if (AR_SREV_9271(ah))
2139 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2140 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2141 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2142 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 2143 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2144 else
2145 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2146
f1dc5600
S		 2147 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2148 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2149 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2150 } else {
2151 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 2152 }
2153
f1dc5600
S		 2154 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2155
e97275cb 2156#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2157 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2158 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2159 ah->rfkill_gpio =
2160 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2161 ah->rfkill_polarity =
2162 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2163
2164 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2165 }
f1dc5600 2166#endif
bde748a4
VN		 2167 if (AR_SREV_9271(ah))
2168 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2169 else
2170 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2171
e7594072 2172 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2173 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2174 else
2175 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2176
608b88cb 2177 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 2178 pCap->reg_cap =
2179 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2180 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2181 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2182 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 2183 } else {
f1dc5600
S		 2184 pCap->reg_cap =
2185 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2186 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 2187 }
f078f209 2188
ebb90cfc
SB		 2189 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2190 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2191 AR_SREV_5416(ah))
2192 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 2193
2194 pCap->num_antcfg_5ghz =
f74df6fb 2195 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 2196 pCap->num_antcfg_2ghz =
f74df6fb 2197 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 2198
fe12946e 2199 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 2200 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 2201 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2202 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 2203
8c8f9ba7 2204 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 2205 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2206 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 2207 } else {
766ec4a9 2208 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 2209 }
22f25d0d 2210 } else {
766ec4a9 2211 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 2212 }
a9a29ce6 2213
ceb26445 2214 if (AR_SREV_9300_20_OR_LATER(ah)) {
e5553724
VT		 2215 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2216 ATH9K_HW_CAP_FASTCLOCK;
ceb26445
VT		 2217 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2218 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2219 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2220 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2221 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2222 } else {
2223 pCap->tx_desc_len = sizeof(struct ath_desc);
6b42e8d0
FF		 2224 if (AR_SREV_9280_20(ah) &&
2225 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2226 AR5416_EEP_MINOR_VER_16) ||
2227 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2228 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2229 }
1adf02ff 2230
6c84ce08
VT		 2231 if (AR_SREV_9300_20_OR_LATER(ah))
2232 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2233
a9a29ce6 2234 return 0;
f078f209
LR		 2235}
2236
cbe61d8a 2237bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2238 u32 capability, u32 *result)
f078f209 2239{
608b88cb 2240 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 2241 switch (type) {
2242 case ATH9K_CAP_CIPHER:
2243 switch (capability) {
2244 case ATH9K_CIPHER_AES_CCM:
2245 case ATH9K_CIPHER_AES_OCB:
2246 case ATH9K_CIPHER_TKIP:
2247 case ATH9K_CIPHER_WEP:
2248 case ATH9K_CIPHER_MIC:
2249 case ATH9K_CIPHER_CLR:
2250 return true;
2251 default:
2252 return false;
2253 }
2254 case ATH9K_CAP_TKIP_MIC:
2255 switch (capability) {
2256 case 0:
2257 return true;
2258 case 1:
2660b81a 2259 return (ah->sta_id1_defaults &
f1dc5600
S		 2260 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2261 false;
2262 }
2263 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 2264 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 2265 false : true;
f1dc5600
S		 2266 case ATH9K_CAP_MCAST_KEYSRCH:
2267 switch (capability) {
2268 case 0:
2269 return true;
2270 case 1:
2271 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2272 return false;
2273 } else {
2660b81a 2274 return (ah->sta_id1_defaults &
f1dc5600
S		 2275 AR_STA_ID1_MCAST_KSRCH) ? true :
2276 false;
2277 }
2278 }
2279 return false;
f1dc5600
S		 2280 case ATH9K_CAP_TXPOW:
2281 switch (capability) {
2282 case 0:
2283 return 0;
2284 case 1:
608b88cb 2285 *result = regulatory->power_limit;
f1dc5600
S		 2286 return 0;
2287 case 2:
608b88cb 2288 *result = regulatory->max_power_level;
f1dc5600
S		 2289 return 0;
2290 case 3:
608b88cb 2291 *result = regulatory->tp_scale;
f1dc5600
S		 2292 return 0;
2293 }
2294 return false;
8bd1d07f
SB		 2295 case ATH9K_CAP_DS:
2296 return (AR_SREV_9280_20_OR_LATER(ah) &&
2297 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2298 ? false : true;
f1dc5600
S		 2299 default:
2300 return false;
f078f209 2301 }
f078f209 2302}
7322fd19 2303EXPORT_SYMBOL(ath9k_hw_getcapability);
f078f209 2304
cbe61d8a 2305bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2306 u32 capability, u32 setting, int *status)
f078f209 2307{
f1dc5600
S		 2308 switch (type) {
2309 case ATH9K_CAP_TKIP_MIC:
2310 if (setting)
2660b81a 2311 ah->sta_id1_defaults |=
f1dc5600
S		 2312 AR_STA_ID1_CRPT_MIC_ENABLE;
2313 else
2660b81a 2314 ah->sta_id1_defaults &=
f1dc5600
S		 2315 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2316 return true;
f1dc5600
S		 2317 case ATH9K_CAP_MCAST_KEYSRCH:
2318 if (setting)
2660b81a 2319 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2320 else
2660b81a 2321 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2322 return true;
f1dc5600
S		 2323 default:
2324 return false;
f078f209
LR		 2325 }
2326}
7322fd19 2327EXPORT_SYMBOL(ath9k_hw_setcapability);
f078f209 2328
f1dc5600
S		 2329/****************************/
2330/* GPIO / RFKILL / Antennae */
2331/****************************/
f078f209 2332
cbe61d8a 2333static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2334 u32 gpio, u32 type)
2335{
2336 int addr;
2337 u32 gpio_shift, tmp;
f078f209 2338
f1dc5600
S		 2339 if (gpio > 11)
2340 addr = AR_GPIO_OUTPUT_MUX3;
2341 else if (gpio > 5)
2342 addr = AR_GPIO_OUTPUT_MUX2;
2343 else
2344 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2345
f1dc5600 2346 gpio_shift = (gpio % 6) * 5;
f078f209 2347
f1dc5600
S		 2348 if (AR_SREV_9280_20_OR_LATER(ah)
2349 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2350 REG_RMW(ah, addr, (type << gpio_shift),
2351 (0x1f << gpio_shift));
f078f209 2352 } else {
f1dc5600
S		 2353 tmp = REG_READ(ah, addr);
2354 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2355 tmp &= ~(0x1f << gpio_shift);
2356 tmp |= (type << gpio_shift);
2357 REG_WRITE(ah, addr, tmp);
f078f209 2358 }
f078f209
LR		 2359}
2360
cbe61d8a 2361void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2362{
f1dc5600 2363 u32 gpio_shift;
f078f209 2364
9680e8a3 2365 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2366
f1dc5600 2367 gpio_shift = gpio << 1;
f078f209 2368
f1dc5600
S		 2369 REG_RMW(ah,
2370 AR_GPIO_OE_OUT,
2371 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2372 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2373}
7322fd19 2374EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2375
cbe61d8a 2376u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2377{
cb33c412
SB		 2378#define MS_REG_READ(x, y) \
2379 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2380
2660b81a 2381 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2382 return 0xffffffff;
f078f209 2383
783dfca1
FF		 2384 if (AR_SREV_9300_20_OR_LATER(ah))
2385 return MS_REG_READ(AR9300, gpio) != 0;
2386 else if (AR_SREV_9271(ah))
5b5fa355
S		 2387 return MS_REG_READ(AR9271, gpio) != 0;
2388 else if (AR_SREV_9287_10_OR_LATER(ah))
ac88b6ec
VN		 2389 return MS_REG_READ(AR9287, gpio) != 0;
2390 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2391 return MS_REG_READ(AR9285, gpio) != 0;
2392 else if (AR_SREV_9280_10_OR_LATER(ah))
2393 return MS_REG_READ(AR928X, gpio) != 0;
2394 else
2395 return MS_REG_READ(AR, gpio) != 0;
f078f209 2396}
7322fd19 2397EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2398
cbe61d8a 2399void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2400 u32 ah_signal_type)
f078f209 2401{
f1dc5600 2402 u32 gpio_shift;
f078f209 2403
f1dc5600 2404 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 2405
f1dc5600 2406 gpio_shift = 2 * gpio;
f078f209 2407
f1dc5600
S		 2408 REG_RMW(ah,
2409 AR_GPIO_OE_OUT,
2410 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2411 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2412}
7322fd19 2413EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2414
cbe61d8a 2415void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2416{
5b5fa355
S		 2417 if (AR_SREV_9271(ah))
2418 val = ~val;
2419
f1dc5600
S		 2420 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2421 AR_GPIO_BIT(gpio));
f078f209 2422}
7322fd19 2423EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2424
cbe61d8a 2425u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2426{
f1dc5600 2427 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2428}
7322fd19 2429EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2430
cbe61d8a 2431void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2432{
f1dc5600 2433 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2434}
7322fd19 2435EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2436
f1dc5600
S		 2437/*********************/
2438/* General Operation */
2439/*********************/
2440
cbe61d8a 2441u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2442{
f1dc5600
S		 2443 u32 bits = REG_READ(ah, AR_RX_FILTER);
2444 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2445
f1dc5600
S		 2446 if (phybits & AR_PHY_ERR_RADAR)
2447 bits |= ATH9K_RX_FILTER_PHYRADAR;
2448 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2449 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2450
f1dc5600 2451 return bits;
f078f209 2452}
7322fd19 2453EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2454
cbe61d8a 2455void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2456{
f1dc5600 2457 u32 phybits;
f078f209 2458
7d0d0df0
S		 2459 ENABLE_REGWRITE_BUFFER(ah);
2460
7ea310be
S		 2461 REG_WRITE(ah, AR_RX_FILTER, bits);
2462
f1dc5600
S		 2463 phybits = 0;
2464 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2465 phybits |= AR_PHY_ERR_RADAR;
2466 if (bits & ATH9K_RX_FILTER_PHYERR)
2467 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2468 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2469
f1dc5600
S		 2470 if (phybits)
2471 REG_WRITE(ah, AR_RXCFG,
2472 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2473 else
2474 REG_WRITE(ah, AR_RXCFG,
2475 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2476
2477 REGWRITE_BUFFER_FLUSH(ah);
2478 DISABLE_REGWRITE_BUFFER(ah);
f1dc5600 2479}
7322fd19 2480EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2481
cbe61d8a 2482bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2483{
63a75b91
SB		 2484 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2485 return false;
2486
2487 ath9k_hw_init_pll(ah, NULL);
2488 return true;
f1dc5600 2489}
7322fd19 2490EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2491
cbe61d8a 2492bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2493{
9ecdef4b 2494 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2495 return false;
f078f209 2496
63a75b91
SB		 2497 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2498 return false;
2499
2500 ath9k_hw_init_pll(ah, NULL);
2501 return true;
f078f209 2502}
7322fd19 2503EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2504
8fbff4b8 2505void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 2506{
608b88cb 2507 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2508 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2509 struct ieee80211_channel *channel = chan->chan;
f078f209 2510
608b88cb 2511 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2512
8fbff4b8 2513 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2514 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2515 channel->max_antenna_gain * 2,
2516 channel->max_power * 2,
2517 min((u32) MAX_RATE_POWER,
608b88cb 2518 (u32) regulatory->power_limit));
6f255425 2519}
7322fd19 2520EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2521
cbe61d8a 2522void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 2523{
1510718d 2524 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
f078f209 2525}
7322fd19 2526EXPORT_SYMBOL(ath9k_hw_setmac);
f078f209 2527
cbe61d8a 2528void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2529{
2660b81a 2530 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2531}
7322fd19 2532EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2533
cbe61d8a 2534void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2535{
f1dc5600
S		 2536 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2537 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2538}
7322fd19 2539EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2540
f2b2143e 2541void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2542{
1510718d
LR		 2543 struct ath_common *common = ath9k_hw_common(ah);
2544
2545 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2546 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2547 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2548}
7322fd19 2549EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2550
1c0fc65e
BP		 2551#define ATH9K_MAX_TSF_READ 10
2552
cbe61d8a 2553u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2554{
1c0fc65e
BP		 2555 u32 tsf_lower, tsf_upper1, tsf_upper2;
2556 int i;
2557
2558 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2559 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2560 tsf_lower = REG_READ(ah, AR_TSF_L32);
2561 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2562 if (tsf_upper2 == tsf_upper1)
2563 break;
2564 tsf_upper1 = tsf_upper2;
2565 }
f078f209 2566
1c0fc65e 2567 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2568
1c0fc65e 2569 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2570}
7322fd19 2571EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2572
cbe61d8a 2573void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2574{
27abe060 2575 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2576 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2577}
7322fd19 2578EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2579
cbe61d8a 2580void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2581{
f9b604f6
GJ		 2582 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2583 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 2584 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2585 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2586
f1dc5600
S		 2587 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2588}
7322fd19 2589EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2590
54e4cec6 2591void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2592{
f1dc5600 2593 if (setting)
2660b81a 2594 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2595 else
2660b81a 2596 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2597}
7322fd19 2598EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2599
30cbd422
LR		 2600/*
2601 * Extend 15-bit time stamp from rx descriptor to
2602 * a full 64-bit TSF using the current h/w TSF.
2603*/
2604u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2605{
2606 u64 tsf;
2607
2608 tsf = ath9k_hw_gettsf64(ah);
2609 if ((tsf & 0x7fff) < rstamp)
2610 tsf -= 0x8000;
2611 return (tsf & ~0x7fff) | rstamp;
2612}
2613EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2614
25c56eec 2615void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2616{
25c56eec 2617 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2618 u32 macmode;
2619
25c56eec 2620 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2621 macmode = AR_2040_JOINED_RX_CLEAR;
2622 else
2623 macmode = 0;
f078f209 2624
f1dc5600 2625 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2626}
ff155a45
VT		 2627
2628/* HW Generic timers configuration */
2629
2630static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2631{
2632 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2633 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2634 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2635 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2636 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2637 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2638 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2639 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2640 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2641 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2642 AR_NDP2_TIMER_MODE, 0x0002},
2643 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2644 AR_NDP2_TIMER_MODE, 0x0004},
2645 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2646 AR_NDP2_TIMER_MODE, 0x0008},
2647 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2648 AR_NDP2_TIMER_MODE, 0x0010},
2649 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2650 AR_NDP2_TIMER_MODE, 0x0020},
2651 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2652 AR_NDP2_TIMER_MODE, 0x0040},
2653 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2654 AR_NDP2_TIMER_MODE, 0x0080}
2655};
2656
2657/* HW generic timer primitives */
2658
2659/* compute and clear index of rightmost 1 */
2660static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2661{
2662 u32 b;
2663
2664 b = *mask;
2665 b &= (0-b);
2666 *mask &= ~b;
2667 b *= debruijn32;
2668 b >>= 27;
2669
2670 return timer_table->gen_timer_index[b];
2671}
2672
1773912b 2673u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2674{
2675 return REG_READ(ah, AR_TSF_L32);
2676}
7322fd19 2677EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2678
2679struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2680 void (*trigger)(void *),
2681 void (*overflow)(void *),
2682 void *arg,
2683 u8 timer_index)
2684{
2685 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2686 struct ath_gen_timer *timer;
2687
2688 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2689
2690 if (timer == NULL) {
c46917bb
LR		 2691 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2692 "Failed to allocate memory"
2693 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 2694 return NULL;
2695 }
2696
2697 /* allocate a hardware generic timer slot */
2698 timer_table->timers[timer_index] = timer;
2699 timer->index = timer_index;
2700 timer->trigger = trigger;
2701 timer->overflow = overflow;
2702 timer->arg = arg;
2703
2704 return timer;
2705}
7322fd19 2706EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2707
cd9bf689
LR		 2708void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2709 struct ath_gen_timer *timer,
2710 u32 timer_next,
2711 u32 timer_period)
ff155a45
VT		 2712{
2713 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2714 u32 tsf;
2715
2716 BUG_ON(!timer_period);
2717
2718 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2719
2720 tsf = ath9k_hw_gettsf32(ah);
2721
c46917bb
LR		 2722 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2723 "curent tsf %x period %x"
2724 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 2725
2726 /*
2727 * Pull timer_next forward if the current TSF already passed it
2728 * because of software latency
2729 */
2730 if (timer_next < tsf)
2731 timer_next = tsf + timer_period;
2732
2733 /*
2734 * Program generic timer registers
2735 */
2736 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2737 timer_next);
2738 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2739 timer_period);
2740 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2741 gen_tmr_configuration[timer->index].mode_mask);
2742
2743 /* Enable both trigger and thresh interrupt masks */
2744 REG_SET_BIT(ah, AR_IMR_S5,
2745 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2746 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2747}
7322fd19 2748EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2749
cd9bf689 2750void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2751{
2752 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2753
2754 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2755 (timer->index >= ATH_MAX_GEN_TIMER)) {
2756 return;
2757 }
2758
2759 /* Clear generic timer enable bits. */
2760 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2761 gen_tmr_configuration[timer->index].mode_mask);
2762
2763 /* Disable both trigger and thresh interrupt masks */
2764 REG_CLR_BIT(ah, AR_IMR_S5,
2765 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2766 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2767
2768 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 2769}
7322fd19 2770EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2771
2772void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2773{
2774 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2775
2776 /* free the hardware generic timer slot */
2777 timer_table->timers[timer->index] = NULL;
2778 kfree(timer);
2779}
7322fd19 2780EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2781
2782/*
2783 * Generic Timer Interrupts handling
2784 */
2785void ath_gen_timer_isr(struct ath_hw *ah)
2786{
2787 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2788 struct ath_gen_timer *timer;
c46917bb 2789 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 2790 u32 trigger_mask, thresh_mask, index;
2791
2792 /* get hardware generic timer interrupt status */
2793 trigger_mask = ah->intr_gen_timer_trigger;
2794 thresh_mask = ah->intr_gen_timer_thresh;
2795 trigger_mask &= timer_table->timer_mask.val;
2796 thresh_mask &= timer_table->timer_mask.val;
2797
2798 trigger_mask &= ~thresh_mask;
2799
2800 while (thresh_mask) {
2801 index = rightmost_index(timer_table, &thresh_mask);
2802 timer = timer_table->timers[index];
2803 BUG_ON(!timer);
c46917bb
LR		 2804 ath_print(common, ATH_DBG_HWTIMER,
2805 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 2806 timer->overflow(timer->arg);
2807 }
2808
2809 while (trigger_mask) {
2810 index = rightmost_index(timer_table, &trigger_mask);
2811 timer = timer_table->timers[index];
2812 BUG_ON(!timer);
c46917bb
LR		 2813 ath_print(common, ATH_DBG_HWTIMER,
2814 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 2815 timer->trigger(timer->arg);
2816 }
2817}
7322fd19 2818EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2819
05020d23
S		 2820/********/
2821/* HTC */
2822/********/
2823
2824void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2825{
2826 ah->htc_reset_init = true;
2827}
2828EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2829
2da4f01a
LR		 2830static struct {
2831 u32 version;
2832 const char * name;
2833} ath_mac_bb_names[] = {
2834 /* Devices with external radios */
2835 { AR_SREV_VERSION_5416_PCI, "5416" },
2836 { AR_SREV_VERSION_5416_PCIE, "5418" },
2837 { AR_SREV_VERSION_9100, "9100" },
2838 { AR_SREV_VERSION_9160, "9160" },
2839 /* Single-chip solutions */
2840 { AR_SREV_VERSION_9280, "9280" },
2841 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 2842 { AR_SREV_VERSION_9287, "9287" },
2843 { AR_SREV_VERSION_9271, "9271" },
ec83903e 2844 { AR_SREV_VERSION_9300, "9300" },
2da4f01a
LR		 2845};
2846
2847/* For devices with external radios */
2848static struct {
2849 u16 version;
2850 const char * name;
2851} ath_rf_names[] = {
2852 { 0, "5133" },
2853 { AR_RAD5133_SREV_MAJOR, "5133" },
2854 { AR_RAD5122_SREV_MAJOR, "5122" },
2855 { AR_RAD2133_SREV_MAJOR, "2133" },
2856 { AR_RAD2122_SREV_MAJOR, "2122" }
2857};
2858
2859/*
2860 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2861 */
f934c4d9 2862static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 2863{
2864 int i;
2865
2866 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2867 if (ath_mac_bb_names[i].version == mac_bb_version) {
2868 return ath_mac_bb_names[i].name;
2869 }
2870 }
2871
2872 return "????";
2873}
2da4f01a
LR		 2874
2875/*
2876 * Return the RF name. "????" is returned if the RF is unknown.
2877 * Used for devices with external radios.
2878 */
f934c4d9 2879static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 2880{
2881 int i;
2882
2883 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2884 if (ath_rf_names[i].version == rf_version) {
2885 return ath_rf_names[i].name;
2886 }
2887 }
2888
2889 return "????";
2890}
f934c4d9
LR		 2891
2892void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2893{
2894 int used;
2895
2896 /* chipsets >= AR9280 are single-chip */
2897 if (AR_SREV_9280_10_OR_LATER(ah)) {
2898 used = snprintf(hw_name, len,
2899 "Atheros AR%s Rev:%x",
2900 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2901 ah->hw_version.macRev);
2902 }
2903 else {
2904 used = snprintf(hw_name, len,
2905 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2906 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2907 ah->hw_version.macRev,
2908 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2909 AR_RADIO_SREV_MAJOR)),
2910 ah->hw_version.phyRev);
2911 }
2912
2913 hw_name[used] = '\0';
2914}
2915EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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