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ath9k: Fix softlockup in AR9485
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
f078f209
LR		 20#include <asm/unaligned.h>
21
af03abec 22#include "hw.h"
d70357d5 23#include "hw-ops.h"
cfe8cba9 24#include "rc.h"
b622a720 25#include "ar9003_mac.h"
f4701b5a 26#include "ar9003_mci.h"
462e58f2
BG		 27#include "debug.h"
28#include "ath9k.h"
f078f209 29
cbe61d8a 30static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 31
7322fd19
LR		 32MODULE_AUTHOR("Atheros Communications");
33MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
34MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
35MODULE_LICENSE("Dual BSD/GPL");
36
37static int __init ath9k_init(void)
38{
39 return 0;
40}
41module_init(ath9k_init);
42
43static void __exit ath9k_exit(void)
44{
45 return;
46}
47module_exit(ath9k_exit);
48
d70357d5
LR		 49/* Private hardware callbacks */
50
51static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
52{
53 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
54}
55
56static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
57{
58 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
59}
60
64773964
LR		 61static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
62 struct ath9k_channel *chan)
63{
64 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
65}
66
991312d8
LR		 67static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
68{
69 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
70 return;
71
72 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
73}
74
e36b27af
LR		 75static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
76{
77 /* You will not have this callback if using the old ANI */
78 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
79 return;
80
81 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
82}
83
f1dc5600
S		 84/********************/
85/* Helper Functions */
86/********************/
f078f209 87
462e58f2
BG		 88#ifdef CONFIG_ATH9K_DEBUGFS
89
90void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
91{
92 struct ath_softc *sc = common->priv;
93 if (sync_cause)
94 sc->debug.stats.istats.sync_cause_all++;
95 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
96 sc->debug.stats.istats.sync_rtc_irq++;
97 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
98 sc->debug.stats.istats.sync_mac_irq++;
99 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
100 sc->debug.stats.istats.eeprom_illegal_access++;
101 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
102 sc->debug.stats.istats.apb_timeout++;
103 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
104 sc->debug.stats.istats.pci_mode_conflict++;
105 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
106 sc->debug.stats.istats.host1_fatal++;
107 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
108 sc->debug.stats.istats.host1_perr++;
109 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
110 sc->debug.stats.istats.trcv_fifo_perr++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
112 sc->debug.stats.istats.radm_cpl_ep++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
114 sc->debug.stats.istats.radm_cpl_dllp_abort++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
116 sc->debug.stats.istats.radm_cpl_tlp_abort++;
117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
118 sc->debug.stats.istats.radm_cpl_ecrc_err++;
119 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
120 sc->debug.stats.istats.radm_cpl_timeout++;
121 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
122 sc->debug.stats.istats.local_timeout++;
123 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
124 sc->debug.stats.istats.pm_access++;
125 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
126 sc->debug.stats.istats.mac_awake++;
127 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
128 sc->debug.stats.istats.mac_asleep++;
129 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
130 sc->debug.stats.istats.mac_sleep_access++;
131}
132#endif
133
134
dfdac8ac 135static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 136{
b002a4a9 137 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
dfdac8ac
FF		 138 struct ath_common *common = ath9k_hw_common(ah);
139 unsigned int clockrate;
cbe61d8a 140
087b6ff6
FF		 141 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
142 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
143 clockrate = 117;
144 else if (!ah->curchan) /* should really check for CCK instead */
dfdac8ac
FF		 145 clockrate = ATH9K_CLOCK_RATE_CCK;
146 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
147 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
148 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
149 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 150 else
dfdac8ac
FF		 151 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
152
153 if (conf_is_ht40(conf))
154 clockrate *= 2;
155
906c7205
FF		 156 if (ah->curchan) {
157 if (IS_CHAN_HALF_RATE(ah->curchan))
158 clockrate /= 2;
159 if (IS_CHAN_QUARTER_RATE(ah->curchan))
160 clockrate /= 4;
161 }
162
dfdac8ac 163 common->clockrate = clockrate;
f1dc5600
S		 164}
165
cbe61d8a 166static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 167{
dfdac8ac 168 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 169
dfdac8ac 170 return usecs * common->clockrate;
f1dc5600 171}
f078f209 172
0caa7b14 173bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 174{
175 int i;
176
0caa7b14
S		 177 BUG_ON(timeout < AH_TIME_QUANTUM);
178
179 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 180 if ((REG_READ(ah, reg) & mask) == val)
181 return true;
182
183 udelay(AH_TIME_QUANTUM);
184 }
04bd4638 185
d2182b69 186 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 187 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
188 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 189
f1dc5600 190 return false;
f078f209 191}
7322fd19 192EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 193
7c5adc8d
FF		 194void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
195 int hw_delay)
196{
197 if (IS_CHAN_B(chan))
198 hw_delay = (4 * hw_delay) / 22;
199 else
200 hw_delay /= 10;
201
202 if (IS_CHAN_HALF_RATE(chan))
203 hw_delay *= 2;
204 else if (IS_CHAN_QUARTER_RATE(chan))
205 hw_delay *= 4;
206
207 udelay(hw_delay + BASE_ACTIVATE_DELAY);
208}
209
a9b6b256
FF		 210void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
211 int column, unsigned int *writecnt)
212{
213 int r;
214
215 ENABLE_REGWRITE_BUFFER(ah);
216 for (r = 0; r < array->ia_rows; r++) {
217 REG_WRITE(ah, INI_RA(array, r, 0),
218 INI_RA(array, r, column));
219 DO_DELAY(*writecnt);
220 }
221 REGWRITE_BUFFER_FLUSH(ah);
222}
223
f078f209
LR		 224u32 ath9k_hw_reverse_bits(u32 val, u32 n)
225{
226 u32 retval;
227 int i;
228
229 for (i = 0, retval = 0; i < n; i++) {
230 retval = (retval << 1) | (val & 1);
231 val >>= 1;
232 }
233 return retval;
234}
235
cbe61d8a 236u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 237 u8 phy, int kbps,
f1dc5600
S		 238 u32 frameLen, u16 rateix,
239 bool shortPreamble)
f078f209 240{
f1dc5600 241 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 242
f1dc5600
S		 243 if (kbps == 0)
244 return 0;
f078f209 245
545750d3 246 switch (phy) {
46d14a58 247 case WLAN_RC_PHY_CCK:
f1dc5600 248 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 249 if (shortPreamble)
f1dc5600
S		 250 phyTime >>= 1;
251 numBits = frameLen << 3;
252 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
253 break;
46d14a58 254 case WLAN_RC_PHY_OFDM:
2660b81a 255 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 256 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
257 numBits = OFDM_PLCP_BITS + (frameLen << 3);
258 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
259 txTime = OFDM_SIFS_TIME_QUARTER
260 + OFDM_PREAMBLE_TIME_QUARTER
261 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 262 } else if (ah->curchan &&
263 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
265 numBits = OFDM_PLCP_BITS + (frameLen << 3);
266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
267 txTime = OFDM_SIFS_TIME_HALF +
268 OFDM_PREAMBLE_TIME_HALF
269 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
270 } else {
271 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
272 numBits = OFDM_PLCP_BITS + (frameLen << 3);
273 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
274 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
275 + (numSymbols * OFDM_SYMBOL_TIME);
276 }
277 break;
278 default:
3800276a
JP		 279 ath_err(ath9k_hw_common(ah),
280 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 281 txTime = 0;
282 break;
283 }
f078f209 284
f1dc5600
S		 285 return txTime;
286}
7322fd19 287EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 288
cbe61d8a 289void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 290 struct ath9k_channel *chan,
291 struct chan_centers *centers)
f078f209 292{
f1dc5600 293 int8_t extoff;
f078f209 294
f1dc5600
S		 295 if (!IS_CHAN_HT40(chan)) {
296 centers->ctl_center = centers->ext_center =
297 centers->synth_center = chan->channel;
298 return;
f078f209 299 }
f078f209 300
f1dc5600
S		 301 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
302 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
303 centers->synth_center =
304 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
305 extoff = 1;
306 } else {
307 centers->synth_center =
308 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
309 extoff = -1;
310 }
f078f209 311
f1dc5600
S		 312 centers->ctl_center =
313 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 314 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 315 centers->ext_center =
6420014c 316 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 317}
318
f1dc5600
S		 319/******************/
320/* Chip Revisions */
321/******************/
322
cbe61d8a 323static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 324{
f1dc5600 325 u32 val;
f078f209 326
ecb1d385
VT		 327 switch (ah->hw_version.devid) {
328 case AR5416_AR9100_DEVID:
329 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
330 break;
3762561a
GJ		 331 case AR9300_DEVID_AR9330:
332 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
333 if (ah->get_mac_revision) {
334 ah->hw_version.macRev = ah->get_mac_revision();
335 } else {
336 val = REG_READ(ah, AR_SREV);
337 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
338 }
339 return;
ecb1d385
VT		 340 case AR9300_DEVID_AR9340:
341 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
342 val = REG_READ(ah, AR_SREV);
343 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
344 return;
345 }
346
f1dc5600 347 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 348
f1dc5600
S		 349 if (val == 0xFF) {
350 val = REG_READ(ah, AR_SREV);
d535a42a
S		 351 ah->hw_version.macVersion =
352 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
353 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 354
423e38e8 355 if (AR_SREV_9462(ah))
76ed94be
MSS		 356 ah->is_pciexpress = true;
357 else
358 ah->is_pciexpress = (val &
359 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 360 } else {
361 if (!AR_SREV_9100(ah))
d535a42a 362 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 363
d535a42a 364 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 365
d535a42a 366 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 367 ah->is_pciexpress = true;
f1dc5600 368 }
f078f209
LR		 369}
370
f1dc5600
S		 371/************************************/
372/* HW Attach, Detach, Init Routines */
373/************************************/
374
cbe61d8a 375static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 376{
040b74f7 377 if (!AR_SREV_5416(ah))
f1dc5600 378 return;
f078f209 379
f1dc5600
S		 380 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
384 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
385 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
386 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
387 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
388 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 389
f1dc5600 390 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 391}
392
1f3f0618 393/* This should work for all families including legacy */
cbe61d8a 394static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 395{
c46917bb 396 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 397 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 398 u32 regHold[2];
07b2fa5a
JP		 399 static const u32 patternData[4] = {
400 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
401 };
1f3f0618 402 int i, j, loop_max;
f078f209 403
1f3f0618
SB		 404 if (!AR_SREV_9300_20_OR_LATER(ah)) {
405 loop_max = 2;
406 regAddr[1] = AR_PHY_BASE + (8 << 2);
407 } else
408 loop_max = 1;
409
410 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 411 u32 addr = regAddr[i];
412 u32 wrData, rdData;
f078f209 413
f1dc5600
S		 414 regHold[i] = REG_READ(ah, addr);
415 for (j = 0; j < 0x100; j++) {
416 wrData = (j << 16) | j;
417 REG_WRITE(ah, addr, wrData);
418 rdData = REG_READ(ah, addr);
419 if (rdData != wrData) {
3800276a
JP		 420 ath_err(common,
421 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
422 addr, wrData, rdData);
f1dc5600
S		 423 return false;
424 }
425 }
426 for (j = 0; j < 4; j++) {
427 wrData = patternData[j];
428 REG_WRITE(ah, addr, wrData);
429 rdData = REG_READ(ah, addr);
430 if (wrData != rdData) {
3800276a
JP		 431 ath_err(common,
432 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
433 addr, wrData, rdData);
f1dc5600
S		 434 return false;
435 }
f078f209 436 }
f1dc5600 437 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 438 }
f1dc5600 439 udelay(100);
cbe61d8a 440
f078f209
LR		 441 return true;
442}
443
b8b0f377 444static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 445{
446 int i;
f078f209 447
689e756f
FF		 448 ah->config.dma_beacon_response_time = 1;
449 ah->config.sw_beacon_response_time = 6;
2660b81a
S		 450 ah->config.additional_swba_backoff = 0;
451 ah->config.ack_6mb = 0x0;
452 ah->config.cwm_ignore_extcca = 0;
2660b81a 453 ah->config.pcie_clock_req = 0;
2660b81a
S		 454 ah->config.pcie_waen = 0;
455 ah->config.analog_shiftreg = 1;
03c72518 456 ah->config.enable_ani = true;
f078f209 457
f1dc5600 458 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 459 ah->config.spurchans[i][0] = AR_NO_SPUR;
460 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 461 }
462
6f481010
LR		 463 /* PAPRD needs some more work to be enabled */
464 ah->config.paprd_disable = 1;
465
0ce024cb 466 ah->config.rx_intr_mitigation = true;
6a0ec30a 467 ah->config.pcieSerDesWrite = true;
6158425b
LR		 468
469 /*
470 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
471 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
472 * This means we use it for all AR5416 devices, and the few
473 * minor PCI AR9280 devices out there.
474 *
475 * Serialization is required because these devices do not handle
476 * well the case of two concurrent reads/writes due to the latency
477 * involved. During one read/write another read/write can be issued
478 * on another CPU while the previous read/write may still be working
479 * on our hardware, if we hit this case the hardware poops in a loop.
480 * We prevent this by serializing reads and writes.
481 *
482 * This issue is not present on PCI-Express devices or pre-AR5416
483 * devices (legacy, 802.11abg).
484 */
485 if (num_possible_cpus() > 1)
2d6a5e95 486 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 487}
488
50aca25b 489static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 490{
608b88cb
LR		 491 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
492
493 regulatory->country_code = CTRY_DEFAULT;
494 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 495
d535a42a 496 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 497 ah->hw_version.subvendorid = 0;
f078f209 498
2660b81a 499 ah->atim_window = 0;
16f2411f
FF		 500 ah->sta_id1_defaults =
501 AR_STA_ID1_CRPT_MIC_ENABLE |
502 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 503 if (AR_SREV_9100(ah))
504 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
e3f2acc7 505 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 506 ah->globaltxtimeout = (u32) -1;
cbdec975 507 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 508 ah->htc_reset_init = true;
f078f209
LR		 509}
510
cbe61d8a 511static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 512{
1510718d 513 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 514 u32 sum;
515 int i;
516 u16 eeval;
07b2fa5a 517 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 518
519 sum = 0;
520 for (i = 0; i < 3; i++) {
49101676 521 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 522 sum += eeval;
1510718d
LR		 523 common->macaddr[2 * i] = eeval >> 8;
524 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 525 }
d8baa939 526 if (sum == 0 || sum == 0xffff * 3)
f078f209 527 return -EADDRNOTAVAIL;
f078f209
LR		 528
529 return 0;
530}
531
f637cfd6 532static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 533{
6cae913d 534 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 535 int ecode;
f078f209 536
6cae913d 537 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 538 if (!ath9k_hw_chip_test(ah))
539 return -ENODEV;
540 }
f078f209 541
ebd5a14a
LR		 542 if (!AR_SREV_9300_20_OR_LATER(ah)) {
543 ecode = ar9002_hw_rf_claim(ah);
544 if (ecode != 0)
545 return ecode;
546 }
f078f209 547
f637cfd6 548 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 549 if (ecode != 0)
550 return ecode;
7d01b221 551
d2182b69 552 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 553 ah->eep_ops->get_eeprom_ver(ah),
554 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 555
8fe65368
LR		 556 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
557 if (ecode) {
3800276a
JP		 558 ath_err(ath9k_hw_common(ah),
559 "Failed allocating banks for external radio\n");
48a7c3df 560 ath9k_hw_rf_free_ext_banks(ah);
8fe65368 561 return ecode;
574d6b12 562 }
f078f209 563
4279425c 564 if (ah->config.enable_ani) {
f1dc5600 565 ath9k_hw_ani_setup(ah);
f637cfd6 566 ath9k_hw_ani_init(ah);
f078f209
LR		 567 }
568
f078f209
LR		 569 return 0;
570}
571
8525f280 572static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 573{
8525f280
LR		 574 if (AR_SREV_9300_20_OR_LATER(ah))
575 ar9003_hw_attach_ops(ah);
576 else
577 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 578}
579
d70357d5
LR		 580/* Called for all hardware families */
581static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 582{
c46917bb 583 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 584 int r = 0;
aa4058ae 585
ac45c12d
SB		 586 ath9k_hw_read_revisions(ah);
587
0a8d7cb0
SB		 588 /*
589 * Read back AR_WA into a permanent copy and set bits 14 and 17.
590 * We need to do this to avoid RMW of this register. We cannot
591 * read the reg when chip is asleep.
592 */
593 ah->WARegVal = REG_READ(ah, AR_WA);
594 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
595 AR_WA_ASPM_TIMER_BASED_DISABLE);
596
aa4058ae 597 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 598 ath_err(common, "Couldn't reset chip\n");
95fafca2 599 return -EIO;
aa4058ae
LR		 600 }
601
423e38e8 602 if (AR_SREV_9462(ah))
eec353c5
RM		 603 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
604
bab1f62e
LR		 605 ath9k_hw_init_defaults(ah);
606 ath9k_hw_init_config(ah);
607
8525f280 608 ath9k_hw_attach_ops(ah);
d70357d5 609
9ecdef4b 610 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 611 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 612 return -EIO;
aa4058ae
LR		 613 }
614
f3eef645 615 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
aa4058ae 616 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
4c85ab11
JL		 617 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
618 !ah->is_pciexpress)) {
aa4058ae
LR		 619 ah->config.serialize_regmode =
620 SER_REG_MODE_ON;
621 } else {
622 ah->config.serialize_regmode =
623 SER_REG_MODE_OFF;
624 }
625 }
626
d2182b69 627 ath_dbg(common, RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 628 ah->config.serialize_regmode);
629
f4709fdf
LR		 630 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
631 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
632 else
633 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
634
6da5a720
FF		 635 switch (ah->hw_version.macVersion) {
636 case AR_SREV_VERSION_5416_PCI:
637 case AR_SREV_VERSION_5416_PCIE:
638 case AR_SREV_VERSION_9160:
639 case AR_SREV_VERSION_9100:
640 case AR_SREV_VERSION_9280:
641 case AR_SREV_VERSION_9285:
642 case AR_SREV_VERSION_9287:
643 case AR_SREV_VERSION_9271:
644 case AR_SREV_VERSION_9300:
2c8e5937 645 case AR_SREV_VERSION_9330:
6da5a720 646 case AR_SREV_VERSION_9485:
bca04689 647 case AR_SREV_VERSION_9340:
423e38e8 648 case AR_SREV_VERSION_9462:
6da5a720
FF		 649 break;
650 default:
3800276a
JP		 651 ath_err(common,
652 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
653 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 654 return -EOPNOTSUPP;
aa4058ae
LR		 655 }
656
2c8e5937
GJ		 657 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
658 AR_SREV_9330(ah))
d7e7d229
LR		 659 ah->is_pciexpress = false;
660
aa4058ae 661 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 662 ath9k_hw_init_cal_settings(ah);
663
664 ah->ani_function = ATH9K_ANI_ALL;
7a37081e 665 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 666 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 667 if (!AR_SREV_9300_20_OR_LATER(ah))
668 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae 669
4f17c48e
NM		 670 /* disable ANI for 9340 */
671 if (AR_SREV_9340(ah))
4279425c
NM		 672 ah->config.enable_ani = false;
673
aa4058ae
LR		 674 ath9k_hw_init_mode_regs(ah);
675
69ce674b 676 if (!ah->is_pciexpress)
aa4058ae
LR		 677 ath9k_hw_disablepcie(ah);
678
f637cfd6 679 r = ath9k_hw_post_init(ah);
aa4058ae 680 if (r)
95fafca2 681 return r;
aa4058ae
LR		 682
683 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 684 r = ath9k_hw_fill_cap_info(ah);
685 if (r)
686 return r;
687
4f3acf81
LR		 688 r = ath9k_hw_init_macaddr(ah);
689 if (r) {
3800276a 690 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 691 return r;
f078f209
LR		 692 }
693
d7e7d229 694 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 695 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 696 else
2660b81a 697 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 698
88e641df
GJ		 699 if (AR_SREV_9330(ah))
700 ah->bb_watchdog_timeout_ms = 85;
701 else
702 ah->bb_watchdog_timeout_ms = 25;
f078f209 703
211f5859
LR		 704 common->state = ATH_HW_INITIALIZED;
705
4f3acf81 706 return 0;
f078f209
LR		 707}
708
d70357d5 709int ath9k_hw_init(struct ath_hw *ah)
f078f209 710{
d70357d5
LR		 711 int ret;
712 struct ath_common *common = ath9k_hw_common(ah);
f078f209 713
d70357d5
LR		 714 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
715 switch (ah->hw_version.devid) {
716 case AR5416_DEVID_PCI:
717 case AR5416_DEVID_PCIE:
718 case AR5416_AR9100_DEVID:
719 case AR9160_DEVID_PCI:
720 case AR9280_DEVID_PCI:
721 case AR9280_DEVID_PCIE:
722 case AR9285_DEVID_PCIE:
db3cc53a
SB		 723 case AR9287_DEVID_PCI:
724 case AR9287_DEVID_PCIE:
d70357d5 725 case AR2427_DEVID_PCIE:
db3cc53a 726 case AR9300_DEVID_PCIE:
3050c914 727 case AR9300_DEVID_AR9485_PCIE:
999a7a88 728 case AR9300_DEVID_AR9330:
bca04689 729 case AR9300_DEVID_AR9340:
5a63ef0f 730 case AR9300_DEVID_AR9580:
423e38e8 731 case AR9300_DEVID_AR9462:
d70357d5
LR		 732 break;
733 default:
734 if (common->bus_ops->ath_bus_type == ATH_USB)
735 break;
3800276a
JP		 736 ath_err(common, "Hardware device ID 0x%04x not supported\n",
737 ah->hw_version.devid);
d70357d5
LR		 738 return -EOPNOTSUPP;
739 }
f078f209 740
d70357d5
LR		 741 ret = __ath9k_hw_init(ah);
742 if (ret) {
3800276a
JP		 743 ath_err(common,
744 "Unable to initialize hardware; initialization status: %d\n",
745 ret);
d70357d5
LR		 746 return ret;
747 }
f078f209 748
d70357d5 749 return 0;
f078f209 750}
d70357d5 751EXPORT_SYMBOL(ath9k_hw_init);
f078f209 752
cbe61d8a 753static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 754{
7d0d0df0
S		 755 ENABLE_REGWRITE_BUFFER(ah);
756
f1dc5600
S		 757 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
758 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 759
f1dc5600
S		 760 REG_WRITE(ah, AR_QOS_NO_ACK,
761 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
762 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
763 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
764
765 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
766 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
767 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
768 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
769 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 770
771 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 772}
773
b84628eb 774u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 775{
ca7a4deb
FF		 776 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
777 udelay(100);
778 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 779
ca7a4deb
FF		 780 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
781 udelay(100);
b1415819 782
ca7a4deb 783 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 784}
785EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
786
cbe61d8a 787static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 788 struct ath9k_channel *chan)
f078f209 789{
d09b17f7
VT		 790 u32 pll;
791
22983c30 792 if (AR_SREV_9485(ah)) {
22983c30 793
3dfd7f60
VT		 794 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
795 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
796 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
797 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
798 AR_CH0_DPLL2_KD, 0x40);
799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
800 AR_CH0_DPLL2_KI, 0x4);
22983c30 801
3dfd7f60
VT		 802 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
803 AR_CH0_BB_DPLL1_REFDIV, 0x5);
804 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
805 AR_CH0_BB_DPLL1_NINI, 0x58);
806 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
807 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 808
809 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 810 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
811 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
812 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 814 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 815
3dfd7f60 816 /* program BB PLL phase_shift to 0x6 */
22983c30 817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 818 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
819
820 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
821 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 822 udelay(1000);
a5415d62
GJ		 823 } else if (AR_SREV_9330(ah)) {
824 u32 ddr_dpll2, pll_control2, kd;
825
826 if (ah->is_clk_25mhz) {
827 ddr_dpll2 = 0x18e82f01;
828 pll_control2 = 0xe04a3d;
829 kd = 0x1d;
830 } else {
831 ddr_dpll2 = 0x19e82f01;
832 pll_control2 = 0x886666;
833 kd = 0x3d;
834 }
835
836 /* program DDR PLL ki and kd value */
837 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
838
839 /* program DDR PLL phase_shift */
840 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
841 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
842
843 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
844 udelay(1000);
845
846 /* program refdiv, nint, frac to RTC register */
847 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
848
849 /* program BB PLL kd and ki value */
850 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
851 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
852
853 /* program BB PLL phase_shift */
854 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
855 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
0b488ac6
VT		 856 } else if (AR_SREV_9340(ah)) {
857 u32 regval, pll2_divint, pll2_divfrac, refdiv;
858
859 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
860 udelay(1000);
861
862 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
863 udelay(100);
864
865 if (ah->is_clk_25mhz) {
866 pll2_divint = 0x54;
867 pll2_divfrac = 0x1eb85;
868 refdiv = 3;
869 } else {
870 pll2_divint = 88;
871 pll2_divfrac = 0;
872 refdiv = 5;
873 }
874
875 regval = REG_READ(ah, AR_PHY_PLL_MODE);
876 regval |= (0x1 << 16);
877 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
878 udelay(100);
879
880 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
881 (pll2_divint << 18) | pll2_divfrac);
882 udelay(100);
883
884 regval = REG_READ(ah, AR_PHY_PLL_MODE);
885 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
886 (0x4 << 26) | (0x18 << 19);
887 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
888 REG_WRITE(ah, AR_PHY_PLL_MODE,
889 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
890 udelay(1000);
22983c30 891 }
d09b17f7
VT		 892
893 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 894
d03a66c1 895 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 896
a5415d62 897 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
3dfd7f60
VT		 898 udelay(1000);
899
c75724d1
LR		 900 /* Switch the core clock for ar9271 to 117Mhz */
901 if (AR_SREV_9271(ah)) {
25e2ab17
S		 902 udelay(500);
903 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 904 }
905
f1dc5600
S		 906 udelay(RTC_PLL_SETTLE_DELAY);
907
908 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6
VT		 909
910 if (AR_SREV_9340(ah)) {
911 if (ah->is_clk_25mhz) {
912 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
913 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
914 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
915 } else {
916 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
917 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
918 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
919 }
920 udelay(100);
921 }
f078f209
LR		 922}
923
cbe61d8a 924static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 925 enum nl80211_iftype opmode)
f078f209 926{
79d1d2b8 927 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 928 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 929 AR_IMR_TXURN |
930 AR_IMR_RXERR |
931 AR_IMR_RXORN |
932 AR_IMR_BCNMISC;
f078f209 933
79d1d2b8
VT		 934 if (AR_SREV_9340(ah))
935 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
936
66860240
VT		 937 if (AR_SREV_9300_20_OR_LATER(ah)) {
938 imr_reg |= AR_IMR_RXOK_HP;
939 if (ah->config.rx_intr_mitigation)
940 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
941 else
942 imr_reg |= AR_IMR_RXOK_LP;
f078f209 943
66860240
VT		 944 } else {
945 if (ah->config.rx_intr_mitigation)
946 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
947 else
948 imr_reg |= AR_IMR_RXOK;
949 }
f078f209 950
66860240
VT		 951 if (ah->config.tx_intr_mitigation)
952 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
953 else
954 imr_reg |= AR_IMR_TXOK;
f078f209 955
d97809db 956 if (opmode == NL80211_IFTYPE_AP)
152d530d 957 imr_reg |= AR_IMR_MIB;
f078f209 958
7d0d0df0
S		 959 ENABLE_REGWRITE_BUFFER(ah);
960
152d530d 961 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 962 ah->imrs2_reg |= AR_IMR_S2_GTT;
963 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 964
f1dc5600
S		 965 if (!AR_SREV_9100(ah)) {
966 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 967 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 968 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
969 }
66860240 970
7d0d0df0 971 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 972
66860240
VT		 973 if (AR_SREV_9300_20_OR_LATER(ah)) {
974 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
975 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
976 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
977 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
978 }
f078f209
LR		 979}
980
b6ba41bb
FF		 981static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
982{
983 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
984 val = min(val, (u32) 0xFFFF);
985 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
986}
987
0005baf4 988static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 989{
0005baf4
FF		 990 u32 val = ath9k_hw_mac_to_clks(ah, us);
991 val = min(val, (u32) 0xFFFF);
992 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 993}
994
0005baf4 995static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 996{
0005baf4
FF		 997 u32 val = ath9k_hw_mac_to_clks(ah, us);
998 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
999 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1000}
1001
1002static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1003{
1004 u32 val = ath9k_hw_mac_to_clks(ah, us);
1005 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1006 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 1007}
f1dc5600 1008
cbe61d8a 1009static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1010{
f078f209 1011 if (tu > 0xFFFF) {
d2182b69
JP		 1012 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1013 tu);
2660b81a 1014 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1015 return false;
1016 } else {
1017 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1018 ah->globaltxtimeout = tu;
f078f209
LR		 1019 return true;
1020 }
1021}
1022
0005baf4 1023void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1024{
b6ba41bb
FF		 1025 struct ath_common *common = ath9k_hw_common(ah);
1026 struct ieee80211_conf *conf = &common->hw->conf;
1027 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 1028 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 1029 int slottime;
0005baf4 1030 int sifstime;
b6ba41bb
FF		 1031 int rx_lat = 0, tx_lat = 0, eifs = 0;
1032 u32 reg;
0005baf4 1033
d2182b69 1034 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1035 ah->misc_mode);
f078f209 1036
b6ba41bb
FF		 1037 if (!chan)
1038 return;
1039
2660b81a 1040 if (ah->misc_mode != 0)
ca7a4deb 1041 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1042
81a91d57
RM		 1043 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1044 rx_lat = 41;
1045 else
1046 rx_lat = 37;
b6ba41bb
FF		 1047 tx_lat = 54;
1048
e88e4861
FF		 1049 if (IS_CHAN_5GHZ(chan))
1050 sifstime = 16;
1051 else
1052 sifstime = 10;
1053
b6ba41bb
FF		 1054 if (IS_CHAN_HALF_RATE(chan)) {
1055 eifs = 175;
1056 rx_lat *= 2;
1057 tx_lat *= 2;
1058 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1059 tx_lat += 11;
1060
e88e4861 1061 sifstime *= 2;
e115b7ec 1062 ack_offset = 16;
b6ba41bb 1063 slottime = 13;
b6ba41bb
FF		 1064 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1065 eifs = 340;
81a91d57 1066 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1067 tx_lat *= 4;
1068 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1069 tx_lat += 22;
1070
e88e4861 1071 sifstime *= 4;
e115b7ec 1072 ack_offset = 32;
b6ba41bb 1073 slottime = 21;
b6ba41bb 1074 } else {
a7be039d
RM		 1075 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1076 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1077 reg = AR_USEC_ASYNC_FIFO;
1078 } else {
1079 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1080 common->clockrate;
1081 reg = REG_READ(ah, AR_USEC);
1082 }
b6ba41bb
FF		 1083 rx_lat = MS(reg, AR_USEC_RX_LAT);
1084 tx_lat = MS(reg, AR_USEC_TX_LAT);
1085
1086 slottime = ah->slottime;
b6ba41bb 1087 }
0005baf4 1088
e239d859 1089 /* As defined by IEEE 802.11-2007 17.3.8.6 */
e115b7ec 1090 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset;
adb5066a 1091 ctstimeout = acktimeout;
42c4568a
FF		 1092
1093 /*
1094 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1095 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1096 * This was initially only meant to work around an issue with delayed
1097 * BA frames in some implementations, but it has been found to fix ACK
1098 * timeout issues in other cases as well.
1099 */
e115b7ec
FF		 1100 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ &&
1101 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1102 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1103 ctstimeout += 48 - sifstime - ah->slottime;
1104 }
1105
42c4568a 1106
b6ba41bb
FF		 1107 ath9k_hw_set_sifs_time(ah, sifstime);
1108 ath9k_hw_setslottime(ah, slottime);
0005baf4 1109 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1110 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1111 if (ah->globaltxtimeout != (u32) -1)
1112 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1113
1114 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1115 REG_RMW(ah, AR_USEC,
1116 (common->clockrate - 1) |
1117 SM(rx_lat, AR_USEC_RX_LAT) |
1118 SM(tx_lat, AR_USEC_TX_LAT),
1119 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1120
f1dc5600 1121}
0005baf4 1122EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1123
285f2dda 1124void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1125{
211f5859
LR		 1126 struct ath_common *common = ath9k_hw_common(ah);
1127
736b3a27 1128 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 1129 goto free_hw;
1130
9ecdef4b 1131 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 1132
1133free_hw:
8fe65368 1134 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 1135}
285f2dda 1136EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1137
f1dc5600
S		 1138/*******/
1139/* INI */
1140/*******/
1141
8fe65368 1142u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1143{
1144 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1145
1146 if (IS_CHAN_B(chan))
1147 ctl |= CTL_11B;
1148 else if (IS_CHAN_G(chan))
1149 ctl |= CTL_11G;
1150 else
1151 ctl |= CTL_11A;
1152
1153 return ctl;
1154}
1155
f1dc5600
S		 1156/****************************************/
1157/* Reset and Channel Switching Routines */
1158/****************************************/
f1dc5600 1159
cbe61d8a 1160static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1161{
57b32227 1162 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 1163
7d0d0df0
S		 1164 ENABLE_REGWRITE_BUFFER(ah);
1165
d7e7d229
LR		 1166 /*
1167 * set AHB_MODE not to do cacheline prefetches
1168 */
ca7a4deb
FF		 1169 if (!AR_SREV_9300_20_OR_LATER(ah))
1170 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1171
d7e7d229
LR		 1172 /*
1173 * let mac dma reads be in 128 byte chunks
1174 */
ca7a4deb 1175 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1176
7d0d0df0 1177 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1178
d7e7d229
LR		 1179 /*
1180 * Restore TX Trigger Level to its pre-reset value.
1181 * The initial value depends on whether aggregation is enabled, and is
1182 * adjusted whenever underruns are detected.
1183 */
57b32227
FF		 1184 if (!AR_SREV_9300_20_OR_LATER(ah))
1185 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1186
7d0d0df0 1187 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1188
d7e7d229
LR		 1189 /*
1190 * let mac dma writes be in 128 byte chunks
1191 */
ca7a4deb 1192 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1193
d7e7d229
LR		 1194 /*
1195 * Setup receive FIFO threshold to hold off TX activities
1196 */
f1dc5600
S		 1197 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1198
57b32227
FF		 1199 if (AR_SREV_9300_20_OR_LATER(ah)) {
1200 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1201 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1202
1203 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1204 ah->caps.rx_status_len);
1205 }
1206
d7e7d229
LR		 1207 /*
1208 * reduce the number of usable entries in PCU TXBUF to avoid
1209 * wrap around issues.
1210 */
f1dc5600 1211 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1212 /* For AR9285 the number of Fifos are reduced to half.
1213 * So set the usable tx buf size also to half to
1214 * avoid data/delimiter underruns
1215 */
f1dc5600
S		 1216 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1217 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1218 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1219 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1220 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1221 }
744d4025 1222
7d0d0df0 1223 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1224
744d4025
VT		 1225 if (AR_SREV_9300_20_OR_LATER(ah))
1226 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1227}
1228
cbe61d8a 1229static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1230{
ca7a4deb
FF		 1231 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1232 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1233
f1dc5600 1234 switch (opmode) {
d97809db 1235 case NL80211_IFTYPE_ADHOC:
9cb5412b 1236 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb 1237 set |= AR_STA_ID1_ADHOC;
f1dc5600 1238 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1239 break;
ca7a4deb
FF		 1240 case NL80211_IFTYPE_AP:
1241 set |= AR_STA_ID1_STA_AP;
1242 /* fall through */
d97809db 1243 case NL80211_IFTYPE_STATION:
ca7a4deb 1244 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1245 break;
5f841b41 1246 default:
ca7a4deb
FF		 1247 if (!ah->is_monitoring)
1248 set = 0;
5f841b41 1249 break;
f1dc5600 1250 }
ca7a4deb 1251 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1252}
1253
8fe65368
LR		 1254void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1255 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1256{
1257 u32 coef_exp, coef_man;
1258
1259 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1260 if ((coef_scaled >> coef_exp) & 0x1)
1261 break;
1262
1263 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1264
1265 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1266
1267 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1268 *coef_exponent = coef_exp - 16;
1269}
1270
cbe61d8a 1271static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1272{
1273 u32 rst_flags;
1274 u32 tmpReg;
1275
70768496 1276 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1277 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1278 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1279 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1280 }
1281
7d0d0df0
S		 1282 ENABLE_REGWRITE_BUFFER(ah);
1283
9a658d2b
LR		 1284 if (AR_SREV_9300_20_OR_LATER(ah)) {
1285 REG_WRITE(ah, AR_WA, ah->WARegVal);
1286 udelay(10);
1287 }
1288
f1dc5600
S		 1289 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1290 AR_RTC_FORCE_WAKE_ON_INT);
1291
1292 if (AR_SREV_9100(ah)) {
1293 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1294 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1295 } else {
1296 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1297 if (tmpReg &
1298 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1299 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1300 u32 val;
f1dc5600 1301 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1302
1303 val = AR_RC_HOSTIF;
1304 if (!AR_SREV_9300_20_OR_LATER(ah))
1305 val |= AR_RC_AHB;
1306 REG_WRITE(ah, AR_RC, val);
1307
1308 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1309 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1310
1311 rst_flags = AR_RTC_RC_MAC_WARM;
1312 if (type == ATH9K_RESET_COLD)
1313 rst_flags |= AR_RTC_RC_MAC_COLD;
1314 }
1315
7d95847c
GJ		 1316 if (AR_SREV_9330(ah)) {
1317 int npend = 0;
1318 int i;
1319
1320 /* AR9330 WAR:
1321 * call external reset function to reset WMAC if:
1322 * - doing a cold reset
1323 * - we have pending frames in the TX queues
1324 */
1325
1326 for (i = 0; i < AR_NUM_QCU; i++) {
1327 npend = ath9k_hw_numtxpending(ah, i);
1328 if (npend)
1329 break;
1330 }
1331
1332 if (ah->external_reset &&
1333 (npend || type == ATH9K_RESET_COLD)) {
1334 int reset_err = 0;
1335
d2182b69 1336 ath_dbg(ath9k_hw_common(ah), RESET,
7d95847c
GJ		 1337 "reset MAC via external reset\n");
1338
1339 reset_err = ah->external_reset();
1340 if (reset_err) {
1341 ath_err(ath9k_hw_common(ah),
1342 "External reset failed, err=%d\n",
1343 reset_err);
1344 return false;
1345 }
1346
1347 REG_WRITE(ah, AR_RTC_RESET, 1);
1348 }
1349 }
1350
3863495b
RM		 1351 if (ath9k_hw_mci_is_enabled(ah))
1352 ar9003_mci_state(ah, MCI_STATE_CHECK_GPM_OFFSET, NULL);
1353
d03a66c1 1354 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1355
1356 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1357
f1dc5600
S		 1358 udelay(50);
1359
d03a66c1 1360 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1361 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1362 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1363 return false;
1364 }
1365
1366 if (!AR_SREV_9100(ah))
1367 REG_WRITE(ah, AR_RC, 0);
1368
f1dc5600
S		 1369 if (AR_SREV_9100(ah))
1370 udelay(50);
1371
1372 return true;
1373}
1374
cbe61d8a 1375static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1376{
7d0d0df0
S		 1377 ENABLE_REGWRITE_BUFFER(ah);
1378
9a658d2b
LR		 1379 if (AR_SREV_9300_20_OR_LATER(ah)) {
1380 REG_WRITE(ah, AR_WA, ah->WARegVal);
1381 udelay(10);
1382 }
1383
f1dc5600
S		 1384 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1385 AR_RTC_FORCE_WAKE_ON_INT);
1386
42d5bc3f 1387 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1388 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1389
d03a66c1 1390 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1391
7d0d0df0 1392 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1393
84e2169b
SB		 1394 if (!AR_SREV_9300_20_OR_LATER(ah))
1395 udelay(2);
1396
1397 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1398 REG_WRITE(ah, AR_RC, 0);
1399
d03a66c1 1400 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1401
1402 if (!ath9k_hw_wait(ah,
1403 AR_RTC_STATUS,
1404 AR_RTC_STATUS_M,
0caa7b14
S		 1405 AR_RTC_STATUS_ON,
1406 AH_WAIT_TIMEOUT)) {
d2182b69 1407 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1408 return false;
f078f209
LR		 1409 }
1410
f1dc5600
S		 1411 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1412}
1413
cbe61d8a 1414static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1415{
7a9233ff 1416 bool ret = false;
2577c6e8 1417
9a658d2b
LR		 1418 if (AR_SREV_9300_20_OR_LATER(ah)) {
1419 REG_WRITE(ah, AR_WA, ah->WARegVal);
1420 udelay(10);
1421 }
1422
f1dc5600
S		 1423 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1424 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1425
1426 switch (type) {
1427 case ATH9K_RESET_POWER_ON:
7a9233ff
MSS		 1428 ret = ath9k_hw_set_reset_power_on(ah);
1429 break;
f1dc5600
S		 1430 case ATH9K_RESET_WARM:
1431 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1432 ret = ath9k_hw_set_reset(ah, type);
1433 break;
f1dc5600 1434 default:
7a9233ff 1435 break;
f1dc5600 1436 }
7a9233ff 1437
7a9233ff 1438 return ret;
f078f209
LR		 1439}
1440
cbe61d8a 1441static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1442 struct ath9k_channel *chan)
f078f209 1443{
9c083af8
FF		 1444 int reset_type = ATH9K_RESET_WARM;
1445
1446 if (AR_SREV_9280(ah)) {
1447 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1448 reset_type = ATH9K_RESET_POWER_ON;
1449 else
1450 reset_type = ATH9K_RESET_COLD;
1451 }
1452
1453 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1454 return false;
f078f209 1455
9ecdef4b 1456 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1457 return false;
f078f209 1458
2660b81a 1459 ah->chip_fullsleep = false;
bfc441a4
FF		 1460
1461 if (AR_SREV_9330(ah))
1462 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1463 ath9k_hw_init_pll(ah, chan);
f1dc5600 1464 ath9k_hw_set_rfmode(ah, chan);
f078f209 1465
f1dc5600 1466 return true;
f078f209
LR		 1467}
1468
cbe61d8a 1469static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1470 struct ath9k_channel *chan)
f078f209 1471{
c46917bb 1472 struct ath_common *common = ath9k_hw_common(ah);
8fe65368 1473 u32 qnum;
0a3b7bac 1474 int r;
5f0c04ea
RM		 1475 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1476 bool band_switch, mode_diff;
1477 u8 ini_reloaded;
1478
1479 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1480 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1481 CHANNEL_5GHZ));
1482 mode_diff = (chan->chanmode != ah->curchan->chanmode);
f078f209
LR		 1483
1484 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1485 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1486 ath_dbg(common, QUEUE,
226afe68 1487 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1488 return false;
1489 }
1490 }
1491
8fe65368 1492 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1493 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1494 return false;
1495 }
1496
5f0c04ea
RM		 1497 if (edma && (band_switch || mode_diff)) {
1498 ath9k_hw_mark_phy_inactive(ah);
1499 udelay(5);
1500
1501 ath9k_hw_init_pll(ah, NULL);
1502
1503 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1504 ath_err(common, "Failed to do fast channel change\n");
1505 return false;
1506 }
1507 }
1508
8fe65368 1509 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1510
8fe65368 1511 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1512 if (r) {
3800276a 1513 ath_err(common, "Failed to set channel\n");
0a3b7bac 1514 return false;
f078f209 1515 }
dfdac8ac 1516 ath9k_hw_set_clockrate(ah);
64ea57d0 1517 ath9k_hw_apply_txpower(ah, chan, false);
8fe65368 1518 ath9k_hw_rfbus_done(ah);
f078f209 1519
f1dc5600
S		 1520 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1521 ath9k_hw_set_delta_slope(ah, chan);
1522
8fe65368 1523 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1524
5f0c04ea 1525 if (edma && (band_switch || mode_diff)) {
a126ff51 1526 ah->ah_flags |= AH_FASTCC;
5f0c04ea
RM		 1527 if (band_switch || ini_reloaded)
1528 ah->eep_ops->set_board_values(ah, chan);
1529
1530 ath9k_hw_init_bb(ah, chan);
1531
1532 if (band_switch || ini_reloaded)
1533 ath9k_hw_init_cal(ah, chan);
a126ff51 1534 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1535 }
1536
f1dc5600
S		 1537 return true;
1538}
1539
691680b8
FF		 1540static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1541{
1542 u32 gpio_mask = ah->gpio_mask;
1543 int i;
1544
1545 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1546 if (!(gpio_mask & 1))
1547 continue;
1548
1549 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1550 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1551 }
1552}
1553
01e18918
RM		 1554static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1555 int *hang_state, int *hang_pos)
1556{
1557 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1558 u32 chain_state, dcs_pos, i;
1559
1560 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1561 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1562 for (i = 0; i < 3; i++) {
1563 if (chain_state == dcu_chain_state[i]) {
1564 *hang_state = chain_state;
1565 *hang_pos = dcs_pos;
1566 return true;
1567 }
1568 }
1569 }
1570 return false;
1571}
1572
1573#define DCU_COMPLETE_STATE 1
1574#define DCU_COMPLETE_STATE_MASK 0x3
1575#define NUM_STATUS_READS 50
1576static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1577{
1578 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1579 u32 i, hang_pos, hang_state, num_state = 6;
1580
1581 comp_state = REG_READ(ah, AR_DMADBG_6);
1582
1583 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1584 ath_dbg(ath9k_hw_common(ah), RESET,
1585 "MAC Hang signature not found at DCU complete\n");
1586 return false;
1587 }
1588
1589 chain_state = REG_READ(ah, dcs_reg);
1590 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1591 goto hang_check_iter;
1592
1593 dcs_reg = AR_DMADBG_5;
1594 num_state = 4;
1595 chain_state = REG_READ(ah, dcs_reg);
1596 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1597 goto hang_check_iter;
1598
1599 ath_dbg(ath9k_hw_common(ah), RESET,
1600 "MAC Hang signature 1 not found\n");
1601 return false;
1602
1603hang_check_iter:
1604 ath_dbg(ath9k_hw_common(ah), RESET,
1605 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1606 chain_state, comp_state, hang_state, hang_pos);
1607
1608 for (i = 0; i < NUM_STATUS_READS; i++) {
1609 chain_state = REG_READ(ah, dcs_reg);
1610 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1611 comp_state = REG_READ(ah, AR_DMADBG_6);
1612
1613 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1614 DCU_COMPLETE_STATE) ||
1615 (chain_state != hang_state))
1616 return false;
1617 }
1618
1619 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1620
1621 return true;
1622}
1623
c9c99e5e 1624bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1625{
c9c99e5e
FF		 1626 int count = 50;
1627 u32 reg;
1628
01e18918
RM		 1629 if (AR_SREV_9300(ah))
1630 return !ath9k_hw_detect_mac_hang(ah);
1631
e17f83ea 1632 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1633 return true;
1634
1635 do {
1636 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1637
c9c99e5e
FF		 1638 if ((reg & 0x7E7FFFEF) == 0x00702400)
1639 continue;
1640
1641 switch (reg & 0x7E000B00) {
1642 case 0x1E000000:
1643 case 0x52000B00:
1644 case 0x18000B00:
1645 continue;
1646 default:
1647 return true;
1648 }
1649 } while (count-- > 0);
3b319aae 1650
c9c99e5e 1651 return false;
3b319aae 1652}
c9c99e5e 1653EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1654
caed6579
SM		 1655/*
1656 * Fast channel change:
1657 * (Change synthesizer based on channel freq without resetting chip)
1658 *
1659 * Don't do FCC when
1660 * - Flag is not set
1661 * - Chip is just coming out of full sleep
1662 * - Channel to be set is same as current channel
1663 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1664 */
1665static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1666{
1667 struct ath_common *common = ath9k_hw_common(ah);
1668 int ret;
1669
1670 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1671 goto fail;
1672
1673 if (ah->chip_fullsleep)
1674 goto fail;
1675
1676 if (!ah->curchan)
1677 goto fail;
1678
1679 if (chan->channel == ah->curchan->channel)
1680 goto fail;
1681
feb7bc99
FF		 1682 if ((ah->curchan->channelFlags | chan->channelFlags) &
1683 (CHANNEL_HALF | CHANNEL_QUARTER))
1684 goto fail;
1685
caed6579
SM		 1686 if ((chan->channelFlags & CHANNEL_ALL) !=
1687 (ah->curchan->channelFlags & CHANNEL_ALL))
1688 goto fail;
1689
1690 if (!ath9k_hw_check_alive(ah))
1691 goto fail;
1692
1693 /*
1694 * For AR9462, make sure that calibration data for
1695 * re-using are present.
1696 */
8a90555f
SM		 1697 if (AR_SREV_9462(ah) && (ah->caldata &&
1698 (!ah->caldata->done_txiqcal_once ||
1699 !ah->caldata->done_txclcal_once ||
1700 !ah->caldata->rtt_done)))
caed6579
SM		 1701 goto fail;
1702
1703 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1704 ah->curchan->channel, chan->channel);
1705
1706 ret = ath9k_hw_channel_change(ah, chan);
1707 if (!ret)
1708 goto fail;
1709
1710 ath9k_hw_loadnf(ah, ah->curchan);
1711 ath9k_hw_start_nfcal(ah, true);
1712
5955b2b0 1713 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1714 ar9003_mci_2g5g_switch(ah, false);
caed6579
SM		 1715
1716 if (AR_SREV_9271(ah))
1717 ar9002_hw_load_ani_reg(ah, chan);
1718
1719 return 0;
1720fail:
1721 return -EINVAL;
1722}
1723
cbe61d8a 1724int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1725 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1726{
1510718d 1727 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1728 u32 saveLedState;
f078f209
LR		 1729 u32 saveDefAntenna;
1730 u32 macStaId1;
46fe782c 1731 u64 tsf = 0;
8fe65368 1732 int i, r;
caed6579 1733 bool start_mci_reset = false;
63d32967
MSS		 1734 bool save_fullsleep = ah->chip_fullsleep;
1735
5955b2b0 1736 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1737 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1738 if (start_mci_reset)
1739 return 0;
63d32967
MSS		 1740 }
1741
9ecdef4b 1742 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1743 return -EIO;
f078f209 1744
caed6579
SM		 1745 if (ah->curchan && !ah->chip_fullsleep)
1746 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1747
20bd2a09
FF		 1748 ah->caldata = caldata;
1749 if (caldata &&
1750 (chan->channel != caldata->channel ||
1751 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1752 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1753 /* Operating channel changed, reset channel calibration data */
1754 memset(caldata, 0, sizeof(*caldata));
1755 ath9k_init_nfcal_hist_buffer(ah, chan);
1756 }
f23fba49 1757 ah->noise = ath9k_hw_getchan_noise(ah, chan);
20bd2a09 1758
caed6579
SM		 1759 if (fastcc) {
1760 r = ath9k_hw_do_fastcc(ah, chan);
1761 if (!r)
1762 return r;
f078f209
LR		 1763 }
1764
5955b2b0 1765 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1766 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1767
f078f209
LR		 1768 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1769 if (saveDefAntenna == 0)
1770 saveDefAntenna = 1;
1771
1772 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1773
46fe782c 1774 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1775 if (AR_SREV_9100(ah) ||
1776 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1777 tsf = ath9k_hw_gettsf64(ah);
1778
f078f209
LR		 1779 saveLedState = REG_READ(ah, AR_CFG_LED) &
1780 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1781 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1782
1783 ath9k_hw_mark_phy_inactive(ah);
1784
45ef6a0b
VT		 1785 ah->paprd_table_write_done = false;
1786
05020d23 1787 /* Only required on the first reset */
d7e7d229
LR		 1788 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1789 REG_WRITE(ah,
1790 AR9271_RESET_POWER_DOWN_CONTROL,
1791 AR9271_RADIO_RF_RST);
1792 udelay(50);
1793 }
1794
f078f209 1795 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1796 ath_err(common, "Chip reset failed\n");
ae8d2858 1797 return -EINVAL;
f078f209
LR		 1798 }
1799
05020d23 1800 /* Only required on the first reset */
d7e7d229
LR		 1801 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1802 ah->htc_reset_init = false;
1803 REG_WRITE(ah,
1804 AR9271_RESET_POWER_DOWN_CONTROL,
1805 AR9271_GATE_MAC_CTL);
1806 udelay(50);
1807 }
1808
46fe782c 1809 /* Restore TSF */
f860d526 1810 if (tsf)
46fe782c
S		 1811 ath9k_hw_settsf64(ah, tsf);
1812
7a37081e 1813 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1814 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1815
e9141f71
S		 1816 if (!AR_SREV_9300_20_OR_LATER(ah))
1817 ar9002_hw_enable_async_fifo(ah);
1818
25c56eec 1819 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1820 if (r)
1821 return r;
f078f209 1822
5955b2b0 1823 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1824 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1825
f860d526
FF		 1826 /*
1827 * Some AR91xx SoC devices frequently fail to accept TSF writes
1828 * right after the chip reset. When that happens, write a new
1829 * value after the initvals have been applied, with an offset
1830 * based on measured time difference
1831 */
1832 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1833 tsf += 1500;
1834 ath9k_hw_settsf64(ah, tsf);
1835 }
1836
0ced0e17
JM		 1837 /* Setup MFP options for CCMP */
1838 if (AR_SREV_9280_20_OR_LATER(ah)) {
1839 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1840 * frames when constructing CCMP AAD. */
1841 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1842 0xc7ff);
1843 ah->sw_mgmt_crypto = false;
1844 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1845 /* Disable hardware crypto for management frames */
1846 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1847 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1848 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1849 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1850 ah->sw_mgmt_crypto = true;
1851 } else
1852 ah->sw_mgmt_crypto = true;
1853
f078f209
LR		 1854 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1855 ath9k_hw_set_delta_slope(ah, chan);
1856
8fe65368 1857 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1858 ah->eep_ops->set_board_values(ah, chan);
a7765828 1859
7d0d0df0
S		 1860 ENABLE_REGWRITE_BUFFER(ah);
1861
1510718d
LR		 1862 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1863 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1864 | macStaId1
1865 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1866 | (ah->config.
60b67f51 1867 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1868 | ah->sta_id1_defaults);
13b81559 1869 ath_hw_setbssidmask(common);
f078f209 1870 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1871 ath9k_hw_write_associd(ah);
f078f209 1872 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1873 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1874
7d0d0df0 1875 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1876
00e0003e
SM		 1877 ath9k_hw_set_operating_mode(ah, ah->opmode);
1878
8fe65368 1879 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1880 if (r)
1881 return r;
f078f209 1882
dfdac8ac
FF		 1883 ath9k_hw_set_clockrate(ah);
1884
7d0d0df0
S		 1885 ENABLE_REGWRITE_BUFFER(ah);
1886
f078f209
LR		 1887 for (i = 0; i < AR_NUM_DCU; i++)
1888 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1889
7d0d0df0 1890 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1891
2660b81a 1892 ah->intr_txqs = 0;
f4c607dc 1893 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
f078f209
LR		 1894 ath9k_hw_resettxqueue(ah, i);
1895
2660b81a 1896 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1897 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1898 ath9k_hw_init_qos(ah);
1899
2660b81a 1900 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1901 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1902
0005baf4 1903 ath9k_hw_init_global_settings(ah);
f078f209 1904
fe2b6afb
FF		 1905 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1906 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1907 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1908 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1909 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1910 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1911 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1912 }
1913
ca7a4deb 1914 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1915
1916 ath9k_hw_set_dma(ah);
1917
ed6ebd8b
RM		 1918 if (!ath9k_hw_mci_is_enabled(ah))
1919 REG_WRITE(ah, AR_OBS, 8);
f078f209 1920
0ce024cb 1921 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1922 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1923 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1924 }
1925
7f62a136
VT		 1926 if (ah->config.tx_intr_mitigation) {
1927 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1928 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1929 }
1930
f078f209
LR		 1931 ath9k_hw_init_bb(ah, chan);
1932
77a5a664 1933 if (caldata) {
5f0c04ea 1934 caldata->done_txiqcal_once = false;
77a5a664
RM		 1935 caldata->done_txclcal_once = false;
1936 }
ae8d2858 1937 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1938 return -EIO;
f078f209 1939
93348928
RM		 1940 ath9k_hw_loadnf(ah, chan);
1941 ath9k_hw_start_nfcal(ah, true);
1942
5955b2b0 1943 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 1944 return -EIO;
63d32967 1945
7d0d0df0 1946 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1947
8fe65368 1948 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1949 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1950
7d0d0df0 1951 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1952
d7e7d229
LR		 1953 /*
1954 * For big endian systems turn on swapping for descriptors
1955 */
f078f209
LR		 1956 if (AR_SREV_9100(ah)) {
1957 u32 mask;
1958 mask = REG_READ(ah, AR_CFG);
1959 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
d2182b69
JP		 1960 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1961 mask);
f078f209
LR		 1962 } else {
1963 mask =
1964 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1965 REG_WRITE(ah, AR_CFG, mask);
d2182b69
JP		 1966 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1967 REG_READ(ah, AR_CFG));
f078f209
LR		 1968 }
1969 } else {
cbba8cd1
S		 1970 if (common->bus_ops->ath_bus_type == ATH_USB) {
1971 /* Configure AR9271 target WLAN */
1972 if (AR_SREV_9271(ah))
1973 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1974 else
1975 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1976 }
f078f209 1977#ifdef __BIG_ENDIAN
4033bdad 1978 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
2be7bfe0
VT		 1979 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1980 else
d7e7d229 1981 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1982#endif
1983 }
1984
dbccdd1d 1985 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 1986 ath9k_hw_btcoex_enable(ah);
1987
5955b2b0 1988 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1989 ar9003_mci_check_bt(ah);
63d32967 1990
51ac8cbb 1991 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 1992 ar9003_hw_bb_watchdog_config(ah);
d8903a53 1993
51ac8cbb
RM		 1994 ar9003_hw_disable_phy_restart(ah);
1995 }
1996
691680b8
FF		 1997 ath9k_hw_apply_gpio_override(ah);
1998
ae8d2858 1999 return 0;
f078f209 2000}
7322fd19 2001EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2002
f1dc5600
S		 2003/******************************/
2004/* Power Management (Chipset) */
2005/******************************/
2006
42d5bc3f
LR		 2007/*
2008 * Notify Power Mgt is disabled in self-generated frames.
2009 * If requested, force chip to sleep.
2010 */
31604cf0 2011static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 2012{
f1dc5600 2013 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 2014
31604cf0 2015 if (AR_SREV_9462(ah)) {
153dccd4
RM		 2016 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2017 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2018 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 2019 /* xxx Required for WLAN only case ? */
2020 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2021 udelay(100);
2022 }
2577c6e8 2023
31604cf0
SM		 2024 /*
2025 * Clear the RTC force wake bit to allow the
2026 * mac to go to sleep.
2027 */
2028 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2029
153dccd4 2030 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2031 udelay(100);
2577c6e8 2032
31604cf0
SM		 2033 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2034 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2035
31604cf0
SM		 2036 /* Shutdown chip. Active low */
2037 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2038 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2039 udelay(2);
f1dc5600 2040 }
9a658d2b
LR		 2041
2042 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2043 if (AR_SREV_9300_20_OR_LATER(ah))
2044 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2045}
2046
bbd79af5
LR		 2047/*
2048 * Notify Power Management is enabled in self-generating
2049 * frames. If request, set power mode of chip to
2050 * auto/normal. Duration in units of 128us (1/8 TU).
2051 */
31604cf0 2052static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2053{
31604cf0 2054 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2055
f1dc5600 2056 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2057
31604cf0
SM		 2058 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2059 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2060 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2061 AR_RTC_FORCE_WAKE_ON_INT);
2062 } else {
2577c6e8 2063
31604cf0
SM		 2064 /* When chip goes into network sleep, it could be waken
2065 * up by MCI_INT interrupt caused by BT's HW messages
2066 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2067 * rate (~100us). This will cause chip to leave and
2068 * re-enter network sleep mode frequently, which in
2069 * consequence will have WLAN MCI HW to generate lots of
2070 * SYS_WAKING and SYS_SLEEPING messages which will make
2071 * BT CPU to busy to process.
2072 */
153dccd4
RM		 2073 if (ath9k_hw_mci_is_enabled(ah))
2074 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2075 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2076 /*
2077 * Clear the RTC force wake bit to allow the
2078 * mac to go to sleep.
2079 */
153dccd4 2080 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2081
153dccd4 2082 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2083 udelay(30);
f078f209 2084 }
9a658d2b
LR		 2085
2086 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2087 if (AR_SREV_9300_20_OR_LATER(ah))
2088 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2089}
2090
31604cf0 2091static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2092{
f1dc5600
S		 2093 u32 val;
2094 int i;
f078f209 2095
9a658d2b
LR		 2096 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2097 if (AR_SREV_9300_20_OR_LATER(ah)) {
2098 REG_WRITE(ah, AR_WA, ah->WARegVal);
2099 udelay(10);
2100 }
2101
31604cf0
SM		 2102 if ((REG_READ(ah, AR_RTC_STATUS) &
2103 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2104 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2105 return false;
f1dc5600 2106 }
31604cf0
SM		 2107 if (!AR_SREV_9300_20_OR_LATER(ah))
2108 ath9k_hw_init_pll(ah, NULL);
2109 }
2110 if (AR_SREV_9100(ah))
2111 REG_SET_BIT(ah, AR_RTC_RESET,
2112 AR_RTC_RESET_EN);
2113
2114 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2115 AR_RTC_FORCE_WAKE_EN);
2116 udelay(50);
f078f209 2117
9dd9b0dc
RM		 2118 if (ath9k_hw_mci_is_enabled(ah))
2119 ar9003_mci_set_power_awake(ah);
2120
31604cf0
SM		 2121 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2122 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2123 if (val == AR_RTC_STATUS_ON)
2124 break;
2125 udelay(50);
f1dc5600
S		 2126 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2127 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2128 }
2129 if (i == 0) {
2130 ath_err(ath9k_hw_common(ah),
2131 "Failed to wakeup in %uus\n",
2132 POWER_UP_TIME / 20);
2133 return false;
f078f209
LR		 2134 }
2135
f1dc5600 2136 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2137
f1dc5600 2138 return true;
f078f209
LR		 2139}
2140
9ecdef4b 2141bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2142{
c46917bb 2143 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2144 int status = true;
f1dc5600
S		 2145 static const char *modes[] = {
2146 "AWAKE",
2147 "FULL-SLEEP",
2148 "NETWORK SLEEP",
2149 "UNDEFINED"
2150 };
f1dc5600 2151
cbdec975
GJ		 2152 if (ah->power_mode == mode)
2153 return status;
2154
d2182b69 2155 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2156 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2157
2158 switch (mode) {
2159 case ATH9K_PM_AWAKE:
31604cf0 2160 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2161 break;
2162 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2163 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2164 ar9003_mci_set_full_sleep(ah);
1010911e 2165
31604cf0 2166 ath9k_set_power_sleep(ah);
2660b81a 2167 ah->chip_fullsleep = true;
f1dc5600
S		 2168 break;
2169 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2170 ath9k_set_power_network_sleep(ah);
f1dc5600 2171 break;
f078f209 2172 default:
3800276a 2173 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2174 return false;
2175 }
2660b81a 2176 ah->power_mode = mode;
f1dc5600 2177
69f4aab1
LR		 2178 /*
2179 * XXX: If this warning never comes up after a while then
2180 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2181 * ath9k_hw_setpower() return type void.
2182 */
97dcec57
SM		 2183
2184 if (!(ah->ah_flags & AH_UNPLUGGED))
2185 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2186
f1dc5600 2187 return status;
f078f209 2188}
7322fd19 2189EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2190
f1dc5600
S		 2191/*******************/
2192/* Beacon Handling */
2193/*******************/
2194
cbe61d8a 2195void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2196{
f078f209
LR		 2197 int flags = 0;
2198
7d0d0df0
S		 2199 ENABLE_REGWRITE_BUFFER(ah);
2200
2660b81a 2201 switch (ah->opmode) {
d97809db 2202 case NL80211_IFTYPE_ADHOC:
9cb5412b 2203 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 2204 REG_SET_BIT(ah, AR_TXCFG,
2205 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
dd347f2f
FF		 2206 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2207 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
f078f209 2208 flags |= AR_NDP_TIMER_EN;
d97809db 2209 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2210 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2211 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2212 TU_TO_USEC(ah->config.dma_beacon_response_time));
2213 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2214 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2215 flags |=
2216 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2217 break;
d97809db 2218 default:
d2182b69
JP		 2219 ath_dbg(ath9k_hw_common(ah), BEACON,
2220 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2221 return;
2222 break;
f078f209
LR		 2223 }
2224
dd347f2f
FF		 2225 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2226 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2227 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2228 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
f078f209 2229
7d0d0df0 2230 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2231
f078f209
LR		 2232 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2233}
7322fd19 2234EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2235
cbe61d8a 2236void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2237 const struct ath9k_beacon_state *bs)
f078f209
LR		 2238{
2239 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2240 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2241 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2242
7d0d0df0
S		 2243 ENABLE_REGWRITE_BUFFER(ah);
2244
f078f209
LR		 2245 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2246
2247 REG_WRITE(ah, AR_BEACON_PERIOD,
f29f5c08 2248 TU_TO_USEC(bs->bs_intval));
f078f209 2249 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
f29f5c08 2250 TU_TO_USEC(bs->bs_intval));
f078f209 2251
7d0d0df0 2252 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2253
f078f209
LR		 2254 REG_RMW_FIELD(ah, AR_RSSI_THR,
2255 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2256
f29f5c08 2257 beaconintval = bs->bs_intval;
f078f209
LR		 2258
2259 if (bs->bs_sleepduration > beaconintval)
2260 beaconintval = bs->bs_sleepduration;
2261
2262 dtimperiod = bs->bs_dtimperiod;
2263 if (bs->bs_sleepduration > dtimperiod)
2264 dtimperiod = bs->bs_sleepduration;
2265
2266 if (beaconintval == dtimperiod)
2267 nextTbtt = bs->bs_nextdtim;
2268 else
2269 nextTbtt = bs->bs_nexttbtt;
2270
d2182b69
JP		 2271 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2272 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2273 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2274 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2275
7d0d0df0
S		 2276 ENABLE_REGWRITE_BUFFER(ah);
2277
f1dc5600
S		 2278 REG_WRITE(ah, AR_NEXT_DTIM,
2279 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2280 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 2281
f1dc5600
S		 2282 REG_WRITE(ah, AR_SLEEP1,
2283 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2284 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2285
f1dc5600
S		 2286 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2287 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2288 else
2289 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2290
f1dc5600
S		 2291 REG_WRITE(ah, AR_SLEEP2,
2292 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2293
f1dc5600
S		 2294 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2295 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2296
7d0d0df0 2297 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2298
f1dc5600
S		 2299 REG_SET_BIT(ah, AR_TIMER_MODE,
2300 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2301 AR_DTIM_TIMER_EN);
f078f209 2302
4af9cf4f
S		 2303 /* TSF Out of Range Threshold */
2304 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2305}
7322fd19 2306EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2307
f1dc5600
S		 2308/*******************/
2309/* HW Capabilities */
2310/*******************/
2311
6054069a
FF		 2312static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2313{
2314 eeprom_chainmask &= chip_chainmask;
2315 if (eeprom_chainmask)
2316 return eeprom_chainmask;
2317 else
2318 return chip_chainmask;
2319}
2320
9a66af33
ZK		 2321/**
2322 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2323 * @ah: the atheros hardware data structure
2324 *
2325 * We enable DFS support upstream on chipsets which have passed a series
2326 * of tests. The testing requirements are going to be documented. Desired
2327 * test requirements are documented at:
2328 *
2329 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2330 *
2331 * Once a new chipset gets properly tested an individual commit can be used
2332 * to document the testing for DFS for that chipset.
2333 */
2334static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2335{
2336
2337 switch (ah->hw_version.macVersion) {
2338 /* AR9580 will likely be our first target to get testing on */
2339 case AR_SREV_VERSION_9580:
2340 default:
2341 return false;
2342 }
2343}
2344
a9a29ce6 2345int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2346{
2660b81a 2347 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2348 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2349 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2350 unsigned int chip_chainmask;
608b88cb 2351
0ff2b5c0 2352 u16 eeval;
47c80de6 2353 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2354
f74df6fb 2355 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2356 regulatory->current_rd = eeval;
f078f209 2357
2660b81a 2358 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2359 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2360 if (regulatory->current_rd == 0x64 ||
2361 regulatory->current_rd == 0x65)
2362 regulatory->current_rd += 5;
2363 else if (regulatory->current_rd == 0x41)
2364 regulatory->current_rd = 0x43;
d2182b69
JP		 2365 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2366 regulatory->current_rd);
f1dc5600 2367 }
f078f209 2368
f74df6fb 2369 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2370 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2371 ath_err(common,
2372 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2373 return -EINVAL;
2374 }
2375
d4659912
FF		 2376 if (eeval & AR5416_OPFLAGS_11A)
2377 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2378
d4659912
FF		 2379 if (eeval & AR5416_OPFLAGS_11G)
2380 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2381
6054069a
FF		 2382 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2383 chip_chainmask = 1;
ba5736a5
MSS		 2384 else if (AR_SREV_9462(ah))
2385 chip_chainmask = 3;
6054069a
FF		 2386 else if (!AR_SREV_9280_20_OR_LATER(ah))
2387 chip_chainmask = 7;
2388 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2389 chip_chainmask = 3;
2390 else
2391 chip_chainmask = 7;
2392
f74df6fb 2393 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2394 /*
2395 * For AR9271 we will temporarilly uses the rx chainmax as read from
2396 * the EEPROM.
2397 */
8147f5de 2398 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2399 !(eeval & AR5416_OPFLAGS_11A) &&
2400 !(AR_SREV_9271(ah)))
2401 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2402 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2403 else if (AR_SREV_9100(ah))
2404 pCap->rx_chainmask = 0x7;
8147f5de 2405 else
d7e7d229 2406 /* Use rx_chainmask from EEPROM. */
8147f5de 2407 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2408
6054069a
FF		 2409 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2410 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2411 ah->txchainmask = pCap->tx_chainmask;
2412 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2413
7a37081e 2414 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2415
02d2ebb2
FF		 2416 /* enable key search for every frame in an aggregate */
2417 if (AR_SREV_9300_20_OR_LATER(ah))
2418 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2419
ce2220d1
BR		 2420 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2421
0db156e9 2422 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2423 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2424 else
2425 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2426
5b5fa355
S		 2427 if (AR_SREV_9271(ah))
2428 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2429 else if (AR_DEVID_7010(ah))
2430 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2431 else if (AR_SREV_9300_20_OR_LATER(ah))
2432 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2433 else if (AR_SREV_9287_11_OR_LATER(ah))
2434 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2435 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2436 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2437 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2438 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2439 else
2440 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2441
1b2538b2 2442 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2443 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2444 else
f1dc5600 2445 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2446
e97275cb 2447#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2448 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2449 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2450 ah->rfkill_gpio =
2451 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2452 ah->rfkill_polarity =
2453 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2454
2455 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2456 }
f1dc5600 2457#endif
d5d1154f 2458 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2459 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2460 else
2461 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2462
e7594072 2463 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2464 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2465 else
2466 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2467
ceb26445 2468 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2469 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
0e707a94 2470 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
784ad503
VT		 2471 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2472
ceb26445
VT		 2473 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2474 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2475 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2476 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2477 pCap->txs_len = sizeof(struct ar9003_txs);
6f481010
LR		 2478 if (!ah->config.paprd_disable &&
2479 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
4935250a 2480 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 2481 } else {
2482 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2483 if (AR_SREV_9280_20(ah))
6b42e8d0 2484 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2485 }
1adf02ff 2486
6c84ce08
VT		 2487 if (AR_SREV_9300_20_OR_LATER(ah))
2488 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2489
6ee63f55
SB		 2490 if (AR_SREV_9300_20_OR_LATER(ah))
2491 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2492
a42acef0 2493 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2494 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2495
754dc536
VT		 2496 if (AR_SREV_9285(ah))
2497 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2498 ant_div_ctl1 =
2499 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2500 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2501 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2502 }
ea066d5a
MSS		 2503 if (AR_SREV_9300_20_OR_LATER(ah)) {
2504 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2505 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2506 }
2507
2508
431da56a 2509 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
21d2c63a
MSS		 2510 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2511 /*
2512 * enable the diversity-combining algorithm only when
2513 * both enable_lna_div and enable_fast_div are set
2514 * Table for Diversity
2515 * ant_div_alt_lnaconf bit 0-1
2516 * ant_div_main_lnaconf bit 2-3
2517 * ant_div_alt_gaintb bit 4
2518 * ant_div_main_gaintb bit 5
2519 * enable_ant_div_lnadiv bit 6
2520 * enable_ant_fast_div bit 7
2521 */
2522 if ((ant_div_ctl1 >> 0x6) == 0x3)
2523 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2524 }
754dc536 2525
8060e169
VT		 2526 if (AR_SREV_9485_10(ah)) {
2527 pCap->pcie_lcr_extsync_en = true;
2528 pCap->pcie_lcr_offset = 0x80;
2529 }
2530
9a66af33
ZK		 2531 if (ath9k_hw_dfs_tested(ah))
2532 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2533
47c80de6
VT		 2534 tx_chainmask = pCap->tx_chainmask;
2535 rx_chainmask = pCap->rx_chainmask;
2536 while (tx_chainmask || rx_chainmask) {
2537 if (tx_chainmask & BIT(0))
2538 pCap->max_txchains++;
2539 if (rx_chainmask & BIT(0))
2540 pCap->max_rxchains++;
2541
2542 tx_chainmask >>= 1;
2543 rx_chainmask >>= 1;
2544 }
2545
8ad74c4d
RM		 2546 if (AR_SREV_9300_20_OR_LATER(ah)) {
2547 ah->enabled_cals |= TX_IQ_CAL;
6fea593d 2548 if (AR_SREV_9485_OR_LATER(ah))
8ad74c4d
RM		 2549 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2550 }
3789d59c
MSS		 2551
2552 if (AR_SREV_9462(ah)) {
2553
2554 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2555 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2556
2557 if (AR_SREV_9462_20(ah))
2558 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2559
2560 }
2561
324c74ad 2562
a9a29ce6 2563 return 0;
f078f209
LR		 2564}
2565
f1dc5600
S		 2566/****************************/
2567/* GPIO / RFKILL / Antennae */
2568/****************************/
f078f209 2569
cbe61d8a 2570static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2571 u32 gpio, u32 type)
2572{
2573 int addr;
2574 u32 gpio_shift, tmp;
f078f209 2575
f1dc5600
S		 2576 if (gpio > 11)
2577 addr = AR_GPIO_OUTPUT_MUX3;
2578 else if (gpio > 5)
2579 addr = AR_GPIO_OUTPUT_MUX2;
2580 else
2581 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2582
f1dc5600 2583 gpio_shift = (gpio % 6) * 5;
f078f209 2584
f1dc5600
S		 2585 if (AR_SREV_9280_20_OR_LATER(ah)
2586 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2587 REG_RMW(ah, addr, (type << gpio_shift),
2588 (0x1f << gpio_shift));
f078f209 2589 } else {
f1dc5600
S		 2590 tmp = REG_READ(ah, addr);
2591 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2592 tmp &= ~(0x1f << gpio_shift);
2593 tmp |= (type << gpio_shift);
2594 REG_WRITE(ah, addr, tmp);
f078f209 2595 }
f078f209
LR		 2596}
2597
cbe61d8a 2598void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2599{
f1dc5600 2600 u32 gpio_shift;
f078f209 2601
9680e8a3 2602 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2603
88c1f4f6
S		 2604 if (AR_DEVID_7010(ah)) {
2605 gpio_shift = gpio;
2606 REG_RMW(ah, AR7010_GPIO_OE,
2607 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2608 (AR7010_GPIO_OE_MASK << gpio_shift));
2609 return;
2610 }
f078f209 2611
88c1f4f6 2612 gpio_shift = gpio << 1;
f1dc5600
S		 2613 REG_RMW(ah,
2614 AR_GPIO_OE_OUT,
2615 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2616 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2617}
7322fd19 2618EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2619
cbe61d8a 2620u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2621{
cb33c412
SB		 2622#define MS_REG_READ(x, y) \
2623 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2624
2660b81a 2625 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2626 return 0xffffffff;
f078f209 2627
88c1f4f6
S		 2628 if (AR_DEVID_7010(ah)) {
2629 u32 val;
2630 val = REG_READ(ah, AR7010_GPIO_IN);
2631 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2632 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2633 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2634 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2635 else if (AR_SREV_9271(ah))
5b5fa355 2636 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2637 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2638 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2639 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2640 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2641 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2642 return MS_REG_READ(AR928X, gpio) != 0;
2643 else
2644 return MS_REG_READ(AR, gpio) != 0;
f078f209 2645}
7322fd19 2646EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2647
cbe61d8a 2648void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2649 u32 ah_signal_type)
f078f209 2650{
f1dc5600 2651 u32 gpio_shift;
f078f209 2652
88c1f4f6
S		 2653 if (AR_DEVID_7010(ah)) {
2654 gpio_shift = gpio;
2655 REG_RMW(ah, AR7010_GPIO_OE,
2656 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2657 (AR7010_GPIO_OE_MASK << gpio_shift));
2658 return;
2659 }
f078f209 2660
88c1f4f6 2661 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2662 gpio_shift = 2 * gpio;
f1dc5600
S		 2663 REG_RMW(ah,
2664 AR_GPIO_OE_OUT,
2665 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2666 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2667}
7322fd19 2668EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2669
cbe61d8a 2670void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2671{
88c1f4f6
S		 2672 if (AR_DEVID_7010(ah)) {
2673 val = val ? 0 : 1;
2674 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2675 AR_GPIO_BIT(gpio));
2676 return;
2677 }
2678
5b5fa355
S		 2679 if (AR_SREV_9271(ah))
2680 val = ~val;
2681
f1dc5600
S		 2682 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2683 AR_GPIO_BIT(gpio));
f078f209 2684}
7322fd19 2685EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2686
cbe61d8a 2687void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2688{
f1dc5600 2689 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2690}
7322fd19 2691EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2692
f1dc5600
S		 2693/*********************/
2694/* General Operation */
2695/*********************/
2696
cbe61d8a 2697u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2698{
f1dc5600
S		 2699 u32 bits = REG_READ(ah, AR_RX_FILTER);
2700 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2701
f1dc5600
S		 2702 if (phybits & AR_PHY_ERR_RADAR)
2703 bits |= ATH9K_RX_FILTER_PHYRADAR;
2704 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2705 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2706
f1dc5600 2707 return bits;
f078f209 2708}
7322fd19 2709EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2710
cbe61d8a 2711void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2712{
f1dc5600 2713 u32 phybits;
f078f209 2714
7d0d0df0
S		 2715 ENABLE_REGWRITE_BUFFER(ah);
2716
423e38e8 2717 if (AR_SREV_9462(ah))
2577c6e8
SB		 2718 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2719
7ea310be
S		 2720 REG_WRITE(ah, AR_RX_FILTER, bits);
2721
f1dc5600
S		 2722 phybits = 0;
2723 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2724 phybits |= AR_PHY_ERR_RADAR;
2725 if (bits & ATH9K_RX_FILTER_PHYERR)
2726 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2727 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2728
f1dc5600 2729 if (phybits)
ca7a4deb 2730 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2731 else
ca7a4deb 2732 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2733
2734 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2735}
7322fd19 2736EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2737
cbe61d8a 2738bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2739{
99922a45
RM		 2740 if (ath9k_hw_mci_is_enabled(ah))
2741 ar9003_mci_bt_gain_ctrl(ah);
2742
63a75b91
SB		 2743 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2744 return false;
2745
2746 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2747 ah->htc_reset_init = true;
63a75b91 2748 return true;
f1dc5600 2749}
7322fd19 2750EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2751
cbe61d8a 2752bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2753{
9ecdef4b 2754 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2755 return false;
f078f209 2756
63a75b91
SB		 2757 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2758 return false;
2759
2760 ath9k_hw_init_pll(ah, NULL);
2761 return true;
f078f209 2762}
7322fd19 2763EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2764
ca2c68cc
FF		 2765static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2766{
2767 enum eeprom_param gain_param;
2768
2769 if (IS_CHAN_2GHZ(chan))
2770 gain_param = EEP_ANTENNA_GAIN_2G;
2771 else
2772 gain_param = EEP_ANTENNA_GAIN_5G;
2773
2774 return ah->eep_ops->get_eeprom(ah, gain_param);
2775}
2776
64ea57d0
GJ		 2777void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2778 bool test)
ca2c68cc
FF		 2779{
2780 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2781 struct ieee80211_channel *channel;
2782 int chan_pwr, new_pwr, max_gain;
2783 int ant_gain, ant_reduction = 0;
2784
2785 if (!chan)
2786 return;
2787
2788 channel = chan->chan;
2789 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2790 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2791 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2792
2793 ant_gain = get_antenna_gain(ah, chan);
2794 if (ant_gain > max_gain)
2795 ant_reduction = ant_gain - max_gain;
2796
2797 ah->eep_ops->set_txpower(ah, chan,
2798 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2799 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2800}
2801
de40f316 2802void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2803{
ca2c68cc 2804 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2805 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2806 struct ieee80211_channel *channel = chan->chan;
9c204b46 2807
48ef5c42 2808 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2809 if (test)
ca2c68cc 2810 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2811
64ea57d0 2812 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2813
ca2c68cc
FF		 2814 if (test)
2815 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2816}
7322fd19 2817EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2818
cbe61d8a 2819void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2820{
2660b81a 2821 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2822}
7322fd19 2823EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2824
cbe61d8a 2825void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2826{
f1dc5600
S		 2827 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2828 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2829}
7322fd19 2830EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2831
f2b2143e 2832void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2833{
1510718d
LR		 2834 struct ath_common *common = ath9k_hw_common(ah);
2835
2836 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2837 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2838 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2839}
7322fd19 2840EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2841
1c0fc65e
BP		 2842#define ATH9K_MAX_TSF_READ 10
2843
cbe61d8a 2844u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2845{
1c0fc65e
BP		 2846 u32 tsf_lower, tsf_upper1, tsf_upper2;
2847 int i;
2848
2849 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2850 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2851 tsf_lower = REG_READ(ah, AR_TSF_L32);
2852 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2853 if (tsf_upper2 == tsf_upper1)
2854 break;
2855 tsf_upper1 = tsf_upper2;
2856 }
f078f209 2857
1c0fc65e 2858 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2859
1c0fc65e 2860 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2861}
7322fd19 2862EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2863
cbe61d8a 2864void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2865{
27abe060 2866 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2867 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2868}
7322fd19 2869EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2870
cbe61d8a 2871void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2872{
f9b604f6
GJ		 2873 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2874 AH_TSF_WRITE_TIMEOUT))
d2182b69 2875 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2876 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2877
f1dc5600
S		 2878 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2879}
7322fd19 2880EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2881
54e4cec6 2882void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2883{
f1dc5600 2884 if (setting)
2660b81a 2885 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2886 else
2660b81a 2887 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2888}
7322fd19 2889EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2890
25c56eec 2891void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2892{
25c56eec 2893 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2894 u32 macmode;
2895
25c56eec 2896 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2897 macmode = AR_2040_JOINED_RX_CLEAR;
2898 else
2899 macmode = 0;
f078f209 2900
f1dc5600 2901 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2902}
ff155a45
VT		 2903
2904/* HW Generic timers configuration */
2905
2906static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2907{
2908 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2909 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2910 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2911 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2912 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2913 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2914 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2915 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2916 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2917 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2918 AR_NDP2_TIMER_MODE, 0x0002},
2919 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2920 AR_NDP2_TIMER_MODE, 0x0004},
2921 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2922 AR_NDP2_TIMER_MODE, 0x0008},
2923 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2924 AR_NDP2_TIMER_MODE, 0x0010},
2925 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2926 AR_NDP2_TIMER_MODE, 0x0020},
2927 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2928 AR_NDP2_TIMER_MODE, 0x0040},
2929 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2930 AR_NDP2_TIMER_MODE, 0x0080}
2931};
2932
2933/* HW generic timer primitives */
2934
2935/* compute and clear index of rightmost 1 */
2936static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2937{
2938 u32 b;
2939
2940 b = *mask;
2941 b &= (0-b);
2942 *mask &= ~b;
2943 b *= debruijn32;
2944 b >>= 27;
2945
2946 return timer_table->gen_timer_index[b];
2947}
2948
dd347f2f 2949u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2950{
2951 return REG_READ(ah, AR_TSF_L32);
2952}
dd347f2f 2953EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2954
2955struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2956 void (*trigger)(void *),
2957 void (*overflow)(void *),
2958 void *arg,
2959 u8 timer_index)
2960{
2961 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2962 struct ath_gen_timer *timer;
2963
2964 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2965
2966 if (timer == NULL) {
3800276a
JP		 2967 ath_err(ath9k_hw_common(ah),
2968 "Failed to allocate memory for hw timer[%d]\n",
2969 timer_index);
ff155a45
VT		 2970 return NULL;
2971 }
2972
2973 /* allocate a hardware generic timer slot */
2974 timer_table->timers[timer_index] = timer;
2975 timer->index = timer_index;
2976 timer->trigger = trigger;
2977 timer->overflow = overflow;
2978 timer->arg = arg;
2979
2980 return timer;
2981}
7322fd19 2982EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2983
cd9bf689
LR		 2984void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2985 struct ath_gen_timer *timer,
788f6875 2986 u32 trig_timeout,
cd9bf689 2987 u32 timer_period)
ff155a45
VT		 2988{
2989 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
788f6875 2990 u32 tsf, timer_next;
ff155a45
VT		 2991
2992 BUG_ON(!timer_period);
2993
2994 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2995
2996 tsf = ath9k_hw_gettsf32(ah);
2997
788f6875
VT		 2998 timer_next = tsf + trig_timeout;
2999
d2182b69 3000 ath_dbg(ath9k_hw_common(ah), HWTIMER,
226afe68
JP		 3001 "current tsf %x period %x timer_next %x\n",
3002 tsf, timer_period, timer_next);
ff155a45 3003
ff155a45
VT		 3004 /*
3005 * Program generic timer registers
3006 */
3007 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3008 timer_next);
3009 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3010 timer_period);
3011 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3012 gen_tmr_configuration[timer->index].mode_mask);
3013
423e38e8 3014 if (AR_SREV_9462(ah)) {
2577c6e8 3015 /*
423e38e8 3016 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3017 * to use. But we still follow the old rule, 0 - 7 use tsf and
3018 * 8 - 15 use tsf2.
3019 */
3020 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3021 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3022 (1 << timer->index));
3023 else
3024 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3025 (1 << timer->index));
3026 }
3027
ff155a45
VT		 3028 /* Enable both trigger and thresh interrupt masks */
3029 REG_SET_BIT(ah, AR_IMR_S5,
3030 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3031 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 3032}
7322fd19 3033EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3034
cd9bf689 3035void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3036{
3037 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3038
3039 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3040 (timer->index >= ATH_MAX_GEN_TIMER)) {
3041 return;
3042 }
3043
3044 /* Clear generic timer enable bits. */
3045 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3046 gen_tmr_configuration[timer->index].mode_mask);
3047
3048 /* Disable both trigger and thresh interrupt masks */
3049 REG_CLR_BIT(ah, AR_IMR_S5,
3050 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3051 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3052
3053 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3054}
7322fd19 3055EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3056
3057void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3058{
3059 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3060
3061 /* free the hardware generic timer slot */
3062 timer_table->timers[timer->index] = NULL;
3063 kfree(timer);
3064}
7322fd19 3065EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3066
3067/*
3068 * Generic Timer Interrupts handling
3069 */
3070void ath_gen_timer_isr(struct ath_hw *ah)
3071{
3072 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3073 struct ath_gen_timer *timer;
c46917bb 3074 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3075 u32 trigger_mask, thresh_mask, index;
3076
3077 /* get hardware generic timer interrupt status */
3078 trigger_mask = ah->intr_gen_timer_trigger;
3079 thresh_mask = ah->intr_gen_timer_thresh;
3080 trigger_mask &= timer_table->timer_mask.val;
3081 thresh_mask &= timer_table->timer_mask.val;
3082
3083 trigger_mask &= ~thresh_mask;
3084
3085 while (thresh_mask) {
3086 index = rightmost_index(timer_table, &thresh_mask);
3087 timer = timer_table->timers[index];
3088 BUG_ON(!timer);
d2182b69
JP		 3089 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3090 index);
ff155a45
VT		 3091 timer->overflow(timer->arg);
3092 }
3093
3094 while (trigger_mask) {
3095 index = rightmost_index(timer_table, &trigger_mask);
3096 timer = timer_table->timers[index];
3097 BUG_ON(!timer);
d2182b69 3098 ath_dbg(common, HWTIMER,
226afe68 3099 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3100 timer->trigger(timer->arg);
3101 }
3102}
7322fd19 3103EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3104
05020d23
S		 3105/********/
3106/* HTC */
3107/********/
3108
2da4f01a
LR		 3109static struct {
3110 u32 version;
3111 const char * name;
3112} ath_mac_bb_names[] = {
3113 /* Devices with external radios */
3114 { AR_SREV_VERSION_5416_PCI, "5416" },
3115 { AR_SREV_VERSION_5416_PCIE, "5418" },
3116 { AR_SREV_VERSION_9100, "9100" },
3117 { AR_SREV_VERSION_9160, "9160" },
3118 /* Single-chip solutions */
3119 { AR_SREV_VERSION_9280, "9280" },
3120 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3121 { AR_SREV_VERSION_9287, "9287" },
3122 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3123 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3124 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3125 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3126 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3127 { AR_SREV_VERSION_9462, "9462" },
2da4f01a
LR		 3128};
3129
3130/* For devices with external radios */
3131static struct {
3132 u16 version;
3133 const char * name;
3134} ath_rf_names[] = {
3135 { 0, "5133" },
3136 { AR_RAD5133_SREV_MAJOR, "5133" },
3137 { AR_RAD5122_SREV_MAJOR, "5122" },
3138 { AR_RAD2133_SREV_MAJOR, "2133" },
3139 { AR_RAD2122_SREV_MAJOR, "2122" }
3140};
3141
3142/*
3143 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3144 */
f934c4d9 3145static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3146{
3147 int i;
3148
3149 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3150 if (ath_mac_bb_names[i].version == mac_bb_version) {
3151 return ath_mac_bb_names[i].name;
3152 }
3153 }
3154
3155 return "????";
3156}
2da4f01a
LR		 3157
3158/*
3159 * Return the RF name. "????" is returned if the RF is unknown.
3160 * Used for devices with external radios.
3161 */
f934c4d9 3162static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3163{
3164 int i;
3165
3166 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3167 if (ath_rf_names[i].version == rf_version) {
3168 return ath_rf_names[i].name;
3169 }
3170 }
3171
3172 return "????";
3173}
f934c4d9
LR		 3174
3175void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3176{
3177 int used;
3178
3179 /* chipsets >= AR9280 are single-chip */
7a37081e 3180 if (AR_SREV_9280_20_OR_LATER(ah)) {
f934c4d9
LR		 3181 used = snprintf(hw_name, len,
3182 "Atheros AR%s Rev:%x",
3183 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3184 ah->hw_version.macRev);
3185 }
3186 else {
3187 used = snprintf(hw_name, len,
3188 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3189 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3190 ah->hw_version.macRev,
3191 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3192 AR_RADIO_SREV_MAJOR)),
3193 ah->hw_version.phyRev);
3194 }
3195
3196 hw_name[used] = '\0';
3197}
3198EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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