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[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
f078f209
LR		 19#include <asm/unaligned.h>
20
af03abec 21#include "hw.h"
d70357d5 22#include "hw-ops.h"
cfe8cba9 23#include "rc.h"
b622a720 24#include "ar9003_mac.h"
f078f209 25
cbe61d8a 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 27
7322fd19
LR		 28MODULE_AUTHOR("Atheros Communications");
29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31MODULE_LICENSE("Dual BSD/GPL");
32
33static int __init ath9k_init(void)
34{
35 return 0;
36}
37module_init(ath9k_init);
38
39static void __exit ath9k_exit(void)
40{
41 return;
42}
43module_exit(ath9k_exit);
44
d70357d5
LR		 45/* Private hardware callbacks */
46
47static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48{
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50}
51
52static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55}
56
57static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
58{
59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
60
61 return priv_ops->macversion_supported(ah->hw_version.macVersion);
62}
63
64773964
LR		 64static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
65 struct ath9k_channel *chan)
66{
67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
68}
69
991312d8
LR		 70static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
71{
72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
73 return;
74
75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
76}
77
e36b27af
LR		 78static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
79{
80 /* You will not have this callback if using the old ANI */
81 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
82 return;
83
84 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
85}
86
f1dc5600
S		 87/********************/
88/* Helper Functions */
89/********************/
f078f209 90
dfdac8ac 91static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 92{
b002a4a9 93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
dfdac8ac
FF		 94 struct ath_common *common = ath9k_hw_common(ah);
95 unsigned int clockrate;
cbe61d8a 96
2660b81a 97 if (!ah->curchan) /* should really check for CCK instead */
dfdac8ac
FF		 98 clockrate = ATH9K_CLOCK_RATE_CCK;
99 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
100 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
101 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
102 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 103 else
dfdac8ac
FF		 104 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
105
106 if (conf_is_ht40(conf))
107 clockrate *= 2;
108
109 common->clockrate = clockrate;
f1dc5600
S		 110}
111
cbe61d8a 112static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 113{
dfdac8ac 114 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 115
dfdac8ac 116 return usecs * common->clockrate;
f1dc5600 117}
f078f209 118
0caa7b14 119bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 120{
121 int i;
122
0caa7b14
S		 123 BUG_ON(timeout < AH_TIME_QUANTUM);
124
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 126 if ((REG_READ(ah, reg) & mask) == val)
127 return true;
128
129 udelay(AH_TIME_QUANTUM);
130 }
04bd4638 131
c46917bb
LR		 132 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 135
f1dc5600 136 return false;
f078f209 137}
7322fd19 138EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 139
140u32 ath9k_hw_reverse_bits(u32 val, u32 n)
141{
142 u32 retval;
143 int i;
144
145 for (i = 0, retval = 0; i < n; i++) {
146 retval = (retval << 1) | (val & 1);
147 val >>= 1;
148 }
149 return retval;
150}
151
cbe61d8a 152bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 153 u16 flags, u16 *low,
154 u16 *high)
f078f209 155{
2660b81a 156 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 157
f1dc5600
S		 158 if (flags & CHANNEL_5GHZ) {
159 *low = pCap->low_5ghz_chan;
160 *high = pCap->high_5ghz_chan;
161 return true;
f078f209 162 }
f1dc5600
S		 163 if ((flags & CHANNEL_2GHZ)) {
164 *low = pCap->low_2ghz_chan;
165 *high = pCap->high_2ghz_chan;
166 return true;
167 }
168 return false;
f078f209
LR		 169}
170
cbe61d8a 171u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 172 u8 phy, int kbps,
f1dc5600
S		 173 u32 frameLen, u16 rateix,
174 bool shortPreamble)
f078f209 175{
f1dc5600 176 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 177
f1dc5600
S		 178 if (kbps == 0)
179 return 0;
f078f209 180
545750d3 181 switch (phy) {
46d14a58 182 case WLAN_RC_PHY_CCK:
f1dc5600 183 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 184 if (shortPreamble)
f1dc5600
S		 185 phyTime >>= 1;
186 numBits = frameLen << 3;
187 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
188 break;
46d14a58 189 case WLAN_RC_PHY_OFDM:
2660b81a 190 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 191 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
192 numBits = OFDM_PLCP_BITS + (frameLen << 3);
193 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
194 txTime = OFDM_SIFS_TIME_QUARTER
195 + OFDM_PREAMBLE_TIME_QUARTER
196 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 197 } else if (ah->curchan &&
198 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME_HALF +
203 OFDM_PREAMBLE_TIME_HALF
204 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
205 } else {
206 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
207 numBits = OFDM_PLCP_BITS + (frameLen << 3);
208 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
209 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
210 + (numSymbols * OFDM_SYMBOL_TIME);
211 }
212 break;
213 default:
c46917bb 214 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 215 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 216 txTime = 0;
217 break;
218 }
f078f209 219
f1dc5600
S		 220 return txTime;
221}
7322fd19 222EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 223
cbe61d8a 224void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 225 struct ath9k_channel *chan,
226 struct chan_centers *centers)
f078f209 227{
f1dc5600 228 int8_t extoff;
f078f209 229
f1dc5600
S		 230 if (!IS_CHAN_HT40(chan)) {
231 centers->ctl_center = centers->ext_center =
232 centers->synth_center = chan->channel;
233 return;
f078f209 234 }
f078f209 235
f1dc5600
S		 236 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
237 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
238 centers->synth_center =
239 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
240 extoff = 1;
241 } else {
242 centers->synth_center =
243 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
244 extoff = -1;
245 }
f078f209 246
f1dc5600
S		 247 centers->ctl_center =
248 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 249 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 250 centers->ext_center =
6420014c 251 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 252}
253
f1dc5600
S		 254/******************/
255/* Chip Revisions */
256/******************/
257
cbe61d8a 258static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 259{
f1dc5600 260 u32 val;
f078f209 261
f1dc5600 262 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 263
f1dc5600
S		 264 if (val == 0xFF) {
265 val = REG_READ(ah, AR_SREV);
d535a42a
S		 266 ah->hw_version.macVersion =
267 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 269 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 270 } else {
271 if (!AR_SREV_9100(ah))
d535a42a 272 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 273
d535a42a 274 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 275
d535a42a 276 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 277 ah->is_pciexpress = true;
f1dc5600 278 }
f078f209
LR		 279}
280
f1dc5600
S		 281/************************************/
282/* HW Attach, Detach, Init Routines */
283/************************************/
284
cbe61d8a 285static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 286{
feed029c 287 if (AR_SREV_9100(ah))
f1dc5600 288 return;
f078f209 289
7d0d0df0
S		 290 ENABLE_REGWRITE_BUFFER(ah);
291
f1dc5600
S		 292 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
298 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
299 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
300 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 301
f1dc5600 302 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
7d0d0df0
S		 303
304 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 305}
306
1f3f0618 307/* This should work for all families including legacy */
cbe61d8a 308static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 309{
c46917bb 310 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 311 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 312 u32 regHold[2];
07b2fa5a
JP		 313 static const u32 patternData[4] = {
314 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
315 };
1f3f0618 316 int i, j, loop_max;
f078f209 317
1f3f0618
SB		 318 if (!AR_SREV_9300_20_OR_LATER(ah)) {
319 loop_max = 2;
320 regAddr[1] = AR_PHY_BASE + (8 << 2);
321 } else
322 loop_max = 1;
323
324 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 325 u32 addr = regAddr[i];
326 u32 wrData, rdData;
f078f209 327
f1dc5600
S		 328 regHold[i] = REG_READ(ah, addr);
329 for (j = 0; j < 0x100; j++) {
330 wrData = (j << 16) | j;
331 REG_WRITE(ah, addr, wrData);
332 rdData = REG_READ(ah, addr);
333 if (rdData != wrData) {
c46917bb
LR		 334 ath_print(common, ATH_DBG_FATAL,
335 "address test failed "
336 "addr: 0x%08x - wr:0x%08x != "
337 "rd:0x%08x\n",
338 addr, wrData, rdData);
f1dc5600
S		 339 return false;
340 }
341 }
342 for (j = 0; j < 4; j++) {
343 wrData = patternData[j];
344 REG_WRITE(ah, addr, wrData);
345 rdData = REG_READ(ah, addr);
346 if (wrData != rdData) {
c46917bb
LR		 347 ath_print(common, ATH_DBG_FATAL,
348 "address test failed "
349 "addr: 0x%08x - wr:0x%08x != "
350 "rd:0x%08x\n",
351 addr, wrData, rdData);
f1dc5600
S		 352 return false;
353 }
f078f209 354 }
f1dc5600 355 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 356 }
f1dc5600 357 udelay(100);
cbe61d8a 358
f078f209
LR		 359 return true;
360}
361
b8b0f377 362static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 363{
364 int i;
f078f209 365
2660b81a
S		 366 ah->config.dma_beacon_response_time = 2;
367 ah->config.sw_beacon_response_time = 10;
368 ah->config.additional_swba_backoff = 0;
369 ah->config.ack_6mb = 0x0;
370 ah->config.cwm_ignore_extcca = 0;
371 ah->config.pcie_powersave_enable = 0;
2660b81a 372 ah->config.pcie_clock_req = 0;
2660b81a
S		 373 ah->config.pcie_waen = 0;
374 ah->config.analog_shiftreg = 1;
03c72518 375 ah->config.enable_ani = true;
f078f209 376
f1dc5600 377 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 378 ah->config.spurchans[i][0] = AR_NO_SPUR;
379 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 380 }
381
5ffaf8a3
LR		 382 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
383 ah->config.ht_enable = 1;
384 else
385 ah->config.ht_enable = 0;
386
0ce024cb 387 ah->config.rx_intr_mitigation = true;
6a0ec30a 388 ah->config.pcieSerDesWrite = true;
6158425b
LR		 389
390 /*
391 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
392 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
393 * This means we use it for all AR5416 devices, and the few
394 * minor PCI AR9280 devices out there.
395 *
396 * Serialization is required because these devices do not handle
397 * well the case of two concurrent reads/writes due to the latency
398 * involved. During one read/write another read/write can be issued
399 * on another CPU while the previous read/write may still be working
400 * on our hardware, if we hit this case the hardware poops in a loop.
401 * We prevent this by serializing reads and writes.
402 *
403 * This issue is not present on PCI-Express devices or pre-AR5416
404 * devices (legacy, 802.11abg).
405 */
406 if (num_possible_cpus() > 1)
2d6a5e95 407 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 408}
409
50aca25b 410static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 411{
608b88cb
LR		 412 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
413
414 regulatory->country_code = CTRY_DEFAULT;
415 regulatory->power_limit = MAX_RATE_POWER;
416 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
417
d535a42a 418 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 419 ah->hw_version.subvendorid = 0;
f078f209 420
2660b81a 421 ah->atim_window = 0;
16f2411f
FF		 422 ah->sta_id1_defaults =
423 AR_STA_ID1_CRPT_MIC_ENABLE |
424 AR_STA_ID1_MCAST_KSRCH;
2660b81a
S		 425 ah->beacon_interval = 100;
426 ah->enable_32kHz_clock = DONT_USE_32KHZ;
427 ah->slottime = (u32) -1;
2660b81a 428 ah->globaltxtimeout = (u32) -1;
cbdec975 429 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 430}
431
cbe61d8a 432static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 433{
1510718d 434 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 435 u32 sum;
436 int i;
437 u16 eeval;
07b2fa5a 438 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 439
440 sum = 0;
441 for (i = 0; i < 3; i++) {
49101676 442 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 443 sum += eeval;
1510718d
LR		 444 common->macaddr[2 * i] = eeval >> 8;
445 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 446 }
d8baa939 447 if (sum == 0 || sum == 0xffff * 3)
f078f209 448 return -EADDRNOTAVAIL;
f078f209
LR		 449
450 return 0;
451}
452
f637cfd6 453static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 454{
f1dc5600 455 int ecode;
f078f209 456
527d485f
S		 457 if (!AR_SREV_9271(ah)) {
458 if (!ath9k_hw_chip_test(ah))
459 return -ENODEV;
460 }
f078f209 461
ebd5a14a
LR		 462 if (!AR_SREV_9300_20_OR_LATER(ah)) {
463 ecode = ar9002_hw_rf_claim(ah);
464 if (ecode != 0)
465 return ecode;
466 }
f078f209 467
f637cfd6 468 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 469 if (ecode != 0)
470 return ecode;
7d01b221 471
c46917bb
LR		 472 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
473 "Eeprom VER: %d, REV: %d\n",
474 ah->eep_ops->get_eeprom_ver(ah),
475 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 476
8fe65368
LR		 477 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
478 if (ecode) {
479 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
480 "Failed allocating banks for "
481 "external radio\n");
482 return ecode;
574d6b12 483 }
f078f209 484
f1dc5600
S		 485 if (!AR_SREV_9100(ah)) {
486 ath9k_hw_ani_setup(ah);
f637cfd6 487 ath9k_hw_ani_init(ah);
f078f209
LR		 488 }
489
f078f209
LR		 490 return 0;
491}
492
8525f280 493static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 494{
8525f280
LR		 495 if (AR_SREV_9300_20_OR_LATER(ah))
496 ar9003_hw_attach_ops(ah);
497 else
498 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 499}
500
d70357d5
LR		 501/* Called for all hardware families */
502static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 503{
c46917bb 504 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 505 int r = 0;
aa4058ae 506
bab1f62e
LR		 507 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
508 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
aa4058ae
LR		 509
510 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 511 ath_print(common, ATH_DBG_FATAL,
512 "Couldn't reset chip\n");
95fafca2 513 return -EIO;
aa4058ae
LR		 514 }
515
bab1f62e
LR		 516 ath9k_hw_init_defaults(ah);
517 ath9k_hw_init_config(ah);
518
8525f280 519 ath9k_hw_attach_ops(ah);
d70357d5 520
9ecdef4b 521 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 522 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 523 return -EIO;
aa4058ae
LR		 524 }
525
526 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
527 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
4c85ab11
JL		 528 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
529 !ah->is_pciexpress)) {
aa4058ae
LR		 530 ah->config.serialize_regmode =
531 SER_REG_MODE_ON;
532 } else {
533 ah->config.serialize_regmode =
534 SER_REG_MODE_OFF;
535 }
536 }
537
c46917bb 538 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 539 ah->config.serialize_regmode);
540
f4709fdf
LR		 541 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
542 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
543 else
544 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
545
d70357d5 546 if (!ath9k_hw_macversion_supported(ah)) {
c46917bb
LR		 547 ath_print(common, ATH_DBG_FATAL,
548 "Mac Chip Rev 0x%02x.%x is not supported by "
549 "this driver\n", ah->hw_version.macVersion,
550 ah->hw_version.macRev);
95fafca2 551 return -EOPNOTSUPP;
aa4058ae
LR		 552 }
553
0df13da4 554 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
d7e7d229
LR		 555 ah->is_pciexpress = false;
556
aa4058ae 557 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 558 ath9k_hw_init_cal_settings(ah);
559
560 ah->ani_function = ATH9K_ANI_ALL;
7a37081e 561 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 562 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 563 if (!AR_SREV_9300_20_OR_LATER(ah))
564 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae
LR		 565
566 ath9k_hw_init_mode_regs(ah);
567
9a658d2b
LR		 568 /*
569 * Read back AR_WA into a permanent copy and set bits 14 and 17.
570 * We need to do this to avoid RMW of this register. We cannot
571 * read the reg when chip is asleep.
572 */
573 ah->WARegVal = REG_READ(ah, AR_WA);
574 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
575 AR_WA_ASPM_TIMER_BASED_DISABLE);
576
aa4058ae 577 if (ah->is_pciexpress)
93b1b37f 578 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 579 else
580 ath9k_hw_disablepcie(ah);
581
d8f492b7
LR		 582 if (!AR_SREV_9300_20_OR_LATER(ah))
583 ar9002_hw_cck_chan14_spread(ah);
193cd458 584
f637cfd6 585 r = ath9k_hw_post_init(ah);
aa4058ae 586 if (r)
95fafca2 587 return r;
aa4058ae
LR		 588
589 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 590 r = ath9k_hw_fill_cap_info(ah);
591 if (r)
592 return r;
593
4f3acf81
LR		 594 r = ath9k_hw_init_macaddr(ah);
595 if (r) {
c46917bb
LR		 596 ath_print(common, ATH_DBG_FATAL,
597 "Failed to initialize MAC address\n");
95fafca2 598 return r;
f078f209
LR		 599 }
600
d7e7d229 601 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 602 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 603 else
2660b81a 604 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 605
aea702b7 606 ah->bb_watchdog_timeout_ms = 25;
f078f209 607
211f5859
LR		 608 common->state = ATH_HW_INITIALIZED;
609
4f3acf81 610 return 0;
f078f209
LR		 611}
612
d70357d5 613int ath9k_hw_init(struct ath_hw *ah)
f078f209 614{
d70357d5
LR		 615 int ret;
616 struct ath_common *common = ath9k_hw_common(ah);
f078f209 617
d70357d5
LR		 618 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
619 switch (ah->hw_version.devid) {
620 case AR5416_DEVID_PCI:
621 case AR5416_DEVID_PCIE:
622 case AR5416_AR9100_DEVID:
623 case AR9160_DEVID_PCI:
624 case AR9280_DEVID_PCI:
625 case AR9280_DEVID_PCIE:
626 case AR9285_DEVID_PCIE:
db3cc53a
SB		 627 case AR9287_DEVID_PCI:
628 case AR9287_DEVID_PCIE:
d70357d5 629 case AR2427_DEVID_PCIE:
db3cc53a 630 case AR9300_DEVID_PCIE:
d70357d5
LR		 631 break;
632 default:
633 if (common->bus_ops->ath_bus_type == ATH_USB)
634 break;
635 ath_print(common, ATH_DBG_FATAL,
636 "Hardware device ID 0x%04x not supported\n",
637 ah->hw_version.devid);
638 return -EOPNOTSUPP;
639 }
f078f209 640
d70357d5
LR		 641 ret = __ath9k_hw_init(ah);
642 if (ret) {
643 ath_print(common, ATH_DBG_FATAL,
644 "Unable to initialize hardware; "
645 "initialization status: %d\n", ret);
646 return ret;
647 }
f078f209 648
d70357d5 649 return 0;
f078f209 650}
d70357d5 651EXPORT_SYMBOL(ath9k_hw_init);
f078f209 652
cbe61d8a 653static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 654{
7d0d0df0
S		 655 ENABLE_REGWRITE_BUFFER(ah);
656
f1dc5600
S		 657 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
658 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 659
f1dc5600
S		 660 REG_WRITE(ah, AR_QOS_NO_ACK,
661 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
662 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
663 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
664
665 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
666 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
667 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
668 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 670
671 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 672}
673
cbe61d8a 674static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 675 struct ath9k_channel *chan)
f078f209 676{
64773964 677 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 678
d03a66c1 679 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 680
c75724d1
LR		 681 /* Switch the core clock for ar9271 to 117Mhz */
682 if (AR_SREV_9271(ah)) {
25e2ab17
S		 683 udelay(500);
684 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 685 }
686
f1dc5600
S		 687 udelay(RTC_PLL_SETTLE_DELAY);
688
689 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 690}
691
cbe61d8a 692static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 693 enum nl80211_iftype opmode)
f078f209 694{
152d530d 695 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 696 AR_IMR_TXURN |
697 AR_IMR_RXERR |
698 AR_IMR_RXORN |
699 AR_IMR_BCNMISC;
f078f209 700
66860240
VT		 701 if (AR_SREV_9300_20_OR_LATER(ah)) {
702 imr_reg |= AR_IMR_RXOK_HP;
703 if (ah->config.rx_intr_mitigation)
704 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
705 else
706 imr_reg |= AR_IMR_RXOK_LP;
f078f209 707
66860240
VT		 708 } else {
709 if (ah->config.rx_intr_mitigation)
710 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
711 else
712 imr_reg |= AR_IMR_RXOK;
713 }
f078f209 714
66860240
VT		 715 if (ah->config.tx_intr_mitigation)
716 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
717 else
718 imr_reg |= AR_IMR_TXOK;
f078f209 719
d97809db 720 if (opmode == NL80211_IFTYPE_AP)
152d530d 721 imr_reg |= AR_IMR_MIB;
f078f209 722
7d0d0df0
S		 723 ENABLE_REGWRITE_BUFFER(ah);
724
152d530d 725 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 726 ah->imrs2_reg |= AR_IMR_S2_GTT;
727 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 728
f1dc5600
S		 729 if (!AR_SREV_9100(ah)) {
730 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
731 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
732 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
733 }
66860240 734
7d0d0df0 735 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 736
66860240
VT		 737 if (AR_SREV_9300_20_OR_LATER(ah)) {
738 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
739 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
740 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
741 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
742 }
f078f209
LR		 743}
744
0005baf4 745static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 746{
0005baf4
FF		 747 u32 val = ath9k_hw_mac_to_clks(ah, us);
748 val = min(val, (u32) 0xFFFF);
749 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 750}
751
0005baf4 752static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 753{
0005baf4
FF		 754 u32 val = ath9k_hw_mac_to_clks(ah, us);
755 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
756 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
757}
758
759static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
760{
761 u32 val = ath9k_hw_mac_to_clks(ah, us);
762 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
763 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 764}
f1dc5600 765
cbe61d8a 766static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 767{
f078f209 768 if (tu > 0xFFFF) {
c46917bb
LR		 769 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
770 "bad global tx timeout %u\n", tu);
2660b81a 771 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 772 return false;
773 } else {
774 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 775 ah->globaltxtimeout = tu;
f078f209
LR		 776 return true;
777 }
778}
779
0005baf4 780void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 781{
0005baf4
FF		 782 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
783 int acktimeout;
e239d859 784 int slottime;
0005baf4
FF		 785 int sifstime;
786
c46917bb
LR		 787 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
788 ah->misc_mode);
f078f209 789
2660b81a 790 if (ah->misc_mode != 0)
f1dc5600 791 REG_WRITE(ah, AR_PCU_MISC,
2660b81a 792 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
0005baf4
FF		 793
794 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
795 sifstime = 16;
796 else
797 sifstime = 10;
798
e239d859
FF		 799 /* As defined by IEEE 802.11-2007 17.3.8.6 */
800 slottime = ah->slottime + 3 * ah->coverage_class;
801 acktimeout = slottime + sifstime;
42c4568a
FF		 802
803 /*
804 * Workaround for early ACK timeouts, add an offset to match the
805 * initval's 64us ack timeout value.
806 * This was initially only meant to work around an issue with delayed
807 * BA frames in some implementations, but it has been found to fix ACK
808 * timeout issues in other cases as well.
809 */
810 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
811 acktimeout += 64 - sifstime - ah->slottime;
812
e239d859 813 ath9k_hw_setslottime(ah, slottime);
0005baf4
FF		 814 ath9k_hw_set_ack_timeout(ah, acktimeout);
815 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 816 if (ah->globaltxtimeout != (u32) -1)
817 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 818}
0005baf4 819EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 820
285f2dda 821void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 822{
211f5859
LR		 823 struct ath_common *common = ath9k_hw_common(ah);
824
736b3a27 825 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 826 goto free_hw;
827
9ecdef4b 828 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 829
830free_hw:
8fe65368 831 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 832}
285f2dda 833EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 834
f1dc5600
S		 835/*******/
836/* INI */
837/*******/
838
8fe65368 839u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 840{
841 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
842
843 if (IS_CHAN_B(chan))
844 ctl |= CTL_11B;
845 else if (IS_CHAN_G(chan))
846 ctl |= CTL_11G;
847 else
848 ctl |= CTL_11A;
849
850 return ctl;
851}
852
f1dc5600
S		 853/****************************************/
854/* Reset and Channel Switching Routines */
855/****************************************/
f1dc5600 856
cbe61d8a 857static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 858{
57b32227 859 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 860 u32 regval;
861
7d0d0df0
S		 862 ENABLE_REGWRITE_BUFFER(ah);
863
d7e7d229
LR		 864 /*
865 * set AHB_MODE not to do cacheline prefetches
866 */
57b32227
FF		 867 if (!AR_SREV_9300_20_OR_LATER(ah)) {
868 regval = REG_READ(ah, AR_AHB_MODE);
869 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
870 }
f1dc5600 871
d7e7d229
LR		 872 /*
873 * let mac dma reads be in 128 byte chunks
874 */
f1dc5600
S		 875 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
876 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
877
7d0d0df0 878 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 879
d7e7d229
LR		 880 /*
881 * Restore TX Trigger Level to its pre-reset value.
882 * The initial value depends on whether aggregation is enabled, and is
883 * adjusted whenever underruns are detected.
884 */
57b32227
FF		 885 if (!AR_SREV_9300_20_OR_LATER(ah))
886 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 887
7d0d0df0 888 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 889
d7e7d229
LR		 890 /*
891 * let mac dma writes be in 128 byte chunks
892 */
f1dc5600
S		 893 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
894 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
895
d7e7d229
LR		 896 /*
897 * Setup receive FIFO threshold to hold off TX activities
898 */
f1dc5600
S		 899 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
900
57b32227
FF		 901 if (AR_SREV_9300_20_OR_LATER(ah)) {
902 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
903 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
904
905 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
906 ah->caps.rx_status_len);
907 }
908
d7e7d229
LR		 909 /*
910 * reduce the number of usable entries in PCU TXBUF to avoid
911 * wrap around issues.
912 */
f1dc5600 913 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 914 /* For AR9285 the number of Fifos are reduced to half.
915 * So set the usable tx buf size also to half to
916 * avoid data/delimiter underruns
917 */
f1dc5600
S		 918 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
919 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 920 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 921 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
922 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
923 }
744d4025 924
7d0d0df0 925 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 926
744d4025
VT		 927 if (AR_SREV_9300_20_OR_LATER(ah))
928 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 929}
930
cbe61d8a 931static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 932{
933 u32 val;
934
935 val = REG_READ(ah, AR_STA_ID1);
936 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
937 switch (opmode) {
d97809db 938 case NL80211_IFTYPE_AP:
f1dc5600
S		 939 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
940 | AR_STA_ID1_KSRCH_MODE);
941 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 942 break;
d97809db 943 case NL80211_IFTYPE_ADHOC:
9cb5412b 944 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 945 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
946 | AR_STA_ID1_KSRCH_MODE);
947 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 948 break;
d97809db
CM		 949 case NL80211_IFTYPE_STATION:
950 case NL80211_IFTYPE_MONITOR:
f1dc5600 951 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 952 break;
f1dc5600
S		 953 }
954}
955
8fe65368
LR		 956void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
957 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 958{
959 u32 coef_exp, coef_man;
960
961 for (coef_exp = 31; coef_exp > 0; coef_exp--)
962 if ((coef_scaled >> coef_exp) & 0x1)
963 break;
964
965 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
966
967 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
968
969 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
970 *coef_exponent = coef_exp - 16;
971}
972
cbe61d8a 973static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 974{
975 u32 rst_flags;
976 u32 tmpReg;
977
70768496
S		 978 if (AR_SREV_9100(ah)) {
979 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
980 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
981 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
982 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
983 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
984 }
985
7d0d0df0
S		 986 ENABLE_REGWRITE_BUFFER(ah);
987
9a658d2b
LR		 988 if (AR_SREV_9300_20_OR_LATER(ah)) {
989 REG_WRITE(ah, AR_WA, ah->WARegVal);
990 udelay(10);
991 }
992
f1dc5600
S		 993 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
994 AR_RTC_FORCE_WAKE_ON_INT);
995
996 if (AR_SREV_9100(ah)) {
997 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
998 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
999 } else {
1000 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1001 if (tmpReg &
1002 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1003 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1004 u32 val;
f1dc5600 1005 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1006
1007 val = AR_RC_HOSTIF;
1008 if (!AR_SREV_9300_20_OR_LATER(ah))
1009 val |= AR_RC_AHB;
1010 REG_WRITE(ah, AR_RC, val);
1011
1012 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1013 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1014
1015 rst_flags = AR_RTC_RC_MAC_WARM;
1016 if (type == ATH9K_RESET_COLD)
1017 rst_flags |= AR_RTC_RC_MAC_COLD;
1018 }
1019
d03a66c1 1020 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1021
1022 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1023
f1dc5600
S		 1024 udelay(50);
1025
d03a66c1 1026 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1027 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1028 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1029 "RTC stuck in MAC reset\n");
f1dc5600
S		 1030 return false;
1031 }
1032
1033 if (!AR_SREV_9100(ah))
1034 REG_WRITE(ah, AR_RC, 0);
1035
f1dc5600
S		 1036 if (AR_SREV_9100(ah))
1037 udelay(50);
1038
1039 return true;
1040}
1041
cbe61d8a 1042static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1043{
7d0d0df0
S		 1044 ENABLE_REGWRITE_BUFFER(ah);
1045
9a658d2b
LR		 1046 if (AR_SREV_9300_20_OR_LATER(ah)) {
1047 REG_WRITE(ah, AR_WA, ah->WARegVal);
1048 udelay(10);
1049 }
1050
f1dc5600
S		 1051 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1052 AR_RTC_FORCE_WAKE_ON_INT);
1053
42d5bc3f 1054 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1055 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1056
d03a66c1 1057 REG_WRITE(ah, AR_RTC_RESET, 0);
ee031112 1058 udelay(2);
1c29ce67 1059
7d0d0df0 1060 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1061
84e2169b
SB		 1062 if (!AR_SREV_9300_20_OR_LATER(ah))
1063 udelay(2);
1064
1065 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1066 REG_WRITE(ah, AR_RC, 0);
1067
d03a66c1 1068 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1069
1070 if (!ath9k_hw_wait(ah,
1071 AR_RTC_STATUS,
1072 AR_RTC_STATUS_M,
0caa7b14
S		 1073 AR_RTC_STATUS_ON,
1074 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1075 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1076 "RTC not waking up\n");
f1dc5600 1077 return false;
f078f209
LR		 1078 }
1079
f1dc5600
S		 1080 ath9k_hw_read_revisions(ah);
1081
1082 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1083}
1084
cbe61d8a 1085static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1086{
9a658d2b
LR		 1087 if (AR_SREV_9300_20_OR_LATER(ah)) {
1088 REG_WRITE(ah, AR_WA, ah->WARegVal);
1089 udelay(10);
1090 }
1091
f1dc5600
S		 1092 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1093 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1094
1095 switch (type) {
1096 case ATH9K_RESET_POWER_ON:
1097 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1098 case ATH9K_RESET_WARM:
1099 case ATH9K_RESET_COLD:
1100 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1101 default:
1102 return false;
1103 }
f078f209
LR		 1104}
1105
cbe61d8a 1106static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1107 struct ath9k_channel *chan)
f078f209 1108{
42abfbee 1109 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1110 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1111 return false;
1112 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1113 return false;
f078f209 1114
9ecdef4b 1115 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1116 return false;
f078f209 1117
2660b81a 1118 ah->chip_fullsleep = false;
f1dc5600 1119 ath9k_hw_init_pll(ah, chan);
f1dc5600 1120 ath9k_hw_set_rfmode(ah, chan);
f078f209 1121
f1dc5600 1122 return true;
f078f209
LR		 1123}
1124
cbe61d8a 1125static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1126 struct ath9k_channel *chan)
f078f209 1127{
608b88cb 1128 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1129 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1130 struct ieee80211_channel *channel = chan->chan;
8fe65368 1131 u32 qnum;
0a3b7bac 1132 int r;
f078f209
LR		 1133
1134 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1135 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1136 ath_print(common, ATH_DBG_QUEUE,
1137 "Transmit frames pending on "
1138 "queue %d\n", qnum);
f078f209
LR		 1139 return false;
1140 }
1141 }
1142
8fe65368 1143 if (!ath9k_hw_rfbus_req(ah)) {
c46917bb
LR		 1144 ath_print(common, ATH_DBG_FATAL,
1145 "Could not kill baseband RX\n");
f078f209
LR		 1146 return false;
1147 }
1148
8fe65368 1149 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1150
8fe65368 1151 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1152 if (r) {
1153 ath_print(common, ATH_DBG_FATAL,
1154 "Failed to set channel\n");
1155 return false;
f078f209 1156 }
dfdac8ac 1157 ath9k_hw_set_clockrate(ah);
f078f209 1158
8fbff4b8 1159 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1160 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1161 channel->max_antenna_gain * 2,
1162 channel->max_power * 2,
1163 min((u32) MAX_RATE_POWER,
de40f316 1164 (u32) regulatory->power_limit), false);
f078f209 1165
8fe65368 1166 ath9k_hw_rfbus_done(ah);
f078f209 1167
f1dc5600
S		 1168 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1169 ath9k_hw_set_delta_slope(ah, chan);
1170
8fe65368 1171 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1172
f1dc5600
S		 1173 return true;
1174}
1175
c9c99e5e 1176bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1177{
c9c99e5e
FF		 1178 int count = 50;
1179 u32 reg;
1180
e17f83ea 1181 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1182 return true;
1183
1184 do {
1185 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1186
c9c99e5e
FF		 1187 if ((reg & 0x7E7FFFEF) == 0x00702400)
1188 continue;
1189
1190 switch (reg & 0x7E000B00) {
1191 case 0x1E000000:
1192 case 0x52000B00:
1193 case 0x18000B00:
1194 continue;
1195 default:
1196 return true;
1197 }
1198 } while (count-- > 0);
3b319aae 1199
c9c99e5e 1200 return false;
3b319aae 1201}
c9c99e5e 1202EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1203
cbe61d8a 1204int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 1205 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
f078f209 1206{
1510718d 1207 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1208 u32 saveLedState;
2660b81a 1209 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1210 u32 saveDefAntenna;
1211 u32 macStaId1;
46fe782c 1212 u64 tsf = 0;
8fe65368 1213 int i, r;
f078f209 1214
43c27613
LR		 1215 ah->txchainmask = common->tx_chainmask;
1216 ah->rxchainmask = common->rx_chainmask;
f078f209 1217
9b9cc61c
VT		 1218 if (!ah->chip_fullsleep) {
1219 ath9k_hw_abortpcurecv(ah);
9cc2f3e8 1220 if (!ath9k_hw_stopdmarecv(ah)) {
9b9cc61c
VT		 1221 ath_print(common, ATH_DBG_XMIT,
1222 "Failed to stop receive dma\n");
9cc2f3e8
FF		 1223 bChannelChange = false;
1224 }
9b9cc61c
VT		 1225 }
1226
9ecdef4b 1227 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1228 return -EIO;
f078f209 1229
d9891c78 1230 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1231 ath9k_hw_getnf(ah, curchan);
1232
20bd2a09
FF		 1233 ah->caldata = caldata;
1234 if (caldata &&
1235 (chan->channel != caldata->channel ||
1236 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1237 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1238 /* Operating channel changed, reset channel calibration data */
1239 memset(caldata, 0, sizeof(*caldata));
1240 ath9k_init_nfcal_hist_buffer(ah, chan);
1241 }
1242
f078f209 1243 if (bChannelChange &&
2660b81a
S		 1244 (ah->chip_fullsleep != true) &&
1245 (ah->curchan != NULL) &&
1246 (chan->channel != ah->curchan->channel) &&
f078f209 1247 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1248 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
58d7e0f3 1249 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
f078f209 1250
25c56eec 1251 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1252 ath9k_hw_loadnf(ah, ah->curchan);
00c86590 1253 ath9k_hw_start_nfcal(ah, true);
c2ba3342
RM		 1254 if (AR_SREV_9271(ah))
1255 ar9002_hw_load_ani_reg(ah, chan);
ae8d2858 1256 return 0;
f078f209
LR		 1257 }
1258 }
1259
1260 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1261 if (saveDefAntenna == 0)
1262 saveDefAntenna = 1;
1263
1264 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1265
46fe782c 1266 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1267 if (AR_SREV_9100(ah) ||
1268 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1269 tsf = ath9k_hw_gettsf64(ah);
1270
f078f209
LR		 1271 saveLedState = REG_READ(ah, AR_CFG_LED) &
1272 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1273 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1274
1275 ath9k_hw_mark_phy_inactive(ah);
1276
05020d23 1277 /* Only required on the first reset */
d7e7d229
LR		 1278 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1279 REG_WRITE(ah,
1280 AR9271_RESET_POWER_DOWN_CONTROL,
1281 AR9271_RADIO_RF_RST);
1282 udelay(50);
1283 }
1284
f078f209 1285 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1286 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1287 return -EINVAL;
f078f209
LR		 1288 }
1289
05020d23 1290 /* Only required on the first reset */
d7e7d229
LR		 1291 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1292 ah->htc_reset_init = false;
1293 REG_WRITE(ah,
1294 AR9271_RESET_POWER_DOWN_CONTROL,
1295 AR9271_GATE_MAC_CTL);
1296 udelay(50);
1297 }
1298
46fe782c 1299 /* Restore TSF */
f860d526 1300 if (tsf)
46fe782c
S		 1301 ath9k_hw_settsf64(ah, tsf);
1302
7a37081e 1303 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1304 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1305
e9141f71
S		 1306 if (!AR_SREV_9300_20_OR_LATER(ah))
1307 ar9002_hw_enable_async_fifo(ah);
1308
25c56eec 1309 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1310 if (r)
1311 return r;
f078f209 1312
f860d526
FF		 1313 /*
1314 * Some AR91xx SoC devices frequently fail to accept TSF writes
1315 * right after the chip reset. When that happens, write a new
1316 * value after the initvals have been applied, with an offset
1317 * based on measured time difference
1318 */
1319 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1320 tsf += 1500;
1321 ath9k_hw_settsf64(ah, tsf);
1322 }
1323
0ced0e17
JM		 1324 /* Setup MFP options for CCMP */
1325 if (AR_SREV_9280_20_OR_LATER(ah)) {
1326 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1327 * frames when constructing CCMP AAD. */
1328 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1329 0xc7ff);
1330 ah->sw_mgmt_crypto = false;
1331 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1332 /* Disable hardware crypto for management frames */
1333 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1334 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1335 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1336 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1337 ah->sw_mgmt_crypto = true;
1338 } else
1339 ah->sw_mgmt_crypto = true;
1340
f078f209
LR		 1341 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1342 ath9k_hw_set_delta_slope(ah, chan);
1343
8fe65368 1344 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1345 ah->eep_ops->set_board_values(ah, chan);
a7765828 1346
6819d57f
S		 1347 ath9k_hw_set_operating_mode(ah, ah->opmode);
1348
7d0d0df0
S		 1349 ENABLE_REGWRITE_BUFFER(ah);
1350
1510718d
LR		 1351 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1352 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1353 | macStaId1
1354 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1355 | (ah->config.
60b67f51 1356 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1357 | ah->sta_id1_defaults);
13b81559 1358 ath_hw_setbssidmask(common);
f078f209 1359 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1360 ath9k_hw_write_associd(ah);
f078f209 1361 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1362 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1363
7d0d0df0 1364 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1365
8fe65368 1366 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1367 if (r)
1368 return r;
f078f209 1369
dfdac8ac
FF		 1370 ath9k_hw_set_clockrate(ah);
1371
7d0d0df0
S		 1372 ENABLE_REGWRITE_BUFFER(ah);
1373
f078f209
LR		 1374 for (i = 0; i < AR_NUM_DCU; i++)
1375 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1376
7d0d0df0 1377 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1378
2660b81a
S		 1379 ah->intr_txqs = 0;
1380 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 1381 ath9k_hw_resettxqueue(ah, i);
1382
2660b81a 1383 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1384 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1385 ath9k_hw_init_qos(ah);
1386
2660b81a 1387 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 1388 ath9k_enable_rfkill(ah);
3b319aae 1389
0005baf4 1390 ath9k_hw_init_global_settings(ah);
f078f209 1391
6c94fdc9 1392 if (!AR_SREV_9300_20_OR_LATER(ah)) {
e9141f71 1393 ar9002_hw_update_async_fifo(ah);
6c94fdc9 1394 ar9002_hw_enable_wep_aggregation(ah);
ac88b6ec
VN		 1395 }
1396
f078f209
LR		 1397 REG_WRITE(ah, AR_STA_ID1,
1398 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1399
1400 ath9k_hw_set_dma(ah);
1401
1402 REG_WRITE(ah, AR_OBS, 8);
1403
0ce024cb 1404 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1405 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1406 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1407 }
1408
7f62a136
VT		 1409 if (ah->config.tx_intr_mitigation) {
1410 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1411 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1412 }
1413
f078f209
LR		 1414 ath9k_hw_init_bb(ah, chan);
1415
ae8d2858 1416 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1417 return -EIO;
f078f209 1418
7d0d0df0 1419 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1420
8fe65368 1421 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1422 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1423
7d0d0df0 1424 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1425
d7e7d229
LR		 1426 /*
1427 * For big endian systems turn on swapping for descriptors
1428 */
f078f209
LR		 1429 if (AR_SREV_9100(ah)) {
1430 u32 mask;
1431 mask = REG_READ(ah, AR_CFG);
1432 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 1433 ath_print(common, ATH_DBG_RESET,
04bd4638 1434 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1435 } else {
1436 mask =
1437 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1438 REG_WRITE(ah, AR_CFG, mask);
c46917bb 1439 ath_print(common, ATH_DBG_RESET,
04bd4638 1440 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1441 }
1442 } else {
cbba8cd1
S		 1443 if (common->bus_ops->ath_bus_type == ATH_USB) {
1444 /* Configure AR9271 target WLAN */
1445 if (AR_SREV_9271(ah))
1446 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1447 else
1448 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1449 }
f078f209 1450#ifdef __BIG_ENDIAN
d7e7d229
LR		 1451 else
1452 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1453#endif
1454 }
1455
766ec4a9 1456 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1457 ath9k_hw_btcoex_enable(ah);
1458
00c86590 1459 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 1460 ar9003_hw_bb_watchdog_config(ah);
d8903a53 1461
ae8d2858 1462 return 0;
f078f209 1463}
7322fd19 1464EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1465
f1dc5600
S		 1466/******************************/
1467/* Power Management (Chipset) */
1468/******************************/
1469
42d5bc3f
LR		 1470/*
1471 * Notify Power Mgt is disabled in self-generated frames.
1472 * If requested, force chip to sleep.
1473 */
cbe61d8a 1474static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1475{
f1dc5600
S		 1476 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1477 if (setChip) {
42d5bc3f
LR		 1478 /*
1479 * Clear the RTC force wake bit to allow the
1480 * mac to go to sleep.
1481 */
f1dc5600
S		 1482 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1483 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1484 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1485 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1486
42d5bc3f 1487 /* Shutdown chip. Active low */
14b3af38 1488 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1489 REG_CLR_BIT(ah, (AR_RTC_RESET),
1490 AR_RTC_RESET_EN);
f1dc5600 1491 }
9a658d2b
LR		 1492
1493 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1494 if (AR_SREV_9300_20_OR_LATER(ah))
1495 REG_WRITE(ah, AR_WA,
1496 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1497}
1498
bbd79af5
LR		 1499/*
1500 * Notify Power Management is enabled in self-generating
1501 * frames. If request, set power mode of chip to
1502 * auto/normal. Duration in units of 128us (1/8 TU).
1503 */
cbe61d8a 1504static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1505{
f1dc5600
S		 1506 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1507 if (setChip) {
2660b81a 1508 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1509
f1dc5600 1510 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1511 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1512 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1513 AR_RTC_FORCE_WAKE_ON_INT);
1514 } else {
bbd79af5
LR		 1515 /*
1516 * Clear the RTC force wake bit to allow the
1517 * mac to go to sleep.
1518 */
f1dc5600
S		 1519 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1520 AR_RTC_FORCE_WAKE_EN);
f078f209 1521 }
f078f209 1522 }
9a658d2b
LR		 1523
1524 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1525 if (AR_SREV_9300_20_OR_LATER(ah))
1526 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1527}
1528
cbe61d8a 1529static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1530{
f1dc5600
S		 1531 u32 val;
1532 int i;
f078f209 1533
9a658d2b
LR		 1534 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1535 if (AR_SREV_9300_20_OR_LATER(ah)) {
1536 REG_WRITE(ah, AR_WA, ah->WARegVal);
1537 udelay(10);
1538 }
1539
f1dc5600
S		 1540 if (setChip) {
1541 if ((REG_READ(ah, AR_RTC_STATUS) &
1542 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1543 if (ath9k_hw_set_reset_reg(ah,
1544 ATH9K_RESET_POWER_ON) != true) {
1545 return false;
1546 }
e041228f
LR		 1547 if (!AR_SREV_9300_20_OR_LATER(ah))
1548 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1549 }
1550 if (AR_SREV_9100(ah))
1551 REG_SET_BIT(ah, AR_RTC_RESET,
1552 AR_RTC_RESET_EN);
f078f209 1553
f1dc5600
S		 1554 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1555 AR_RTC_FORCE_WAKE_EN);
1556 udelay(50);
f078f209 1557
f1dc5600
S		 1558 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1559 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1560 if (val == AR_RTC_STATUS_ON)
1561 break;
1562 udelay(50);
1563 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1564 AR_RTC_FORCE_WAKE_EN);
f078f209 1565 }
f1dc5600 1566 if (i == 0) {
c46917bb
LR		 1567 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1568 "Failed to wakeup in %uus\n",
1569 POWER_UP_TIME / 20);
f1dc5600 1570 return false;
f078f209 1571 }
f078f209
LR		 1572 }
1573
f1dc5600 1574 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1575
f1dc5600 1576 return true;
f078f209
LR		 1577}
1578
9ecdef4b 1579bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1580{
c46917bb 1581 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1582 int status = true, setChip = true;
f1dc5600
S		 1583 static const char *modes[] = {
1584 "AWAKE",
1585 "FULL-SLEEP",
1586 "NETWORK SLEEP",
1587 "UNDEFINED"
1588 };
f1dc5600 1589
cbdec975
GJ		 1590 if (ah->power_mode == mode)
1591 return status;
1592
c46917bb
LR		 1593 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1594 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1595
1596 switch (mode) {
1597 case ATH9K_PM_AWAKE:
1598 status = ath9k_hw_set_power_awake(ah, setChip);
1599 break;
1600 case ATH9K_PM_FULL_SLEEP:
1601 ath9k_set_power_sleep(ah, setChip);
2660b81a 1602 ah->chip_fullsleep = true;
f1dc5600
S		 1603 break;
1604 case ATH9K_PM_NETWORK_SLEEP:
1605 ath9k_set_power_network_sleep(ah, setChip);
1606 break;
f078f209 1607 default:
c46917bb
LR		 1608 ath_print(common, ATH_DBG_FATAL,
1609 "Unknown power mode %u\n", mode);
f078f209
LR		 1610 return false;
1611 }
2660b81a 1612 ah->power_mode = mode;
f1dc5600
S		 1613
1614 return status;
f078f209 1615}
7322fd19 1616EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1617
f1dc5600
S		 1618/*******************/
1619/* Beacon Handling */
1620/*******************/
1621
cbe61d8a 1622void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 1623{
f078f209
LR		 1624 int flags = 0;
1625
2660b81a 1626 ah->beacon_interval = beacon_period;
f078f209 1627
7d0d0df0
S		 1628 ENABLE_REGWRITE_BUFFER(ah);
1629
2660b81a 1630 switch (ah->opmode) {
d97809db
CM		 1631 case NL80211_IFTYPE_STATION:
1632 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 1633 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1634 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1635 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1636 flags |= AR_TBTT_TIMER_EN;
1637 break;
d97809db 1638 case NL80211_IFTYPE_ADHOC:
9cb5412b 1639 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 1640 REG_SET_BIT(ah, AR_TXCFG,
1641 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1642 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1643 TU_TO_USEC(next_beacon +
2660b81a
S		 1644 (ah->atim_window ? ah->
1645 atim_window : 1)));
f078f209 1646 flags |= AR_NDP_TIMER_EN;
d97809db 1647 case NL80211_IFTYPE_AP:
f078f209
LR		 1648 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1649 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1650 TU_TO_USEC(next_beacon -
2660b81a 1651 ah->config.
60b67f51 1652 dma_beacon_response_time));
f078f209
LR		 1653 REG_WRITE(ah, AR_NEXT_SWBA,
1654 TU_TO_USEC(next_beacon -
2660b81a 1655 ah->config.
60b67f51 1656 sw_beacon_response_time));
f078f209
LR		 1657 flags |=
1658 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1659 break;
d97809db 1660 default:
c46917bb
LR		 1661 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1662 "%s: unsupported opmode: %d\n",
1663 __func__, ah->opmode);
d97809db
CM		 1664 return;
1665 break;
f078f209
LR		 1666 }
1667
1668 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1669 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1670 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1671 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1672
7d0d0df0 1673 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1674
f078f209
LR		 1675 beacon_period &= ~ATH9K_BEACON_ENA;
1676 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 1677 ath9k_hw_reset_tsf(ah);
1678 }
1679
1680 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1681}
7322fd19 1682EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 1683
cbe61d8a 1684void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 1685 const struct ath9k_beacon_state *bs)
f078f209
LR		 1686{
1687 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 1688 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1689 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1690
7d0d0df0
S		 1691 ENABLE_REGWRITE_BUFFER(ah);
1692
f078f209
LR		 1693 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1694
1695 REG_WRITE(ah, AR_BEACON_PERIOD,
1696 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1697 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1698 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1699
7d0d0df0 1700 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1701
f078f209
LR		 1702 REG_RMW_FIELD(ah, AR_RSSI_THR,
1703 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1704
1705 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1706
1707 if (bs->bs_sleepduration > beaconintval)
1708 beaconintval = bs->bs_sleepduration;
1709
1710 dtimperiod = bs->bs_dtimperiod;
1711 if (bs->bs_sleepduration > dtimperiod)
1712 dtimperiod = bs->bs_sleepduration;
1713
1714 if (beaconintval == dtimperiod)
1715 nextTbtt = bs->bs_nextdtim;
1716 else
1717 nextTbtt = bs->bs_nexttbtt;
1718
c46917bb
LR		 1719 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1720 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1721 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1722 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 1723
7d0d0df0
S		 1724 ENABLE_REGWRITE_BUFFER(ah);
1725
f1dc5600
S		 1726 REG_WRITE(ah, AR_NEXT_DTIM,
1727 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1728 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 1729
f1dc5600
S		 1730 REG_WRITE(ah, AR_SLEEP1,
1731 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1732 | AR_SLEEP1_ASSUME_DTIM);
f078f209 1733
f1dc5600
S		 1734 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1735 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1736 else
1737 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 1738
f1dc5600
S		 1739 REG_WRITE(ah, AR_SLEEP2,
1740 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 1741
f1dc5600
S		 1742 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1743 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 1744
7d0d0df0 1745 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1746
f1dc5600
S		 1747 REG_SET_BIT(ah, AR_TIMER_MODE,
1748 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1749 AR_DTIM_TIMER_EN);
f078f209 1750
4af9cf4f
S		 1751 /* TSF Out of Range Threshold */
1752 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 1753}
7322fd19 1754EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 1755
f1dc5600
S		 1756/*******************/
1757/* HW Capabilities */
1758/*******************/
1759
a9a29ce6 1760int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 1761{
2660b81a 1762 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 1763 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1764 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 1765 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 1766
f1dc5600 1767 u16 capField = 0, eeval;
754dc536 1768 u8 ant_div_ctl1;
f078f209 1769
f74df6fb 1770 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 1771 regulatory->current_rd = eeval;
f078f209 1772
f74df6fb 1773 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
e17f83ea 1774 if (AR_SREV_9285_12_OR_LATER(ah))
fec0de11 1775 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 1776 regulatory->current_rd_ext = eeval;
f078f209 1777
f74df6fb 1778 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 1779
2660b81a 1780 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 1781 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 1782 if (regulatory->current_rd == 0x64 ||
1783 regulatory->current_rd == 0x65)
1784 regulatory->current_rd += 5;
1785 else if (regulatory->current_rd == 0x41)
1786 regulatory->current_rd = 0x43;
c46917bb
LR		 1787 ath_print(common, ATH_DBG_REGULATORY,
1788 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 1789 }
f078f209 1790
f74df6fb 1791 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6
GJ		 1792 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1793 ath_print(common, ATH_DBG_FATAL,
1794 "no band has been marked as supported in EEPROM.\n");
1795 return -EINVAL;
1796 }
1797
d4659912
FF		 1798 if (eeval & AR5416_OPFLAGS_11A)
1799 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 1800
d4659912
FF		 1801 if (eeval & AR5416_OPFLAGS_11G)
1802 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 1803
f74df6fb 1804 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 1805 /*
1806 * For AR9271 we will temporarilly uses the rx chainmax as read from
1807 * the EEPROM.
1808 */
8147f5de 1809 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 1810 !(eeval & AR5416_OPFLAGS_11A) &&
1811 !(AR_SREV_9271(ah)))
1812 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 1813 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1814 else
d7e7d229 1815 /* Use rx_chainmask from EEPROM. */
8147f5de 1816 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 1817
7a37081e 1818 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 1819
f1dc5600
S		 1820 pCap->low_2ghz_chan = 2312;
1821 pCap->high_2ghz_chan = 2732;
f078f209 1822
f1dc5600
S		 1823 pCap->low_5ghz_chan = 4920;
1824 pCap->high_5ghz_chan = 6100;
f078f209 1825
ce2220d1
BR		 1826 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1827
2660b81a 1828 if (ah->config.ht_enable)
f1dc5600
S		 1829 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1830 else
1831 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 1832
f1dc5600
S		 1833 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1834 pCap->total_queues =
1835 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1836 else
1837 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 1838
f1dc5600
S		 1839 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1840 pCap->keycache_size =
1841 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
1842 else
1843 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 1844
f4709fdf
LR		 1845 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1846 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
1847 else
1848 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 1849
5b5fa355
S		 1850 if (AR_SREV_9271(ah))
1851 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 1852 else if (AR_DEVID_7010(ah))
1853 pCap->num_gpio_pins = AR7010_NUM_GPIO;
e17f83ea 1854 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 1855 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 1856 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 1857 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1858 else
1859 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 1860
f1dc5600
S		 1861 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1862 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1863 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1864 } else {
1865 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 1866 }
1867
f1dc5600
S		 1868 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
1869
e97275cb 1870#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 1871 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1872 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1873 ah->rfkill_gpio =
1874 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1875 ah->rfkill_polarity =
1876 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 1877
1878 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 1879 }
f1dc5600 1880#endif
d5d1154f 1881 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 1882 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1883 else
1884 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 1885
e7594072 1886 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 1887 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1888 else
1889 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 1890
608b88cb 1891 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 1892 pCap->reg_cap =
1893 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1894 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
1895 AR_EEPROM_EEREGCAP_EN_KK_U2 |
1896 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 1897 } else {
f1dc5600
S		 1898 pCap->reg_cap =
1899 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1900 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 1901 }
f078f209 1902
ebb90cfc
SB		 1903 /* Advertise midband for AR5416 with FCC midband set in eeprom */
1904 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
1905 AR_SREV_5416(ah))
1906 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 1907
1908 pCap->num_antcfg_5ghz =
f74df6fb 1909 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 1910 pCap->num_antcfg_2ghz =
f74df6fb 1911 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 1912
7a37081e 1913 if (AR_SREV_9280_20_OR_LATER(ah) &&
a36cfbca 1914 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 1915 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1916 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 1917
8c8f9ba7 1918 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 1919 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1920 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 1921 } else {
766ec4a9 1922 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 1923 }
22f25d0d 1924 } else {
766ec4a9 1925 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 1926 }
a9a29ce6 1927
ceb26445 1928 if (AR_SREV_9300_20_OR_LATER(ah)) {
e5553724
VT		 1929 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
1930 ATH9K_HW_CAP_FASTCLOCK;
ceb26445
VT		 1931 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1932 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1933 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 1934 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 1935 pCap->txs_len = sizeof(struct ar9003_txs);
4935250a
FF		 1936 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1937 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 1938 } else {
1939 pCap->tx_desc_len = sizeof(struct ath_desc);
6b42e8d0
FF		 1940 if (AR_SREV_9280_20(ah) &&
1941 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1942 AR5416_EEP_MINOR_VER_16) ||
1943 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1944 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 1945 }
1adf02ff 1946
6c84ce08
VT		 1947 if (AR_SREV_9300_20_OR_LATER(ah))
1948 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1949
6ee63f55
SB		 1950 if (AR_SREV_9300_20_OR_LATER(ah))
1951 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1952
a42acef0 1953 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 1954 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1955
754dc536
VT		 1956 if (AR_SREV_9285(ah))
1957 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1958 ant_div_ctl1 =
1959 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1960 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1961 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
1962 }
1963
a9a29ce6 1964 return 0;
f078f209
LR		 1965}
1966
f1dc5600
S		 1967/****************************/
1968/* GPIO / RFKILL / Antennae */
1969/****************************/
f078f209 1970
cbe61d8a 1971static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 1972 u32 gpio, u32 type)
1973{
1974 int addr;
1975 u32 gpio_shift, tmp;
f078f209 1976
f1dc5600
S		 1977 if (gpio > 11)
1978 addr = AR_GPIO_OUTPUT_MUX3;
1979 else if (gpio > 5)
1980 addr = AR_GPIO_OUTPUT_MUX2;
1981 else
1982 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 1983
f1dc5600 1984 gpio_shift = (gpio % 6) * 5;
f078f209 1985
f1dc5600
S		 1986 if (AR_SREV_9280_20_OR_LATER(ah)
1987 || (addr != AR_GPIO_OUTPUT_MUX1)) {
1988 REG_RMW(ah, addr, (type << gpio_shift),
1989 (0x1f << gpio_shift));
f078f209 1990 } else {
f1dc5600
S		 1991 tmp = REG_READ(ah, addr);
1992 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
1993 tmp &= ~(0x1f << gpio_shift);
1994 tmp |= (type << gpio_shift);
1995 REG_WRITE(ah, addr, tmp);
f078f209 1996 }
f078f209
LR		 1997}
1998
cbe61d8a 1999void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2000{
f1dc5600 2001 u32 gpio_shift;
f078f209 2002
9680e8a3 2003 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2004
88c1f4f6
S		 2005 if (AR_DEVID_7010(ah)) {
2006 gpio_shift = gpio;
2007 REG_RMW(ah, AR7010_GPIO_OE,
2008 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2009 (AR7010_GPIO_OE_MASK << gpio_shift));
2010 return;
2011 }
f078f209 2012
88c1f4f6 2013 gpio_shift = gpio << 1;
f1dc5600
S		 2014 REG_RMW(ah,
2015 AR_GPIO_OE_OUT,
2016 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2017 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2018}
7322fd19 2019EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2020
cbe61d8a 2021u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2022{
cb33c412
SB		 2023#define MS_REG_READ(x, y) \
2024 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2025
2660b81a 2026 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2027 return 0xffffffff;
f078f209 2028
88c1f4f6
S		 2029 if (AR_DEVID_7010(ah)) {
2030 u32 val;
2031 val = REG_READ(ah, AR7010_GPIO_IN);
2032 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2033 } else if (AR_SREV_9300_20_OR_LATER(ah))
783dfca1
FF		 2034 return MS_REG_READ(AR9300, gpio) != 0;
2035 else if (AR_SREV_9271(ah))
5b5fa355 2036 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2037 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2038 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2039 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2040 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2041 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2042 return MS_REG_READ(AR928X, gpio) != 0;
2043 else
2044 return MS_REG_READ(AR, gpio) != 0;
f078f209 2045}
7322fd19 2046EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2047
cbe61d8a 2048void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2049 u32 ah_signal_type)
f078f209 2050{
f1dc5600 2051 u32 gpio_shift;
f078f209 2052
88c1f4f6
S		 2053 if (AR_DEVID_7010(ah)) {
2054 gpio_shift = gpio;
2055 REG_RMW(ah, AR7010_GPIO_OE,
2056 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2057 (AR7010_GPIO_OE_MASK << gpio_shift));
2058 return;
2059 }
f078f209 2060
88c1f4f6 2061 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2062 gpio_shift = 2 * gpio;
f1dc5600
S		 2063 REG_RMW(ah,
2064 AR_GPIO_OE_OUT,
2065 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2066 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2067}
7322fd19 2068EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2069
cbe61d8a 2070void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2071{
88c1f4f6
S		 2072 if (AR_DEVID_7010(ah)) {
2073 val = val ? 0 : 1;
2074 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2075 AR_GPIO_BIT(gpio));
2076 return;
2077 }
2078
5b5fa355
S		 2079 if (AR_SREV_9271(ah))
2080 val = ~val;
2081
f1dc5600
S		 2082 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2083 AR_GPIO_BIT(gpio));
f078f209 2084}
7322fd19 2085EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2086
cbe61d8a 2087u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2088{
f1dc5600 2089 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2090}
7322fd19 2091EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2092
cbe61d8a 2093void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2094{
f1dc5600 2095 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2096}
7322fd19 2097EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2098
f1dc5600
S		 2099/*********************/
2100/* General Operation */
2101/*********************/
2102
cbe61d8a 2103u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2104{
f1dc5600
S		 2105 u32 bits = REG_READ(ah, AR_RX_FILTER);
2106 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2107
f1dc5600
S		 2108 if (phybits & AR_PHY_ERR_RADAR)
2109 bits |= ATH9K_RX_FILTER_PHYRADAR;
2110 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2111 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2112
f1dc5600 2113 return bits;
f078f209 2114}
7322fd19 2115EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2116
cbe61d8a 2117void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2118{
f1dc5600 2119 u32 phybits;
f078f209 2120
7d0d0df0
S		 2121 ENABLE_REGWRITE_BUFFER(ah);
2122
7ea310be
S		 2123 REG_WRITE(ah, AR_RX_FILTER, bits);
2124
f1dc5600
S		 2125 phybits = 0;
2126 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2127 phybits |= AR_PHY_ERR_RADAR;
2128 if (bits & ATH9K_RX_FILTER_PHYERR)
2129 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2130 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2131
f1dc5600
S		 2132 if (phybits)
2133 REG_WRITE(ah, AR_RXCFG,
2134 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2135 else
2136 REG_WRITE(ah, AR_RXCFG,
2137 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2138
2139 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2140}
7322fd19 2141EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2142
cbe61d8a 2143bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2144{
63a75b91
SB		 2145 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2146 return false;
2147
2148 ath9k_hw_init_pll(ah, NULL);
2149 return true;
f1dc5600 2150}
7322fd19 2151EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2152
cbe61d8a 2153bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2154{
9ecdef4b 2155 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2156 return false;
f078f209 2157
63a75b91
SB		 2158 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2159 return false;
2160
2161 ath9k_hw_init_pll(ah, NULL);
2162 return true;
f078f209 2163}
7322fd19 2164EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2165
de40f316 2166void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2167{
608b88cb 2168 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2169 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2170 struct ieee80211_channel *channel = chan->chan;
f078f209 2171
608b88cb 2172 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2173
8fbff4b8 2174 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2175 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2176 channel->max_antenna_gain * 2,
2177 channel->max_power * 2,
2178 min((u32) MAX_RATE_POWER,
de40f316 2179 (u32) regulatory->power_limit), test);
6f255425 2180}
7322fd19 2181EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2182
cbe61d8a 2183void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2184{
2660b81a 2185 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2186}
7322fd19 2187EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2188
cbe61d8a 2189void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2190{
f1dc5600
S		 2191 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2192 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2193}
7322fd19 2194EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2195
f2b2143e 2196void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2197{
1510718d
LR		 2198 struct ath_common *common = ath9k_hw_common(ah);
2199
2200 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2201 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2202 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2203}
7322fd19 2204EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2205
1c0fc65e
BP		 2206#define ATH9K_MAX_TSF_READ 10
2207
cbe61d8a 2208u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2209{
1c0fc65e
BP		 2210 u32 tsf_lower, tsf_upper1, tsf_upper2;
2211 int i;
2212
2213 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2214 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2215 tsf_lower = REG_READ(ah, AR_TSF_L32);
2216 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2217 if (tsf_upper2 == tsf_upper1)
2218 break;
2219 tsf_upper1 = tsf_upper2;
2220 }
f078f209 2221
1c0fc65e 2222 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2223
1c0fc65e 2224 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2225}
7322fd19 2226EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2227
cbe61d8a 2228void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2229{
27abe060 2230 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2231 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2232}
7322fd19 2233EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2234
cbe61d8a 2235void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2236{
f9b604f6
GJ		 2237 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2238 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 2239 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2240 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2241
f1dc5600
S		 2242 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2243}
7322fd19 2244EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2245
54e4cec6 2246void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2247{
f1dc5600 2248 if (setting)
2660b81a 2249 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2250 else
2660b81a 2251 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2252}
7322fd19 2253EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2254
25c56eec 2255void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2256{
25c56eec 2257 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2258 u32 macmode;
2259
25c56eec 2260 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2261 macmode = AR_2040_JOINED_RX_CLEAR;
2262 else
2263 macmode = 0;
f078f209 2264
f1dc5600 2265 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2266}
ff155a45
VT		 2267
2268/* HW Generic timers configuration */
2269
2270static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2271{
2272 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2273 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2274 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2275 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2276 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2277 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2278 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2279 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2280 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2281 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2282 AR_NDP2_TIMER_MODE, 0x0002},
2283 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2284 AR_NDP2_TIMER_MODE, 0x0004},
2285 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2286 AR_NDP2_TIMER_MODE, 0x0008},
2287 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2288 AR_NDP2_TIMER_MODE, 0x0010},
2289 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2290 AR_NDP2_TIMER_MODE, 0x0020},
2291 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2292 AR_NDP2_TIMER_MODE, 0x0040},
2293 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2294 AR_NDP2_TIMER_MODE, 0x0080}
2295};
2296
2297/* HW generic timer primitives */
2298
2299/* compute and clear index of rightmost 1 */
2300static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2301{
2302 u32 b;
2303
2304 b = *mask;
2305 b &= (0-b);
2306 *mask &= ~b;
2307 b *= debruijn32;
2308 b >>= 27;
2309
2310 return timer_table->gen_timer_index[b];
2311}
2312
744bcb42 2313static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2314{
2315 return REG_READ(ah, AR_TSF_L32);
2316}
2317
2318struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2319 void (*trigger)(void *),
2320 void (*overflow)(void *),
2321 void *arg,
2322 u8 timer_index)
2323{
2324 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2325 struct ath_gen_timer *timer;
2326
2327 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2328
2329 if (timer == NULL) {
c46917bb
LR		 2330 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2331 "Failed to allocate memory"
2332 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 2333 return NULL;
2334 }
2335
2336 /* allocate a hardware generic timer slot */
2337 timer_table->timers[timer_index] = timer;
2338 timer->index = timer_index;
2339 timer->trigger = trigger;
2340 timer->overflow = overflow;
2341 timer->arg = arg;
2342
2343 return timer;
2344}
7322fd19 2345EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2346
cd9bf689
LR		 2347void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2348 struct ath_gen_timer *timer,
2349 u32 timer_next,
2350 u32 timer_period)
ff155a45
VT		 2351{
2352 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2353 u32 tsf;
2354
2355 BUG_ON(!timer_period);
2356
2357 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2358
2359 tsf = ath9k_hw_gettsf32(ah);
2360
c46917bb
LR		 2361 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2362 "curent tsf %x period %x"
2363 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 2364
2365 /*
2366 * Pull timer_next forward if the current TSF already passed it
2367 * because of software latency
2368 */
2369 if (timer_next < tsf)
2370 timer_next = tsf + timer_period;
2371
2372 /*
2373 * Program generic timer registers
2374 */
2375 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2376 timer_next);
2377 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2378 timer_period);
2379 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2380 gen_tmr_configuration[timer->index].mode_mask);
2381
2382 /* Enable both trigger and thresh interrupt masks */
2383 REG_SET_BIT(ah, AR_IMR_S5,
2384 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2385 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2386}
7322fd19 2387EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2388
cd9bf689 2389void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2390{
2391 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2392
2393 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2394 (timer->index >= ATH_MAX_GEN_TIMER)) {
2395 return;
2396 }
2397
2398 /* Clear generic timer enable bits. */
2399 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2400 gen_tmr_configuration[timer->index].mode_mask);
2401
2402 /* Disable both trigger and thresh interrupt masks */
2403 REG_CLR_BIT(ah, AR_IMR_S5,
2404 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2405 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2406
2407 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 2408}
7322fd19 2409EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2410
2411void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2412{
2413 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2414
2415 /* free the hardware generic timer slot */
2416 timer_table->timers[timer->index] = NULL;
2417 kfree(timer);
2418}
7322fd19 2419EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2420
2421/*
2422 * Generic Timer Interrupts handling
2423 */
2424void ath_gen_timer_isr(struct ath_hw *ah)
2425{
2426 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2427 struct ath_gen_timer *timer;
c46917bb 2428 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 2429 u32 trigger_mask, thresh_mask, index;
2430
2431 /* get hardware generic timer interrupt status */
2432 trigger_mask = ah->intr_gen_timer_trigger;
2433 thresh_mask = ah->intr_gen_timer_thresh;
2434 trigger_mask &= timer_table->timer_mask.val;
2435 thresh_mask &= timer_table->timer_mask.val;
2436
2437 trigger_mask &= ~thresh_mask;
2438
2439 while (thresh_mask) {
2440 index = rightmost_index(timer_table, &thresh_mask);
2441 timer = timer_table->timers[index];
2442 BUG_ON(!timer);
c46917bb
LR		 2443 ath_print(common, ATH_DBG_HWTIMER,
2444 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 2445 timer->overflow(timer->arg);
2446 }
2447
2448 while (trigger_mask) {
2449 index = rightmost_index(timer_table, &trigger_mask);
2450 timer = timer_table->timers[index];
2451 BUG_ON(!timer);
c46917bb
LR		 2452 ath_print(common, ATH_DBG_HWTIMER,
2453 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 2454 timer->trigger(timer->arg);
2455 }
2456}
7322fd19 2457EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2458
05020d23
S		 2459/********/
2460/* HTC */
2461/********/
2462
2463void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2464{
2465 ah->htc_reset_init = true;
2466}
2467EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2468
2da4f01a
LR		 2469static struct {
2470 u32 version;
2471 const char * name;
2472} ath_mac_bb_names[] = {
2473 /* Devices with external radios */
2474 { AR_SREV_VERSION_5416_PCI, "5416" },
2475 { AR_SREV_VERSION_5416_PCIE, "5418" },
2476 { AR_SREV_VERSION_9100, "9100" },
2477 { AR_SREV_VERSION_9160, "9160" },
2478 /* Single-chip solutions */
2479 { AR_SREV_VERSION_9280, "9280" },
2480 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 2481 { AR_SREV_VERSION_9287, "9287" },
2482 { AR_SREV_VERSION_9271, "9271" },
ec83903e 2483 { AR_SREV_VERSION_9300, "9300" },
2da4f01a
LR		 2484};
2485
2486/* For devices with external radios */
2487static struct {
2488 u16 version;
2489 const char * name;
2490} ath_rf_names[] = {
2491 { 0, "5133" },
2492 { AR_RAD5133_SREV_MAJOR, "5133" },
2493 { AR_RAD5122_SREV_MAJOR, "5122" },
2494 { AR_RAD2133_SREV_MAJOR, "2133" },
2495 { AR_RAD2122_SREV_MAJOR, "2122" }
2496};
2497
2498/*
2499 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2500 */
f934c4d9 2501static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 2502{
2503 int i;
2504
2505 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2506 if (ath_mac_bb_names[i].version == mac_bb_version) {
2507 return ath_mac_bb_names[i].name;
2508 }
2509 }
2510
2511 return "????";
2512}
2da4f01a
LR		 2513
2514/*
2515 * Return the RF name. "????" is returned if the RF is unknown.
2516 * Used for devices with external radios.
2517 */
f934c4d9 2518static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 2519{
2520 int i;
2521
2522 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2523 if (ath_rf_names[i].version == rf_version) {
2524 return ath_rf_names[i].name;
2525 }
2526 }
2527
2528 return "????";
2529}
f934c4d9
LR		 2530
2531void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2532{
2533 int used;
2534
2535 /* chipsets >= AR9280 are single-chip */
7a37081e 2536 if (AR_SREV_9280_20_OR_LATER(ah)) {
f934c4d9
LR		 2537 used = snprintf(hw_name, len,
2538 "Atheros AR%s Rev:%x",
2539 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2540 ah->hw_version.macRev);
2541 }
2542 else {
2543 used = snprintf(hw_name, len,
2544 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2545 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2546 ah->hw_version.macRev,
2547 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2548 AR_RADIO_SREV_MAJOR)),
2549 ah->hw_version.phyRev);
2550 }
2551
2552 hw_name[used] = '\0';
2553}
2554EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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