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[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
f078f209
LR		 19#include <asm/unaligned.h>
20
af03abec 21#include "hw.h"
d70357d5 22#include "hw-ops.h"
cfe8cba9 23#include "rc.h"
b622a720 24#include "ar9003_mac.h"
f078f209 25
cbe61d8a 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 27
7322fd19
LR		 28MODULE_AUTHOR("Atheros Communications");
29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31MODULE_LICENSE("Dual BSD/GPL");
32
33static int __init ath9k_init(void)
34{
35 return 0;
36}
37module_init(ath9k_init);
38
39static void __exit ath9k_exit(void)
40{
41 return;
42}
43module_exit(ath9k_exit);
44
d70357d5
LR		 45/* Private hardware callbacks */
46
47static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48{
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50}
51
52static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55}
56
57static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
58{
59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
60
61 return priv_ops->macversion_supported(ah->hw_version.macVersion);
62}
63
64773964
LR		 64static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
65 struct ath9k_channel *chan)
66{
67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
68}
69
991312d8
LR		 70static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
71{
72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
73 return;
74
75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
76}
77
e36b27af
LR		 78static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
79{
80 /* You will not have this callback if using the old ANI */
81 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
82 return;
83
84 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
85}
86
f1dc5600
S		 87/********************/
88/* Helper Functions */
89/********************/
f078f209 90
cbe61d8a 91static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 92{
b002a4a9 93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 94
2660b81a 95 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 96 return usecs *ATH9K_CLOCK_RATE_CCK;
97 if (conf->channel->band == IEEE80211_BAND_2GHZ)
98 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
e5553724
VT		 99
100 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
101 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
102 else
103 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 104}
105
cbe61d8a 106static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 107{
b002a4a9 108 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 109
4febf7b8 110 if (conf_is_ht40(conf))
f1dc5600
S		 111 return ath9k_hw_mac_clks(ah, usecs) * 2;
112 else
113 return ath9k_hw_mac_clks(ah, usecs);
114}
f078f209 115
0caa7b14 116bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 117{
118 int i;
119
0caa7b14
S		 120 BUG_ON(timeout < AH_TIME_QUANTUM);
121
122 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 123 if ((REG_READ(ah, reg) & mask) == val)
124 return true;
125
126 udelay(AH_TIME_QUANTUM);
127 }
04bd4638 128
c46917bb
LR		 129 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
131 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 132
f1dc5600 133 return false;
f078f209 134}
7322fd19 135EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 136
137u32 ath9k_hw_reverse_bits(u32 val, u32 n)
138{
139 u32 retval;
140 int i;
141
142 for (i = 0, retval = 0; i < n; i++) {
143 retval = (retval << 1) | (val & 1);
144 val >>= 1;
145 }
146 return retval;
147}
148
cbe61d8a 149bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 150 u16 flags, u16 *low,
151 u16 *high)
f078f209 152{
2660b81a 153 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 154
f1dc5600
S		 155 if (flags & CHANNEL_5GHZ) {
156 *low = pCap->low_5ghz_chan;
157 *high = pCap->high_5ghz_chan;
158 return true;
f078f209 159 }
f1dc5600
S		 160 if ((flags & CHANNEL_2GHZ)) {
161 *low = pCap->low_2ghz_chan;
162 *high = pCap->high_2ghz_chan;
163 return true;
164 }
165 return false;
f078f209
LR		 166}
167
cbe61d8a 168u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 169 u8 phy, int kbps,
f1dc5600
S		 170 u32 frameLen, u16 rateix,
171 bool shortPreamble)
f078f209 172{
f1dc5600 173 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 174
f1dc5600
S		 175 if (kbps == 0)
176 return 0;
f078f209 177
545750d3 178 switch (phy) {
46d14a58 179 case WLAN_RC_PHY_CCK:
f1dc5600 180 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 181 if (shortPreamble)
f1dc5600
S		 182 phyTime >>= 1;
183 numBits = frameLen << 3;
184 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
185 break;
46d14a58 186 case WLAN_RC_PHY_OFDM:
2660b81a 187 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 188 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
189 numBits = OFDM_PLCP_BITS + (frameLen << 3);
190 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
191 txTime = OFDM_SIFS_TIME_QUARTER
192 + OFDM_PREAMBLE_TIME_QUARTER
193 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 194 } else if (ah->curchan &&
195 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 196 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
197 numBits = OFDM_PLCP_BITS + (frameLen << 3);
198 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
199 txTime = OFDM_SIFS_TIME_HALF +
200 OFDM_PREAMBLE_TIME_HALF
201 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
202 } else {
203 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
204 numBits = OFDM_PLCP_BITS + (frameLen << 3);
205 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
206 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
207 + (numSymbols * OFDM_SYMBOL_TIME);
208 }
209 break;
210 default:
c46917bb 211 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 212 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 213 txTime = 0;
214 break;
215 }
f078f209 216
f1dc5600
S		 217 return txTime;
218}
7322fd19 219EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 220
cbe61d8a 221void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 222 struct ath9k_channel *chan,
223 struct chan_centers *centers)
f078f209 224{
f1dc5600 225 int8_t extoff;
f078f209 226
f1dc5600
S		 227 if (!IS_CHAN_HT40(chan)) {
228 centers->ctl_center = centers->ext_center =
229 centers->synth_center = chan->channel;
230 return;
f078f209 231 }
f078f209 232
f1dc5600
S		 233 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
234 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
235 centers->synth_center =
236 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
237 extoff = 1;
238 } else {
239 centers->synth_center =
240 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
241 extoff = -1;
242 }
f078f209 243
f1dc5600
S		 244 centers->ctl_center =
245 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 246 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 247 centers->ext_center =
6420014c 248 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 249}
250
f1dc5600
S		 251/******************/
252/* Chip Revisions */
253/******************/
254
cbe61d8a 255static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 256{
f1dc5600 257 u32 val;
f078f209 258
f1dc5600 259 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 260
f1dc5600
S		 261 if (val == 0xFF) {
262 val = REG_READ(ah, AR_SREV);
d535a42a
S		 263 ah->hw_version.macVersion =
264 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
265 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 266 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 267 } else {
268 if (!AR_SREV_9100(ah))
d535a42a 269 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 270
d535a42a 271 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 272
d535a42a 273 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 274 ah->is_pciexpress = true;
f1dc5600 275 }
f078f209
LR		 276}
277
f1dc5600
S		 278/************************************/
279/* HW Attach, Detach, Init Routines */
280/************************************/
281
cbe61d8a 282static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 283{
feed029c 284 if (AR_SREV_9100(ah))
f1dc5600 285 return;
f078f209 286
7d0d0df0
S		 287 ENABLE_REGWRITE_BUFFER(ah);
288
f1dc5600
S		 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 298
f1dc5600 299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
7d0d0df0
S		 300
301 REGWRITE_BUFFER_FLUSH(ah);
302 DISABLE_REGWRITE_BUFFER(ah);
f078f209
LR		 303}
304
1f3f0618 305/* This should work for all families including legacy */
cbe61d8a 306static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 307{
c46917bb 308 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 309 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600
S		 310 u32 regHold[2];
311 u32 patternData[4] = { 0x55555555,
312 0xaaaaaaaa,
313 0x66666666,
314 0x99999999 };
1f3f0618 315 int i, j, loop_max;
f078f209 316
1f3f0618
SB		 317 if (!AR_SREV_9300_20_OR_LATER(ah)) {
318 loop_max = 2;
319 regAddr[1] = AR_PHY_BASE + (8 << 2);
320 } else
321 loop_max = 1;
322
323 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 324 u32 addr = regAddr[i];
325 u32 wrData, rdData;
f078f209 326
f1dc5600
S		 327 regHold[i] = REG_READ(ah, addr);
328 for (j = 0; j < 0x100; j++) {
329 wrData = (j << 16) | j;
330 REG_WRITE(ah, addr, wrData);
331 rdData = REG_READ(ah, addr);
332 if (rdData != wrData) {
c46917bb
LR		 333 ath_print(common, ATH_DBG_FATAL,
334 "address test failed "
335 "addr: 0x%08x - wr:0x%08x != "
336 "rd:0x%08x\n",
337 addr, wrData, rdData);
f1dc5600
S		 338 return false;
339 }
340 }
341 for (j = 0; j < 4; j++) {
342 wrData = patternData[j];
343 REG_WRITE(ah, addr, wrData);
344 rdData = REG_READ(ah, addr);
345 if (wrData != rdData) {
c46917bb
LR		 346 ath_print(common, ATH_DBG_FATAL,
347 "address test failed "
348 "addr: 0x%08x - wr:0x%08x != "
349 "rd:0x%08x\n",
350 addr, wrData, rdData);
f1dc5600
S		 351 return false;
352 }
f078f209 353 }
f1dc5600 354 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 355 }
f1dc5600 356 udelay(100);
cbe61d8a 357
f078f209
LR		 358 return true;
359}
360
b8b0f377 361static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 362{
363 int i;
f078f209 364
2660b81a
S		 365 ah->config.dma_beacon_response_time = 2;
366 ah->config.sw_beacon_response_time = 10;
367 ah->config.additional_swba_backoff = 0;
368 ah->config.ack_6mb = 0x0;
369 ah->config.cwm_ignore_extcca = 0;
370 ah->config.pcie_powersave_enable = 0;
2660b81a 371 ah->config.pcie_clock_req = 0;
2660b81a
S		 372 ah->config.pcie_waen = 0;
373 ah->config.analog_shiftreg = 1;
2660b81a
S		 374 ah->config.ofdm_trig_low = 200;
375 ah->config.ofdm_trig_high = 500;
376 ah->config.cck_trig_high = 200;
377 ah->config.cck_trig_low = 100;
03c72518 378 ah->config.enable_ani = true;
f078f209 379
f1dc5600 380 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 381 ah->config.spurchans[i][0] = AR_NO_SPUR;
382 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 383 }
384
5ffaf8a3
LR		 385 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
386 ah->config.ht_enable = 1;
387 else
388 ah->config.ht_enable = 0;
389
0ce024cb 390 ah->config.rx_intr_mitigation = true;
6a0ec30a 391 ah->config.pcieSerDesWrite = true;
6158425b
LR		 392
393 /*
394 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
395 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
396 * This means we use it for all AR5416 devices, and the few
397 * minor PCI AR9280 devices out there.
398 *
399 * Serialization is required because these devices do not handle
400 * well the case of two concurrent reads/writes due to the latency
401 * involved. During one read/write another read/write can be issued
402 * on another CPU while the previous read/write may still be working
403 * on our hardware, if we hit this case the hardware poops in a loop.
404 * We prevent this by serializing reads and writes.
405 *
406 * This issue is not present on PCI-Express devices or pre-AR5416
407 * devices (legacy, 802.11abg).
408 */
409 if (num_possible_cpus() > 1)
2d6a5e95 410 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 411}
412
50aca25b 413static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 414{
608b88cb
LR		 415 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
416
417 regulatory->country_code = CTRY_DEFAULT;
418 regulatory->power_limit = MAX_RATE_POWER;
419 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
420
d535a42a 421 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 422 ah->hw_version.subvendorid = 0;
f078f209
LR		 423
424 ah->ah_flags = 0;
f078f209
LR		 425 if (!AR_SREV_9100(ah))
426 ah->ah_flags = AH_USE_EEPROM;
427
2660b81a 428 ah->atim_window = 0;
16f2411f
FF		 429 ah->sta_id1_defaults =
430 AR_STA_ID1_CRPT_MIC_ENABLE |
431 AR_STA_ID1_MCAST_KSRCH;
2660b81a
S		 432 ah->beacon_interval = 100;
433 ah->enable_32kHz_clock = DONT_USE_32KHZ;
434 ah->slottime = (u32) -1;
2660b81a 435 ah->globaltxtimeout = (u32) -1;
cbdec975 436 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 437}
438
cbe61d8a 439static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 440{
1510718d 441 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 442 u32 sum;
443 int i;
444 u16 eeval;
49101676 445 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 446
447 sum = 0;
448 for (i = 0; i < 3; i++) {
49101676 449 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 450 sum += eeval;
1510718d
LR		 451 common->macaddr[2 * i] = eeval >> 8;
452 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 453 }
d8baa939 454 if (sum == 0 || sum == 0xffff * 3)
f078f209 455 return -EADDRNOTAVAIL;
f078f209
LR		 456
457 return 0;
458}
459
f637cfd6 460static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 461{
f1dc5600 462 int ecode;
f078f209 463
527d485f
S		 464 if (!AR_SREV_9271(ah)) {
465 if (!ath9k_hw_chip_test(ah))
466 return -ENODEV;
467 }
f078f209 468
ebd5a14a
LR		 469 if (!AR_SREV_9300_20_OR_LATER(ah)) {
470 ecode = ar9002_hw_rf_claim(ah);
471 if (ecode != 0)
472 return ecode;
473 }
f078f209 474
f637cfd6 475 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 476 if (ecode != 0)
477 return ecode;
7d01b221 478
c46917bb
LR		 479 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
480 "Eeprom VER: %d, REV: %d\n",
481 ah->eep_ops->get_eeprom_ver(ah),
482 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 483
8fe65368
LR		 484 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
485 if (ecode) {
486 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
487 "Failed allocating banks for "
488 "external radio\n");
489 return ecode;
574d6b12 490 }
f078f209 491
f1dc5600
S		 492 if (!AR_SREV_9100(ah)) {
493 ath9k_hw_ani_setup(ah);
f637cfd6 494 ath9k_hw_ani_init(ah);
f078f209
LR		 495 }
496
f078f209
LR		 497 return 0;
498}
499
8525f280 500static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 501{
8525f280
LR		 502 if (AR_SREV_9300_20_OR_LATER(ah))
503 ar9003_hw_attach_ops(ah);
504 else
505 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 506}
507
d70357d5
LR		 508/* Called for all hardware families */
509static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 510{
c46917bb 511 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 512 int r = 0;
aa4058ae 513
bab1f62e
LR		 514 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
515 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
aa4058ae
LR		 516
517 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 518 ath_print(common, ATH_DBG_FATAL,
519 "Couldn't reset chip\n");
95fafca2 520 return -EIO;
aa4058ae
LR		 521 }
522
bab1f62e
LR		 523 ath9k_hw_init_defaults(ah);
524 ath9k_hw_init_config(ah);
525
8525f280 526 ath9k_hw_attach_ops(ah);
d70357d5 527
9ecdef4b 528 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 529 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 530 return -EIO;
aa4058ae
LR		 531 }
532
533 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
534 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
4c85ab11
JL		 535 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
536 !ah->is_pciexpress)) {
aa4058ae
LR		 537 ah->config.serialize_regmode =
538 SER_REG_MODE_ON;
539 } else {
540 ah->config.serialize_regmode =
541 SER_REG_MODE_OFF;
542 }
543 }
544
c46917bb 545 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 546 ah->config.serialize_regmode);
547
f4709fdf
LR		 548 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
549 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
550 else
551 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
552
d70357d5 553 if (!ath9k_hw_macversion_supported(ah)) {
c46917bb
LR		 554 ath_print(common, ATH_DBG_FATAL,
555 "Mac Chip Rev 0x%02x.%x is not supported by "
556 "this driver\n", ah->hw_version.macVersion,
557 ah->hw_version.macRev);
95fafca2 558 return -EOPNOTSUPP;
aa4058ae
LR		 559 }
560
0df13da4 561 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
d7e7d229
LR		 562 ah->is_pciexpress = false;
563
aa4058ae 564 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 565 ath9k_hw_init_cal_settings(ah);
566
567 ah->ani_function = ATH9K_ANI_ALL;
31a0bd3c 568 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 569 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 570 if (!AR_SREV_9300_20_OR_LATER(ah))
571 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae
LR		 572
573 ath9k_hw_init_mode_regs(ah);
574
9a658d2b
LR		 575 /*
576 * Read back AR_WA into a permanent copy and set bits 14 and 17.
577 * We need to do this to avoid RMW of this register. We cannot
578 * read the reg when chip is asleep.
579 */
580 ah->WARegVal = REG_READ(ah, AR_WA);
581 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
582 AR_WA_ASPM_TIMER_BASED_DISABLE);
583
aa4058ae 584 if (ah->is_pciexpress)
93b1b37f 585 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 586 else
587 ath9k_hw_disablepcie(ah);
588
d8f492b7
LR		 589 if (!AR_SREV_9300_20_OR_LATER(ah))
590 ar9002_hw_cck_chan14_spread(ah);
193cd458 591
f637cfd6 592 r = ath9k_hw_post_init(ah);
aa4058ae 593 if (r)
95fafca2 594 return r;
aa4058ae
LR		 595
596 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 597 r = ath9k_hw_fill_cap_info(ah);
598 if (r)
599 return r;
600
4f3acf81
LR		 601 r = ath9k_hw_init_macaddr(ah);
602 if (r) {
c46917bb
LR		 603 ath_print(common, ATH_DBG_FATAL,
604 "Failed to initialize MAC address\n");
95fafca2 605 return r;
f078f209
LR		 606 }
607
d7e7d229 608 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 609 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 610 else
2660b81a 611 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 612
aea702b7 613 ah->bb_watchdog_timeout_ms = 25;
f078f209 614
211f5859
LR		 615 common->state = ATH_HW_INITIALIZED;
616
4f3acf81 617 return 0;
f078f209
LR		 618}
619
d70357d5 620int ath9k_hw_init(struct ath_hw *ah)
f078f209 621{
d70357d5
LR		 622 int ret;
623 struct ath_common *common = ath9k_hw_common(ah);
f078f209 624
d70357d5
LR		 625 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
626 switch (ah->hw_version.devid) {
627 case AR5416_DEVID_PCI:
628 case AR5416_DEVID_PCIE:
629 case AR5416_AR9100_DEVID:
630 case AR9160_DEVID_PCI:
631 case AR9280_DEVID_PCI:
632 case AR9280_DEVID_PCIE:
633 case AR9285_DEVID_PCIE:
db3cc53a
SB		 634 case AR9287_DEVID_PCI:
635 case AR9287_DEVID_PCIE:
d70357d5 636 case AR2427_DEVID_PCIE:
db3cc53a 637 case AR9300_DEVID_PCIE:
d70357d5
LR		 638 break;
639 default:
640 if (common->bus_ops->ath_bus_type == ATH_USB)
641 break;
642 ath_print(common, ATH_DBG_FATAL,
643 "Hardware device ID 0x%04x not supported\n",
644 ah->hw_version.devid);
645 return -EOPNOTSUPP;
646 }
f078f209 647
d70357d5
LR		 648 ret = __ath9k_hw_init(ah);
649 if (ret) {
650 ath_print(common, ATH_DBG_FATAL,
651 "Unable to initialize hardware; "
652 "initialization status: %d\n", ret);
653 return ret;
654 }
f078f209 655
d70357d5 656 return 0;
f078f209 657}
d70357d5 658EXPORT_SYMBOL(ath9k_hw_init);
f078f209 659
cbe61d8a 660static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 661{
7d0d0df0
S		 662 ENABLE_REGWRITE_BUFFER(ah);
663
f1dc5600
S		 664 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
665 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 666
f1dc5600
S		 667 REG_WRITE(ah, AR_QOS_NO_ACK,
668 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
669 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
670 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
671
672 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
673 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
674 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
675 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
676 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 677
678 REGWRITE_BUFFER_FLUSH(ah);
679 DISABLE_REGWRITE_BUFFER(ah);
f078f209
LR		 680}
681
cbe61d8a 682static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 683 struct ath9k_channel *chan)
f078f209 684{
64773964 685 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 686
d03a66c1 687 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 688
c75724d1
LR		 689 /* Switch the core clock for ar9271 to 117Mhz */
690 if (AR_SREV_9271(ah)) {
25e2ab17
S		 691 udelay(500);
692 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 693 }
694
f1dc5600
S		 695 udelay(RTC_PLL_SETTLE_DELAY);
696
697 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 698}
699
cbe61d8a 700static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 701 enum nl80211_iftype opmode)
f078f209 702{
152d530d 703 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 704 AR_IMR_TXURN |
705 AR_IMR_RXERR |
706 AR_IMR_RXORN |
707 AR_IMR_BCNMISC;
f078f209 708
66860240
VT		 709 if (AR_SREV_9300_20_OR_LATER(ah)) {
710 imr_reg |= AR_IMR_RXOK_HP;
711 if (ah->config.rx_intr_mitigation)
712 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
713 else
714 imr_reg |= AR_IMR_RXOK_LP;
f078f209 715
66860240
VT		 716 } else {
717 if (ah->config.rx_intr_mitigation)
718 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
719 else
720 imr_reg |= AR_IMR_RXOK;
721 }
f078f209 722
66860240
VT		 723 if (ah->config.tx_intr_mitigation)
724 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
725 else
726 imr_reg |= AR_IMR_TXOK;
f078f209 727
d97809db 728 if (opmode == NL80211_IFTYPE_AP)
152d530d 729 imr_reg |= AR_IMR_MIB;
f078f209 730
7d0d0df0
S		 731 ENABLE_REGWRITE_BUFFER(ah);
732
152d530d 733 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 734 ah->imrs2_reg |= AR_IMR_S2_GTT;
735 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 736
f1dc5600
S		 737 if (!AR_SREV_9100(ah)) {
738 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
739 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
740 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
741 }
66860240 742
7d0d0df0
S		 743 REGWRITE_BUFFER_FLUSH(ah);
744 DISABLE_REGWRITE_BUFFER(ah);
745
66860240
VT		 746 if (AR_SREV_9300_20_OR_LATER(ah)) {
747 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
748 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
749 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
750 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
751 }
f078f209
LR		 752}
753
0005baf4 754static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 755{
0005baf4
FF		 756 u32 val = ath9k_hw_mac_to_clks(ah, us);
757 val = min(val, (u32) 0xFFFF);
758 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 759}
760
0005baf4 761static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 762{
0005baf4
FF		 763 u32 val = ath9k_hw_mac_to_clks(ah, us);
764 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
765 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
766}
767
768static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
769{
770 u32 val = ath9k_hw_mac_to_clks(ah, us);
771 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
772 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 773}
f1dc5600 774
cbe61d8a 775static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 776{
f078f209 777 if (tu > 0xFFFF) {
c46917bb
LR		 778 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
779 "bad global tx timeout %u\n", tu);
2660b81a 780 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 781 return false;
782 } else {
783 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 784 ah->globaltxtimeout = tu;
f078f209
LR		 785 return true;
786 }
787}
788
0005baf4 789void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 790{
0005baf4
FF		 791 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
792 int acktimeout;
e239d859 793 int slottime;
0005baf4
FF		 794 int sifstime;
795
c46917bb
LR		 796 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
797 ah->misc_mode);
f078f209 798
2660b81a 799 if (ah->misc_mode != 0)
f1dc5600 800 REG_WRITE(ah, AR_PCU_MISC,
2660b81a 801 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
0005baf4
FF		 802
803 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
804 sifstime = 16;
805 else
806 sifstime = 10;
807
e239d859
FF		 808 /* As defined by IEEE 802.11-2007 17.3.8.6 */
809 slottime = ah->slottime + 3 * ah->coverage_class;
810 acktimeout = slottime + sifstime;
42c4568a
FF		 811
812 /*
813 * Workaround for early ACK timeouts, add an offset to match the
814 * initval's 64us ack timeout value.
815 * This was initially only meant to work around an issue with delayed
816 * BA frames in some implementations, but it has been found to fix ACK
817 * timeout issues in other cases as well.
818 */
819 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
820 acktimeout += 64 - sifstime - ah->slottime;
821
e239d859 822 ath9k_hw_setslottime(ah, slottime);
0005baf4
FF		 823 ath9k_hw_set_ack_timeout(ah, acktimeout);
824 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 825 if (ah->globaltxtimeout != (u32) -1)
826 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 827}
0005baf4 828EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 829
285f2dda 830void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 831{
211f5859
LR		 832 struct ath_common *common = ath9k_hw_common(ah);
833
736b3a27 834 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 835 goto free_hw;
836
9ecdef4b 837 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 838
839free_hw:
8fe65368 840 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 841}
285f2dda 842EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 843
f1dc5600
S		 844/*******/
845/* INI */
846/*******/
847
8fe65368 848u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 849{
850 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
851
852 if (IS_CHAN_B(chan))
853 ctl |= CTL_11B;
854 else if (IS_CHAN_G(chan))
855 ctl |= CTL_11G;
856 else
857 ctl |= CTL_11A;
858
859 return ctl;
860}
861
f1dc5600
S		 862/****************************************/
863/* Reset and Channel Switching Routines */
864/****************************************/
f1dc5600 865
cbe61d8a 866static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 867{
57b32227 868 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 869 u32 regval;
870
7d0d0df0
S		 871 ENABLE_REGWRITE_BUFFER(ah);
872
d7e7d229
LR		 873 /*
874 * set AHB_MODE not to do cacheline prefetches
875 */
57b32227
FF		 876 if (!AR_SREV_9300_20_OR_LATER(ah)) {
877 regval = REG_READ(ah, AR_AHB_MODE);
878 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
879 }
f1dc5600 880
d7e7d229
LR		 881 /*
882 * let mac dma reads be in 128 byte chunks
883 */
f1dc5600
S		 884 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
885 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
886
7d0d0df0
S		 887 REGWRITE_BUFFER_FLUSH(ah);
888 DISABLE_REGWRITE_BUFFER(ah);
889
d7e7d229
LR		 890 /*
891 * Restore TX Trigger Level to its pre-reset value.
892 * The initial value depends on whether aggregation is enabled, and is
893 * adjusted whenever underruns are detected.
894 */
57b32227
FF		 895 if (!AR_SREV_9300_20_OR_LATER(ah))
896 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 897
7d0d0df0 898 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 899
d7e7d229
LR		 900 /*
901 * let mac dma writes be in 128 byte chunks
902 */
f1dc5600
S		 903 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
904 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
905
d7e7d229
LR		 906 /*
907 * Setup receive FIFO threshold to hold off TX activities
908 */
f1dc5600
S		 909 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
910
57b32227
FF		 911 if (AR_SREV_9300_20_OR_LATER(ah)) {
912 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
913 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
914
915 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
916 ah->caps.rx_status_len);
917 }
918
d7e7d229
LR		 919 /*
920 * reduce the number of usable entries in PCU TXBUF to avoid
921 * wrap around issues.
922 */
f1dc5600 923 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 924 /* For AR9285 the number of Fifos are reduced to half.
925 * So set the usable tx buf size also to half to
926 * avoid data/delimiter underruns
927 */
f1dc5600
S		 928 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
929 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 930 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 931 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
932 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
933 }
744d4025 934
7d0d0df0
S		 935 REGWRITE_BUFFER_FLUSH(ah);
936 DISABLE_REGWRITE_BUFFER(ah);
937
744d4025
VT		 938 if (AR_SREV_9300_20_OR_LATER(ah))
939 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 940}
941
cbe61d8a 942static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 943{
944 u32 val;
945
946 val = REG_READ(ah, AR_STA_ID1);
947 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
948 switch (opmode) {
d97809db 949 case NL80211_IFTYPE_AP:
f1dc5600
S		 950 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
951 | AR_STA_ID1_KSRCH_MODE);
952 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 953 break;
d97809db 954 case NL80211_IFTYPE_ADHOC:
9cb5412b 955 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 956 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
957 | AR_STA_ID1_KSRCH_MODE);
958 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 959 break;
d97809db
CM		 960 case NL80211_IFTYPE_STATION:
961 case NL80211_IFTYPE_MONITOR:
f1dc5600 962 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 963 break;
f1dc5600
S		 964 }
965}
966
8fe65368
LR		 967void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
968 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 969{
970 u32 coef_exp, coef_man;
971
972 for (coef_exp = 31; coef_exp > 0; coef_exp--)
973 if ((coef_scaled >> coef_exp) & 0x1)
974 break;
975
976 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
977
978 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
979
980 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
981 *coef_exponent = coef_exp - 16;
982}
983
cbe61d8a 984static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 985{
986 u32 rst_flags;
987 u32 tmpReg;
988
70768496
S		 989 if (AR_SREV_9100(ah)) {
990 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
991 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
992 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
993 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
994 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
995 }
996
7d0d0df0
S		 997 ENABLE_REGWRITE_BUFFER(ah);
998
9a658d2b
LR		 999 if (AR_SREV_9300_20_OR_LATER(ah)) {
1000 REG_WRITE(ah, AR_WA, ah->WARegVal);
1001 udelay(10);
1002 }
1003
f1dc5600
S		 1004 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1005 AR_RTC_FORCE_WAKE_ON_INT);
1006
1007 if (AR_SREV_9100(ah)) {
1008 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1009 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1010 } else {
1011 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1012 if (tmpReg &
1013 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1014 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1015 u32 val;
f1dc5600 1016 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1017
1018 val = AR_RC_HOSTIF;
1019 if (!AR_SREV_9300_20_OR_LATER(ah))
1020 val |= AR_RC_AHB;
1021 REG_WRITE(ah, AR_RC, val);
1022
1023 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1024 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1025
1026 rst_flags = AR_RTC_RC_MAC_WARM;
1027 if (type == ATH9K_RESET_COLD)
1028 rst_flags |= AR_RTC_RC_MAC_COLD;
1029 }
1030
d03a66c1 1031 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1032
1033 REGWRITE_BUFFER_FLUSH(ah);
1034 DISABLE_REGWRITE_BUFFER(ah);
1035
f1dc5600
S		 1036 udelay(50);
1037
d03a66c1 1038 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1039 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1040 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1041 "RTC stuck in MAC reset\n");
f1dc5600
S		 1042 return false;
1043 }
1044
1045 if (!AR_SREV_9100(ah))
1046 REG_WRITE(ah, AR_RC, 0);
1047
f1dc5600
S		 1048 if (AR_SREV_9100(ah))
1049 udelay(50);
1050
1051 return true;
1052}
1053
cbe61d8a 1054static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1055{
7d0d0df0
S		 1056 ENABLE_REGWRITE_BUFFER(ah);
1057
9a658d2b
LR		 1058 if (AR_SREV_9300_20_OR_LATER(ah)) {
1059 REG_WRITE(ah, AR_WA, ah->WARegVal);
1060 udelay(10);
1061 }
1062
f1dc5600
S		 1063 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1064 AR_RTC_FORCE_WAKE_ON_INT);
1065
42d5bc3f 1066 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1067 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1068
d03a66c1 1069 REG_WRITE(ah, AR_RTC_RESET, 0);
ee031112 1070 udelay(2);
1c29ce67 1071
7d0d0df0
S		 1072 REGWRITE_BUFFER_FLUSH(ah);
1073 DISABLE_REGWRITE_BUFFER(ah);
1074
84e2169b
SB		 1075 if (!AR_SREV_9300_20_OR_LATER(ah))
1076 udelay(2);
1077
1078 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1079 REG_WRITE(ah, AR_RC, 0);
1080
d03a66c1 1081 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1082
1083 if (!ath9k_hw_wait(ah,
1084 AR_RTC_STATUS,
1085 AR_RTC_STATUS_M,
0caa7b14
S		 1086 AR_RTC_STATUS_ON,
1087 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1088 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1089 "RTC not waking up\n");
f1dc5600 1090 return false;
f078f209
LR		 1091 }
1092
f1dc5600
S		 1093 ath9k_hw_read_revisions(ah);
1094
1095 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1096}
1097
cbe61d8a 1098static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1099{
9a658d2b
LR		 1100 if (AR_SREV_9300_20_OR_LATER(ah)) {
1101 REG_WRITE(ah, AR_WA, ah->WARegVal);
1102 udelay(10);
1103 }
1104
f1dc5600
S		 1105 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1106 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1107
1108 switch (type) {
1109 case ATH9K_RESET_POWER_ON:
1110 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1111 case ATH9K_RESET_WARM:
1112 case ATH9K_RESET_COLD:
1113 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1114 default:
1115 return false;
1116 }
f078f209
LR		 1117}
1118
cbe61d8a 1119static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1120 struct ath9k_channel *chan)
f078f209 1121{
42abfbee 1122 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1123 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1124 return false;
1125 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1126 return false;
f078f209 1127
9ecdef4b 1128 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1129 return false;
f078f209 1130
2660b81a 1131 ah->chip_fullsleep = false;
f1dc5600 1132 ath9k_hw_init_pll(ah, chan);
f1dc5600 1133 ath9k_hw_set_rfmode(ah, chan);
f078f209 1134
f1dc5600 1135 return true;
f078f209
LR		 1136}
1137
cbe61d8a 1138static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1139 struct ath9k_channel *chan)
f078f209 1140{
608b88cb 1141 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1142 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1143 struct ieee80211_channel *channel = chan->chan;
8fe65368 1144 u32 qnum;
0a3b7bac 1145 int r;
f078f209
LR		 1146
1147 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1148 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1149 ath_print(common, ATH_DBG_QUEUE,
1150 "Transmit frames pending on "
1151 "queue %d\n", qnum);
f078f209
LR		 1152 return false;
1153 }
1154 }
1155
8fe65368 1156 if (!ath9k_hw_rfbus_req(ah)) {
c46917bb
LR		 1157 ath_print(common, ATH_DBG_FATAL,
1158 "Could not kill baseband RX\n");
f078f209
LR		 1159 return false;
1160 }
1161
8fe65368 1162 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1163
8fe65368 1164 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1165 if (r) {
1166 ath_print(common, ATH_DBG_FATAL,
1167 "Failed to set channel\n");
1168 return false;
f078f209
LR		 1169 }
1170
8fbff4b8 1171 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1172 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1173 channel->max_antenna_gain * 2,
1174 channel->max_power * 2,
1175 min((u32) MAX_RATE_POWER,
608b88cb 1176 (u32) regulatory->power_limit));
f078f209 1177
8fe65368 1178 ath9k_hw_rfbus_done(ah);
f078f209 1179
f1dc5600
S		 1180 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1181 ath9k_hw_set_delta_slope(ah, chan);
1182
8fe65368 1183 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1184
f1dc5600
S		 1185 return true;
1186}
1187
c9c99e5e 1188bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1189{
c9c99e5e
FF		 1190 int count = 50;
1191 u32 reg;
1192
1193 if (AR_SREV_9285_10_OR_LATER(ah))
1194 return true;
1195
1196 do {
1197 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1198
c9c99e5e
FF		 1199 if ((reg & 0x7E7FFFEF) == 0x00702400)
1200 continue;
1201
1202 switch (reg & 0x7E000B00) {
1203 case 0x1E000000:
1204 case 0x52000B00:
1205 case 0x18000B00:
1206 continue;
1207 default:
1208 return true;
1209 }
1210 } while (count-- > 0);
3b319aae 1211
c9c99e5e 1212 return false;
3b319aae 1213}
c9c99e5e 1214EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1215
cbe61d8a 1216int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 1217 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
f078f209 1218{
1510718d 1219 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1220 u32 saveLedState;
2660b81a 1221 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1222 u32 saveDefAntenna;
1223 u32 macStaId1;
46fe782c 1224 u64 tsf = 0;
8fe65368 1225 int i, r;
f078f209 1226
43c27613
LR		 1227 ah->txchainmask = common->tx_chainmask;
1228 ah->rxchainmask = common->rx_chainmask;
f078f209 1229
9b9cc61c
VT		 1230 if (!ah->chip_fullsleep) {
1231 ath9k_hw_abortpcurecv(ah);
9cc2f3e8 1232 if (!ath9k_hw_stopdmarecv(ah)) {
9b9cc61c
VT		 1233 ath_print(common, ATH_DBG_XMIT,
1234 "Failed to stop receive dma\n");
9cc2f3e8
FF		 1235 bChannelChange = false;
1236 }
9b9cc61c
VT		 1237 }
1238
9ecdef4b 1239 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1240 return -EIO;
f078f209 1241
20bd2a09 1242 if (curchan && !ah->chip_fullsleep && ah->caldata)
f078f209
LR		 1243 ath9k_hw_getnf(ah, curchan);
1244
20bd2a09
FF		 1245 ah->caldata = caldata;
1246 if (caldata &&
1247 (chan->channel != caldata->channel ||
1248 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1249 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1250 /* Operating channel changed, reset channel calibration data */
1251 memset(caldata, 0, sizeof(*caldata));
1252 ath9k_init_nfcal_hist_buffer(ah, chan);
1253 }
1254
f078f209 1255 if (bChannelChange &&
2660b81a
S		 1256 (ah->chip_fullsleep != true) &&
1257 (ah->curchan != NULL) &&
1258 (chan->channel != ah->curchan->channel) &&
f078f209 1259 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1260 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
6b42e8d0 1261 !AR_SREV_9280(ah)) {
f078f209 1262
25c56eec 1263 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1264 ath9k_hw_loadnf(ah, ah->curchan);
00c86590 1265 ath9k_hw_start_nfcal(ah, true);
ae8d2858 1266 return 0;
f078f209
LR		 1267 }
1268 }
1269
1270 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1271 if (saveDefAntenna == 0)
1272 saveDefAntenna = 1;
1273
1274 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1275
46fe782c 1276 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1277 if (AR_SREV_9100(ah) ||
1278 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1279 tsf = ath9k_hw_gettsf64(ah);
1280
f078f209
LR		 1281 saveLedState = REG_READ(ah, AR_CFG_LED) &
1282 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1283 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1284
1285 ath9k_hw_mark_phy_inactive(ah);
1286
05020d23 1287 /* Only required on the first reset */
d7e7d229
LR		 1288 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1289 REG_WRITE(ah,
1290 AR9271_RESET_POWER_DOWN_CONTROL,
1291 AR9271_RADIO_RF_RST);
1292 udelay(50);
1293 }
1294
f078f209 1295 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1296 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1297 return -EINVAL;
f078f209
LR		 1298 }
1299
05020d23 1300 /* Only required on the first reset */
d7e7d229
LR		 1301 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1302 ah->htc_reset_init = false;
1303 REG_WRITE(ah,
1304 AR9271_RESET_POWER_DOWN_CONTROL,
1305 AR9271_GATE_MAC_CTL);
1306 udelay(50);
1307 }
1308
46fe782c 1309 /* Restore TSF */
f860d526 1310 if (tsf)
46fe782c
S		 1311 ath9k_hw_settsf64(ah, tsf);
1312
369391db
VT		 1313 if (AR_SREV_9280_10_OR_LATER(ah))
1314 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1315
e9141f71
S		 1316 if (!AR_SREV_9300_20_OR_LATER(ah))
1317 ar9002_hw_enable_async_fifo(ah);
1318
25c56eec 1319 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1320 if (r)
1321 return r;
f078f209 1322
f860d526
FF		 1323 /*
1324 * Some AR91xx SoC devices frequently fail to accept TSF writes
1325 * right after the chip reset. When that happens, write a new
1326 * value after the initvals have been applied, with an offset
1327 * based on measured time difference
1328 */
1329 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1330 tsf += 1500;
1331 ath9k_hw_settsf64(ah, tsf);
1332 }
1333
0ced0e17
JM		 1334 /* Setup MFP options for CCMP */
1335 if (AR_SREV_9280_20_OR_LATER(ah)) {
1336 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1337 * frames when constructing CCMP AAD. */
1338 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1339 0xc7ff);
1340 ah->sw_mgmt_crypto = false;
1341 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1342 /* Disable hardware crypto for management frames */
1343 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1344 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1345 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1346 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1347 ah->sw_mgmt_crypto = true;
1348 } else
1349 ah->sw_mgmt_crypto = true;
1350
f078f209
LR		 1351 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1352 ath9k_hw_set_delta_slope(ah, chan);
1353
8fe65368 1354 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1355 ah->eep_ops->set_board_values(ah, chan);
a7765828 1356
6819d57f
S		 1357 ath9k_hw_set_operating_mode(ah, ah->opmode);
1358
7d0d0df0
S		 1359 ENABLE_REGWRITE_BUFFER(ah);
1360
1510718d
LR		 1361 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1362 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1363 | macStaId1
1364 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1365 | (ah->config.
60b67f51 1366 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1367 | ah->sta_id1_defaults);
13b81559 1368 ath_hw_setbssidmask(common);
f078f209 1369 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1370 ath9k_hw_write_associd(ah);
f078f209 1371 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1372 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1373
7d0d0df0
S		 1374 REGWRITE_BUFFER_FLUSH(ah);
1375 DISABLE_REGWRITE_BUFFER(ah);
1376
8fe65368 1377 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1378 if (r)
1379 return r;
f078f209 1380
7d0d0df0
S		 1381 ENABLE_REGWRITE_BUFFER(ah);
1382
f078f209
LR		 1383 for (i = 0; i < AR_NUM_DCU; i++)
1384 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1385
7d0d0df0
S		 1386 REGWRITE_BUFFER_FLUSH(ah);
1387 DISABLE_REGWRITE_BUFFER(ah);
1388
2660b81a
S		 1389 ah->intr_txqs = 0;
1390 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 1391 ath9k_hw_resettxqueue(ah, i);
1392
2660b81a 1393 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1394 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1395 ath9k_hw_init_qos(ah);
1396
2660b81a 1397 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 1398 ath9k_enable_rfkill(ah);
3b319aae 1399
0005baf4 1400 ath9k_hw_init_global_settings(ah);
f078f209 1401
6c94fdc9 1402 if (!AR_SREV_9300_20_OR_LATER(ah)) {
e9141f71 1403 ar9002_hw_update_async_fifo(ah);
6c94fdc9 1404 ar9002_hw_enable_wep_aggregation(ah);
ac88b6ec
VN		 1405 }
1406
f078f209
LR		 1407 REG_WRITE(ah, AR_STA_ID1,
1408 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1409
1410 ath9k_hw_set_dma(ah);
1411
1412 REG_WRITE(ah, AR_OBS, 8);
1413
0ce024cb 1414 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1415 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1416 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1417 }
1418
7f62a136
VT		 1419 if (ah->config.tx_intr_mitigation) {
1420 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1421 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1422 }
1423
f078f209
LR		 1424 ath9k_hw_init_bb(ah, chan);
1425
ae8d2858 1426 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1427 return -EIO;
f078f209 1428
7d0d0df0 1429 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1430
8fe65368 1431 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1432 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1433
7d0d0df0
S		 1434 REGWRITE_BUFFER_FLUSH(ah);
1435 DISABLE_REGWRITE_BUFFER(ah);
1436
d7e7d229
LR		 1437 /*
1438 * For big endian systems turn on swapping for descriptors
1439 */
f078f209
LR		 1440 if (AR_SREV_9100(ah)) {
1441 u32 mask;
1442 mask = REG_READ(ah, AR_CFG);
1443 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 1444 ath_print(common, ATH_DBG_RESET,
04bd4638 1445 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1446 } else {
1447 mask =
1448 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1449 REG_WRITE(ah, AR_CFG, mask);
c46917bb 1450 ath_print(common, ATH_DBG_RESET,
04bd4638 1451 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1452 }
1453 } else {
cbba8cd1
S		 1454 if (common->bus_ops->ath_bus_type == ATH_USB) {
1455 /* Configure AR9271 target WLAN */
1456 if (AR_SREV_9271(ah))
1457 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1458 else
1459 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1460 }
f078f209 1461#ifdef __BIG_ENDIAN
d7e7d229
LR		 1462 else
1463 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1464#endif
1465 }
1466
766ec4a9 1467 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1468 ath9k_hw_btcoex_enable(ah);
1469
00c86590 1470 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 1471 ar9003_hw_bb_watchdog_config(ah);
d8903a53 1472
ae8d2858 1473 return 0;
f078f209 1474}
7322fd19 1475EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1476
f1dc5600
S		 1477/************************/
1478/* Key Cache Management */
1479/************************/
f078f209 1480
cbe61d8a 1481bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 1482{
f1dc5600 1483 u32 keyType;
f078f209 1484
2660b81a 1485 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1486 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1487 "keychache entry %u out of range\n", entry);
f078f209
LR		 1488 return false;
1489 }
1490
f1dc5600 1491 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 1492
f1dc5600
S		 1493 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1494 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1495 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1496 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1497 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1498 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1499 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1500 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 1501
f1dc5600
S		 1502 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1503 u16 micentry = entry + 64;
f078f209 1504
f1dc5600
S		 1505 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1506 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1507 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1508 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 1509
f078f209
LR		 1510 }
1511
f078f209
LR		 1512 return true;
1513}
7322fd19 1514EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 1515
f35376a4 1516static bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 1517{
f1dc5600 1518 u32 macHi, macLo;
1d0bb42d 1519 u32 unicast_flag = AR_KEYTABLE_VALID;
f078f209 1520
2660b81a 1521 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1522 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1523 "keychache entry %u out of range\n", entry);
f1dc5600 1524 return false;
f078f209
LR		 1525 }
1526
f1dc5600 1527 if (mac != NULL) {
1d0bb42d
FF		 1528 /*
1529 * AR_KEYTABLE_VALID indicates that the address is a unicast
1530 * address, which must match the transmitter address for
1531 * decrypting frames.
1532 * Not setting this bit allows the hardware to use the key
1533 * for multicast frame decryption.
1534 */
1535 if (mac[0] & 0x01)
1536 unicast_flag = 0;
1537
f1dc5600
S		 1538 macHi = (mac[5] << 8) | mac[4];
1539 macLo = (mac[3] << 24) |
1540 (mac[2] << 16) |
1541 (mac[1] << 8) |
1542 mac[0];
1543 macLo >>= 1;
1544 macLo |= (macHi & 1) << 31;
1545 macHi >>= 1;
f078f209 1546 } else {
f1dc5600 1547 macLo = macHi = 0;
f078f209 1548 }
f1dc5600 1549 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1d0bb42d 1550 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
f078f209 1551
f1dc5600 1552 return true;
f078f209
LR		 1553}
1554
cbe61d8a 1555bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 1556 const struct ath9k_keyval *k,
e0caf9ea 1557 const u8 *mac)
f078f209 1558{
2660b81a 1559 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1560 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 1561 u32 key0, key1, key2, key3, key4;
1562 u32 keyType;
f078f209 1563
f1dc5600 1564 if (entry >= pCap->keycache_size) {
c46917bb
LR		 1565 ath_print(common, ATH_DBG_FATAL,
1566 "keycache entry %u out of range\n", entry);
f1dc5600 1567 return false;
f078f209
LR		 1568 }
1569
f1dc5600
S		 1570 switch (k->kv_type) {
1571 case ATH9K_CIPHER_AES_OCB:
1572 keyType = AR_KEYTABLE_TYPE_AES;
1573 break;
1574 case ATH9K_CIPHER_AES_CCM:
1575 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 1576 ath_print(common, ATH_DBG_ANY,
1577 "AES-CCM not supported by mac rev 0x%x\n",
1578 ah->hw_version.macRev);
f1dc5600
S		 1579 return false;
1580 }
1581 keyType = AR_KEYTABLE_TYPE_CCM;
1582 break;
1583 case ATH9K_CIPHER_TKIP:
1584 keyType = AR_KEYTABLE_TYPE_TKIP;
1585 if (ATH9K_IS_MIC_ENABLED(ah)
1586 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 1587 ath_print(common, ATH_DBG_ANY,
1588 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 1589 return false;
1590 }
1591 break;
1592 case ATH9K_CIPHER_WEP:
e31a16d6 1593 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 1594 ath_print(common, ATH_DBG_ANY,
1595 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 1596 return false;
1597 }
e31a16d6 1598 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 1599 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 1600 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 1601 keyType = AR_KEYTABLE_TYPE_104;
1602 else
1603 keyType = AR_KEYTABLE_TYPE_128;
1604 break;
1605 case ATH9K_CIPHER_CLR:
1606 keyType = AR_KEYTABLE_TYPE_CLR;
1607 break;
1608 default:
c46917bb
LR		 1609 ath_print(common, ATH_DBG_FATAL,
1610 "cipher %u not supported\n", k->kv_type);
f1dc5600 1611 return false;
f078f209
LR		 1612 }
1613
e0caf9ea
JM		 1614 key0 = get_unaligned_le32(k->kv_val + 0);
1615 key1 = get_unaligned_le16(k->kv_val + 4);
1616 key2 = get_unaligned_le32(k->kv_val + 6);
1617 key3 = get_unaligned_le16(k->kv_val + 10);
1618 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 1619 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 1620 key4 &= 0xff;
f078f209 1621
672903b3
JM		 1622 /*
1623 * Note: Key cache registers access special memory area that requires
1624 * two 32-bit writes to actually update the values in the internal
1625 * memory. Consequently, the exact order and pairs used here must be
1626 * maintained.
1627 */
1628
f1dc5600
S		 1629 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1630 u16 micentry = entry + 64;
f078f209 1631
672903b3
JM		 1632 /*
1633 * Write inverted key[47:0] first to avoid Michael MIC errors
1634 * on frames that could be sent or received at the same time.
1635 * The correct key will be written in the end once everything
1636 * else is ready.
1637 */
f1dc5600
S		 1638 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1639 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 1640
1641 /* Write key[95:48] */
f1dc5600
S		 1642 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1643 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1644
1645 /* Write key[127:96] and key type */
f1dc5600
S		 1646 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1647 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 1648
1649 /* Write MAC address for the entry */
f1dc5600 1650 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 1651
2660b81a 1652 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 1653 /*
1654 * TKIP uses two key cache entries:
1655 * Michael MIC TX/RX keys in the same key cache entry
1656 * (idx = main index + 64):
1657 * key0 [31:0] = RX key [31:0]
1658 * key1 [15:0] = TX key [31:16]
1659 * key1 [31:16] = reserved
1660 * key2 [31:0] = RX key [63:32]
1661 * key3 [15:0] = TX key [15:0]
1662 * key3 [31:16] = reserved
1663 * key4 [31:0] = TX key [63:32]
1664 */
f1dc5600 1665 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 1666
f1dc5600
S		 1667 mic0 = get_unaligned_le32(k->kv_mic + 0);
1668 mic2 = get_unaligned_le32(k->kv_mic + 4);
1669 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1670 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1671 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 1672
1673 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 1674 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1675 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 1676
1677 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 1678 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1679 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 1680
1681 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1682 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1683 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1684 AR_KEYTABLE_TYPE_CLR);
f078f209 1685
f1dc5600 1686 } else {
672903b3
JM		 1687 /*
1688 * TKIP uses four key cache entries (two for group
1689 * keys):
1690 * Michael MIC TX/RX keys are in different key cache
1691 * entries (idx = main index + 64 for TX and
1692 * main index + 32 + 96 for RX):
1693 * key0 [31:0] = TX/RX MIC key [31:0]
1694 * key1 [31:0] = reserved
1695 * key2 [31:0] = TX/RX MIC key [63:32]
1696 * key3 [31:0] = reserved
1697 * key4 [31:0] = reserved
1698 *
1699 * Upper layer code will call this function separately
1700 * for TX and RX keys when these registers offsets are
1701 * used.
1702 */
f1dc5600 1703 u32 mic0, mic2;
f078f209 1704
f1dc5600
S		 1705 mic0 = get_unaligned_le32(k->kv_mic + 0);
1706 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 1707
1708 /* Write MIC key[31:0] */
f1dc5600
S		 1709 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1710 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 1711
1712 /* Write MIC key[63:32] */
f1dc5600
S		 1713 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1714 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 1715
1716 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1717 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1718 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1719 AR_KEYTABLE_TYPE_CLR);
1720 }
672903b3
JM		 1721
1722 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 1723 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1724 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 1725
1726 /*
1727 * Write the correct (un-inverted) key[47:0] last to enable
1728 * TKIP now that all other registers are set with correct
1729 * values.
1730 */
f1dc5600
S		 1731 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1732 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1733 } else {
672903b3 1734 /* Write key[47:0] */
f1dc5600
S		 1735 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1736 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 1737
1738 /* Write key[95:48] */
f1dc5600
S		 1739 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1740 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1741
1742 /* Write key[127:96] and key type */
f1dc5600
S		 1743 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1744 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 1745
672903b3 1746 /* Write MAC address for the entry */
f1dc5600
S		 1747 (void) ath9k_hw_keysetmac(ah, entry, mac);
1748 }
f078f209 1749
f078f209
LR		 1750 return true;
1751}
7322fd19 1752EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 1753
f1dc5600
S		 1754/******************************/
1755/* Power Management (Chipset) */
1756/******************************/
1757
42d5bc3f
LR		 1758/*
1759 * Notify Power Mgt is disabled in self-generated frames.
1760 * If requested, force chip to sleep.
1761 */
cbe61d8a 1762static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1763{
f1dc5600
S		 1764 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1765 if (setChip) {
42d5bc3f
LR		 1766 /*
1767 * Clear the RTC force wake bit to allow the
1768 * mac to go to sleep.
1769 */
f1dc5600
S		 1770 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1771 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1772 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1773 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1774
42d5bc3f 1775 /* Shutdown chip. Active low */
14b3af38 1776 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1777 REG_CLR_BIT(ah, (AR_RTC_RESET),
1778 AR_RTC_RESET_EN);
f1dc5600 1779 }
9a658d2b
LR		 1780
1781 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1782 if (AR_SREV_9300_20_OR_LATER(ah))
1783 REG_WRITE(ah, AR_WA,
1784 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1785}
1786
bbd79af5
LR		 1787/*
1788 * Notify Power Management is enabled in self-generating
1789 * frames. If request, set power mode of chip to
1790 * auto/normal. Duration in units of 128us (1/8 TU).
1791 */
cbe61d8a 1792static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1793{
f1dc5600
S		 1794 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1795 if (setChip) {
2660b81a 1796 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1797
f1dc5600 1798 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1799 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1800 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1801 AR_RTC_FORCE_WAKE_ON_INT);
1802 } else {
bbd79af5
LR		 1803 /*
1804 * Clear the RTC force wake bit to allow the
1805 * mac to go to sleep.
1806 */
f1dc5600
S		 1807 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1808 AR_RTC_FORCE_WAKE_EN);
f078f209 1809 }
f078f209 1810 }
9a658d2b
LR		 1811
1812 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1813 if (AR_SREV_9300_20_OR_LATER(ah))
1814 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1815}
1816
cbe61d8a 1817static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1818{
f1dc5600
S		 1819 u32 val;
1820 int i;
f078f209 1821
9a658d2b
LR		 1822 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1823 if (AR_SREV_9300_20_OR_LATER(ah)) {
1824 REG_WRITE(ah, AR_WA, ah->WARegVal);
1825 udelay(10);
1826 }
1827
f1dc5600
S		 1828 if (setChip) {
1829 if ((REG_READ(ah, AR_RTC_STATUS) &
1830 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1831 if (ath9k_hw_set_reset_reg(ah,
1832 ATH9K_RESET_POWER_ON) != true) {
1833 return false;
1834 }
e041228f
LR		 1835 if (!AR_SREV_9300_20_OR_LATER(ah))
1836 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1837 }
1838 if (AR_SREV_9100(ah))
1839 REG_SET_BIT(ah, AR_RTC_RESET,
1840 AR_RTC_RESET_EN);
f078f209 1841
f1dc5600
S		 1842 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1843 AR_RTC_FORCE_WAKE_EN);
1844 udelay(50);
f078f209 1845
f1dc5600
S		 1846 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1847 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1848 if (val == AR_RTC_STATUS_ON)
1849 break;
1850 udelay(50);
1851 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1852 AR_RTC_FORCE_WAKE_EN);
f078f209 1853 }
f1dc5600 1854 if (i == 0) {
c46917bb
LR		 1855 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1856 "Failed to wakeup in %uus\n",
1857 POWER_UP_TIME / 20);
f1dc5600 1858 return false;
f078f209 1859 }
f078f209
LR		 1860 }
1861
f1dc5600 1862 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1863
f1dc5600 1864 return true;
f078f209
LR		 1865}
1866
9ecdef4b 1867bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1868{
c46917bb 1869 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1870 int status = true, setChip = true;
f1dc5600
S		 1871 static const char *modes[] = {
1872 "AWAKE",
1873 "FULL-SLEEP",
1874 "NETWORK SLEEP",
1875 "UNDEFINED"
1876 };
f1dc5600 1877
cbdec975
GJ		 1878 if (ah->power_mode == mode)
1879 return status;
1880
c46917bb
LR		 1881 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1882 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1883
1884 switch (mode) {
1885 case ATH9K_PM_AWAKE:
1886 status = ath9k_hw_set_power_awake(ah, setChip);
1887 break;
1888 case ATH9K_PM_FULL_SLEEP:
1889 ath9k_set_power_sleep(ah, setChip);
2660b81a 1890 ah->chip_fullsleep = true;
f1dc5600
S		 1891 break;
1892 case ATH9K_PM_NETWORK_SLEEP:
1893 ath9k_set_power_network_sleep(ah, setChip);
1894 break;
f078f209 1895 default:
c46917bb
LR		 1896 ath_print(common, ATH_DBG_FATAL,
1897 "Unknown power mode %u\n", mode);
f078f209
LR		 1898 return false;
1899 }
2660b81a 1900 ah->power_mode = mode;
f1dc5600
S		 1901
1902 return status;
f078f209 1903}
7322fd19 1904EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1905
f1dc5600
S		 1906/*******************/
1907/* Beacon Handling */
1908/*******************/
1909
cbe61d8a 1910void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 1911{
f078f209
LR		 1912 int flags = 0;
1913
2660b81a 1914 ah->beacon_interval = beacon_period;
f078f209 1915
7d0d0df0
S		 1916 ENABLE_REGWRITE_BUFFER(ah);
1917
2660b81a 1918 switch (ah->opmode) {
d97809db
CM		 1919 case NL80211_IFTYPE_STATION:
1920 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 1921 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1922 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1923 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1924 flags |= AR_TBTT_TIMER_EN;
1925 break;
d97809db 1926 case NL80211_IFTYPE_ADHOC:
9cb5412b 1927 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 1928 REG_SET_BIT(ah, AR_TXCFG,
1929 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1930 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1931 TU_TO_USEC(next_beacon +
2660b81a
S		 1932 (ah->atim_window ? ah->
1933 atim_window : 1)));
f078f209 1934 flags |= AR_NDP_TIMER_EN;
d97809db 1935 case NL80211_IFTYPE_AP:
f078f209
LR		 1936 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1937 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1938 TU_TO_USEC(next_beacon -
2660b81a 1939 ah->config.
60b67f51 1940 dma_beacon_response_time));
f078f209
LR		 1941 REG_WRITE(ah, AR_NEXT_SWBA,
1942 TU_TO_USEC(next_beacon -
2660b81a 1943 ah->config.
60b67f51 1944 sw_beacon_response_time));
f078f209
LR		 1945 flags |=
1946 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1947 break;
d97809db 1948 default:
c46917bb
LR		 1949 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1950 "%s: unsupported opmode: %d\n",
1951 __func__, ah->opmode);
d97809db
CM		 1952 return;
1953 break;
f078f209
LR		 1954 }
1955
1956 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1957 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1958 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1959 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1960
7d0d0df0
S		 1961 REGWRITE_BUFFER_FLUSH(ah);
1962 DISABLE_REGWRITE_BUFFER(ah);
1963
f078f209
LR		 1964 beacon_period &= ~ATH9K_BEACON_ENA;
1965 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 1966 ath9k_hw_reset_tsf(ah);
1967 }
1968
1969 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1970}
7322fd19 1971EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 1972
cbe61d8a 1973void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 1974 const struct ath9k_beacon_state *bs)
f078f209
LR		 1975{
1976 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 1977 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1978 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1979
7d0d0df0
S		 1980 ENABLE_REGWRITE_BUFFER(ah);
1981
f078f209
LR		 1982 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1983
1984 REG_WRITE(ah, AR_BEACON_PERIOD,
1985 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1986 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1987 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1988
7d0d0df0
S		 1989 REGWRITE_BUFFER_FLUSH(ah);
1990 DISABLE_REGWRITE_BUFFER(ah);
1991
f078f209
LR		 1992 REG_RMW_FIELD(ah, AR_RSSI_THR,
1993 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1994
1995 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1996
1997 if (bs->bs_sleepduration > beaconintval)
1998 beaconintval = bs->bs_sleepduration;
1999
2000 dtimperiod = bs->bs_dtimperiod;
2001 if (bs->bs_sleepduration > dtimperiod)
2002 dtimperiod = bs->bs_sleepduration;
2003
2004 if (beaconintval == dtimperiod)
2005 nextTbtt = bs->bs_nextdtim;
2006 else
2007 nextTbtt = bs->bs_nexttbtt;
2008
c46917bb
LR		 2009 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2010 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2011 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2012 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2013
7d0d0df0
S		 2014 ENABLE_REGWRITE_BUFFER(ah);
2015
f1dc5600
S		 2016 REG_WRITE(ah, AR_NEXT_DTIM,
2017 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2018 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 2019
f1dc5600
S		 2020 REG_WRITE(ah, AR_SLEEP1,
2021 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2022 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2023
f1dc5600
S		 2024 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2025 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2026 else
2027 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2028
f1dc5600
S		 2029 REG_WRITE(ah, AR_SLEEP2,
2030 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2031
f1dc5600
S		 2032 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2033 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2034
7d0d0df0
S		 2035 REGWRITE_BUFFER_FLUSH(ah);
2036 DISABLE_REGWRITE_BUFFER(ah);
2037
f1dc5600
S		 2038 REG_SET_BIT(ah, AR_TIMER_MODE,
2039 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2040 AR_DTIM_TIMER_EN);
f078f209 2041
4af9cf4f
S		 2042 /* TSF Out of Range Threshold */
2043 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2044}
7322fd19 2045EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2046
f1dc5600
S		 2047/*******************/
2048/* HW Capabilities */
2049/*******************/
2050
a9a29ce6 2051int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2052{
2660b81a 2053 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2054 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2055 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 2056 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 2057
f1dc5600 2058 u16 capField = 0, eeval;
f078f209 2059
f74df6fb 2060 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2061 regulatory->current_rd = eeval;
f078f209 2062
f74df6fb 2063 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 2064 if (AR_SREV_9285_10_OR_LATER(ah))
2065 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 2066 regulatory->current_rd_ext = eeval;
f078f209 2067
f74df6fb 2068 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 2069
2660b81a 2070 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2071 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2072 if (regulatory->current_rd == 0x64 ||
2073 regulatory->current_rd == 0x65)
2074 regulatory->current_rd += 5;
2075 else if (regulatory->current_rd == 0x41)
2076 regulatory->current_rd = 0x43;
c46917bb
LR		 2077 ath_print(common, ATH_DBG_REGULATORY,
2078 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 2079 }
f078f209 2080
f74df6fb 2081 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6
GJ		 2082 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2083 ath_print(common, ATH_DBG_FATAL,
2084 "no band has been marked as supported in EEPROM.\n");
2085 return -EINVAL;
2086 }
2087
f1dc5600 2088 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 2089
f1dc5600
S		 2090 if (eeval & AR5416_OPFLAGS_11A) {
2091 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 2092 if (ah->config.ht_enable) {
f1dc5600
S		 2093 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2094 set_bit(ATH9K_MODE_11NA_HT20,
2095 pCap->wireless_modes);
2096 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2097 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2098 pCap->wireless_modes);
2099 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2100 pCap->wireless_modes);
2101 }
f078f209 2102 }
f078f209
LR		 2103 }
2104
f1dc5600 2105 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 2106 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 2107 if (ah->config.ht_enable) {
f1dc5600
S		 2108 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2109 set_bit(ATH9K_MODE_11NG_HT20,
2110 pCap->wireless_modes);
2111 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2112 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2113 pCap->wireless_modes);
2114 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2115 pCap->wireless_modes);
2116 }
2117 }
f078f209 2118 }
f1dc5600 2119
f74df6fb 2120 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2121 /*
2122 * For AR9271 we will temporarilly uses the rx chainmax as read from
2123 * the EEPROM.
2124 */
8147f5de 2125 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2126 !(eeval & AR5416_OPFLAGS_11A) &&
2127 !(AR_SREV_9271(ah)))
2128 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 2129 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2130 else
d7e7d229 2131 /* Use rx_chainmask from EEPROM. */
8147f5de 2132 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2133
d535a42a 2134 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 2135 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2136
f1dc5600
S		 2137 pCap->low_2ghz_chan = 2312;
2138 pCap->high_2ghz_chan = 2732;
f078f209 2139
f1dc5600
S		 2140 pCap->low_5ghz_chan = 4920;
2141 pCap->high_5ghz_chan = 6100;
f078f209 2142
f1dc5600
S		 2143 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2144 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2145 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 2146
f1dc5600
S		 2147 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2148 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2149 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 2150
2660b81a 2151 if (ah->config.ht_enable)
f1dc5600
S		 2152 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2153 else
2154 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2155
f1dc5600
S		 2156 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2157 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2158 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2159 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 2160
f1dc5600
S		 2161 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2162 pCap->total_queues =
2163 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2164 else
2165 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 2166
f1dc5600
S		 2167 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2168 pCap->keycache_size =
2169 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2170 else
2171 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 2172
f1dc5600 2173 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f4709fdf
LR		 2174
2175 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2176 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2177 else
2178 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 2179
5b5fa355
S		 2180 if (AR_SREV_9271(ah))
2181 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2182 else if (AR_DEVID_7010(ah))
2183 pCap->num_gpio_pins = AR7010_NUM_GPIO;
5b5fa355 2184 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2185 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2186 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 2187 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2188 else
2189 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2190
f1dc5600
S		 2191 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2192 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2193 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2194 } else {
2195 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 2196 }
2197
f1dc5600
S		 2198 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2199
e97275cb 2200#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2201 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2202 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2203 ah->rfkill_gpio =
2204 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2205 ah->rfkill_polarity =
2206 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2207
2208 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2209 }
f1dc5600 2210#endif
d5d1154f 2211 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2212 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2213 else
2214 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2215
e7594072 2216 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2217 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2218 else
2219 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2220
608b88cb 2221 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 2222 pCap->reg_cap =
2223 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2224 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2225 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2226 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 2227 } else {
f1dc5600
S		 2228 pCap->reg_cap =
2229 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2230 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 2231 }
f078f209 2232
ebb90cfc
SB		 2233 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2234 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2235 AR_SREV_5416(ah))
2236 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 2237
2238 pCap->num_antcfg_5ghz =
f74df6fb 2239 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 2240 pCap->num_antcfg_2ghz =
f74df6fb 2241 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 2242
fe12946e 2243 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 2244 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 2245 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2246 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 2247
8c8f9ba7 2248 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 2249 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2250 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 2251 } else {
766ec4a9 2252 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 2253 }
22f25d0d 2254 } else {
766ec4a9 2255 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 2256 }
a9a29ce6 2257
ceb26445 2258 if (AR_SREV_9300_20_OR_LATER(ah)) {
e5553724
VT		 2259 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2260 ATH9K_HW_CAP_FASTCLOCK;
ceb26445
VT		 2261 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2262 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2263 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2264 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2265 pCap->txs_len = sizeof(struct ar9003_txs);
4935250a
FF		 2266 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2267 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 2268 } else {
2269 pCap->tx_desc_len = sizeof(struct ath_desc);
6b42e8d0
FF		 2270 if (AR_SREV_9280_20(ah) &&
2271 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2272 AR5416_EEP_MINOR_VER_16) ||
2273 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2274 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2275 }
1adf02ff 2276
6c84ce08
VT		 2277 if (AR_SREV_9300_20_OR_LATER(ah))
2278 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2279
b4dec5e8 2280 if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2281 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2282
a9a29ce6 2283 return 0;
f078f209
LR		 2284}
2285
f1dc5600
S		 2286/****************************/
2287/* GPIO / RFKILL / Antennae */
2288/****************************/
f078f209 2289
cbe61d8a 2290static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2291 u32 gpio, u32 type)
2292{
2293 int addr;
2294 u32 gpio_shift, tmp;
f078f209 2295
f1dc5600
S		 2296 if (gpio > 11)
2297 addr = AR_GPIO_OUTPUT_MUX3;
2298 else if (gpio > 5)
2299 addr = AR_GPIO_OUTPUT_MUX2;
2300 else
2301 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2302
f1dc5600 2303 gpio_shift = (gpio % 6) * 5;
f078f209 2304
f1dc5600
S		 2305 if (AR_SREV_9280_20_OR_LATER(ah)
2306 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2307 REG_RMW(ah, addr, (type << gpio_shift),
2308 (0x1f << gpio_shift));
f078f209 2309 } else {
f1dc5600
S		 2310 tmp = REG_READ(ah, addr);
2311 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2312 tmp &= ~(0x1f << gpio_shift);
2313 tmp |= (type << gpio_shift);
2314 REG_WRITE(ah, addr, tmp);
f078f209 2315 }
f078f209
LR		 2316}
2317
cbe61d8a 2318void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2319{
f1dc5600 2320 u32 gpio_shift;
f078f209 2321
9680e8a3 2322 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2323
88c1f4f6
S		 2324 if (AR_DEVID_7010(ah)) {
2325 gpio_shift = gpio;
2326 REG_RMW(ah, AR7010_GPIO_OE,
2327 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2328 (AR7010_GPIO_OE_MASK << gpio_shift));
2329 return;
2330 }
f078f209 2331
88c1f4f6 2332 gpio_shift = gpio << 1;
f1dc5600
S		 2333 REG_RMW(ah,
2334 AR_GPIO_OE_OUT,
2335 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2336 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2337}
7322fd19 2338EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2339
cbe61d8a 2340u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2341{
cb33c412
SB		 2342#define MS_REG_READ(x, y) \
2343 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2344
2660b81a 2345 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2346 return 0xffffffff;
f078f209 2347
88c1f4f6
S		 2348 if (AR_DEVID_7010(ah)) {
2349 u32 val;
2350 val = REG_READ(ah, AR7010_GPIO_IN);
2351 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2352 } else if (AR_SREV_9300_20_OR_LATER(ah))
783dfca1
FF		 2353 return MS_REG_READ(AR9300, gpio) != 0;
2354 else if (AR_SREV_9271(ah))
5b5fa355
S		 2355 return MS_REG_READ(AR9271, gpio) != 0;
2356 else if (AR_SREV_9287_10_OR_LATER(ah))
ac88b6ec
VN		 2357 return MS_REG_READ(AR9287, gpio) != 0;
2358 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2359 return MS_REG_READ(AR9285, gpio) != 0;
2360 else if (AR_SREV_9280_10_OR_LATER(ah))
2361 return MS_REG_READ(AR928X, gpio) != 0;
2362 else
2363 return MS_REG_READ(AR, gpio) != 0;
f078f209 2364}
7322fd19 2365EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2366
cbe61d8a 2367void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2368 u32 ah_signal_type)
f078f209 2369{
f1dc5600 2370 u32 gpio_shift;
f078f209 2371
88c1f4f6
S		 2372 if (AR_DEVID_7010(ah)) {
2373 gpio_shift = gpio;
2374 REG_RMW(ah, AR7010_GPIO_OE,
2375 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2376 (AR7010_GPIO_OE_MASK << gpio_shift));
2377 return;
2378 }
f078f209 2379
88c1f4f6 2380 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2381 gpio_shift = 2 * gpio;
f1dc5600
S		 2382 REG_RMW(ah,
2383 AR_GPIO_OE_OUT,
2384 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2385 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2386}
7322fd19 2387EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2388
cbe61d8a 2389void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2390{
88c1f4f6
S		 2391 if (AR_DEVID_7010(ah)) {
2392 val = val ? 0 : 1;
2393 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2394 AR_GPIO_BIT(gpio));
2395 return;
2396 }
2397
5b5fa355
S		 2398 if (AR_SREV_9271(ah))
2399 val = ~val;
2400
f1dc5600
S		 2401 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2402 AR_GPIO_BIT(gpio));
f078f209 2403}
7322fd19 2404EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2405
cbe61d8a 2406u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2407{
f1dc5600 2408 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2409}
7322fd19 2410EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2411
cbe61d8a 2412void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2413{
f1dc5600 2414 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2415}
7322fd19 2416EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2417
f1dc5600
S		 2418/*********************/
2419/* General Operation */
2420/*********************/
2421
cbe61d8a 2422u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2423{
f1dc5600
S		 2424 u32 bits = REG_READ(ah, AR_RX_FILTER);
2425 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2426
f1dc5600
S		 2427 if (phybits & AR_PHY_ERR_RADAR)
2428 bits |= ATH9K_RX_FILTER_PHYRADAR;
2429 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2430 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2431
f1dc5600 2432 return bits;
f078f209 2433}
7322fd19 2434EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2435
cbe61d8a 2436void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2437{
f1dc5600 2438 u32 phybits;
f078f209 2439
7d0d0df0
S		 2440 ENABLE_REGWRITE_BUFFER(ah);
2441
7ea310be
S		 2442 REG_WRITE(ah, AR_RX_FILTER, bits);
2443
f1dc5600
S		 2444 phybits = 0;
2445 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2446 phybits |= AR_PHY_ERR_RADAR;
2447 if (bits & ATH9K_RX_FILTER_PHYERR)
2448 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2449 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2450
f1dc5600
S		 2451 if (phybits)
2452 REG_WRITE(ah, AR_RXCFG,
2453 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2454 else
2455 REG_WRITE(ah, AR_RXCFG,
2456 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2457
2458 REGWRITE_BUFFER_FLUSH(ah);
2459 DISABLE_REGWRITE_BUFFER(ah);
f1dc5600 2460}
7322fd19 2461EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2462
cbe61d8a 2463bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2464{
63a75b91
SB		 2465 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2466 return false;
2467
2468 ath9k_hw_init_pll(ah, NULL);
2469 return true;
f1dc5600 2470}
7322fd19 2471EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2472
cbe61d8a 2473bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2474{
9ecdef4b 2475 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2476 return false;
f078f209 2477
63a75b91
SB		 2478 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2479 return false;
2480
2481 ath9k_hw_init_pll(ah, NULL);
2482 return true;
f078f209 2483}
7322fd19 2484EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2485
8fbff4b8 2486void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 2487{
608b88cb 2488 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2489 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2490 struct ieee80211_channel *channel = chan->chan;
f078f209 2491
608b88cb 2492 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2493
8fbff4b8 2494 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2495 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2496 channel->max_antenna_gain * 2,
2497 channel->max_power * 2,
2498 min((u32) MAX_RATE_POWER,
608b88cb 2499 (u32) regulatory->power_limit));
6f255425 2500}
7322fd19 2501EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2502
cbe61d8a 2503void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2504{
2660b81a 2505 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2506}
7322fd19 2507EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2508
cbe61d8a 2509void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2510{
f1dc5600
S		 2511 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2512 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2513}
7322fd19 2514EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2515
f2b2143e 2516void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2517{
1510718d
LR		 2518 struct ath_common *common = ath9k_hw_common(ah);
2519
2520 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2521 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2522 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2523}
7322fd19 2524EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2525
1c0fc65e
BP		 2526#define ATH9K_MAX_TSF_READ 10
2527
cbe61d8a 2528u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2529{
1c0fc65e
BP		 2530 u32 tsf_lower, tsf_upper1, tsf_upper2;
2531 int i;
2532
2533 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2534 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2535 tsf_lower = REG_READ(ah, AR_TSF_L32);
2536 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2537 if (tsf_upper2 == tsf_upper1)
2538 break;
2539 tsf_upper1 = tsf_upper2;
2540 }
f078f209 2541
1c0fc65e 2542 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2543
1c0fc65e 2544 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2545}
7322fd19 2546EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2547
cbe61d8a 2548void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2549{
27abe060 2550 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2551 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2552}
7322fd19 2553EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2554
cbe61d8a 2555void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2556{
f9b604f6
GJ		 2557 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2558 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 2559 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2560 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2561
f1dc5600
S		 2562 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2563}
7322fd19 2564EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2565
54e4cec6 2566void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2567{
f1dc5600 2568 if (setting)
2660b81a 2569 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2570 else
2660b81a 2571 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2572}
7322fd19 2573EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2574
25c56eec 2575void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2576{
25c56eec 2577 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2578 u32 macmode;
2579
25c56eec 2580 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2581 macmode = AR_2040_JOINED_RX_CLEAR;
2582 else
2583 macmode = 0;
f078f209 2584
f1dc5600 2585 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2586}
ff155a45
VT		 2587
2588/* HW Generic timers configuration */
2589
2590static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2591{
2592 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2593 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2594 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2595 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2596 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2597 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2598 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2599 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2600 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2601 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2602 AR_NDP2_TIMER_MODE, 0x0002},
2603 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2604 AR_NDP2_TIMER_MODE, 0x0004},
2605 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2606 AR_NDP2_TIMER_MODE, 0x0008},
2607 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2608 AR_NDP2_TIMER_MODE, 0x0010},
2609 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2610 AR_NDP2_TIMER_MODE, 0x0020},
2611 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2612 AR_NDP2_TIMER_MODE, 0x0040},
2613 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2614 AR_NDP2_TIMER_MODE, 0x0080}
2615};
2616
2617/* HW generic timer primitives */
2618
2619/* compute and clear index of rightmost 1 */
2620static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2621{
2622 u32 b;
2623
2624 b = *mask;
2625 b &= (0-b);
2626 *mask &= ~b;
2627 b *= debruijn32;
2628 b >>= 27;
2629
2630 return timer_table->gen_timer_index[b];
2631}
2632
1773912b 2633u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2634{
2635 return REG_READ(ah, AR_TSF_L32);
2636}
7322fd19 2637EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2638
2639struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2640 void (*trigger)(void *),
2641 void (*overflow)(void *),
2642 void *arg,
2643 u8 timer_index)
2644{
2645 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2646 struct ath_gen_timer *timer;
2647
2648 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2649
2650 if (timer == NULL) {
c46917bb
LR		 2651 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2652 "Failed to allocate memory"
2653 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 2654 return NULL;
2655 }
2656
2657 /* allocate a hardware generic timer slot */
2658 timer_table->timers[timer_index] = timer;
2659 timer->index = timer_index;
2660 timer->trigger = trigger;
2661 timer->overflow = overflow;
2662 timer->arg = arg;
2663
2664 return timer;
2665}
7322fd19 2666EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2667
cd9bf689
LR		 2668void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2669 struct ath_gen_timer *timer,
2670 u32 timer_next,
2671 u32 timer_period)
ff155a45
VT		 2672{
2673 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2674 u32 tsf;
2675
2676 BUG_ON(!timer_period);
2677
2678 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2679
2680 tsf = ath9k_hw_gettsf32(ah);
2681
c46917bb
LR		 2682 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2683 "curent tsf %x period %x"
2684 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 2685
2686 /*
2687 * Pull timer_next forward if the current TSF already passed it
2688 * because of software latency
2689 */
2690 if (timer_next < tsf)
2691 timer_next = tsf + timer_period;
2692
2693 /*
2694 * Program generic timer registers
2695 */
2696 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2697 timer_next);
2698 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2699 timer_period);
2700 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2701 gen_tmr_configuration[timer->index].mode_mask);
2702
2703 /* Enable both trigger and thresh interrupt masks */
2704 REG_SET_BIT(ah, AR_IMR_S5,
2705 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2706 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2707}
7322fd19 2708EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2709
cd9bf689 2710void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2711{
2712 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2713
2714 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2715 (timer->index >= ATH_MAX_GEN_TIMER)) {
2716 return;
2717 }
2718
2719 /* Clear generic timer enable bits. */
2720 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2721 gen_tmr_configuration[timer->index].mode_mask);
2722
2723 /* Disable both trigger and thresh interrupt masks */
2724 REG_CLR_BIT(ah, AR_IMR_S5,
2725 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2726 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2727
2728 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 2729}
7322fd19 2730EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2731
2732void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2733{
2734 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2735
2736 /* free the hardware generic timer slot */
2737 timer_table->timers[timer->index] = NULL;
2738 kfree(timer);
2739}
7322fd19 2740EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2741
2742/*
2743 * Generic Timer Interrupts handling
2744 */
2745void ath_gen_timer_isr(struct ath_hw *ah)
2746{
2747 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2748 struct ath_gen_timer *timer;
c46917bb 2749 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 2750 u32 trigger_mask, thresh_mask, index;
2751
2752 /* get hardware generic timer interrupt status */
2753 trigger_mask = ah->intr_gen_timer_trigger;
2754 thresh_mask = ah->intr_gen_timer_thresh;
2755 trigger_mask &= timer_table->timer_mask.val;
2756 thresh_mask &= timer_table->timer_mask.val;
2757
2758 trigger_mask &= ~thresh_mask;
2759
2760 while (thresh_mask) {
2761 index = rightmost_index(timer_table, &thresh_mask);
2762 timer = timer_table->timers[index];
2763 BUG_ON(!timer);
c46917bb
LR		 2764 ath_print(common, ATH_DBG_HWTIMER,
2765 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 2766 timer->overflow(timer->arg);
2767 }
2768
2769 while (trigger_mask) {
2770 index = rightmost_index(timer_table, &trigger_mask);
2771 timer = timer_table->timers[index];
2772 BUG_ON(!timer);
c46917bb
LR		 2773 ath_print(common, ATH_DBG_HWTIMER,
2774 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 2775 timer->trigger(timer->arg);
2776 }
2777}
7322fd19 2778EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2779
05020d23
S		 2780/********/
2781/* HTC */
2782/********/
2783
2784void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2785{
2786 ah->htc_reset_init = true;
2787}
2788EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2789
2da4f01a
LR		 2790static struct {
2791 u32 version;
2792 const char * name;
2793} ath_mac_bb_names[] = {
2794 /* Devices with external radios */
2795 { AR_SREV_VERSION_5416_PCI, "5416" },
2796 { AR_SREV_VERSION_5416_PCIE, "5418" },
2797 { AR_SREV_VERSION_9100, "9100" },
2798 { AR_SREV_VERSION_9160, "9160" },
2799 /* Single-chip solutions */
2800 { AR_SREV_VERSION_9280, "9280" },
2801 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 2802 { AR_SREV_VERSION_9287, "9287" },
2803 { AR_SREV_VERSION_9271, "9271" },
ec83903e 2804 { AR_SREV_VERSION_9300, "9300" },
2da4f01a
LR		 2805};
2806
2807/* For devices with external radios */
2808static struct {
2809 u16 version;
2810 const char * name;
2811} ath_rf_names[] = {
2812 { 0, "5133" },
2813 { AR_RAD5133_SREV_MAJOR, "5133" },
2814 { AR_RAD5122_SREV_MAJOR, "5122" },
2815 { AR_RAD2133_SREV_MAJOR, "2133" },
2816 { AR_RAD2122_SREV_MAJOR, "2122" }
2817};
2818
2819/*
2820 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2821 */
f934c4d9 2822static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 2823{
2824 int i;
2825
2826 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2827 if (ath_mac_bb_names[i].version == mac_bb_version) {
2828 return ath_mac_bb_names[i].name;
2829 }
2830 }
2831
2832 return "????";
2833}
2da4f01a
LR		 2834
2835/*
2836 * Return the RF name. "????" is returned if the RF is unknown.
2837 * Used for devices with external radios.
2838 */
f934c4d9 2839static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 2840{
2841 int i;
2842
2843 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2844 if (ath_rf_names[i].version == rf_version) {
2845 return ath_rf_names[i].name;
2846 }
2847 }
2848
2849 return "????";
2850}
f934c4d9
LR		 2851
2852void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2853{
2854 int used;
2855
2856 /* chipsets >= AR9280 are single-chip */
2857 if (AR_SREV_9280_10_OR_LATER(ah)) {
2858 used = snprintf(hw_name, len,
2859 "Atheros AR%s Rev:%x",
2860 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2861 ah->hw_version.macRev);
2862 }
2863 else {
2864 used = snprintf(hw_name, len,
2865 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2866 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2867 ah->hw_version.macRev,
2868 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2869 AR_RADIO_SREV_MAJOR)),
2870 ah->hw_version.phyRev);
2871 }
2872
2873 hw_name[used] = '\0';
2874}
2875EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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