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mac80211: fix the increment of unicast/multicast counters for forwarded PREQ
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
f078f209
LR		 20#include <asm/unaligned.h>
21
af03abec 22#include "hw.h"
d70357d5 23#include "hw-ops.h"
cfe8cba9 24#include "rc.h"
b622a720 25#include "ar9003_mac.h"
f4701b5a 26#include "ar9003_mci.h"
462e58f2
BG		 27#include "debug.h"
28#include "ath9k.h"
f078f209 29
cbe61d8a 30static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 31
7322fd19
LR		 32MODULE_AUTHOR("Atheros Communications");
33MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
34MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
35MODULE_LICENSE("Dual BSD/GPL");
36
37static int __init ath9k_init(void)
38{
39 return 0;
40}
41module_init(ath9k_init);
42
43static void __exit ath9k_exit(void)
44{
45 return;
46}
47module_exit(ath9k_exit);
48
d70357d5
LR		 49/* Private hardware callbacks */
50
51static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
52{
53 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
54}
55
56static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
57{
58 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
59}
60
64773964
LR		 61static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
62 struct ath9k_channel *chan)
63{
64 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
65}
66
991312d8
LR		 67static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
68{
69 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
70 return;
71
72 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
73}
74
e36b27af
LR		 75static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
76{
77 /* You will not have this callback if using the old ANI */
78 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
79 return;
80
81 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
82}
83
f1dc5600
S		 84/********************/
85/* Helper Functions */
86/********************/
f078f209 87
462e58f2
BG		 88#ifdef CONFIG_ATH9K_DEBUGFS
89
90void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
91{
92 struct ath_softc *sc = common->priv;
93 if (sync_cause)
94 sc->debug.stats.istats.sync_cause_all++;
95 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
96 sc->debug.stats.istats.sync_rtc_irq++;
97 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
98 sc->debug.stats.istats.sync_mac_irq++;
99 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
100 sc->debug.stats.istats.eeprom_illegal_access++;
101 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
102 sc->debug.stats.istats.apb_timeout++;
103 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
104 sc->debug.stats.istats.pci_mode_conflict++;
105 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
106 sc->debug.stats.istats.host1_fatal++;
107 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
108 sc->debug.stats.istats.host1_perr++;
109 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
110 sc->debug.stats.istats.trcv_fifo_perr++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
112 sc->debug.stats.istats.radm_cpl_ep++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
114 sc->debug.stats.istats.radm_cpl_dllp_abort++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
116 sc->debug.stats.istats.radm_cpl_tlp_abort++;
117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
118 sc->debug.stats.istats.radm_cpl_ecrc_err++;
119 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
120 sc->debug.stats.istats.radm_cpl_timeout++;
121 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
122 sc->debug.stats.istats.local_timeout++;
123 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
124 sc->debug.stats.istats.pm_access++;
125 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
126 sc->debug.stats.istats.mac_awake++;
127 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
128 sc->debug.stats.istats.mac_asleep++;
129 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
130 sc->debug.stats.istats.mac_sleep_access++;
131}
132#endif
133
134
dfdac8ac 135static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 136{
b002a4a9 137 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
dfdac8ac
FF		 138 struct ath_common *common = ath9k_hw_common(ah);
139 unsigned int clockrate;
cbe61d8a 140
087b6ff6
FF		 141 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
142 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
143 clockrate = 117;
144 else if (!ah->curchan) /* should really check for CCK instead */
dfdac8ac
FF		 145 clockrate = ATH9K_CLOCK_RATE_CCK;
146 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
147 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
148 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
149 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 150 else
dfdac8ac
FF		 151 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
152
153 if (conf_is_ht40(conf))
154 clockrate *= 2;
155
906c7205
FF		 156 if (ah->curchan) {
157 if (IS_CHAN_HALF_RATE(ah->curchan))
158 clockrate /= 2;
159 if (IS_CHAN_QUARTER_RATE(ah->curchan))
160 clockrate /= 4;
161 }
162
dfdac8ac 163 common->clockrate = clockrate;
f1dc5600
S		 164}
165
cbe61d8a 166static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 167{
dfdac8ac 168 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 169
dfdac8ac 170 return usecs * common->clockrate;
f1dc5600 171}
f078f209 172
0caa7b14 173bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 174{
175 int i;
176
0caa7b14
S		 177 BUG_ON(timeout < AH_TIME_QUANTUM);
178
179 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 180 if ((REG_READ(ah, reg) & mask) == val)
181 return true;
182
183 udelay(AH_TIME_QUANTUM);
184 }
04bd4638 185
d2182b69 186 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 187 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
188 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 189
f1dc5600 190 return false;
f078f209 191}
7322fd19 192EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 193
7c5adc8d
FF		 194void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
195 int hw_delay)
196{
197 if (IS_CHAN_B(chan))
198 hw_delay = (4 * hw_delay) / 22;
199 else
200 hw_delay /= 10;
201
202 if (IS_CHAN_HALF_RATE(chan))
203 hw_delay *= 2;
204 else if (IS_CHAN_QUARTER_RATE(chan))
205 hw_delay *= 4;
206
207 udelay(hw_delay + BASE_ACTIVATE_DELAY);
208}
209
a9b6b256
FF		 210void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
211 int column, unsigned int *writecnt)
212{
213 int r;
214
215 ENABLE_REGWRITE_BUFFER(ah);
216 for (r = 0; r < array->ia_rows; r++) {
217 REG_WRITE(ah, INI_RA(array, r, 0),
218 INI_RA(array, r, column));
219 DO_DELAY(*writecnt);
220 }
221 REGWRITE_BUFFER_FLUSH(ah);
222}
223
f078f209
LR		 224u32 ath9k_hw_reverse_bits(u32 val, u32 n)
225{
226 u32 retval;
227 int i;
228
229 for (i = 0, retval = 0; i < n; i++) {
230 retval = (retval << 1) | (val & 1);
231 val >>= 1;
232 }
233 return retval;
234}
235
cbe61d8a 236u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 237 u8 phy, int kbps,
f1dc5600
S		 238 u32 frameLen, u16 rateix,
239 bool shortPreamble)
f078f209 240{
f1dc5600 241 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 242
f1dc5600
S		 243 if (kbps == 0)
244 return 0;
f078f209 245
545750d3 246 switch (phy) {
46d14a58 247 case WLAN_RC_PHY_CCK:
f1dc5600 248 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 249 if (shortPreamble)
f1dc5600
S		 250 phyTime >>= 1;
251 numBits = frameLen << 3;
252 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
253 break;
46d14a58 254 case WLAN_RC_PHY_OFDM:
2660b81a 255 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 256 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
257 numBits = OFDM_PLCP_BITS + (frameLen << 3);
258 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
259 txTime = OFDM_SIFS_TIME_QUARTER
260 + OFDM_PREAMBLE_TIME_QUARTER
261 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 262 } else if (ah->curchan &&
263 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
265 numBits = OFDM_PLCP_BITS + (frameLen << 3);
266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
267 txTime = OFDM_SIFS_TIME_HALF +
268 OFDM_PREAMBLE_TIME_HALF
269 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
270 } else {
271 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
272 numBits = OFDM_PLCP_BITS + (frameLen << 3);
273 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
274 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
275 + (numSymbols * OFDM_SYMBOL_TIME);
276 }
277 break;
278 default:
3800276a
JP		 279 ath_err(ath9k_hw_common(ah),
280 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 281 txTime = 0;
282 break;
283 }
f078f209 284
f1dc5600
S		 285 return txTime;
286}
7322fd19 287EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 288
cbe61d8a 289void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 290 struct ath9k_channel *chan,
291 struct chan_centers *centers)
f078f209 292{
f1dc5600 293 int8_t extoff;
f078f209 294
f1dc5600
S		 295 if (!IS_CHAN_HT40(chan)) {
296 centers->ctl_center = centers->ext_center =
297 centers->synth_center = chan->channel;
298 return;
f078f209 299 }
f078f209 300
f1dc5600
S		 301 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
302 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
303 centers->synth_center =
304 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
305 extoff = 1;
306 } else {
307 centers->synth_center =
308 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
309 extoff = -1;
310 }
f078f209 311
f1dc5600
S		 312 centers->ctl_center =
313 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 314 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 315 centers->ext_center =
6420014c 316 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 317}
318
f1dc5600
S		 319/******************/
320/* Chip Revisions */
321/******************/
322
cbe61d8a 323static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 324{
f1dc5600 325 u32 val;
f078f209 326
ecb1d385
VT		 327 switch (ah->hw_version.devid) {
328 case AR5416_AR9100_DEVID:
329 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
330 break;
3762561a
GJ		 331 case AR9300_DEVID_AR9330:
332 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
333 if (ah->get_mac_revision) {
334 ah->hw_version.macRev = ah->get_mac_revision();
335 } else {
336 val = REG_READ(ah, AR_SREV);
337 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
338 }
339 return;
ecb1d385
VT		 340 case AR9300_DEVID_AR9340:
341 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
342 val = REG_READ(ah, AR_SREV);
343 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
344 return;
345 }
346
f1dc5600 347 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 348
f1dc5600
S		 349 if (val == 0xFF) {
350 val = REG_READ(ah, AR_SREV);
d535a42a
S		 351 ah->hw_version.macVersion =
352 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
353 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 354
423e38e8 355 if (AR_SREV_9462(ah))
76ed94be
MSS		 356 ah->is_pciexpress = true;
357 else
358 ah->is_pciexpress = (val &
359 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 360 } else {
361 if (!AR_SREV_9100(ah))
d535a42a 362 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 363
d535a42a 364 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 365
d535a42a 366 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 367 ah->is_pciexpress = true;
f1dc5600 368 }
f078f209
LR		 369}
370
f1dc5600
S		 371/************************************/
372/* HW Attach, Detach, Init Routines */
373/************************************/
374
cbe61d8a 375static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 376{
040b74f7 377 if (!AR_SREV_5416(ah))
f1dc5600 378 return;
f078f209 379
f1dc5600
S		 380 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
384 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
385 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
386 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
387 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
388 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 389
f1dc5600 390 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 391}
392
d4930086
SG		 393static void ath9k_hw_aspm_init(struct ath_hw *ah)
394{
395 struct ath_common *common = ath9k_hw_common(ah);
396
397 if (common->bus_ops->aspm_init)
398 common->bus_ops->aspm_init(common);
399}
400
1f3f0618 401/* This should work for all families including legacy */
cbe61d8a 402static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 403{
c46917bb 404 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 405 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 406 u32 regHold[2];
07b2fa5a
JP		 407 static const u32 patternData[4] = {
408 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
409 };
1f3f0618 410 int i, j, loop_max;
f078f209 411
1f3f0618
SB		 412 if (!AR_SREV_9300_20_OR_LATER(ah)) {
413 loop_max = 2;
414 regAddr[1] = AR_PHY_BASE + (8 << 2);
415 } else
416 loop_max = 1;
417
418 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 419 u32 addr = regAddr[i];
420 u32 wrData, rdData;
f078f209 421
f1dc5600
S		 422 regHold[i] = REG_READ(ah, addr);
423 for (j = 0; j < 0x100; j++) {
424 wrData = (j << 16) | j;
425 REG_WRITE(ah, addr, wrData);
426 rdData = REG_READ(ah, addr);
427 if (rdData != wrData) {
3800276a
JP		 428 ath_err(common,
429 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
430 addr, wrData, rdData);
f1dc5600
S		 431 return false;
432 }
433 }
434 for (j = 0; j < 4; j++) {
435 wrData = patternData[j];
436 REG_WRITE(ah, addr, wrData);
437 rdData = REG_READ(ah, addr);
438 if (wrData != rdData) {
3800276a
JP		 439 ath_err(common,
440 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
441 addr, wrData, rdData);
f1dc5600
S		 442 return false;
443 }
f078f209 444 }
f1dc5600 445 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 446 }
f1dc5600 447 udelay(100);
cbe61d8a 448
f078f209
LR		 449 return true;
450}
451
b8b0f377 452static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 453{
454 int i;
f078f209 455
689e756f
FF		 456 ah->config.dma_beacon_response_time = 1;
457 ah->config.sw_beacon_response_time = 6;
2660b81a
S		 458 ah->config.additional_swba_backoff = 0;
459 ah->config.ack_6mb = 0x0;
460 ah->config.cwm_ignore_extcca = 0;
2660b81a 461 ah->config.pcie_clock_req = 0;
2660b81a
S		 462 ah->config.pcie_waen = 0;
463 ah->config.analog_shiftreg = 1;
03c72518 464 ah->config.enable_ani = true;
f078f209 465
f1dc5600 466 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 467 ah->config.spurchans[i][0] = AR_NO_SPUR;
468 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 469 }
470
6f481010
LR		 471 /* PAPRD needs some more work to be enabled */
472 ah->config.paprd_disable = 1;
473
0ce024cb 474 ah->config.rx_intr_mitigation = true;
6a0ec30a 475 ah->config.pcieSerDesWrite = true;
6158425b
LR		 476
477 /*
478 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
479 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
480 * This means we use it for all AR5416 devices, and the few
481 * minor PCI AR9280 devices out there.
482 *
483 * Serialization is required because these devices do not handle
484 * well the case of two concurrent reads/writes due to the latency
485 * involved. During one read/write another read/write can be issued
486 * on another CPU while the previous read/write may still be working
487 * on our hardware, if we hit this case the hardware poops in a loop.
488 * We prevent this by serializing reads and writes.
489 *
490 * This issue is not present on PCI-Express devices or pre-AR5416
491 * devices (legacy, 802.11abg).
492 */
493 if (num_possible_cpus() > 1)
2d6a5e95 494 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 495}
496
50aca25b 497static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 498{
608b88cb
LR		 499 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
500
501 regulatory->country_code = CTRY_DEFAULT;
502 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 503
d535a42a 504 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 505 ah->hw_version.subvendorid = 0;
f078f209 506
2660b81a 507 ah->atim_window = 0;
16f2411f
FF		 508 ah->sta_id1_defaults =
509 AR_STA_ID1_CRPT_MIC_ENABLE |
510 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 511 if (AR_SREV_9100(ah))
512 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
e3f2acc7 513 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 514 ah->globaltxtimeout = (u32) -1;
cbdec975 515 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 516 ah->htc_reset_init = true;
f078f209
LR		 517}
518
cbe61d8a 519static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 520{
1510718d 521 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 522 u32 sum;
523 int i;
524 u16 eeval;
07b2fa5a 525 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 526
527 sum = 0;
528 for (i = 0; i < 3; i++) {
49101676 529 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 530 sum += eeval;
1510718d
LR		 531 common->macaddr[2 * i] = eeval >> 8;
532 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 533 }
d8baa939 534 if (sum == 0 || sum == 0xffff * 3)
f078f209 535 return -EADDRNOTAVAIL;
f078f209
LR		 536
537 return 0;
538}
539
f637cfd6 540static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 541{
6cae913d 542 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 543 int ecode;
f078f209 544
6cae913d 545 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 546 if (!ath9k_hw_chip_test(ah))
547 return -ENODEV;
548 }
f078f209 549
ebd5a14a
LR		 550 if (!AR_SREV_9300_20_OR_LATER(ah)) {
551 ecode = ar9002_hw_rf_claim(ah);
552 if (ecode != 0)
553 return ecode;
554 }
f078f209 555
f637cfd6 556 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 557 if (ecode != 0)
558 return ecode;
7d01b221 559
d2182b69 560 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 561 ah->eep_ops->get_eeprom_ver(ah),
562 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 563
8fe65368
LR		 564 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
565 if (ecode) {
3800276a
JP		 566 ath_err(ath9k_hw_common(ah),
567 "Failed allocating banks for external radio\n");
48a7c3df 568 ath9k_hw_rf_free_ext_banks(ah);
8fe65368 569 return ecode;
574d6b12 570 }
f078f209 571
4279425c 572 if (ah->config.enable_ani) {
f1dc5600 573 ath9k_hw_ani_setup(ah);
f637cfd6 574 ath9k_hw_ani_init(ah);
f078f209
LR		 575 }
576
f078f209
LR		 577 return 0;
578}
579
8525f280 580static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 581{
8525f280
LR		 582 if (AR_SREV_9300_20_OR_LATER(ah))
583 ar9003_hw_attach_ops(ah);
584 else
585 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 586}
587
d70357d5
LR		 588/* Called for all hardware families */
589static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 590{
c46917bb 591 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 592 int r = 0;
aa4058ae 593
ac45c12d
SB		 594 ath9k_hw_read_revisions(ah);
595
0a8d7cb0
SB		 596 /*
597 * Read back AR_WA into a permanent copy and set bits 14 and 17.
598 * We need to do this to avoid RMW of this register. We cannot
599 * read the reg when chip is asleep.
600 */
601 ah->WARegVal = REG_READ(ah, AR_WA);
602 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
603 AR_WA_ASPM_TIMER_BASED_DISABLE);
604
aa4058ae 605 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 606 ath_err(common, "Couldn't reset chip\n");
95fafca2 607 return -EIO;
aa4058ae
LR		 608 }
609
423e38e8 610 if (AR_SREV_9462(ah))
eec353c5
RM		 611 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
612
bab1f62e
LR		 613 ath9k_hw_init_defaults(ah);
614 ath9k_hw_init_config(ah);
615
8525f280 616 ath9k_hw_attach_ops(ah);
d70357d5 617
9ecdef4b 618 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 619 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 620 return -EIO;
aa4058ae
LR		 621 }
622
f3eef645 623 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
aa4058ae 624 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
4c85ab11
JL		 625 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
626 !ah->is_pciexpress)) {
aa4058ae
LR		 627 ah->config.serialize_regmode =
628 SER_REG_MODE_ON;
629 } else {
630 ah->config.serialize_regmode =
631 SER_REG_MODE_OFF;
632 }
633 }
634
d2182b69 635 ath_dbg(common, RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 636 ah->config.serialize_regmode);
637
f4709fdf
LR		 638 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
639 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
640 else
641 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
642
6da5a720
FF		 643 switch (ah->hw_version.macVersion) {
644 case AR_SREV_VERSION_5416_PCI:
645 case AR_SREV_VERSION_5416_PCIE:
646 case AR_SREV_VERSION_9160:
647 case AR_SREV_VERSION_9100:
648 case AR_SREV_VERSION_9280:
649 case AR_SREV_VERSION_9285:
650 case AR_SREV_VERSION_9287:
651 case AR_SREV_VERSION_9271:
652 case AR_SREV_VERSION_9300:
2c8e5937 653 case AR_SREV_VERSION_9330:
6da5a720 654 case AR_SREV_VERSION_9485:
bca04689 655 case AR_SREV_VERSION_9340:
423e38e8 656 case AR_SREV_VERSION_9462:
6da5a720
FF		 657 break;
658 default:
3800276a
JP		 659 ath_err(common,
660 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
661 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 662 return -EOPNOTSUPP;
aa4058ae
LR		 663 }
664
2c8e5937
GJ		 665 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
666 AR_SREV_9330(ah))
d7e7d229
LR		 667 ah->is_pciexpress = false;
668
aa4058ae 669 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 670 ath9k_hw_init_cal_settings(ah);
671
672 ah->ani_function = ATH9K_ANI_ALL;
7a37081e 673 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 674 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 675 if (!AR_SREV_9300_20_OR_LATER(ah))
676 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae 677
4f17c48e
NM		 678 /* disable ANI for 9340 */
679 if (AR_SREV_9340(ah))
4279425c
NM		 680 ah->config.enable_ani = false;
681
aa4058ae
LR		 682 ath9k_hw_init_mode_regs(ah);
683
69ce674b 684 if (!ah->is_pciexpress)
aa4058ae
LR		 685 ath9k_hw_disablepcie(ah);
686
f637cfd6 687 r = ath9k_hw_post_init(ah);
aa4058ae 688 if (r)
95fafca2 689 return r;
aa4058ae
LR		 690
691 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 692 r = ath9k_hw_fill_cap_info(ah);
693 if (r)
694 return r;
695
69ce674b
SG		 696 if (ah->is_pciexpress)
697 ath9k_hw_aspm_init(ah);
698
4f3acf81
LR		 699 r = ath9k_hw_init_macaddr(ah);
700 if (r) {
3800276a 701 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 702 return r;
f078f209
LR		 703 }
704
d7e7d229 705 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 706 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 707 else
2660b81a 708 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 709
88e641df
GJ		 710 if (AR_SREV_9330(ah))
711 ah->bb_watchdog_timeout_ms = 85;
712 else
713 ah->bb_watchdog_timeout_ms = 25;
f078f209 714
211f5859
LR		 715 common->state = ATH_HW_INITIALIZED;
716
4f3acf81 717 return 0;
f078f209
LR		 718}
719
d70357d5 720int ath9k_hw_init(struct ath_hw *ah)
f078f209 721{
d70357d5
LR		 722 int ret;
723 struct ath_common *common = ath9k_hw_common(ah);
f078f209 724
d70357d5
LR		 725 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
726 switch (ah->hw_version.devid) {
727 case AR5416_DEVID_PCI:
728 case AR5416_DEVID_PCIE:
729 case AR5416_AR9100_DEVID:
730 case AR9160_DEVID_PCI:
731 case AR9280_DEVID_PCI:
732 case AR9280_DEVID_PCIE:
733 case AR9285_DEVID_PCIE:
db3cc53a
SB		 734 case AR9287_DEVID_PCI:
735 case AR9287_DEVID_PCIE:
d70357d5 736 case AR2427_DEVID_PCIE:
db3cc53a 737 case AR9300_DEVID_PCIE:
3050c914 738 case AR9300_DEVID_AR9485_PCIE:
999a7a88 739 case AR9300_DEVID_AR9330:
bca04689 740 case AR9300_DEVID_AR9340:
5a63ef0f 741 case AR9300_DEVID_AR9580:
423e38e8 742 case AR9300_DEVID_AR9462:
d70357d5
LR		 743 break;
744 default:
745 if (common->bus_ops->ath_bus_type == ATH_USB)
746 break;
3800276a
JP		 747 ath_err(common, "Hardware device ID 0x%04x not supported\n",
748 ah->hw_version.devid);
d70357d5
LR		 749 return -EOPNOTSUPP;
750 }
f078f209 751
d70357d5
LR		 752 ret = __ath9k_hw_init(ah);
753 if (ret) {
3800276a
JP		 754 ath_err(common,
755 "Unable to initialize hardware; initialization status: %d\n",
756 ret);
d70357d5
LR		 757 return ret;
758 }
f078f209 759
d70357d5 760 return 0;
f078f209 761}
d70357d5 762EXPORT_SYMBOL(ath9k_hw_init);
f078f209 763
cbe61d8a 764static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 765{
7d0d0df0
S		 766 ENABLE_REGWRITE_BUFFER(ah);
767
f1dc5600
S		 768 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
769 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 770
f1dc5600
S		 771 REG_WRITE(ah, AR_QOS_NO_ACK,
772 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
773 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
774 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
775
776 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
777 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
778 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
779 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
780 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 781
782 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 783}
784
b84628eb 785u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 786{
ca7a4deb
FF		 787 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
788 udelay(100);
789 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 790
ca7a4deb
FF		 791 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
792 udelay(100);
b1415819 793
ca7a4deb 794 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 795}
796EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
797
cbe61d8a 798static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 799 struct ath9k_channel *chan)
f078f209 800{
d09b17f7
VT		 801 u32 pll;
802
22983c30 803 if (AR_SREV_9485(ah)) {
22983c30 804
3dfd7f60
VT		 805 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
806 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
807 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
808 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
809 AR_CH0_DPLL2_KD, 0x40);
810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
811 AR_CH0_DPLL2_KI, 0x4);
22983c30 812
3dfd7f60
VT		 813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
814 AR_CH0_BB_DPLL1_REFDIV, 0x5);
815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
816 AR_CH0_BB_DPLL1_NINI, 0x58);
817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
818 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 819
820 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 821 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
822 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
823 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 824 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 825 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 826
3dfd7f60 827 /* program BB PLL phase_shift to 0x6 */
22983c30 828 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 829 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
830
831 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
832 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 833 udelay(1000);
a5415d62
GJ		 834 } else if (AR_SREV_9330(ah)) {
835 u32 ddr_dpll2, pll_control2, kd;
836
837 if (ah->is_clk_25mhz) {
838 ddr_dpll2 = 0x18e82f01;
839 pll_control2 = 0xe04a3d;
840 kd = 0x1d;
841 } else {
842 ddr_dpll2 = 0x19e82f01;
843 pll_control2 = 0x886666;
844 kd = 0x3d;
845 }
846
847 /* program DDR PLL ki and kd value */
848 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
849
850 /* program DDR PLL phase_shift */
851 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
852 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
853
854 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
855 udelay(1000);
856
857 /* program refdiv, nint, frac to RTC register */
858 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
859
860 /* program BB PLL kd and ki value */
861 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
862 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
863
864 /* program BB PLL phase_shift */
865 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
866 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
0b488ac6
VT		 867 } else if (AR_SREV_9340(ah)) {
868 u32 regval, pll2_divint, pll2_divfrac, refdiv;
869
870 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
871 udelay(1000);
872
873 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
874 udelay(100);
875
876 if (ah->is_clk_25mhz) {
877 pll2_divint = 0x54;
878 pll2_divfrac = 0x1eb85;
879 refdiv = 3;
880 } else {
881 pll2_divint = 88;
882 pll2_divfrac = 0;
883 refdiv = 5;
884 }
885
886 regval = REG_READ(ah, AR_PHY_PLL_MODE);
887 regval |= (0x1 << 16);
888 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
889 udelay(100);
890
891 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
892 (pll2_divint << 18) | pll2_divfrac);
893 udelay(100);
894
895 regval = REG_READ(ah, AR_PHY_PLL_MODE);
896 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
897 (0x4 << 26) | (0x18 << 19);
898 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
899 REG_WRITE(ah, AR_PHY_PLL_MODE,
900 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
901 udelay(1000);
22983c30 902 }
d09b17f7
VT		 903
904 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 905
d03a66c1 906 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 907
a5415d62 908 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
3dfd7f60
VT		 909 udelay(1000);
910
c75724d1
LR		 911 /* Switch the core clock for ar9271 to 117Mhz */
912 if (AR_SREV_9271(ah)) {
25e2ab17
S		 913 udelay(500);
914 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 915 }
916
f1dc5600
S		 917 udelay(RTC_PLL_SETTLE_DELAY);
918
919 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6
VT		 920
921 if (AR_SREV_9340(ah)) {
922 if (ah->is_clk_25mhz) {
923 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
924 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
925 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
926 } else {
927 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
928 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
929 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
930 }
931 udelay(100);
932 }
f078f209
LR		 933}
934
cbe61d8a 935static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 936 enum nl80211_iftype opmode)
f078f209 937{
79d1d2b8 938 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 939 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 940 AR_IMR_TXURN |
941 AR_IMR_RXERR |
942 AR_IMR_RXORN |
943 AR_IMR_BCNMISC;
f078f209 944
79d1d2b8
VT		 945 if (AR_SREV_9340(ah))
946 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
947
66860240
VT		 948 if (AR_SREV_9300_20_OR_LATER(ah)) {
949 imr_reg |= AR_IMR_RXOK_HP;
950 if (ah->config.rx_intr_mitigation)
951 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
952 else
953 imr_reg |= AR_IMR_RXOK_LP;
f078f209 954
66860240
VT		 955 } else {
956 if (ah->config.rx_intr_mitigation)
957 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
958 else
959 imr_reg |= AR_IMR_RXOK;
960 }
f078f209 961
66860240
VT		 962 if (ah->config.tx_intr_mitigation)
963 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
964 else
965 imr_reg |= AR_IMR_TXOK;
f078f209 966
d97809db 967 if (opmode == NL80211_IFTYPE_AP)
152d530d 968 imr_reg |= AR_IMR_MIB;
f078f209 969
7d0d0df0
S		 970 ENABLE_REGWRITE_BUFFER(ah);
971
152d530d 972 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 973 ah->imrs2_reg |= AR_IMR_S2_GTT;
974 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 975
f1dc5600
S		 976 if (!AR_SREV_9100(ah)) {
977 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 978 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 979 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
980 }
66860240 981
7d0d0df0 982 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 983
66860240
VT		 984 if (AR_SREV_9300_20_OR_LATER(ah)) {
985 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
986 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
987 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
988 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
989 }
f078f209
LR		 990}
991
b6ba41bb
FF		 992static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
993{
994 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
995 val = min(val, (u32) 0xFFFF);
996 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
997}
998
0005baf4 999static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 1000{
0005baf4
FF		 1001 u32 val = ath9k_hw_mac_to_clks(ah, us);
1002 val = min(val, (u32) 0xFFFF);
1003 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 1004}
1005
0005baf4 1006static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1007{
0005baf4
FF		 1008 u32 val = ath9k_hw_mac_to_clks(ah, us);
1009 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1010 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1011}
1012
1013static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1014{
1015 u32 val = ath9k_hw_mac_to_clks(ah, us);
1016 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1017 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 1018}
f1dc5600 1019
cbe61d8a 1020static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1021{
f078f209 1022 if (tu > 0xFFFF) {
d2182b69
JP		 1023 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1024 tu);
2660b81a 1025 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1026 return false;
1027 } else {
1028 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1029 ah->globaltxtimeout = tu;
f078f209
LR		 1030 return true;
1031 }
1032}
1033
0005baf4 1034void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1035{
b6ba41bb
FF		 1036 struct ath_common *common = ath9k_hw_common(ah);
1037 struct ieee80211_conf *conf = &common->hw->conf;
1038 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 1039 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 1040 int slottime;
0005baf4 1041 int sifstime;
b6ba41bb
FF		 1042 int rx_lat = 0, tx_lat = 0, eifs = 0;
1043 u32 reg;
0005baf4 1044
d2182b69 1045 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1046 ah->misc_mode);
f078f209 1047
b6ba41bb
FF		 1048 if (!chan)
1049 return;
1050
2660b81a 1051 if (ah->misc_mode != 0)
ca7a4deb 1052 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1053
81a91d57
RM		 1054 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1055 rx_lat = 41;
1056 else
1057 rx_lat = 37;
b6ba41bb
FF		 1058 tx_lat = 54;
1059
e88e4861
FF		 1060 if (IS_CHAN_5GHZ(chan))
1061 sifstime = 16;
1062 else
1063 sifstime = 10;
1064
b6ba41bb
FF		 1065 if (IS_CHAN_HALF_RATE(chan)) {
1066 eifs = 175;
1067 rx_lat *= 2;
1068 tx_lat *= 2;
1069 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1070 tx_lat += 11;
1071
e88e4861 1072 sifstime *= 2;
e115b7ec 1073 ack_offset = 16;
b6ba41bb 1074 slottime = 13;
b6ba41bb
FF		 1075 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1076 eifs = 340;
81a91d57 1077 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1078 tx_lat *= 4;
1079 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1080 tx_lat += 22;
1081
e88e4861 1082 sifstime *= 4;
e115b7ec 1083 ack_offset = 32;
b6ba41bb 1084 slottime = 21;
b6ba41bb 1085 } else {
a7be039d
RM		 1086 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1087 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1088 reg = AR_USEC_ASYNC_FIFO;
1089 } else {
1090 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1091 common->clockrate;
1092 reg = REG_READ(ah, AR_USEC);
1093 }
b6ba41bb
FF		 1094 rx_lat = MS(reg, AR_USEC_RX_LAT);
1095 tx_lat = MS(reg, AR_USEC_TX_LAT);
1096
1097 slottime = ah->slottime;
b6ba41bb 1098 }
0005baf4 1099
e239d859 1100 /* As defined by IEEE 802.11-2007 17.3.8.6 */
e115b7ec 1101 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset;
adb5066a 1102 ctstimeout = acktimeout;
42c4568a
FF		 1103
1104 /*
1105 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1106 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1107 * This was initially only meant to work around an issue with delayed
1108 * BA frames in some implementations, but it has been found to fix ACK
1109 * timeout issues in other cases as well.
1110 */
e115b7ec
FF		 1111 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ &&
1112 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1113 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1114 ctstimeout += 48 - sifstime - ah->slottime;
1115 }
1116
42c4568a 1117
b6ba41bb
FF		 1118 ath9k_hw_set_sifs_time(ah, sifstime);
1119 ath9k_hw_setslottime(ah, slottime);
0005baf4 1120 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1121 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1122 if (ah->globaltxtimeout != (u32) -1)
1123 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1124
1125 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1126 REG_RMW(ah, AR_USEC,
1127 (common->clockrate - 1) |
1128 SM(rx_lat, AR_USEC_RX_LAT) |
1129 SM(tx_lat, AR_USEC_TX_LAT),
1130 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1131
f1dc5600 1132}
0005baf4 1133EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1134
285f2dda 1135void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1136{
211f5859
LR		 1137 struct ath_common *common = ath9k_hw_common(ah);
1138
736b3a27 1139 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 1140 goto free_hw;
1141
9ecdef4b 1142 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 1143
1144free_hw:
8fe65368 1145 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 1146}
285f2dda 1147EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1148
f1dc5600
S		 1149/*******/
1150/* INI */
1151/*******/
1152
8fe65368 1153u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1154{
1155 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1156
1157 if (IS_CHAN_B(chan))
1158 ctl |= CTL_11B;
1159 else if (IS_CHAN_G(chan))
1160 ctl |= CTL_11G;
1161 else
1162 ctl |= CTL_11A;
1163
1164 return ctl;
1165}
1166
f1dc5600
S		 1167/****************************************/
1168/* Reset and Channel Switching Routines */
1169/****************************************/
f1dc5600 1170
cbe61d8a 1171static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1172{
57b32227 1173 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 1174
7d0d0df0
S		 1175 ENABLE_REGWRITE_BUFFER(ah);
1176
d7e7d229
LR		 1177 /*
1178 * set AHB_MODE not to do cacheline prefetches
1179 */
ca7a4deb
FF		 1180 if (!AR_SREV_9300_20_OR_LATER(ah))
1181 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1182
d7e7d229
LR		 1183 /*
1184 * let mac dma reads be in 128 byte chunks
1185 */
ca7a4deb 1186 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1187
7d0d0df0 1188 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1189
d7e7d229
LR		 1190 /*
1191 * Restore TX Trigger Level to its pre-reset value.
1192 * The initial value depends on whether aggregation is enabled, and is
1193 * adjusted whenever underruns are detected.
1194 */
57b32227
FF		 1195 if (!AR_SREV_9300_20_OR_LATER(ah))
1196 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1197
7d0d0df0 1198 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1199
d7e7d229
LR		 1200 /*
1201 * let mac dma writes be in 128 byte chunks
1202 */
ca7a4deb 1203 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1204
d7e7d229
LR		 1205 /*
1206 * Setup receive FIFO threshold to hold off TX activities
1207 */
f1dc5600
S		 1208 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1209
57b32227
FF		 1210 if (AR_SREV_9300_20_OR_LATER(ah)) {
1211 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1212 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1213
1214 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1215 ah->caps.rx_status_len);
1216 }
1217
d7e7d229
LR		 1218 /*
1219 * reduce the number of usable entries in PCU TXBUF to avoid
1220 * wrap around issues.
1221 */
f1dc5600 1222 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1223 /* For AR9285 the number of Fifos are reduced to half.
1224 * So set the usable tx buf size also to half to
1225 * avoid data/delimiter underruns
1226 */
f1dc5600
S		 1227 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1228 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1229 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1230 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1231 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1232 }
744d4025 1233
7d0d0df0 1234 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1235
744d4025
VT		 1236 if (AR_SREV_9300_20_OR_LATER(ah))
1237 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1238}
1239
cbe61d8a 1240static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1241{
ca7a4deb
FF		 1242 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1243 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1244
f1dc5600 1245 switch (opmode) {
d97809db 1246 case NL80211_IFTYPE_ADHOC:
9cb5412b 1247 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb 1248 set |= AR_STA_ID1_ADHOC;
f1dc5600 1249 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1250 break;
ca7a4deb
FF		 1251 case NL80211_IFTYPE_AP:
1252 set |= AR_STA_ID1_STA_AP;
1253 /* fall through */
d97809db 1254 case NL80211_IFTYPE_STATION:
ca7a4deb 1255 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1256 break;
5f841b41 1257 default:
ca7a4deb
FF		 1258 if (!ah->is_monitoring)
1259 set = 0;
5f841b41 1260 break;
f1dc5600 1261 }
ca7a4deb 1262 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1263}
1264
8fe65368
LR		 1265void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1266 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1267{
1268 u32 coef_exp, coef_man;
1269
1270 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1271 if ((coef_scaled >> coef_exp) & 0x1)
1272 break;
1273
1274 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1275
1276 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1277
1278 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1279 *coef_exponent = coef_exp - 16;
1280}
1281
cbe61d8a 1282static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1283{
1284 u32 rst_flags;
1285 u32 tmpReg;
1286
70768496 1287 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1288 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1289 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1290 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1291 }
1292
7d0d0df0
S		 1293 ENABLE_REGWRITE_BUFFER(ah);
1294
9a658d2b
LR		 1295 if (AR_SREV_9300_20_OR_LATER(ah)) {
1296 REG_WRITE(ah, AR_WA, ah->WARegVal);
1297 udelay(10);
1298 }
1299
f1dc5600
S		 1300 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1301 AR_RTC_FORCE_WAKE_ON_INT);
1302
1303 if (AR_SREV_9100(ah)) {
1304 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1305 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1306 } else {
1307 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1308 if (tmpReg &
1309 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1310 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1311 u32 val;
f1dc5600 1312 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1313
1314 val = AR_RC_HOSTIF;
1315 if (!AR_SREV_9300_20_OR_LATER(ah))
1316 val |= AR_RC_AHB;
1317 REG_WRITE(ah, AR_RC, val);
1318
1319 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1320 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1321
1322 rst_flags = AR_RTC_RC_MAC_WARM;
1323 if (type == ATH9K_RESET_COLD)
1324 rst_flags |= AR_RTC_RC_MAC_COLD;
1325 }
1326
7d95847c
GJ		 1327 if (AR_SREV_9330(ah)) {
1328 int npend = 0;
1329 int i;
1330
1331 /* AR9330 WAR:
1332 * call external reset function to reset WMAC if:
1333 * - doing a cold reset
1334 * - we have pending frames in the TX queues
1335 */
1336
1337 for (i = 0; i < AR_NUM_QCU; i++) {
1338 npend = ath9k_hw_numtxpending(ah, i);
1339 if (npend)
1340 break;
1341 }
1342
1343 if (ah->external_reset &&
1344 (npend || type == ATH9K_RESET_COLD)) {
1345 int reset_err = 0;
1346
d2182b69 1347 ath_dbg(ath9k_hw_common(ah), RESET,
7d95847c
GJ		 1348 "reset MAC via external reset\n");
1349
1350 reset_err = ah->external_reset();
1351 if (reset_err) {
1352 ath_err(ath9k_hw_common(ah),
1353 "External reset failed, err=%d\n",
1354 reset_err);
1355 return false;
1356 }
1357
1358 REG_WRITE(ah, AR_RTC_RESET, 1);
1359 }
1360 }
1361
d03a66c1 1362 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1363
1364 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1365
f1dc5600
S		 1366 udelay(50);
1367
d03a66c1 1368 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1369 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1370 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1371 return false;
1372 }
1373
1374 if (!AR_SREV_9100(ah))
1375 REG_WRITE(ah, AR_RC, 0);
1376
f1dc5600
S		 1377 if (AR_SREV_9100(ah))
1378 udelay(50);
1379
1380 return true;
1381}
1382
cbe61d8a 1383static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1384{
7d0d0df0
S		 1385 ENABLE_REGWRITE_BUFFER(ah);
1386
9a658d2b
LR		 1387 if (AR_SREV_9300_20_OR_LATER(ah)) {
1388 REG_WRITE(ah, AR_WA, ah->WARegVal);
1389 udelay(10);
1390 }
1391
f1dc5600
S		 1392 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1393 AR_RTC_FORCE_WAKE_ON_INT);
1394
42d5bc3f 1395 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1396 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1397
d03a66c1 1398 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1399
7d0d0df0 1400 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1401
84e2169b
SB		 1402 if (!AR_SREV_9300_20_OR_LATER(ah))
1403 udelay(2);
1404
1405 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1406 REG_WRITE(ah, AR_RC, 0);
1407
d03a66c1 1408 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1409
1410 if (!ath9k_hw_wait(ah,
1411 AR_RTC_STATUS,
1412 AR_RTC_STATUS_M,
0caa7b14
S		 1413 AR_RTC_STATUS_ON,
1414 AH_WAIT_TIMEOUT)) {
d2182b69 1415 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1416 return false;
f078f209
LR		 1417 }
1418
f1dc5600
S		 1419 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1420}
1421
cbe61d8a 1422static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1423{
7a9233ff 1424 bool ret = false;
2577c6e8 1425
9a658d2b
LR		 1426 if (AR_SREV_9300_20_OR_LATER(ah)) {
1427 REG_WRITE(ah, AR_WA, ah->WARegVal);
1428 udelay(10);
1429 }
1430
f1dc5600
S		 1431 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1432 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1433
1434 switch (type) {
1435 case ATH9K_RESET_POWER_ON:
7a9233ff
MSS		 1436 ret = ath9k_hw_set_reset_power_on(ah);
1437 break;
f1dc5600
S		 1438 case ATH9K_RESET_WARM:
1439 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1440 ret = ath9k_hw_set_reset(ah, type);
1441 break;
f1dc5600 1442 default:
7a9233ff 1443 break;
f1dc5600 1444 }
7a9233ff
MSS		 1445
1446 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1447 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1448
1449 return ret;
f078f209
LR		 1450}
1451
cbe61d8a 1452static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1453 struct ath9k_channel *chan)
f078f209 1454{
9c083af8
FF		 1455 int reset_type = ATH9K_RESET_WARM;
1456
1457 if (AR_SREV_9280(ah)) {
1458 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1459 reset_type = ATH9K_RESET_POWER_ON;
1460 else
1461 reset_type = ATH9K_RESET_COLD;
1462 }
1463
1464 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1465 return false;
f078f209 1466
9ecdef4b 1467 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1468 return false;
f078f209 1469
2660b81a 1470 ah->chip_fullsleep = false;
f1dc5600 1471 ath9k_hw_init_pll(ah, chan);
f1dc5600 1472 ath9k_hw_set_rfmode(ah, chan);
f078f209 1473
f1dc5600 1474 return true;
f078f209
LR		 1475}
1476
cbe61d8a 1477static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1478 struct ath9k_channel *chan)
f078f209 1479{
c46917bb 1480 struct ath_common *common = ath9k_hw_common(ah);
8fe65368 1481 u32 qnum;
0a3b7bac 1482 int r;
5f0c04ea
RM		 1483 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1484 bool band_switch, mode_diff;
1485 u8 ini_reloaded;
1486
1487 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1488 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1489 CHANNEL_5GHZ));
1490 mode_diff = (chan->chanmode != ah->curchan->chanmode);
f078f209
LR		 1491
1492 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1493 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1494 ath_dbg(common, QUEUE,
226afe68 1495 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1496 return false;
1497 }
1498 }
1499
8fe65368 1500 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1501 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1502 return false;
1503 }
1504
5f0c04ea
RM		 1505 if (edma && (band_switch || mode_diff)) {
1506 ath9k_hw_mark_phy_inactive(ah);
1507 udelay(5);
1508
1509 ath9k_hw_init_pll(ah, NULL);
1510
1511 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1512 ath_err(common, "Failed to do fast channel change\n");
1513 return false;
1514 }
1515 }
1516
8fe65368 1517 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1518
8fe65368 1519 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1520 if (r) {
3800276a 1521 ath_err(common, "Failed to set channel\n");
0a3b7bac 1522 return false;
f078f209 1523 }
dfdac8ac 1524 ath9k_hw_set_clockrate(ah);
64ea57d0 1525 ath9k_hw_apply_txpower(ah, chan, false);
8fe65368 1526 ath9k_hw_rfbus_done(ah);
f078f209 1527
f1dc5600
S		 1528 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1529 ath9k_hw_set_delta_slope(ah, chan);
1530
8fe65368 1531 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1532
5f0c04ea 1533 if (edma && (band_switch || mode_diff)) {
a126ff51 1534 ah->ah_flags |= AH_FASTCC;
5f0c04ea
RM		 1535 if (band_switch || ini_reloaded)
1536 ah->eep_ops->set_board_values(ah, chan);
1537
1538 ath9k_hw_init_bb(ah, chan);
1539
1540 if (band_switch || ini_reloaded)
1541 ath9k_hw_init_cal(ah, chan);
a126ff51 1542 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1543 }
1544
f1dc5600
S		 1545 return true;
1546}
1547
691680b8
FF		 1548static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1549{
1550 u32 gpio_mask = ah->gpio_mask;
1551 int i;
1552
1553 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1554 if (!(gpio_mask & 1))
1555 continue;
1556
1557 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1558 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1559 }
1560}
1561
01e18918
RM		 1562static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1563 int *hang_state, int *hang_pos)
1564{
1565 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1566 u32 chain_state, dcs_pos, i;
1567
1568 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1569 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1570 for (i = 0; i < 3; i++) {
1571 if (chain_state == dcu_chain_state[i]) {
1572 *hang_state = chain_state;
1573 *hang_pos = dcs_pos;
1574 return true;
1575 }
1576 }
1577 }
1578 return false;
1579}
1580
1581#define DCU_COMPLETE_STATE 1
1582#define DCU_COMPLETE_STATE_MASK 0x3
1583#define NUM_STATUS_READS 50
1584static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1585{
1586 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1587 u32 i, hang_pos, hang_state, num_state = 6;
1588
1589 comp_state = REG_READ(ah, AR_DMADBG_6);
1590
1591 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1592 ath_dbg(ath9k_hw_common(ah), RESET,
1593 "MAC Hang signature not found at DCU complete\n");
1594 return false;
1595 }
1596
1597 chain_state = REG_READ(ah, dcs_reg);
1598 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1599 goto hang_check_iter;
1600
1601 dcs_reg = AR_DMADBG_5;
1602 num_state = 4;
1603 chain_state = REG_READ(ah, dcs_reg);
1604 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1605 goto hang_check_iter;
1606
1607 ath_dbg(ath9k_hw_common(ah), RESET,
1608 "MAC Hang signature 1 not found\n");
1609 return false;
1610
1611hang_check_iter:
1612 ath_dbg(ath9k_hw_common(ah), RESET,
1613 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1614 chain_state, comp_state, hang_state, hang_pos);
1615
1616 for (i = 0; i < NUM_STATUS_READS; i++) {
1617 chain_state = REG_READ(ah, dcs_reg);
1618 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1619 comp_state = REG_READ(ah, AR_DMADBG_6);
1620
1621 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1622 DCU_COMPLETE_STATE) ||
1623 (chain_state != hang_state))
1624 return false;
1625 }
1626
1627 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1628
1629 return true;
1630}
1631
c9c99e5e 1632bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1633{
c9c99e5e
FF		 1634 int count = 50;
1635 u32 reg;
1636
01e18918
RM		 1637 if (AR_SREV_9300(ah))
1638 return !ath9k_hw_detect_mac_hang(ah);
1639
e17f83ea 1640 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1641 return true;
1642
1643 do {
1644 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1645
c9c99e5e
FF		 1646 if ((reg & 0x7E7FFFEF) == 0x00702400)
1647 continue;
1648
1649 switch (reg & 0x7E000B00) {
1650 case 0x1E000000:
1651 case 0x52000B00:
1652 case 0x18000B00:
1653 continue;
1654 default:
1655 return true;
1656 }
1657 } while (count-- > 0);
3b319aae 1658
c9c99e5e 1659 return false;
3b319aae 1660}
c9c99e5e 1661EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1662
caed6579
SM		 1663/*
1664 * Fast channel change:
1665 * (Change synthesizer based on channel freq without resetting chip)
1666 *
1667 * Don't do FCC when
1668 * - Flag is not set
1669 * - Chip is just coming out of full sleep
1670 * - Channel to be set is same as current channel
1671 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1672 */
1673static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1674{
1675 struct ath_common *common = ath9k_hw_common(ah);
1676 int ret;
1677
1678 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1679 goto fail;
1680
1681 if (ah->chip_fullsleep)
1682 goto fail;
1683
1684 if (!ah->curchan)
1685 goto fail;
1686
1687 if (chan->channel == ah->curchan->channel)
1688 goto fail;
1689
feb7bc99
FF		 1690 if ((ah->curchan->channelFlags | chan->channelFlags) &
1691 (CHANNEL_HALF | CHANNEL_QUARTER))
1692 goto fail;
1693
caed6579
SM		 1694 if ((chan->channelFlags & CHANNEL_ALL) !=
1695 (ah->curchan->channelFlags & CHANNEL_ALL))
1696 goto fail;
1697
1698 if (!ath9k_hw_check_alive(ah))
1699 goto fail;
1700
1701 /*
1702 * For AR9462, make sure that calibration data for
1703 * re-using are present.
1704 */
1705 if (AR_SREV_9462(ah) && (!ah->caldata ||
1706 !ah->caldata->done_txiqcal_once ||
1707 !ah->caldata->done_txclcal_once ||
1708 !ah->caldata->rtt_hist.num_readings))
1709 goto fail;
1710
1711 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1712 ah->curchan->channel, chan->channel);
1713
1714 ret = ath9k_hw_channel_change(ah, chan);
1715 if (!ret)
1716 goto fail;
1717
1718 ath9k_hw_loadnf(ah, ah->curchan);
1719 ath9k_hw_start_nfcal(ah, true);
1720
1721 if ((ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && ar9003_mci_is_ready(ah))
1722 ar9003_mci_2g5g_switch(ah, true);
1723
1724 if (AR_SREV_9271(ah))
1725 ar9002_hw_load_ani_reg(ah, chan);
1726
1727 return 0;
1728fail:
1729 return -EINVAL;
1730}
1731
cbe61d8a 1732int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1733 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1734{
1510718d 1735 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1736 u32 saveLedState;
f078f209
LR		 1737 u32 saveDefAntenna;
1738 u32 macStaId1;
46fe782c 1739 u64 tsf = 0;
8fe65368 1740 int i, r;
caed6579 1741 bool start_mci_reset = false;
63d32967
MSS		 1742 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1743 bool save_fullsleep = ah->chip_fullsleep;
1744
1745 if (mci) {
528e5d36
SM		 1746 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1747 if (start_mci_reset)
1748 return 0;
63d32967
MSS		 1749 }
1750
9ecdef4b 1751 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1752 return -EIO;
f078f209 1753
caed6579
SM		 1754 if (ah->curchan && !ah->chip_fullsleep)
1755 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1756
20bd2a09
FF		 1757 ah->caldata = caldata;
1758 if (caldata &&
1759 (chan->channel != caldata->channel ||
1760 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1761 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1762 /* Operating channel changed, reset channel calibration data */
1763 memset(caldata, 0, sizeof(*caldata));
1764 ath9k_init_nfcal_hist_buffer(ah, chan);
1765 }
f23fba49 1766 ah->noise = ath9k_hw_getchan_noise(ah, chan);
20bd2a09 1767
caed6579
SM		 1768 if (fastcc) {
1769 r = ath9k_hw_do_fastcc(ah, chan);
1770 if (!r)
1771 return r;
f078f209
LR		 1772 }
1773
528e5d36
SM		 1774 if (mci)
1775 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1776
f078f209
LR		 1777 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1778 if (saveDefAntenna == 0)
1779 saveDefAntenna = 1;
1780
1781 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1782
46fe782c 1783 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1784 if (AR_SREV_9100(ah) ||
1785 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1786 tsf = ath9k_hw_gettsf64(ah);
1787
f078f209
LR		 1788 saveLedState = REG_READ(ah, AR_CFG_LED) &
1789 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1790 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1791
1792 ath9k_hw_mark_phy_inactive(ah);
1793
45ef6a0b
VT		 1794 ah->paprd_table_write_done = false;
1795
05020d23 1796 /* Only required on the first reset */
d7e7d229
LR		 1797 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1798 REG_WRITE(ah,
1799 AR9271_RESET_POWER_DOWN_CONTROL,
1800 AR9271_RADIO_RF_RST);
1801 udelay(50);
1802 }
1803
f078f209 1804 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1805 ath_err(common, "Chip reset failed\n");
ae8d2858 1806 return -EINVAL;
f078f209
LR		 1807 }
1808
05020d23 1809 /* Only required on the first reset */
d7e7d229
LR		 1810 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1811 ah->htc_reset_init = false;
1812 REG_WRITE(ah,
1813 AR9271_RESET_POWER_DOWN_CONTROL,
1814 AR9271_GATE_MAC_CTL);
1815 udelay(50);
1816 }
1817
46fe782c 1818 /* Restore TSF */
f860d526 1819 if (tsf)
46fe782c
S		 1820 ath9k_hw_settsf64(ah, tsf);
1821
7a37081e 1822 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1823 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1824
e9141f71
S		 1825 if (!AR_SREV_9300_20_OR_LATER(ah))
1826 ar9002_hw_enable_async_fifo(ah);
1827
25c56eec 1828 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1829 if (r)
1830 return r;
f078f209 1831
63d32967
MSS		 1832 if (mci)
1833 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1834
f860d526
FF		 1835 /*
1836 * Some AR91xx SoC devices frequently fail to accept TSF writes
1837 * right after the chip reset. When that happens, write a new
1838 * value after the initvals have been applied, with an offset
1839 * based on measured time difference
1840 */
1841 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1842 tsf += 1500;
1843 ath9k_hw_settsf64(ah, tsf);
1844 }
1845
0ced0e17
JM		 1846 /* Setup MFP options for CCMP */
1847 if (AR_SREV_9280_20_OR_LATER(ah)) {
1848 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1849 * frames when constructing CCMP AAD. */
1850 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1851 0xc7ff);
1852 ah->sw_mgmt_crypto = false;
1853 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1854 /* Disable hardware crypto for management frames */
1855 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1856 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1857 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1858 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1859 ah->sw_mgmt_crypto = true;
1860 } else
1861 ah->sw_mgmt_crypto = true;
1862
f078f209
LR		 1863 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1864 ath9k_hw_set_delta_slope(ah, chan);
1865
8fe65368 1866 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1867 ah->eep_ops->set_board_values(ah, chan);
a7765828 1868
7d0d0df0
S		 1869 ENABLE_REGWRITE_BUFFER(ah);
1870
1510718d
LR		 1871 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1872 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1873 | macStaId1
1874 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1875 | (ah->config.
60b67f51 1876 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1877 | ah->sta_id1_defaults);
13b81559 1878 ath_hw_setbssidmask(common);
f078f209 1879 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1880 ath9k_hw_write_associd(ah);
f078f209 1881 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1882 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1883
7d0d0df0 1884 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1885
00e0003e
SM		 1886 ath9k_hw_set_operating_mode(ah, ah->opmode);
1887
8fe65368 1888 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1889 if (r)
1890 return r;
f078f209 1891
dfdac8ac
FF		 1892 ath9k_hw_set_clockrate(ah);
1893
7d0d0df0
S		 1894 ENABLE_REGWRITE_BUFFER(ah);
1895
f078f209
LR		 1896 for (i = 0; i < AR_NUM_DCU; i++)
1897 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1898
7d0d0df0 1899 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1900
2660b81a 1901 ah->intr_txqs = 0;
f4c607dc 1902 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
f078f209
LR		 1903 ath9k_hw_resettxqueue(ah, i);
1904
2660b81a 1905 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1906 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1907 ath9k_hw_init_qos(ah);
1908
2660b81a 1909 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1910 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1911
0005baf4 1912 ath9k_hw_init_global_settings(ah);
f078f209 1913
fe2b6afb
FF		 1914 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1915 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1916 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1917 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1918 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1919 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1920 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1921 }
1922
ca7a4deb 1923 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1924
1925 ath9k_hw_set_dma(ah);
1926
1927 REG_WRITE(ah, AR_OBS, 8);
1928
0ce024cb 1929 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1930 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1931 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1932 }
1933
7f62a136
VT		 1934 if (ah->config.tx_intr_mitigation) {
1935 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1936 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1937 }
1938
f078f209
LR		 1939 ath9k_hw_init_bb(ah, chan);
1940
77a5a664 1941 if (caldata) {
5f0c04ea 1942 caldata->done_txiqcal_once = false;
77a5a664 1943 caldata->done_txclcal_once = false;
324c74ad 1944 caldata->rtt_hist.num_readings = 0;
77a5a664 1945 }
ae8d2858 1946 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1947 return -EIO;
f078f209 1948
93348928
RM		 1949 ath9k_hw_loadnf(ah, chan);
1950 ath9k_hw_start_nfcal(ah, true);
1951
528e5d36
SM		 1952 if (mci && ar9003_mci_end_reset(ah, chan, caldata))
1953 return -EIO;
63d32967 1954
7d0d0df0 1955 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1956
8fe65368 1957 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1958 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1959
7d0d0df0 1960 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1961
d7e7d229
LR		 1962 /*
1963 * For big endian systems turn on swapping for descriptors
1964 */
f078f209
LR		 1965 if (AR_SREV_9100(ah)) {
1966 u32 mask;
1967 mask = REG_READ(ah, AR_CFG);
1968 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
d2182b69
JP		 1969 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1970 mask);
f078f209
LR		 1971 } else {
1972 mask =
1973 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1974 REG_WRITE(ah, AR_CFG, mask);
d2182b69
JP		 1975 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1976 REG_READ(ah, AR_CFG));
f078f209
LR		 1977 }
1978 } else {
cbba8cd1
S		 1979 if (common->bus_ops->ath_bus_type == ATH_USB) {
1980 /* Configure AR9271 target WLAN */
1981 if (AR_SREV_9271(ah))
1982 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1983 else
1984 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1985 }
f078f209 1986#ifdef __BIG_ENDIAN
4033bdad 1987 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
2be7bfe0
VT		 1988 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1989 else
d7e7d229 1990 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1991#endif
1992 }
1993
dbccdd1d 1994 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 1995 ath9k_hw_btcoex_enable(ah);
1996
528e5d36
SM		 1997 if (mci)
1998 ar9003_mci_check_bt(ah);
63d32967 1999
51ac8cbb 2000 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 2001 ar9003_hw_bb_watchdog_config(ah);
d8903a53 2002
51ac8cbb
RM		 2003 ar9003_hw_disable_phy_restart(ah);
2004 }
2005
691680b8
FF		 2006 ath9k_hw_apply_gpio_override(ah);
2007
ae8d2858 2008 return 0;
f078f209 2009}
7322fd19 2010EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2011
f1dc5600
S		 2012/******************************/
2013/* Power Management (Chipset) */
2014/******************************/
2015
42d5bc3f
LR		 2016/*
2017 * Notify Power Mgt is disabled in self-generated frames.
2018 * If requested, force chip to sleep.
2019 */
cbe61d8a 2020static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2021{
f1dc5600
S		 2022 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2023 if (setChip) {
423e38e8 2024 if (AR_SREV_9462(ah)) {
2577c6e8
SB		 2025 REG_WRITE(ah, AR_TIMER_MODE,
2026 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
2027 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
2028 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
2029 REG_WRITE(ah, AR_SLP32_INC,
2030 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
2031 /* xxx Required for WLAN only case ? */
2032 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2033 udelay(100);
2034 }
2035
42d5bc3f
LR		 2036 /*
2037 * Clear the RTC force wake bit to allow the
2038 * mac to go to sleep.
2039 */
2577c6e8
SB		 2040 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2041
423e38e8 2042 if (AR_SREV_9462(ah))
2577c6e8
SB		 2043 udelay(100);
2044
42d5bc3f 2045 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 2046 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2047
42d5bc3f 2048 /* Shutdown chip. Active low */
c91ec465 2049 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2577c6e8
SB		 2050 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2051 udelay(2);
2052 }
f1dc5600 2053 }
9a658d2b
LR		 2054
2055 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2056 if (AR_SREV_9300_20_OR_LATER(ah))
2057 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2058}
2059
bbd79af5
LR		 2060/*
2061 * Notify Power Management is enabled in self-generating
2062 * frames. If request, set power mode of chip to
2063 * auto/normal. Duration in units of 128us (1/8 TU).
2064 */
cbe61d8a 2065static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2066{
2577c6e8
SB		 2067 u32 val;
2068
f1dc5600
S		 2069 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2070 if (setChip) {
2660b81a 2071 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2072
f1dc5600 2073 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 2074 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 2075 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2076 AR_RTC_FORCE_WAKE_ON_INT);
2077 } else {
2577c6e8
SB		 2078
2079 /* When chip goes into network sleep, it could be waken
2080 * up by MCI_INT interrupt caused by BT's HW messages
2081 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2082 * rate (~100us). This will cause chip to leave and
2083 * re-enter network sleep mode frequently, which in
2084 * consequence will have WLAN MCI HW to generate lots of
2085 * SYS_WAKING and SYS_SLEEPING messages which will make
2086 * BT CPU to busy to process.
2087 */
423e38e8 2088 if (AR_SREV_9462(ah)) {
2577c6e8
SB		 2089 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
2090 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
2091 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
2092 }
bbd79af5
LR		 2093 /*
2094 * Clear the RTC force wake bit to allow the
2095 * mac to go to sleep.
2096 */
f1dc5600
S		 2097 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2098 AR_RTC_FORCE_WAKE_EN);
2577c6e8 2099
423e38e8 2100 if (AR_SREV_9462(ah))
2577c6e8 2101 udelay(30);
f078f209 2102 }
f078f209 2103 }
9a658d2b
LR		 2104
2105 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2106 if (AR_SREV_9300_20_OR_LATER(ah))
2107 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2108}
2109
cbe61d8a 2110static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2111{
f1dc5600
S		 2112 u32 val;
2113 int i;
f078f209 2114
9a658d2b
LR		 2115 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2116 if (AR_SREV_9300_20_OR_LATER(ah)) {
2117 REG_WRITE(ah, AR_WA, ah->WARegVal);
2118 udelay(10);
2119 }
2120
f1dc5600
S		 2121 if (setChip) {
2122 if ((REG_READ(ah, AR_RTC_STATUS) &
2123 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
23677ce3 2124 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
f1dc5600
S		 2125 return false;
2126 }
e041228f
LR		 2127 if (!AR_SREV_9300_20_OR_LATER(ah))
2128 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 2129 }
2130 if (AR_SREV_9100(ah))
2131 REG_SET_BIT(ah, AR_RTC_RESET,
2132 AR_RTC_RESET_EN);
f078f209 2133
f1dc5600
S		 2134 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2135 AR_RTC_FORCE_WAKE_EN);
2136 udelay(50);
f078f209 2137
f1dc5600
S		 2138 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2139 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2140 if (val == AR_RTC_STATUS_ON)
2141 break;
2142 udelay(50);
2143 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2144 AR_RTC_FORCE_WAKE_EN);
f078f209 2145 }
f1dc5600 2146 if (i == 0) {
3800276a
JP		 2147 ath_err(ath9k_hw_common(ah),
2148 "Failed to wakeup in %uus\n",
2149 POWER_UP_TIME / 20);
f1dc5600 2150 return false;
f078f209 2151 }
f078f209
LR		 2152 }
2153
f1dc5600 2154 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2155
f1dc5600 2156 return true;
f078f209
LR		 2157}
2158
9ecdef4b 2159bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2160{
c46917bb 2161 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 2162 int status = true, setChip = true;
f1dc5600
S		 2163 static const char *modes[] = {
2164 "AWAKE",
2165 "FULL-SLEEP",
2166 "NETWORK SLEEP",
2167 "UNDEFINED"
2168 };
f1dc5600 2169
cbdec975
GJ		 2170 if (ah->power_mode == mode)
2171 return status;
2172
d2182b69 2173 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2174 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2175
2176 switch (mode) {
2177 case ATH9K_PM_AWAKE:
2178 status = ath9k_hw_set_power_awake(ah, setChip);
1010911e
MSS		 2179
2180 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2181 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2182
f1dc5600
S		 2183 break;
2184 case ATH9K_PM_FULL_SLEEP:
d1ca8b8e
SM		 2185 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2186 ar9003_mci_set_full_sleep(ah);
1010911e 2187
f1dc5600 2188 ath9k_set_power_sleep(ah, setChip);
2660b81a 2189 ah->chip_fullsleep = true;
f1dc5600
S		 2190 break;
2191 case ATH9K_PM_NETWORK_SLEEP:
1010911e
MSS		 2192
2193 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2194 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2195
f1dc5600
S		 2196 ath9k_set_power_network_sleep(ah, setChip);
2197 break;
f078f209 2198 default:
3800276a 2199 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2200 return false;
2201 }
2660b81a 2202 ah->power_mode = mode;
f1dc5600 2203
69f4aab1
LR		 2204 /*
2205 * XXX: If this warning never comes up after a while then
2206 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2207 * ath9k_hw_setpower() return type void.
2208 */
97dcec57
SM		 2209
2210 if (!(ah->ah_flags & AH_UNPLUGGED))
2211 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2212
f1dc5600 2213 return status;
f078f209 2214}
7322fd19 2215EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2216
f1dc5600
S		 2217/*******************/
2218/* Beacon Handling */
2219/*******************/
2220
cbe61d8a 2221void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2222{
f078f209
LR		 2223 int flags = 0;
2224
7d0d0df0
S		 2225 ENABLE_REGWRITE_BUFFER(ah);
2226
2660b81a 2227 switch (ah->opmode) {
d97809db 2228 case NL80211_IFTYPE_ADHOC:
9cb5412b 2229 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 2230 REG_SET_BIT(ah, AR_TXCFG,
2231 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
dd347f2f
FF		 2232 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2233 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
f078f209 2234 flags |= AR_NDP_TIMER_EN;
d97809db 2235 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2236 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2237 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2238 TU_TO_USEC(ah->config.dma_beacon_response_time));
2239 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2240 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2241 flags |=
2242 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2243 break;
d97809db 2244 default:
d2182b69
JP		 2245 ath_dbg(ath9k_hw_common(ah), BEACON,
2246 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2247 return;
2248 break;
f078f209
LR		 2249 }
2250
dd347f2f
FF		 2251 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2252 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2253 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2254 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
f078f209 2255
7d0d0df0 2256 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2257
f078f209
LR		 2258 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2259}
7322fd19 2260EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2261
cbe61d8a 2262void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2263 const struct ath9k_beacon_state *bs)
f078f209
LR		 2264{
2265 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2266 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2267 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2268
7d0d0df0
S		 2269 ENABLE_REGWRITE_BUFFER(ah);
2270
f078f209
LR		 2271 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2272
2273 REG_WRITE(ah, AR_BEACON_PERIOD,
f29f5c08 2274 TU_TO_USEC(bs->bs_intval));
f078f209 2275 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
f29f5c08 2276 TU_TO_USEC(bs->bs_intval));
f078f209 2277
7d0d0df0 2278 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2279
f078f209
LR		 2280 REG_RMW_FIELD(ah, AR_RSSI_THR,
2281 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2282
f29f5c08 2283 beaconintval = bs->bs_intval;
f078f209
LR		 2284
2285 if (bs->bs_sleepduration > beaconintval)
2286 beaconintval = bs->bs_sleepduration;
2287
2288 dtimperiod = bs->bs_dtimperiod;
2289 if (bs->bs_sleepduration > dtimperiod)
2290 dtimperiod = bs->bs_sleepduration;
2291
2292 if (beaconintval == dtimperiod)
2293 nextTbtt = bs->bs_nextdtim;
2294 else
2295 nextTbtt = bs->bs_nexttbtt;
2296
d2182b69
JP		 2297 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2298 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2299 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2300 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2301
7d0d0df0
S		 2302 ENABLE_REGWRITE_BUFFER(ah);
2303
f1dc5600
S		 2304 REG_WRITE(ah, AR_NEXT_DTIM,
2305 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2306 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 2307
f1dc5600
S		 2308 REG_WRITE(ah, AR_SLEEP1,
2309 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2310 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2311
f1dc5600
S		 2312 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2313 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2314 else
2315 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2316
f1dc5600
S		 2317 REG_WRITE(ah, AR_SLEEP2,
2318 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2319
f1dc5600
S		 2320 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2321 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2322
7d0d0df0 2323 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2324
f1dc5600
S		 2325 REG_SET_BIT(ah, AR_TIMER_MODE,
2326 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2327 AR_DTIM_TIMER_EN);
f078f209 2328
4af9cf4f
S		 2329 /* TSF Out of Range Threshold */
2330 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2331}
7322fd19 2332EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2333
f1dc5600
S		 2334/*******************/
2335/* HW Capabilities */
2336/*******************/
2337
6054069a
FF		 2338static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2339{
2340 eeprom_chainmask &= chip_chainmask;
2341 if (eeprom_chainmask)
2342 return eeprom_chainmask;
2343 else
2344 return chip_chainmask;
2345}
2346
9a66af33
ZK		 2347/**
2348 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2349 * @ah: the atheros hardware data structure
2350 *
2351 * We enable DFS support upstream on chipsets which have passed a series
2352 * of tests. The testing requirements are going to be documented. Desired
2353 * test requirements are documented at:
2354 *
2355 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2356 *
2357 * Once a new chipset gets properly tested an individual commit can be used
2358 * to document the testing for DFS for that chipset.
2359 */
2360static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2361{
2362
2363 switch (ah->hw_version.macVersion) {
2364 /* AR9580 will likely be our first target to get testing on */
2365 case AR_SREV_VERSION_9580:
2366 default:
2367 return false;
2368 }
2369}
2370
a9a29ce6 2371int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2372{
2660b81a 2373 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2374 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2375 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2376 unsigned int chip_chainmask;
608b88cb 2377
0ff2b5c0 2378 u16 eeval;
47c80de6 2379 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2380
f74df6fb 2381 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2382 regulatory->current_rd = eeval;
f078f209 2383
2660b81a 2384 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2385 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2386 if (regulatory->current_rd == 0x64 ||
2387 regulatory->current_rd == 0x65)
2388 regulatory->current_rd += 5;
2389 else if (regulatory->current_rd == 0x41)
2390 regulatory->current_rd = 0x43;
d2182b69
JP		 2391 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2392 regulatory->current_rd);
f1dc5600 2393 }
f078f209 2394
f74df6fb 2395 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2396 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2397 ath_err(common,
2398 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2399 return -EINVAL;
2400 }
2401
d4659912
FF		 2402 if (eeval & AR5416_OPFLAGS_11A)
2403 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2404
d4659912
FF		 2405 if (eeval & AR5416_OPFLAGS_11G)
2406 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2407
6054069a
FF		 2408 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2409 chip_chainmask = 1;
ba5736a5
MSS		 2410 else if (AR_SREV_9462(ah))
2411 chip_chainmask = 3;
6054069a
FF		 2412 else if (!AR_SREV_9280_20_OR_LATER(ah))
2413 chip_chainmask = 7;
2414 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2415 chip_chainmask = 3;
2416 else
2417 chip_chainmask = 7;
2418
f74df6fb 2419 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2420 /*
2421 * For AR9271 we will temporarilly uses the rx chainmax as read from
2422 * the EEPROM.
2423 */
8147f5de 2424 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2425 !(eeval & AR5416_OPFLAGS_11A) &&
2426 !(AR_SREV_9271(ah)))
2427 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2428 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2429 else if (AR_SREV_9100(ah))
2430 pCap->rx_chainmask = 0x7;
8147f5de 2431 else
d7e7d229 2432 /* Use rx_chainmask from EEPROM. */
8147f5de 2433 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2434
6054069a
FF		 2435 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2436 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2437 ah->txchainmask = pCap->tx_chainmask;
2438 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2439
7a37081e 2440 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2441
02d2ebb2
FF		 2442 /* enable key search for every frame in an aggregate */
2443 if (AR_SREV_9300_20_OR_LATER(ah))
2444 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2445
ce2220d1
BR		 2446 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2447
0db156e9 2448 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2449 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2450 else
2451 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2452
5b5fa355
S		 2453 if (AR_SREV_9271(ah))
2454 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2455 else if (AR_DEVID_7010(ah))
2456 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2457 else if (AR_SREV_9300_20_OR_LATER(ah))
2458 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2459 else if (AR_SREV_9287_11_OR_LATER(ah))
2460 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2461 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2462 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2463 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2464 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2465 else
2466 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2467
1b2538b2 2468 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2469 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2470 else
f1dc5600 2471 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2472
e97275cb 2473#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2474 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2475 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2476 ah->rfkill_gpio =
2477 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2478 ah->rfkill_polarity =
2479 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2480
2481 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2482 }
f1dc5600 2483#endif
d5d1154f 2484 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2485 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2486 else
2487 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2488
e7594072 2489 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2490 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2491 else
2492 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2493
ceb26445 2494 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2495 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
0e707a94 2496 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
784ad503
VT		 2497 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2498
ceb26445
VT		 2499 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2500 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2501 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2502 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2503 pCap->txs_len = sizeof(struct ar9003_txs);
6f481010
LR		 2504 if (!ah->config.paprd_disable &&
2505 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
4935250a 2506 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 2507 } else {
2508 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2509 if (AR_SREV_9280_20(ah))
6b42e8d0 2510 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2511 }
1adf02ff 2512
6c84ce08
VT		 2513 if (AR_SREV_9300_20_OR_LATER(ah))
2514 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2515
6ee63f55
SB		 2516 if (AR_SREV_9300_20_OR_LATER(ah))
2517 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2518
a42acef0 2519 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2520 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2521
754dc536
VT		 2522 if (AR_SREV_9285(ah))
2523 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2524 ant_div_ctl1 =
2525 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2526 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2527 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2528 }
ea066d5a
MSS		 2529 if (AR_SREV_9300_20_OR_LATER(ah)) {
2530 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2531 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2532 }
2533
2534
431da56a 2535 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
21d2c63a
MSS		 2536 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2537 /*
2538 * enable the diversity-combining algorithm only when
2539 * both enable_lna_div and enable_fast_div are set
2540 * Table for Diversity
2541 * ant_div_alt_lnaconf bit 0-1
2542 * ant_div_main_lnaconf bit 2-3
2543 * ant_div_alt_gaintb bit 4
2544 * ant_div_main_gaintb bit 5
2545 * enable_ant_div_lnadiv bit 6
2546 * enable_ant_fast_div bit 7
2547 */
2548 if ((ant_div_ctl1 >> 0x6) == 0x3)
2549 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2550 }
754dc536 2551
8060e169
VT		 2552 if (AR_SREV_9485_10(ah)) {
2553 pCap->pcie_lcr_extsync_en = true;
2554 pCap->pcie_lcr_offset = 0x80;
2555 }
2556
9a66af33
ZK		 2557 if (ath9k_hw_dfs_tested(ah))
2558 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2559
47c80de6
VT		 2560 tx_chainmask = pCap->tx_chainmask;
2561 rx_chainmask = pCap->rx_chainmask;
2562 while (tx_chainmask || rx_chainmask) {
2563 if (tx_chainmask & BIT(0))
2564 pCap->max_txchains++;
2565 if (rx_chainmask & BIT(0))
2566 pCap->max_rxchains++;
2567
2568 tx_chainmask >>= 1;
2569 rx_chainmask >>= 1;
2570 }
2571
8ad74c4d
RM		 2572 if (AR_SREV_9300_20_OR_LATER(ah)) {
2573 ah->enabled_cals |= TX_IQ_CAL;
6fea593d 2574 if (AR_SREV_9485_OR_LATER(ah))
8ad74c4d
RM		 2575 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2576 }
3789d59c
MSS		 2577
2578 if (AR_SREV_9462(ah)) {
2579
2580 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2581 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2582
2583 if (AR_SREV_9462_20(ah))
2584 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2585
2586 }
2587
324c74ad 2588
a9a29ce6 2589 return 0;
f078f209
LR		 2590}
2591
f1dc5600
S		 2592/****************************/
2593/* GPIO / RFKILL / Antennae */
2594/****************************/
f078f209 2595
cbe61d8a 2596static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2597 u32 gpio, u32 type)
2598{
2599 int addr;
2600 u32 gpio_shift, tmp;
f078f209 2601
f1dc5600
S		 2602 if (gpio > 11)
2603 addr = AR_GPIO_OUTPUT_MUX3;
2604 else if (gpio > 5)
2605 addr = AR_GPIO_OUTPUT_MUX2;
2606 else
2607 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2608
f1dc5600 2609 gpio_shift = (gpio % 6) * 5;
f078f209 2610
f1dc5600
S		 2611 if (AR_SREV_9280_20_OR_LATER(ah)
2612 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2613 REG_RMW(ah, addr, (type << gpio_shift),
2614 (0x1f << gpio_shift));
f078f209 2615 } else {
f1dc5600
S		 2616 tmp = REG_READ(ah, addr);
2617 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2618 tmp &= ~(0x1f << gpio_shift);
2619 tmp |= (type << gpio_shift);
2620 REG_WRITE(ah, addr, tmp);
f078f209 2621 }
f078f209
LR		 2622}
2623
cbe61d8a 2624void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2625{
f1dc5600 2626 u32 gpio_shift;
f078f209 2627
9680e8a3 2628 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2629
88c1f4f6
S		 2630 if (AR_DEVID_7010(ah)) {
2631 gpio_shift = gpio;
2632 REG_RMW(ah, AR7010_GPIO_OE,
2633 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2634 (AR7010_GPIO_OE_MASK << gpio_shift));
2635 return;
2636 }
f078f209 2637
88c1f4f6 2638 gpio_shift = gpio << 1;
f1dc5600
S		 2639 REG_RMW(ah,
2640 AR_GPIO_OE_OUT,
2641 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2642 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2643}
7322fd19 2644EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2645
cbe61d8a 2646u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2647{
cb33c412
SB		 2648#define MS_REG_READ(x, y) \
2649 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2650
2660b81a 2651 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2652 return 0xffffffff;
f078f209 2653
88c1f4f6
S		 2654 if (AR_DEVID_7010(ah)) {
2655 u32 val;
2656 val = REG_READ(ah, AR7010_GPIO_IN);
2657 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2658 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2659 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2660 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2661 else if (AR_SREV_9271(ah))
5b5fa355 2662 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2663 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2664 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2665 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2666 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2667 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2668 return MS_REG_READ(AR928X, gpio) != 0;
2669 else
2670 return MS_REG_READ(AR, gpio) != 0;
f078f209 2671}
7322fd19 2672EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2673
cbe61d8a 2674void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2675 u32 ah_signal_type)
f078f209 2676{
f1dc5600 2677 u32 gpio_shift;
f078f209 2678
88c1f4f6
S		 2679 if (AR_DEVID_7010(ah)) {
2680 gpio_shift = gpio;
2681 REG_RMW(ah, AR7010_GPIO_OE,
2682 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2683 (AR7010_GPIO_OE_MASK << gpio_shift));
2684 return;
2685 }
f078f209 2686
88c1f4f6 2687 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2688 gpio_shift = 2 * gpio;
f1dc5600
S		 2689 REG_RMW(ah,
2690 AR_GPIO_OE_OUT,
2691 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2692 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2693}
7322fd19 2694EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2695
cbe61d8a 2696void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2697{
88c1f4f6
S		 2698 if (AR_DEVID_7010(ah)) {
2699 val = val ? 0 : 1;
2700 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2701 AR_GPIO_BIT(gpio));
2702 return;
2703 }
2704
5b5fa355
S		 2705 if (AR_SREV_9271(ah))
2706 val = ~val;
2707
f1dc5600
S		 2708 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2709 AR_GPIO_BIT(gpio));
f078f209 2710}
7322fd19 2711EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2712
cbe61d8a 2713void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2714{
f1dc5600 2715 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2716}
7322fd19 2717EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2718
f1dc5600
S		 2719/*********************/
2720/* General Operation */
2721/*********************/
2722
cbe61d8a 2723u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2724{
f1dc5600
S		 2725 u32 bits = REG_READ(ah, AR_RX_FILTER);
2726 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2727
f1dc5600
S		 2728 if (phybits & AR_PHY_ERR_RADAR)
2729 bits |= ATH9K_RX_FILTER_PHYRADAR;
2730 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2731 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2732
f1dc5600 2733 return bits;
f078f209 2734}
7322fd19 2735EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2736
cbe61d8a 2737void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2738{
f1dc5600 2739 u32 phybits;
f078f209 2740
7d0d0df0
S		 2741 ENABLE_REGWRITE_BUFFER(ah);
2742
423e38e8 2743 if (AR_SREV_9462(ah))
2577c6e8
SB		 2744 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2745
7ea310be
S		 2746 REG_WRITE(ah, AR_RX_FILTER, bits);
2747
f1dc5600
S		 2748 phybits = 0;
2749 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2750 phybits |= AR_PHY_ERR_RADAR;
2751 if (bits & ATH9K_RX_FILTER_PHYERR)
2752 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2753 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2754
f1dc5600 2755 if (phybits)
ca7a4deb 2756 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2757 else
ca7a4deb 2758 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2759
2760 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2761}
7322fd19 2762EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2763
cbe61d8a 2764bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2765{
63a75b91
SB		 2766 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2767 return false;
2768
2769 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2770 ah->htc_reset_init = true;
63a75b91 2771 return true;
f1dc5600 2772}
7322fd19 2773EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2774
cbe61d8a 2775bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2776{
9ecdef4b 2777 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2778 return false;
f078f209 2779
63a75b91
SB		 2780 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2781 return false;
2782
2783 ath9k_hw_init_pll(ah, NULL);
2784 return true;
f078f209 2785}
7322fd19 2786EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2787
ca2c68cc
FF		 2788static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2789{
2790 enum eeprom_param gain_param;
2791
2792 if (IS_CHAN_2GHZ(chan))
2793 gain_param = EEP_ANTENNA_GAIN_2G;
2794 else
2795 gain_param = EEP_ANTENNA_GAIN_5G;
2796
2797 return ah->eep_ops->get_eeprom(ah, gain_param);
2798}
2799
64ea57d0
GJ		 2800void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2801 bool test)
ca2c68cc
FF		 2802{
2803 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2804 struct ieee80211_channel *channel;
2805 int chan_pwr, new_pwr, max_gain;
2806 int ant_gain, ant_reduction = 0;
2807
2808 if (!chan)
2809 return;
2810
2811 channel = chan->chan;
2812 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2813 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2814 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2815
2816 ant_gain = get_antenna_gain(ah, chan);
2817 if (ant_gain > max_gain)
2818 ant_reduction = ant_gain - max_gain;
2819
2820 ah->eep_ops->set_txpower(ah, chan,
2821 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2822 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2823}
2824
de40f316 2825void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2826{
ca2c68cc 2827 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2828 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2829 struct ieee80211_channel *channel = chan->chan;
9c204b46 2830
48ef5c42 2831 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2832 if (test)
ca2c68cc 2833 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2834
64ea57d0 2835 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2836
ca2c68cc
FF		 2837 if (test)
2838 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2839}
7322fd19 2840EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2841
cbe61d8a 2842void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2843{
2660b81a 2844 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2845}
7322fd19 2846EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2847
cbe61d8a 2848void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2849{
f1dc5600
S		 2850 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2851 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2852}
7322fd19 2853EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2854
f2b2143e 2855void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2856{
1510718d
LR		 2857 struct ath_common *common = ath9k_hw_common(ah);
2858
2859 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2860 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2861 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2862}
7322fd19 2863EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2864
1c0fc65e
BP		 2865#define ATH9K_MAX_TSF_READ 10
2866
cbe61d8a 2867u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2868{
1c0fc65e
BP		 2869 u32 tsf_lower, tsf_upper1, tsf_upper2;
2870 int i;
2871
2872 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2873 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2874 tsf_lower = REG_READ(ah, AR_TSF_L32);
2875 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2876 if (tsf_upper2 == tsf_upper1)
2877 break;
2878 tsf_upper1 = tsf_upper2;
2879 }
f078f209 2880
1c0fc65e 2881 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2882
1c0fc65e 2883 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2884}
7322fd19 2885EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2886
cbe61d8a 2887void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2888{
27abe060 2889 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2890 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2891}
7322fd19 2892EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2893
cbe61d8a 2894void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2895{
f9b604f6
GJ		 2896 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2897 AH_TSF_WRITE_TIMEOUT))
d2182b69 2898 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2899 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2900
f1dc5600
S		 2901 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2902}
7322fd19 2903EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2904
54e4cec6 2905void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2906{
f1dc5600 2907 if (setting)
2660b81a 2908 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2909 else
2660b81a 2910 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2911}
7322fd19 2912EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2913
25c56eec 2914void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2915{
25c56eec 2916 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2917 u32 macmode;
2918
25c56eec 2919 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2920 macmode = AR_2040_JOINED_RX_CLEAR;
2921 else
2922 macmode = 0;
f078f209 2923
f1dc5600 2924 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2925}
ff155a45
VT		 2926
2927/* HW Generic timers configuration */
2928
2929static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2930{
2931 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2932 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2933 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2934 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2935 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2936 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2937 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2938 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2939 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2940 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2941 AR_NDP2_TIMER_MODE, 0x0002},
2942 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2943 AR_NDP2_TIMER_MODE, 0x0004},
2944 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2945 AR_NDP2_TIMER_MODE, 0x0008},
2946 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2947 AR_NDP2_TIMER_MODE, 0x0010},
2948 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2949 AR_NDP2_TIMER_MODE, 0x0020},
2950 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2951 AR_NDP2_TIMER_MODE, 0x0040},
2952 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2953 AR_NDP2_TIMER_MODE, 0x0080}
2954};
2955
2956/* HW generic timer primitives */
2957
2958/* compute and clear index of rightmost 1 */
2959static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2960{
2961 u32 b;
2962
2963 b = *mask;
2964 b &= (0-b);
2965 *mask &= ~b;
2966 b *= debruijn32;
2967 b >>= 27;
2968
2969 return timer_table->gen_timer_index[b];
2970}
2971
dd347f2f 2972u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2973{
2974 return REG_READ(ah, AR_TSF_L32);
2975}
dd347f2f 2976EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2977
2978struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2979 void (*trigger)(void *),
2980 void (*overflow)(void *),
2981 void *arg,
2982 u8 timer_index)
2983{
2984 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2985 struct ath_gen_timer *timer;
2986
2987 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2988
2989 if (timer == NULL) {
3800276a
JP		 2990 ath_err(ath9k_hw_common(ah),
2991 "Failed to allocate memory for hw timer[%d]\n",
2992 timer_index);
ff155a45
VT		 2993 return NULL;
2994 }
2995
2996 /* allocate a hardware generic timer slot */
2997 timer_table->timers[timer_index] = timer;
2998 timer->index = timer_index;
2999 timer->trigger = trigger;
3000 timer->overflow = overflow;
3001 timer->arg = arg;
3002
3003 return timer;
3004}
7322fd19 3005EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3006
cd9bf689
LR		 3007void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3008 struct ath_gen_timer *timer,
788f6875 3009 u32 trig_timeout,
cd9bf689 3010 u32 timer_period)
ff155a45
VT		 3011{
3012 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
788f6875 3013 u32 tsf, timer_next;
ff155a45
VT		 3014
3015 BUG_ON(!timer_period);
3016
3017 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3018
3019 tsf = ath9k_hw_gettsf32(ah);
3020
788f6875
VT		 3021 timer_next = tsf + trig_timeout;
3022
d2182b69 3023 ath_dbg(ath9k_hw_common(ah), HWTIMER,
226afe68
JP		 3024 "current tsf %x period %x timer_next %x\n",
3025 tsf, timer_period, timer_next);
ff155a45 3026
ff155a45
VT		 3027 /*
3028 * Program generic timer registers
3029 */
3030 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3031 timer_next);
3032 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3033 timer_period);
3034 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3035 gen_tmr_configuration[timer->index].mode_mask);
3036
423e38e8 3037 if (AR_SREV_9462(ah)) {
2577c6e8 3038 /*
423e38e8 3039 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3040 * to use. But we still follow the old rule, 0 - 7 use tsf and
3041 * 8 - 15 use tsf2.
3042 */
3043 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3044 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3045 (1 << timer->index));
3046 else
3047 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3048 (1 << timer->index));
3049 }
3050
ff155a45
VT		 3051 /* Enable both trigger and thresh interrupt masks */
3052 REG_SET_BIT(ah, AR_IMR_S5,
3053 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3054 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 3055}
7322fd19 3056EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3057
cd9bf689 3058void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3059{
3060 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3061
3062 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3063 (timer->index >= ATH_MAX_GEN_TIMER)) {
3064 return;
3065 }
3066
3067 /* Clear generic timer enable bits. */
3068 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3069 gen_tmr_configuration[timer->index].mode_mask);
3070
3071 /* Disable both trigger and thresh interrupt masks */
3072 REG_CLR_BIT(ah, AR_IMR_S5,
3073 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3074 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3075
3076 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3077}
7322fd19 3078EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3079
3080void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3081{
3082 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3083
3084 /* free the hardware generic timer slot */
3085 timer_table->timers[timer->index] = NULL;
3086 kfree(timer);
3087}
7322fd19 3088EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3089
3090/*
3091 * Generic Timer Interrupts handling
3092 */
3093void ath_gen_timer_isr(struct ath_hw *ah)
3094{
3095 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3096 struct ath_gen_timer *timer;
c46917bb 3097 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3098 u32 trigger_mask, thresh_mask, index;
3099
3100 /* get hardware generic timer interrupt status */
3101 trigger_mask = ah->intr_gen_timer_trigger;
3102 thresh_mask = ah->intr_gen_timer_thresh;
3103 trigger_mask &= timer_table->timer_mask.val;
3104 thresh_mask &= timer_table->timer_mask.val;
3105
3106 trigger_mask &= ~thresh_mask;
3107
3108 while (thresh_mask) {
3109 index = rightmost_index(timer_table, &thresh_mask);
3110 timer = timer_table->timers[index];
3111 BUG_ON(!timer);
d2182b69
JP		 3112 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3113 index);
ff155a45
VT		 3114 timer->overflow(timer->arg);
3115 }
3116
3117 while (trigger_mask) {
3118 index = rightmost_index(timer_table, &trigger_mask);
3119 timer = timer_table->timers[index];
3120 BUG_ON(!timer);
d2182b69 3121 ath_dbg(common, HWTIMER,
226afe68 3122 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3123 timer->trigger(timer->arg);
3124 }
3125}
7322fd19 3126EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3127
05020d23
S		 3128/********/
3129/* HTC */
3130/********/
3131
2da4f01a
LR		 3132static struct {
3133 u32 version;
3134 const char * name;
3135} ath_mac_bb_names[] = {
3136 /* Devices with external radios */
3137 { AR_SREV_VERSION_5416_PCI, "5416" },
3138 { AR_SREV_VERSION_5416_PCIE, "5418" },
3139 { AR_SREV_VERSION_9100, "9100" },
3140 { AR_SREV_VERSION_9160, "9160" },
3141 /* Single-chip solutions */
3142 { AR_SREV_VERSION_9280, "9280" },
3143 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3144 { AR_SREV_VERSION_9287, "9287" },
3145 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3146 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3147 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3148 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3149 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3150 { AR_SREV_VERSION_9462, "9462" },
2da4f01a
LR		 3151};
3152
3153/* For devices with external radios */
3154static struct {
3155 u16 version;
3156 const char * name;
3157} ath_rf_names[] = {
3158 { 0, "5133" },
3159 { AR_RAD5133_SREV_MAJOR, "5133" },
3160 { AR_RAD5122_SREV_MAJOR, "5122" },
3161 { AR_RAD2133_SREV_MAJOR, "2133" },
3162 { AR_RAD2122_SREV_MAJOR, "2122" }
3163};
3164
3165/*
3166 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3167 */
f934c4d9 3168static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3169{
3170 int i;
3171
3172 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3173 if (ath_mac_bb_names[i].version == mac_bb_version) {
3174 return ath_mac_bb_names[i].name;
3175 }
3176 }
3177
3178 return "????";
3179}
2da4f01a
LR		 3180
3181/*
3182 * Return the RF name. "????" is returned if the RF is unknown.
3183 * Used for devices with external radios.
3184 */
f934c4d9 3185static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3186{
3187 int i;
3188
3189 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3190 if (ath_rf_names[i].version == rf_version) {
3191 return ath_rf_names[i].name;
3192 }
3193 }
3194
3195 return "????";
3196}
f934c4d9
LR		 3197
3198void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3199{
3200 int used;
3201
3202 /* chipsets >= AR9280 are single-chip */
7a37081e 3203 if (AR_SREV_9280_20_OR_LATER(ah)) {
f934c4d9
LR		 3204 used = snprintf(hw_name, len,
3205 "Atheros AR%s Rev:%x",
3206 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3207 ah->hw_version.macRev);
3208 }
3209 else {
3210 used = snprintf(hw_name, len,
3211 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3212 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3213 ah->hw_version.macRev,
3214 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3215 AR_RADIO_SREV_MAJOR)),
3216 ah->hw_version.phyRev);
3217 }
3218
3219 hw_name[used] = '\0';
3220}
3221EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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