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ath9k_hw: Configure Tx interrupt mitigation timer
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
af03abec 20#include "hw.h"
d70357d5 21#include "hw-ops.h"
cfe8cba9 22#include "rc.h"
f078f209 23
4febf7b8
LR		 24#define ATH9K_CLOCK_RATE_CCK 22
25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 27
cbe61d8a 28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 29
7322fd19
LR		 30MODULE_AUTHOR("Atheros Communications");
31MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
32MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
33MODULE_LICENSE("Dual BSD/GPL");
34
35static int __init ath9k_init(void)
36{
37 return 0;
38}
39module_init(ath9k_init);
40
41static void __exit ath9k_exit(void)
42{
43 return;
44}
45module_exit(ath9k_exit);
46
d70357d5
LR		 47/* Private hardware callbacks */
48
49static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
50{
51 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52}
53
54static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
55{
56 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57}
58
59static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
60{
61 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
62
63 return priv_ops->macversion_supported(ah->hw_version.macVersion);
64}
65
64773964
LR		 66static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
67 struct ath9k_channel *chan)
68{
69 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
70}
71
991312d8
LR		 72static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
73{
74 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
78}
79
f1dc5600
S		 80/********************/
81/* Helper Functions */
82/********************/
f078f209 83
cbe61d8a 84static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 85{
b002a4a9 86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 87
2660b81a 88 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 89 return usecs *ATH9K_CLOCK_RATE_CCK;
90 if (conf->channel->band == IEEE80211_BAND_2GHZ)
91 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
92 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 93}
94
cbe61d8a 95static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 96{
b002a4a9 97 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 98
4febf7b8 99 if (conf_is_ht40(conf))
f1dc5600
S		 100 return ath9k_hw_mac_clks(ah, usecs) * 2;
101 else
102 return ath9k_hw_mac_clks(ah, usecs);
103}
f078f209 104
0caa7b14 105bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 106{
107 int i;
108
0caa7b14
S		 109 BUG_ON(timeout < AH_TIME_QUANTUM);
110
111 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 112 if ((REG_READ(ah, reg) & mask) == val)
113 return true;
114
115 udelay(AH_TIME_QUANTUM);
116 }
04bd4638 117
c46917bb
LR		 118 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
119 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
120 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 121
f1dc5600 122 return false;
f078f209 123}
7322fd19 124EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 125
126u32 ath9k_hw_reverse_bits(u32 val, u32 n)
127{
128 u32 retval;
129 int i;
130
131 for (i = 0, retval = 0; i < n; i++) {
132 retval = (retval << 1) | (val & 1);
133 val >>= 1;
134 }
135 return retval;
136}
137
cbe61d8a 138bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 139 u16 flags, u16 *low,
140 u16 *high)
f078f209 141{
2660b81a 142 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 143
f1dc5600
S		 144 if (flags & CHANNEL_5GHZ) {
145 *low = pCap->low_5ghz_chan;
146 *high = pCap->high_5ghz_chan;
147 return true;
f078f209 148 }
f1dc5600
S		 149 if ((flags & CHANNEL_2GHZ)) {
150 *low = pCap->low_2ghz_chan;
151 *high = pCap->high_2ghz_chan;
152 return true;
153 }
154 return false;
f078f209
LR		 155}
156
cbe61d8a 157u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 158 u8 phy, int kbps,
f1dc5600
S		 159 u32 frameLen, u16 rateix,
160 bool shortPreamble)
f078f209 161{
f1dc5600 162 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 163
f1dc5600
S		 164 if (kbps == 0)
165 return 0;
f078f209 166
545750d3 167 switch (phy) {
46d14a58 168 case WLAN_RC_PHY_CCK:
f1dc5600 169 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 170 if (shortPreamble)
f1dc5600
S		 171 phyTime >>= 1;
172 numBits = frameLen << 3;
173 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
174 break;
46d14a58 175 case WLAN_RC_PHY_OFDM:
2660b81a 176 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 177 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
178 numBits = OFDM_PLCP_BITS + (frameLen << 3);
179 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
180 txTime = OFDM_SIFS_TIME_QUARTER
181 + OFDM_PREAMBLE_TIME_QUARTER
182 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 183 } else if (ah->curchan &&
184 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 185 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
186 numBits = OFDM_PLCP_BITS + (frameLen << 3);
187 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
188 txTime = OFDM_SIFS_TIME_HALF +
189 OFDM_PREAMBLE_TIME_HALF
190 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
191 } else {
192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
193 numBits = OFDM_PLCP_BITS + (frameLen << 3);
194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
195 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
196 + (numSymbols * OFDM_SYMBOL_TIME);
197 }
198 break;
199 default:
c46917bb 200 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 201 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 202 txTime = 0;
203 break;
204 }
f078f209 205
f1dc5600
S		 206 return txTime;
207}
7322fd19 208EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 209
cbe61d8a 210void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 211 struct ath9k_channel *chan,
212 struct chan_centers *centers)
f078f209 213{
f1dc5600 214 int8_t extoff;
f078f209 215
f1dc5600
S		 216 if (!IS_CHAN_HT40(chan)) {
217 centers->ctl_center = centers->ext_center =
218 centers->synth_center = chan->channel;
219 return;
f078f209 220 }
f078f209 221
f1dc5600
S		 222 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
223 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
224 centers->synth_center =
225 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
226 extoff = 1;
227 } else {
228 centers->synth_center =
229 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
230 extoff = -1;
231 }
f078f209 232
f1dc5600
S		 233 centers->ctl_center =
234 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 235 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 236 centers->ext_center =
6420014c 237 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 238}
239
f1dc5600
S		 240/******************/
241/* Chip Revisions */
242/******************/
243
cbe61d8a 244static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 245{
f1dc5600 246 u32 val;
f078f209 247
f1dc5600 248 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 249
f1dc5600
S		 250 if (val == 0xFF) {
251 val = REG_READ(ah, AR_SREV);
d535a42a
S		 252 ah->hw_version.macVersion =
253 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
254 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 255 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 256 } else {
257 if (!AR_SREV_9100(ah))
d535a42a 258 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 259
d535a42a 260 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 261
d535a42a 262 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 263 ah->is_pciexpress = true;
f1dc5600 264 }
f078f209
LR		 265}
266
f1dc5600
S		 267/************************************/
268/* HW Attach, Detach, Init Routines */
269/************************************/
270
cbe61d8a 271static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 272{
feed029c 273 if (AR_SREV_9100(ah))
f1dc5600 274 return;
f078f209 275
f1dc5600
S		 276 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 285
f1dc5600 286 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 287}
288
1f3f0618 289/* This should work for all families including legacy */
cbe61d8a 290static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 291{
c46917bb 292 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 293 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600
S		 294 u32 regHold[2];
295 u32 patternData[4] = { 0x55555555,
296 0xaaaaaaaa,
297 0x66666666,
298 0x99999999 };
1f3f0618 299 int i, j, loop_max;
f078f209 300
1f3f0618
SB		 301 if (!AR_SREV_9300_20_OR_LATER(ah)) {
302 loop_max = 2;
303 regAddr[1] = AR_PHY_BASE + (8 << 2);
304 } else
305 loop_max = 1;
306
307 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 308 u32 addr = regAddr[i];
309 u32 wrData, rdData;
f078f209 310
f1dc5600
S		 311 regHold[i] = REG_READ(ah, addr);
312 for (j = 0; j < 0x100; j++) {
313 wrData = (j << 16) | j;
314 REG_WRITE(ah, addr, wrData);
315 rdData = REG_READ(ah, addr);
316 if (rdData != wrData) {
c46917bb
LR		 317 ath_print(common, ATH_DBG_FATAL,
318 "address test failed "
319 "addr: 0x%08x - wr:0x%08x != "
320 "rd:0x%08x\n",
321 addr, wrData, rdData);
f1dc5600
S		 322 return false;
323 }
324 }
325 for (j = 0; j < 4; j++) {
326 wrData = patternData[j];
327 REG_WRITE(ah, addr, wrData);
328 rdData = REG_READ(ah, addr);
329 if (wrData != rdData) {
c46917bb
LR		 330 ath_print(common, ATH_DBG_FATAL,
331 "address test failed "
332 "addr: 0x%08x - wr:0x%08x != "
333 "rd:0x%08x\n",
334 addr, wrData, rdData);
f1dc5600
S		 335 return false;
336 }
f078f209 337 }
f1dc5600 338 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 339 }
f1dc5600 340 udelay(100);
cbe61d8a 341
f078f209
LR		 342 return true;
343}
344
b8b0f377 345static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 346{
347 int i;
f078f209 348
2660b81a
S		 349 ah->config.dma_beacon_response_time = 2;
350 ah->config.sw_beacon_response_time = 10;
351 ah->config.additional_swba_backoff = 0;
352 ah->config.ack_6mb = 0x0;
353 ah->config.cwm_ignore_extcca = 0;
354 ah->config.pcie_powersave_enable = 0;
2660b81a 355 ah->config.pcie_clock_req = 0;
2660b81a
S		 356 ah->config.pcie_waen = 0;
357 ah->config.analog_shiftreg = 1;
2660b81a
S		 358 ah->config.ofdm_trig_low = 200;
359 ah->config.ofdm_trig_high = 500;
360 ah->config.cck_trig_high = 200;
361 ah->config.cck_trig_low = 100;
31a0bd3c
LR		 362
363 /*
364 * For now ANI is disabled for AR9003, it is still
365 * being tested.
366 */
367 if (!AR_SREV_9300_20_OR_LATER(ah))
368 ah->config.enable_ani = 1;
f078f209 369
f1dc5600 370 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 371 ah->config.spurchans[i][0] = AR_NO_SPUR;
372 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 373 }
374
5ffaf8a3
LR		 375 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
376 ah->config.ht_enable = 1;
377 else
378 ah->config.ht_enable = 0;
379
0ce024cb 380 ah->config.rx_intr_mitigation = true;
6158425b
LR		 381
382 /*
383 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
384 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
385 * This means we use it for all AR5416 devices, and the few
386 * minor PCI AR9280 devices out there.
387 *
388 * Serialization is required because these devices do not handle
389 * well the case of two concurrent reads/writes due to the latency
390 * involved. During one read/write another read/write can be issued
391 * on another CPU while the previous read/write may still be working
392 * on our hardware, if we hit this case the hardware poops in a loop.
393 * We prevent this by serializing reads and writes.
394 *
395 * This issue is not present on PCI-Express devices or pre-AR5416
396 * devices (legacy, 802.11abg).
397 */
398 if (num_possible_cpus() > 1)
2d6a5e95 399 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 400}
401
50aca25b 402static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 403{
608b88cb
LR		 404 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
405
406 regulatory->country_code = CTRY_DEFAULT;
407 regulatory->power_limit = MAX_RATE_POWER;
408 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
409
d535a42a 410 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 411 ah->hw_version.subvendorid = 0;
f078f209
LR		 412
413 ah->ah_flags = 0;
f078f209
LR		 414 if (!AR_SREV_9100(ah))
415 ah->ah_flags = AH_USE_EEPROM;
416
2660b81a 417 ah->atim_window = 0;
2660b81a
S		 418 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
419 ah->beacon_interval = 100;
420 ah->enable_32kHz_clock = DONT_USE_32KHZ;
421 ah->slottime = (u32) -1;
2660b81a 422 ah->globaltxtimeout = (u32) -1;
cbdec975 423 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 424}
425
cbe61d8a 426static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 427{
1510718d 428 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 429 u32 sum;
430 int i;
431 u16 eeval;
49101676 432 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 433
434 sum = 0;
435 for (i = 0; i < 3; i++) {
49101676 436 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 437 sum += eeval;
1510718d
LR		 438 common->macaddr[2 * i] = eeval >> 8;
439 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 440 }
d8baa939 441 if (sum == 0 || sum == 0xffff * 3)
f078f209 442 return -EADDRNOTAVAIL;
f078f209
LR		 443
444 return 0;
445}
446
f637cfd6 447static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 448{
f1dc5600 449 int ecode;
f078f209 450
527d485f
S		 451 if (!AR_SREV_9271(ah)) {
452 if (!ath9k_hw_chip_test(ah))
453 return -ENODEV;
454 }
f078f209 455
ebd5a14a
LR		 456 if (!AR_SREV_9300_20_OR_LATER(ah)) {
457 ecode = ar9002_hw_rf_claim(ah);
458 if (ecode != 0)
459 return ecode;
460 }
f078f209 461
f637cfd6 462 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 463 if (ecode != 0)
464 return ecode;
7d01b221 465
c46917bb
LR		 466 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
467 "Eeprom VER: %d, REV: %d\n",
468 ah->eep_ops->get_eeprom_ver(ah),
469 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 470
8fe65368
LR		 471 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
472 if (ecode) {
473 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
474 "Failed allocating banks for "
475 "external radio\n");
476 return ecode;
574d6b12 477 }
f078f209 478
f1dc5600
S		 479 if (!AR_SREV_9100(ah)) {
480 ath9k_hw_ani_setup(ah);
f637cfd6 481 ath9k_hw_ani_init(ah);
f078f209
LR		 482 }
483
f078f209
LR		 484 return 0;
485}
486
8525f280
LR		 487static void ath9k_hw_attach_ops(struct ath_hw *ah)
488{
489 if (AR_SREV_9300_20_OR_LATER(ah))
490 ar9003_hw_attach_ops(ah);
491 else
492 ar9002_hw_attach_ops(ah);
493}
494
d70357d5
LR		 495/* Called for all hardware families */
496static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 497{
c46917bb 498 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 499 int r = 0;
aa4058ae 500
bab1f62e
LR		 501 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
502 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
aa4058ae
LR		 503
504 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 505 ath_print(common, ATH_DBG_FATAL,
506 "Couldn't reset chip\n");
95fafca2 507 return -EIO;
aa4058ae
LR		 508 }
509
bab1f62e
LR		 510 ath9k_hw_init_defaults(ah);
511 ath9k_hw_init_config(ah);
512
8525f280 513 ath9k_hw_attach_ops(ah);
d70357d5 514
9ecdef4b 515 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 516 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 517 return -EIO;
aa4058ae
LR		 518 }
519
520 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
521 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
522 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
523 ah->config.serialize_regmode =
524 SER_REG_MODE_ON;
525 } else {
526 ah->config.serialize_regmode =
527 SER_REG_MODE_OFF;
528 }
529 }
530
c46917bb 531 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 532 ah->config.serialize_regmode);
533
f4709fdf
LR		 534 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
535 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
536 else
537 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
538
d70357d5 539 if (!ath9k_hw_macversion_supported(ah)) {
c46917bb
LR		 540 ath_print(common, ATH_DBG_FATAL,
541 "Mac Chip Rev 0x%02x.%x is not supported by "
542 "this driver\n", ah->hw_version.macVersion,
543 ah->hw_version.macRev);
95fafca2 544 return -EOPNOTSUPP;
aa4058ae
LR		 545 }
546
0df13da4 547 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
d7e7d229
LR		 548 ah->is_pciexpress = false;
549
aa4058ae 550 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 551 ath9k_hw_init_cal_settings(ah);
552
553 ah->ani_function = ATH9K_ANI_ALL;
31a0bd3c 554 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae
LR		 555 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
556
557 ath9k_hw_init_mode_regs(ah);
558
559 if (ah->is_pciexpress)
93b1b37f 560 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 561 else
562 ath9k_hw_disablepcie(ah);
563
d8f492b7
LR		 564 if (!AR_SREV_9300_20_OR_LATER(ah))
565 ar9002_hw_cck_chan14_spread(ah);
193cd458 566
f637cfd6 567 r = ath9k_hw_post_init(ah);
aa4058ae 568 if (r)
95fafca2 569 return r;
aa4058ae
LR		 570
571 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 572 r = ath9k_hw_fill_cap_info(ah);
573 if (r)
574 return r;
575
4f3acf81
LR		 576 r = ath9k_hw_init_macaddr(ah);
577 if (r) {
c46917bb
LR		 578 ath_print(common, ATH_DBG_FATAL,
579 "Failed to initialize MAC address\n");
95fafca2 580 return r;
f078f209
LR		 581 }
582
d7e7d229 583 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 584 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 585 else
2660b81a 586 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 587
641d9921
FF		 588 if (AR_SREV_9300_20_OR_LATER(ah))
589 ar9003_hw_set_nf_limits(ah);
590
f1dc5600 591 ath9k_init_nfcal_hist_buffer(ah);
f078f209 592
211f5859
LR		 593 common->state = ATH_HW_INITIALIZED;
594
4f3acf81 595 return 0;
f078f209
LR		 596}
597
d70357d5
LR		 598int ath9k_hw_init(struct ath_hw *ah)
599{
600 int ret;
601 struct ath_common *common = ath9k_hw_common(ah);
602
603 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
604 switch (ah->hw_version.devid) {
605 case AR5416_DEVID_PCI:
606 case AR5416_DEVID_PCIE:
607 case AR5416_AR9100_DEVID:
608 case AR9160_DEVID_PCI:
609 case AR9280_DEVID_PCI:
610 case AR9280_DEVID_PCIE:
611 case AR9285_DEVID_PCIE:
db3cc53a
SB		 612 case AR9287_DEVID_PCI:
613 case AR9287_DEVID_PCIE:
d70357d5 614 case AR2427_DEVID_PCIE:
db3cc53a 615 case AR9300_DEVID_PCIE:
d70357d5
LR		 616 break;
617 default:
618 if (common->bus_ops->ath_bus_type == ATH_USB)
619 break;
620 ath_print(common, ATH_DBG_FATAL,
621 "Hardware device ID 0x%04x not supported\n",
622 ah->hw_version.devid);
623 return -EOPNOTSUPP;
624 }
625
626 ret = __ath9k_hw_init(ah);
627 if (ret) {
628 ath_print(common, ATH_DBG_FATAL,
629 "Unable to initialize hardware; "
630 "initialization status: %d\n", ret);
631 return ret;
632 }
633
634 return 0;
635}
636EXPORT_SYMBOL(ath9k_hw_init);
637
cbe61d8a 638static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 639{
f1dc5600
S		 640 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
641 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 642
f1dc5600
S		 643 REG_WRITE(ah, AR_QOS_NO_ACK,
644 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
645 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
646 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
647
648 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
649 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
650 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
651 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
652 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 653}
654
cbe61d8a 655static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 656 struct ath9k_channel *chan)
f078f209 657{
64773964 658 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 659
d03a66c1 660 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 661
c75724d1
LR		 662 /* Switch the core clock for ar9271 to 117Mhz */
663 if (AR_SREV_9271(ah)) {
25e2ab17
S		 664 udelay(500);
665 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 666 }
667
f1dc5600
S		 668 udelay(RTC_PLL_SETTLE_DELAY);
669
670 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 671}
672
cbe61d8a 673static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 674 enum nl80211_iftype opmode)
f078f209 675{
152d530d 676 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 677 AR_IMR_TXURN |
678 AR_IMR_RXERR |
679 AR_IMR_RXORN |
680 AR_IMR_BCNMISC;
f078f209 681
66860240
VT		 682 if (AR_SREV_9300_20_OR_LATER(ah)) {
683 imr_reg |= AR_IMR_RXOK_HP;
684 if (ah->config.rx_intr_mitigation)
685 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
686 else
687 imr_reg |= AR_IMR_RXOK_LP;
f078f209 688
66860240
VT		 689 } else {
690 if (ah->config.rx_intr_mitigation)
691 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
692 else
693 imr_reg |= AR_IMR_RXOK;
694 }
695
696 if (ah->config.tx_intr_mitigation)
697 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
698 else
699 imr_reg |= AR_IMR_TXOK;
f078f209 700
d97809db 701 if (opmode == NL80211_IFTYPE_AP)
152d530d 702 imr_reg |= AR_IMR_MIB;
f078f209 703
152d530d 704 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 705 ah->imrs2_reg |= AR_IMR_S2_GTT;
706 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 707
f1dc5600
S		 708 if (!AR_SREV_9100(ah)) {
709 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
710 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
711 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
712 }
66860240
VT		 713
714 if (AR_SREV_9300_20_OR_LATER(ah)) {
715 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
716 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
717 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
718 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
719 }
f078f209
LR		 720}
721
0005baf4 722static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 723{
0005baf4
FF		 724 u32 val = ath9k_hw_mac_to_clks(ah, us);
725 val = min(val, (u32) 0xFFFF);
726 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 727}
728
0005baf4 729static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 730{
0005baf4
FF		 731 u32 val = ath9k_hw_mac_to_clks(ah, us);
732 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
733 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
734}
735
736static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
737{
738 u32 val = ath9k_hw_mac_to_clks(ah, us);
739 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
740 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 741}
f1dc5600 742
cbe61d8a 743static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 744{
f078f209 745 if (tu > 0xFFFF) {
c46917bb
LR		 746 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
747 "bad global tx timeout %u\n", tu);
2660b81a 748 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 749 return false;
750 } else {
751 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 752 ah->globaltxtimeout = tu;
f078f209
LR		 753 return true;
754 }
755}
756
0005baf4 757void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 758{
0005baf4
FF		 759 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
760 int acktimeout;
e239d859 761 int slottime;
0005baf4
FF		 762 int sifstime;
763
c46917bb
LR		 764 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
765 ah->misc_mode);
f078f209 766
2660b81a 767 if (ah->misc_mode != 0)
f1dc5600 768 REG_WRITE(ah, AR_PCU_MISC,
2660b81a 769 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
0005baf4
FF		 770
771 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
772 sifstime = 16;
773 else
774 sifstime = 10;
775
e239d859
FF		 776 /* As defined by IEEE 802.11-2007 17.3.8.6 */
777 slottime = ah->slottime + 3 * ah->coverage_class;
778 acktimeout = slottime + sifstime;
42c4568a
FF		 779
780 /*
781 * Workaround for early ACK timeouts, add an offset to match the
782 * initval's 64us ack timeout value.
783 * This was initially only meant to work around an issue with delayed
784 * BA frames in some implementations, but it has been found to fix ACK
785 * timeout issues in other cases as well.
786 */
787 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
788 acktimeout += 64 - sifstime - ah->slottime;
789
e239d859 790 ath9k_hw_setslottime(ah, slottime);
0005baf4
FF		 791 ath9k_hw_set_ack_timeout(ah, acktimeout);
792 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 793 if (ah->globaltxtimeout != (u32) -1)
794 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 795}
0005baf4 796EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 797
285f2dda 798void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 799{
211f5859
LR		 800 struct ath_common *common = ath9k_hw_common(ah);
801
736b3a27 802 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 803 goto free_hw;
804
f1dc5600 805 if (!AR_SREV_9100(ah))
e70c0cfd 806 ath9k_hw_ani_disable(ah);
f1dc5600 807
9ecdef4b 808 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 809
810free_hw:
8fe65368 811 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 812}
285f2dda 813EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 814
f1dc5600
S		 815/*******/
816/* INI */
817/*******/
818
8fe65368 819u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 820{
821 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
822
823 if (IS_CHAN_B(chan))
824 ctl |= CTL_11B;
825 else if (IS_CHAN_G(chan))
826 ctl |= CTL_11G;
827 else
828 ctl |= CTL_11A;
829
830 return ctl;
831}
832
f1dc5600
S		 833/****************************************/
834/* Reset and Channel Switching Routines */
835/****************************************/
836
cbe61d8a 837static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 838{
839 u32 regval;
840
d7e7d229
LR		 841 /*
842 * set AHB_MODE not to do cacheline prefetches
843 */
f1dc5600
S		 844 regval = REG_READ(ah, AR_AHB_MODE);
845 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
846
d7e7d229
LR		 847 /*
848 * let mac dma reads be in 128 byte chunks
849 */
f1dc5600
S		 850 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
851 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
852
d7e7d229
LR		 853 /*
854 * Restore TX Trigger Level to its pre-reset value.
855 * The initial value depends on whether aggregation is enabled, and is
856 * adjusted whenever underruns are detected.
857 */
2660b81a 858 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 859
d7e7d229
LR		 860 /*
861 * let mac dma writes be in 128 byte chunks
862 */
f1dc5600
S		 863 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
864 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
865
d7e7d229
LR		 866 /*
867 * Setup receive FIFO threshold to hold off TX activities
868 */
f1dc5600
S		 869 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
870
d7e7d229
LR		 871 /*
872 * reduce the number of usable entries in PCU TXBUF to avoid
873 * wrap around issues.
874 */
f1dc5600 875 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 876 /* For AR9285 the number of Fifos are reduced to half.
877 * So set the usable tx buf size also to half to
878 * avoid data/delimiter underruns
879 */
f1dc5600
S		 880 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
881 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 882 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 883 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
884 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
885 }
886}
887
cbe61d8a 888static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 889{
890 u32 val;
891
892 val = REG_READ(ah, AR_STA_ID1);
893 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
894 switch (opmode) {
d97809db 895 case NL80211_IFTYPE_AP:
f1dc5600
S		 896 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
897 | AR_STA_ID1_KSRCH_MODE);
898 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 899 break;
d97809db 900 case NL80211_IFTYPE_ADHOC:
9cb5412b 901 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 902 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
903 | AR_STA_ID1_KSRCH_MODE);
904 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 905 break;
d97809db
CM		 906 case NL80211_IFTYPE_STATION:
907 case NL80211_IFTYPE_MONITOR:
f1dc5600 908 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 909 break;
f1dc5600
S		 910 }
911}
912
8fe65368
LR		 913void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
914 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 915{
916 u32 coef_exp, coef_man;
917
918 for (coef_exp = 31; coef_exp > 0; coef_exp--)
919 if ((coef_scaled >> coef_exp) & 0x1)
920 break;
921
922 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
923
924 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
925
926 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
927 *coef_exponent = coef_exp - 16;
928}
929
cbe61d8a 930static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 931{
932 u32 rst_flags;
933 u32 tmpReg;
934
70768496
S		 935 if (AR_SREV_9100(ah)) {
936 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
937 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
938 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
939 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
940 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
941 }
942
f1dc5600
S		 943 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
944 AR_RTC_FORCE_WAKE_ON_INT);
945
946 if (AR_SREV_9100(ah)) {
947 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
948 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
949 } else {
950 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
951 if (tmpReg &
952 (AR_INTR_SYNC_LOCAL_TIMEOUT |
953 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 954 u32 val;
f1dc5600 955 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 956
957 val = AR_RC_HOSTIF;
958 if (!AR_SREV_9300_20_OR_LATER(ah))
959 val |= AR_RC_AHB;
960 REG_WRITE(ah, AR_RC, val);
961
962 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 963 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 964
965 rst_flags = AR_RTC_RC_MAC_WARM;
966 if (type == ATH9K_RESET_COLD)
967 rst_flags |= AR_RTC_RC_MAC_COLD;
968 }
969
d03a66c1 970 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 971 udelay(50);
972
d03a66c1 973 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 974 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 975 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
976 "RTC stuck in MAC reset\n");
f1dc5600
S		 977 return false;
978 }
979
980 if (!AR_SREV_9100(ah))
981 REG_WRITE(ah, AR_RC, 0);
982
f1dc5600
S		 983 if (AR_SREV_9100(ah))
984 udelay(50);
985
986 return true;
987}
988
cbe61d8a 989static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 990{
991 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
992 AR_RTC_FORCE_WAKE_ON_INT);
993
42d5bc3f 994 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 995 REG_WRITE(ah, AR_RC, AR_RC_AHB);
996
d03a66c1 997 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 998
84e2169b
SB		 999 if (!AR_SREV_9300_20_OR_LATER(ah))
1000 udelay(2);
1001
1002 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1003 REG_WRITE(ah, AR_RC, 0);
1004
d03a66c1 1005 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1006
1007 if (!ath9k_hw_wait(ah,
1008 AR_RTC_STATUS,
1009 AR_RTC_STATUS_M,
0caa7b14
S		 1010 AR_RTC_STATUS_ON,
1011 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1012 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1013 "RTC not waking up\n");
f1dc5600 1014 return false;
f078f209
LR		 1015 }
1016
f1dc5600
S		 1017 ath9k_hw_read_revisions(ah);
1018
1019 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1020}
1021
cbe61d8a 1022static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1023{
1024 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1025 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1026
1027 switch (type) {
1028 case ATH9K_RESET_POWER_ON:
1029 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1030 case ATH9K_RESET_WARM:
1031 case ATH9K_RESET_COLD:
1032 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1033 default:
1034 return false;
1035 }
f078f209
LR		 1036}
1037
cbe61d8a 1038static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1039 struct ath9k_channel *chan)
f078f209 1040{
42abfbee 1041 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1042 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1043 return false;
1044 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1045 return false;
f078f209 1046
9ecdef4b 1047 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1048 return false;
f078f209 1049
2660b81a 1050 ah->chip_fullsleep = false;
f1dc5600 1051 ath9k_hw_init_pll(ah, chan);
f1dc5600 1052 ath9k_hw_set_rfmode(ah, chan);
f078f209 1053
f1dc5600 1054 return true;
f078f209
LR		 1055}
1056
cbe61d8a 1057static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1058 struct ath9k_channel *chan)
f078f209 1059{
608b88cb 1060 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1061 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1062 struct ieee80211_channel *channel = chan->chan;
8fe65368 1063 u32 qnum;
0a3b7bac 1064 int r;
f078f209
LR		 1065
1066 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1067 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1068 ath_print(common, ATH_DBG_QUEUE,
1069 "Transmit frames pending on "
1070 "queue %d\n", qnum);
f078f209
LR		 1071 return false;
1072 }
1073 }
1074
8fe65368 1075 if (!ath9k_hw_rfbus_req(ah)) {
c46917bb
LR		 1076 ath_print(common, ATH_DBG_FATAL,
1077 "Could not kill baseband RX\n");
f078f209
LR		 1078 return false;
1079 }
1080
8fe65368 1081 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1082
8fe65368 1083 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1084 if (r) {
1085 ath_print(common, ATH_DBG_FATAL,
1086 "Failed to set channel\n");
1087 return false;
f078f209
LR		 1088 }
1089
8fbff4b8 1090 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1091 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1092 channel->max_antenna_gain * 2,
1093 channel->max_power * 2,
1094 min((u32) MAX_RATE_POWER,
608b88cb 1095 (u32) regulatory->power_limit));
f078f209 1096
8fe65368 1097 ath9k_hw_rfbus_done(ah);
f078f209 1098
f1dc5600
S		 1099 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1100 ath9k_hw_set_delta_slope(ah, chan);
1101
8fe65368 1102 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600
S		 1103
1104 if (!chan->oneTimeCalsDone)
1105 chan->oneTimeCalsDone = true;
1106
1107 return true;
1108}
1109
cbe61d8a 1110int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 1111 bool bChannelChange)
f078f209 1112{
1510718d 1113 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1114 u32 saveLedState;
2660b81a 1115 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1116 u32 saveDefAntenna;
1117 u32 macStaId1;
46fe782c 1118 u64 tsf = 0;
8fe65368 1119 int i, r;
f078f209 1120
43c27613
LR		 1121 ah->txchainmask = common->tx_chainmask;
1122 ah->rxchainmask = common->rx_chainmask;
f078f209 1123
9ecdef4b 1124 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1125 return -EIO;
f078f209 1126
9ebef799 1127 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1128 ath9k_hw_getnf(ah, curchan);
1129
1130 if (bChannelChange &&
2660b81a
S		 1131 (ah->chip_fullsleep != true) &&
1132 (ah->curchan != NULL) &&
1133 (chan->channel != ah->curchan->channel) &&
f078f209 1134 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1135 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
0a475cc6
VT		 1136 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1137 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
f078f209 1138
25c56eec 1139 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1140 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 1141 ath9k_hw_start_nfcal(ah);
ae8d2858 1142 return 0;
f078f209
LR		 1143 }
1144 }
1145
1146 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1147 if (saveDefAntenna == 0)
1148 saveDefAntenna = 1;
1149
1150 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1151
46fe782c
S		 1152 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1153 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1154 tsf = ath9k_hw_gettsf64(ah);
1155
f078f209
LR		 1156 saveLedState = REG_READ(ah, AR_CFG_LED) &
1157 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1158 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1159
1160 ath9k_hw_mark_phy_inactive(ah);
1161
05020d23 1162 /* Only required on the first reset */
d7e7d229
LR		 1163 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1164 REG_WRITE(ah,
1165 AR9271_RESET_POWER_DOWN_CONTROL,
1166 AR9271_RADIO_RF_RST);
1167 udelay(50);
1168 }
1169
f078f209 1170 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1171 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1172 return -EINVAL;
f078f209
LR		 1173 }
1174
05020d23 1175 /* Only required on the first reset */
d7e7d229
LR		 1176 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1177 ah->htc_reset_init = false;
1178 REG_WRITE(ah,
1179 AR9271_RESET_POWER_DOWN_CONTROL,
1180 AR9271_GATE_MAC_CTL);
1181 udelay(50);
1182 }
1183
46fe782c
S		 1184 /* Restore TSF */
1185 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1186 ath9k_hw_settsf64(ah, tsf);
1187
369391db
VT		 1188 if (AR_SREV_9280_10_OR_LATER(ah))
1189 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1190
25c56eec 1191 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1192 if (r)
1193 return r;
f078f209 1194
0ced0e17
JM		 1195 /* Setup MFP options for CCMP */
1196 if (AR_SREV_9280_20_OR_LATER(ah)) {
1197 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1198 * frames when constructing CCMP AAD. */
1199 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1200 0xc7ff);
1201 ah->sw_mgmt_crypto = false;
1202 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1203 /* Disable hardware crypto for management frames */
1204 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1205 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1206 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1207 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1208 ah->sw_mgmt_crypto = true;
1209 } else
1210 ah->sw_mgmt_crypto = true;
1211
f078f209
LR		 1212 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1213 ath9k_hw_set_delta_slope(ah, chan);
1214
8fe65368 1215 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1216 ah->eep_ops->set_board_values(ah, chan);
a7765828 1217
1510718d
LR		 1218 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1219 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1220 | macStaId1
1221 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1222 | (ah->config.
60b67f51 1223 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 1224 | ah->sta_id1_defaults);
1225 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 1226
13b81559 1227 ath_hw_setbssidmask(common);
f078f209
LR		 1228
1229 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1230
3453ad88 1231 ath9k_hw_write_associd(ah);
f078f209
LR		 1232
1233 REG_WRITE(ah, AR_ISR, ~0);
1234
1235 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1236
8fe65368 1237 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1238 if (r)
1239 return r;
f078f209
LR		 1240
1241 for (i = 0; i < AR_NUM_DCU; i++)
1242 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1243
2660b81a
S		 1244 ah->intr_txqs = 0;
1245 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 1246 ath9k_hw_resettxqueue(ah, i);
1247
2660b81a 1248 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 1249 ath9k_hw_init_qos(ah);
1250
2660b81a 1251 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 1252 ath9k_enable_rfkill(ah);
3b319aae 1253
0005baf4 1254 ath9k_hw_init_global_settings(ah);
f078f209 1255
326bebbc 1256 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 1257 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
1258 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
1259 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
1260 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
1261 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
1262 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
1263
1264 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
1265 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
1266
1267 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1268 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1269 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1270 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1271 }
326bebbc 1272 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 1273 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1274 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1275 }
1276
f078f209
LR		 1277 REG_WRITE(ah, AR_STA_ID1,
1278 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1279
1280 ath9k_hw_set_dma(ah);
1281
1282 REG_WRITE(ah, AR_OBS, 8);
1283
0ce024cb 1284 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1285 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1286 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1287 }
1288
7f62a136
VT		 1289 if (ah->config.tx_intr_mitigation) {
1290 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1291 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1292 }
1293
f078f209
LR		 1294 ath9k_hw_init_bb(ah, chan);
1295
ae8d2858 1296 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1297 return -EIO;
f078f209 1298
8fe65368 1299 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1300 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1301
d7e7d229
LR		 1302 /*
1303 * For big endian systems turn on swapping for descriptors
1304 */
f078f209
LR		 1305 if (AR_SREV_9100(ah)) {
1306 u32 mask;
1307 mask = REG_READ(ah, AR_CFG);
1308 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 1309 ath_print(common, ATH_DBG_RESET,
04bd4638 1310 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1311 } else {
1312 mask =
1313 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1314 REG_WRITE(ah, AR_CFG, mask);
c46917bb 1315 ath_print(common, ATH_DBG_RESET,
04bd4638 1316 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1317 }
1318 } else {
d7e7d229
LR		 1319 /* Configure AR9271 target WLAN */
1320 if (AR_SREV_9271(ah))
1321 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 1322#ifdef __BIG_ENDIAN
d7e7d229
LR		 1323 else
1324 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1325#endif
1326 }
1327
766ec4a9 1328 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1329 ath9k_hw_btcoex_enable(ah);
1330
ae8d2858 1331 return 0;
f078f209 1332}
7322fd19 1333EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1334
f1dc5600
S		 1335/************************/
1336/* Key Cache Management */
1337/************************/
f078f209 1338
cbe61d8a 1339bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 1340{
f1dc5600 1341 u32 keyType;
f078f209 1342
2660b81a 1343 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1344 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1345 "keychache entry %u out of range\n", entry);
f078f209
LR		 1346 return false;
1347 }
1348
f1dc5600 1349 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 1350
f1dc5600
S		 1351 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1352 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1353 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1354 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1355 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1356 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1357 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1358 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 1359
f1dc5600
S		 1360 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1361 u16 micentry = entry + 64;
f078f209 1362
f1dc5600
S		 1363 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1364 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1365 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1366 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 1367
f078f209
LR		 1368 }
1369
f078f209
LR		 1370 return true;
1371}
7322fd19 1372EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 1373
cbe61d8a 1374bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 1375{
f1dc5600 1376 u32 macHi, macLo;
f078f209 1377
2660b81a 1378 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1379 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1380 "keychache entry %u out of range\n", entry);
f1dc5600 1381 return false;
f078f209
LR		 1382 }
1383
f1dc5600
S		 1384 if (mac != NULL) {
1385 macHi = (mac[5] << 8) | mac[4];
1386 macLo = (mac[3] << 24) |
1387 (mac[2] << 16) |
1388 (mac[1] << 8) |
1389 mac[0];
1390 macLo >>= 1;
1391 macLo |= (macHi & 1) << 31;
1392 macHi >>= 1;
f078f209 1393 } else {
f1dc5600 1394 macLo = macHi = 0;
f078f209 1395 }
f1dc5600
S		 1396 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1397 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 1398
f1dc5600 1399 return true;
f078f209 1400}
7322fd19 1401EXPORT_SYMBOL(ath9k_hw_keysetmac);
f078f209 1402
cbe61d8a 1403bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 1404 const struct ath9k_keyval *k,
e0caf9ea 1405 const u8 *mac)
f078f209 1406{
2660b81a 1407 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1408 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 1409 u32 key0, key1, key2, key3, key4;
1410 u32 keyType;
f078f209 1411
f1dc5600 1412 if (entry >= pCap->keycache_size) {
c46917bb
LR		 1413 ath_print(common, ATH_DBG_FATAL,
1414 "keycache entry %u out of range\n", entry);
f1dc5600 1415 return false;
f078f209
LR		 1416 }
1417
f1dc5600
S		 1418 switch (k->kv_type) {
1419 case ATH9K_CIPHER_AES_OCB:
1420 keyType = AR_KEYTABLE_TYPE_AES;
1421 break;
1422 case ATH9K_CIPHER_AES_CCM:
1423 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 1424 ath_print(common, ATH_DBG_ANY,
1425 "AES-CCM not supported by mac rev 0x%x\n",
1426 ah->hw_version.macRev);
f1dc5600
S		 1427 return false;
1428 }
1429 keyType = AR_KEYTABLE_TYPE_CCM;
1430 break;
1431 case ATH9K_CIPHER_TKIP:
1432 keyType = AR_KEYTABLE_TYPE_TKIP;
1433 if (ATH9K_IS_MIC_ENABLED(ah)
1434 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 1435 ath_print(common, ATH_DBG_ANY,
1436 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 1437 return false;
1438 }
1439 break;
1440 case ATH9K_CIPHER_WEP:
e31a16d6 1441 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 1442 ath_print(common, ATH_DBG_ANY,
1443 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 1444 return false;
1445 }
e31a16d6 1446 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 1447 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 1448 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 1449 keyType = AR_KEYTABLE_TYPE_104;
1450 else
1451 keyType = AR_KEYTABLE_TYPE_128;
1452 break;
1453 case ATH9K_CIPHER_CLR:
1454 keyType = AR_KEYTABLE_TYPE_CLR;
1455 break;
1456 default:
c46917bb
LR		 1457 ath_print(common, ATH_DBG_FATAL,
1458 "cipher %u not supported\n", k->kv_type);
f1dc5600 1459 return false;
f078f209
LR		 1460 }
1461
e0caf9ea
JM		 1462 key0 = get_unaligned_le32(k->kv_val + 0);
1463 key1 = get_unaligned_le16(k->kv_val + 4);
1464 key2 = get_unaligned_le32(k->kv_val + 6);
1465 key3 = get_unaligned_le16(k->kv_val + 10);
1466 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 1467 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 1468 key4 &= 0xff;
f078f209 1469
672903b3
JM		 1470 /*
1471 * Note: Key cache registers access special memory area that requires
1472 * two 32-bit writes to actually update the values in the internal
1473 * memory. Consequently, the exact order and pairs used here must be
1474 * maintained.
1475 */
1476
f1dc5600
S		 1477 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1478 u16 micentry = entry + 64;
f078f209 1479
672903b3
JM		 1480 /*
1481 * Write inverted key[47:0] first to avoid Michael MIC errors
1482 * on frames that could be sent or received at the same time.
1483 * The correct key will be written in the end once everything
1484 * else is ready.
1485 */
f1dc5600
S		 1486 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1487 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 1488
1489 /* Write key[95:48] */
f1dc5600
S		 1490 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1491 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1492
1493 /* Write key[127:96] and key type */
f1dc5600
S		 1494 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1495 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 1496
1497 /* Write MAC address for the entry */
f1dc5600 1498 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 1499
2660b81a 1500 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 1501 /*
1502 * TKIP uses two key cache entries:
1503 * Michael MIC TX/RX keys in the same key cache entry
1504 * (idx = main index + 64):
1505 * key0 [31:0] = RX key [31:0]
1506 * key1 [15:0] = TX key [31:16]
1507 * key1 [31:16] = reserved
1508 * key2 [31:0] = RX key [63:32]
1509 * key3 [15:0] = TX key [15:0]
1510 * key3 [31:16] = reserved
1511 * key4 [31:0] = TX key [63:32]
1512 */
f1dc5600 1513 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 1514
f1dc5600
S		 1515 mic0 = get_unaligned_le32(k->kv_mic + 0);
1516 mic2 = get_unaligned_le32(k->kv_mic + 4);
1517 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1518 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1519 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 1520
1521 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 1522 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1523 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 1524
1525 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 1526 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1527 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 1528
1529 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1530 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1531 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1532 AR_KEYTABLE_TYPE_CLR);
f078f209 1533
f1dc5600 1534 } else {
672903b3
JM		 1535 /*
1536 * TKIP uses four key cache entries (two for group
1537 * keys):
1538 * Michael MIC TX/RX keys are in different key cache
1539 * entries (idx = main index + 64 for TX and
1540 * main index + 32 + 96 for RX):
1541 * key0 [31:0] = TX/RX MIC key [31:0]
1542 * key1 [31:0] = reserved
1543 * key2 [31:0] = TX/RX MIC key [63:32]
1544 * key3 [31:0] = reserved
1545 * key4 [31:0] = reserved
1546 *
1547 * Upper layer code will call this function separately
1548 * for TX and RX keys when these registers offsets are
1549 * used.
1550 */
f1dc5600 1551 u32 mic0, mic2;
f078f209 1552
f1dc5600
S		 1553 mic0 = get_unaligned_le32(k->kv_mic + 0);
1554 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 1555
1556 /* Write MIC key[31:0] */
f1dc5600
S		 1557 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1558 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 1559
1560 /* Write MIC key[63:32] */
f1dc5600
S		 1561 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1562 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 1563
1564 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1565 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1566 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1567 AR_KEYTABLE_TYPE_CLR);
1568 }
672903b3
JM		 1569
1570 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 1571 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1572 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 1573
1574 /*
1575 * Write the correct (un-inverted) key[47:0] last to enable
1576 * TKIP now that all other registers are set with correct
1577 * values.
1578 */
f1dc5600
S		 1579 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1580 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1581 } else {
672903b3 1582 /* Write key[47:0] */
f1dc5600
S		 1583 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1584 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 1585
1586 /* Write key[95:48] */
f1dc5600
S		 1587 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1588 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1589
1590 /* Write key[127:96] and key type */
f1dc5600
S		 1591 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1592 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 1593
672903b3 1594 /* Write MAC address for the entry */
f1dc5600
S		 1595 (void) ath9k_hw_keysetmac(ah, entry, mac);
1596 }
f078f209 1597
f078f209
LR		 1598 return true;
1599}
7322fd19 1600EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 1601
cbe61d8a 1602bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 1603{
2660b81a 1604 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 1605 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1606 if (val & AR_KEYTABLE_VALID)
1607 return true;
1608 }
1609 return false;
f078f209 1610}
7322fd19 1611EXPORT_SYMBOL(ath9k_hw_keyisvalid);
f078f209 1612
f1dc5600
S		 1613/******************************/
1614/* Power Management (Chipset) */
1615/******************************/
1616
42d5bc3f
LR		 1617/*
1618 * Notify Power Mgt is disabled in self-generated frames.
1619 * If requested, force chip to sleep.
1620 */
cbe61d8a 1621static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1622{
f1dc5600
S		 1623 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1624 if (setChip) {
42d5bc3f
LR		 1625 /*
1626 * Clear the RTC force wake bit to allow the
1627 * mac to go to sleep.
1628 */
f1dc5600
S		 1629 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1630 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1631 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1632 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1633
42d5bc3f 1634 /* Shutdown chip. Active low */
14b3af38 1635 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1636 REG_CLR_BIT(ah, (AR_RTC_RESET),
1637 AR_RTC_RESET_EN);
f1dc5600 1638 }
f078f209
LR		 1639}
1640
bbd79af5
LR		 1641/*
1642 * Notify Power Management is enabled in self-generating
1643 * frames. If request, set power mode of chip to
1644 * auto/normal. Duration in units of 128us (1/8 TU).
1645 */
cbe61d8a 1646static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1647{
f1dc5600
S		 1648 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1649 if (setChip) {
2660b81a 1650 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1651
f1dc5600 1652 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1653 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1654 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1655 AR_RTC_FORCE_WAKE_ON_INT);
1656 } else {
bbd79af5
LR		 1657 /*
1658 * Clear the RTC force wake bit to allow the
1659 * mac to go to sleep.
1660 */
f1dc5600
S		 1661 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1662 AR_RTC_FORCE_WAKE_EN);
f078f209 1663 }
f078f209 1664 }
f078f209
LR		 1665}
1666
cbe61d8a 1667static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1668{
f1dc5600
S		 1669 u32 val;
1670 int i;
f078f209 1671
f1dc5600
S		 1672 if (setChip) {
1673 if ((REG_READ(ah, AR_RTC_STATUS) &
1674 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1675 if (ath9k_hw_set_reset_reg(ah,
1676 ATH9K_RESET_POWER_ON) != true) {
1677 return false;
1678 }
e041228f
LR		 1679 if (!AR_SREV_9300_20_OR_LATER(ah))
1680 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1681 }
1682 if (AR_SREV_9100(ah))
1683 REG_SET_BIT(ah, AR_RTC_RESET,
1684 AR_RTC_RESET_EN);
f078f209 1685
f1dc5600
S		 1686 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1687 AR_RTC_FORCE_WAKE_EN);
1688 udelay(50);
f078f209 1689
f1dc5600
S		 1690 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1691 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1692 if (val == AR_RTC_STATUS_ON)
1693 break;
1694 udelay(50);
1695 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1696 AR_RTC_FORCE_WAKE_EN);
f078f209 1697 }
f1dc5600 1698 if (i == 0) {
c46917bb
LR		 1699 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1700 "Failed to wakeup in %uus\n",
1701 POWER_UP_TIME / 20);
f1dc5600 1702 return false;
f078f209 1703 }
f078f209
LR		 1704 }
1705
f1dc5600 1706 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1707
f1dc5600 1708 return true;
f078f209
LR		 1709}
1710
9ecdef4b 1711bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1712{
c46917bb 1713 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1714 int status = true, setChip = true;
f1dc5600
S		 1715 static const char *modes[] = {
1716 "AWAKE",
1717 "FULL-SLEEP",
1718 "NETWORK SLEEP",
1719 "UNDEFINED"
1720 };
f1dc5600 1721
cbdec975
GJ		 1722 if (ah->power_mode == mode)
1723 return status;
1724
c46917bb
LR		 1725 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1726 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1727
1728 switch (mode) {
1729 case ATH9K_PM_AWAKE:
1730 status = ath9k_hw_set_power_awake(ah, setChip);
1731 break;
1732 case ATH9K_PM_FULL_SLEEP:
1733 ath9k_set_power_sleep(ah, setChip);
2660b81a 1734 ah->chip_fullsleep = true;
f1dc5600
S		 1735 break;
1736 case ATH9K_PM_NETWORK_SLEEP:
1737 ath9k_set_power_network_sleep(ah, setChip);
1738 break;
f078f209 1739 default:
c46917bb
LR		 1740 ath_print(common, ATH_DBG_FATAL,
1741 "Unknown power mode %u\n", mode);
f078f209
LR		 1742 return false;
1743 }
2660b81a 1744 ah->power_mode = mode;
f1dc5600
S		 1745
1746 return status;
f078f209 1747}
7322fd19 1748EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1749
f1dc5600
S		 1750/*******************/
1751/* Beacon Handling */
1752/*******************/
1753
cbe61d8a 1754void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 1755{
f078f209
LR		 1756 int flags = 0;
1757
2660b81a 1758 ah->beacon_interval = beacon_period;
f078f209 1759
2660b81a 1760 switch (ah->opmode) {
d97809db
CM		 1761 case NL80211_IFTYPE_STATION:
1762 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 1763 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1764 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1765 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1766 flags |= AR_TBTT_TIMER_EN;
1767 break;
d97809db 1768 case NL80211_IFTYPE_ADHOC:
9cb5412b 1769 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 1770 REG_SET_BIT(ah, AR_TXCFG,
1771 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1772 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1773 TU_TO_USEC(next_beacon +
2660b81a
S		 1774 (ah->atim_window ? ah->
1775 atim_window : 1)));
f078f209 1776 flags |= AR_NDP_TIMER_EN;
d97809db 1777 case NL80211_IFTYPE_AP:
f078f209
LR		 1778 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1779 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1780 TU_TO_USEC(next_beacon -
2660b81a 1781 ah->config.
60b67f51 1782 dma_beacon_response_time));
f078f209
LR		 1783 REG_WRITE(ah, AR_NEXT_SWBA,
1784 TU_TO_USEC(next_beacon -
2660b81a 1785 ah->config.
60b67f51 1786 sw_beacon_response_time));
f078f209
LR		 1787 flags |=
1788 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1789 break;
d97809db 1790 default:
c46917bb
LR		 1791 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1792 "%s: unsupported opmode: %d\n",
1793 __func__, ah->opmode);
d97809db
CM		 1794 return;
1795 break;
f078f209
LR		 1796 }
1797
1798 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1799 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1800 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1801 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1802
1803 beacon_period &= ~ATH9K_BEACON_ENA;
1804 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 1805 ath9k_hw_reset_tsf(ah);
1806 }
1807
1808 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1809}
7322fd19 1810EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 1811
cbe61d8a 1812void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 1813 const struct ath9k_beacon_state *bs)
f078f209
LR		 1814{
1815 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 1816 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1817 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 1818
1819 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1820
1821 REG_WRITE(ah, AR_BEACON_PERIOD,
1822 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1823 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1824 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1825
1826 REG_RMW_FIELD(ah, AR_RSSI_THR,
1827 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1828
1829 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1830
1831 if (bs->bs_sleepduration > beaconintval)
1832 beaconintval = bs->bs_sleepduration;
1833
1834 dtimperiod = bs->bs_dtimperiod;
1835 if (bs->bs_sleepduration > dtimperiod)
1836 dtimperiod = bs->bs_sleepduration;
1837
1838 if (beaconintval == dtimperiod)
1839 nextTbtt = bs->bs_nextdtim;
1840 else
1841 nextTbtt = bs->bs_nexttbtt;
1842
c46917bb
LR		 1843 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1844 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1845 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1846 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 1847
f1dc5600
S		 1848 REG_WRITE(ah, AR_NEXT_DTIM,
1849 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1850 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 1851
f1dc5600
S		 1852 REG_WRITE(ah, AR_SLEEP1,
1853 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1854 | AR_SLEEP1_ASSUME_DTIM);
f078f209 1855
f1dc5600
S		 1856 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1857 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1858 else
1859 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 1860
f1dc5600
S		 1861 REG_WRITE(ah, AR_SLEEP2,
1862 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 1863
f1dc5600
S		 1864 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1865 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 1866
f1dc5600
S		 1867 REG_SET_BIT(ah, AR_TIMER_MODE,
1868 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1869 AR_DTIM_TIMER_EN);
f078f209 1870
4af9cf4f
S		 1871 /* TSF Out of Range Threshold */
1872 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 1873}
7322fd19 1874EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 1875
f1dc5600
S		 1876/*******************/
1877/* HW Capabilities */
1878/*******************/
1879
a9a29ce6 1880int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 1881{
2660b81a 1882 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 1883 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1884 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 1885 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 1886
f1dc5600 1887 u16 capField = 0, eeval;
f078f209 1888
f74df6fb 1889 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 1890 regulatory->current_rd = eeval;
f078f209 1891
f74df6fb 1892 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 1893 if (AR_SREV_9285_10_OR_LATER(ah))
1894 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 1895 regulatory->current_rd_ext = eeval;
f078f209 1896
f74df6fb 1897 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 1898
2660b81a 1899 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 1900 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 1901 if (regulatory->current_rd == 0x64 ||
1902 regulatory->current_rd == 0x65)
1903 regulatory->current_rd += 5;
1904 else if (regulatory->current_rd == 0x41)
1905 regulatory->current_rd = 0x43;
c46917bb
LR		 1906 ath_print(common, ATH_DBG_REGULATORY,
1907 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 1908 }
f078f209 1909
f74df6fb 1910 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6
GJ		 1911 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1912 ath_print(common, ATH_DBG_FATAL,
1913 "no band has been marked as supported in EEPROM.\n");
1914 return -EINVAL;
1915 }
1916
f1dc5600 1917 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 1918
f1dc5600
S		 1919 if (eeval & AR5416_OPFLAGS_11A) {
1920 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 1921 if (ah->config.ht_enable) {
f1dc5600
S		 1922 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
1923 set_bit(ATH9K_MODE_11NA_HT20,
1924 pCap->wireless_modes);
1925 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
1926 set_bit(ATH9K_MODE_11NA_HT40PLUS,
1927 pCap->wireless_modes);
1928 set_bit(ATH9K_MODE_11NA_HT40MINUS,
1929 pCap->wireless_modes);
1930 }
f078f209 1931 }
f078f209
LR		 1932 }
1933
f1dc5600 1934 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 1935 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 1936 if (ah->config.ht_enable) {
f1dc5600
S		 1937 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
1938 set_bit(ATH9K_MODE_11NG_HT20,
1939 pCap->wireless_modes);
1940 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
1941 set_bit(ATH9K_MODE_11NG_HT40PLUS,
1942 pCap->wireless_modes);
1943 set_bit(ATH9K_MODE_11NG_HT40MINUS,
1944 pCap->wireless_modes);
1945 }
1946 }
f078f209 1947 }
f1dc5600 1948
f74df6fb 1949 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 1950 /*
1951 * For AR9271 we will temporarilly uses the rx chainmax as read from
1952 * the EEPROM.
1953 */
8147f5de 1954 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 1955 !(eeval & AR5416_OPFLAGS_11A) &&
1956 !(AR_SREV_9271(ah)))
1957 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 1958 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1959 else
d7e7d229 1960 /* Use rx_chainmask from EEPROM. */
8147f5de 1961 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 1962
d535a42a 1963 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 1964 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 1965
f1dc5600
S		 1966 pCap->low_2ghz_chan = 2312;
1967 pCap->high_2ghz_chan = 2732;
f078f209 1968
f1dc5600
S		 1969 pCap->low_5ghz_chan = 4920;
1970 pCap->high_5ghz_chan = 6100;
f078f209 1971
f1dc5600
S		 1972 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
1973 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
1974 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 1975
f1dc5600
S		 1976 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
1977 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
1978 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 1979
2660b81a 1980 if (ah->config.ht_enable)
f1dc5600
S		 1981 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1982 else
1983 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 1984
f1dc5600
S		 1985 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
1986 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
1987 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
1988 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 1989
f1dc5600
S		 1990 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1991 pCap->total_queues =
1992 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1993 else
1994 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 1995
f1dc5600
S		 1996 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1997 pCap->keycache_size =
1998 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
1999 else
2000 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 2001
f1dc5600 2002 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f4709fdf
LR		 2003
2004 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2005 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2006 else
2007 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 2008
5b5fa355
S		 2009 if (AR_SREV_9271(ah))
2010 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2011 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2012 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2013 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 2014 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2015 else
2016 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2017
f1dc5600
S		 2018 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2019 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2020 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2021 } else {
2022 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 2023 }
2024
f1dc5600
S		 2025 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2026
e97275cb 2027#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2028 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2029 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2030 ah->rfkill_gpio =
2031 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2032 ah->rfkill_polarity =
2033 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2034
2035 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2036 }
f1dc5600 2037#endif
bde748a4
VN		 2038 if (AR_SREV_9271(ah))
2039 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2040 else
2041 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2042
e7594072 2043 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2044 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2045 else
2046 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2047
608b88cb 2048 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 2049 pCap->reg_cap =
2050 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2051 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2052 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2053 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 2054 } else {
f1dc5600
S		 2055 pCap->reg_cap =
2056 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2057 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 2058 }
f078f209 2059
ebb90cfc
SB		 2060 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2061 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2062 AR_SREV_5416(ah))
2063 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 2064
2065 pCap->num_antcfg_5ghz =
f74df6fb 2066 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 2067 pCap->num_antcfg_2ghz =
f74df6fb 2068 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 2069
fe12946e 2070 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 2071 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 2072 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2073 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 2074
8c8f9ba7 2075 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 2076 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2077 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 2078 } else {
766ec4a9 2079 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 2080 }
22f25d0d 2081 } else {
766ec4a9 2082 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 2083 }
a9a29ce6 2084
ceb26445 2085 if (AR_SREV_9300_20_OR_LATER(ah)) {
1adf02ff 2086 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
ceb26445
VT		 2087 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2088 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2089 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3
VT		 2090 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2091 } else {
2092 pCap->tx_desc_len = sizeof(struct ath_desc);
ceb26445 2093 }
1adf02ff 2094
6c84ce08
VT		 2095 if (AR_SREV_9300_20_OR_LATER(ah))
2096 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2097
a9a29ce6 2098 return 0;
f078f209
LR		 2099}
2100
cbe61d8a 2101bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2102 u32 capability, u32 *result)
f078f209 2103{
608b88cb 2104 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 2105 switch (type) {
2106 case ATH9K_CAP_CIPHER:
2107 switch (capability) {
2108 case ATH9K_CIPHER_AES_CCM:
2109 case ATH9K_CIPHER_AES_OCB:
2110 case ATH9K_CIPHER_TKIP:
2111 case ATH9K_CIPHER_WEP:
2112 case ATH9K_CIPHER_MIC:
2113 case ATH9K_CIPHER_CLR:
2114 return true;
2115 default:
2116 return false;
2117 }
2118 case ATH9K_CAP_TKIP_MIC:
2119 switch (capability) {
2120 case 0:
2121 return true;
2122 case 1:
2660b81a 2123 return (ah->sta_id1_defaults &
f1dc5600
S		 2124 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2125 false;
2126 }
2127 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 2128 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 2129 false : true;
f1dc5600
S		 2130 case ATH9K_CAP_MCAST_KEYSRCH:
2131 switch (capability) {
2132 case 0:
2133 return true;
2134 case 1:
2135 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2136 return false;
2137 } else {
2660b81a 2138 return (ah->sta_id1_defaults &
f1dc5600
S		 2139 AR_STA_ID1_MCAST_KSRCH) ? true :
2140 false;
2141 }
2142 }
2143 return false;
f1dc5600
S		 2144 case ATH9K_CAP_TXPOW:
2145 switch (capability) {
2146 case 0:
2147 return 0;
2148 case 1:
608b88cb 2149 *result = regulatory->power_limit;
f1dc5600
S		 2150 return 0;
2151 case 2:
608b88cb 2152 *result = regulatory->max_power_level;
f1dc5600
S		 2153 return 0;
2154 case 3:
608b88cb 2155 *result = regulatory->tp_scale;
f1dc5600
S		 2156 return 0;
2157 }
2158 return false;
8bd1d07f
SB		 2159 case ATH9K_CAP_DS:
2160 return (AR_SREV_9280_20_OR_LATER(ah) &&
2161 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2162 ? false : true;
f1dc5600
S		 2163 default:
2164 return false;
f078f209 2165 }
f078f209 2166}
7322fd19 2167EXPORT_SYMBOL(ath9k_hw_getcapability);
f078f209 2168
cbe61d8a 2169bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2170 u32 capability, u32 setting, int *status)
f078f209 2171{
f1dc5600
S		 2172 switch (type) {
2173 case ATH9K_CAP_TKIP_MIC:
2174 if (setting)
2660b81a 2175 ah->sta_id1_defaults |=
f1dc5600
S		 2176 AR_STA_ID1_CRPT_MIC_ENABLE;
2177 else
2660b81a 2178 ah->sta_id1_defaults &=
f1dc5600
S		 2179 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2180 return true;
f1dc5600
S		 2181 case ATH9K_CAP_MCAST_KEYSRCH:
2182 if (setting)
2660b81a 2183 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2184 else
2660b81a 2185 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2186 return true;
f1dc5600
S		 2187 default:
2188 return false;
f078f209
LR		 2189 }
2190}
7322fd19 2191EXPORT_SYMBOL(ath9k_hw_setcapability);
f078f209 2192
f1dc5600
S		 2193/****************************/
2194/* GPIO / RFKILL / Antennae */
2195/****************************/
f078f209 2196
cbe61d8a 2197static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2198 u32 gpio, u32 type)
2199{
2200 int addr;
2201 u32 gpio_shift, tmp;
f078f209 2202
f1dc5600
S		 2203 if (gpio > 11)
2204 addr = AR_GPIO_OUTPUT_MUX3;
2205 else if (gpio > 5)
2206 addr = AR_GPIO_OUTPUT_MUX2;
2207 else
2208 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2209
f1dc5600 2210 gpio_shift = (gpio % 6) * 5;
f078f209 2211
f1dc5600
S		 2212 if (AR_SREV_9280_20_OR_LATER(ah)
2213 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2214 REG_RMW(ah, addr, (type << gpio_shift),
2215 (0x1f << gpio_shift));
f078f209 2216 } else {
f1dc5600
S		 2217 tmp = REG_READ(ah, addr);
2218 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2219 tmp &= ~(0x1f << gpio_shift);
2220 tmp |= (type << gpio_shift);
2221 REG_WRITE(ah, addr, tmp);
f078f209 2222 }
f078f209
LR		 2223}
2224
cbe61d8a 2225void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2226{
f1dc5600 2227 u32 gpio_shift;
f078f209 2228
9680e8a3 2229 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2230
f1dc5600 2231 gpio_shift = gpio << 1;
f078f209 2232
f1dc5600
S		 2233 REG_RMW(ah,
2234 AR_GPIO_OE_OUT,
2235 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2236 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2237}
7322fd19 2238EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2239
cbe61d8a 2240u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2241{
cb33c412
SB		 2242#define MS_REG_READ(x, y) \
2243 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2244
2660b81a 2245 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2246 return 0xffffffff;
f078f209 2247
783dfca1
FF		 2248 if (AR_SREV_9300_20_OR_LATER(ah))
2249 return MS_REG_READ(AR9300, gpio) != 0;
2250 else if (AR_SREV_9271(ah))
5b5fa355
S		 2251 return MS_REG_READ(AR9271, gpio) != 0;
2252 else if (AR_SREV_9287_10_OR_LATER(ah))
ac88b6ec
VN		 2253 return MS_REG_READ(AR9287, gpio) != 0;
2254 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2255 return MS_REG_READ(AR9285, gpio) != 0;
2256 else if (AR_SREV_9280_10_OR_LATER(ah))
2257 return MS_REG_READ(AR928X, gpio) != 0;
2258 else
2259 return MS_REG_READ(AR, gpio) != 0;
f078f209 2260}
7322fd19 2261EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2262
cbe61d8a 2263void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2264 u32 ah_signal_type)
f078f209 2265{
f1dc5600 2266 u32 gpio_shift;
f078f209 2267
f1dc5600 2268 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 2269
f1dc5600 2270 gpio_shift = 2 * gpio;
f078f209 2271
f1dc5600
S		 2272 REG_RMW(ah,
2273 AR_GPIO_OE_OUT,
2274 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2275 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2276}
7322fd19 2277EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2278
cbe61d8a 2279void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2280{
5b5fa355
S		 2281 if (AR_SREV_9271(ah))
2282 val = ~val;
2283
f1dc5600
S		 2284 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2285 AR_GPIO_BIT(gpio));
f078f209 2286}
7322fd19 2287EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2288
cbe61d8a 2289u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2290{
f1dc5600 2291 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2292}
7322fd19 2293EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2294
cbe61d8a 2295void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2296{
f1dc5600 2297 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2298}
7322fd19 2299EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2300
f1dc5600
S		 2301/*********************/
2302/* General Operation */
2303/*********************/
2304
cbe61d8a 2305u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2306{
f1dc5600
S		 2307 u32 bits = REG_READ(ah, AR_RX_FILTER);
2308 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2309
f1dc5600
S		 2310 if (phybits & AR_PHY_ERR_RADAR)
2311 bits |= ATH9K_RX_FILTER_PHYRADAR;
2312 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2313 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2314
f1dc5600 2315 return bits;
f078f209 2316}
7322fd19 2317EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2318
cbe61d8a 2319void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2320{
f1dc5600 2321 u32 phybits;
f078f209 2322
7ea310be
S		 2323 REG_WRITE(ah, AR_RX_FILTER, bits);
2324
f1dc5600
S		 2325 phybits = 0;
2326 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2327 phybits |= AR_PHY_ERR_RADAR;
2328 if (bits & ATH9K_RX_FILTER_PHYERR)
2329 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2330 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2331
f1dc5600
S		 2332 if (phybits)
2333 REG_WRITE(ah, AR_RXCFG,
2334 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2335 else
2336 REG_WRITE(ah, AR_RXCFG,
2337 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2338}
7322fd19 2339EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2340
cbe61d8a 2341bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2342{
63a75b91
SB		 2343 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2344 return false;
2345
2346 ath9k_hw_init_pll(ah, NULL);
2347 return true;
f1dc5600 2348}
7322fd19 2349EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2350
cbe61d8a 2351bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2352{
9ecdef4b 2353 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2354 return false;
f078f209 2355
63a75b91
SB		 2356 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2357 return false;
2358
2359 ath9k_hw_init_pll(ah, NULL);
2360 return true;
f078f209 2361}
7322fd19 2362EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2363
8fbff4b8 2364void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 2365{
608b88cb 2366 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2367 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2368 struct ieee80211_channel *channel = chan->chan;
f078f209 2369
608b88cb 2370 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2371
8fbff4b8 2372 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2373 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2374 channel->max_antenna_gain * 2,
2375 channel->max_power * 2,
2376 min((u32) MAX_RATE_POWER,
608b88cb 2377 (u32) regulatory->power_limit));
6f255425 2378}
7322fd19 2379EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2380
cbe61d8a 2381void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 2382{
1510718d 2383 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
f078f209 2384}
7322fd19 2385EXPORT_SYMBOL(ath9k_hw_setmac);
f078f209 2386
cbe61d8a 2387void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2388{
2660b81a 2389 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2390}
7322fd19 2391EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2392
cbe61d8a 2393void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2394{
f1dc5600
S		 2395 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2396 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2397}
7322fd19 2398EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2399
f2b2143e 2400void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2401{
1510718d
LR		 2402 struct ath_common *common = ath9k_hw_common(ah);
2403
2404 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2405 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2406 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2407}
7322fd19 2408EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2409
cbe61d8a 2410u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2411{
f1dc5600 2412 u64 tsf;
f078f209 2413
f1dc5600
S		 2414 tsf = REG_READ(ah, AR_TSF_U32);
2415 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 2416
f1dc5600
S		 2417 return tsf;
2418}
7322fd19 2419EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2420
cbe61d8a 2421void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2422{
27abe060 2423 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2424 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2425}
7322fd19 2426EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2427
cbe61d8a 2428void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2429{
f9b604f6
GJ		 2430 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2431 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 2432 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2433 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2434
f1dc5600
S		 2435 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2436}
7322fd19 2437EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2438
54e4cec6 2439void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2440{
f1dc5600 2441 if (setting)
2660b81a 2442 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2443 else
2660b81a 2444 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2445}
7322fd19 2446EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2447
30cbd422
LR		 2448/*
2449 * Extend 15-bit time stamp from rx descriptor to
2450 * a full 64-bit TSF using the current h/w TSF.
2451*/
2452u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2453{
2454 u64 tsf;
2455
2456 tsf = ath9k_hw_gettsf64(ah);
2457 if ((tsf & 0x7fff) < rstamp)
2458 tsf -= 0x8000;
2459 return (tsf & ~0x7fff) | rstamp;
2460}
2461EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2462
25c56eec 2463void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2464{
25c56eec 2465 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2466 u32 macmode;
2467
25c56eec 2468 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2469 macmode = AR_2040_JOINED_RX_CLEAR;
2470 else
2471 macmode = 0;
f078f209 2472
f1dc5600 2473 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2474}
ff155a45
VT		 2475
2476/* HW Generic timers configuration */
2477
2478static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2479{
2480 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2481 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2482 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2483 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2484 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2485 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2486 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2487 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2488 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2489 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2490 AR_NDP2_TIMER_MODE, 0x0002},
2491 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2492 AR_NDP2_TIMER_MODE, 0x0004},
2493 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2494 AR_NDP2_TIMER_MODE, 0x0008},
2495 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2496 AR_NDP2_TIMER_MODE, 0x0010},
2497 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2498 AR_NDP2_TIMER_MODE, 0x0020},
2499 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2500 AR_NDP2_TIMER_MODE, 0x0040},
2501 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2502 AR_NDP2_TIMER_MODE, 0x0080}
2503};
2504
2505/* HW generic timer primitives */
2506
2507/* compute and clear index of rightmost 1 */
2508static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2509{
2510 u32 b;
2511
2512 b = *mask;
2513 b &= (0-b);
2514 *mask &= ~b;
2515 b *= debruijn32;
2516 b >>= 27;
2517
2518 return timer_table->gen_timer_index[b];
2519}
2520
1773912b 2521u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2522{
2523 return REG_READ(ah, AR_TSF_L32);
2524}
7322fd19 2525EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2526
2527struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2528 void (*trigger)(void *),
2529 void (*overflow)(void *),
2530 void *arg,
2531 u8 timer_index)
2532{
2533 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2534 struct ath_gen_timer *timer;
2535
2536 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2537
2538 if (timer == NULL) {
c46917bb
LR		 2539 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2540 "Failed to allocate memory"
2541 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 2542 return NULL;
2543 }
2544
2545 /* allocate a hardware generic timer slot */
2546 timer_table->timers[timer_index] = timer;
2547 timer->index = timer_index;
2548 timer->trigger = trigger;
2549 timer->overflow = overflow;
2550 timer->arg = arg;
2551
2552 return timer;
2553}
7322fd19 2554EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2555
cd9bf689
LR		 2556void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2557 struct ath_gen_timer *timer,
2558 u32 timer_next,
2559 u32 timer_period)
ff155a45
VT		 2560{
2561 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2562 u32 tsf;
2563
2564 BUG_ON(!timer_period);
2565
2566 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2567
2568 tsf = ath9k_hw_gettsf32(ah);
2569
c46917bb
LR		 2570 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2571 "curent tsf %x period %x"
2572 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 2573
2574 /*
2575 * Pull timer_next forward if the current TSF already passed it
2576 * because of software latency
2577 */
2578 if (timer_next < tsf)
2579 timer_next = tsf + timer_period;
2580
2581 /*
2582 * Program generic timer registers
2583 */
2584 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2585 timer_next);
2586 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2587 timer_period);
2588 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2589 gen_tmr_configuration[timer->index].mode_mask);
2590
2591 /* Enable both trigger and thresh interrupt masks */
2592 REG_SET_BIT(ah, AR_IMR_S5,
2593 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2594 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2595}
7322fd19 2596EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2597
cd9bf689 2598void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2599{
2600 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2601
2602 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2603 (timer->index >= ATH_MAX_GEN_TIMER)) {
2604 return;
2605 }
2606
2607 /* Clear generic timer enable bits. */
2608 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2609 gen_tmr_configuration[timer->index].mode_mask);
2610
2611 /* Disable both trigger and thresh interrupt masks */
2612 REG_CLR_BIT(ah, AR_IMR_S5,
2613 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2614 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2615
2616 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 2617}
7322fd19 2618EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2619
2620void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2621{
2622 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2623
2624 /* free the hardware generic timer slot */
2625 timer_table->timers[timer->index] = NULL;
2626 kfree(timer);
2627}
7322fd19 2628EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2629
2630/*
2631 * Generic Timer Interrupts handling
2632 */
2633void ath_gen_timer_isr(struct ath_hw *ah)
2634{
2635 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2636 struct ath_gen_timer *timer;
c46917bb 2637 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 2638 u32 trigger_mask, thresh_mask, index;
2639
2640 /* get hardware generic timer interrupt status */
2641 trigger_mask = ah->intr_gen_timer_trigger;
2642 thresh_mask = ah->intr_gen_timer_thresh;
2643 trigger_mask &= timer_table->timer_mask.val;
2644 thresh_mask &= timer_table->timer_mask.val;
2645
2646 trigger_mask &= ~thresh_mask;
2647
2648 while (thresh_mask) {
2649 index = rightmost_index(timer_table, &thresh_mask);
2650 timer = timer_table->timers[index];
2651 BUG_ON(!timer);
c46917bb
LR		 2652 ath_print(common, ATH_DBG_HWTIMER,
2653 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 2654 timer->overflow(timer->arg);
2655 }
2656
2657 while (trigger_mask) {
2658 index = rightmost_index(timer_table, &trigger_mask);
2659 timer = timer_table->timers[index];
2660 BUG_ON(!timer);
c46917bb
LR		 2661 ath_print(common, ATH_DBG_HWTIMER,
2662 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 2663 timer->trigger(timer->arg);
2664 }
2665}
7322fd19 2666EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2667
05020d23
S		 2668/********/
2669/* HTC */
2670/********/
2671
2672void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2673{
2674 ah->htc_reset_init = true;
2675}
2676EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2677
2da4f01a
LR		 2678static struct {
2679 u32 version;
2680 const char * name;
2681} ath_mac_bb_names[] = {
2682 /* Devices with external radios */
2683 { AR_SREV_VERSION_5416_PCI, "5416" },
2684 { AR_SREV_VERSION_5416_PCIE, "5418" },
2685 { AR_SREV_VERSION_9100, "9100" },
2686 { AR_SREV_VERSION_9160, "9160" },
2687 /* Single-chip solutions */
2688 { AR_SREV_VERSION_9280, "9280" },
2689 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 2690 { AR_SREV_VERSION_9287, "9287" },
2691 { AR_SREV_VERSION_9271, "9271" },
2da4f01a
LR		 2692};
2693
2694/* For devices with external radios */
2695static struct {
2696 u16 version;
2697 const char * name;
2698} ath_rf_names[] = {
2699 { 0, "5133" },
2700 { AR_RAD5133_SREV_MAJOR, "5133" },
2701 { AR_RAD5122_SREV_MAJOR, "5122" },
2702 { AR_RAD2133_SREV_MAJOR, "2133" },
2703 { AR_RAD2122_SREV_MAJOR, "2122" }
2704};
2705
2706/*
2707 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2708 */
f934c4d9 2709static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 2710{
2711 int i;
2712
2713 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2714 if (ath_mac_bb_names[i].version == mac_bb_version) {
2715 return ath_mac_bb_names[i].name;
2716 }
2717 }
2718
2719 return "????";
2720}
2da4f01a
LR		 2721
2722/*
2723 * Return the RF name. "????" is returned if the RF is unknown.
2724 * Used for devices with external radios.
2725 */
f934c4d9 2726static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 2727{
2728 int i;
2729
2730 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2731 if (ath_rf_names[i].version == rf_version) {
2732 return ath_rf_names[i].name;
2733 }
2734 }
2735
2736 return "????";
2737}
f934c4d9
LR		 2738
2739void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2740{
2741 int used;
2742
2743 /* chipsets >= AR9280 are single-chip */
2744 if (AR_SREV_9280_10_OR_LATER(ah)) {
2745 used = snprintf(hw_name, len,
2746 "Atheros AR%s Rev:%x",
2747 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2748 ah->hw_version.macRev);
2749 }
2750 else {
2751 used = snprintf(hw_name, len,
2752 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2753 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2754 ah->hw_version.macRev,
2755 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2756 AR_RADIO_SREV_MAJOR)),
2757 ah->hw_version.phyRev);
2758 }
2759
2760 hw_name[used] = '\0';
2761}
2762EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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