projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ath9k_hw: Add WoW hardware capability flags
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
f078f209
LR		 20#include <asm/unaligned.h>
21
af03abec 22#include "hw.h"
d70357d5 23#include "hw-ops.h"
cfe8cba9 24#include "rc.h"
b622a720 25#include "ar9003_mac.h"
f4701b5a 26#include "ar9003_mci.h"
462e58f2
BG		 27#include "debug.h"
28#include "ath9k.h"
f078f209 29
cbe61d8a 30static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 31
7322fd19
LR		 32MODULE_AUTHOR("Atheros Communications");
33MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
34MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
35MODULE_LICENSE("Dual BSD/GPL");
36
37static int __init ath9k_init(void)
38{
39 return 0;
40}
41module_init(ath9k_init);
42
43static void __exit ath9k_exit(void)
44{
45 return;
46}
47module_exit(ath9k_exit);
48
d70357d5
LR		 49/* Private hardware callbacks */
50
51static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
52{
53 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
54}
55
56static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
57{
58 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
59}
60
64773964
LR		 61static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
62 struct ath9k_channel *chan)
63{
64 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
65}
66
991312d8
LR		 67static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
68{
69 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
70 return;
71
72 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
73}
74
e36b27af
LR		 75static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
76{
77 /* You will not have this callback if using the old ANI */
78 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
79 return;
80
81 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
82}
83
f1dc5600
S		 84/********************/
85/* Helper Functions */
86/********************/
f078f209 87
462e58f2
BG		 88#ifdef CONFIG_ATH9K_DEBUGFS
89
90void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
91{
92 struct ath_softc *sc = common->priv;
93 if (sync_cause)
94 sc->debug.stats.istats.sync_cause_all++;
95 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
96 sc->debug.stats.istats.sync_rtc_irq++;
97 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
98 sc->debug.stats.istats.sync_mac_irq++;
99 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
100 sc->debug.stats.istats.eeprom_illegal_access++;
101 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
102 sc->debug.stats.istats.apb_timeout++;
103 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
104 sc->debug.stats.istats.pci_mode_conflict++;
105 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
106 sc->debug.stats.istats.host1_fatal++;
107 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
108 sc->debug.stats.istats.host1_perr++;
109 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
110 sc->debug.stats.istats.trcv_fifo_perr++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
112 sc->debug.stats.istats.radm_cpl_ep++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
114 sc->debug.stats.istats.radm_cpl_dllp_abort++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
116 sc->debug.stats.istats.radm_cpl_tlp_abort++;
117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
118 sc->debug.stats.istats.radm_cpl_ecrc_err++;
119 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
120 sc->debug.stats.istats.radm_cpl_timeout++;
121 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
122 sc->debug.stats.istats.local_timeout++;
123 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
124 sc->debug.stats.istats.pm_access++;
125 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
126 sc->debug.stats.istats.mac_awake++;
127 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
128 sc->debug.stats.istats.mac_asleep++;
129 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
130 sc->debug.stats.istats.mac_sleep_access++;
131}
132#endif
133
134
dfdac8ac 135static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 136{
b002a4a9 137 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
dfdac8ac
FF		 138 struct ath_common *common = ath9k_hw_common(ah);
139 unsigned int clockrate;
cbe61d8a 140
087b6ff6
FF		 141 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
142 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
143 clockrate = 117;
144 else if (!ah->curchan) /* should really check for CCK instead */
dfdac8ac
FF		 145 clockrate = ATH9K_CLOCK_RATE_CCK;
146 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
147 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
148 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
149 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 150 else
dfdac8ac
FF		 151 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
152
153 if (conf_is_ht40(conf))
154 clockrate *= 2;
155
906c7205
FF		 156 if (ah->curchan) {
157 if (IS_CHAN_HALF_RATE(ah->curchan))
158 clockrate /= 2;
159 if (IS_CHAN_QUARTER_RATE(ah->curchan))
160 clockrate /= 4;
161 }
162
dfdac8ac 163 common->clockrate = clockrate;
f1dc5600
S		 164}
165
cbe61d8a 166static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 167{
dfdac8ac 168 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 169
dfdac8ac 170 return usecs * common->clockrate;
f1dc5600 171}
f078f209 172
0caa7b14 173bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 174{
175 int i;
176
0caa7b14
S		 177 BUG_ON(timeout < AH_TIME_QUANTUM);
178
179 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 180 if ((REG_READ(ah, reg) & mask) == val)
181 return true;
182
183 udelay(AH_TIME_QUANTUM);
184 }
04bd4638 185
d2182b69 186 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 187 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
188 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 189
f1dc5600 190 return false;
f078f209 191}
7322fd19 192EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 193
7c5adc8d
FF		 194void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
195 int hw_delay)
196{
197 if (IS_CHAN_B(chan))
198 hw_delay = (4 * hw_delay) / 22;
199 else
200 hw_delay /= 10;
201
202 if (IS_CHAN_HALF_RATE(chan))
203 hw_delay *= 2;
204 else if (IS_CHAN_QUARTER_RATE(chan))
205 hw_delay *= 4;
206
207 udelay(hw_delay + BASE_ACTIVATE_DELAY);
208}
209
a9b6b256
FF		 210void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
211 int column, unsigned int *writecnt)
212{
213 int r;
214
215 ENABLE_REGWRITE_BUFFER(ah);
216 for (r = 0; r < array->ia_rows; r++) {
217 REG_WRITE(ah, INI_RA(array, r, 0),
218 INI_RA(array, r, column));
219 DO_DELAY(*writecnt);
220 }
221 REGWRITE_BUFFER_FLUSH(ah);
222}
223
f078f209
LR		 224u32 ath9k_hw_reverse_bits(u32 val, u32 n)
225{
226 u32 retval;
227 int i;
228
229 for (i = 0, retval = 0; i < n; i++) {
230 retval = (retval << 1) | (val & 1);
231 val >>= 1;
232 }
233 return retval;
234}
235
cbe61d8a 236u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 237 u8 phy, int kbps,
f1dc5600
S		 238 u32 frameLen, u16 rateix,
239 bool shortPreamble)
f078f209 240{
f1dc5600 241 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 242
f1dc5600
S		 243 if (kbps == 0)
244 return 0;
f078f209 245
545750d3 246 switch (phy) {
46d14a58 247 case WLAN_RC_PHY_CCK:
f1dc5600 248 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 249 if (shortPreamble)
f1dc5600
S		 250 phyTime >>= 1;
251 numBits = frameLen << 3;
252 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
253 break;
46d14a58 254 case WLAN_RC_PHY_OFDM:
2660b81a 255 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 256 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
257 numBits = OFDM_PLCP_BITS + (frameLen << 3);
258 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
259 txTime = OFDM_SIFS_TIME_QUARTER
260 + OFDM_PREAMBLE_TIME_QUARTER
261 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 262 } else if (ah->curchan &&
263 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
265 numBits = OFDM_PLCP_BITS + (frameLen << 3);
266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
267 txTime = OFDM_SIFS_TIME_HALF +
268 OFDM_PREAMBLE_TIME_HALF
269 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
270 } else {
271 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
272 numBits = OFDM_PLCP_BITS + (frameLen << 3);
273 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
274 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
275 + (numSymbols * OFDM_SYMBOL_TIME);
276 }
277 break;
278 default:
3800276a
JP		 279 ath_err(ath9k_hw_common(ah),
280 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 281 txTime = 0;
282 break;
283 }
f078f209 284
f1dc5600
S		 285 return txTime;
286}
7322fd19 287EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 288
cbe61d8a 289void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 290 struct ath9k_channel *chan,
291 struct chan_centers *centers)
f078f209 292{
f1dc5600 293 int8_t extoff;
f078f209 294
f1dc5600
S		 295 if (!IS_CHAN_HT40(chan)) {
296 centers->ctl_center = centers->ext_center =
297 centers->synth_center = chan->channel;
298 return;
f078f209 299 }
f078f209 300
f1dc5600
S		 301 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
302 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
303 centers->synth_center =
304 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
305 extoff = 1;
306 } else {
307 centers->synth_center =
308 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
309 extoff = -1;
310 }
f078f209 311
f1dc5600
S		 312 centers->ctl_center =
313 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 314 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 315 centers->ext_center =
6420014c 316 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 317}
318
f1dc5600
S		 319/******************/
320/* Chip Revisions */
321/******************/
322
cbe61d8a 323static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 324{
f1dc5600 325 u32 val;
f078f209 326
ecb1d385
VT		 327 switch (ah->hw_version.devid) {
328 case AR5416_AR9100_DEVID:
329 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
330 break;
3762561a
GJ		 331 case AR9300_DEVID_AR9330:
332 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
333 if (ah->get_mac_revision) {
334 ah->hw_version.macRev = ah->get_mac_revision();
335 } else {
336 val = REG_READ(ah, AR_SREV);
337 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
338 }
339 return;
ecb1d385
VT		 340 case AR9300_DEVID_AR9340:
341 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
342 val = REG_READ(ah, AR_SREV);
343 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
344 return;
813831dc
GJ		 345 case AR9300_DEVID_QCA955X:
346 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
347 return;
ecb1d385
VT		 348 }
349
f1dc5600 350 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 351
f1dc5600
S		 352 if (val == 0xFF) {
353 val = REG_READ(ah, AR_SREV);
d535a42a
S		 354 ah->hw_version.macVersion =
355 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
356 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 357
423e38e8 358 if (AR_SREV_9462(ah))
76ed94be
MSS		 359 ah->is_pciexpress = true;
360 else
361 ah->is_pciexpress = (val &
362 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 363 } else {
364 if (!AR_SREV_9100(ah))
d535a42a 365 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 366
d535a42a 367 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 368
d535a42a 369 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 370 ah->is_pciexpress = true;
f1dc5600 371 }
f078f209
LR		 372}
373
f1dc5600
S		 374/************************************/
375/* HW Attach, Detach, Init Routines */
376/************************************/
377
cbe61d8a 378static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 379{
040b74f7 380 if (!AR_SREV_5416(ah))
f1dc5600 381 return;
f078f209 382
f1dc5600
S		 383 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
384 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
385 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
386 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
387 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
388 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
389 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
390 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
391 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 392
f1dc5600 393 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 394}
395
1f3f0618 396/* This should work for all families including legacy */
cbe61d8a 397static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 398{
c46917bb 399 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 400 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 401 u32 regHold[2];
07b2fa5a
JP		 402 static const u32 patternData[4] = {
403 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
404 };
1f3f0618 405 int i, j, loop_max;
f078f209 406
1f3f0618
SB		 407 if (!AR_SREV_9300_20_OR_LATER(ah)) {
408 loop_max = 2;
409 regAddr[1] = AR_PHY_BASE + (8 << 2);
410 } else
411 loop_max = 1;
412
413 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 414 u32 addr = regAddr[i];
415 u32 wrData, rdData;
f078f209 416
f1dc5600
S		 417 regHold[i] = REG_READ(ah, addr);
418 for (j = 0; j < 0x100; j++) {
419 wrData = (j << 16) | j;
420 REG_WRITE(ah, addr, wrData);
421 rdData = REG_READ(ah, addr);
422 if (rdData != wrData) {
3800276a
JP		 423 ath_err(common,
424 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
425 addr, wrData, rdData);
f1dc5600
S		 426 return false;
427 }
428 }
429 for (j = 0; j < 4; j++) {
430 wrData = patternData[j];
431 REG_WRITE(ah, addr, wrData);
432 rdData = REG_READ(ah, addr);
433 if (wrData != rdData) {
3800276a
JP		 434 ath_err(common,
435 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
436 addr, wrData, rdData);
f1dc5600
S		 437 return false;
438 }
f078f209 439 }
f1dc5600 440 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 441 }
f1dc5600 442 udelay(100);
cbe61d8a 443
f078f209
LR		 444 return true;
445}
446
b8b0f377 447static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 448{
449 int i;
f078f209 450
689e756f
FF		 451 ah->config.dma_beacon_response_time = 1;
452 ah->config.sw_beacon_response_time = 6;
2660b81a
S		 453 ah->config.additional_swba_backoff = 0;
454 ah->config.ack_6mb = 0x0;
455 ah->config.cwm_ignore_extcca = 0;
2660b81a 456 ah->config.pcie_clock_req = 0;
2660b81a
S		 457 ah->config.pcie_waen = 0;
458 ah->config.analog_shiftreg = 1;
03c72518 459 ah->config.enable_ani = true;
f078f209 460
f1dc5600 461 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 462 ah->config.spurchans[i][0] = AR_NO_SPUR;
463 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 464 }
465
6f481010
LR		 466 /* PAPRD needs some more work to be enabled */
467 ah->config.paprd_disable = 1;
468
0ce024cb 469 ah->config.rx_intr_mitigation = true;
6a0ec30a 470 ah->config.pcieSerDesWrite = true;
6158425b
LR		 471
472 /*
473 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
474 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
475 * This means we use it for all AR5416 devices, and the few
476 * minor PCI AR9280 devices out there.
477 *
478 * Serialization is required because these devices do not handle
479 * well the case of two concurrent reads/writes due to the latency
480 * involved. During one read/write another read/write can be issued
481 * on another CPU while the previous read/write may still be working
482 * on our hardware, if we hit this case the hardware poops in a loop.
483 * We prevent this by serializing reads and writes.
484 *
485 * This issue is not present on PCI-Express devices or pre-AR5416
486 * devices (legacy, 802.11abg).
487 */
488 if (num_possible_cpus() > 1)
2d6a5e95 489 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 490}
491
50aca25b 492static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 493{
608b88cb
LR		 494 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
495
496 regulatory->country_code = CTRY_DEFAULT;
497 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 498
d535a42a 499 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 500 ah->hw_version.subvendorid = 0;
f078f209 501
2660b81a 502 ah->atim_window = 0;
16f2411f
FF		 503 ah->sta_id1_defaults =
504 AR_STA_ID1_CRPT_MIC_ENABLE |
505 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 506 if (AR_SREV_9100(ah))
507 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
e3f2acc7 508 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 509 ah->globaltxtimeout = (u32) -1;
cbdec975 510 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 511 ah->htc_reset_init = true;
f078f209
LR		 512}
513
cbe61d8a 514static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 515{
1510718d 516 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 517 u32 sum;
518 int i;
519 u16 eeval;
07b2fa5a 520 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 521
522 sum = 0;
523 for (i = 0; i < 3; i++) {
49101676 524 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 525 sum += eeval;
1510718d
LR		 526 common->macaddr[2 * i] = eeval >> 8;
527 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 528 }
d8baa939 529 if (sum == 0 || sum == 0xffff * 3)
f078f209 530 return -EADDRNOTAVAIL;
f078f209
LR		 531
532 return 0;
533}
534
f637cfd6 535static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 536{
6cae913d 537 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 538 int ecode;
f078f209 539
6cae913d 540 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 541 if (!ath9k_hw_chip_test(ah))
542 return -ENODEV;
543 }
f078f209 544
ebd5a14a
LR		 545 if (!AR_SREV_9300_20_OR_LATER(ah)) {
546 ecode = ar9002_hw_rf_claim(ah);
547 if (ecode != 0)
548 return ecode;
549 }
f078f209 550
f637cfd6 551 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 552 if (ecode != 0)
553 return ecode;
7d01b221 554
d2182b69 555 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 556 ah->eep_ops->get_eeprom_ver(ah),
557 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 558
8fe65368
LR		 559 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
560 if (ecode) {
3800276a
JP		 561 ath_err(ath9k_hw_common(ah),
562 "Failed allocating banks for external radio\n");
48a7c3df 563 ath9k_hw_rf_free_ext_banks(ah);
8fe65368 564 return ecode;
574d6b12 565 }
f078f209 566
4279425c 567 if (ah->config.enable_ani) {
f1dc5600 568 ath9k_hw_ani_setup(ah);
f637cfd6 569 ath9k_hw_ani_init(ah);
f078f209
LR		 570 }
571
f078f209
LR		 572 return 0;
573}
574
8525f280 575static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 576{
8525f280
LR		 577 if (AR_SREV_9300_20_OR_LATER(ah))
578 ar9003_hw_attach_ops(ah);
579 else
580 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 581}
582
d70357d5
LR		 583/* Called for all hardware families */
584static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 585{
c46917bb 586 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 587 int r = 0;
aa4058ae 588
ac45c12d
SB		 589 ath9k_hw_read_revisions(ah);
590
0a8d7cb0
SB		 591 /*
592 * Read back AR_WA into a permanent copy and set bits 14 and 17.
593 * We need to do this to avoid RMW of this register. We cannot
594 * read the reg when chip is asleep.
595 */
596 ah->WARegVal = REG_READ(ah, AR_WA);
597 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
598 AR_WA_ASPM_TIMER_BASED_DISABLE);
599
aa4058ae 600 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 601 ath_err(common, "Couldn't reset chip\n");
95fafca2 602 return -EIO;
aa4058ae
LR		 603 }
604
423e38e8 605 if (AR_SREV_9462(ah))
eec353c5
RM		 606 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
607
bab1f62e
LR		 608 ath9k_hw_init_defaults(ah);
609 ath9k_hw_init_config(ah);
610
8525f280 611 ath9k_hw_attach_ops(ah);
d70357d5 612
9ecdef4b 613 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 614 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 615 return -EIO;
aa4058ae
LR		 616 }
617
f3eef645 618 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
aa4058ae 619 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
7508b657 620 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
4c85ab11 621 !ah->is_pciexpress)) {
aa4058ae
LR		 622 ah->config.serialize_regmode =
623 SER_REG_MODE_ON;
624 } else {
625 ah->config.serialize_regmode =
626 SER_REG_MODE_OFF;
627 }
628 }
629
d2182b69 630 ath_dbg(common, RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 631 ah->config.serialize_regmode);
632
f4709fdf
LR		 633 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
634 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
635 else
636 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
637
6da5a720
FF		 638 switch (ah->hw_version.macVersion) {
639 case AR_SREV_VERSION_5416_PCI:
640 case AR_SREV_VERSION_5416_PCIE:
641 case AR_SREV_VERSION_9160:
642 case AR_SREV_VERSION_9100:
643 case AR_SREV_VERSION_9280:
644 case AR_SREV_VERSION_9285:
645 case AR_SREV_VERSION_9287:
646 case AR_SREV_VERSION_9271:
647 case AR_SREV_VERSION_9300:
2c8e5937 648 case AR_SREV_VERSION_9330:
6da5a720 649 case AR_SREV_VERSION_9485:
bca04689 650 case AR_SREV_VERSION_9340:
423e38e8 651 case AR_SREV_VERSION_9462:
2b943a33 652 case AR_SREV_VERSION_9550:
6da5a720
FF		 653 break;
654 default:
3800276a
JP		 655 ath_err(common,
656 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
657 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 658 return -EOPNOTSUPP;
aa4058ae
LR		 659 }
660
2c8e5937 661 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 662 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 663 ah->is_pciexpress = false;
664
aa4058ae 665 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 666 ath9k_hw_init_cal_settings(ah);
667
668 ah->ani_function = ATH9K_ANI_ALL;
7a37081e 669 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 670 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 671 if (!AR_SREV_9300_20_OR_LATER(ah))
672 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae 673
4f17c48e
NM		 674 /* disable ANI for 9340 */
675 if (AR_SREV_9340(ah))
4279425c
NM		 676 ah->config.enable_ani = false;
677
aa4058ae
LR		 678 ath9k_hw_init_mode_regs(ah);
679
69ce674b 680 if (!ah->is_pciexpress)
aa4058ae
LR		 681 ath9k_hw_disablepcie(ah);
682
f637cfd6 683 r = ath9k_hw_post_init(ah);
aa4058ae 684 if (r)
95fafca2 685 return r;
aa4058ae
LR		 686
687 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 688 r = ath9k_hw_fill_cap_info(ah);
689 if (r)
690 return r;
691
4f3acf81
LR		 692 r = ath9k_hw_init_macaddr(ah);
693 if (r) {
3800276a 694 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 695 return r;
f078f209
LR		 696 }
697
d7e7d229 698 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 699 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 700 else
2660b81a 701 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 702
88e641df
GJ		 703 if (AR_SREV_9330(ah))
704 ah->bb_watchdog_timeout_ms = 85;
705 else
706 ah->bb_watchdog_timeout_ms = 25;
f078f209 707
211f5859
LR		 708 common->state = ATH_HW_INITIALIZED;
709
4f3acf81 710 return 0;
f078f209
LR		 711}
712
d70357d5 713int ath9k_hw_init(struct ath_hw *ah)
f078f209 714{
d70357d5
LR		 715 int ret;
716 struct ath_common *common = ath9k_hw_common(ah);
f078f209 717
d70357d5
LR		 718 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
719 switch (ah->hw_version.devid) {
720 case AR5416_DEVID_PCI:
721 case AR5416_DEVID_PCIE:
722 case AR5416_AR9100_DEVID:
723 case AR9160_DEVID_PCI:
724 case AR9280_DEVID_PCI:
725 case AR9280_DEVID_PCIE:
726 case AR9285_DEVID_PCIE:
db3cc53a
SB		 727 case AR9287_DEVID_PCI:
728 case AR9287_DEVID_PCIE:
d70357d5 729 case AR2427_DEVID_PCIE:
db3cc53a 730 case AR9300_DEVID_PCIE:
3050c914 731 case AR9300_DEVID_AR9485_PCIE:
999a7a88 732 case AR9300_DEVID_AR9330:
bca04689 733 case AR9300_DEVID_AR9340:
2b943a33 734 case AR9300_DEVID_QCA955X:
5a63ef0f 735 case AR9300_DEVID_AR9580:
423e38e8 736 case AR9300_DEVID_AR9462:
d70357d5
LR		 737 break;
738 default:
739 if (common->bus_ops->ath_bus_type == ATH_USB)
740 break;
3800276a
JP		 741 ath_err(common, "Hardware device ID 0x%04x not supported\n",
742 ah->hw_version.devid);
d70357d5
LR		 743 return -EOPNOTSUPP;
744 }
f078f209 745
d70357d5
LR		 746 ret = __ath9k_hw_init(ah);
747 if (ret) {
3800276a
JP		 748 ath_err(common,
749 "Unable to initialize hardware; initialization status: %d\n",
750 ret);
d70357d5
LR		 751 return ret;
752 }
f078f209 753
d70357d5 754 return 0;
f078f209 755}
d70357d5 756EXPORT_SYMBOL(ath9k_hw_init);
f078f209 757
cbe61d8a 758static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 759{
7d0d0df0
S		 760 ENABLE_REGWRITE_BUFFER(ah);
761
f1dc5600
S		 762 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
763 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 764
f1dc5600
S		 765 REG_WRITE(ah, AR_QOS_NO_ACK,
766 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
767 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
768 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
769
770 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
771 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
772 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
773 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
774 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 775
776 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 777}
778
b84628eb 779u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 780{
f18e3c6b
MSS		 781 struct ath_common *common = ath9k_hw_common(ah);
782 int i = 0;
783
ca7a4deb
FF		 784 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
785 udelay(100);
786 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 787
f18e3c6b
MSS		 788 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
789
ca7a4deb 790 udelay(100);
b1415819 791
f18e3c6b
MSS		 792 if (WARN_ON_ONCE(i >= 100)) {
793 ath_err(common, "PLL4 meaurement not done\n");
794 break;
795 }
796
797 i++;
798 }
799
ca7a4deb 800 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 801}
802EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
803
cbe61d8a 804static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 805 struct ath9k_channel *chan)
f078f209 806{
d09b17f7
VT		 807 u32 pll;
808
22983c30 809 if (AR_SREV_9485(ah)) {
22983c30 810
3dfd7f60
VT		 811 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
812 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
813 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
815 AR_CH0_DPLL2_KD, 0x40);
816 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
817 AR_CH0_DPLL2_KI, 0x4);
22983c30 818
3dfd7f60
VT		 819 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
820 AR_CH0_BB_DPLL1_REFDIV, 0x5);
821 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
822 AR_CH0_BB_DPLL1_NINI, 0x58);
823 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
824 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 825
826 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 827 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
828 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
829 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 830 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 831 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 832
3dfd7f60 833 /* program BB PLL phase_shift to 0x6 */
22983c30 834 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 835 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
836
837 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
838 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 839 udelay(1000);
a5415d62
GJ		 840 } else if (AR_SREV_9330(ah)) {
841 u32 ddr_dpll2, pll_control2, kd;
842
843 if (ah->is_clk_25mhz) {
844 ddr_dpll2 = 0x18e82f01;
845 pll_control2 = 0xe04a3d;
846 kd = 0x1d;
847 } else {
848 ddr_dpll2 = 0x19e82f01;
849 pll_control2 = 0x886666;
850 kd = 0x3d;
851 }
852
853 /* program DDR PLL ki and kd value */
854 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
855
856 /* program DDR PLL phase_shift */
857 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
858 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
859
860 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
861 udelay(1000);
862
863 /* program refdiv, nint, frac to RTC register */
864 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
865
866 /* program BB PLL kd and ki value */
867 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
868 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
869
870 /* program BB PLL phase_shift */
871 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
872 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
fc05a317 873 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 874 u32 regval, pll2_divint, pll2_divfrac, refdiv;
875
876 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
877 udelay(1000);
878
879 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
880 udelay(100);
881
882 if (ah->is_clk_25mhz) {
883 pll2_divint = 0x54;
884 pll2_divfrac = 0x1eb85;
885 refdiv = 3;
886 } else {
fc05a317
GJ		 887 if (AR_SREV_9340(ah)) {
888 pll2_divint = 88;
889 pll2_divfrac = 0;
890 refdiv = 5;
891 } else {
892 pll2_divint = 0x11;
893 pll2_divfrac = 0x26666;
894 refdiv = 1;
895 }
0b488ac6
VT		 896 }
897
898 regval = REG_READ(ah, AR_PHY_PLL_MODE);
899 regval |= (0x1 << 16);
900 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
901 udelay(100);
902
903 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
904 (pll2_divint << 18) | pll2_divfrac);
905 udelay(100);
906
907 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317
GJ		 908 if (AR_SREV_9340(ah))
909 regval = (regval & 0x80071fff) | (0x1 << 30) |
910 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
911 else
912 regval = (regval & 0x80071fff) | (0x3 << 30) |
913 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
0b488ac6
VT		 914 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
915 REG_WRITE(ah, AR_PHY_PLL_MODE,
916 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
917 udelay(1000);
22983c30 918 }
d09b17f7
VT		 919
920 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 921
d03a66c1 922 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 923
fc05a317
GJ		 924 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
925 AR_SREV_9550(ah))
3dfd7f60
VT		 926 udelay(1000);
927
c75724d1
LR		 928 /* Switch the core clock for ar9271 to 117Mhz */
929 if (AR_SREV_9271(ah)) {
25e2ab17
S		 930 udelay(500);
931 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 932 }
933
f1dc5600
S		 934 udelay(RTC_PLL_SETTLE_DELAY);
935
936 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6 937
fc05a317 938 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 939 if (ah->is_clk_25mhz) {
940 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
941 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
942 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
943 } else {
944 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
945 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
946 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
947 }
948 udelay(100);
949 }
f078f209
LR		 950}
951
cbe61d8a 952static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 953 enum nl80211_iftype opmode)
f078f209 954{
79d1d2b8 955 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 956 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 957 AR_IMR_TXURN |
958 AR_IMR_RXERR |
959 AR_IMR_RXORN |
960 AR_IMR_BCNMISC;
f078f209 961
3b8a0577 962 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
79d1d2b8
VT		 963 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
964
66860240
VT		 965 if (AR_SREV_9300_20_OR_LATER(ah)) {
966 imr_reg |= AR_IMR_RXOK_HP;
967 if (ah->config.rx_intr_mitigation)
968 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
969 else
970 imr_reg |= AR_IMR_RXOK_LP;
f078f209 971
66860240
VT		 972 } else {
973 if (ah->config.rx_intr_mitigation)
974 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
975 else
976 imr_reg |= AR_IMR_RXOK;
977 }
f078f209 978
66860240
VT		 979 if (ah->config.tx_intr_mitigation)
980 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
981 else
982 imr_reg |= AR_IMR_TXOK;
f078f209 983
d97809db 984 if (opmode == NL80211_IFTYPE_AP)
152d530d 985 imr_reg |= AR_IMR_MIB;
f078f209 986
7d0d0df0
S		 987 ENABLE_REGWRITE_BUFFER(ah);
988
152d530d 989 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 990 ah->imrs2_reg |= AR_IMR_S2_GTT;
991 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 992
f1dc5600
S		 993 if (!AR_SREV_9100(ah)) {
994 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 995 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 996 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
997 }
66860240 998
7d0d0df0 999 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1000
66860240
VT		 1001 if (AR_SREV_9300_20_OR_LATER(ah)) {
1002 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
1003 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
1004 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
1005 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
1006 }
f078f209
LR		 1007}
1008
b6ba41bb
FF		 1009static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
1010{
1011 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
1012 val = min(val, (u32) 0xFFFF);
1013 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
1014}
1015
0005baf4 1016static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 1017{
0005baf4
FF		 1018 u32 val = ath9k_hw_mac_to_clks(ah, us);
1019 val = min(val, (u32) 0xFFFF);
1020 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 1021}
1022
0005baf4 1023static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1024{
0005baf4
FF		 1025 u32 val = ath9k_hw_mac_to_clks(ah, us);
1026 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1027 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1028}
1029
1030static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1031{
1032 u32 val = ath9k_hw_mac_to_clks(ah, us);
1033 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1034 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 1035}
f1dc5600 1036
cbe61d8a 1037static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1038{
f078f209 1039 if (tu > 0xFFFF) {
d2182b69
JP		 1040 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1041 tu);
2660b81a 1042 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1043 return false;
1044 } else {
1045 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1046 ah->globaltxtimeout = tu;
f078f209
LR		 1047 return true;
1048 }
1049}
1050
0005baf4 1051void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1052{
b6ba41bb
FF		 1053 struct ath_common *common = ath9k_hw_common(ah);
1054 struct ieee80211_conf *conf = &common->hw->conf;
1055 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 1056 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 1057 int slottime;
0005baf4 1058 int sifstime;
b6ba41bb
FF		 1059 int rx_lat = 0, tx_lat = 0, eifs = 0;
1060 u32 reg;
0005baf4 1061
d2182b69 1062 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1063 ah->misc_mode);
f078f209 1064
b6ba41bb
FF		 1065 if (!chan)
1066 return;
1067
2660b81a 1068 if (ah->misc_mode != 0)
ca7a4deb 1069 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1070
81a91d57
RM		 1071 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1072 rx_lat = 41;
1073 else
1074 rx_lat = 37;
b6ba41bb
FF		 1075 tx_lat = 54;
1076
e88e4861
FF		 1077 if (IS_CHAN_5GHZ(chan))
1078 sifstime = 16;
1079 else
1080 sifstime = 10;
1081
b6ba41bb
FF		 1082 if (IS_CHAN_HALF_RATE(chan)) {
1083 eifs = 175;
1084 rx_lat *= 2;
1085 tx_lat *= 2;
1086 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1087 tx_lat += 11;
1088
e88e4861 1089 sifstime *= 2;
e115b7ec 1090 ack_offset = 16;
b6ba41bb 1091 slottime = 13;
b6ba41bb
FF		 1092 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1093 eifs = 340;
81a91d57 1094 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1095 tx_lat *= 4;
1096 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1097 tx_lat += 22;
1098
e88e4861 1099 sifstime *= 4;
e115b7ec 1100 ack_offset = 32;
b6ba41bb 1101 slottime = 21;
b6ba41bb 1102 } else {
a7be039d
RM		 1103 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1104 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1105 reg = AR_USEC_ASYNC_FIFO;
1106 } else {
1107 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1108 common->clockrate;
1109 reg = REG_READ(ah, AR_USEC);
1110 }
b6ba41bb
FF		 1111 rx_lat = MS(reg, AR_USEC_RX_LAT);
1112 tx_lat = MS(reg, AR_USEC_TX_LAT);
1113
1114 slottime = ah->slottime;
b6ba41bb 1115 }
0005baf4 1116
e239d859 1117 /* As defined by IEEE 802.11-2007 17.3.8.6 */
e115b7ec 1118 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset;
adb5066a 1119 ctstimeout = acktimeout;
42c4568a
FF		 1120
1121 /*
1122 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1123 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1124 * This was initially only meant to work around an issue with delayed
1125 * BA frames in some implementations, but it has been found to fix ACK
1126 * timeout issues in other cases as well.
1127 */
e115b7ec
FF		 1128 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ &&
1129 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1130 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1131 ctstimeout += 48 - sifstime - ah->slottime;
1132 }
1133
42c4568a 1134
b6ba41bb
FF		 1135 ath9k_hw_set_sifs_time(ah, sifstime);
1136 ath9k_hw_setslottime(ah, slottime);
0005baf4 1137 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1138 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1139 if (ah->globaltxtimeout != (u32) -1)
1140 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1141
1142 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1143 REG_RMW(ah, AR_USEC,
1144 (common->clockrate - 1) |
1145 SM(rx_lat, AR_USEC_RX_LAT) |
1146 SM(tx_lat, AR_USEC_TX_LAT),
1147 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1148
f1dc5600 1149}
0005baf4 1150EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1151
285f2dda 1152void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1153{
211f5859
LR		 1154 struct ath_common *common = ath9k_hw_common(ah);
1155
736b3a27 1156 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 1157 goto free_hw;
1158
9ecdef4b 1159 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 1160
1161free_hw:
8fe65368 1162 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 1163}
285f2dda 1164EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1165
f1dc5600
S		 1166/*******/
1167/* INI */
1168/*******/
1169
8fe65368 1170u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1171{
1172 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1173
1174 if (IS_CHAN_B(chan))
1175 ctl |= CTL_11B;
1176 else if (IS_CHAN_G(chan))
1177 ctl |= CTL_11G;
1178 else
1179 ctl |= CTL_11A;
1180
1181 return ctl;
1182}
1183
f1dc5600
S		 1184/****************************************/
1185/* Reset and Channel Switching Routines */
1186/****************************************/
f1dc5600 1187
cbe61d8a 1188static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1189{
57b32227 1190 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 1191
7d0d0df0
S		 1192 ENABLE_REGWRITE_BUFFER(ah);
1193
d7e7d229
LR		 1194 /*
1195 * set AHB_MODE not to do cacheline prefetches
1196 */
ca7a4deb
FF		 1197 if (!AR_SREV_9300_20_OR_LATER(ah))
1198 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1199
d7e7d229
LR		 1200 /*
1201 * let mac dma reads be in 128 byte chunks
1202 */
ca7a4deb 1203 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1204
7d0d0df0 1205 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1206
d7e7d229
LR		 1207 /*
1208 * Restore TX Trigger Level to its pre-reset value.
1209 * The initial value depends on whether aggregation is enabled, and is
1210 * adjusted whenever underruns are detected.
1211 */
57b32227
FF		 1212 if (!AR_SREV_9300_20_OR_LATER(ah))
1213 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1214
7d0d0df0 1215 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1216
d7e7d229
LR		 1217 /*
1218 * let mac dma writes be in 128 byte chunks
1219 */
ca7a4deb 1220 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1221
d7e7d229
LR		 1222 /*
1223 * Setup receive FIFO threshold to hold off TX activities
1224 */
f1dc5600
S		 1225 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1226
57b32227
FF		 1227 if (AR_SREV_9300_20_OR_LATER(ah)) {
1228 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1229 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1230
1231 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1232 ah->caps.rx_status_len);
1233 }
1234
d7e7d229
LR		 1235 /*
1236 * reduce the number of usable entries in PCU TXBUF to avoid
1237 * wrap around issues.
1238 */
f1dc5600 1239 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1240 /* For AR9285 the number of Fifos are reduced to half.
1241 * So set the usable tx buf size also to half to
1242 * avoid data/delimiter underruns
1243 */
f1dc5600
S		 1244 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1245 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1246 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1247 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1248 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1249 }
744d4025 1250
7d0d0df0 1251 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1252
744d4025
VT		 1253 if (AR_SREV_9300_20_OR_LATER(ah))
1254 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1255}
1256
cbe61d8a 1257static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1258{
ca7a4deb
FF		 1259 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1260 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1261
f1dc5600 1262 switch (opmode) {
d97809db 1263 case NL80211_IFTYPE_ADHOC:
9cb5412b 1264 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb 1265 set |= AR_STA_ID1_ADHOC;
f1dc5600 1266 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1267 break;
ca7a4deb
FF		 1268 case NL80211_IFTYPE_AP:
1269 set |= AR_STA_ID1_STA_AP;
1270 /* fall through */
d97809db 1271 case NL80211_IFTYPE_STATION:
ca7a4deb 1272 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1273 break;
5f841b41 1274 default:
ca7a4deb
FF		 1275 if (!ah->is_monitoring)
1276 set = 0;
5f841b41 1277 break;
f1dc5600 1278 }
ca7a4deb 1279 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1280}
1281
8fe65368
LR		 1282void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1283 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1284{
1285 u32 coef_exp, coef_man;
1286
1287 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1288 if ((coef_scaled >> coef_exp) & 0x1)
1289 break;
1290
1291 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1292
1293 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1294
1295 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1296 *coef_exponent = coef_exp - 16;
1297}
1298
cbe61d8a 1299static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1300{
1301 u32 rst_flags;
1302 u32 tmpReg;
1303
70768496 1304 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1305 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1306 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1307 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1308 }
1309
7d0d0df0
S		 1310 ENABLE_REGWRITE_BUFFER(ah);
1311
9a658d2b
LR		 1312 if (AR_SREV_9300_20_OR_LATER(ah)) {
1313 REG_WRITE(ah, AR_WA, ah->WARegVal);
1314 udelay(10);
1315 }
1316
f1dc5600
S		 1317 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1318 AR_RTC_FORCE_WAKE_ON_INT);
1319
1320 if (AR_SREV_9100(ah)) {
1321 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1322 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1323 } else {
1324 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1325 if (tmpReg &
1326 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1327 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1328 u32 val;
f1dc5600 1329 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1330
1331 val = AR_RC_HOSTIF;
1332 if (!AR_SREV_9300_20_OR_LATER(ah))
1333 val |= AR_RC_AHB;
1334 REG_WRITE(ah, AR_RC, val);
1335
1336 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1337 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1338
1339 rst_flags = AR_RTC_RC_MAC_WARM;
1340 if (type == ATH9K_RESET_COLD)
1341 rst_flags |= AR_RTC_RC_MAC_COLD;
1342 }
1343
7d95847c
GJ		 1344 if (AR_SREV_9330(ah)) {
1345 int npend = 0;
1346 int i;
1347
1348 /* AR9330 WAR:
1349 * call external reset function to reset WMAC if:
1350 * - doing a cold reset
1351 * - we have pending frames in the TX queues
1352 */
1353
1354 for (i = 0; i < AR_NUM_QCU; i++) {
1355 npend = ath9k_hw_numtxpending(ah, i);
1356 if (npend)
1357 break;
1358 }
1359
1360 if (ah->external_reset &&
1361 (npend || type == ATH9K_RESET_COLD)) {
1362 int reset_err = 0;
1363
d2182b69 1364 ath_dbg(ath9k_hw_common(ah), RESET,
7d95847c
GJ		 1365 "reset MAC via external reset\n");
1366
1367 reset_err = ah->external_reset();
1368 if (reset_err) {
1369 ath_err(ath9k_hw_common(ah),
1370 "External reset failed, err=%d\n",
1371 reset_err);
1372 return false;
1373 }
1374
1375 REG_WRITE(ah, AR_RTC_RESET, 1);
1376 }
1377 }
1378
3863495b 1379 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1380 ar9003_mci_check_gpm_offset(ah);
3863495b 1381
d03a66c1 1382 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1383
1384 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1385
f1dc5600
S		 1386 udelay(50);
1387
d03a66c1 1388 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1389 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1390 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1391 return false;
1392 }
1393
1394 if (!AR_SREV_9100(ah))
1395 REG_WRITE(ah, AR_RC, 0);
1396
f1dc5600
S		 1397 if (AR_SREV_9100(ah))
1398 udelay(50);
1399
1400 return true;
1401}
1402
cbe61d8a 1403static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1404{
7d0d0df0
S		 1405 ENABLE_REGWRITE_BUFFER(ah);
1406
9a658d2b
LR		 1407 if (AR_SREV_9300_20_OR_LATER(ah)) {
1408 REG_WRITE(ah, AR_WA, ah->WARegVal);
1409 udelay(10);
1410 }
1411
f1dc5600
S		 1412 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1413 AR_RTC_FORCE_WAKE_ON_INT);
1414
42d5bc3f 1415 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1416 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1417
d03a66c1 1418 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1419
7d0d0df0 1420 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1421
84e2169b
SB		 1422 if (!AR_SREV_9300_20_OR_LATER(ah))
1423 udelay(2);
1424
1425 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1426 REG_WRITE(ah, AR_RC, 0);
1427
d03a66c1 1428 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1429
1430 if (!ath9k_hw_wait(ah,
1431 AR_RTC_STATUS,
1432 AR_RTC_STATUS_M,
0caa7b14
S		 1433 AR_RTC_STATUS_ON,
1434 AH_WAIT_TIMEOUT)) {
d2182b69 1435 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1436 return false;
f078f209
LR		 1437 }
1438
f1dc5600
S		 1439 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1440}
1441
cbe61d8a 1442static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1443{
7a9233ff 1444 bool ret = false;
2577c6e8 1445
9a658d2b
LR		 1446 if (AR_SREV_9300_20_OR_LATER(ah)) {
1447 REG_WRITE(ah, AR_WA, ah->WARegVal);
1448 udelay(10);
1449 }
1450
f1dc5600
S		 1451 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1452 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1453
1454 switch (type) {
1455 case ATH9K_RESET_POWER_ON:
7a9233ff
MSS		 1456 ret = ath9k_hw_set_reset_power_on(ah);
1457 break;
f1dc5600
S		 1458 case ATH9K_RESET_WARM:
1459 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1460 ret = ath9k_hw_set_reset(ah, type);
1461 break;
f1dc5600 1462 default:
7a9233ff 1463 break;
f1dc5600 1464 }
7a9233ff 1465
7a9233ff 1466 return ret;
f078f209
LR		 1467}
1468
cbe61d8a 1469static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1470 struct ath9k_channel *chan)
f078f209 1471{
9c083af8
FF		 1472 int reset_type = ATH9K_RESET_WARM;
1473
1474 if (AR_SREV_9280(ah)) {
1475 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1476 reset_type = ATH9K_RESET_POWER_ON;
1477 else
1478 reset_type = ATH9K_RESET_COLD;
1479 }
1480
1481 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1482 return false;
f078f209 1483
9ecdef4b 1484 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1485 return false;
f078f209 1486
2660b81a 1487 ah->chip_fullsleep = false;
bfc441a4
FF		 1488
1489 if (AR_SREV_9330(ah))
1490 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1491 ath9k_hw_init_pll(ah, chan);
f1dc5600 1492 ath9k_hw_set_rfmode(ah, chan);
f078f209 1493
f1dc5600 1494 return true;
f078f209
LR		 1495}
1496
cbe61d8a 1497static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1498 struct ath9k_channel *chan)
f078f209 1499{
c46917bb 1500 struct ath_common *common = ath9k_hw_common(ah);
8fe65368 1501 u32 qnum;
0a3b7bac 1502 int r;
5f0c04ea
RM		 1503 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1504 bool band_switch, mode_diff;
1505 u8 ini_reloaded;
1506
1507 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1508 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1509 CHANNEL_5GHZ));
1510 mode_diff = (chan->chanmode != ah->curchan->chanmode);
f078f209
LR		 1511
1512 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1513 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1514 ath_dbg(common, QUEUE,
226afe68 1515 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1516 return false;
1517 }
1518 }
1519
8fe65368 1520 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1521 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1522 return false;
1523 }
1524
5f0c04ea
RM		 1525 if (edma && (band_switch || mode_diff)) {
1526 ath9k_hw_mark_phy_inactive(ah);
1527 udelay(5);
1528
1529 ath9k_hw_init_pll(ah, NULL);
1530
1531 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1532 ath_err(common, "Failed to do fast channel change\n");
1533 return false;
1534 }
1535 }
1536
8fe65368 1537 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1538
8fe65368 1539 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1540 if (r) {
3800276a 1541 ath_err(common, "Failed to set channel\n");
0a3b7bac 1542 return false;
f078f209 1543 }
dfdac8ac 1544 ath9k_hw_set_clockrate(ah);
64ea57d0 1545 ath9k_hw_apply_txpower(ah, chan, false);
8fe65368 1546 ath9k_hw_rfbus_done(ah);
f078f209 1547
f1dc5600
S		 1548 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1549 ath9k_hw_set_delta_slope(ah, chan);
1550
8fe65368 1551 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1552
5f0c04ea 1553 if (edma && (band_switch || mode_diff)) {
a126ff51 1554 ah->ah_flags |= AH_FASTCC;
5f0c04ea
RM		 1555 if (band_switch || ini_reloaded)
1556 ah->eep_ops->set_board_values(ah, chan);
1557
1558 ath9k_hw_init_bb(ah, chan);
1559
1560 if (band_switch || ini_reloaded)
1561 ath9k_hw_init_cal(ah, chan);
a126ff51 1562 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1563 }
1564
f1dc5600
S		 1565 return true;
1566}
1567
691680b8
FF		 1568static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1569{
1570 u32 gpio_mask = ah->gpio_mask;
1571 int i;
1572
1573 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1574 if (!(gpio_mask & 1))
1575 continue;
1576
1577 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1578 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1579 }
1580}
1581
01e18918
RM		 1582static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1583 int *hang_state, int *hang_pos)
1584{
1585 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1586 u32 chain_state, dcs_pos, i;
1587
1588 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1589 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1590 for (i = 0; i < 3; i++) {
1591 if (chain_state == dcu_chain_state[i]) {
1592 *hang_state = chain_state;
1593 *hang_pos = dcs_pos;
1594 return true;
1595 }
1596 }
1597 }
1598 return false;
1599}
1600
1601#define DCU_COMPLETE_STATE 1
1602#define DCU_COMPLETE_STATE_MASK 0x3
1603#define NUM_STATUS_READS 50
1604static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1605{
1606 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1607 u32 i, hang_pos, hang_state, num_state = 6;
1608
1609 comp_state = REG_READ(ah, AR_DMADBG_6);
1610
1611 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1612 ath_dbg(ath9k_hw_common(ah), RESET,
1613 "MAC Hang signature not found at DCU complete\n");
1614 return false;
1615 }
1616
1617 chain_state = REG_READ(ah, dcs_reg);
1618 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1619 goto hang_check_iter;
1620
1621 dcs_reg = AR_DMADBG_5;
1622 num_state = 4;
1623 chain_state = REG_READ(ah, dcs_reg);
1624 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1625 goto hang_check_iter;
1626
1627 ath_dbg(ath9k_hw_common(ah), RESET,
1628 "MAC Hang signature 1 not found\n");
1629 return false;
1630
1631hang_check_iter:
1632 ath_dbg(ath9k_hw_common(ah), RESET,
1633 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1634 chain_state, comp_state, hang_state, hang_pos);
1635
1636 for (i = 0; i < NUM_STATUS_READS; i++) {
1637 chain_state = REG_READ(ah, dcs_reg);
1638 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1639 comp_state = REG_READ(ah, AR_DMADBG_6);
1640
1641 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1642 DCU_COMPLETE_STATE) ||
1643 (chain_state != hang_state))
1644 return false;
1645 }
1646
1647 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1648
1649 return true;
1650}
1651
c9c99e5e 1652bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1653{
c9c99e5e
FF		 1654 int count = 50;
1655 u32 reg;
1656
01e18918
RM		 1657 if (AR_SREV_9300(ah))
1658 return !ath9k_hw_detect_mac_hang(ah);
1659
e17f83ea 1660 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1661 return true;
1662
1663 do {
1664 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1665
c9c99e5e
FF		 1666 if ((reg & 0x7E7FFFEF) == 0x00702400)
1667 continue;
1668
1669 switch (reg & 0x7E000B00) {
1670 case 0x1E000000:
1671 case 0x52000B00:
1672 case 0x18000B00:
1673 continue;
1674 default:
1675 return true;
1676 }
1677 } while (count-- > 0);
3b319aae 1678
c9c99e5e 1679 return false;
3b319aae 1680}
c9c99e5e 1681EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1682
caed6579
SM		 1683/*
1684 * Fast channel change:
1685 * (Change synthesizer based on channel freq without resetting chip)
1686 *
1687 * Don't do FCC when
1688 * - Flag is not set
1689 * - Chip is just coming out of full sleep
1690 * - Channel to be set is same as current channel
1691 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1692 */
1693static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1694{
1695 struct ath_common *common = ath9k_hw_common(ah);
1696 int ret;
1697
1698 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1699 goto fail;
1700
1701 if (ah->chip_fullsleep)
1702 goto fail;
1703
1704 if (!ah->curchan)
1705 goto fail;
1706
1707 if (chan->channel == ah->curchan->channel)
1708 goto fail;
1709
feb7bc99
FF		 1710 if ((ah->curchan->channelFlags | chan->channelFlags) &
1711 (CHANNEL_HALF | CHANNEL_QUARTER))
1712 goto fail;
1713
caed6579
SM		 1714 if ((chan->channelFlags & CHANNEL_ALL) !=
1715 (ah->curchan->channelFlags & CHANNEL_ALL))
1716 goto fail;
1717
1718 if (!ath9k_hw_check_alive(ah))
1719 goto fail;
1720
1721 /*
1722 * For AR9462, make sure that calibration data for
1723 * re-using are present.
1724 */
8a90555f
SM		 1725 if (AR_SREV_9462(ah) && (ah->caldata &&
1726 (!ah->caldata->done_txiqcal_once ||
1727 !ah->caldata->done_txclcal_once ||
1728 !ah->caldata->rtt_done)))
caed6579
SM		 1729 goto fail;
1730
1731 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1732 ah->curchan->channel, chan->channel);
1733
1734 ret = ath9k_hw_channel_change(ah, chan);
1735 if (!ret)
1736 goto fail;
1737
1738 ath9k_hw_loadnf(ah, ah->curchan);
1739 ath9k_hw_start_nfcal(ah, true);
1740
5955b2b0 1741 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1742 ar9003_mci_2g5g_switch(ah, false);
caed6579
SM		 1743
1744 if (AR_SREV_9271(ah))
1745 ar9002_hw_load_ani_reg(ah, chan);
1746
1747 return 0;
1748fail:
1749 return -EINVAL;
1750}
1751
cbe61d8a 1752int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1753 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1754{
1510718d 1755 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1756 u32 saveLedState;
f078f209
LR		 1757 u32 saveDefAntenna;
1758 u32 macStaId1;
46fe782c 1759 u64 tsf = 0;
8fe65368 1760 int i, r;
caed6579 1761 bool start_mci_reset = false;
63d32967
MSS		 1762 bool save_fullsleep = ah->chip_fullsleep;
1763
5955b2b0 1764 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1765 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1766 if (start_mci_reset)
1767 return 0;
63d32967
MSS		 1768 }
1769
9ecdef4b 1770 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1771 return -EIO;
f078f209 1772
caed6579
SM		 1773 if (ah->curchan && !ah->chip_fullsleep)
1774 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1775
20bd2a09
FF		 1776 ah->caldata = caldata;
1777 if (caldata &&
1778 (chan->channel != caldata->channel ||
1779 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1780 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1781 /* Operating channel changed, reset channel calibration data */
1782 memset(caldata, 0, sizeof(*caldata));
1783 ath9k_init_nfcal_hist_buffer(ah, chan);
1784 }
f23fba49 1785 ah->noise = ath9k_hw_getchan_noise(ah, chan);
20bd2a09 1786
caed6579
SM		 1787 if (fastcc) {
1788 r = ath9k_hw_do_fastcc(ah, chan);
1789 if (!r)
1790 return r;
f078f209
LR		 1791 }
1792
5955b2b0 1793 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1794 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1795
f078f209
LR		 1796 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1797 if (saveDefAntenna == 0)
1798 saveDefAntenna = 1;
1799
1800 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1801
46fe782c 1802 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1803 if (AR_SREV_9100(ah) ||
1804 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1805 tsf = ath9k_hw_gettsf64(ah);
1806
f078f209
LR		 1807 saveLedState = REG_READ(ah, AR_CFG_LED) &
1808 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1809 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1810
1811 ath9k_hw_mark_phy_inactive(ah);
1812
45ef6a0b
VT		 1813 ah->paprd_table_write_done = false;
1814
05020d23 1815 /* Only required on the first reset */
d7e7d229
LR		 1816 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1817 REG_WRITE(ah,
1818 AR9271_RESET_POWER_DOWN_CONTROL,
1819 AR9271_RADIO_RF_RST);
1820 udelay(50);
1821 }
1822
f078f209 1823 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1824 ath_err(common, "Chip reset failed\n");
ae8d2858 1825 return -EINVAL;
f078f209
LR		 1826 }
1827
05020d23 1828 /* Only required on the first reset */
d7e7d229
LR		 1829 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1830 ah->htc_reset_init = false;
1831 REG_WRITE(ah,
1832 AR9271_RESET_POWER_DOWN_CONTROL,
1833 AR9271_GATE_MAC_CTL);
1834 udelay(50);
1835 }
1836
46fe782c 1837 /* Restore TSF */
f860d526 1838 if (tsf)
46fe782c
S		 1839 ath9k_hw_settsf64(ah, tsf);
1840
7a37081e 1841 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1842 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1843
e9141f71
S		 1844 if (!AR_SREV_9300_20_OR_LATER(ah))
1845 ar9002_hw_enable_async_fifo(ah);
1846
25c56eec 1847 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1848 if (r)
1849 return r;
f078f209 1850
5955b2b0 1851 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1852 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1853
f860d526
FF		 1854 /*
1855 * Some AR91xx SoC devices frequently fail to accept TSF writes
1856 * right after the chip reset. When that happens, write a new
1857 * value after the initvals have been applied, with an offset
1858 * based on measured time difference
1859 */
1860 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1861 tsf += 1500;
1862 ath9k_hw_settsf64(ah, tsf);
1863 }
1864
0ced0e17
JM		 1865 /* Setup MFP options for CCMP */
1866 if (AR_SREV_9280_20_OR_LATER(ah)) {
1867 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1868 * frames when constructing CCMP AAD. */
1869 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1870 0xc7ff);
1871 ah->sw_mgmt_crypto = false;
1872 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1873 /* Disable hardware crypto for management frames */
1874 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1875 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1876 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1877 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1878 ah->sw_mgmt_crypto = true;
1879 } else
1880 ah->sw_mgmt_crypto = true;
1881
f078f209
LR		 1882 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1883 ath9k_hw_set_delta_slope(ah, chan);
1884
8fe65368 1885 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1886 ah->eep_ops->set_board_values(ah, chan);
a7765828 1887
7d0d0df0
S		 1888 ENABLE_REGWRITE_BUFFER(ah);
1889
1510718d
LR		 1890 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1891 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1892 | macStaId1
1893 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1894 | (ah->config.
60b67f51 1895 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1896 | ah->sta_id1_defaults);
13b81559 1897 ath_hw_setbssidmask(common);
f078f209 1898 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1899 ath9k_hw_write_associd(ah);
f078f209 1900 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1901 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1902
7d0d0df0 1903 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1904
00e0003e
SM		 1905 ath9k_hw_set_operating_mode(ah, ah->opmode);
1906
8fe65368 1907 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1908 if (r)
1909 return r;
f078f209 1910
dfdac8ac
FF		 1911 ath9k_hw_set_clockrate(ah);
1912
7d0d0df0
S		 1913 ENABLE_REGWRITE_BUFFER(ah);
1914
f078f209
LR		 1915 for (i = 0; i < AR_NUM_DCU; i++)
1916 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1917
7d0d0df0 1918 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1919
2660b81a 1920 ah->intr_txqs = 0;
f4c607dc 1921 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
f078f209
LR		 1922 ath9k_hw_resettxqueue(ah, i);
1923
2660b81a 1924 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1925 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1926 ath9k_hw_init_qos(ah);
1927
2660b81a 1928 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1929 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1930
0005baf4 1931 ath9k_hw_init_global_settings(ah);
f078f209 1932
fe2b6afb
FF		 1933 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1934 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1935 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1936 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1937 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1938 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1939 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1940 }
1941
ca7a4deb 1942 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1943
1944 ath9k_hw_set_dma(ah);
1945
ed6ebd8b
RM		 1946 if (!ath9k_hw_mci_is_enabled(ah))
1947 REG_WRITE(ah, AR_OBS, 8);
f078f209 1948
0ce024cb 1949 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1950 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1951 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1952 }
1953
7f62a136
VT		 1954 if (ah->config.tx_intr_mitigation) {
1955 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1956 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1957 }
1958
f078f209
LR		 1959 ath9k_hw_init_bb(ah, chan);
1960
77a5a664 1961 if (caldata) {
5f0c04ea 1962 caldata->done_txiqcal_once = false;
77a5a664
RM		 1963 caldata->done_txclcal_once = false;
1964 }
ae8d2858 1965 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1966 return -EIO;
f078f209 1967
5955b2b0 1968 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 1969 return -EIO;
63d32967 1970
7d0d0df0 1971 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1972
8fe65368 1973 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1974 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1975
7d0d0df0 1976 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1977
d7e7d229
LR		 1978 /*
1979 * For big endian systems turn on swapping for descriptors
1980 */
f078f209
LR		 1981 if (AR_SREV_9100(ah)) {
1982 u32 mask;
1983 mask = REG_READ(ah, AR_CFG);
1984 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
d2182b69
JP		 1985 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1986 mask);
f078f209
LR		 1987 } else {
1988 mask =
1989 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1990 REG_WRITE(ah, AR_CFG, mask);
d2182b69
JP		 1991 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1992 REG_READ(ah, AR_CFG));
f078f209
LR		 1993 }
1994 } else {
cbba8cd1
S		 1995 if (common->bus_ops->ath_bus_type == ATH_USB) {
1996 /* Configure AR9271 target WLAN */
1997 if (AR_SREV_9271(ah))
1998 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1999 else
2000 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2001 }
f078f209 2002#ifdef __BIG_ENDIAN
2f8d10fd
GJ		 2003 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
2004 AR_SREV_9550(ah))
2be7bfe0
VT		 2005 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
2006 else
d7e7d229 2007 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 2008#endif
2009 }
2010
dbccdd1d 2011 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 2012 ath9k_hw_btcoex_enable(ah);
2013
5955b2b0 2014 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 2015 ar9003_mci_check_bt(ah);
63d32967 2016
1fe860ed
RM		 2017 ath9k_hw_loadnf(ah, chan);
2018 ath9k_hw_start_nfcal(ah, true);
2019
51ac8cbb 2020 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 2021 ar9003_hw_bb_watchdog_config(ah);
d8903a53 2022
51ac8cbb
RM		 2023 ar9003_hw_disable_phy_restart(ah);
2024 }
2025
691680b8
FF		 2026 ath9k_hw_apply_gpio_override(ah);
2027
ae8d2858 2028 return 0;
f078f209 2029}
7322fd19 2030EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2031
f1dc5600
S		 2032/******************************/
2033/* Power Management (Chipset) */
2034/******************************/
2035
42d5bc3f
LR		 2036/*
2037 * Notify Power Mgt is disabled in self-generated frames.
2038 * If requested, force chip to sleep.
2039 */
31604cf0 2040static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 2041{
f1dc5600 2042 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 2043
31604cf0 2044 if (AR_SREV_9462(ah)) {
153dccd4
RM		 2045 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2046 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2047 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 2048 /* xxx Required for WLAN only case ? */
2049 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2050 udelay(100);
2051 }
2577c6e8 2052
31604cf0
SM		 2053 /*
2054 * Clear the RTC force wake bit to allow the
2055 * mac to go to sleep.
2056 */
2057 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2058
153dccd4 2059 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2060 udelay(100);
2577c6e8 2061
31604cf0
SM		 2062 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2063 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2064
31604cf0
SM		 2065 /* Shutdown chip. Active low */
2066 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2067 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2068 udelay(2);
f1dc5600 2069 }
9a658d2b
LR		 2070
2071 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2072 if (AR_SREV_9300_20_OR_LATER(ah))
2073 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2074}
2075
bbd79af5
LR		 2076/*
2077 * Notify Power Management is enabled in self-generating
2078 * frames. If request, set power mode of chip to
2079 * auto/normal. Duration in units of 128us (1/8 TU).
2080 */
31604cf0 2081static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2082{
31604cf0 2083 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2084
f1dc5600 2085 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2086
31604cf0
SM		 2087 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2088 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2089 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2090 AR_RTC_FORCE_WAKE_ON_INT);
2091 } else {
2577c6e8 2092
31604cf0
SM		 2093 /* When chip goes into network sleep, it could be waken
2094 * up by MCI_INT interrupt caused by BT's HW messages
2095 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2096 * rate (~100us). This will cause chip to leave and
2097 * re-enter network sleep mode frequently, which in
2098 * consequence will have WLAN MCI HW to generate lots of
2099 * SYS_WAKING and SYS_SLEEPING messages which will make
2100 * BT CPU to busy to process.
2101 */
153dccd4
RM		 2102 if (ath9k_hw_mci_is_enabled(ah))
2103 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2104 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2105 /*
2106 * Clear the RTC force wake bit to allow the
2107 * mac to go to sleep.
2108 */
153dccd4 2109 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2110
153dccd4 2111 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2112 udelay(30);
f078f209 2113 }
9a658d2b
LR		 2114
2115 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2116 if (AR_SREV_9300_20_OR_LATER(ah))
2117 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2118}
2119
31604cf0 2120static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2121{
f1dc5600
S		 2122 u32 val;
2123 int i;
f078f209 2124
9a658d2b
LR		 2125 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2126 if (AR_SREV_9300_20_OR_LATER(ah)) {
2127 REG_WRITE(ah, AR_WA, ah->WARegVal);
2128 udelay(10);
2129 }
2130
31604cf0
SM		 2131 if ((REG_READ(ah, AR_RTC_STATUS) &
2132 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2133 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2134 return false;
f1dc5600 2135 }
31604cf0
SM		 2136 if (!AR_SREV_9300_20_OR_LATER(ah))
2137 ath9k_hw_init_pll(ah, NULL);
2138 }
2139 if (AR_SREV_9100(ah))
2140 REG_SET_BIT(ah, AR_RTC_RESET,
2141 AR_RTC_RESET_EN);
2142
2143 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2144 AR_RTC_FORCE_WAKE_EN);
2145 udelay(50);
f078f209 2146
9dd9b0dc
RM		 2147 if (ath9k_hw_mci_is_enabled(ah))
2148 ar9003_mci_set_power_awake(ah);
2149
31604cf0
SM		 2150 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2151 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2152 if (val == AR_RTC_STATUS_ON)
2153 break;
2154 udelay(50);
f1dc5600
S		 2155 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2156 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2157 }
2158 if (i == 0) {
2159 ath_err(ath9k_hw_common(ah),
2160 "Failed to wakeup in %uus\n",
2161 POWER_UP_TIME / 20);
2162 return false;
f078f209
LR		 2163 }
2164
f1dc5600 2165 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2166
f1dc5600 2167 return true;
f078f209
LR		 2168}
2169
9ecdef4b 2170bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2171{
c46917bb 2172 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2173 int status = true;
f1dc5600
S		 2174 static const char *modes[] = {
2175 "AWAKE",
2176 "FULL-SLEEP",
2177 "NETWORK SLEEP",
2178 "UNDEFINED"
2179 };
f1dc5600 2180
cbdec975
GJ		 2181 if (ah->power_mode == mode)
2182 return status;
2183
d2182b69 2184 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2185 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2186
2187 switch (mode) {
2188 case ATH9K_PM_AWAKE:
31604cf0 2189 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2190 break;
2191 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2192 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2193 ar9003_mci_set_full_sleep(ah);
1010911e 2194
31604cf0 2195 ath9k_set_power_sleep(ah);
2660b81a 2196 ah->chip_fullsleep = true;
f1dc5600
S		 2197 break;
2198 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2199 ath9k_set_power_network_sleep(ah);
f1dc5600 2200 break;
f078f209 2201 default:
3800276a 2202 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2203 return false;
2204 }
2660b81a 2205 ah->power_mode = mode;
f1dc5600 2206
69f4aab1
LR		 2207 /*
2208 * XXX: If this warning never comes up after a while then
2209 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2210 * ath9k_hw_setpower() return type void.
2211 */
97dcec57
SM		 2212
2213 if (!(ah->ah_flags & AH_UNPLUGGED))
2214 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2215
f1dc5600 2216 return status;
f078f209 2217}
7322fd19 2218EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2219
f1dc5600
S		 2220/*******************/
2221/* Beacon Handling */
2222/*******************/
2223
cbe61d8a 2224void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2225{
f078f209
LR		 2226 int flags = 0;
2227
7d0d0df0
S		 2228 ENABLE_REGWRITE_BUFFER(ah);
2229
2660b81a 2230 switch (ah->opmode) {
d97809db 2231 case NL80211_IFTYPE_ADHOC:
9cb5412b 2232 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 2233 REG_SET_BIT(ah, AR_TXCFG,
2234 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
dd347f2f
FF		 2235 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2236 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
f078f209 2237 flags |= AR_NDP_TIMER_EN;
d97809db 2238 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2239 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2240 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2241 TU_TO_USEC(ah->config.dma_beacon_response_time));
2242 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2243 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2244 flags |=
2245 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2246 break;
d97809db 2247 default:
d2182b69
JP		 2248 ath_dbg(ath9k_hw_common(ah), BEACON,
2249 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2250 return;
2251 break;
f078f209
LR		 2252 }
2253
dd347f2f
FF		 2254 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2255 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2256 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2257 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
f078f209 2258
7d0d0df0 2259 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2260
f078f209
LR		 2261 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2262}
7322fd19 2263EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2264
cbe61d8a 2265void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2266 const struct ath9k_beacon_state *bs)
f078f209
LR		 2267{
2268 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2269 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2270 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2271
7d0d0df0
S		 2272 ENABLE_REGWRITE_BUFFER(ah);
2273
f078f209
LR		 2274 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2275
2276 REG_WRITE(ah, AR_BEACON_PERIOD,
f29f5c08 2277 TU_TO_USEC(bs->bs_intval));
f078f209 2278 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
f29f5c08 2279 TU_TO_USEC(bs->bs_intval));
f078f209 2280
7d0d0df0 2281 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2282
f078f209
LR		 2283 REG_RMW_FIELD(ah, AR_RSSI_THR,
2284 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2285
f29f5c08 2286 beaconintval = bs->bs_intval;
f078f209
LR		 2287
2288 if (bs->bs_sleepduration > beaconintval)
2289 beaconintval = bs->bs_sleepduration;
2290
2291 dtimperiod = bs->bs_dtimperiod;
2292 if (bs->bs_sleepduration > dtimperiod)
2293 dtimperiod = bs->bs_sleepduration;
2294
2295 if (beaconintval == dtimperiod)
2296 nextTbtt = bs->bs_nextdtim;
2297 else
2298 nextTbtt = bs->bs_nexttbtt;
2299
d2182b69
JP		 2300 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2301 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2302 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2303 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2304
7d0d0df0
S		 2305 ENABLE_REGWRITE_BUFFER(ah);
2306
f1dc5600
S		 2307 REG_WRITE(ah, AR_NEXT_DTIM,
2308 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2309 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 2310
f1dc5600
S		 2311 REG_WRITE(ah, AR_SLEEP1,
2312 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2313 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2314
f1dc5600
S		 2315 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2316 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2317 else
2318 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2319
f1dc5600
S		 2320 REG_WRITE(ah, AR_SLEEP2,
2321 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2322
f1dc5600
S		 2323 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2324 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2325
7d0d0df0 2326 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2327
f1dc5600
S		 2328 REG_SET_BIT(ah, AR_TIMER_MODE,
2329 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2330 AR_DTIM_TIMER_EN);
f078f209 2331
4af9cf4f
S		 2332 /* TSF Out of Range Threshold */
2333 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2334}
7322fd19 2335EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2336
f1dc5600
S		 2337/*******************/
2338/* HW Capabilities */
2339/*******************/
2340
6054069a
FF		 2341static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2342{
2343 eeprom_chainmask &= chip_chainmask;
2344 if (eeprom_chainmask)
2345 return eeprom_chainmask;
2346 else
2347 return chip_chainmask;
2348}
2349
9a66af33
ZK		 2350/**
2351 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2352 * @ah: the atheros hardware data structure
2353 *
2354 * We enable DFS support upstream on chipsets which have passed a series
2355 * of tests. The testing requirements are going to be documented. Desired
2356 * test requirements are documented at:
2357 *
2358 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2359 *
2360 * Once a new chipset gets properly tested an individual commit can be used
2361 * to document the testing for DFS for that chipset.
2362 */
2363static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2364{
2365
2366 switch (ah->hw_version.macVersion) {
2367 /* AR9580 will likely be our first target to get testing on */
2368 case AR_SREV_VERSION_9580:
2369 default:
2370 return false;
2371 }
2372}
2373
a9a29ce6 2374int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2375{
2660b81a 2376 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2377 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2378 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2379 unsigned int chip_chainmask;
608b88cb 2380
0ff2b5c0 2381 u16 eeval;
47c80de6 2382 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2383
f74df6fb 2384 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2385 regulatory->current_rd = eeval;
f078f209 2386
2660b81a 2387 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2388 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2389 if (regulatory->current_rd == 0x64 ||
2390 regulatory->current_rd == 0x65)
2391 regulatory->current_rd += 5;
2392 else if (regulatory->current_rd == 0x41)
2393 regulatory->current_rd = 0x43;
d2182b69
JP		 2394 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2395 regulatory->current_rd);
f1dc5600 2396 }
f078f209 2397
f74df6fb 2398 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2399 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2400 ath_err(common,
2401 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2402 return -EINVAL;
2403 }
2404
d4659912
FF		 2405 if (eeval & AR5416_OPFLAGS_11A)
2406 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2407
d4659912
FF		 2408 if (eeval & AR5416_OPFLAGS_11G)
2409 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2410
6054069a
FF		 2411 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2412 chip_chainmask = 1;
ba5736a5
MSS		 2413 else if (AR_SREV_9462(ah))
2414 chip_chainmask = 3;
6054069a
FF		 2415 else if (!AR_SREV_9280_20_OR_LATER(ah))
2416 chip_chainmask = 7;
2417 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2418 chip_chainmask = 3;
2419 else
2420 chip_chainmask = 7;
2421
f74df6fb 2422 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2423 /*
2424 * For AR9271 we will temporarilly uses the rx chainmax as read from
2425 * the EEPROM.
2426 */
8147f5de 2427 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2428 !(eeval & AR5416_OPFLAGS_11A) &&
2429 !(AR_SREV_9271(ah)))
2430 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2431 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2432 else if (AR_SREV_9100(ah))
2433 pCap->rx_chainmask = 0x7;
8147f5de 2434 else
d7e7d229 2435 /* Use rx_chainmask from EEPROM. */
8147f5de 2436 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2437
6054069a
FF		 2438 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2439 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2440 ah->txchainmask = pCap->tx_chainmask;
2441 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2442
7a37081e 2443 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2444
02d2ebb2
FF		 2445 /* enable key search for every frame in an aggregate */
2446 if (AR_SREV_9300_20_OR_LATER(ah))
2447 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2448
ce2220d1
BR		 2449 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2450
0db156e9 2451 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2452 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2453 else
2454 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2455
5b5fa355
S		 2456 if (AR_SREV_9271(ah))
2457 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2458 else if (AR_DEVID_7010(ah))
2459 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2460 else if (AR_SREV_9300_20_OR_LATER(ah))
2461 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2462 else if (AR_SREV_9287_11_OR_LATER(ah))
2463 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2464 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2465 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2466 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2467 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2468 else
2469 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2470
1b2538b2 2471 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2472 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2473 else
f1dc5600 2474 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2475
e97275cb 2476#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2477 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2478 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2479 ah->rfkill_gpio =
2480 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2481 ah->rfkill_polarity =
2482 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2483
2484 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2485 }
f1dc5600 2486#endif
d5d1154f 2487 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2488 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2489 else
2490 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2491
e7594072 2492 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2493 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2494 else
2495 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2496
ceb26445 2497 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2498 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
0e707a94 2499 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
784ad503
VT		 2500 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2501
ceb26445
VT		 2502 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2503 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2504 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2505 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2506 pCap->txs_len = sizeof(struct ar9003_txs);
6f481010
LR		 2507 if (!ah->config.paprd_disable &&
2508 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
4935250a 2509 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 2510 } else {
2511 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2512 if (AR_SREV_9280_20(ah))
6b42e8d0 2513 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2514 }
1adf02ff 2515
6c84ce08
VT		 2516 if (AR_SREV_9300_20_OR_LATER(ah))
2517 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2518
6ee63f55
SB		 2519 if (AR_SREV_9300_20_OR_LATER(ah))
2520 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2521
a42acef0 2522 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2523 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2524
754dc536
VT		 2525 if (AR_SREV_9285(ah))
2526 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2527 ant_div_ctl1 =
2528 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2529 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2530 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2531 }
ea066d5a
MSS		 2532 if (AR_SREV_9300_20_OR_LATER(ah)) {
2533 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2534 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2535 }
2536
2537
431da56a 2538 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
21d2c63a
MSS		 2539 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2540 /*
2541 * enable the diversity-combining algorithm only when
2542 * both enable_lna_div and enable_fast_div are set
2543 * Table for Diversity
2544 * ant_div_alt_lnaconf bit 0-1
2545 * ant_div_main_lnaconf bit 2-3
2546 * ant_div_alt_gaintb bit 4
2547 * ant_div_main_gaintb bit 5
2548 * enable_ant_div_lnadiv bit 6
2549 * enable_ant_fast_div bit 7
2550 */
2551 if ((ant_div_ctl1 >> 0x6) == 0x3)
2552 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2553 }
754dc536 2554
8060e169
VT		 2555 if (AR_SREV_9485_10(ah)) {
2556 pCap->pcie_lcr_extsync_en = true;
2557 pCap->pcie_lcr_offset = 0x80;
2558 }
2559
9a66af33
ZK		 2560 if (ath9k_hw_dfs_tested(ah))
2561 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2562
47c80de6
VT		 2563 tx_chainmask = pCap->tx_chainmask;
2564 rx_chainmask = pCap->rx_chainmask;
2565 while (tx_chainmask || rx_chainmask) {
2566 if (tx_chainmask & BIT(0))
2567 pCap->max_txchains++;
2568 if (rx_chainmask & BIT(0))
2569 pCap->max_rxchains++;
2570
2571 tx_chainmask >>= 1;
2572 rx_chainmask >>= 1;
2573 }
2574
8ad74c4d
RM		 2575 if (AR_SREV_9300_20_OR_LATER(ah)) {
2576 ah->enabled_cals |= TX_IQ_CAL;
6fea593d 2577 if (AR_SREV_9485_OR_LATER(ah))
8ad74c4d
RM		 2578 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2579 }
3789d59c
MSS		 2580
2581 if (AR_SREV_9462(ah)) {
2582
2583 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2584 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2585
2586 if (AR_SREV_9462_20(ah))
2587 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2588
2589 }
2590
324c74ad 2591
a9a29ce6 2592 return 0;
f078f209
LR		 2593}
2594
f1dc5600
S		 2595/****************************/
2596/* GPIO / RFKILL / Antennae */
2597/****************************/
f078f209 2598
cbe61d8a 2599static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2600 u32 gpio, u32 type)
2601{
2602 int addr;
2603 u32 gpio_shift, tmp;
f078f209 2604
f1dc5600
S		 2605 if (gpio > 11)
2606 addr = AR_GPIO_OUTPUT_MUX3;
2607 else if (gpio > 5)
2608 addr = AR_GPIO_OUTPUT_MUX2;
2609 else
2610 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2611
f1dc5600 2612 gpio_shift = (gpio % 6) * 5;
f078f209 2613
f1dc5600
S		 2614 if (AR_SREV_9280_20_OR_LATER(ah)
2615 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2616 REG_RMW(ah, addr, (type << gpio_shift),
2617 (0x1f << gpio_shift));
f078f209 2618 } else {
f1dc5600
S		 2619 tmp = REG_READ(ah, addr);
2620 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2621 tmp &= ~(0x1f << gpio_shift);
2622 tmp |= (type << gpio_shift);
2623 REG_WRITE(ah, addr, tmp);
f078f209 2624 }
f078f209
LR		 2625}
2626
cbe61d8a 2627void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2628{
f1dc5600 2629 u32 gpio_shift;
f078f209 2630
9680e8a3 2631 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2632
88c1f4f6
S		 2633 if (AR_DEVID_7010(ah)) {
2634 gpio_shift = gpio;
2635 REG_RMW(ah, AR7010_GPIO_OE,
2636 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2637 (AR7010_GPIO_OE_MASK << gpio_shift));
2638 return;
2639 }
f078f209 2640
88c1f4f6 2641 gpio_shift = gpio << 1;
f1dc5600
S		 2642 REG_RMW(ah,
2643 AR_GPIO_OE_OUT,
2644 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2645 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2646}
7322fd19 2647EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2648
cbe61d8a 2649u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2650{
cb33c412
SB		 2651#define MS_REG_READ(x, y) \
2652 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2653
2660b81a 2654 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2655 return 0xffffffff;
f078f209 2656
88c1f4f6
S		 2657 if (AR_DEVID_7010(ah)) {
2658 u32 val;
2659 val = REG_READ(ah, AR7010_GPIO_IN);
2660 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2661 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2662 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2663 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2664 else if (AR_SREV_9271(ah))
5b5fa355 2665 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2666 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2667 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2668 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2669 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2670 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2671 return MS_REG_READ(AR928X, gpio) != 0;
2672 else
2673 return MS_REG_READ(AR, gpio) != 0;
f078f209 2674}
7322fd19 2675EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2676
cbe61d8a 2677void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2678 u32 ah_signal_type)
f078f209 2679{
f1dc5600 2680 u32 gpio_shift;
f078f209 2681
88c1f4f6
S		 2682 if (AR_DEVID_7010(ah)) {
2683 gpio_shift = gpio;
2684 REG_RMW(ah, AR7010_GPIO_OE,
2685 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2686 (AR7010_GPIO_OE_MASK << gpio_shift));
2687 return;
2688 }
f078f209 2689
88c1f4f6 2690 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2691 gpio_shift = 2 * gpio;
f1dc5600
S		 2692 REG_RMW(ah,
2693 AR_GPIO_OE_OUT,
2694 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2695 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2696}
7322fd19 2697EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2698
cbe61d8a 2699void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2700{
88c1f4f6
S		 2701 if (AR_DEVID_7010(ah)) {
2702 val = val ? 0 : 1;
2703 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2704 AR_GPIO_BIT(gpio));
2705 return;
2706 }
2707
5b5fa355
S		 2708 if (AR_SREV_9271(ah))
2709 val = ~val;
2710
f1dc5600
S		 2711 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2712 AR_GPIO_BIT(gpio));
f078f209 2713}
7322fd19 2714EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2715
cbe61d8a 2716void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2717{
f1dc5600 2718 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2719}
7322fd19 2720EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2721
f1dc5600
S		 2722/*********************/
2723/* General Operation */
2724/*********************/
2725
cbe61d8a 2726u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2727{
f1dc5600
S		 2728 u32 bits = REG_READ(ah, AR_RX_FILTER);
2729 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2730
f1dc5600
S		 2731 if (phybits & AR_PHY_ERR_RADAR)
2732 bits |= ATH9K_RX_FILTER_PHYRADAR;
2733 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2734 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2735
f1dc5600 2736 return bits;
f078f209 2737}
7322fd19 2738EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2739
cbe61d8a 2740void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2741{
f1dc5600 2742 u32 phybits;
f078f209 2743
7d0d0df0
S		 2744 ENABLE_REGWRITE_BUFFER(ah);
2745
423e38e8 2746 if (AR_SREV_9462(ah))
2577c6e8
SB		 2747 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2748
7ea310be
S		 2749 REG_WRITE(ah, AR_RX_FILTER, bits);
2750
f1dc5600
S		 2751 phybits = 0;
2752 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2753 phybits |= AR_PHY_ERR_RADAR;
2754 if (bits & ATH9K_RX_FILTER_PHYERR)
2755 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2756 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2757
f1dc5600 2758 if (phybits)
ca7a4deb 2759 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2760 else
ca7a4deb 2761 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2762
2763 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2764}
7322fd19 2765EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2766
cbe61d8a 2767bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2768{
99922a45
RM		 2769 if (ath9k_hw_mci_is_enabled(ah))
2770 ar9003_mci_bt_gain_ctrl(ah);
2771
63a75b91
SB		 2772 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2773 return false;
2774
2775 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2776 ah->htc_reset_init = true;
63a75b91 2777 return true;
f1dc5600 2778}
7322fd19 2779EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2780
cbe61d8a 2781bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2782{
9ecdef4b 2783 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2784 return false;
f078f209 2785
63a75b91
SB		 2786 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2787 return false;
2788
2789 ath9k_hw_init_pll(ah, NULL);
2790 return true;
f078f209 2791}
7322fd19 2792EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2793
ca2c68cc
FF		 2794static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2795{
2796 enum eeprom_param gain_param;
2797
2798 if (IS_CHAN_2GHZ(chan))
2799 gain_param = EEP_ANTENNA_GAIN_2G;
2800 else
2801 gain_param = EEP_ANTENNA_GAIN_5G;
2802
2803 return ah->eep_ops->get_eeprom(ah, gain_param);
2804}
2805
64ea57d0
GJ		 2806void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2807 bool test)
ca2c68cc
FF		 2808{
2809 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2810 struct ieee80211_channel *channel;
2811 int chan_pwr, new_pwr, max_gain;
2812 int ant_gain, ant_reduction = 0;
2813
2814 if (!chan)
2815 return;
2816
2817 channel = chan->chan;
2818 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2819 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2820 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2821
2822 ant_gain = get_antenna_gain(ah, chan);
2823 if (ant_gain > max_gain)
2824 ant_reduction = ant_gain - max_gain;
2825
2826 ah->eep_ops->set_txpower(ah, chan,
2827 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2828 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2829}
2830
de40f316 2831void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2832{
ca2c68cc 2833 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2834 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2835 struct ieee80211_channel *channel = chan->chan;
9c204b46 2836
48ef5c42 2837 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2838 if (test)
ca2c68cc 2839 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2840
64ea57d0 2841 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2842
ca2c68cc
FF		 2843 if (test)
2844 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2845}
7322fd19 2846EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2847
cbe61d8a 2848void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2849{
2660b81a 2850 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2851}
7322fd19 2852EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2853
cbe61d8a 2854void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2855{
f1dc5600
S		 2856 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2857 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2858}
7322fd19 2859EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2860
f2b2143e 2861void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2862{
1510718d
LR		 2863 struct ath_common *common = ath9k_hw_common(ah);
2864
2865 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2866 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2867 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2868}
7322fd19 2869EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2870
1c0fc65e
BP		 2871#define ATH9K_MAX_TSF_READ 10
2872
cbe61d8a 2873u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2874{
1c0fc65e
BP		 2875 u32 tsf_lower, tsf_upper1, tsf_upper2;
2876 int i;
2877
2878 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2879 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2880 tsf_lower = REG_READ(ah, AR_TSF_L32);
2881 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2882 if (tsf_upper2 == tsf_upper1)
2883 break;
2884 tsf_upper1 = tsf_upper2;
2885 }
f078f209 2886
1c0fc65e 2887 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2888
1c0fc65e 2889 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2890}
7322fd19 2891EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2892
cbe61d8a 2893void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2894{
27abe060 2895 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2896 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2897}
7322fd19 2898EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2899
cbe61d8a 2900void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2901{
f9b604f6
GJ		 2902 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2903 AH_TSF_WRITE_TIMEOUT))
d2182b69 2904 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2905 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2906
f1dc5600
S		 2907 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2908}
7322fd19 2909EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2910
54e4cec6 2911void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2912{
f1dc5600 2913 if (setting)
2660b81a 2914 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2915 else
2660b81a 2916 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2917}
7322fd19 2918EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2919
25c56eec 2920void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2921{
25c56eec 2922 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2923 u32 macmode;
2924
25c56eec 2925 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2926 macmode = AR_2040_JOINED_RX_CLEAR;
2927 else
2928 macmode = 0;
f078f209 2929
f1dc5600 2930 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2931}
ff155a45
VT		 2932
2933/* HW Generic timers configuration */
2934
2935static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2936{
2937 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2938 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2939 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2940 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2941 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2942 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2943 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2944 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2945 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2946 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2947 AR_NDP2_TIMER_MODE, 0x0002},
2948 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2949 AR_NDP2_TIMER_MODE, 0x0004},
2950 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2951 AR_NDP2_TIMER_MODE, 0x0008},
2952 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2953 AR_NDP2_TIMER_MODE, 0x0010},
2954 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2955 AR_NDP2_TIMER_MODE, 0x0020},
2956 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2957 AR_NDP2_TIMER_MODE, 0x0040},
2958 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2959 AR_NDP2_TIMER_MODE, 0x0080}
2960};
2961
2962/* HW generic timer primitives */
2963
2964/* compute and clear index of rightmost 1 */
2965static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2966{
2967 u32 b;
2968
2969 b = *mask;
2970 b &= (0-b);
2971 *mask &= ~b;
2972 b *= debruijn32;
2973 b >>= 27;
2974
2975 return timer_table->gen_timer_index[b];
2976}
2977
dd347f2f 2978u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2979{
2980 return REG_READ(ah, AR_TSF_L32);
2981}
dd347f2f 2982EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2983
2984struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2985 void (*trigger)(void *),
2986 void (*overflow)(void *),
2987 void *arg,
2988 u8 timer_index)
2989{
2990 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2991 struct ath_gen_timer *timer;
2992
2993 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2994
2995 if (timer == NULL) {
3800276a
JP		 2996 ath_err(ath9k_hw_common(ah),
2997 "Failed to allocate memory for hw timer[%d]\n",
2998 timer_index);
ff155a45
VT		 2999 return NULL;
3000 }
3001
3002 /* allocate a hardware generic timer slot */
3003 timer_table->timers[timer_index] = timer;
3004 timer->index = timer_index;
3005 timer->trigger = trigger;
3006 timer->overflow = overflow;
3007 timer->arg = arg;
3008
3009 return timer;
3010}
7322fd19 3011EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3012
cd9bf689
LR		 3013void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3014 struct ath_gen_timer *timer,
788f6875 3015 u32 trig_timeout,
cd9bf689 3016 u32 timer_period)
ff155a45
VT		 3017{
3018 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
788f6875 3019 u32 tsf, timer_next;
ff155a45
VT		 3020
3021 BUG_ON(!timer_period);
3022
3023 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3024
3025 tsf = ath9k_hw_gettsf32(ah);
3026
788f6875
VT		 3027 timer_next = tsf + trig_timeout;
3028
d2182b69 3029 ath_dbg(ath9k_hw_common(ah), HWTIMER,
226afe68
JP		 3030 "current tsf %x period %x timer_next %x\n",
3031 tsf, timer_period, timer_next);
ff155a45 3032
ff155a45
VT		 3033 /*
3034 * Program generic timer registers
3035 */
3036 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3037 timer_next);
3038 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3039 timer_period);
3040 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3041 gen_tmr_configuration[timer->index].mode_mask);
3042
423e38e8 3043 if (AR_SREV_9462(ah)) {
2577c6e8 3044 /*
423e38e8 3045 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3046 * to use. But we still follow the old rule, 0 - 7 use tsf and
3047 * 8 - 15 use tsf2.
3048 */
3049 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3050 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3051 (1 << timer->index));
3052 else
3053 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3054 (1 << timer->index));
3055 }
3056
ff155a45
VT		 3057 /* Enable both trigger and thresh interrupt masks */
3058 REG_SET_BIT(ah, AR_IMR_S5,
3059 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3060 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 3061}
7322fd19 3062EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3063
cd9bf689 3064void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3065{
3066 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3067
3068 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3069 (timer->index >= ATH_MAX_GEN_TIMER)) {
3070 return;
3071 }
3072
3073 /* Clear generic timer enable bits. */
3074 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3075 gen_tmr_configuration[timer->index].mode_mask);
3076
3077 /* Disable both trigger and thresh interrupt masks */
3078 REG_CLR_BIT(ah, AR_IMR_S5,
3079 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3080 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3081
3082 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3083}
7322fd19 3084EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3085
3086void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3087{
3088 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3089
3090 /* free the hardware generic timer slot */
3091 timer_table->timers[timer->index] = NULL;
3092 kfree(timer);
3093}
7322fd19 3094EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3095
3096/*
3097 * Generic Timer Interrupts handling
3098 */
3099void ath_gen_timer_isr(struct ath_hw *ah)
3100{
3101 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3102 struct ath_gen_timer *timer;
c46917bb 3103 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3104 u32 trigger_mask, thresh_mask, index;
3105
3106 /* get hardware generic timer interrupt status */
3107 trigger_mask = ah->intr_gen_timer_trigger;
3108 thresh_mask = ah->intr_gen_timer_thresh;
3109 trigger_mask &= timer_table->timer_mask.val;
3110 thresh_mask &= timer_table->timer_mask.val;
3111
3112 trigger_mask &= ~thresh_mask;
3113
3114 while (thresh_mask) {
3115 index = rightmost_index(timer_table, &thresh_mask);
3116 timer = timer_table->timers[index];
3117 BUG_ON(!timer);
d2182b69
JP		 3118 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3119 index);
ff155a45
VT		 3120 timer->overflow(timer->arg);
3121 }
3122
3123 while (trigger_mask) {
3124 index = rightmost_index(timer_table, &trigger_mask);
3125 timer = timer_table->timers[index];
3126 BUG_ON(!timer);
d2182b69 3127 ath_dbg(common, HWTIMER,
226afe68 3128 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3129 timer->trigger(timer->arg);
3130 }
3131}
7322fd19 3132EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3133
05020d23
S		 3134/********/
3135/* HTC */
3136/********/
3137
2da4f01a
LR		 3138static struct {
3139 u32 version;
3140 const char * name;
3141} ath_mac_bb_names[] = {
3142 /* Devices with external radios */
3143 { AR_SREV_VERSION_5416_PCI, "5416" },
3144 { AR_SREV_VERSION_5416_PCIE, "5418" },
3145 { AR_SREV_VERSION_9100, "9100" },
3146 { AR_SREV_VERSION_9160, "9160" },
3147 /* Single-chip solutions */
3148 { AR_SREV_VERSION_9280, "9280" },
3149 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3150 { AR_SREV_VERSION_9287, "9287" },
3151 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3152 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3153 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3154 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3155 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3156 { AR_SREV_VERSION_9462, "9462" },
485124cb 3157 { AR_SREV_VERSION_9550, "9550" },
2da4f01a
LR		 3158};
3159
3160/* For devices with external radios */
3161static struct {
3162 u16 version;
3163 const char * name;
3164} ath_rf_names[] = {
3165 { 0, "5133" },
3166 { AR_RAD5133_SREV_MAJOR, "5133" },
3167 { AR_RAD5122_SREV_MAJOR, "5122" },
3168 { AR_RAD2133_SREV_MAJOR, "2133" },
3169 { AR_RAD2122_SREV_MAJOR, "2122" }
3170};
3171
3172/*
3173 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3174 */
f934c4d9 3175static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3176{
3177 int i;
3178
3179 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3180 if (ath_mac_bb_names[i].version == mac_bb_version) {
3181 return ath_mac_bb_names[i].name;
3182 }
3183 }
3184
3185 return "????";
3186}
2da4f01a
LR		 3187
3188/*
3189 * Return the RF name. "????" is returned if the RF is unknown.
3190 * Used for devices with external radios.
3191 */
f934c4d9 3192static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3193{
3194 int i;
3195
3196 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3197 if (ath_rf_names[i].version == rf_version) {
3198 return ath_rf_names[i].name;
3199 }
3200 }
3201
3202 return "????";
3203}
f934c4d9
LR		 3204
3205void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3206{
3207 int used;
3208
3209 /* chipsets >= AR9280 are single-chip */
7a37081e 3210 if (AR_SREV_9280_20_OR_LATER(ah)) {
f934c4d9
LR		 3211 used = snprintf(hw_name, len,
3212 "Atheros AR%s Rev:%x",
3213 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3214 ah->hw_version.macRev);
3215 }
3216 else {
3217 used = snprintf(hw_name, len,
3218 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3219 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3220 ah->hw_version.macRev,
3221 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3222 AR_RADIO_SREV_MAJOR)),
3223 ah->hw_version.phyRev);
3224 }
3225
3226 hw_name[used] = '\0';
3227}
3228EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
This page took 1.305896 seconds and 5 git commands to generate.