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ath9k: Remove ath9k rate control
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
f078f209
LR		 22#include <asm/unaligned.h>
23
af03abec 24#include "hw.h"
d70357d5 25#include "hw-ops.h"
b622a720 26#include "ar9003_mac.h"
f4701b5a 27#include "ar9003_mci.h"
362cd03f 28#include "ar9003_phy.h"
462e58f2
BG		 29#include "debug.h"
30#include "ath9k.h"
f078f209 31
cbe61d8a 32static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 33
7322fd19
LR		 34MODULE_AUTHOR("Atheros Communications");
35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37MODULE_LICENSE("Dual BSD/GPL");
38
dfdac8ac 39static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 40{
dfdac8ac 41 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 42 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 43 unsigned int clockrate;
cbe61d8a 44
087b6ff6
FF		 45 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
46 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
47 clockrate = 117;
e4744ec7 48 else if (!chan) /* should really check for CCK instead */
dfdac8ac 49 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 50 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 51 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
52 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
53 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 54 else
dfdac8ac
FF		 55 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
56
beae416b
MN		 57 if (chan) {
58 if (IS_CHAN_HT40(chan))
59 clockrate *= 2;
e4744ec7 60 if (IS_CHAN_HALF_RATE(chan))
906c7205 61 clockrate /= 2;
e4744ec7 62 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 63 clockrate /= 4;
64 }
65
dfdac8ac 66 common->clockrate = clockrate;
f1dc5600
S		 67}
68
cbe61d8a 69static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 70{
dfdac8ac 71 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 72
dfdac8ac 73 return usecs * common->clockrate;
f1dc5600 74}
f078f209 75
0caa7b14 76bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 77{
78 int i;
79
0caa7b14
S		 80 BUG_ON(timeout < AH_TIME_QUANTUM);
81
82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 83 if ((REG_READ(ah, reg) & mask) == val)
84 return true;
85
86 udelay(AH_TIME_QUANTUM);
87 }
04bd4638 88
d2182b69 89 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 92
f1dc5600 93 return false;
f078f209 94}
7322fd19 95EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 96
7c5adc8d
FF		 97void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
98 int hw_delay)
99{
1a5e6326 100 hw_delay /= 10;
7c5adc8d
FF		 101
102 if (IS_CHAN_HALF_RATE(chan))
103 hw_delay *= 2;
104 else if (IS_CHAN_QUARTER_RATE(chan))
105 hw_delay *= 4;
106
107 udelay(hw_delay + BASE_ACTIVATE_DELAY);
108}
109
0166b4be 110void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 111 int column, unsigned int *writecnt)
112{
113 int r;
114
115 ENABLE_REGWRITE_BUFFER(ah);
116 for (r = 0; r < array->ia_rows; r++) {
117 REG_WRITE(ah, INI_RA(array, r, 0),
118 INI_RA(array, r, column));
119 DO_DELAY(*writecnt);
120 }
121 REGWRITE_BUFFER_FLUSH(ah);
122}
123
f078f209
LR		 124u32 ath9k_hw_reverse_bits(u32 val, u32 n)
125{
126 u32 retval;
127 int i;
128
129 for (i = 0, retval = 0; i < n; i++) {
130 retval = (retval << 1) | (val & 1);
131 val >>= 1;
132 }
133 return retval;
134}
135
cbe61d8a 136u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 137 u8 phy, int kbps,
f1dc5600
S		 138 u32 frameLen, u16 rateix,
139 bool shortPreamble)
f078f209 140{
f1dc5600 141 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 142
f1dc5600
S		 143 if (kbps == 0)
144 return 0;
f078f209 145
545750d3 146 switch (phy) {
46d14a58 147 case WLAN_RC_PHY_CCK:
f1dc5600 148 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 149 if (shortPreamble)
f1dc5600
S		 150 phyTime >>= 1;
151 numBits = frameLen << 3;
152 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
153 break;
46d14a58 154 case WLAN_RC_PHY_OFDM:
2660b81a 155 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
157 numBits = OFDM_PLCP_BITS + (frameLen << 3);
158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
159 txTime = OFDM_SIFS_TIME_QUARTER
160 + OFDM_PREAMBLE_TIME_QUARTER
161 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 162 } else if (ah->curchan &&
163 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 164 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
165 numBits = OFDM_PLCP_BITS + (frameLen << 3);
166 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
167 txTime = OFDM_SIFS_TIME_HALF +
168 OFDM_PREAMBLE_TIME_HALF
169 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
170 } else {
171 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
172 numBits = OFDM_PLCP_BITS + (frameLen << 3);
173 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
174 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
175 + (numSymbols * OFDM_SYMBOL_TIME);
176 }
177 break;
178 default:
3800276a
JP		 179 ath_err(ath9k_hw_common(ah),
180 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 181 txTime = 0;
182 break;
183 }
f078f209 184
f1dc5600
S		 185 return txTime;
186}
7322fd19 187EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 188
cbe61d8a 189void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 190 struct ath9k_channel *chan,
191 struct chan_centers *centers)
f078f209 192{
f1dc5600 193 int8_t extoff;
f078f209 194
f1dc5600
S		 195 if (!IS_CHAN_HT40(chan)) {
196 centers->ctl_center = centers->ext_center =
197 centers->synth_center = chan->channel;
198 return;
f078f209 199 }
f078f209 200
8896934c 201 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 202 centers->synth_center =
203 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
204 extoff = 1;
205 } else {
206 centers->synth_center =
207 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
208 extoff = -1;
209 }
f078f209 210
f1dc5600
S		 211 centers->ctl_center =
212 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 213 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 214 centers->ext_center =
6420014c 215 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 216}
217
f1dc5600
S		 218/******************/
219/* Chip Revisions */
220/******************/
221
cbe61d8a 222static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 223{
f1dc5600 224 u32 val;
f078f209 225
ecb1d385
VT		 226 switch (ah->hw_version.devid) {
227 case AR5416_AR9100_DEVID:
228 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
229 break;
3762561a
GJ		 230 case AR9300_DEVID_AR9330:
231 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
232 if (ah->get_mac_revision) {
233 ah->hw_version.macRev = ah->get_mac_revision();
234 } else {
235 val = REG_READ(ah, AR_SREV);
236 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
237 }
238 return;
ecb1d385
VT		 239 case AR9300_DEVID_AR9340:
240 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
241 val = REG_READ(ah, AR_SREV);
242 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
243 return;
813831dc
GJ		 244 case AR9300_DEVID_QCA955X:
245 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
246 return;
e6b1e46e
SM		 247 case AR9300_DEVID_AR953X:
248 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
249 return;
ecb1d385
VT		 250 }
251
f1dc5600 252 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 253
f1dc5600
S		 254 if (val == 0xFF) {
255 val = REG_READ(ah, AR_SREV);
d535a42a
S		 256 ah->hw_version.macVersion =
257 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
258 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 259
77fac465 260 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 261 ah->is_pciexpress = true;
262 else
263 ah->is_pciexpress = (val &
264 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 265 } else {
266 if (!AR_SREV_9100(ah))
d535a42a 267 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 268
d535a42a 269 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 270
d535a42a 271 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 272 ah->is_pciexpress = true;
f1dc5600 273 }
f078f209
LR		 274}
275
f1dc5600
S		 276/************************************/
277/* HW Attach, Detach, Init Routines */
278/************************************/
279
cbe61d8a 280static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 281{
040b74f7 282 if (!AR_SREV_5416(ah))
f1dc5600 283 return;
f078f209 284
f1dc5600
S		 285 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 294
f1dc5600 295 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 296}
297
1f3f0618 298/* This should work for all families including legacy */
cbe61d8a 299static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 300{
c46917bb 301 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 302 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 303 u32 regHold[2];
07b2fa5a
JP		 304 static const u32 patternData[4] = {
305 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
306 };
1f3f0618 307 int i, j, loop_max;
f078f209 308
1f3f0618
SB		 309 if (!AR_SREV_9300_20_OR_LATER(ah)) {
310 loop_max = 2;
311 regAddr[1] = AR_PHY_BASE + (8 << 2);
312 } else
313 loop_max = 1;
314
315 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 316 u32 addr = regAddr[i];
317 u32 wrData, rdData;
f078f209 318
f1dc5600
S		 319 regHold[i] = REG_READ(ah, addr);
320 for (j = 0; j < 0x100; j++) {
321 wrData = (j << 16) | j;
322 REG_WRITE(ah, addr, wrData);
323 rdData = REG_READ(ah, addr);
324 if (rdData != wrData) {
3800276a
JP		 325 ath_err(common,
326 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
327 addr, wrData, rdData);
f1dc5600
S		 328 return false;
329 }
330 }
331 for (j = 0; j < 4; j++) {
332 wrData = patternData[j];
333 REG_WRITE(ah, addr, wrData);
334 rdData = REG_READ(ah, addr);
335 if (wrData != rdData) {
3800276a
JP		 336 ath_err(common,
337 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
338 addr, wrData, rdData);
f1dc5600
S		 339 return false;
340 }
f078f209 341 }
f1dc5600 342 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 343 }
f1dc5600 344 udelay(100);
cbe61d8a 345
f078f209
LR		 346 return true;
347}
348
b8b0f377 349static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 350{
f57cf939
SM		 351 struct ath_common *common = ath9k_hw_common(ah);
352
689e756f
FF		 353 ah->config.dma_beacon_response_time = 1;
354 ah->config.sw_beacon_response_time = 6;
2660b81a 355 ah->config.cwm_ignore_extcca = 0;
2660b81a 356 ah->config.analog_shiftreg = 1;
f078f209 357
0ce024cb 358 ah->config.rx_intr_mitigation = true;
6158425b 359
a64e1a45
SM		 360 if (AR_SREV_9300_20_OR_LATER(ah)) {
361 ah->config.rimt_last = 500;
362 ah->config.rimt_first = 2000;
363 } else {
364 ah->config.rimt_last = 250;
365 ah->config.rimt_first = 700;
366 }
367
6158425b
LR		 368 /*
369 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
370 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
371 * This means we use it for all AR5416 devices, and the few
372 * minor PCI AR9280 devices out there.
373 *
374 * Serialization is required because these devices do not handle
375 * well the case of two concurrent reads/writes due to the latency
376 * involved. During one read/write another read/write can be issued
377 * on another CPU while the previous read/write may still be working
378 * on our hardware, if we hit this case the hardware poops in a loop.
379 * We prevent this by serializing reads and writes.
380 *
381 * This issue is not present on PCI-Express devices or pre-AR5416
382 * devices (legacy, 802.11abg).
383 */
384 if (num_possible_cpus() > 1)
2d6a5e95 385 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f57cf939
SM		 386
387 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
388 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
389 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
390 !ah->is_pciexpress)) {
391 ah->config.serialize_regmode = SER_REG_MODE_ON;
392 } else {
393 ah->config.serialize_regmode = SER_REG_MODE_OFF;
394 }
395 }
396
397 ath_dbg(common, RESET, "serialize_regmode is %d\n",
398 ah->config.serialize_regmode);
399
400 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
401 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
402 else
403 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
f078f209
LR		 404}
405
50aca25b 406static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 407{
608b88cb
LR		 408 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
409
410 regulatory->country_code = CTRY_DEFAULT;
411 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 412
d535a42a 413 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 414 ah->hw_version.subvendorid = 0;
f078f209 415
f57cf939
SM		 416 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
417 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 418 if (AR_SREV_9100(ah))
419 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
f57cf939 420
e3f2acc7 421 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 422 ah->globaltxtimeout = (u32) -1;
cbdec975 423 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 424 ah->htc_reset_init = true;
f57cf939
SM		 425
426 ah->ani_function = ATH9K_ANI_ALL;
427 if (!AR_SREV_9300_20_OR_LATER(ah))
428 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
429
430 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
431 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
432 else
433 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209
LR		 434}
435
cbe61d8a 436static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 437{
1510718d 438 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 439 u32 sum;
440 int i;
441 u16 eeval;
07b2fa5a 442 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 443
444 sum = 0;
445 for (i = 0; i < 3; i++) {
49101676 446 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 447 sum += eeval;
1510718d
LR		 448 common->macaddr[2 * i] = eeval >> 8;
449 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 450 }
d8baa939 451 if (sum == 0 || sum == 0xffff * 3)
f078f209 452 return -EADDRNOTAVAIL;
f078f209
LR		 453
454 return 0;
455}
456
f637cfd6 457static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 458{
6cae913d 459 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 460 int ecode;
f078f209 461
6cae913d 462 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 463 if (!ath9k_hw_chip_test(ah))
464 return -ENODEV;
465 }
f078f209 466
ebd5a14a
LR		 467 if (!AR_SREV_9300_20_OR_LATER(ah)) {
468 ecode = ar9002_hw_rf_claim(ah);
469 if (ecode != 0)
470 return ecode;
471 }
f078f209 472
f637cfd6 473 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 474 if (ecode != 0)
475 return ecode;
7d01b221 476
d2182b69 477 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 478 ah->eep_ops->get_eeprom_ver(ah),
479 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 480
e323300d 481 ath9k_hw_ani_init(ah);
f078f209 482
d3b371cb
SM		 483 /*
484 * EEPROM needs to be initialized before we do this.
485 * This is required for regulatory compliance.
486 */
0c7c2bb4 487 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 488 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
489 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 490 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
491 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 492 }
493 }
494
f078f209
LR		 495 return 0;
496}
497
c1b976d2 498static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 499{
c1b976d2
FF		 500 if (!AR_SREV_9300_20_OR_LATER(ah))
501 return ar9002_hw_attach_ops(ah);
502
503 ar9003_hw_attach_ops(ah);
504 return 0;
aa4058ae
LR		 505}
506
d70357d5
LR		 507/* Called for all hardware families */
508static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 509{
c46917bb 510 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 511 int r = 0;
aa4058ae 512
ac45c12d
SB		 513 ath9k_hw_read_revisions(ah);
514
de82582b
SM		 515 switch (ah->hw_version.macVersion) {
516 case AR_SREV_VERSION_5416_PCI:
517 case AR_SREV_VERSION_5416_PCIE:
518 case AR_SREV_VERSION_9160:
519 case AR_SREV_VERSION_9100:
520 case AR_SREV_VERSION_9280:
521 case AR_SREV_VERSION_9285:
522 case AR_SREV_VERSION_9287:
523 case AR_SREV_VERSION_9271:
524 case AR_SREV_VERSION_9300:
525 case AR_SREV_VERSION_9330:
526 case AR_SREV_VERSION_9485:
527 case AR_SREV_VERSION_9340:
528 case AR_SREV_VERSION_9462:
529 case AR_SREV_VERSION_9550:
530 case AR_SREV_VERSION_9565:
e6b1e46e 531 case AR_SREV_VERSION_9531:
de82582b
SM		 532 break;
533 default:
534 ath_err(common,
535 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
536 ah->hw_version.macVersion, ah->hw_version.macRev);
537 return -EOPNOTSUPP;
538 }
539
0a8d7cb0
SB		 540 /*
541 * Read back AR_WA into a permanent copy and set bits 14 and 17.
542 * We need to do this to avoid RMW of this register. We cannot
543 * read the reg when chip is asleep.
544 */
27251e00
SM		 545 if (AR_SREV_9300_20_OR_LATER(ah)) {
546 ah->WARegVal = REG_READ(ah, AR_WA);
547 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
548 AR_WA_ASPM_TIMER_BASED_DISABLE);
549 }
0a8d7cb0 550
aa4058ae 551 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 552 ath_err(common, "Couldn't reset chip\n");
95fafca2 553 return -EIO;
aa4058ae
LR		 554 }
555
a4a2954f
SM		 556 if (AR_SREV_9565(ah)) {
557 ah->WARegVal |= AR_WA_BIT22;
558 REG_WRITE(ah, AR_WA, ah->WARegVal);
559 }
560
bab1f62e
LR		 561 ath9k_hw_init_defaults(ah);
562 ath9k_hw_init_config(ah);
563
c1b976d2
FF		 564 r = ath9k_hw_attach_ops(ah);
565 if (r)
566 return r;
d70357d5 567
9ecdef4b 568 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 569 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 570 return -EIO;
aa4058ae
LR		 571 }
572
2c8e5937 573 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 574 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 575 ah->is_pciexpress = false;
576
aa4058ae 577 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 578 ath9k_hw_init_cal_settings(ah);
579
69ce674b 580 if (!ah->is_pciexpress)
aa4058ae
LR		 581 ath9k_hw_disablepcie(ah);
582
f637cfd6 583 r = ath9k_hw_post_init(ah);
aa4058ae 584 if (r)
95fafca2 585 return r;
aa4058ae
LR		 586
587 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 588 r = ath9k_hw_fill_cap_info(ah);
589 if (r)
590 return r;
591
4f3acf81
LR		 592 r = ath9k_hw_init_macaddr(ah);
593 if (r) {
3800276a 594 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 595 return r;
f078f209
LR		 596 }
597
4598702d 598 ath9k_hw_init_hang_checks(ah);
f078f209 599
211f5859
LR		 600 common->state = ATH_HW_INITIALIZED;
601
4f3acf81 602 return 0;
f078f209
LR		 603}
604
d70357d5 605int ath9k_hw_init(struct ath_hw *ah)
f078f209 606{
d70357d5
LR		 607 int ret;
608 struct ath_common *common = ath9k_hw_common(ah);
f078f209 609
77fac465 610 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 611 switch (ah->hw_version.devid) {
612 case AR5416_DEVID_PCI:
613 case AR5416_DEVID_PCIE:
614 case AR5416_AR9100_DEVID:
615 case AR9160_DEVID_PCI:
616 case AR9280_DEVID_PCI:
617 case AR9280_DEVID_PCIE:
618 case AR9285_DEVID_PCIE:
db3cc53a
SB		 619 case AR9287_DEVID_PCI:
620 case AR9287_DEVID_PCIE:
d70357d5 621 case AR2427_DEVID_PCIE:
db3cc53a 622 case AR9300_DEVID_PCIE:
3050c914 623 case AR9300_DEVID_AR9485_PCIE:
999a7a88 624 case AR9300_DEVID_AR9330:
bca04689 625 case AR9300_DEVID_AR9340:
2b943a33 626 case AR9300_DEVID_QCA955X:
5a63ef0f 627 case AR9300_DEVID_AR9580:
423e38e8 628 case AR9300_DEVID_AR9462:
d4e5979c 629 case AR9485_DEVID_AR1111:
77fac465 630 case AR9300_DEVID_AR9565:
e6b1e46e 631 case AR9300_DEVID_AR953X:
d70357d5
LR		 632 break;
633 default:
634 if (common->bus_ops->ath_bus_type == ATH_USB)
635 break;
3800276a
JP		 636 ath_err(common, "Hardware device ID 0x%04x not supported\n",
637 ah->hw_version.devid);
d70357d5
LR		 638 return -EOPNOTSUPP;
639 }
f078f209 640
d70357d5
LR		 641 ret = __ath9k_hw_init(ah);
642 if (ret) {
3800276a
JP		 643 ath_err(common,
644 "Unable to initialize hardware; initialization status: %d\n",
645 ret);
d70357d5
LR		 646 return ret;
647 }
f078f209 648
d70357d5 649 return 0;
f078f209 650}
d70357d5 651EXPORT_SYMBOL(ath9k_hw_init);
f078f209 652
cbe61d8a 653static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 654{
7d0d0df0
S		 655 ENABLE_REGWRITE_BUFFER(ah);
656
f1dc5600
S		 657 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
658 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 659
f1dc5600
S		 660 REG_WRITE(ah, AR_QOS_NO_ACK,
661 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
662 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
663 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
664
665 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
666 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
667 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
668 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 670
671 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 672}
673
b84628eb 674u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 675{
f18e3c6b
MSS		 676 struct ath_common *common = ath9k_hw_common(ah);
677 int i = 0;
678
ca7a4deb
FF		 679 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
680 udelay(100);
681 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 682
f18e3c6b
MSS		 683 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
684
ca7a4deb 685 udelay(100);
b1415819 686
f18e3c6b
MSS		 687 if (WARN_ON_ONCE(i >= 100)) {
688 ath_err(common, "PLL4 meaurement not done\n");
689 break;
690 }
691
692 i++;
693 }
694
ca7a4deb 695 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 696}
697EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
698
cbe61d8a 699static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 700 struct ath9k_channel *chan)
f078f209 701{
d09b17f7
VT		 702 u32 pll;
703
a4a2954f 704 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 705 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
706 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
707 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
709 AR_CH0_DPLL2_KD, 0x40);
710 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
711 AR_CH0_DPLL2_KI, 0x4);
22983c30 712
3dfd7f60
VT		 713 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
714 AR_CH0_BB_DPLL1_REFDIV, 0x5);
715 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
716 AR_CH0_BB_DPLL1_NINI, 0x58);
717 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
718 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 719
720 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 721 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
723 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 724 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 725 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 726
3dfd7f60 727 /* program BB PLL phase_shift to 0x6 */
22983c30 728 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 729 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
730
731 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
732 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 733 udelay(1000);
a5415d62
GJ		 734 } else if (AR_SREV_9330(ah)) {
735 u32 ddr_dpll2, pll_control2, kd;
736
737 if (ah->is_clk_25mhz) {
738 ddr_dpll2 = 0x18e82f01;
739 pll_control2 = 0xe04a3d;
740 kd = 0x1d;
741 } else {
742 ddr_dpll2 = 0x19e82f01;
743 pll_control2 = 0x886666;
744 kd = 0x3d;
745 }
746
747 /* program DDR PLL ki and kd value */
748 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
749
750 /* program DDR PLL phase_shift */
751 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
752 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
753
754 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
755 udelay(1000);
756
757 /* program refdiv, nint, frac to RTC register */
758 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
759
760 /* program BB PLL kd and ki value */
761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
763
764 /* program BB PLL phase_shift */
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
766 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
2c323058 767 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
0b488ac6
VT		 768 u32 regval, pll2_divint, pll2_divfrac, refdiv;
769
770 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
771 udelay(1000);
772
773 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
774 udelay(100);
775
776 if (ah->is_clk_25mhz) {
2c323058
SM		 777 if (AR_SREV_9531(ah)) {
778 pll2_divint = 0x1c;
779 pll2_divfrac = 0xa3d2;
780 refdiv = 1;
781 } else {
782 pll2_divint = 0x54;
783 pll2_divfrac = 0x1eb85;
784 refdiv = 3;
785 }
0b488ac6 786 } else {
fc05a317
GJ		 787 if (AR_SREV_9340(ah)) {
788 pll2_divint = 88;
789 pll2_divfrac = 0;
790 refdiv = 5;
791 } else {
792 pll2_divint = 0x11;
793 pll2_divfrac = 0x26666;
794 refdiv = 1;
795 }
0b488ac6
VT		 796 }
797
798 regval = REG_READ(ah, AR_PHY_PLL_MODE);
2c323058
SM		 799 if (AR_SREV_9531(ah))
800 regval |= (0x1 << 22);
801 else
802 regval |= (0x1 << 16);
0b488ac6
VT		 803 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
804 udelay(100);
805
806 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
807 (pll2_divint << 18) | pll2_divfrac);
808 udelay(100);
809
810 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317 811 if (AR_SREV_9340(ah))
2c323058
SM		 812 regval = (regval & 0x80071fff) |
813 (0x1 << 30) |
814 (0x1 << 13) |
815 (0x4 << 26) |
816 (0x18 << 19);
817 else if (AR_SREV_9531(ah))
818 regval = (regval & 0x01c00fff) |
819 (0x1 << 31) |
820 (0x2 << 29) |
821 (0xa << 25) |
822 (0x1 << 19) |
823 (0x6 << 12);
fc05a317 824 else
2c323058
SM		 825 regval = (regval & 0x80071fff) |
826 (0x3 << 30) |
827 (0x1 << 13) |
828 (0x4 << 26) |
829 (0x60 << 19);
0b488ac6 830 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
2c323058
SM		 831
832 if (AR_SREV_9531(ah))
833 REG_WRITE(ah, AR_PHY_PLL_MODE,
834 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
835 else
836 REG_WRITE(ah, AR_PHY_PLL_MODE,
837 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
838
0b488ac6 839 udelay(1000);
22983c30 840 }
d09b17f7
VT		 841
842 pll = ath9k_hw_compute_pll_control(ah, chan);
8565f8bf
SM		 843 if (AR_SREV_9565(ah))
844 pll |= 0x40000;
d03a66c1 845 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 846
fc05a317
GJ		 847 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
848 AR_SREV_9550(ah))
3dfd7f60
VT		 849 udelay(1000);
850
c75724d1
LR		 851 /* Switch the core clock for ar9271 to 117Mhz */
852 if (AR_SREV_9271(ah)) {
25e2ab17
S		 853 udelay(500);
854 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 855 }
856
f1dc5600
S		 857 udelay(RTC_PLL_SETTLE_DELAY);
858
859 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6 860
fc05a317 861 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 862 if (ah->is_clk_25mhz) {
863 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
864 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
865 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
866 } else {
867 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
868 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
869 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
870 }
871 udelay(100);
872 }
f078f209
LR		 873}
874
cbe61d8a 875static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 876 enum nl80211_iftype opmode)
f078f209 877{
79d1d2b8 878 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 879 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 880 AR_IMR_TXURN |
881 AR_IMR_RXERR |
882 AR_IMR_RXORN |
883 AR_IMR_BCNMISC;
f078f209 884
3b8a0577 885 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
79d1d2b8
VT		 886 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
887
66860240
VT		 888 if (AR_SREV_9300_20_OR_LATER(ah)) {
889 imr_reg |= AR_IMR_RXOK_HP;
890 if (ah->config.rx_intr_mitigation)
891 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
892 else
893 imr_reg |= AR_IMR_RXOK_LP;
f078f209 894
66860240
VT		 895 } else {
896 if (ah->config.rx_intr_mitigation)
897 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
898 else
899 imr_reg |= AR_IMR_RXOK;
900 }
f078f209 901
66860240
VT		 902 if (ah->config.tx_intr_mitigation)
903 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
904 else
905 imr_reg |= AR_IMR_TXOK;
f078f209 906
7d0d0df0
S		 907 ENABLE_REGWRITE_BUFFER(ah);
908
152d530d 909 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 910 ah->imrs2_reg |= AR_IMR_S2_GTT;
911 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 912
f1dc5600
S		 913 if (!AR_SREV_9100(ah)) {
914 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 915 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 916 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
917 }
66860240 918
7d0d0df0 919 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 920
66860240
VT		 921 if (AR_SREV_9300_20_OR_LATER(ah)) {
922 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
923 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
924 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
925 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
926 }
f078f209
LR		 927}
928
b6ba41bb
FF		 929static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
930{
931 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
932 val = min(val, (u32) 0xFFFF);
933 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
934}
935
0005baf4 936static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 937{
0005baf4
FF		 938 u32 val = ath9k_hw_mac_to_clks(ah, us);
939 val = min(val, (u32) 0xFFFF);
940 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 941}
942
0005baf4 943static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 944{
0005baf4
FF		 945 u32 val = ath9k_hw_mac_to_clks(ah, us);
946 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
947 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
948}
949
950static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
951{
952 u32 val = ath9k_hw_mac_to_clks(ah, us);
953 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
954 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 955}
f1dc5600 956
cbe61d8a 957static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 958{
f078f209 959 if (tu > 0xFFFF) {
d2182b69
JP		 960 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
961 tu);
2660b81a 962 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 963 return false;
964 } else {
965 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 966 ah->globaltxtimeout = tu;
f078f209
LR		 967 return true;
968 }
969}
970
0005baf4 971void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 972{
b6ba41bb 973 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 974 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 975 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 976 int slottime;
0005baf4 977 int sifstime;
b6ba41bb
FF		 978 int rx_lat = 0, tx_lat = 0, eifs = 0;
979 u32 reg;
0005baf4 980
d2182b69 981 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 982 ah->misc_mode);
f078f209 983
b6ba41bb
FF		 984 if (!chan)
985 return;
986
2660b81a 987 if (ah->misc_mode != 0)
ca7a4deb 988 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 989
81a91d57
RM		 990 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
991 rx_lat = 41;
992 else
993 rx_lat = 37;
b6ba41bb
FF		 994 tx_lat = 54;
995
e88e4861
FF		 996 if (IS_CHAN_5GHZ(chan))
997 sifstime = 16;
998 else
999 sifstime = 10;
1000
b6ba41bb
FF		 1001 if (IS_CHAN_HALF_RATE(chan)) {
1002 eifs = 175;
1003 rx_lat *= 2;
1004 tx_lat *= 2;
1005 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1006 tx_lat += 11;
1007
92367fe7 1008 sifstime = 32;
e115b7ec 1009 ack_offset = 16;
b6ba41bb 1010 slottime = 13;
b6ba41bb
FF		 1011 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1012 eifs = 340;
81a91d57 1013 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1014 tx_lat *= 4;
1015 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1016 tx_lat += 22;
1017
92367fe7 1018 sifstime = 64;
e115b7ec 1019 ack_offset = 32;
b6ba41bb 1020 slottime = 21;
b6ba41bb 1021 } else {
a7be039d
RM		 1022 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1023 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1024 reg = AR_USEC_ASYNC_FIFO;
1025 } else {
1026 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1027 common->clockrate;
1028 reg = REG_READ(ah, AR_USEC);
1029 }
b6ba41bb
FF		 1030 rx_lat = MS(reg, AR_USEC_RX_LAT);
1031 tx_lat = MS(reg, AR_USEC_TX_LAT);
1032
1033 slottime = ah->slottime;
b6ba41bb 1034 }
0005baf4 1035
e239d859 1036 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1037 slottime += 3 * ah->coverage_class;
1038 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1039 ctstimeout = acktimeout;
42c4568a
FF		 1040
1041 /*
1042 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1043 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1044 * This was initially only meant to work around an issue with delayed
1045 * BA frames in some implementations, but it has been found to fix ACK
1046 * timeout issues in other cases as well.
1047 */
e4744ec7 1048 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1049 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1050 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1051 ctstimeout += 48 - sifstime - ah->slottime;
1052 }
1053
b6ba41bb
FF		 1054 ath9k_hw_set_sifs_time(ah, sifstime);
1055 ath9k_hw_setslottime(ah, slottime);
0005baf4 1056 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1057 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1058 if (ah->globaltxtimeout != (u32) -1)
1059 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1060
1061 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1062 REG_RMW(ah, AR_USEC,
1063 (common->clockrate - 1) |
1064 SM(rx_lat, AR_USEC_RX_LAT) |
1065 SM(tx_lat, AR_USEC_TX_LAT),
1066 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1067
f1dc5600 1068}
0005baf4 1069EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1070
285f2dda 1071void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1072{
211f5859
LR		 1073 struct ath_common *common = ath9k_hw_common(ah);
1074
736b3a27 1075 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1076 return;
211f5859 1077
9ecdef4b 1078 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1079}
285f2dda 1080EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1081
f1dc5600
S		 1082/*******/
1083/* INI */
1084/*******/
1085
8fe65368 1086u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1087{
1088 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1089
6b21fd20 1090 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1091 ctl |= CTL_11G;
1092 else
1093 ctl |= CTL_11A;
1094
1095 return ctl;
1096}
1097
f1dc5600
S		 1098/****************************************/
1099/* Reset and Channel Switching Routines */
1100/****************************************/
f1dc5600 1101
cbe61d8a 1102static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1103{
57b32227 1104 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1105 int txbuf_size;
f1dc5600 1106
7d0d0df0
S		 1107 ENABLE_REGWRITE_BUFFER(ah);
1108
d7e7d229
LR		 1109 /*
1110 * set AHB_MODE not to do cacheline prefetches
1111 */
ca7a4deb
FF		 1112 if (!AR_SREV_9300_20_OR_LATER(ah))
1113 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1114
d7e7d229
LR		 1115 /*
1116 * let mac dma reads be in 128 byte chunks
1117 */
ca7a4deb 1118 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1119
7d0d0df0 1120 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1121
d7e7d229
LR		 1122 /*
1123 * Restore TX Trigger Level to its pre-reset value.
1124 * The initial value depends on whether aggregation is enabled, and is
1125 * adjusted whenever underruns are detected.
1126 */
57b32227
FF		 1127 if (!AR_SREV_9300_20_OR_LATER(ah))
1128 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1129
7d0d0df0 1130 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1131
d7e7d229
LR		 1132 /*
1133 * let mac dma writes be in 128 byte chunks
1134 */
ca7a4deb 1135 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1136
d7e7d229
LR		 1137 /*
1138 * Setup receive FIFO threshold to hold off TX activities
1139 */
f1dc5600
S		 1140 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1141
57b32227
FF		 1142 if (AR_SREV_9300_20_OR_LATER(ah)) {
1143 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1144 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1145
1146 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1147 ah->caps.rx_status_len);
1148 }
1149
d7e7d229
LR		 1150 /*
1151 * reduce the number of usable entries in PCU TXBUF to avoid
1152 * wrap around issues.
1153 */
f1dc5600 1154 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1155 /* For AR9285 the number of Fifos are reduced to half.
1156 * So set the usable tx buf size also to half to
1157 * avoid data/delimiter underruns
1158 */
86c157b3
FF		 1159 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1160 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1161 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1162 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1163 } else {
1164 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1165 }
744d4025 1166
86c157b3
FF		 1167 if (!AR_SREV_9271(ah))
1168 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1169
7d0d0df0 1170 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1171
744d4025
VT		 1172 if (AR_SREV_9300_20_OR_LATER(ah))
1173 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1174}
1175
cbe61d8a 1176static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1177{
ca7a4deb
FF		 1178 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1179 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1180
f1dc5600 1181 switch (opmode) {
d97809db 1182 case NL80211_IFTYPE_ADHOC:
ca7a4deb 1183 set |= AR_STA_ID1_ADHOC;
f1dc5600 1184 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1185 break;
2664d666 1186 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1187 case NL80211_IFTYPE_AP:
1188 set |= AR_STA_ID1_STA_AP;
1189 /* fall through */
d97809db 1190 case NL80211_IFTYPE_STATION:
ca7a4deb 1191 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1192 break;
5f841b41 1193 default:
ca7a4deb
FF		 1194 if (!ah->is_monitoring)
1195 set = 0;
5f841b41 1196 break;
f1dc5600 1197 }
ca7a4deb 1198 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1199}
1200
8fe65368
LR		 1201void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1202 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1203{
1204 u32 coef_exp, coef_man;
1205
1206 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1207 if ((coef_scaled >> coef_exp) & 0x1)
1208 break;
1209
1210 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1211
1212 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1213
1214 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1215 *coef_exponent = coef_exp - 16;
1216}
1217
d7df7a55
SM		 1218/* AR9330 WAR:
1219 * call external reset function to reset WMAC if:
1220 * - doing a cold reset
1221 * - we have pending frames in the TX queues.
1222 */
1223static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1224{
1225 int i, npend = 0;
1226
1227 for (i = 0; i < AR_NUM_QCU; i++) {
1228 npend = ath9k_hw_numtxpending(ah, i);
1229 if (npend)
1230 break;
1231 }
1232
1233 if (ah->external_reset &&
1234 (npend || type == ATH9K_RESET_COLD)) {
1235 int reset_err = 0;
1236
1237 ath_dbg(ath9k_hw_common(ah), RESET,
1238 "reset MAC via external reset\n");
1239
1240 reset_err = ah->external_reset();
1241 if (reset_err) {
1242 ath_err(ath9k_hw_common(ah),
1243 "External reset failed, err=%d\n",
1244 reset_err);
1245 return false;
1246 }
1247
1248 REG_WRITE(ah, AR_RTC_RESET, 1);
1249 }
1250
1251 return true;
1252}
1253
cbe61d8a 1254static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1255{
1256 u32 rst_flags;
1257 u32 tmpReg;
1258
70768496 1259 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1260 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1261 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1262 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1263 }
1264
7d0d0df0
S		 1265 ENABLE_REGWRITE_BUFFER(ah);
1266
9a658d2b
LR		 1267 if (AR_SREV_9300_20_OR_LATER(ah)) {
1268 REG_WRITE(ah, AR_WA, ah->WARegVal);
1269 udelay(10);
1270 }
1271
f1dc5600
S		 1272 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1273 AR_RTC_FORCE_WAKE_ON_INT);
1274
1275 if (AR_SREV_9100(ah)) {
1276 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1277 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1278 } else {
1279 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1280 if (AR_SREV_9340(ah))
1281 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1282 else
1283 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1284 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1285
1286 if (tmpReg) {
42d5bc3f 1287 u32 val;
f1dc5600 1288 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1289
1290 val = AR_RC_HOSTIF;
1291 if (!AR_SREV_9300_20_OR_LATER(ah))
1292 val |= AR_RC_AHB;
1293 REG_WRITE(ah, AR_RC, val);
1294
1295 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1296 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1297
1298 rst_flags = AR_RTC_RC_MAC_WARM;
1299 if (type == ATH9K_RESET_COLD)
1300 rst_flags |= AR_RTC_RC_MAC_COLD;
1301 }
1302
7d95847c 1303 if (AR_SREV_9330(ah)) {
d7df7a55
SM		 1304 if (!ath9k_hw_ar9330_reset_war(ah, type))
1305 return false;
7d95847c
GJ		 1306 }
1307
3863495b 1308 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1309 ar9003_mci_check_gpm_offset(ah);
3863495b 1310
d03a66c1 1311 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1312
1313 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1314
4dc78c43
SM		 1315 if (AR_SREV_9300_20_OR_LATER(ah))
1316 udelay(50);
1317 else if (AR_SREV_9100(ah))
1318 udelay(10000);
1319 else
1320 udelay(100);
f1dc5600 1321
d03a66c1 1322 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1323 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1324 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1325 return false;
1326 }
1327
1328 if (!AR_SREV_9100(ah))
1329 REG_WRITE(ah, AR_RC, 0);
1330
f1dc5600
S		 1331 if (AR_SREV_9100(ah))
1332 udelay(50);
1333
1334 return true;
1335}
1336
cbe61d8a 1337static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1338{
7d0d0df0
S		 1339 ENABLE_REGWRITE_BUFFER(ah);
1340
9a658d2b
LR		 1341 if (AR_SREV_9300_20_OR_LATER(ah)) {
1342 REG_WRITE(ah, AR_WA, ah->WARegVal);
1343 udelay(10);
1344 }
1345
f1dc5600
S		 1346 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1347 AR_RTC_FORCE_WAKE_ON_INT);
1348
42d5bc3f 1349 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1350 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1351
d03a66c1 1352 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1353
7d0d0df0 1354 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1355
afe36533 1356 udelay(2);
84e2169b
SB		 1357
1358 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1359 REG_WRITE(ah, AR_RC, 0);
1360
d03a66c1 1361 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1362
1363 if (!ath9k_hw_wait(ah,
1364 AR_RTC_STATUS,
1365 AR_RTC_STATUS_M,
0caa7b14
S		 1366 AR_RTC_STATUS_ON,
1367 AH_WAIT_TIMEOUT)) {
d2182b69 1368 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1369 return false;
f078f209
LR		 1370 }
1371
f1dc5600
S		 1372 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1373}
1374
cbe61d8a 1375static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1376{
7a9233ff 1377 bool ret = false;
2577c6e8 1378
9a658d2b
LR		 1379 if (AR_SREV_9300_20_OR_LATER(ah)) {
1380 REG_WRITE(ah, AR_WA, ah->WARegVal);
1381 udelay(10);
1382 }
1383
f1dc5600
S		 1384 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1385 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1386
ceb26a60
FF		 1387 if (!ah->reset_power_on)
1388 type = ATH9K_RESET_POWER_ON;
1389
f1dc5600
S		 1390 switch (type) {
1391 case ATH9K_RESET_POWER_ON:
7a9233ff 1392 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1393 if (ret)
ceb26a60 1394 ah->reset_power_on = true;
7a9233ff 1395 break;
f1dc5600
S		 1396 case ATH9K_RESET_WARM:
1397 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1398 ret = ath9k_hw_set_reset(ah, type);
1399 break;
f1dc5600 1400 default:
7a9233ff 1401 break;
f1dc5600 1402 }
7a9233ff 1403
7a9233ff 1404 return ret;
f078f209
LR		 1405}
1406
cbe61d8a 1407static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1408 struct ath9k_channel *chan)
f078f209 1409{
9c083af8
FF		 1410 int reset_type = ATH9K_RESET_WARM;
1411
1412 if (AR_SREV_9280(ah)) {
1413 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1414 reset_type = ATH9K_RESET_POWER_ON;
1415 else
1416 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1417 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1418 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1419 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1420
1421 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1422 return false;
f078f209 1423
9ecdef4b 1424 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1425 return false;
f078f209 1426
2660b81a 1427 ah->chip_fullsleep = false;
bfc441a4
FF		 1428
1429 if (AR_SREV_9330(ah))
1430 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1431 ath9k_hw_init_pll(ah, chan);
f078f209 1432
f1dc5600 1433 return true;
f078f209
LR		 1434}
1435
cbe61d8a 1436static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1437 struct ath9k_channel *chan)
f078f209 1438{
c46917bb 1439 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1440 struct ath9k_hw_capabilities *pCap = &ah->caps;
1441 bool band_switch = false, mode_diff = false;
70e89a71 1442 u8 ini_reloaded = 0;
8fe65368 1443 u32 qnum;
0a3b7bac 1444 int r;
5f0c04ea 1445
b840cffe 1446 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1447 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1448 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1449 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1450 }
f078f209
LR		 1451
1452 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1453 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1454 ath_dbg(common, QUEUE,
226afe68 1455 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1456 return false;
1457 }
1458 }
1459
8fe65368 1460 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1461 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1462 return false;
1463 }
1464
b840cffe 1465 if (band_switch || mode_diff) {
5f0c04ea
RM		 1466 ath9k_hw_mark_phy_inactive(ah);
1467 udelay(5);
1468
5f35c0fa
SM		 1469 if (band_switch)
1470 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1471
1472 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1473 ath_err(common, "Failed to do fast channel change\n");
1474 return false;
1475 }
1476 }
1477
8fe65368 1478 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1479
8fe65368 1480 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1481 if (r) {
3800276a 1482 ath_err(common, "Failed to set channel\n");
0a3b7bac 1483 return false;
f078f209 1484 }
dfdac8ac 1485 ath9k_hw_set_clockrate(ah);
64ea57d0 1486 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1487
81c507a8 1488 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1489 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1490
70e89a71
SM		 1491 if (band_switch || ini_reloaded)
1492 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1493
70e89a71
SM		 1494 ath9k_hw_init_bb(ah, chan);
1495 ath9k_hw_rfbus_done(ah);
5f0c04ea 1496
70e89a71
SM		 1497 if (band_switch || ini_reloaded) {
1498 ah->ah_flags |= AH_FASTCC;
1499 ath9k_hw_init_cal(ah, chan);
a126ff51 1500 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1501 }
1502
f1dc5600
S		 1503 return true;
1504}
1505
691680b8
FF		 1506static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1507{
1508 u32 gpio_mask = ah->gpio_mask;
1509 int i;
1510
1511 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1512 if (!(gpio_mask & 1))
1513 continue;
1514
1515 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1516 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1517 }
1518}
1519
1e516ca7
SM		 1520void ath9k_hw_check_nav(struct ath_hw *ah)
1521{
1522 struct ath_common *common = ath9k_hw_common(ah);
1523 u32 val;
1524
1525 val = REG_READ(ah, AR_NAV);
1526 if (val != 0xdeadbeef && val > 0x7fff) {
1527 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1528 REG_WRITE(ah, AR_NAV, 0);
1529 }
1530}
1531EXPORT_SYMBOL(ath9k_hw_check_nav);
1532
c9c99e5e 1533bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1534{
c9c99e5e
FF		 1535 int count = 50;
1536 u32 reg;
1537
01e18918
RM		 1538 if (AR_SREV_9300(ah))
1539 return !ath9k_hw_detect_mac_hang(ah);
1540
e17f83ea 1541 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1542 return true;
1543
1544 do {
1545 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1546
c9c99e5e
FF		 1547 if ((reg & 0x7E7FFFEF) == 0x00702400)
1548 continue;
1549
1550 switch (reg & 0x7E000B00) {
1551 case 0x1E000000:
1552 case 0x52000B00:
1553 case 0x18000B00:
1554 continue;
1555 default:
1556 return true;
1557 }
1558 } while (count-- > 0);
3b319aae 1559
c9c99e5e 1560 return false;
3b319aae 1561}
c9c99e5e 1562EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1563
15d2b585
SM		 1564static void ath9k_hw_init_mfp(struct ath_hw *ah)
1565{
1566 /* Setup MFP options for CCMP */
1567 if (AR_SREV_9280_20_OR_LATER(ah)) {
1568 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1569 * frames when constructing CCMP AAD. */
1570 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1571 0xc7ff);
1572 ah->sw_mgmt_crypto = false;
1573 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1574 /* Disable hardware crypto for management frames */
1575 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1576 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1577 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1578 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1579 ah->sw_mgmt_crypto = true;
1580 } else {
1581 ah->sw_mgmt_crypto = true;
1582 }
1583}
1584
1585static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1586 u32 macStaId1, u32 saveDefAntenna)
1587{
1588 struct ath_common *common = ath9k_hw_common(ah);
1589
1590 ENABLE_REGWRITE_BUFFER(ah);
1591
ecbbed32 1592 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585 1593 | AR_STA_ID1_RTS_USE_DEF
ecbbed32
FF		 1594 | ah->sta_id1_defaults,
1595 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1596 ath_hw_setbssidmask(common);
1597 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1598 ath9k_hw_write_associd(ah);
1599 REG_WRITE(ah, AR_ISR, ~0);
1600 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1601
1602 REGWRITE_BUFFER_FLUSH(ah);
1603
1604 ath9k_hw_set_operating_mode(ah, ah->opmode);
1605}
1606
1607static void ath9k_hw_init_queues(struct ath_hw *ah)
1608{
1609 int i;
1610
1611 ENABLE_REGWRITE_BUFFER(ah);
1612
1613 for (i = 0; i < AR_NUM_DCU; i++)
1614 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1615
1616 REGWRITE_BUFFER_FLUSH(ah);
1617
1618 ah->intr_txqs = 0;
1619 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1620 ath9k_hw_resettxqueue(ah, i);
1621}
1622
1623/*
1624 * For big endian systems turn on swapping for descriptors
1625 */
1626static void ath9k_hw_init_desc(struct ath_hw *ah)
1627{
1628 struct ath_common *common = ath9k_hw_common(ah);
1629
1630 if (AR_SREV_9100(ah)) {
1631 u32 mask;
1632 mask = REG_READ(ah, AR_CFG);
1633 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1634 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1635 mask);
1636 } else {
1637 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1638 REG_WRITE(ah, AR_CFG, mask);
1639 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1640 REG_READ(ah, AR_CFG));
1641 }
1642 } else {
1643 if (common->bus_ops->ath_bus_type == ATH_USB) {
1644 /* Configure AR9271 target WLAN */
1645 if (AR_SREV_9271(ah))
1646 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1647 else
1648 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1649 }
1650#ifdef __BIG_ENDIAN
1651 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
2c323058 1652 AR_SREV_9550(ah) || AR_SREV_9531(ah))
15d2b585
SM		 1653 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1654 else
1655 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1656#endif
1657 }
1658}
1659
caed6579
SM		 1660/*
1661 * Fast channel change:
1662 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1663 */
1664static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1665{
1666 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1667 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1668 int ret;
1669
1670 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1671 goto fail;
1672
1673 if (ah->chip_fullsleep)
1674 goto fail;
1675
1676 if (!ah->curchan)
1677 goto fail;
1678
1679 if (chan->channel == ah->curchan->channel)
1680 goto fail;
1681
feb7bc99
FF		 1682 if ((ah->curchan->channelFlags | chan->channelFlags) &
1683 (CHANNEL_HALF | CHANNEL_QUARTER))
1684 goto fail;
1685
b840cffe 1686 /*
6b21fd20 1687 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1688 */
6b21fd20 1689 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1690 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1691 goto fail;
caed6579
SM		 1692
1693 if (!ath9k_hw_check_alive(ah))
1694 goto fail;
1695
1696 /*
1697 * For AR9462, make sure that calibration data for
1698 * re-using are present.
1699 */
8a90555f 1700 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1701 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1702 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1703 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1704 goto fail;
1705
1706 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1707 ah->curchan->channel, chan->channel);
1708
1709 ret = ath9k_hw_channel_change(ah, chan);
1710 if (!ret)
1711 goto fail;
1712
5955b2b0 1713 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1714 ar9003_mci_2g5g_switch(ah, false);
caed6579 1715
88033318
RM		 1716 ath9k_hw_loadnf(ah, ah->curchan);
1717 ath9k_hw_start_nfcal(ah, true);
1718
caed6579
SM		 1719 if (AR_SREV_9271(ah))
1720 ar9002_hw_load_ani_reg(ah, chan);
1721
1722 return 0;
1723fail:
1724 return -EINVAL;
1725}
1726
cbe61d8a 1727int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1728 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1729{
1510718d 1730 struct ath_common *common = ath9k_hw_common(ah);
09d8e315 1731 struct timespec ts;
f078f209 1732 u32 saveLedState;
f078f209
LR		 1733 u32 saveDefAntenna;
1734 u32 macStaId1;
46fe782c 1735 u64 tsf = 0;
09d8e315 1736 s64 usec = 0;
15d2b585 1737 int r;
caed6579 1738 bool start_mci_reset = false;
63d32967
MSS		 1739 bool save_fullsleep = ah->chip_fullsleep;
1740
5955b2b0 1741 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1742 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1743 if (start_mci_reset)
1744 return 0;
63d32967
MSS		 1745 }
1746
9ecdef4b 1747 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1748 return -EIO;
f078f209 1749
caed6579
SM		 1750 if (ah->curchan && !ah->chip_fullsleep)
1751 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1752
20bd2a09 1753 ah->caldata = caldata;
fcb9a3de 1754 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1755 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1756 /* Operating channel changed, reset channel calibration data */
1757 memset(caldata, 0, sizeof(*caldata));
1758 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1759 } else if (caldata) {
4b9b42bf 1760 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1761 }
5bc225ac 1762 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1763
caed6579
SM		 1764 if (fastcc) {
1765 r = ath9k_hw_do_fastcc(ah, chan);
1766 if (!r)
1767 return r;
f078f209
LR		 1768 }
1769
5955b2b0 1770 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1771 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1772
f078f209
LR		 1773 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1774 if (saveDefAntenna == 0)
1775 saveDefAntenna = 1;
1776
1777 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1778
09d8e315
FF		 1779 /* Save TSF before chip reset, a cold reset clears it */
1780 tsf = ath9k_hw_gettsf64(ah);
1781 getrawmonotonic(&ts);
cca213fd 1782 usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000;
46fe782c 1783
f078f209
LR		 1784 saveLedState = REG_READ(ah, AR_CFG_LED) &
1785 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1786 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1787
1788 ath9k_hw_mark_phy_inactive(ah);
1789
45ef6a0b
VT		 1790 ah->paprd_table_write_done = false;
1791
05020d23 1792 /* Only required on the first reset */
d7e7d229
LR		 1793 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1794 REG_WRITE(ah,
1795 AR9271_RESET_POWER_DOWN_CONTROL,
1796 AR9271_RADIO_RF_RST);
1797 udelay(50);
1798 }
1799
f078f209 1800 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1801 ath_err(common, "Chip reset failed\n");
ae8d2858 1802 return -EINVAL;
f078f209
LR		 1803 }
1804
05020d23 1805 /* Only required on the first reset */
d7e7d229
LR		 1806 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1807 ah->htc_reset_init = false;
1808 REG_WRITE(ah,
1809 AR9271_RESET_POWER_DOWN_CONTROL,
1810 AR9271_GATE_MAC_CTL);
1811 udelay(50);
1812 }
1813
46fe782c 1814 /* Restore TSF */
09d8e315 1815 getrawmonotonic(&ts);
cca213fd 1816 usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000 - usec;
09d8e315 1817 ath9k_hw_settsf64(ah, tsf + usec);
46fe782c 1818
7a37081e 1819 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1820 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1821
e9141f71
S		 1822 if (!AR_SREV_9300_20_OR_LATER(ah))
1823 ar9002_hw_enable_async_fifo(ah);
1824
25c56eec 1825 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1826 if (r)
1827 return r;
f078f209 1828
935d00cc
LB		 1829 ath9k_hw_set_rfmode(ah, chan);
1830
5955b2b0 1831 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1832 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1833
f860d526
FF		 1834 /*
1835 * Some AR91xx SoC devices frequently fail to accept TSF writes
1836 * right after the chip reset. When that happens, write a new
1837 * value after the initvals have been applied, with an offset
1838 * based on measured time difference
1839 */
1840 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1841 tsf += 1500;
1842 ath9k_hw_settsf64(ah, tsf);
1843 }
1844
15d2b585 1845 ath9k_hw_init_mfp(ah);
0ced0e17 1846
81c507a8 1847 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1848 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1849 ah->eep_ops->set_board_values(ah, chan);
a7765828 1850
15d2b585 1851 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1852
8fe65368 1853 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1854 if (r)
1855 return r;
f078f209 1856
dfdac8ac
FF		 1857 ath9k_hw_set_clockrate(ah);
1858
15d2b585 1859 ath9k_hw_init_queues(ah);
2660b81a 1860 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1861 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1862 ath9k_hw_init_qos(ah);
1863
2660b81a 1864 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1865 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1866
0005baf4 1867 ath9k_hw_init_global_settings(ah);
f078f209 1868
fe2b6afb
FF		 1869 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1870 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1871 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1872 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1873 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1874 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1875 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1876 }
1877
ca7a4deb 1878 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1879
1880 ath9k_hw_set_dma(ah);
1881
ed6ebd8b
RM		 1882 if (!ath9k_hw_mci_is_enabled(ah))
1883 REG_WRITE(ah, AR_OBS, 8);
f078f209 1884
0ce024cb 1885 if (ah->config.rx_intr_mitigation) {
a64e1a45
SM		 1886 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1887 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
f078f209
LR		 1888 }
1889
7f62a136
VT		 1890 if (ah->config.tx_intr_mitigation) {
1891 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1892 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1893 }
1894
f078f209
LR		 1895 ath9k_hw_init_bb(ah, chan);
1896
77a5a664 1897 if (caldata) {
4b9b42bf
SM		 1898 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1899 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 1900 }
ae8d2858 1901 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1902 return -EIO;
f078f209 1903
5955b2b0 1904 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 1905 return -EIO;
63d32967 1906
7d0d0df0 1907 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1908
8fe65368 1909 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1910 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1911
7d0d0df0 1912 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1913
15d2b585 1914 ath9k_hw_init_desc(ah);
f078f209 1915
dbccdd1d 1916 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 1917 ath9k_hw_btcoex_enable(ah);
1918
5955b2b0 1919 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1920 ar9003_mci_check_bt(ah);
63d32967 1921
1fe860ed
RM		 1922 ath9k_hw_loadnf(ah, chan);
1923 ath9k_hw_start_nfcal(ah, true);
1924
a7abaf7d 1925 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 1926 ar9003_hw_bb_watchdog_config(ah);
a7abaf7d
SM		 1927
1928 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
51ac8cbb 1929 ar9003_hw_disable_phy_restart(ah);
51ac8cbb 1930
691680b8
FF		 1931 ath9k_hw_apply_gpio_override(ah);
1932
7bdea96a 1933 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 1934 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
1935
ae8d2858 1936 return 0;
f078f209 1937}
7322fd19 1938EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1939
f1dc5600
S		 1940/******************************/
1941/* Power Management (Chipset) */
1942/******************************/
1943
42d5bc3f
LR		 1944/*
1945 * Notify Power Mgt is disabled in self-generated frames.
1946 * If requested, force chip to sleep.
1947 */
31604cf0 1948static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 1949{
f1dc5600 1950 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 1951
a4a2954f 1952 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 1953 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
1954 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
1955 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 1956 /* xxx Required for WLAN only case ? */
1957 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1958 udelay(100);
1959 }
2577c6e8 1960
31604cf0
SM		 1961 /*
1962 * Clear the RTC force wake bit to allow the
1963 * mac to go to sleep.
1964 */
1965 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1966
153dccd4 1967 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 1968 udelay(100);
2577c6e8 1969
31604cf0
SM		 1970 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1971 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1972
31604cf0
SM		 1973 /* Shutdown chip. Active low */
1974 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
1975 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1976 udelay(2);
f1dc5600 1977 }
9a658d2b
LR		 1978
1979 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 1980 if (AR_SREV_9300_20_OR_LATER(ah))
1981 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1982}
1983
bbd79af5
LR		 1984/*
1985 * Notify Power Management is enabled in self-generating
1986 * frames. If request, set power mode of chip to
1987 * auto/normal. Duration in units of 128us (1/8 TU).
1988 */
31604cf0 1989static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 1990{
31604cf0 1991 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 1992
f1dc5600 1993 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1994
31604cf0
SM		 1995 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1996 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1997 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1998 AR_RTC_FORCE_WAKE_ON_INT);
1999 } else {
2577c6e8 2000
31604cf0
SM		 2001 /* When chip goes into network sleep, it could be waken
2002 * up by MCI_INT interrupt caused by BT's HW messages
2003 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2004 * rate (~100us). This will cause chip to leave and
2005 * re-enter network sleep mode frequently, which in
2006 * consequence will have WLAN MCI HW to generate lots of
2007 * SYS_WAKING and SYS_SLEEPING messages which will make
2008 * BT CPU to busy to process.
2009 */
153dccd4
RM		 2010 if (ath9k_hw_mci_is_enabled(ah))
2011 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2012 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2013 /*
2014 * Clear the RTC force wake bit to allow the
2015 * mac to go to sleep.
2016 */
153dccd4 2017 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2018
153dccd4 2019 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2020 udelay(30);
f078f209 2021 }
9a658d2b
LR		 2022
2023 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2024 if (AR_SREV_9300_20_OR_LATER(ah))
2025 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2026}
2027
31604cf0 2028static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2029{
f1dc5600
S		 2030 u32 val;
2031 int i;
f078f209 2032
9a658d2b
LR		 2033 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2034 if (AR_SREV_9300_20_OR_LATER(ah)) {
2035 REG_WRITE(ah, AR_WA, ah->WARegVal);
2036 udelay(10);
2037 }
2038
31604cf0
SM		 2039 if ((REG_READ(ah, AR_RTC_STATUS) &
2040 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2041 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2042 return false;
f1dc5600 2043 }
31604cf0
SM		 2044 if (!AR_SREV_9300_20_OR_LATER(ah))
2045 ath9k_hw_init_pll(ah, NULL);
2046 }
2047 if (AR_SREV_9100(ah))
2048 REG_SET_BIT(ah, AR_RTC_RESET,
2049 AR_RTC_RESET_EN);
2050
2051 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2052 AR_RTC_FORCE_WAKE_EN);
04575f21
SM		 2053
2054 if (AR_SREV_9100(ah))
2055 udelay(10000);
2056 else
2057 udelay(50);
f078f209 2058
31604cf0
SM		 2059 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2060 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2061 if (val == AR_RTC_STATUS_ON)
2062 break;
2063 udelay(50);
f1dc5600
S		 2064 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2065 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2066 }
2067 if (i == 0) {
2068 ath_err(ath9k_hw_common(ah),
2069 "Failed to wakeup in %uus\n",
2070 POWER_UP_TIME / 20);
2071 return false;
f078f209
LR		 2072 }
2073
cdbe408d
RM		 2074 if (ath9k_hw_mci_is_enabled(ah))
2075 ar9003_mci_set_power_awake(ah);
2076
f1dc5600 2077 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2078
f1dc5600 2079 return true;
f078f209
LR		 2080}
2081
9ecdef4b 2082bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2083{
c46917bb 2084 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2085 int status = true;
f1dc5600
S		 2086 static const char *modes[] = {
2087 "AWAKE",
2088 "FULL-SLEEP",
2089 "NETWORK SLEEP",
2090 "UNDEFINED"
2091 };
f1dc5600 2092
cbdec975
GJ		 2093 if (ah->power_mode == mode)
2094 return status;
2095
d2182b69 2096 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2097 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2098
2099 switch (mode) {
2100 case ATH9K_PM_AWAKE:
31604cf0 2101 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2102 break;
2103 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2104 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2105 ar9003_mci_set_full_sleep(ah);
1010911e 2106
31604cf0 2107 ath9k_set_power_sleep(ah);
2660b81a 2108 ah->chip_fullsleep = true;
f1dc5600
S		 2109 break;
2110 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2111 ath9k_set_power_network_sleep(ah);
f1dc5600 2112 break;
f078f209 2113 default:
3800276a 2114 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2115 return false;
2116 }
2660b81a 2117 ah->power_mode = mode;
f1dc5600 2118
69f4aab1
LR		 2119 /*
2120 * XXX: If this warning never comes up after a while then
2121 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2122 * ath9k_hw_setpower() return type void.
2123 */
97dcec57
SM		 2124
2125 if (!(ah->ah_flags & AH_UNPLUGGED))
2126 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2127
f1dc5600 2128 return status;
f078f209 2129}
7322fd19 2130EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2131
f1dc5600
S		 2132/*******************/
2133/* Beacon Handling */
2134/*******************/
2135
cbe61d8a 2136void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2137{
f078f209
LR		 2138 int flags = 0;
2139
7d0d0df0
S		 2140 ENABLE_REGWRITE_BUFFER(ah);
2141
2660b81a 2142 switch (ah->opmode) {
d97809db 2143 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2144 REG_SET_BIT(ah, AR_TXCFG,
2145 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2146 case NL80211_IFTYPE_MESH_POINT:
d97809db 2147 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2148 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2149 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2150 TU_TO_USEC(ah->config.dma_beacon_response_time));
2151 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2152 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2153 flags |=
2154 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2155 break;
d97809db 2156 default:
d2182b69
JP		 2157 ath_dbg(ath9k_hw_common(ah), BEACON,
2158 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2159 return;
2160 break;
f078f209
LR		 2161 }
2162
dd347f2f
FF		 2163 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2164 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2165 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2166
7d0d0df0 2167 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2168
f078f209
LR		 2169 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2170}
7322fd19 2171EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2172
cbe61d8a 2173void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2174 const struct ath9k_beacon_state *bs)
f078f209
LR		 2175{
2176 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2177 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2178 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2179
7d0d0df0
S		 2180 ENABLE_REGWRITE_BUFFER(ah);
2181
4ed15762
FF		 2182 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2183 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2184 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2185
7d0d0df0 2186 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2187
f078f209
LR		 2188 REG_RMW_FIELD(ah, AR_RSSI_THR,
2189 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2190
f29f5c08 2191 beaconintval = bs->bs_intval;
f078f209
LR		 2192
2193 if (bs->bs_sleepduration > beaconintval)
2194 beaconintval = bs->bs_sleepduration;
2195
2196 dtimperiod = bs->bs_dtimperiod;
2197 if (bs->bs_sleepduration > dtimperiod)
2198 dtimperiod = bs->bs_sleepduration;
2199
2200 if (beaconintval == dtimperiod)
2201 nextTbtt = bs->bs_nextdtim;
2202 else
2203 nextTbtt = bs->bs_nexttbtt;
2204
d2182b69
JP		 2205 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2206 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2207 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2208 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2209
7d0d0df0
S		 2210 ENABLE_REGWRITE_BUFFER(ah);
2211
4ed15762
FF		 2212 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2213 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2214
f1dc5600
S		 2215 REG_WRITE(ah, AR_SLEEP1,
2216 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2217 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2218
f1dc5600
S		 2219 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2220 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2221 else
2222 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2223
f1dc5600
S		 2224 REG_WRITE(ah, AR_SLEEP2,
2225 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2226
4ed15762
FF		 2227 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2228 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2229
7d0d0df0 2230 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2231
f1dc5600
S		 2232 REG_SET_BIT(ah, AR_TIMER_MODE,
2233 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2234 AR_DTIM_TIMER_EN);
f078f209 2235
4af9cf4f
S		 2236 /* TSF Out of Range Threshold */
2237 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2238}
7322fd19 2239EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2240
f1dc5600
S		 2241/*******************/
2242/* HW Capabilities */
2243/*******************/
2244
6054069a
FF		 2245static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2246{
2247 eeprom_chainmask &= chip_chainmask;
2248 if (eeprom_chainmask)
2249 return eeprom_chainmask;
2250 else
2251 return chip_chainmask;
2252}
2253
9a66af33
ZK		 2254/**
2255 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2256 * @ah: the atheros hardware data structure
2257 *
2258 * We enable DFS support upstream on chipsets which have passed a series
2259 * of tests. The testing requirements are going to be documented. Desired
2260 * test requirements are documented at:
2261 *
2262 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2263 *
2264 * Once a new chipset gets properly tested an individual commit can be used
2265 * to document the testing for DFS for that chipset.
2266 */
2267static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2268{
2269
2270 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2271 /* for temporary testing DFS with 9280 */
2272 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2273 /* AR9580 will likely be our first target to get testing on */
2274 case AR_SREV_VERSION_9580:
73e4937d 2275 return true;
9a66af33
ZK		 2276 default:
2277 return false;
2278 }
2279}
2280
a9a29ce6 2281int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2282{
2660b81a 2283 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2284 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2285 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2286 unsigned int chip_chainmask;
608b88cb 2287
0ff2b5c0 2288 u16 eeval;
47c80de6 2289 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2290
f74df6fb 2291 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2292 regulatory->current_rd = eeval;
f078f209 2293
2660b81a 2294 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2295 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2296 if (regulatory->current_rd == 0x64 ||
2297 regulatory->current_rd == 0x65)
2298 regulatory->current_rd += 5;
2299 else if (regulatory->current_rd == 0x41)
2300 regulatory->current_rd = 0x43;
d2182b69
JP		 2301 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2302 regulatory->current_rd);
f1dc5600 2303 }
f078f209 2304
f74df6fb 2305 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2306 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2307 ath_err(common,
2308 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2309 return -EINVAL;
2310 }
2311
d4659912
FF		 2312 if (eeval & AR5416_OPFLAGS_11A)
2313 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2314
d4659912
FF		 2315 if (eeval & AR5416_OPFLAGS_11G)
2316 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2317
e41db61d
SM		 2318 if (AR_SREV_9485(ah) ||
2319 AR_SREV_9285(ah) ||
2320 AR_SREV_9330(ah) ||
2321 AR_SREV_9565(ah))
6054069a 2322 chip_chainmask = 1;
ba5736a5
MSS		 2323 else if (AR_SREV_9462(ah))
2324 chip_chainmask = 3;
6054069a
FF		 2325 else if (!AR_SREV_9280_20_OR_LATER(ah))
2326 chip_chainmask = 7;
2327 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2328 chip_chainmask = 3;
2329 else
2330 chip_chainmask = 7;
2331
f74df6fb 2332 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2333 /*
2334 * For AR9271 we will temporarilly uses the rx chainmax as read from
2335 * the EEPROM.
2336 */
8147f5de 2337 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2338 !(eeval & AR5416_OPFLAGS_11A) &&
2339 !(AR_SREV_9271(ah)))
2340 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2341 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2342 else if (AR_SREV_9100(ah))
2343 pCap->rx_chainmask = 0x7;
8147f5de 2344 else
d7e7d229 2345 /* Use rx_chainmask from EEPROM. */
8147f5de 2346 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2347
6054069a
FF		 2348 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2349 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2350 ah->txchainmask = pCap->tx_chainmask;
2351 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2352
7a37081e 2353 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2354
02d2ebb2
FF		 2355 /* enable key search for every frame in an aggregate */
2356 if (AR_SREV_9300_20_OR_LATER(ah))
2357 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2358
ce2220d1
BR		 2359 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2360
0db156e9 2361 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2362 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2363 else
2364 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2365
5b5fa355
S		 2366 if (AR_SREV_9271(ah))
2367 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2368 else if (AR_DEVID_7010(ah))
2369 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2370 else if (AR_SREV_9300_20_OR_LATER(ah))
2371 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2372 else if (AR_SREV_9287_11_OR_LATER(ah))
2373 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2374 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2375 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2376 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2377 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2378 else
2379 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2380
1b2538b2 2381 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2382 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2383 else
f1dc5600 2384 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2385
74e13060 2386#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2387 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2388 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2389 ah->rfkill_gpio =
2390 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2391 ah->rfkill_polarity =
2392 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2393
2394 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2395 }
f1dc5600 2396#endif
d5d1154f 2397 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2398 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2399 else
2400 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2401
e7594072 2402 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2403 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2404 else
2405 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2406
ceb26445 2407 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2408 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
a4a2954f 2409 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2410 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2411
ceb26445
VT		 2412 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2413 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2414 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2415 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2416 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2417 } else {
2418 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2419 if (AR_SREV_9280_20(ah))
6b42e8d0 2420 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2421 }
1adf02ff 2422
6c84ce08
VT		 2423 if (AR_SREV_9300_20_OR_LATER(ah))
2424 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2425
6ee63f55
SB		 2426 if (AR_SREV_9300_20_OR_LATER(ah))
2427 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2428
a42acef0 2429 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2430 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2431
f85c3371 2432 if (AR_SREV_9285(ah)) {
754dc536
VT		 2433 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2434 ant_div_ctl1 =
2435 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2436 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2437 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2438 ath_info(common, "Enable LNA combining\n");
2439 }
754dc536 2440 }
f85c3371
SM		 2441 }
2442
ea066d5a
MSS		 2443 if (AR_SREV_9300_20_OR_LATER(ah)) {
2444 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2445 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2446 }
2447
06236e53 2448 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2449 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2450 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2451 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2452 ath_info(common, "Enable LNA combining\n");
2453 }
21d2c63a 2454 }
754dc536 2455
9a66af33
ZK		 2456 if (ath9k_hw_dfs_tested(ah))
2457 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2458
47c80de6
VT		 2459 tx_chainmask = pCap->tx_chainmask;
2460 rx_chainmask = pCap->rx_chainmask;
2461 while (tx_chainmask || rx_chainmask) {
2462 if (tx_chainmask & BIT(0))
2463 pCap->max_txchains++;
2464 if (rx_chainmask & BIT(0))
2465 pCap->max_rxchains++;
2466
2467 tx_chainmask >>= 1;
2468 rx_chainmask >>= 1;
2469 }
2470
a4a2954f 2471 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2472 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2473 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2474
2b5e54e2 2475 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2476 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2477 }
2478
846e438f
SM		 2479 if (AR_SREV_9462(ah))
2480 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
d687809b 2481
0f21ee8d
SM		 2482 if (AR_SREV_9300_20_OR_LATER(ah) &&
2483 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2484 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2485
a9a29ce6 2486 return 0;
f078f209
LR		 2487}
2488
f1dc5600
S		 2489/****************************/
2490/* GPIO / RFKILL / Antennae */
2491/****************************/
f078f209 2492
cbe61d8a 2493static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2494 u32 gpio, u32 type)
2495{
2496 int addr;
2497 u32 gpio_shift, tmp;
f078f209 2498
f1dc5600
S		 2499 if (gpio > 11)
2500 addr = AR_GPIO_OUTPUT_MUX3;
2501 else if (gpio > 5)
2502 addr = AR_GPIO_OUTPUT_MUX2;
2503 else
2504 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2505
f1dc5600 2506 gpio_shift = (gpio % 6) * 5;
f078f209 2507
f1dc5600
S		 2508 if (AR_SREV_9280_20_OR_LATER(ah)
2509 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2510 REG_RMW(ah, addr, (type << gpio_shift),
2511 (0x1f << gpio_shift));
f078f209 2512 } else {
f1dc5600
S		 2513 tmp = REG_READ(ah, addr);
2514 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2515 tmp &= ~(0x1f << gpio_shift);
2516 tmp |= (type << gpio_shift);
2517 REG_WRITE(ah, addr, tmp);
f078f209 2518 }
f078f209
LR		 2519}
2520
cbe61d8a 2521void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2522{
f1dc5600 2523 u32 gpio_shift;
f078f209 2524
9680e8a3 2525 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2526
88c1f4f6
S		 2527 if (AR_DEVID_7010(ah)) {
2528 gpio_shift = gpio;
2529 REG_RMW(ah, AR7010_GPIO_OE,
2530 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2531 (AR7010_GPIO_OE_MASK << gpio_shift));
2532 return;
2533 }
f078f209 2534
88c1f4f6 2535 gpio_shift = gpio << 1;
f1dc5600
S		 2536 REG_RMW(ah,
2537 AR_GPIO_OE_OUT,
2538 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2539 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2540}
7322fd19 2541EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2542
cbe61d8a 2543u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2544{
cb33c412
SB		 2545#define MS_REG_READ(x, y) \
2546 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2547
2660b81a 2548 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2549 return 0xffffffff;
f078f209 2550
88c1f4f6
S		 2551 if (AR_DEVID_7010(ah)) {
2552 u32 val;
2553 val = REG_READ(ah, AR7010_GPIO_IN);
2554 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2555 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2556 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2557 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2558 else if (AR_SREV_9271(ah))
5b5fa355 2559 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2560 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2561 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2562 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2563 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2564 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2565 return MS_REG_READ(AR928X, gpio) != 0;
2566 else
2567 return MS_REG_READ(AR, gpio) != 0;
f078f209 2568}
7322fd19 2569EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2570
cbe61d8a 2571void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2572 u32 ah_signal_type)
f078f209 2573{
f1dc5600 2574 u32 gpio_shift;
f078f209 2575
88c1f4f6
S		 2576 if (AR_DEVID_7010(ah)) {
2577 gpio_shift = gpio;
2578 REG_RMW(ah, AR7010_GPIO_OE,
2579 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2580 (AR7010_GPIO_OE_MASK << gpio_shift));
2581 return;
2582 }
f078f209 2583
88c1f4f6 2584 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2585 gpio_shift = 2 * gpio;
f1dc5600
S		 2586 REG_RMW(ah,
2587 AR_GPIO_OE_OUT,
2588 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2589 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2590}
7322fd19 2591EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2592
cbe61d8a 2593void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2594{
88c1f4f6
S		 2595 if (AR_DEVID_7010(ah)) {
2596 val = val ? 0 : 1;
2597 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2598 AR_GPIO_BIT(gpio));
2599 return;
2600 }
2601
5b5fa355
S		 2602 if (AR_SREV_9271(ah))
2603 val = ~val;
2604
f1dc5600
S		 2605 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2606 AR_GPIO_BIT(gpio));
f078f209 2607}
7322fd19 2608EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2609
cbe61d8a 2610void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2611{
f1dc5600 2612 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2613}
7322fd19 2614EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2615
f1dc5600
S		 2616/*********************/
2617/* General Operation */
2618/*********************/
2619
cbe61d8a 2620u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2621{
f1dc5600
S		 2622 u32 bits = REG_READ(ah, AR_RX_FILTER);
2623 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2624
f1dc5600
S		 2625 if (phybits & AR_PHY_ERR_RADAR)
2626 bits |= ATH9K_RX_FILTER_PHYRADAR;
2627 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2628 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2629
f1dc5600 2630 return bits;
f078f209 2631}
7322fd19 2632EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2633
cbe61d8a 2634void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2635{
f1dc5600 2636 u32 phybits;
f078f209 2637
7d0d0df0
S		 2638 ENABLE_REGWRITE_BUFFER(ah);
2639
a4a2954f 2640 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2577c6e8
SB		 2641 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2642
7ea310be
S		 2643 REG_WRITE(ah, AR_RX_FILTER, bits);
2644
f1dc5600
S		 2645 phybits = 0;
2646 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2647 phybits |= AR_PHY_ERR_RADAR;
2648 if (bits & ATH9K_RX_FILTER_PHYERR)
2649 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2650 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2651
f1dc5600 2652 if (phybits)
ca7a4deb 2653 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2654 else
ca7a4deb 2655 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2656
2657 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2658}
7322fd19 2659EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2660
cbe61d8a 2661bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2662{
99922a45
RM		 2663 if (ath9k_hw_mci_is_enabled(ah))
2664 ar9003_mci_bt_gain_ctrl(ah);
2665
63a75b91
SB		 2666 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2667 return false;
2668
2669 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2670 ah->htc_reset_init = true;
63a75b91 2671 return true;
f1dc5600 2672}
7322fd19 2673EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2674
cbe61d8a 2675bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2676{
9ecdef4b 2677 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2678 return false;
f078f209 2679
63a75b91
SB		 2680 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2681 return false;
2682
2683 ath9k_hw_init_pll(ah, NULL);
2684 return true;
f078f209 2685}
7322fd19 2686EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2687
ca2c68cc
FF		 2688static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2689{
2690 enum eeprom_param gain_param;
2691
2692 if (IS_CHAN_2GHZ(chan))
2693 gain_param = EEP_ANTENNA_GAIN_2G;
2694 else
2695 gain_param = EEP_ANTENNA_GAIN_5G;
2696
2697 return ah->eep_ops->get_eeprom(ah, gain_param);
2698}
2699
64ea57d0
GJ		 2700void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2701 bool test)
ca2c68cc
FF		 2702{
2703 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2704 struct ieee80211_channel *channel;
2705 int chan_pwr, new_pwr, max_gain;
2706 int ant_gain, ant_reduction = 0;
2707
2708 if (!chan)
2709 return;
2710
2711 channel = chan->chan;
2712 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2713 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2714 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2715
2716 ant_gain = get_antenna_gain(ah, chan);
2717 if (ant_gain > max_gain)
2718 ant_reduction = ant_gain - max_gain;
2719
2720 ah->eep_ops->set_txpower(ah, chan,
2721 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2722 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2723}
2724
de40f316 2725void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2726{
ca2c68cc 2727 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2728 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2729 struct ieee80211_channel *channel = chan->chan;
9c204b46 2730
48ef5c42 2731 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2732 if (test)
ca2c68cc 2733 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2734
64ea57d0 2735 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2736
ca2c68cc
FF		 2737 if (test)
2738 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2739}
7322fd19 2740EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2741
cbe61d8a 2742void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2743{
2660b81a 2744 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2745}
7322fd19 2746EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2747
cbe61d8a 2748void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2749{
f1dc5600
S		 2750 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2751 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2752}
7322fd19 2753EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2754
f2b2143e 2755void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2756{
1510718d
LR		 2757 struct ath_common *common = ath9k_hw_common(ah);
2758
2759 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2760 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2761 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2762}
7322fd19 2763EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2764
1c0fc65e
BP		 2765#define ATH9K_MAX_TSF_READ 10
2766
cbe61d8a 2767u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2768{
1c0fc65e
BP		 2769 u32 tsf_lower, tsf_upper1, tsf_upper2;
2770 int i;
2771
2772 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2773 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2774 tsf_lower = REG_READ(ah, AR_TSF_L32);
2775 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2776 if (tsf_upper2 == tsf_upper1)
2777 break;
2778 tsf_upper1 = tsf_upper2;
2779 }
f078f209 2780
1c0fc65e 2781 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2782
1c0fc65e 2783 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2784}
7322fd19 2785EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2786
cbe61d8a 2787void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2788{
27abe060 2789 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2790 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2791}
7322fd19 2792EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2793
cbe61d8a 2794void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2795{
f9b604f6
GJ		 2796 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2797 AH_TSF_WRITE_TIMEOUT))
d2182b69 2798 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2799 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2800
f1dc5600
S		 2801 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2802}
7322fd19 2803EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2804
60ca9f87 2805void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 2806{
60ca9f87 2807 if (set)
2660b81a 2808 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2809 else
2660b81a 2810 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2811}
7322fd19 2812EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2813
e4744ec7 2814void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 2815{
2816 u32 macmode;
2817
e4744ec7 2818 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2819 macmode = AR_2040_JOINED_RX_CLEAR;
2820 else
2821 macmode = 0;
f078f209 2822
f1dc5600 2823 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2824}
ff155a45
VT		 2825
2826/* HW Generic timers configuration */
2827
2828static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2829{
2830 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2831 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2832 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2833 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2834 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2835 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2836 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2837 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2838 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2839 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2840 AR_NDP2_TIMER_MODE, 0x0002},
2841 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2842 AR_NDP2_TIMER_MODE, 0x0004},
2843 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2844 AR_NDP2_TIMER_MODE, 0x0008},
2845 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2846 AR_NDP2_TIMER_MODE, 0x0010},
2847 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2848 AR_NDP2_TIMER_MODE, 0x0020},
2849 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2850 AR_NDP2_TIMER_MODE, 0x0040},
2851 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2852 AR_NDP2_TIMER_MODE, 0x0080}
2853};
2854
2855/* HW generic timer primitives */
2856
dd347f2f 2857u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2858{
2859 return REG_READ(ah, AR_TSF_L32);
2860}
dd347f2f 2861EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2862
2863struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2864 void (*trigger)(void *),
2865 void (*overflow)(void *),
2866 void *arg,
2867 u8 timer_index)
2868{
2869 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2870 struct ath_gen_timer *timer;
2871
c67ce339
FF		 2872 if ((timer_index < AR_FIRST_NDP_TIMER) ||
2873 (timer_index >= ATH_MAX_GEN_TIMER))
2874 return NULL;
2875
ff155a45 2876 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 2877 if (timer == NULL)
ff155a45 2878 return NULL;
ff155a45
VT		 2879
2880 /* allocate a hardware generic timer slot */
2881 timer_table->timers[timer_index] = timer;
2882 timer->index = timer_index;
2883 timer->trigger = trigger;
2884 timer->overflow = overflow;
2885 timer->arg = arg;
2886
2887 return timer;
2888}
7322fd19 2889EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2890
cd9bf689
LR		 2891void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2892 struct ath_gen_timer *timer,
c67ce339 2893 u32 timer_next,
cd9bf689 2894 u32 timer_period)
ff155a45
VT		 2895{
2896 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 2897 u32 mask = 0;
788f6875 2898
c67ce339 2899 timer_table->timer_mask |= BIT(timer->index);
ff155a45 2900
ff155a45
VT		 2901 /*
2902 * Program generic timer registers
2903 */
2904 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2905 timer_next);
2906 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2907 timer_period);
2908 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2909 gen_tmr_configuration[timer->index].mode_mask);
2910
a4a2954f 2911 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 2912 /*
423e38e8 2913 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 2914 * to use. But we still follow the old rule, 0 - 7 use tsf and
2915 * 8 - 15 use tsf2.
2916 */
2917 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2918 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2919 (1 << timer->index));
2920 else
2921 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2922 (1 << timer->index));
2923 }
2924
c67ce339
FF		 2925 if (timer->trigger)
2926 mask |= SM(AR_GENTMR_BIT(timer->index),
2927 AR_IMR_S5_GENTIMER_TRIG);
2928 if (timer->overflow)
2929 mask |= SM(AR_GENTMR_BIT(timer->index),
2930 AR_IMR_S5_GENTIMER_THRESH);
2931
2932 REG_SET_BIT(ah, AR_IMR_S5, mask);
2933
2934 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
2935 ah->imask |= ATH9K_INT_GENTIMER;
2936 ath9k_hw_set_interrupts(ah);
2937 }
ff155a45 2938}
7322fd19 2939EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2940
cd9bf689 2941void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2942{
2943 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2944
ff155a45
VT		 2945 /* Clear generic timer enable bits. */
2946 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2947 gen_tmr_configuration[timer->index].mode_mask);
2948
b7f59766
SM		 2949 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2950 /*
2951 * Need to switch back to TSF if it was using TSF2.
2952 */
2953 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
2954 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2955 (1 << timer->index));
2956 }
2957 }
2958
ff155a45
VT		 2959 /* Disable both trigger and thresh interrupt masks */
2960 REG_CLR_BIT(ah, AR_IMR_S5,
2961 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2962 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2963
c67ce339
FF		 2964 timer_table->timer_mask &= ~BIT(timer->index);
2965
2966 if (timer_table->timer_mask == 0) {
2967 ah->imask &= ~ATH9K_INT_GENTIMER;
2968 ath9k_hw_set_interrupts(ah);
2969 }
ff155a45 2970}
7322fd19 2971EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2972
2973void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2974{
2975 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2976
2977 /* free the hardware generic timer slot */
2978 timer_table->timers[timer->index] = NULL;
2979 kfree(timer);
2980}
7322fd19 2981EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2982
2983/*
2984 * Generic Timer Interrupts handling
2985 */
2986void ath_gen_timer_isr(struct ath_hw *ah)
2987{
2988 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2989 struct ath_gen_timer *timer;
c67ce339
FF		 2990 unsigned long trigger_mask, thresh_mask;
2991 unsigned int index;
ff155a45
VT		 2992
2993 /* get hardware generic timer interrupt status */
2994 trigger_mask = ah->intr_gen_timer_trigger;
2995 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 2996 trigger_mask &= timer_table->timer_mask;
2997 thresh_mask &= timer_table->timer_mask;
ff155a45 2998
c67ce339 2999 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3000 timer = timer_table->timers[index];
c67ce339
FF		 3001 if (!timer)
3002 continue;
3003 if (!timer->overflow)
3004 continue;
a6a172b2
FF		 3005
3006 trigger_mask &= ~BIT(index);
ff155a45
VT		 3007 timer->overflow(timer->arg);
3008 }
3009
c67ce339 3010 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3011 timer = timer_table->timers[index];
c67ce339
FF		 3012 if (!timer)
3013 continue;
3014 if (!timer->trigger)
3015 continue;
ff155a45
VT		 3016 timer->trigger(timer->arg);
3017 }
3018}
7322fd19 3019EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3020
05020d23
S		 3021/********/
3022/* HTC */
3023/********/
3024
2da4f01a
LR		 3025static struct {
3026 u32 version;
3027 const char * name;
3028} ath_mac_bb_names[] = {
3029 /* Devices with external radios */
3030 { AR_SREV_VERSION_5416_PCI, "5416" },
3031 { AR_SREV_VERSION_5416_PCIE, "5418" },
3032 { AR_SREV_VERSION_9100, "9100" },
3033 { AR_SREV_VERSION_9160, "9160" },
3034 /* Single-chip solutions */
3035 { AR_SREV_VERSION_9280, "9280" },
3036 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3037 { AR_SREV_VERSION_9287, "9287" },
3038 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3039 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3040 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3041 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3042 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3043 { AR_SREV_VERSION_9462, "9462" },
485124cb 3044 { AR_SREV_VERSION_9550, "9550" },
77fac465 3045 { AR_SREV_VERSION_9565, "9565" },
2da4f01a
LR		 3046};
3047
3048/* For devices with external radios */
3049static struct {
3050 u16 version;
3051 const char * name;
3052} ath_rf_names[] = {
3053 { 0, "5133" },
3054 { AR_RAD5133_SREV_MAJOR, "5133" },
3055 { AR_RAD5122_SREV_MAJOR, "5122" },
3056 { AR_RAD2133_SREV_MAJOR, "2133" },
3057 { AR_RAD2122_SREV_MAJOR, "2122" }
3058};
3059
3060/*
3061 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3062 */
f934c4d9 3063static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3064{
3065 int i;
3066
3067 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3068 if (ath_mac_bb_names[i].version == mac_bb_version) {
3069 return ath_mac_bb_names[i].name;
3070 }
3071 }
3072
3073 return "????";
3074}
2da4f01a
LR		 3075
3076/*
3077 * Return the RF name. "????" is returned if the RF is unknown.
3078 * Used for devices with external radios.
3079 */
f934c4d9 3080static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3081{
3082 int i;
3083
3084 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3085 if (ath_rf_names[i].version == rf_version) {
3086 return ath_rf_names[i].name;
3087 }
3088 }
3089
3090 return "????";
3091}
f934c4d9
LR		 3092
3093void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3094{
3095 int used;
3096
3097 /* chipsets >= AR9280 are single-chip */
7a37081e 3098 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3099 used = scnprintf(hw_name, len,
3100 "Atheros AR%s Rev:%x",
3101 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3102 ah->hw_version.macRev);
f934c4d9
LR		 3103 }
3104 else {
5e88ba62
ZK		 3105 used = scnprintf(hw_name, len,
3106 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3107 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3108 ah->hw_version.macRev,
3109 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3110 & AR_RADIO_SREV_MAJOR)),
3111 ah->hw_version.phyRev);
f934c4d9
LR		 3112 }
3113
3114 hw_name[used] = '\0';
3115}
3116EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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