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ath9k: add AR9330 specific PLL initialization
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
f078f209
LR		 19#include <asm/unaligned.h>
20
af03abec 21#include "hw.h"
d70357d5 22#include "hw-ops.h"
cfe8cba9 23#include "rc.h"
b622a720 24#include "ar9003_mac.h"
f078f209 25
cbe61d8a 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 27
7322fd19
LR		 28MODULE_AUTHOR("Atheros Communications");
29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31MODULE_LICENSE("Dual BSD/GPL");
32
33static int __init ath9k_init(void)
34{
35 return 0;
36}
37module_init(ath9k_init);
38
39static void __exit ath9k_exit(void)
40{
41 return;
42}
43module_exit(ath9k_exit);
44
d70357d5
LR		 45/* Private hardware callbacks */
46
47static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48{
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50}
51
52static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55}
56
64773964
LR		 57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59{
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61}
62
991312d8
LR		 63static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64{
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69}
70
e36b27af
LR		 71static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72{
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78}
79
f1dc5600
S		 80/********************/
81/* Helper Functions */
82/********************/
f078f209 83
dfdac8ac 84static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 85{
b002a4a9 86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
dfdac8ac
FF		 87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
cbe61d8a 89
2660b81a 90 if (!ah->curchan) /* should really check for CCK instead */
dfdac8ac
FF		 91 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 96 else
dfdac8ac
FF		 97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
98
99 if (conf_is_ht40(conf))
100 clockrate *= 2;
101
102 common->clockrate = clockrate;
f1dc5600
S		 103}
104
cbe61d8a 105static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 106{
dfdac8ac 107 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 108
dfdac8ac 109 return usecs * common->clockrate;
f1dc5600 110}
f078f209 111
0caa7b14 112bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 113{
114 int i;
115
0caa7b14
S		 116 BUG_ON(timeout < AH_TIME_QUANTUM);
117
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 119 if ((REG_READ(ah, reg) & mask) == val)
120 return true;
121
122 udelay(AH_TIME_QUANTUM);
123 }
04bd4638 124
226afe68
JP		 125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 128
f1dc5600 129 return false;
f078f209 130}
7322fd19 131EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 132
a9b6b256
FF		 133void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
134 int column, unsigned int *writecnt)
135{
136 int r;
137
138 ENABLE_REGWRITE_BUFFER(ah);
139 for (r = 0; r < array->ia_rows; r++) {
140 REG_WRITE(ah, INI_RA(array, r, 0),
141 INI_RA(array, r, column));
142 DO_DELAY(*writecnt);
143 }
144 REGWRITE_BUFFER_FLUSH(ah);
145}
146
f078f209
LR		 147u32 ath9k_hw_reverse_bits(u32 val, u32 n)
148{
149 u32 retval;
150 int i;
151
152 for (i = 0, retval = 0; i < n; i++) {
153 retval = (retval << 1) | (val & 1);
154 val >>= 1;
155 }
156 return retval;
157}
158
cbe61d8a 159u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 160 u8 phy, int kbps,
f1dc5600
S		 161 u32 frameLen, u16 rateix,
162 bool shortPreamble)
f078f209 163{
f1dc5600 164 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 165
f1dc5600
S		 166 if (kbps == 0)
167 return 0;
f078f209 168
545750d3 169 switch (phy) {
46d14a58 170 case WLAN_RC_PHY_CCK:
f1dc5600 171 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 172 if (shortPreamble)
f1dc5600
S		 173 phyTime >>= 1;
174 numBits = frameLen << 3;
175 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
176 break;
46d14a58 177 case WLAN_RC_PHY_OFDM:
2660b81a 178 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 179 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
180 numBits = OFDM_PLCP_BITS + (frameLen << 3);
181 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
182 txTime = OFDM_SIFS_TIME_QUARTER
183 + OFDM_PREAMBLE_TIME_QUARTER
184 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 185 } else if (ah->curchan &&
186 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_HALF +
191 OFDM_PREAMBLE_TIME_HALF
192 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
193 } else {
194 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
195 numBits = OFDM_PLCP_BITS + (frameLen << 3);
196 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
197 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
198 + (numSymbols * OFDM_SYMBOL_TIME);
199 }
200 break;
201 default:
3800276a
JP		 202 ath_err(ath9k_hw_common(ah),
203 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 204 txTime = 0;
205 break;
206 }
f078f209 207
f1dc5600
S		 208 return txTime;
209}
7322fd19 210EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 211
cbe61d8a 212void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 213 struct ath9k_channel *chan,
214 struct chan_centers *centers)
f078f209 215{
f1dc5600 216 int8_t extoff;
f078f209 217
f1dc5600
S		 218 if (!IS_CHAN_HT40(chan)) {
219 centers->ctl_center = centers->ext_center =
220 centers->synth_center = chan->channel;
221 return;
f078f209 222 }
f078f209 223
f1dc5600
S		 224 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
225 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
226 centers->synth_center =
227 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
228 extoff = 1;
229 } else {
230 centers->synth_center =
231 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
232 extoff = -1;
233 }
f078f209 234
f1dc5600
S		 235 centers->ctl_center =
236 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 237 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 238 centers->ext_center =
6420014c 239 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 240}
241
f1dc5600
S		 242/******************/
243/* Chip Revisions */
244/******************/
245
cbe61d8a 246static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 247{
f1dc5600 248 u32 val;
f078f209 249
ecb1d385
VT		 250 switch (ah->hw_version.devid) {
251 case AR5416_AR9100_DEVID:
252 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
253 break;
3762561a
GJ		 254 case AR9300_DEVID_AR9330:
255 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
256 if (ah->get_mac_revision) {
257 ah->hw_version.macRev = ah->get_mac_revision();
258 } else {
259 val = REG_READ(ah, AR_SREV);
260 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
261 }
262 return;
ecb1d385
VT		 263 case AR9300_DEVID_AR9340:
264 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
265 val = REG_READ(ah, AR_SREV);
266 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
267 return;
268 }
269
f1dc5600 270 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 271
f1dc5600
S		 272 if (val == 0xFF) {
273 val = REG_READ(ah, AR_SREV);
d535a42a
S		 274 ah->hw_version.macVersion =
275 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
276 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 277 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 278 } else {
279 if (!AR_SREV_9100(ah))
d535a42a 280 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 281
d535a42a 282 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 283
d535a42a 284 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 285 ah->is_pciexpress = true;
f1dc5600 286 }
f078f209
LR		 287}
288
f1dc5600
S		 289/************************************/
290/* HW Attach, Detach, Init Routines */
291/************************************/
292
cbe61d8a 293static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 294{
040b74f7 295 if (!AR_SREV_5416(ah))
f1dc5600 296 return;
f078f209 297
f1dc5600
S		 298 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
299 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
300 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
301 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
302 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
303 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
304 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
305 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
306 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 307
f1dc5600 308 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 309}
310
1f3f0618 311/* This should work for all families including legacy */
cbe61d8a 312static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 313{
c46917bb 314 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 315 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 316 u32 regHold[2];
07b2fa5a
JP		 317 static const u32 patternData[4] = {
318 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
319 };
1f3f0618 320 int i, j, loop_max;
f078f209 321
1f3f0618
SB		 322 if (!AR_SREV_9300_20_OR_LATER(ah)) {
323 loop_max = 2;
324 regAddr[1] = AR_PHY_BASE + (8 << 2);
325 } else
326 loop_max = 1;
327
328 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 329 u32 addr = regAddr[i];
330 u32 wrData, rdData;
f078f209 331
f1dc5600
S		 332 regHold[i] = REG_READ(ah, addr);
333 for (j = 0; j < 0x100; j++) {
334 wrData = (j << 16) | j;
335 REG_WRITE(ah, addr, wrData);
336 rdData = REG_READ(ah, addr);
337 if (rdData != wrData) {
3800276a
JP		 338 ath_err(common,
339 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
340 addr, wrData, rdData);
f1dc5600
S		 341 return false;
342 }
343 }
344 for (j = 0; j < 4; j++) {
345 wrData = patternData[j];
346 REG_WRITE(ah, addr, wrData);
347 rdData = REG_READ(ah, addr);
348 if (wrData != rdData) {
3800276a
JP		 349 ath_err(common,
350 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
351 addr, wrData, rdData);
f1dc5600
S		 352 return false;
353 }
f078f209 354 }
f1dc5600 355 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 356 }
f1dc5600 357 udelay(100);
cbe61d8a 358
f078f209
LR		 359 return true;
360}
361
b8b0f377 362static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 363{
364 int i;
f078f209 365
2660b81a
S		 366 ah->config.dma_beacon_response_time = 2;
367 ah->config.sw_beacon_response_time = 10;
368 ah->config.additional_swba_backoff = 0;
369 ah->config.ack_6mb = 0x0;
370 ah->config.cwm_ignore_extcca = 0;
371 ah->config.pcie_powersave_enable = 0;
2660b81a 372 ah->config.pcie_clock_req = 0;
2660b81a
S		 373 ah->config.pcie_waen = 0;
374 ah->config.analog_shiftreg = 1;
03c72518 375 ah->config.enable_ani = true;
f078f209 376
f1dc5600 377 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 378 ah->config.spurchans[i][0] = AR_NO_SPUR;
379 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 380 }
381
6f481010
LR		 382 /* PAPRD needs some more work to be enabled */
383 ah->config.paprd_disable = 1;
384
0ce024cb 385 ah->config.rx_intr_mitigation = true;
6a0ec30a 386 ah->config.pcieSerDesWrite = true;
6158425b
LR		 387
388 /*
389 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
390 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
391 * This means we use it for all AR5416 devices, and the few
392 * minor PCI AR9280 devices out there.
393 *
394 * Serialization is required because these devices do not handle
395 * well the case of two concurrent reads/writes due to the latency
396 * involved. During one read/write another read/write can be issued
397 * on another CPU while the previous read/write may still be working
398 * on our hardware, if we hit this case the hardware poops in a loop.
399 * We prevent this by serializing reads and writes.
400 *
401 * This issue is not present on PCI-Express devices or pre-AR5416
402 * devices (legacy, 802.11abg).
403 */
404 if (num_possible_cpus() > 1)
2d6a5e95 405 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 406}
407
50aca25b 408static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 409{
608b88cb
LR		 410 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
411
412 regulatory->country_code = CTRY_DEFAULT;
413 regulatory->power_limit = MAX_RATE_POWER;
414 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
415
d535a42a 416 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 417 ah->hw_version.subvendorid = 0;
f078f209 418
2660b81a 419 ah->atim_window = 0;
16f2411f
FF		 420 ah->sta_id1_defaults =
421 AR_STA_ID1_CRPT_MIC_ENABLE |
422 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 423 if (AR_SREV_9100(ah))
424 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
2660b81a 425 ah->enable_32kHz_clock = DONT_USE_32KHZ;
4357c6bf 426 ah->slottime = 20;
2660b81a 427 ah->globaltxtimeout = (u32) -1;
cbdec975 428 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 429}
430
cbe61d8a 431static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 432{
1510718d 433 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 434 u32 sum;
435 int i;
436 u16 eeval;
07b2fa5a 437 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 438
439 sum = 0;
440 for (i = 0; i < 3; i++) {
49101676 441 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 442 sum += eeval;
1510718d
LR		 443 common->macaddr[2 * i] = eeval >> 8;
444 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 445 }
d8baa939 446 if (sum == 0 || sum == 0xffff * 3)
f078f209 447 return -EADDRNOTAVAIL;
f078f209
LR		 448
449 return 0;
450}
451
f637cfd6 452static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 453{
6cae913d 454 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 455 int ecode;
f078f209 456
6cae913d 457 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 458 if (!ath9k_hw_chip_test(ah))
459 return -ENODEV;
460 }
f078f209 461
ebd5a14a
LR		 462 if (!AR_SREV_9300_20_OR_LATER(ah)) {
463 ecode = ar9002_hw_rf_claim(ah);
464 if (ecode != 0)
465 return ecode;
466 }
f078f209 467
f637cfd6 468 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 469 if (ecode != 0)
470 return ecode;
7d01b221 471
226afe68
JP		 472 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
473 "Eeprom VER: %d, REV: %d\n",
474 ah->eep_ops->get_eeprom_ver(ah),
475 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 476
8fe65368
LR		 477 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
478 if (ecode) {
3800276a
JP		 479 ath_err(ath9k_hw_common(ah),
480 "Failed allocating banks for external radio\n");
48a7c3df 481 ath9k_hw_rf_free_ext_banks(ah);
8fe65368 482 return ecode;
574d6b12 483 }
f078f209 484
070c4d50 485 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
f1dc5600 486 ath9k_hw_ani_setup(ah);
f637cfd6 487 ath9k_hw_ani_init(ah);
f078f209
LR		 488 }
489
f078f209
LR		 490 return 0;
491}
492
8525f280 493static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 494{
8525f280
LR		 495 if (AR_SREV_9300_20_OR_LATER(ah))
496 ar9003_hw_attach_ops(ah);
497 else
498 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 499}
500
d70357d5
LR		 501/* Called for all hardware families */
502static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 503{
c46917bb 504 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 505 int r = 0;
aa4058ae 506
ac45c12d
SB		 507 ath9k_hw_read_revisions(ah);
508
0a8d7cb0
SB		 509 /*
510 * Read back AR_WA into a permanent copy and set bits 14 and 17.
511 * We need to do this to avoid RMW of this register. We cannot
512 * read the reg when chip is asleep.
513 */
514 ah->WARegVal = REG_READ(ah, AR_WA);
515 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
516 AR_WA_ASPM_TIMER_BASED_DISABLE);
517
aa4058ae 518 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 519 ath_err(common, "Couldn't reset chip\n");
95fafca2 520 return -EIO;
aa4058ae
LR		 521 }
522
bab1f62e
LR		 523 ath9k_hw_init_defaults(ah);
524 ath9k_hw_init_config(ah);
525
8525f280 526 ath9k_hw_attach_ops(ah);
d70357d5 527
9ecdef4b 528 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 529 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 530 return -EIO;
aa4058ae
LR		 531 }
532
533 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
534 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
4c85ab11
JL		 535 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
536 !ah->is_pciexpress)) {
aa4058ae
LR		 537 ah->config.serialize_regmode =
538 SER_REG_MODE_ON;
539 } else {
540 ah->config.serialize_regmode =
541 SER_REG_MODE_OFF;
542 }
543 }
544
226afe68 545 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 546 ah->config.serialize_regmode);
547
f4709fdf
LR		 548 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
549 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
550 else
551 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
552
6da5a720
FF		 553 switch (ah->hw_version.macVersion) {
554 case AR_SREV_VERSION_5416_PCI:
555 case AR_SREV_VERSION_5416_PCIE:
556 case AR_SREV_VERSION_9160:
557 case AR_SREV_VERSION_9100:
558 case AR_SREV_VERSION_9280:
559 case AR_SREV_VERSION_9285:
560 case AR_SREV_VERSION_9287:
561 case AR_SREV_VERSION_9271:
562 case AR_SREV_VERSION_9300:
2c8e5937 563 case AR_SREV_VERSION_9330:
6da5a720 564 case AR_SREV_VERSION_9485:
bca04689 565 case AR_SREV_VERSION_9340:
6da5a720
FF		 566 break;
567 default:
3800276a
JP		 568 ath_err(common,
569 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
570 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 571 return -EOPNOTSUPP;
aa4058ae
LR		 572 }
573
2c8e5937
GJ		 574 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
575 AR_SREV_9330(ah))
d7e7d229
LR		 576 ah->is_pciexpress = false;
577
aa4058ae 578 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 579 ath9k_hw_init_cal_settings(ah);
580
581 ah->ani_function = ATH9K_ANI_ALL;
7a37081e 582 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 583 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 584 if (!AR_SREV_9300_20_OR_LATER(ah))
585 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae
LR		 586
587 ath9k_hw_init_mode_regs(ah);
588
9a658d2b 589
aa4058ae 590 if (ah->is_pciexpress)
93b1b37f 591 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 592 else
593 ath9k_hw_disablepcie(ah);
594
d8f492b7
LR		 595 if (!AR_SREV_9300_20_OR_LATER(ah))
596 ar9002_hw_cck_chan14_spread(ah);
193cd458 597
f637cfd6 598 r = ath9k_hw_post_init(ah);
aa4058ae 599 if (r)
95fafca2 600 return r;
aa4058ae
LR		 601
602 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 603 r = ath9k_hw_fill_cap_info(ah);
604 if (r)
605 return r;
606
4f3acf81
LR		 607 r = ath9k_hw_init_macaddr(ah);
608 if (r) {
3800276a 609 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 610 return r;
f078f209
LR		 611 }
612
d7e7d229 613 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 614 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 615 else
2660b81a 616 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 617
aea702b7 618 ah->bb_watchdog_timeout_ms = 25;
f078f209 619
211f5859
LR		 620 common->state = ATH_HW_INITIALIZED;
621
4f3acf81 622 return 0;
f078f209
LR		 623}
624
d70357d5 625int ath9k_hw_init(struct ath_hw *ah)
f078f209 626{
d70357d5
LR		 627 int ret;
628 struct ath_common *common = ath9k_hw_common(ah);
f078f209 629
d70357d5
LR		 630 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
631 switch (ah->hw_version.devid) {
632 case AR5416_DEVID_PCI:
633 case AR5416_DEVID_PCIE:
634 case AR5416_AR9100_DEVID:
635 case AR9160_DEVID_PCI:
636 case AR9280_DEVID_PCI:
637 case AR9280_DEVID_PCIE:
638 case AR9285_DEVID_PCIE:
db3cc53a
SB		 639 case AR9287_DEVID_PCI:
640 case AR9287_DEVID_PCIE:
d70357d5 641 case AR2427_DEVID_PCIE:
db3cc53a 642 case AR9300_DEVID_PCIE:
3050c914 643 case AR9300_DEVID_AR9485_PCIE:
bca04689 644 case AR9300_DEVID_AR9340:
d70357d5
LR		 645 break;
646 default:
647 if (common->bus_ops->ath_bus_type == ATH_USB)
648 break;
3800276a
JP		 649 ath_err(common, "Hardware device ID 0x%04x not supported\n",
650 ah->hw_version.devid);
d70357d5
LR		 651 return -EOPNOTSUPP;
652 }
f078f209 653
d70357d5
LR		 654 ret = __ath9k_hw_init(ah);
655 if (ret) {
3800276a
JP		 656 ath_err(common,
657 "Unable to initialize hardware; initialization status: %d\n",
658 ret);
d70357d5
LR		 659 return ret;
660 }
f078f209 661
d70357d5 662 return 0;
f078f209 663}
d70357d5 664EXPORT_SYMBOL(ath9k_hw_init);
f078f209 665
cbe61d8a 666static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 667{
7d0d0df0
S		 668 ENABLE_REGWRITE_BUFFER(ah);
669
f1dc5600
S		 670 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
671 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 672
f1dc5600
S		 673 REG_WRITE(ah, AR_QOS_NO_ACK,
674 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
675 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
676 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
677
678 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
679 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
680 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
681 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
682 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 683
684 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 685}
686
b84628eb 687u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 688{
ca7a4deb
FF		 689 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
690 udelay(100);
691 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 692
ca7a4deb
FF		 693 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
694 udelay(100);
b1415819 695
ca7a4deb 696 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 697}
698EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
699
cbe61d8a 700static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 701 struct ath9k_channel *chan)
f078f209 702{
d09b17f7
VT		 703 u32 pll;
704
22983c30 705 if (AR_SREV_9485(ah)) {
22983c30 706
3dfd7f60
VT		 707 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
709 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
710 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
711 AR_CH0_DPLL2_KD, 0x40);
712 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
713 AR_CH0_DPLL2_KI, 0x4);
22983c30 714
3dfd7f60
VT		 715 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
716 AR_CH0_BB_DPLL1_REFDIV, 0x5);
717 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
718 AR_CH0_BB_DPLL1_NINI, 0x58);
719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
720 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 721
722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 723 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
724 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
725 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 726 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 727 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 728
3dfd7f60 729 /* program BB PLL phase_shift to 0x6 */
22983c30 730 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 731 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
732
733 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
734 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 735 udelay(1000);
a5415d62
GJ		 736 } else if (AR_SREV_9330(ah)) {
737 u32 ddr_dpll2, pll_control2, kd;
738
739 if (ah->is_clk_25mhz) {
740 ddr_dpll2 = 0x18e82f01;
741 pll_control2 = 0xe04a3d;
742 kd = 0x1d;
743 } else {
744 ddr_dpll2 = 0x19e82f01;
745 pll_control2 = 0x886666;
746 kd = 0x3d;
747 }
748
749 /* program DDR PLL ki and kd value */
750 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
751
752 /* program DDR PLL phase_shift */
753 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
754 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
755
756 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
757 udelay(1000);
758
759 /* program refdiv, nint, frac to RTC register */
760 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
761
762 /* program BB PLL kd and ki value */
763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
764 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
765
766 /* program BB PLL phase_shift */
767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
768 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
0b488ac6
VT		 769 } else if (AR_SREV_9340(ah)) {
770 u32 regval, pll2_divint, pll2_divfrac, refdiv;
771
772 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
773 udelay(1000);
774
775 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
776 udelay(100);
777
778 if (ah->is_clk_25mhz) {
779 pll2_divint = 0x54;
780 pll2_divfrac = 0x1eb85;
781 refdiv = 3;
782 } else {
783 pll2_divint = 88;
784 pll2_divfrac = 0;
785 refdiv = 5;
786 }
787
788 regval = REG_READ(ah, AR_PHY_PLL_MODE);
789 regval |= (0x1 << 16);
790 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
791 udelay(100);
792
793 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
794 (pll2_divint << 18) | pll2_divfrac);
795 udelay(100);
796
797 regval = REG_READ(ah, AR_PHY_PLL_MODE);
798 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
799 (0x4 << 26) | (0x18 << 19);
800 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
801 REG_WRITE(ah, AR_PHY_PLL_MODE,
802 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
803 udelay(1000);
22983c30 804 }
d09b17f7
VT		 805
806 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 807
d03a66c1 808 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 809
a5415d62 810 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
3dfd7f60
VT		 811 udelay(1000);
812
c75724d1
LR		 813 /* Switch the core clock for ar9271 to 117Mhz */
814 if (AR_SREV_9271(ah)) {
25e2ab17
S		 815 udelay(500);
816 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 817 }
818
f1dc5600
S		 819 udelay(RTC_PLL_SETTLE_DELAY);
820
821 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6
VT		 822
823 if (AR_SREV_9340(ah)) {
824 if (ah->is_clk_25mhz) {
825 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
826 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
827 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
828 } else {
829 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
830 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
831 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
832 }
833 udelay(100);
834 }
f078f209
LR		 835}
836
cbe61d8a 837static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 838 enum nl80211_iftype opmode)
f078f209 839{
79d1d2b8 840 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 841 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 842 AR_IMR_TXURN |
843 AR_IMR_RXERR |
844 AR_IMR_RXORN |
845 AR_IMR_BCNMISC;
f078f209 846
79d1d2b8
VT		 847 if (AR_SREV_9340(ah))
848 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
849
66860240
VT		 850 if (AR_SREV_9300_20_OR_LATER(ah)) {
851 imr_reg |= AR_IMR_RXOK_HP;
852 if (ah->config.rx_intr_mitigation)
853 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
854 else
855 imr_reg |= AR_IMR_RXOK_LP;
f078f209 856
66860240
VT		 857 } else {
858 if (ah->config.rx_intr_mitigation)
859 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
860 else
861 imr_reg |= AR_IMR_RXOK;
862 }
f078f209 863
66860240
VT		 864 if (ah->config.tx_intr_mitigation)
865 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
866 else
867 imr_reg |= AR_IMR_TXOK;
f078f209 868
d97809db 869 if (opmode == NL80211_IFTYPE_AP)
152d530d 870 imr_reg |= AR_IMR_MIB;
f078f209 871
7d0d0df0
S		 872 ENABLE_REGWRITE_BUFFER(ah);
873
152d530d 874 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 875 ah->imrs2_reg |= AR_IMR_S2_GTT;
876 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 877
f1dc5600
S		 878 if (!AR_SREV_9100(ah)) {
879 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 880 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 881 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
882 }
66860240 883
7d0d0df0 884 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 885
66860240
VT		 886 if (AR_SREV_9300_20_OR_LATER(ah)) {
887 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
888 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
889 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
890 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
891 }
f078f209
LR		 892}
893
0005baf4 894static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 895{
0005baf4
FF		 896 u32 val = ath9k_hw_mac_to_clks(ah, us);
897 val = min(val, (u32) 0xFFFF);
898 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 899}
900
0005baf4 901static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 902{
0005baf4
FF		 903 u32 val = ath9k_hw_mac_to_clks(ah, us);
904 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
905 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
906}
907
908static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
909{
910 u32 val = ath9k_hw_mac_to_clks(ah, us);
911 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
912 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 913}
f1dc5600 914
cbe61d8a 915static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 916{
f078f209 917 if (tu > 0xFFFF) {
226afe68
JP		 918 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
919 "bad global tx timeout %u\n", tu);
2660b81a 920 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 921 return false;
922 } else {
923 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 924 ah->globaltxtimeout = tu;
f078f209
LR		 925 return true;
926 }
927}
928
0005baf4 929void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 930{
0005baf4
FF		 931 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
932 int acktimeout;
e239d859 933 int slottime;
0005baf4
FF		 934 int sifstime;
935
226afe68
JP		 936 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
937 ah->misc_mode);
f078f209 938
2660b81a 939 if (ah->misc_mode != 0)
ca7a4deb 940 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4
FF		 941
942 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
943 sifstime = 16;
944 else
945 sifstime = 10;
946
e239d859
FF		 947 /* As defined by IEEE 802.11-2007 17.3.8.6 */
948 slottime = ah->slottime + 3 * ah->coverage_class;
949 acktimeout = slottime + sifstime;
42c4568a
FF		 950
951 /*
952 * Workaround for early ACK timeouts, add an offset to match the
953 * initval's 64us ack timeout value.
954 * This was initially only meant to work around an issue with delayed
955 * BA frames in some implementations, but it has been found to fix ACK
956 * timeout issues in other cases as well.
957 */
958 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
959 acktimeout += 64 - sifstime - ah->slottime;
960
caabf2bf 961 ath9k_hw_setslottime(ah, ah->slottime);
0005baf4
FF		 962 ath9k_hw_set_ack_timeout(ah, acktimeout);
963 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 964 if (ah->globaltxtimeout != (u32) -1)
965 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 966}
0005baf4 967EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 968
285f2dda 969void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 970{
211f5859
LR		 971 struct ath_common *common = ath9k_hw_common(ah);
972
736b3a27 973 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 974 goto free_hw;
975
9ecdef4b 976 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 977
978free_hw:
8fe65368 979 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 980}
285f2dda 981EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 982
f1dc5600
S		 983/*******/
984/* INI */
985/*******/
986
8fe65368 987u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 988{
989 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
990
991 if (IS_CHAN_B(chan))
992 ctl |= CTL_11B;
993 else if (IS_CHAN_G(chan))
994 ctl |= CTL_11G;
995 else
996 ctl |= CTL_11A;
997
998 return ctl;
999}
1000
f1dc5600
S		 1001/****************************************/
1002/* Reset and Channel Switching Routines */
1003/****************************************/
f1dc5600 1004
cbe61d8a 1005static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1006{
57b32227 1007 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 1008
7d0d0df0
S		 1009 ENABLE_REGWRITE_BUFFER(ah);
1010
d7e7d229
LR		 1011 /*
1012 * set AHB_MODE not to do cacheline prefetches
1013 */
ca7a4deb
FF		 1014 if (!AR_SREV_9300_20_OR_LATER(ah))
1015 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1016
d7e7d229
LR		 1017 /*
1018 * let mac dma reads be in 128 byte chunks
1019 */
ca7a4deb 1020 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1021
7d0d0df0 1022 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1023
d7e7d229
LR		 1024 /*
1025 * Restore TX Trigger Level to its pre-reset value.
1026 * The initial value depends on whether aggregation is enabled, and is
1027 * adjusted whenever underruns are detected.
1028 */
57b32227
FF		 1029 if (!AR_SREV_9300_20_OR_LATER(ah))
1030 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1031
7d0d0df0 1032 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1033
d7e7d229
LR		 1034 /*
1035 * let mac dma writes be in 128 byte chunks
1036 */
ca7a4deb 1037 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1038
d7e7d229
LR		 1039 /*
1040 * Setup receive FIFO threshold to hold off TX activities
1041 */
f1dc5600
S		 1042 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1043
57b32227
FF		 1044 if (AR_SREV_9300_20_OR_LATER(ah)) {
1045 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1046 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1047
1048 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1049 ah->caps.rx_status_len);
1050 }
1051
d7e7d229
LR		 1052 /*
1053 * reduce the number of usable entries in PCU TXBUF to avoid
1054 * wrap around issues.
1055 */
f1dc5600 1056 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1057 /* For AR9285 the number of Fifos are reduced to half.
1058 * So set the usable tx buf size also to half to
1059 * avoid data/delimiter underruns
1060 */
f1dc5600
S		 1061 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1062 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1063 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1064 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1065 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1066 }
744d4025 1067
7d0d0df0 1068 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1069
744d4025
VT		 1070 if (AR_SREV_9300_20_OR_LATER(ah))
1071 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1072}
1073
cbe61d8a 1074static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1075{
ca7a4deb
FF		 1076 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1077 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1078
f1dc5600 1079 switch (opmode) {
d97809db 1080 case NL80211_IFTYPE_ADHOC:
9cb5412b 1081 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb 1082 set |= AR_STA_ID1_ADHOC;
f1dc5600 1083 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1084 break;
ca7a4deb
FF		 1085 case NL80211_IFTYPE_AP:
1086 set |= AR_STA_ID1_STA_AP;
1087 /* fall through */
d97809db 1088 case NL80211_IFTYPE_STATION:
ca7a4deb 1089 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1090 break;
5f841b41 1091 default:
ca7a4deb
FF		 1092 if (!ah->is_monitoring)
1093 set = 0;
5f841b41 1094 break;
f1dc5600 1095 }
ca7a4deb 1096 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1097}
1098
8fe65368
LR		 1099void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1100 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1101{
1102 u32 coef_exp, coef_man;
1103
1104 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1105 if ((coef_scaled >> coef_exp) & 0x1)
1106 break;
1107
1108 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1109
1110 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1111
1112 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1113 *coef_exponent = coef_exp - 16;
1114}
1115
cbe61d8a 1116static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1117{
1118 u32 rst_flags;
1119 u32 tmpReg;
1120
70768496 1121 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1122 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1123 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1124 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1125 }
1126
7d0d0df0
S		 1127 ENABLE_REGWRITE_BUFFER(ah);
1128
9a658d2b
LR		 1129 if (AR_SREV_9300_20_OR_LATER(ah)) {
1130 REG_WRITE(ah, AR_WA, ah->WARegVal);
1131 udelay(10);
1132 }
1133
f1dc5600
S		 1134 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1135 AR_RTC_FORCE_WAKE_ON_INT);
1136
1137 if (AR_SREV_9100(ah)) {
1138 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1139 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1140 } else {
1141 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1142 if (tmpReg &
1143 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1144 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1145 u32 val;
f1dc5600 1146 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1147
1148 val = AR_RC_HOSTIF;
1149 if (!AR_SREV_9300_20_OR_LATER(ah))
1150 val |= AR_RC_AHB;
1151 REG_WRITE(ah, AR_RC, val);
1152
1153 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1154 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1155
1156 rst_flags = AR_RTC_RC_MAC_WARM;
1157 if (type == ATH9K_RESET_COLD)
1158 rst_flags |= AR_RTC_RC_MAC_COLD;
1159 }
1160
d03a66c1 1161 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1162
1163 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1164
f1dc5600
S		 1165 udelay(50);
1166
d03a66c1 1167 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1168 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
226afe68
JP		 1169 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1170 "RTC stuck in MAC reset\n");
f1dc5600
S		 1171 return false;
1172 }
1173
1174 if (!AR_SREV_9100(ah))
1175 REG_WRITE(ah, AR_RC, 0);
1176
f1dc5600
S		 1177 if (AR_SREV_9100(ah))
1178 udelay(50);
1179
1180 return true;
1181}
1182
cbe61d8a 1183static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1184{
7d0d0df0
S		 1185 ENABLE_REGWRITE_BUFFER(ah);
1186
9a658d2b
LR		 1187 if (AR_SREV_9300_20_OR_LATER(ah)) {
1188 REG_WRITE(ah, AR_WA, ah->WARegVal);
1189 udelay(10);
1190 }
1191
f1dc5600
S		 1192 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1193 AR_RTC_FORCE_WAKE_ON_INT);
1194
42d5bc3f 1195 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1196 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1197
d03a66c1 1198 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1199
7d0d0df0 1200 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1201
84e2169b
SB		 1202 if (!AR_SREV_9300_20_OR_LATER(ah))
1203 udelay(2);
1204
1205 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1206 REG_WRITE(ah, AR_RC, 0);
1207
d03a66c1 1208 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1209
1210 if (!ath9k_hw_wait(ah,
1211 AR_RTC_STATUS,
1212 AR_RTC_STATUS_M,
0caa7b14
S		 1213 AR_RTC_STATUS_ON,
1214 AH_WAIT_TIMEOUT)) {
226afe68
JP		 1215 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1216 "RTC not waking up\n");
f1dc5600 1217 return false;
f078f209
LR		 1218 }
1219
f1dc5600
S		 1220 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1221}
1222
cbe61d8a 1223static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1224{
9a658d2b
LR		 1225 if (AR_SREV_9300_20_OR_LATER(ah)) {
1226 REG_WRITE(ah, AR_WA, ah->WARegVal);
1227 udelay(10);
1228 }
1229
f1dc5600
S		 1230 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1231 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1232
1233 switch (type) {
1234 case ATH9K_RESET_POWER_ON:
1235 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1236 case ATH9K_RESET_WARM:
1237 case ATH9K_RESET_COLD:
1238 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1239 default:
1240 return false;
1241 }
f078f209
LR		 1242}
1243
cbe61d8a 1244static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1245 struct ath9k_channel *chan)
f078f209 1246{
42abfbee 1247 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1248 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1249 return false;
1250 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1251 return false;
f078f209 1252
9ecdef4b 1253 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1254 return false;
f078f209 1255
2660b81a 1256 ah->chip_fullsleep = false;
f1dc5600 1257 ath9k_hw_init_pll(ah, chan);
f1dc5600 1258 ath9k_hw_set_rfmode(ah, chan);
f078f209 1259
f1dc5600 1260 return true;
f078f209
LR		 1261}
1262
cbe61d8a 1263static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1264 struct ath9k_channel *chan)
f078f209 1265{
608b88cb 1266 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1267 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1268 struct ieee80211_channel *channel = chan->chan;
8fe65368 1269 u32 qnum;
0a3b7bac 1270 int r;
f078f209
LR		 1271
1272 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1273 if (ath9k_hw_numtxpending(ah, qnum)) {
226afe68
JP		 1274 ath_dbg(common, ATH_DBG_QUEUE,
1275 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1276 return false;
1277 }
1278 }
1279
8fe65368 1280 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1281 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1282 return false;
1283 }
1284
8fe65368 1285 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1286
8fe65368 1287 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1288 if (r) {
3800276a 1289 ath_err(common, "Failed to set channel\n");
0a3b7bac 1290 return false;
f078f209 1291 }
dfdac8ac 1292 ath9k_hw_set_clockrate(ah);
f078f209 1293
8fbff4b8 1294 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1295 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1296 channel->max_antenna_gain * 2,
1297 channel->max_power * 2,
1298 min((u32) MAX_RATE_POWER,
de40f316 1299 (u32) regulatory->power_limit), false);
f078f209 1300
8fe65368 1301 ath9k_hw_rfbus_done(ah);
f078f209 1302
f1dc5600
S		 1303 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1304 ath9k_hw_set_delta_slope(ah, chan);
1305
8fe65368 1306 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1307
f1dc5600
S		 1308 return true;
1309}
1310
691680b8
FF		 1311static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1312{
1313 u32 gpio_mask = ah->gpio_mask;
1314 int i;
1315
1316 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1317 if (!(gpio_mask & 1))
1318 continue;
1319
1320 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1321 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1322 }
1323}
1324
c9c99e5e 1325bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1326{
c9c99e5e
FF		 1327 int count = 50;
1328 u32 reg;
1329
e17f83ea 1330 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1331 return true;
1332
1333 do {
1334 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1335
c9c99e5e
FF		 1336 if ((reg & 0x7E7FFFEF) == 0x00702400)
1337 continue;
1338
1339 switch (reg & 0x7E000B00) {
1340 case 0x1E000000:
1341 case 0x52000B00:
1342 case 0x18000B00:
1343 continue;
1344 default:
1345 return true;
1346 }
1347 } while (count-- > 0);
3b319aae 1348
c9c99e5e 1349 return false;
3b319aae 1350}
c9c99e5e 1351EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1352
cbe61d8a 1353int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 1354 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
f078f209 1355{
1510718d 1356 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1357 u32 saveLedState;
2660b81a 1358 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1359 u32 saveDefAntenna;
1360 u32 macStaId1;
46fe782c 1361 u64 tsf = 0;
8fe65368 1362 int i, r;
f078f209 1363
43c27613
LR		 1364 ah->txchainmask = common->tx_chainmask;
1365 ah->rxchainmask = common->rx_chainmask;
f078f209 1366
9ecdef4b 1367 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1368 return -EIO;
f078f209 1369
d9891c78 1370 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1371 ath9k_hw_getnf(ah, curchan);
1372
20bd2a09
FF		 1373 ah->caldata = caldata;
1374 if (caldata &&
1375 (chan->channel != caldata->channel ||
1376 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1377 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1378 /* Operating channel changed, reset channel calibration data */
1379 memset(caldata, 0, sizeof(*caldata));
1380 ath9k_init_nfcal_hist_buffer(ah, chan);
1381 }
1382
f078f209 1383 if (bChannelChange &&
2660b81a
S		 1384 (ah->chip_fullsleep != true) &&
1385 (ah->curchan != NULL) &&
1386 (chan->channel != ah->curchan->channel) &&
f078f209 1387 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1388 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
58d7e0f3 1389 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
f078f209 1390
25c56eec 1391 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1392 ath9k_hw_loadnf(ah, ah->curchan);
00c86590 1393 ath9k_hw_start_nfcal(ah, true);
c2ba3342
RM		 1394 if (AR_SREV_9271(ah))
1395 ar9002_hw_load_ani_reg(ah, chan);
ae8d2858 1396 return 0;
f078f209
LR		 1397 }
1398 }
1399
1400 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1401 if (saveDefAntenna == 0)
1402 saveDefAntenna = 1;
1403
1404 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1405
46fe782c 1406 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1407 if (AR_SREV_9100(ah) ||
1408 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1409 tsf = ath9k_hw_gettsf64(ah);
1410
f078f209
LR		 1411 saveLedState = REG_READ(ah, AR_CFG_LED) &
1412 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1413 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1414
1415 ath9k_hw_mark_phy_inactive(ah);
1416
45ef6a0b
VT		 1417 ah->paprd_table_write_done = false;
1418
05020d23 1419 /* Only required on the first reset */
d7e7d229
LR		 1420 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1421 REG_WRITE(ah,
1422 AR9271_RESET_POWER_DOWN_CONTROL,
1423 AR9271_RADIO_RF_RST);
1424 udelay(50);
1425 }
1426
f078f209 1427 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1428 ath_err(common, "Chip reset failed\n");
ae8d2858 1429 return -EINVAL;
f078f209
LR		 1430 }
1431
05020d23 1432 /* Only required on the first reset */
d7e7d229
LR		 1433 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1434 ah->htc_reset_init = false;
1435 REG_WRITE(ah,
1436 AR9271_RESET_POWER_DOWN_CONTROL,
1437 AR9271_GATE_MAC_CTL);
1438 udelay(50);
1439 }
1440
46fe782c 1441 /* Restore TSF */
f860d526 1442 if (tsf)
46fe782c
S		 1443 ath9k_hw_settsf64(ah, tsf);
1444
7a37081e 1445 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1446 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1447
e9141f71
S		 1448 if (!AR_SREV_9300_20_OR_LATER(ah))
1449 ar9002_hw_enable_async_fifo(ah);
1450
25c56eec 1451 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1452 if (r)
1453 return r;
f078f209 1454
f860d526
FF		 1455 /*
1456 * Some AR91xx SoC devices frequently fail to accept TSF writes
1457 * right after the chip reset. When that happens, write a new
1458 * value after the initvals have been applied, with an offset
1459 * based on measured time difference
1460 */
1461 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1462 tsf += 1500;
1463 ath9k_hw_settsf64(ah, tsf);
1464 }
1465
0ced0e17
JM		 1466 /* Setup MFP options for CCMP */
1467 if (AR_SREV_9280_20_OR_LATER(ah)) {
1468 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1469 * frames when constructing CCMP AAD. */
1470 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1471 0xc7ff);
1472 ah->sw_mgmt_crypto = false;
1473 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1474 /* Disable hardware crypto for management frames */
1475 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1476 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1477 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1478 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1479 ah->sw_mgmt_crypto = true;
1480 } else
1481 ah->sw_mgmt_crypto = true;
1482
f078f209
LR		 1483 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1484 ath9k_hw_set_delta_slope(ah, chan);
1485
8fe65368 1486 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1487 ah->eep_ops->set_board_values(ah, chan);
a7765828 1488
7d0d0df0
S		 1489 ENABLE_REGWRITE_BUFFER(ah);
1490
1510718d
LR		 1491 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1492 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1493 | macStaId1
1494 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1495 | (ah->config.
60b67f51 1496 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1497 | ah->sta_id1_defaults);
13b81559 1498 ath_hw_setbssidmask(common);
f078f209 1499 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1500 ath9k_hw_write_associd(ah);
f078f209 1501 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1502 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1503
7d0d0df0 1504 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1505
00e0003e
SM		 1506 ath9k_hw_set_operating_mode(ah, ah->opmode);
1507
8fe65368 1508 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1509 if (r)
1510 return r;
f078f209 1511
dfdac8ac
FF		 1512 ath9k_hw_set_clockrate(ah);
1513
7d0d0df0
S		 1514 ENABLE_REGWRITE_BUFFER(ah);
1515
f078f209
LR		 1516 for (i = 0; i < AR_NUM_DCU; i++)
1517 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1518
7d0d0df0 1519 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1520
2660b81a 1521 ah->intr_txqs = 0;
f4c607dc 1522 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
f078f209
LR		 1523 ath9k_hw_resettxqueue(ah, i);
1524
2660b81a 1525 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1526 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1527 ath9k_hw_init_qos(ah);
1528
2660b81a 1529 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1530 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1531
0005baf4 1532 ath9k_hw_init_global_settings(ah);
f078f209 1533
6c94fdc9 1534 if (!AR_SREV_9300_20_OR_LATER(ah)) {
e9141f71 1535 ar9002_hw_update_async_fifo(ah);
6c94fdc9 1536 ar9002_hw_enable_wep_aggregation(ah);
ac88b6ec
VN		 1537 }
1538
ca7a4deb 1539 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1540
1541 ath9k_hw_set_dma(ah);
1542
1543 REG_WRITE(ah, AR_OBS, 8);
1544
0ce024cb 1545 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1546 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1547 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1548 }
1549
7f62a136
VT		 1550 if (ah->config.tx_intr_mitigation) {
1551 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1552 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1553 }
1554
f078f209
LR		 1555 ath9k_hw_init_bb(ah, chan);
1556
ae8d2858 1557 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1558 return -EIO;
f078f209 1559
7d0d0df0 1560 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1561
8fe65368 1562 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1563 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1564
7d0d0df0 1565 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1566
d7e7d229
LR		 1567 /*
1568 * For big endian systems turn on swapping for descriptors
1569 */
f078f209
LR		 1570 if (AR_SREV_9100(ah)) {
1571 u32 mask;
1572 mask = REG_READ(ah, AR_CFG);
1573 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
226afe68 1574 ath_dbg(common, ATH_DBG_RESET,
04bd4638 1575 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1576 } else {
1577 mask =
1578 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1579 REG_WRITE(ah, AR_CFG, mask);
226afe68 1580 ath_dbg(common, ATH_DBG_RESET,
04bd4638 1581 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1582 }
1583 } else {
cbba8cd1
S		 1584 if (common->bus_ops->ath_bus_type == ATH_USB) {
1585 /* Configure AR9271 target WLAN */
1586 if (AR_SREV_9271(ah))
1587 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1588 else
1589 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1590 }
f078f209 1591#ifdef __BIG_ENDIAN
2be7bfe0
VT		 1592 else if (AR_SREV_9340(ah))
1593 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1594 else
d7e7d229 1595 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1596#endif
1597 }
1598
766ec4a9 1599 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1600 ath9k_hw_btcoex_enable(ah);
1601
51ac8cbb 1602 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 1603 ar9003_hw_bb_watchdog_config(ah);
d8903a53 1604
51ac8cbb
RM		 1605 ar9003_hw_disable_phy_restart(ah);
1606 }
1607
691680b8
FF		 1608 ath9k_hw_apply_gpio_override(ah);
1609
ae8d2858 1610 return 0;
f078f209 1611}
7322fd19 1612EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1613
f1dc5600
S		 1614/******************************/
1615/* Power Management (Chipset) */
1616/******************************/
1617
42d5bc3f
LR		 1618/*
1619 * Notify Power Mgt is disabled in self-generated frames.
1620 * If requested, force chip to sleep.
1621 */
cbe61d8a 1622static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1623{
f1dc5600
S		 1624 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1625 if (setChip) {
42d5bc3f
LR		 1626 /*
1627 * Clear the RTC force wake bit to allow the
1628 * mac to go to sleep.
1629 */
f1dc5600
S		 1630 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1631 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1632 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1633 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1634
42d5bc3f 1635 /* Shutdown chip. Active low */
14b3af38 1636 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1637 REG_CLR_BIT(ah, (AR_RTC_RESET),
1638 AR_RTC_RESET_EN);
f1dc5600 1639 }
9a658d2b
LR		 1640
1641 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1642 if (AR_SREV_9300_20_OR_LATER(ah))
1643 REG_WRITE(ah, AR_WA,
1644 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1645}
1646
bbd79af5
LR		 1647/*
1648 * Notify Power Management is enabled in self-generating
1649 * frames. If request, set power mode of chip to
1650 * auto/normal. Duration in units of 128us (1/8 TU).
1651 */
cbe61d8a 1652static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1653{
f1dc5600
S		 1654 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1655 if (setChip) {
2660b81a 1656 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1657
f1dc5600 1658 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1659 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1660 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1661 AR_RTC_FORCE_WAKE_ON_INT);
1662 } else {
bbd79af5
LR		 1663 /*
1664 * Clear the RTC force wake bit to allow the
1665 * mac to go to sleep.
1666 */
f1dc5600
S		 1667 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1668 AR_RTC_FORCE_WAKE_EN);
f078f209 1669 }
f078f209 1670 }
9a658d2b
LR		 1671
1672 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1673 if (AR_SREV_9300_20_OR_LATER(ah))
1674 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1675}
1676
cbe61d8a 1677static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1678{
f1dc5600
S		 1679 u32 val;
1680 int i;
f078f209 1681
9a658d2b
LR		 1682 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1683 if (AR_SREV_9300_20_OR_LATER(ah)) {
1684 REG_WRITE(ah, AR_WA, ah->WARegVal);
1685 udelay(10);
1686 }
1687
f1dc5600
S		 1688 if (setChip) {
1689 if ((REG_READ(ah, AR_RTC_STATUS) &
1690 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1691 if (ath9k_hw_set_reset_reg(ah,
1692 ATH9K_RESET_POWER_ON) != true) {
1693 return false;
1694 }
e041228f
LR		 1695 if (!AR_SREV_9300_20_OR_LATER(ah))
1696 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1697 }
1698 if (AR_SREV_9100(ah))
1699 REG_SET_BIT(ah, AR_RTC_RESET,
1700 AR_RTC_RESET_EN);
f078f209 1701
f1dc5600
S		 1702 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1703 AR_RTC_FORCE_WAKE_EN);
1704 udelay(50);
f078f209 1705
f1dc5600
S		 1706 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1707 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1708 if (val == AR_RTC_STATUS_ON)
1709 break;
1710 udelay(50);
1711 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1712 AR_RTC_FORCE_WAKE_EN);
f078f209 1713 }
f1dc5600 1714 if (i == 0) {
3800276a
JP		 1715 ath_err(ath9k_hw_common(ah),
1716 "Failed to wakeup in %uus\n",
1717 POWER_UP_TIME / 20);
f1dc5600 1718 return false;
f078f209 1719 }
f078f209
LR		 1720 }
1721
f1dc5600 1722 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1723
f1dc5600 1724 return true;
f078f209
LR		 1725}
1726
9ecdef4b 1727bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1728{
c46917bb 1729 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1730 int status = true, setChip = true;
f1dc5600
S		 1731 static const char *modes[] = {
1732 "AWAKE",
1733 "FULL-SLEEP",
1734 "NETWORK SLEEP",
1735 "UNDEFINED"
1736 };
f1dc5600 1737
cbdec975
GJ		 1738 if (ah->power_mode == mode)
1739 return status;
1740
226afe68
JP		 1741 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1742 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1743
1744 switch (mode) {
1745 case ATH9K_PM_AWAKE:
1746 status = ath9k_hw_set_power_awake(ah, setChip);
1747 break;
1748 case ATH9K_PM_FULL_SLEEP:
1749 ath9k_set_power_sleep(ah, setChip);
2660b81a 1750 ah->chip_fullsleep = true;
f1dc5600
S		 1751 break;
1752 case ATH9K_PM_NETWORK_SLEEP:
1753 ath9k_set_power_network_sleep(ah, setChip);
1754 break;
f078f209 1755 default:
3800276a 1756 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 1757 return false;
1758 }
2660b81a 1759 ah->power_mode = mode;
f1dc5600 1760
69f4aab1
LR		 1761 /*
1762 * XXX: If this warning never comes up after a while then
1763 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1764 * ath9k_hw_setpower() return type void.
1765 */
97dcec57
SM		 1766
1767 if (!(ah->ah_flags & AH_UNPLUGGED))
1768 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 1769
f1dc5600 1770 return status;
f078f209 1771}
7322fd19 1772EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1773
f1dc5600
S		 1774/*******************/
1775/* Beacon Handling */
1776/*******************/
1777
cbe61d8a 1778void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 1779{
f078f209
LR		 1780 int flags = 0;
1781
7d0d0df0
S		 1782 ENABLE_REGWRITE_BUFFER(ah);
1783
2660b81a 1784 switch (ah->opmode) {
d97809db 1785 case NL80211_IFTYPE_ADHOC:
9cb5412b 1786 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 1787 REG_SET_BIT(ah, AR_TXCFG,
1788 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
dd347f2f
FF		 1789 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1790 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
f078f209 1791 flags |= AR_NDP_TIMER_EN;
d97809db 1792 case NL80211_IFTYPE_AP:
dd347f2f
FF		 1793 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1794 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1795 TU_TO_USEC(ah->config.dma_beacon_response_time));
1796 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1797 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 1798 flags |=
1799 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1800 break;
d97809db 1801 default:
226afe68
JP		 1802 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1803 "%s: unsupported opmode: %d\n",
1804 __func__, ah->opmode);
d97809db
CM		 1805 return;
1806 break;
f078f209
LR		 1807 }
1808
dd347f2f
FF		 1809 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1810 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1811 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1812 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
f078f209 1813
7d0d0df0 1814 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1815
f078f209
LR		 1816 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1817}
7322fd19 1818EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 1819
cbe61d8a 1820void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 1821 const struct ath9k_beacon_state *bs)
f078f209
LR		 1822{
1823 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 1824 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1825 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1826
7d0d0df0
S		 1827 ENABLE_REGWRITE_BUFFER(ah);
1828
f078f209
LR		 1829 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1830
1831 REG_WRITE(ah, AR_BEACON_PERIOD,
f29f5c08 1832 TU_TO_USEC(bs->bs_intval));
f078f209 1833 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
f29f5c08 1834 TU_TO_USEC(bs->bs_intval));
f078f209 1835
7d0d0df0 1836 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1837
f078f209
LR		 1838 REG_RMW_FIELD(ah, AR_RSSI_THR,
1839 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1840
f29f5c08 1841 beaconintval = bs->bs_intval;
f078f209
LR		 1842
1843 if (bs->bs_sleepduration > beaconintval)
1844 beaconintval = bs->bs_sleepduration;
1845
1846 dtimperiod = bs->bs_dtimperiod;
1847 if (bs->bs_sleepduration > dtimperiod)
1848 dtimperiod = bs->bs_sleepduration;
1849
1850 if (beaconintval == dtimperiod)
1851 nextTbtt = bs->bs_nextdtim;
1852 else
1853 nextTbtt = bs->bs_nexttbtt;
1854
226afe68
JP		 1855 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1856 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1857 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1858 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 1859
7d0d0df0
S		 1860 ENABLE_REGWRITE_BUFFER(ah);
1861
f1dc5600
S		 1862 REG_WRITE(ah, AR_NEXT_DTIM,
1863 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1864 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 1865
f1dc5600
S		 1866 REG_WRITE(ah, AR_SLEEP1,
1867 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1868 | AR_SLEEP1_ASSUME_DTIM);
f078f209 1869
f1dc5600
S		 1870 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1871 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1872 else
1873 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 1874
f1dc5600
S		 1875 REG_WRITE(ah, AR_SLEEP2,
1876 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 1877
f1dc5600
S		 1878 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1879 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 1880
7d0d0df0 1881 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1882
f1dc5600
S		 1883 REG_SET_BIT(ah, AR_TIMER_MODE,
1884 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1885 AR_DTIM_TIMER_EN);
f078f209 1886
4af9cf4f
S		 1887 /* TSF Out of Range Threshold */
1888 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 1889}
7322fd19 1890EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 1891
f1dc5600
S		 1892/*******************/
1893/* HW Capabilities */
1894/*******************/
1895
a9a29ce6 1896int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 1897{
2660b81a 1898 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 1899 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1900 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 1901 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 1902
0ff2b5c0 1903 u16 eeval;
47c80de6 1904 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 1905
f74df6fb 1906 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 1907 regulatory->current_rd = eeval;
f078f209 1908
f74df6fb 1909 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
e17f83ea 1910 if (AR_SREV_9285_12_OR_LATER(ah))
fec0de11 1911 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 1912 regulatory->current_rd_ext = eeval;
f078f209 1913
2660b81a 1914 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 1915 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 1916 if (regulatory->current_rd == 0x64 ||
1917 regulatory->current_rd == 0x65)
1918 regulatory->current_rd += 5;
1919 else if (regulatory->current_rd == 0x41)
1920 regulatory->current_rd = 0x43;
226afe68
JP		 1921 ath_dbg(common, ATH_DBG_REGULATORY,
1922 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 1923 }
f078f209 1924
f74df6fb 1925 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 1926 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 1927 ath_err(common,
1928 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 1929 return -EINVAL;
1930 }
1931
d4659912
FF		 1932 if (eeval & AR5416_OPFLAGS_11A)
1933 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 1934
d4659912
FF		 1935 if (eeval & AR5416_OPFLAGS_11G)
1936 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 1937
f74df6fb 1938 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 1939 /*
1940 * For AR9271 we will temporarilly uses the rx chainmax as read from
1941 * the EEPROM.
1942 */
8147f5de 1943 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 1944 !(eeval & AR5416_OPFLAGS_11A) &&
1945 !(AR_SREV_9271(ah)))
1946 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 1947 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 1948 else if (AR_SREV_9100(ah))
1949 pCap->rx_chainmask = 0x7;
8147f5de 1950 else
d7e7d229 1951 /* Use rx_chainmask from EEPROM. */
8147f5de 1952 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 1953
7a37081e 1954 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 1955
02d2ebb2
FF		 1956 /* enable key search for every frame in an aggregate */
1957 if (AR_SREV_9300_20_OR_LATER(ah))
1958 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1959
ce2220d1
BR		 1960 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1961
0db156e9 1962 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 1963 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1964 else
1965 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 1966
5b5fa355
S		 1967 if (AR_SREV_9271(ah))
1968 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 1969 else if (AR_DEVID_7010(ah))
1970 pCap->num_gpio_pins = AR7010_NUM_GPIO;
e17f83ea 1971 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 1972 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 1973 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 1974 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1975 else
1976 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 1977
f1dc5600
S		 1978 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1979 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1980 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1981 } else {
1982 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 1983 }
1984
e97275cb 1985#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 1986 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1987 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1988 ah->rfkill_gpio =
1989 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1990 ah->rfkill_polarity =
1991 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 1992
1993 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 1994 }
f1dc5600 1995#endif
d5d1154f 1996 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 1997 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1998 else
1999 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2000
e7594072 2001 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2002 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2003 else
2004 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2005
a6ef530f
VN		 2006 if (common->btcoex_enabled) {
2007 if (AR_SREV_9300_20_OR_LATER(ah)) {
766ec4a9 2008 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
a6ef530f
VN		 2009 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2010 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2011 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
2012 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2013 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
2014 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
2015
2016 if (AR_SREV_9285(ah)) {
2017 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2018 btcoex_hw->btpriority_gpio =
2019 ATH_BTPRIORITY_GPIO_9285;
2020 } else {
2021 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2022 }
8c8f9ba7 2023 }
22f25d0d 2024 } else {
766ec4a9 2025 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 2026 }
a9a29ce6 2027
ceb26445 2028 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503
VT		 2029 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2030 if (!AR_SREV_9485(ah))
2031 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2032
ceb26445
VT		 2033 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2034 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2035 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2036 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2037 pCap->txs_len = sizeof(struct ar9003_txs);
6f481010
LR		 2038 if (!ah->config.paprd_disable &&
2039 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
4935250a 2040 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 2041 } else {
2042 pCap->tx_desc_len = sizeof(struct ath_desc);
6b42e8d0
FF		 2043 if (AR_SREV_9280_20(ah) &&
2044 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2045 AR5416_EEP_MINOR_VER_16) ||
2046 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2047 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2048 }
1adf02ff 2049
6c84ce08
VT		 2050 if (AR_SREV_9300_20_OR_LATER(ah))
2051 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2052
6ee63f55
SB		 2053 if (AR_SREV_9300_20_OR_LATER(ah))
2054 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2055
a42acef0 2056 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2057 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2058
754dc536
VT		 2059 if (AR_SREV_9285(ah))
2060 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2061 ant_div_ctl1 =
2062 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2063 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2064 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2065 }
ea066d5a
MSS		 2066 if (AR_SREV_9300_20_OR_LATER(ah)) {
2067 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2068 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2069 }
2070
2071
21d2c63a
MSS		 2072 if (AR_SREV_9485(ah)) {
2073 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2074 /*
2075 * enable the diversity-combining algorithm only when
2076 * both enable_lna_div and enable_fast_div are set
2077 * Table for Diversity
2078 * ant_div_alt_lnaconf bit 0-1
2079 * ant_div_main_lnaconf bit 2-3
2080 * ant_div_alt_gaintb bit 4
2081 * ant_div_main_gaintb bit 5
2082 * enable_ant_div_lnadiv bit 6
2083 * enable_ant_fast_div bit 7
2084 */
2085 if ((ant_div_ctl1 >> 0x6) == 0x3)
2086 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2087 }
754dc536 2088
8060e169
VT		 2089 if (AR_SREV_9485_10(ah)) {
2090 pCap->pcie_lcr_extsync_en = true;
2091 pCap->pcie_lcr_offset = 0x80;
2092 }
2093
47c80de6
VT		 2094 tx_chainmask = pCap->tx_chainmask;
2095 rx_chainmask = pCap->rx_chainmask;
2096 while (tx_chainmask || rx_chainmask) {
2097 if (tx_chainmask & BIT(0))
2098 pCap->max_txchains++;
2099 if (rx_chainmask & BIT(0))
2100 pCap->max_rxchains++;
2101
2102 tx_chainmask >>= 1;
2103 rx_chainmask >>= 1;
2104 }
2105
a9a29ce6 2106 return 0;
f078f209
LR		 2107}
2108
f1dc5600
S		 2109/****************************/
2110/* GPIO / RFKILL / Antennae */
2111/****************************/
f078f209 2112
cbe61d8a 2113static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2114 u32 gpio, u32 type)
2115{
2116 int addr;
2117 u32 gpio_shift, tmp;
f078f209 2118
f1dc5600
S		 2119 if (gpio > 11)
2120 addr = AR_GPIO_OUTPUT_MUX3;
2121 else if (gpio > 5)
2122 addr = AR_GPIO_OUTPUT_MUX2;
2123 else
2124 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2125
f1dc5600 2126 gpio_shift = (gpio % 6) * 5;
f078f209 2127
f1dc5600
S		 2128 if (AR_SREV_9280_20_OR_LATER(ah)
2129 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2130 REG_RMW(ah, addr, (type << gpio_shift),
2131 (0x1f << gpio_shift));
f078f209 2132 } else {
f1dc5600
S		 2133 tmp = REG_READ(ah, addr);
2134 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2135 tmp &= ~(0x1f << gpio_shift);
2136 tmp |= (type << gpio_shift);
2137 REG_WRITE(ah, addr, tmp);
f078f209 2138 }
f078f209
LR		 2139}
2140
cbe61d8a 2141void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2142{
f1dc5600 2143 u32 gpio_shift;
f078f209 2144
9680e8a3 2145 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2146
88c1f4f6
S		 2147 if (AR_DEVID_7010(ah)) {
2148 gpio_shift = gpio;
2149 REG_RMW(ah, AR7010_GPIO_OE,
2150 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2151 (AR7010_GPIO_OE_MASK << gpio_shift));
2152 return;
2153 }
f078f209 2154
88c1f4f6 2155 gpio_shift = gpio << 1;
f1dc5600
S		 2156 REG_RMW(ah,
2157 AR_GPIO_OE_OUT,
2158 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2159 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2160}
7322fd19 2161EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2162
cbe61d8a 2163u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2164{
cb33c412
SB		 2165#define MS_REG_READ(x, y) \
2166 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2167
2660b81a 2168 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2169 return 0xffffffff;
f078f209 2170
88c1f4f6
S		 2171 if (AR_DEVID_7010(ah)) {
2172 u32 val;
2173 val = REG_READ(ah, AR7010_GPIO_IN);
2174 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2175 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2176 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2177 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2178 else if (AR_SREV_9271(ah))
5b5fa355 2179 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2180 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2181 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2182 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2183 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2184 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2185 return MS_REG_READ(AR928X, gpio) != 0;
2186 else
2187 return MS_REG_READ(AR, gpio) != 0;
f078f209 2188}
7322fd19 2189EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2190
cbe61d8a 2191void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2192 u32 ah_signal_type)
f078f209 2193{
f1dc5600 2194 u32 gpio_shift;
f078f209 2195
88c1f4f6
S		 2196 if (AR_DEVID_7010(ah)) {
2197 gpio_shift = gpio;
2198 REG_RMW(ah, AR7010_GPIO_OE,
2199 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2200 (AR7010_GPIO_OE_MASK << gpio_shift));
2201 return;
2202 }
f078f209 2203
88c1f4f6 2204 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2205 gpio_shift = 2 * gpio;
f1dc5600
S		 2206 REG_RMW(ah,
2207 AR_GPIO_OE_OUT,
2208 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2209 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2210}
7322fd19 2211EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2212
cbe61d8a 2213void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2214{
88c1f4f6
S		 2215 if (AR_DEVID_7010(ah)) {
2216 val = val ? 0 : 1;
2217 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2218 AR_GPIO_BIT(gpio));
2219 return;
2220 }
2221
5b5fa355
S		 2222 if (AR_SREV_9271(ah))
2223 val = ~val;
2224
f1dc5600
S		 2225 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2226 AR_GPIO_BIT(gpio));
f078f209 2227}
7322fd19 2228EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2229
cbe61d8a 2230u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2231{
f1dc5600 2232 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2233}
7322fd19 2234EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2235
cbe61d8a 2236void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2237{
f1dc5600 2238 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2239}
7322fd19 2240EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2241
f1dc5600
S		 2242/*********************/
2243/* General Operation */
2244/*********************/
2245
cbe61d8a 2246u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2247{
f1dc5600
S		 2248 u32 bits = REG_READ(ah, AR_RX_FILTER);
2249 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2250
f1dc5600
S		 2251 if (phybits & AR_PHY_ERR_RADAR)
2252 bits |= ATH9K_RX_FILTER_PHYRADAR;
2253 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2254 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2255
f1dc5600 2256 return bits;
f078f209 2257}
7322fd19 2258EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2259
cbe61d8a 2260void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2261{
f1dc5600 2262 u32 phybits;
f078f209 2263
7d0d0df0
S		 2264 ENABLE_REGWRITE_BUFFER(ah);
2265
7ea310be
S		 2266 REG_WRITE(ah, AR_RX_FILTER, bits);
2267
f1dc5600
S		 2268 phybits = 0;
2269 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2270 phybits |= AR_PHY_ERR_RADAR;
2271 if (bits & ATH9K_RX_FILTER_PHYERR)
2272 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2273 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2274
f1dc5600 2275 if (phybits)
ca7a4deb 2276 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2277 else
ca7a4deb 2278 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2279
2280 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2281}
7322fd19 2282EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2283
cbe61d8a 2284bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2285{
63a75b91
SB		 2286 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2287 return false;
2288
2289 ath9k_hw_init_pll(ah, NULL);
2290 return true;
f1dc5600 2291}
7322fd19 2292EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2293
cbe61d8a 2294bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2295{
9ecdef4b 2296 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2297 return false;
f078f209 2298
63a75b91
SB		 2299 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2300 return false;
2301
2302 ath9k_hw_init_pll(ah, NULL);
2303 return true;
f078f209 2304}
7322fd19 2305EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2306
de40f316 2307void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2308{
608b88cb 2309 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2310 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2311 struct ieee80211_channel *channel = chan->chan;
f078f209 2312
608b88cb 2313 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2314
8fbff4b8 2315 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2316 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2317 channel->max_antenna_gain * 2,
2318 channel->max_power * 2,
2319 min((u32) MAX_RATE_POWER,
de40f316 2320 (u32) regulatory->power_limit), test);
6f255425 2321}
7322fd19 2322EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2323
cbe61d8a 2324void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2325{
2660b81a 2326 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2327}
7322fd19 2328EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2329
cbe61d8a 2330void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2331{
f1dc5600
S		 2332 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2333 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2334}
7322fd19 2335EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2336
f2b2143e 2337void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2338{
1510718d
LR		 2339 struct ath_common *common = ath9k_hw_common(ah);
2340
2341 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2342 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2343 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2344}
7322fd19 2345EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2346
1c0fc65e
BP		 2347#define ATH9K_MAX_TSF_READ 10
2348
cbe61d8a 2349u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2350{
1c0fc65e
BP		 2351 u32 tsf_lower, tsf_upper1, tsf_upper2;
2352 int i;
2353
2354 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2355 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2356 tsf_lower = REG_READ(ah, AR_TSF_L32);
2357 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2358 if (tsf_upper2 == tsf_upper1)
2359 break;
2360 tsf_upper1 = tsf_upper2;
2361 }
f078f209 2362
1c0fc65e 2363 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2364
1c0fc65e 2365 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2366}
7322fd19 2367EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2368
cbe61d8a 2369void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2370{
27abe060 2371 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2372 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2373}
7322fd19 2374EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2375
cbe61d8a 2376void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2377{
f9b604f6
GJ		 2378 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2379 AH_TSF_WRITE_TIMEOUT))
226afe68
JP		 2380 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2381 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2382
f1dc5600
S		 2383 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2384}
7322fd19 2385EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2386
54e4cec6 2387void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2388{
f1dc5600 2389 if (setting)
2660b81a 2390 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2391 else
2660b81a 2392 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2393}
7322fd19 2394EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2395
25c56eec 2396void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2397{
25c56eec 2398 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2399 u32 macmode;
2400
25c56eec 2401 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2402 macmode = AR_2040_JOINED_RX_CLEAR;
2403 else
2404 macmode = 0;
f078f209 2405
f1dc5600 2406 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2407}
ff155a45
VT		 2408
2409/* HW Generic timers configuration */
2410
2411static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2412{
2413 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2414 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2415 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2416 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2417 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2418 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2419 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2420 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2421 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2422 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2423 AR_NDP2_TIMER_MODE, 0x0002},
2424 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2425 AR_NDP2_TIMER_MODE, 0x0004},
2426 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2427 AR_NDP2_TIMER_MODE, 0x0008},
2428 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2429 AR_NDP2_TIMER_MODE, 0x0010},
2430 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2431 AR_NDP2_TIMER_MODE, 0x0020},
2432 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2433 AR_NDP2_TIMER_MODE, 0x0040},
2434 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2435 AR_NDP2_TIMER_MODE, 0x0080}
2436};
2437
2438/* HW generic timer primitives */
2439
2440/* compute and clear index of rightmost 1 */
2441static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2442{
2443 u32 b;
2444
2445 b = *mask;
2446 b &= (0-b);
2447 *mask &= ~b;
2448 b *= debruijn32;
2449 b >>= 27;
2450
2451 return timer_table->gen_timer_index[b];
2452}
2453
dd347f2f 2454u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2455{
2456 return REG_READ(ah, AR_TSF_L32);
2457}
dd347f2f 2458EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2459
2460struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2461 void (*trigger)(void *),
2462 void (*overflow)(void *),
2463 void *arg,
2464 u8 timer_index)
2465{
2466 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2467 struct ath_gen_timer *timer;
2468
2469 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2470
2471 if (timer == NULL) {
3800276a
JP		 2472 ath_err(ath9k_hw_common(ah),
2473 "Failed to allocate memory for hw timer[%d]\n",
2474 timer_index);
ff155a45
VT		 2475 return NULL;
2476 }
2477
2478 /* allocate a hardware generic timer slot */
2479 timer_table->timers[timer_index] = timer;
2480 timer->index = timer_index;
2481 timer->trigger = trigger;
2482 timer->overflow = overflow;
2483 timer->arg = arg;
2484
2485 return timer;
2486}
7322fd19 2487EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2488
cd9bf689
LR		 2489void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2490 struct ath_gen_timer *timer,
788f6875 2491 u32 trig_timeout,
cd9bf689 2492 u32 timer_period)
ff155a45
VT		 2493{
2494 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
788f6875 2495 u32 tsf, timer_next;
ff155a45
VT		 2496
2497 BUG_ON(!timer_period);
2498
2499 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2500
2501 tsf = ath9k_hw_gettsf32(ah);
2502
788f6875
VT		 2503 timer_next = tsf + trig_timeout;
2504
226afe68
JP		 2505 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2506 "current tsf %x period %x timer_next %x\n",
2507 tsf, timer_period, timer_next);
ff155a45 2508
ff155a45
VT		 2509 /*
2510 * Program generic timer registers
2511 */
2512 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2513 timer_next);
2514 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2515 timer_period);
2516 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2517 gen_tmr_configuration[timer->index].mode_mask);
2518
2519 /* Enable both trigger and thresh interrupt masks */
2520 REG_SET_BIT(ah, AR_IMR_S5,
2521 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2522 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2523}
7322fd19 2524EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2525
cd9bf689 2526void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2527{
2528 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2529
2530 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2531 (timer->index >= ATH_MAX_GEN_TIMER)) {
2532 return;
2533 }
2534
2535 /* Clear generic timer enable bits. */
2536 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2537 gen_tmr_configuration[timer->index].mode_mask);
2538
2539 /* Disable both trigger and thresh interrupt masks */
2540 REG_CLR_BIT(ah, AR_IMR_S5,
2541 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2542 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2543
2544 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 2545}
7322fd19 2546EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2547
2548void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2549{
2550 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2551
2552 /* free the hardware generic timer slot */
2553 timer_table->timers[timer->index] = NULL;
2554 kfree(timer);
2555}
7322fd19 2556EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2557
2558/*
2559 * Generic Timer Interrupts handling
2560 */
2561void ath_gen_timer_isr(struct ath_hw *ah)
2562{
2563 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2564 struct ath_gen_timer *timer;
c46917bb 2565 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 2566 u32 trigger_mask, thresh_mask, index;
2567
2568 /* get hardware generic timer interrupt status */
2569 trigger_mask = ah->intr_gen_timer_trigger;
2570 thresh_mask = ah->intr_gen_timer_thresh;
2571 trigger_mask &= timer_table->timer_mask.val;
2572 thresh_mask &= timer_table->timer_mask.val;
2573
2574 trigger_mask &= ~thresh_mask;
2575
2576 while (thresh_mask) {
2577 index = rightmost_index(timer_table, &thresh_mask);
2578 timer = timer_table->timers[index];
2579 BUG_ON(!timer);
226afe68
JP		 2580 ath_dbg(common, ATH_DBG_HWTIMER,
2581 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 2582 timer->overflow(timer->arg);
2583 }
2584
2585 while (trigger_mask) {
2586 index = rightmost_index(timer_table, &trigger_mask);
2587 timer = timer_table->timers[index];
2588 BUG_ON(!timer);
226afe68
JP		 2589 ath_dbg(common, ATH_DBG_HWTIMER,
2590 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 2591 timer->trigger(timer->arg);
2592 }
2593}
7322fd19 2594EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2595
05020d23
S		 2596/********/
2597/* HTC */
2598/********/
2599
2600void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2601{
2602 ah->htc_reset_init = true;
2603}
2604EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2605
2da4f01a
LR		 2606static struct {
2607 u32 version;
2608 const char * name;
2609} ath_mac_bb_names[] = {
2610 /* Devices with external radios */
2611 { AR_SREV_VERSION_5416_PCI, "5416" },
2612 { AR_SREV_VERSION_5416_PCIE, "5418" },
2613 { AR_SREV_VERSION_9100, "9100" },
2614 { AR_SREV_VERSION_9160, "9160" },
2615 /* Single-chip solutions */
2616 { AR_SREV_VERSION_9280, "9280" },
2617 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 2618 { AR_SREV_VERSION_9287, "9287" },
2619 { AR_SREV_VERSION_9271, "9271" },
ec83903e 2620 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 2621 { AR_SREV_VERSION_9330, "9330" },
8f06ca2c 2622 { AR_SREV_VERSION_9485, "9485" },
2da4f01a
LR		 2623};
2624
2625/* For devices with external radios */
2626static struct {
2627 u16 version;
2628 const char * name;
2629} ath_rf_names[] = {
2630 { 0, "5133" },
2631 { AR_RAD5133_SREV_MAJOR, "5133" },
2632 { AR_RAD5122_SREV_MAJOR, "5122" },
2633 { AR_RAD2133_SREV_MAJOR, "2133" },
2634 { AR_RAD2122_SREV_MAJOR, "2122" }
2635};
2636
2637/*
2638 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2639 */
f934c4d9 2640static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 2641{
2642 int i;
2643
2644 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2645 if (ath_mac_bb_names[i].version == mac_bb_version) {
2646 return ath_mac_bb_names[i].name;
2647 }
2648 }
2649
2650 return "????";
2651}
2da4f01a
LR		 2652
2653/*
2654 * Return the RF name. "????" is returned if the RF is unknown.
2655 * Used for devices with external radios.
2656 */
f934c4d9 2657static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 2658{
2659 int i;
2660
2661 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2662 if (ath_rf_names[i].version == rf_version) {
2663 return ath_rf_names[i].name;
2664 }
2665 }
2666
2667 return "????";
2668}
f934c4d9
LR		 2669
2670void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2671{
2672 int used;
2673
2674 /* chipsets >= AR9280 are single-chip */
7a37081e 2675 if (AR_SREV_9280_20_OR_LATER(ah)) {
f934c4d9
LR		 2676 used = snprintf(hw_name, len,
2677 "Atheros AR%s Rev:%x",
2678 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2679 ah->hw_version.macRev);
2680 }
2681 else {
2682 used = snprintf(hw_name, len,
2683 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2684 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2685 ah->hw_version.macRev,
2686 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2687 AR_RADIO_SREV_MAJOR)),
2688 ah->hw_version.phyRev);
2689 }
2690
2691 hw_name[used] = '\0';
2692}
2693EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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