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ath9k_hw: fix gentimer callback without overflow handler
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
f078f209
LR		 22#include <asm/unaligned.h>
23
af03abec 24#include "hw.h"
d70357d5 25#include "hw-ops.h"
cfe8cba9 26#include "rc.h"
b622a720 27#include "ar9003_mac.h"
f4701b5a 28#include "ar9003_mci.h"
362cd03f 29#include "ar9003_phy.h"
462e58f2
BG		 30#include "debug.h"
31#include "ath9k.h"
f078f209 32
cbe61d8a 33static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 34
7322fd19
LR		 35MODULE_AUTHOR("Atheros Communications");
36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38MODULE_LICENSE("Dual BSD/GPL");
39
40static int __init ath9k_init(void)
41{
42 return 0;
43}
44module_init(ath9k_init);
45
46static void __exit ath9k_exit(void)
47{
48 return;
49}
50module_exit(ath9k_exit);
51
d70357d5
LR		 52/* Private hardware callbacks */
53
54static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
55{
56 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
57}
58
64773964
LR		 59static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
60 struct ath9k_channel *chan)
61{
62 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
63}
64
991312d8
LR		 65static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
66{
67 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
68 return;
69
70 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
71}
72
e36b27af
LR		 73static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
74{
75 /* You will not have this callback if using the old ANI */
76 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
77 return;
78
79 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
80}
81
f1dc5600
S		 82/********************/
83/* Helper Functions */
84/********************/
f078f209 85
462e58f2
BG		 86#ifdef CONFIG_ATH9K_DEBUGFS
87
462e58f2
BG		 88#endif
89
90
dfdac8ac 91static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 92{
dfdac8ac 93 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 94 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 95 unsigned int clockrate;
cbe61d8a 96
087b6ff6
FF		 97 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
98 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
99 clockrate = 117;
e4744ec7 100 else if (!chan) /* should really check for CCK instead */
dfdac8ac 101 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 102 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 103 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
104 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
105 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 106 else
dfdac8ac
FF		 107 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
108
beae416b
MN		 109 if (chan) {
110 if (IS_CHAN_HT40(chan))
111 clockrate *= 2;
e4744ec7 112 if (IS_CHAN_HALF_RATE(chan))
906c7205 113 clockrate /= 2;
e4744ec7 114 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 115 clockrate /= 4;
116 }
117
dfdac8ac 118 common->clockrate = clockrate;
f1dc5600
S		 119}
120
cbe61d8a 121static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 122{
dfdac8ac 123 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 124
dfdac8ac 125 return usecs * common->clockrate;
f1dc5600 126}
f078f209 127
0caa7b14 128bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 129{
130 int i;
131
0caa7b14
S		 132 BUG_ON(timeout < AH_TIME_QUANTUM);
133
134 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 135 if ((REG_READ(ah, reg) & mask) == val)
136 return true;
137
138 udelay(AH_TIME_QUANTUM);
139 }
04bd4638 140
d2182b69 141 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 142 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
143 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 144
f1dc5600 145 return false;
f078f209 146}
7322fd19 147EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 148
7c5adc8d
FF		 149void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
150 int hw_delay)
151{
1a5e6326 152 hw_delay /= 10;
7c5adc8d
FF		 153
154 if (IS_CHAN_HALF_RATE(chan))
155 hw_delay *= 2;
156 else if (IS_CHAN_QUARTER_RATE(chan))
157 hw_delay *= 4;
158
159 udelay(hw_delay + BASE_ACTIVATE_DELAY);
160}
161
0166b4be 162void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 163 int column, unsigned int *writecnt)
164{
165 int r;
166
167 ENABLE_REGWRITE_BUFFER(ah);
168 for (r = 0; r < array->ia_rows; r++) {
169 REG_WRITE(ah, INI_RA(array, r, 0),
170 INI_RA(array, r, column));
171 DO_DELAY(*writecnt);
172 }
173 REGWRITE_BUFFER_FLUSH(ah);
174}
175
f078f209
LR		 176u32 ath9k_hw_reverse_bits(u32 val, u32 n)
177{
178 u32 retval;
179 int i;
180
181 for (i = 0, retval = 0; i < n; i++) {
182 retval = (retval << 1) | (val & 1);
183 val >>= 1;
184 }
185 return retval;
186}
187
cbe61d8a 188u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 189 u8 phy, int kbps,
f1dc5600
S		 190 u32 frameLen, u16 rateix,
191 bool shortPreamble)
f078f209 192{
f1dc5600 193 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 194
f1dc5600
S		 195 if (kbps == 0)
196 return 0;
f078f209 197
545750d3 198 switch (phy) {
46d14a58 199 case WLAN_RC_PHY_CCK:
f1dc5600 200 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 201 if (shortPreamble)
f1dc5600
S		 202 phyTime >>= 1;
203 numBits = frameLen << 3;
204 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
205 break;
46d14a58 206 case WLAN_RC_PHY_OFDM:
2660b81a 207 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 208 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
209 numBits = OFDM_PLCP_BITS + (frameLen << 3);
210 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
211 txTime = OFDM_SIFS_TIME_QUARTER
212 + OFDM_PREAMBLE_TIME_QUARTER
213 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 214 } else if (ah->curchan &&
215 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 216 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
217 numBits = OFDM_PLCP_BITS + (frameLen << 3);
218 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
219 txTime = OFDM_SIFS_TIME_HALF +
220 OFDM_PREAMBLE_TIME_HALF
221 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
222 } else {
223 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
224 numBits = OFDM_PLCP_BITS + (frameLen << 3);
225 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
226 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
227 + (numSymbols * OFDM_SYMBOL_TIME);
228 }
229 break;
230 default:
3800276a
JP		 231 ath_err(ath9k_hw_common(ah),
232 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 233 txTime = 0;
234 break;
235 }
f078f209 236
f1dc5600
S		 237 return txTime;
238}
7322fd19 239EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 240
cbe61d8a 241void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 242 struct ath9k_channel *chan,
243 struct chan_centers *centers)
f078f209 244{
f1dc5600 245 int8_t extoff;
f078f209 246
f1dc5600
S		 247 if (!IS_CHAN_HT40(chan)) {
248 centers->ctl_center = centers->ext_center =
249 centers->synth_center = chan->channel;
250 return;
f078f209 251 }
f078f209 252
8896934c 253 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 254 centers->synth_center =
255 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
256 extoff = 1;
257 } else {
258 centers->synth_center =
259 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
260 extoff = -1;
261 }
f078f209 262
f1dc5600
S		 263 centers->ctl_center =
264 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 265 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 266 centers->ext_center =
6420014c 267 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 268}
269
f1dc5600
S		 270/******************/
271/* Chip Revisions */
272/******************/
273
cbe61d8a 274static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 275{
f1dc5600 276 u32 val;
f078f209 277
ecb1d385
VT		 278 switch (ah->hw_version.devid) {
279 case AR5416_AR9100_DEVID:
280 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
281 break;
3762561a
GJ		 282 case AR9300_DEVID_AR9330:
283 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
284 if (ah->get_mac_revision) {
285 ah->hw_version.macRev = ah->get_mac_revision();
286 } else {
287 val = REG_READ(ah, AR_SREV);
288 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
289 }
290 return;
ecb1d385
VT		 291 case AR9300_DEVID_AR9340:
292 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
293 val = REG_READ(ah, AR_SREV);
294 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
295 return;
813831dc
GJ		 296 case AR9300_DEVID_QCA955X:
297 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
298 return;
ecb1d385
VT		 299 }
300
f1dc5600 301 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 302
f1dc5600
S		 303 if (val == 0xFF) {
304 val = REG_READ(ah, AR_SREV);
d535a42a
S		 305 ah->hw_version.macVersion =
306 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
307 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 308
77fac465 309 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 310 ah->is_pciexpress = true;
311 else
312 ah->is_pciexpress = (val &
313 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 314 } else {
315 if (!AR_SREV_9100(ah))
d535a42a 316 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 317
d535a42a 318 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 319
d535a42a 320 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 321 ah->is_pciexpress = true;
f1dc5600 322 }
f078f209
LR		 323}
324
f1dc5600
S		 325/************************************/
326/* HW Attach, Detach, Init Routines */
327/************************************/
328
cbe61d8a 329static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 330{
040b74f7 331 if (!AR_SREV_5416(ah))
f1dc5600 332 return;
f078f209 333
f1dc5600
S		 334 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
335 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
336 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
337 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
338 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
339 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
340 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
341 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
342 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 343
f1dc5600 344 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 345}
346
1f3f0618 347/* This should work for all families including legacy */
cbe61d8a 348static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 349{
c46917bb 350 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 351 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 352 u32 regHold[2];
07b2fa5a
JP		 353 static const u32 patternData[4] = {
354 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
355 };
1f3f0618 356 int i, j, loop_max;
f078f209 357
1f3f0618
SB		 358 if (!AR_SREV_9300_20_OR_LATER(ah)) {
359 loop_max = 2;
360 regAddr[1] = AR_PHY_BASE + (8 << 2);
361 } else
362 loop_max = 1;
363
364 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 365 u32 addr = regAddr[i];
366 u32 wrData, rdData;
f078f209 367
f1dc5600
S		 368 regHold[i] = REG_READ(ah, addr);
369 for (j = 0; j < 0x100; j++) {
370 wrData = (j << 16) | j;
371 REG_WRITE(ah, addr, wrData);
372 rdData = REG_READ(ah, addr);
373 if (rdData != wrData) {
3800276a
JP		 374 ath_err(common,
375 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
376 addr, wrData, rdData);
f1dc5600
S		 377 return false;
378 }
379 }
380 for (j = 0; j < 4; j++) {
381 wrData = patternData[j];
382 REG_WRITE(ah, addr, wrData);
383 rdData = REG_READ(ah, addr);
384 if (wrData != rdData) {
3800276a
JP		 385 ath_err(common,
386 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
387 addr, wrData, rdData);
f1dc5600
S		 388 return false;
389 }
f078f209 390 }
f1dc5600 391 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 392 }
f1dc5600 393 udelay(100);
cbe61d8a 394
f078f209
LR		 395 return true;
396}
397
b8b0f377 398static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 399{
689e756f
FF		 400 ah->config.dma_beacon_response_time = 1;
401 ah->config.sw_beacon_response_time = 6;
2660b81a
S		 402 ah->config.ack_6mb = 0x0;
403 ah->config.cwm_ignore_extcca = 0;
2660b81a 404 ah->config.analog_shiftreg = 1;
f078f209 405
0ce024cb 406 ah->config.rx_intr_mitigation = true;
6158425b
LR		 407
408 /*
409 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
410 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
411 * This means we use it for all AR5416 devices, and the few
412 * minor PCI AR9280 devices out there.
413 *
414 * Serialization is required because these devices do not handle
415 * well the case of two concurrent reads/writes due to the latency
416 * involved. During one read/write another read/write can be issued
417 * on another CPU while the previous read/write may still be working
418 * on our hardware, if we hit this case the hardware poops in a loop.
419 * We prevent this by serializing reads and writes.
420 *
421 * This issue is not present on PCI-Express devices or pre-AR5416
422 * devices (legacy, 802.11abg).
423 */
424 if (num_possible_cpus() > 1)
2d6a5e95 425 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 426}
427
50aca25b 428static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 429{
608b88cb
LR		 430 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
431
432 regulatory->country_code = CTRY_DEFAULT;
433 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 434
d535a42a 435 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 436 ah->hw_version.subvendorid = 0;
f078f209 437
16f2411f
FF		 438 ah->sta_id1_defaults =
439 AR_STA_ID1_CRPT_MIC_ENABLE |
440 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 441 if (AR_SREV_9100(ah))
442 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
e3f2acc7 443 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 444 ah->globaltxtimeout = (u32) -1;
cbdec975 445 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 446 ah->htc_reset_init = true;
f078f209
LR		 447}
448
cbe61d8a 449static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 450{
1510718d 451 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 452 u32 sum;
453 int i;
454 u16 eeval;
07b2fa5a 455 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 456
457 sum = 0;
458 for (i = 0; i < 3; i++) {
49101676 459 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 460 sum += eeval;
1510718d
LR		 461 common->macaddr[2 * i] = eeval >> 8;
462 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 463 }
d8baa939 464 if (sum == 0 || sum == 0xffff * 3)
f078f209 465 return -EADDRNOTAVAIL;
f078f209
LR		 466
467 return 0;
468}
469
f637cfd6 470static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 471{
6cae913d 472 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 473 int ecode;
f078f209 474
6cae913d 475 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 476 if (!ath9k_hw_chip_test(ah))
477 return -ENODEV;
478 }
f078f209 479
ebd5a14a
LR		 480 if (!AR_SREV_9300_20_OR_LATER(ah)) {
481 ecode = ar9002_hw_rf_claim(ah);
482 if (ecode != 0)
483 return ecode;
484 }
f078f209 485
f637cfd6 486 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 487 if (ecode != 0)
488 return ecode;
7d01b221 489
d2182b69 490 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 491 ah->eep_ops->get_eeprom_ver(ah),
492 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 493
e323300d 494 ath9k_hw_ani_init(ah);
f078f209 495
d3b371cb
SM		 496 /*
497 * EEPROM needs to be initialized before we do this.
498 * This is required for regulatory compliance.
499 */
0c7c2bb4 500 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 501 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
502 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 503 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
504 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 505 }
506 }
507
f078f209
LR		 508 return 0;
509}
510
c1b976d2 511static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 512{
c1b976d2
FF		 513 if (!AR_SREV_9300_20_OR_LATER(ah))
514 return ar9002_hw_attach_ops(ah);
515
516 ar9003_hw_attach_ops(ah);
517 return 0;
aa4058ae
LR		 518}
519
d70357d5
LR		 520/* Called for all hardware families */
521static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 522{
c46917bb 523 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 524 int r = 0;
aa4058ae 525
ac45c12d
SB		 526 ath9k_hw_read_revisions(ah);
527
0a8d7cb0
SB		 528 /*
529 * Read back AR_WA into a permanent copy and set bits 14 and 17.
530 * We need to do this to avoid RMW of this register. We cannot
531 * read the reg when chip is asleep.
532 */
27251e00
SM		 533 if (AR_SREV_9300_20_OR_LATER(ah)) {
534 ah->WARegVal = REG_READ(ah, AR_WA);
535 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
536 AR_WA_ASPM_TIMER_BASED_DISABLE);
537 }
0a8d7cb0 538
aa4058ae 539 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 540 ath_err(common, "Couldn't reset chip\n");
95fafca2 541 return -EIO;
aa4058ae
LR		 542 }
543
a4a2954f
SM		 544 if (AR_SREV_9565(ah)) {
545 ah->WARegVal |= AR_WA_BIT22;
546 REG_WRITE(ah, AR_WA, ah->WARegVal);
547 }
548
bab1f62e
LR		 549 ath9k_hw_init_defaults(ah);
550 ath9k_hw_init_config(ah);
551
c1b976d2
FF		 552 r = ath9k_hw_attach_ops(ah);
553 if (r)
554 return r;
d70357d5 555
9ecdef4b 556 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 557 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 558 return -EIO;
aa4058ae
LR		 559 }
560
f3eef645 561 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
aa4058ae 562 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
7508b657 563 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
4c85ab11 564 !ah->is_pciexpress)) {
aa4058ae
LR		 565 ah->config.serialize_regmode =
566 SER_REG_MODE_ON;
567 } else {
568 ah->config.serialize_regmode =
569 SER_REG_MODE_OFF;
570 }
571 }
572
d2182b69 573 ath_dbg(common, RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 574 ah->config.serialize_regmode);
575
f4709fdf
LR		 576 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
577 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
578 else
579 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
580
6da5a720
FF		 581 switch (ah->hw_version.macVersion) {
582 case AR_SREV_VERSION_5416_PCI:
583 case AR_SREV_VERSION_5416_PCIE:
584 case AR_SREV_VERSION_9160:
585 case AR_SREV_VERSION_9100:
586 case AR_SREV_VERSION_9280:
587 case AR_SREV_VERSION_9285:
588 case AR_SREV_VERSION_9287:
589 case AR_SREV_VERSION_9271:
590 case AR_SREV_VERSION_9300:
2c8e5937 591 case AR_SREV_VERSION_9330:
6da5a720 592 case AR_SREV_VERSION_9485:
bca04689 593 case AR_SREV_VERSION_9340:
423e38e8 594 case AR_SREV_VERSION_9462:
2b943a33 595 case AR_SREV_VERSION_9550:
77fac465 596 case AR_SREV_VERSION_9565:
6da5a720
FF		 597 break;
598 default:
3800276a
JP		 599 ath_err(common,
600 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
601 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 602 return -EOPNOTSUPP;
aa4058ae
LR		 603 }
604
2c8e5937 605 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 606 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 607 ah->is_pciexpress = false;
608
aa4058ae 609 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 610 ath9k_hw_init_cal_settings(ah);
611
612 ah->ani_function = ATH9K_ANI_ALL;
e36b27af
LR		 613 if (!AR_SREV_9300_20_OR_LATER(ah))
614 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae 615
69ce674b 616 if (!ah->is_pciexpress)
aa4058ae
LR		 617 ath9k_hw_disablepcie(ah);
618
f637cfd6 619 r = ath9k_hw_post_init(ah);
aa4058ae 620 if (r)
95fafca2 621 return r;
aa4058ae
LR		 622
623 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 624 r = ath9k_hw_fill_cap_info(ah);
625 if (r)
626 return r;
627
4f3acf81
LR		 628 r = ath9k_hw_init_macaddr(ah);
629 if (r) {
3800276a 630 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 631 return r;
f078f209
LR		 632 }
633
d7e7d229 634 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 635 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 636 else
2660b81a 637 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 638
88e641df
GJ		 639 if (AR_SREV_9330(ah))
640 ah->bb_watchdog_timeout_ms = 85;
641 else
642 ah->bb_watchdog_timeout_ms = 25;
f078f209 643
211f5859
LR		 644 common->state = ATH_HW_INITIALIZED;
645
4f3acf81 646 return 0;
f078f209
LR		 647}
648
d70357d5 649int ath9k_hw_init(struct ath_hw *ah)
f078f209 650{
d70357d5
LR		 651 int ret;
652 struct ath_common *common = ath9k_hw_common(ah);
f078f209 653
77fac465 654 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 655 switch (ah->hw_version.devid) {
656 case AR5416_DEVID_PCI:
657 case AR5416_DEVID_PCIE:
658 case AR5416_AR9100_DEVID:
659 case AR9160_DEVID_PCI:
660 case AR9280_DEVID_PCI:
661 case AR9280_DEVID_PCIE:
662 case AR9285_DEVID_PCIE:
db3cc53a
SB		 663 case AR9287_DEVID_PCI:
664 case AR9287_DEVID_PCIE:
d70357d5 665 case AR2427_DEVID_PCIE:
db3cc53a 666 case AR9300_DEVID_PCIE:
3050c914 667 case AR9300_DEVID_AR9485_PCIE:
999a7a88 668 case AR9300_DEVID_AR9330:
bca04689 669 case AR9300_DEVID_AR9340:
2b943a33 670 case AR9300_DEVID_QCA955X:
5a63ef0f 671 case AR9300_DEVID_AR9580:
423e38e8 672 case AR9300_DEVID_AR9462:
d4e5979c 673 case AR9485_DEVID_AR1111:
77fac465 674 case AR9300_DEVID_AR9565:
d70357d5
LR		 675 break;
676 default:
677 if (common->bus_ops->ath_bus_type == ATH_USB)
678 break;
3800276a
JP		 679 ath_err(common, "Hardware device ID 0x%04x not supported\n",
680 ah->hw_version.devid);
d70357d5
LR		 681 return -EOPNOTSUPP;
682 }
f078f209 683
d70357d5
LR		 684 ret = __ath9k_hw_init(ah);
685 if (ret) {
3800276a
JP		 686 ath_err(common,
687 "Unable to initialize hardware; initialization status: %d\n",
688 ret);
d70357d5
LR		 689 return ret;
690 }
f078f209 691
d70357d5 692 return 0;
f078f209 693}
d70357d5 694EXPORT_SYMBOL(ath9k_hw_init);
f078f209 695
cbe61d8a 696static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 697{
7d0d0df0
S		 698 ENABLE_REGWRITE_BUFFER(ah);
699
f1dc5600
S		 700 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
701 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 702
f1dc5600
S		 703 REG_WRITE(ah, AR_QOS_NO_ACK,
704 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
705 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
706 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
707
708 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
709 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
710 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
711 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
712 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 713
714 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 715}
716
b84628eb 717u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 718{
f18e3c6b
MSS		 719 struct ath_common *common = ath9k_hw_common(ah);
720 int i = 0;
721
ca7a4deb
FF		 722 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
723 udelay(100);
724 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 725
f18e3c6b
MSS		 726 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
727
ca7a4deb 728 udelay(100);
b1415819 729
f18e3c6b
MSS		 730 if (WARN_ON_ONCE(i >= 100)) {
731 ath_err(common, "PLL4 meaurement not done\n");
732 break;
733 }
734
735 i++;
736 }
737
ca7a4deb 738 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 739}
740EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
741
cbe61d8a 742static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 743 struct ath9k_channel *chan)
f078f209 744{
d09b17f7
VT		 745 u32 pll;
746
a4a2954f 747 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 748 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
749 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
750 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
751 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
752 AR_CH0_DPLL2_KD, 0x40);
753 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
754 AR_CH0_DPLL2_KI, 0x4);
22983c30 755
3dfd7f60
VT		 756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
757 AR_CH0_BB_DPLL1_REFDIV, 0x5);
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
759 AR_CH0_BB_DPLL1_NINI, 0x58);
760 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
761 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 762
763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 764 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
766 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 768 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 769
3dfd7f60 770 /* program BB PLL phase_shift to 0x6 */
22983c30 771 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 772 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
773
774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
775 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 776 udelay(1000);
a5415d62
GJ		 777 } else if (AR_SREV_9330(ah)) {
778 u32 ddr_dpll2, pll_control2, kd;
779
780 if (ah->is_clk_25mhz) {
781 ddr_dpll2 = 0x18e82f01;
782 pll_control2 = 0xe04a3d;
783 kd = 0x1d;
784 } else {
785 ddr_dpll2 = 0x19e82f01;
786 pll_control2 = 0x886666;
787 kd = 0x3d;
788 }
789
790 /* program DDR PLL ki and kd value */
791 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
792
793 /* program DDR PLL phase_shift */
794 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
795 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
796
797 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
798 udelay(1000);
799
800 /* program refdiv, nint, frac to RTC register */
801 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
802
803 /* program BB PLL kd and ki value */
804 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
805 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
806
807 /* program BB PLL phase_shift */
808 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
809 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
fc05a317 810 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 811 u32 regval, pll2_divint, pll2_divfrac, refdiv;
812
813 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
814 udelay(1000);
815
816 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
817 udelay(100);
818
819 if (ah->is_clk_25mhz) {
820 pll2_divint = 0x54;
821 pll2_divfrac = 0x1eb85;
822 refdiv = 3;
823 } else {
fc05a317
GJ		 824 if (AR_SREV_9340(ah)) {
825 pll2_divint = 88;
826 pll2_divfrac = 0;
827 refdiv = 5;
828 } else {
829 pll2_divint = 0x11;
830 pll2_divfrac = 0x26666;
831 refdiv = 1;
832 }
0b488ac6
VT		 833 }
834
835 regval = REG_READ(ah, AR_PHY_PLL_MODE);
836 regval |= (0x1 << 16);
837 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
838 udelay(100);
839
840 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
841 (pll2_divint << 18) | pll2_divfrac);
842 udelay(100);
843
844 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317
GJ		 845 if (AR_SREV_9340(ah))
846 regval = (regval & 0x80071fff) | (0x1 << 30) |
847 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
848 else
849 regval = (regval & 0x80071fff) | (0x3 << 30) |
850 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
0b488ac6
VT		 851 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
852 REG_WRITE(ah, AR_PHY_PLL_MODE,
853 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
854 udelay(1000);
22983c30 855 }
d09b17f7
VT		 856
857 pll = ath9k_hw_compute_pll_control(ah, chan);
8565f8bf
SM		 858 if (AR_SREV_9565(ah))
859 pll |= 0x40000;
d03a66c1 860 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 861
fc05a317
GJ		 862 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
863 AR_SREV_9550(ah))
3dfd7f60
VT		 864 udelay(1000);
865
c75724d1
LR		 866 /* Switch the core clock for ar9271 to 117Mhz */
867 if (AR_SREV_9271(ah)) {
25e2ab17
S		 868 udelay(500);
869 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 870 }
871
f1dc5600
S		 872 udelay(RTC_PLL_SETTLE_DELAY);
873
874 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6 875
fc05a317 876 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 877 if (ah->is_clk_25mhz) {
878 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
879 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
880 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
881 } else {
882 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
883 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
884 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
885 }
886 udelay(100);
887 }
f078f209
LR		 888}
889
cbe61d8a 890static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 891 enum nl80211_iftype opmode)
f078f209 892{
79d1d2b8 893 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 894 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 895 AR_IMR_TXURN |
896 AR_IMR_RXERR |
897 AR_IMR_RXORN |
898 AR_IMR_BCNMISC;
f078f209 899
3b8a0577 900 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
79d1d2b8
VT		 901 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
902
66860240
VT		 903 if (AR_SREV_9300_20_OR_LATER(ah)) {
904 imr_reg |= AR_IMR_RXOK_HP;
905 if (ah->config.rx_intr_mitigation)
906 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
907 else
908 imr_reg |= AR_IMR_RXOK_LP;
f078f209 909
66860240
VT		 910 } else {
911 if (ah->config.rx_intr_mitigation)
912 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
913 else
914 imr_reg |= AR_IMR_RXOK;
915 }
f078f209 916
66860240
VT		 917 if (ah->config.tx_intr_mitigation)
918 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
919 else
920 imr_reg |= AR_IMR_TXOK;
f078f209 921
7d0d0df0
S		 922 ENABLE_REGWRITE_BUFFER(ah);
923
152d530d 924 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 925 ah->imrs2_reg |= AR_IMR_S2_GTT;
926 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 927
f1dc5600
S		 928 if (!AR_SREV_9100(ah)) {
929 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 930 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 931 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
932 }
66860240 933
7d0d0df0 934 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 935
66860240
VT		 936 if (AR_SREV_9300_20_OR_LATER(ah)) {
937 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
938 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
939 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
940 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
941 }
f078f209
LR		 942}
943
b6ba41bb
FF		 944static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
945{
946 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
947 val = min(val, (u32) 0xFFFF);
948 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
949}
950
0005baf4 951static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 952{
0005baf4
FF		 953 u32 val = ath9k_hw_mac_to_clks(ah, us);
954 val = min(val, (u32) 0xFFFF);
955 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 956}
957
0005baf4 958static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 959{
0005baf4
FF		 960 u32 val = ath9k_hw_mac_to_clks(ah, us);
961 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
962 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
963}
964
965static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
966{
967 u32 val = ath9k_hw_mac_to_clks(ah, us);
968 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
969 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 970}
f1dc5600 971
cbe61d8a 972static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 973{
f078f209 974 if (tu > 0xFFFF) {
d2182b69
JP		 975 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
976 tu);
2660b81a 977 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 978 return false;
979 } else {
980 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 981 ah->globaltxtimeout = tu;
f078f209
LR		 982 return true;
983 }
984}
985
0005baf4 986void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 987{
b6ba41bb 988 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 989 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 990 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 991 int slottime;
0005baf4 992 int sifstime;
b6ba41bb
FF		 993 int rx_lat = 0, tx_lat = 0, eifs = 0;
994 u32 reg;
0005baf4 995
d2182b69 996 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 997 ah->misc_mode);
f078f209 998
b6ba41bb
FF		 999 if (!chan)
1000 return;
1001
2660b81a 1002 if (ah->misc_mode != 0)
ca7a4deb 1003 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1004
81a91d57
RM		 1005 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1006 rx_lat = 41;
1007 else
1008 rx_lat = 37;
b6ba41bb
FF		 1009 tx_lat = 54;
1010
e88e4861
FF		 1011 if (IS_CHAN_5GHZ(chan))
1012 sifstime = 16;
1013 else
1014 sifstime = 10;
1015
b6ba41bb
FF		 1016 if (IS_CHAN_HALF_RATE(chan)) {
1017 eifs = 175;
1018 rx_lat *= 2;
1019 tx_lat *= 2;
1020 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1021 tx_lat += 11;
1022
92367fe7 1023 sifstime = 32;
e115b7ec 1024 ack_offset = 16;
b6ba41bb 1025 slottime = 13;
b6ba41bb
FF		 1026 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1027 eifs = 340;
81a91d57 1028 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1029 tx_lat *= 4;
1030 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1031 tx_lat += 22;
1032
92367fe7 1033 sifstime = 64;
e115b7ec 1034 ack_offset = 32;
b6ba41bb 1035 slottime = 21;
b6ba41bb 1036 } else {
a7be039d
RM		 1037 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1038 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1039 reg = AR_USEC_ASYNC_FIFO;
1040 } else {
1041 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1042 common->clockrate;
1043 reg = REG_READ(ah, AR_USEC);
1044 }
b6ba41bb
FF		 1045 rx_lat = MS(reg, AR_USEC_RX_LAT);
1046 tx_lat = MS(reg, AR_USEC_TX_LAT);
1047
1048 slottime = ah->slottime;
b6ba41bb 1049 }
0005baf4 1050
e239d859 1051 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1052 slottime += 3 * ah->coverage_class;
1053 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1054 ctstimeout = acktimeout;
42c4568a
FF		 1055
1056 /*
1057 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1058 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1059 * This was initially only meant to work around an issue with delayed
1060 * BA frames in some implementations, but it has been found to fix ACK
1061 * timeout issues in other cases as well.
1062 */
e4744ec7 1063 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1064 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1065 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1066 ctstimeout += 48 - sifstime - ah->slottime;
1067 }
1068
b6ba41bb
FF		 1069 ath9k_hw_set_sifs_time(ah, sifstime);
1070 ath9k_hw_setslottime(ah, slottime);
0005baf4 1071 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1072 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1073 if (ah->globaltxtimeout != (u32) -1)
1074 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1075
1076 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1077 REG_RMW(ah, AR_USEC,
1078 (common->clockrate - 1) |
1079 SM(rx_lat, AR_USEC_RX_LAT) |
1080 SM(tx_lat, AR_USEC_TX_LAT),
1081 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1082
f1dc5600 1083}
0005baf4 1084EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1085
285f2dda 1086void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1087{
211f5859
LR		 1088 struct ath_common *common = ath9k_hw_common(ah);
1089
736b3a27 1090 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1091 return;
211f5859 1092
9ecdef4b 1093 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1094}
285f2dda 1095EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1096
f1dc5600
S		 1097/*******/
1098/* INI */
1099/*******/
1100
8fe65368 1101u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1102{
1103 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1104
6b21fd20 1105 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1106 ctl |= CTL_11G;
1107 else
1108 ctl |= CTL_11A;
1109
1110 return ctl;
1111}
1112
f1dc5600
S		 1113/****************************************/
1114/* Reset and Channel Switching Routines */
1115/****************************************/
f1dc5600 1116
cbe61d8a 1117static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1118{
57b32227 1119 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1120 int txbuf_size;
f1dc5600 1121
7d0d0df0
S		 1122 ENABLE_REGWRITE_BUFFER(ah);
1123
d7e7d229
LR		 1124 /*
1125 * set AHB_MODE not to do cacheline prefetches
1126 */
ca7a4deb
FF		 1127 if (!AR_SREV_9300_20_OR_LATER(ah))
1128 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1129
d7e7d229
LR		 1130 /*
1131 * let mac dma reads be in 128 byte chunks
1132 */
ca7a4deb 1133 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1134
7d0d0df0 1135 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1136
d7e7d229
LR		 1137 /*
1138 * Restore TX Trigger Level to its pre-reset value.
1139 * The initial value depends on whether aggregation is enabled, and is
1140 * adjusted whenever underruns are detected.
1141 */
57b32227
FF		 1142 if (!AR_SREV_9300_20_OR_LATER(ah))
1143 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1144
7d0d0df0 1145 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1146
d7e7d229
LR		 1147 /*
1148 * let mac dma writes be in 128 byte chunks
1149 */
ca7a4deb 1150 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1151
d7e7d229
LR		 1152 /*
1153 * Setup receive FIFO threshold to hold off TX activities
1154 */
f1dc5600
S		 1155 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1156
57b32227
FF		 1157 if (AR_SREV_9300_20_OR_LATER(ah)) {
1158 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1159 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1160
1161 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1162 ah->caps.rx_status_len);
1163 }
1164
d7e7d229
LR		 1165 /*
1166 * reduce the number of usable entries in PCU TXBUF to avoid
1167 * wrap around issues.
1168 */
f1dc5600 1169 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1170 /* For AR9285 the number of Fifos are reduced to half.
1171 * So set the usable tx buf size also to half to
1172 * avoid data/delimiter underruns
1173 */
86c157b3
FF		 1174 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1175 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1176 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1177 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1178 } else {
1179 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1180 }
744d4025 1181
86c157b3
FF		 1182 if (!AR_SREV_9271(ah))
1183 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1184
7d0d0df0 1185 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1186
744d4025
VT		 1187 if (AR_SREV_9300_20_OR_LATER(ah))
1188 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1189}
1190
cbe61d8a 1191static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1192{
ca7a4deb
FF		 1193 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1194 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1195
f1dc5600 1196 switch (opmode) {
d97809db 1197 case NL80211_IFTYPE_ADHOC:
ca7a4deb 1198 set |= AR_STA_ID1_ADHOC;
f1dc5600 1199 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1200 break;
2664d666 1201 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1202 case NL80211_IFTYPE_AP:
1203 set |= AR_STA_ID1_STA_AP;
1204 /* fall through */
d97809db 1205 case NL80211_IFTYPE_STATION:
ca7a4deb 1206 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1207 break;
5f841b41 1208 default:
ca7a4deb
FF		 1209 if (!ah->is_monitoring)
1210 set = 0;
5f841b41 1211 break;
f1dc5600 1212 }
ca7a4deb 1213 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1214}
1215
8fe65368
LR		 1216void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1217 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1218{
1219 u32 coef_exp, coef_man;
1220
1221 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1222 if ((coef_scaled >> coef_exp) & 0x1)
1223 break;
1224
1225 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1226
1227 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1228
1229 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1230 *coef_exponent = coef_exp - 16;
1231}
1232
d7df7a55
SM		 1233/* AR9330 WAR:
1234 * call external reset function to reset WMAC if:
1235 * - doing a cold reset
1236 * - we have pending frames in the TX queues.
1237 */
1238static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1239{
1240 int i, npend = 0;
1241
1242 for (i = 0; i < AR_NUM_QCU; i++) {
1243 npend = ath9k_hw_numtxpending(ah, i);
1244 if (npend)
1245 break;
1246 }
1247
1248 if (ah->external_reset &&
1249 (npend || type == ATH9K_RESET_COLD)) {
1250 int reset_err = 0;
1251
1252 ath_dbg(ath9k_hw_common(ah), RESET,
1253 "reset MAC via external reset\n");
1254
1255 reset_err = ah->external_reset();
1256 if (reset_err) {
1257 ath_err(ath9k_hw_common(ah),
1258 "External reset failed, err=%d\n",
1259 reset_err);
1260 return false;
1261 }
1262
1263 REG_WRITE(ah, AR_RTC_RESET, 1);
1264 }
1265
1266 return true;
1267}
1268
cbe61d8a 1269static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1270{
1271 u32 rst_flags;
1272 u32 tmpReg;
1273
70768496 1274 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1275 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1276 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1277 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1278 }
1279
7d0d0df0
S		 1280 ENABLE_REGWRITE_BUFFER(ah);
1281
9a658d2b
LR		 1282 if (AR_SREV_9300_20_OR_LATER(ah)) {
1283 REG_WRITE(ah, AR_WA, ah->WARegVal);
1284 udelay(10);
1285 }
1286
f1dc5600
S		 1287 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1288 AR_RTC_FORCE_WAKE_ON_INT);
1289
1290 if (AR_SREV_9100(ah)) {
1291 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1292 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1293 } else {
1294 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1295 if (AR_SREV_9340(ah))
1296 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1297 else
1298 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1299 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1300
1301 if (tmpReg) {
42d5bc3f 1302 u32 val;
f1dc5600 1303 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1304
1305 val = AR_RC_HOSTIF;
1306 if (!AR_SREV_9300_20_OR_LATER(ah))
1307 val |= AR_RC_AHB;
1308 REG_WRITE(ah, AR_RC, val);
1309
1310 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1311 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1312
1313 rst_flags = AR_RTC_RC_MAC_WARM;
1314 if (type == ATH9K_RESET_COLD)
1315 rst_flags |= AR_RTC_RC_MAC_COLD;
1316 }
1317
7d95847c 1318 if (AR_SREV_9330(ah)) {
d7df7a55
SM		 1319 if (!ath9k_hw_ar9330_reset_war(ah, type))
1320 return false;
7d95847c
GJ		 1321 }
1322
3863495b 1323 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1324 ar9003_mci_check_gpm_offset(ah);
3863495b 1325
d03a66c1 1326 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1327
1328 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1329
4dc78c43
SM		 1330 if (AR_SREV_9300_20_OR_LATER(ah))
1331 udelay(50);
1332 else if (AR_SREV_9100(ah))
1333 udelay(10000);
1334 else
1335 udelay(100);
f1dc5600 1336
d03a66c1 1337 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1338 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1339 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1340 return false;
1341 }
1342
1343 if (!AR_SREV_9100(ah))
1344 REG_WRITE(ah, AR_RC, 0);
1345
f1dc5600
S		 1346 if (AR_SREV_9100(ah))
1347 udelay(50);
1348
1349 return true;
1350}
1351
cbe61d8a 1352static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1353{
7d0d0df0
S		 1354 ENABLE_REGWRITE_BUFFER(ah);
1355
9a658d2b
LR		 1356 if (AR_SREV_9300_20_OR_LATER(ah)) {
1357 REG_WRITE(ah, AR_WA, ah->WARegVal);
1358 udelay(10);
1359 }
1360
f1dc5600
S		 1361 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1362 AR_RTC_FORCE_WAKE_ON_INT);
1363
42d5bc3f 1364 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1365 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1366
d03a66c1 1367 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1368
7d0d0df0 1369 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1370
afe36533 1371 udelay(2);
84e2169b
SB		 1372
1373 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1374 REG_WRITE(ah, AR_RC, 0);
1375
d03a66c1 1376 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1377
1378 if (!ath9k_hw_wait(ah,
1379 AR_RTC_STATUS,
1380 AR_RTC_STATUS_M,
0caa7b14
S		 1381 AR_RTC_STATUS_ON,
1382 AH_WAIT_TIMEOUT)) {
d2182b69 1383 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1384 return false;
f078f209
LR		 1385 }
1386
f1dc5600
S		 1387 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1388}
1389
cbe61d8a 1390static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1391{
7a9233ff 1392 bool ret = false;
2577c6e8 1393
9a658d2b
LR		 1394 if (AR_SREV_9300_20_OR_LATER(ah)) {
1395 REG_WRITE(ah, AR_WA, ah->WARegVal);
1396 udelay(10);
1397 }
1398
f1dc5600
S		 1399 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1400 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1401
ceb26a60
FF		 1402 if (!ah->reset_power_on)
1403 type = ATH9K_RESET_POWER_ON;
1404
f1dc5600
S		 1405 switch (type) {
1406 case ATH9K_RESET_POWER_ON:
7a9233ff 1407 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1408 if (ret)
ceb26a60 1409 ah->reset_power_on = true;
7a9233ff 1410 break;
f1dc5600
S		 1411 case ATH9K_RESET_WARM:
1412 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1413 ret = ath9k_hw_set_reset(ah, type);
1414 break;
f1dc5600 1415 default:
7a9233ff 1416 break;
f1dc5600 1417 }
7a9233ff 1418
7a9233ff 1419 return ret;
f078f209
LR		 1420}
1421
cbe61d8a 1422static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1423 struct ath9k_channel *chan)
f078f209 1424{
9c083af8
FF		 1425 int reset_type = ATH9K_RESET_WARM;
1426
1427 if (AR_SREV_9280(ah)) {
1428 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1429 reset_type = ATH9K_RESET_POWER_ON;
1430 else
1431 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1432 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1433 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1434 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1435
1436 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1437 return false;
f078f209 1438
9ecdef4b 1439 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1440 return false;
f078f209 1441
2660b81a 1442 ah->chip_fullsleep = false;
bfc441a4
FF		 1443
1444 if (AR_SREV_9330(ah))
1445 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1446 ath9k_hw_init_pll(ah, chan);
f078f209 1447
f1dc5600 1448 return true;
f078f209
LR		 1449}
1450
cbe61d8a 1451static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1452 struct ath9k_channel *chan)
f078f209 1453{
c46917bb 1454 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1455 struct ath9k_hw_capabilities *pCap = &ah->caps;
1456 bool band_switch = false, mode_diff = false;
70e89a71 1457 u8 ini_reloaded = 0;
8fe65368 1458 u32 qnum;
0a3b7bac 1459 int r;
5f0c04ea 1460
b840cffe 1461 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1462 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1463 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1464 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1465 }
f078f209
LR		 1466
1467 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1468 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1469 ath_dbg(common, QUEUE,
226afe68 1470 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1471 return false;
1472 }
1473 }
1474
8fe65368 1475 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1476 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1477 return false;
1478 }
1479
b840cffe 1480 if (band_switch || mode_diff) {
5f0c04ea
RM		 1481 ath9k_hw_mark_phy_inactive(ah);
1482 udelay(5);
1483
5f35c0fa
SM		 1484 if (band_switch)
1485 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1486
1487 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1488 ath_err(common, "Failed to do fast channel change\n");
1489 return false;
1490 }
1491 }
1492
8fe65368 1493 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1494
8fe65368 1495 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1496 if (r) {
3800276a 1497 ath_err(common, "Failed to set channel\n");
0a3b7bac 1498 return false;
f078f209 1499 }
dfdac8ac 1500 ath9k_hw_set_clockrate(ah);
64ea57d0 1501 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1502
81c507a8 1503 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1504 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1505
70e89a71
SM		 1506 if (band_switch || ini_reloaded)
1507 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1508
70e89a71
SM		 1509 ath9k_hw_init_bb(ah, chan);
1510 ath9k_hw_rfbus_done(ah);
5f0c04ea 1511
70e89a71
SM		 1512 if (band_switch || ini_reloaded) {
1513 ah->ah_flags |= AH_FASTCC;
1514 ath9k_hw_init_cal(ah, chan);
a126ff51 1515 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1516 }
1517
f1dc5600
S		 1518 return true;
1519}
1520
691680b8
FF		 1521static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1522{
1523 u32 gpio_mask = ah->gpio_mask;
1524 int i;
1525
1526 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1527 if (!(gpio_mask & 1))
1528 continue;
1529
1530 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1531 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1532 }
1533}
1534
01e18918
RM		 1535static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1536 int *hang_state, int *hang_pos)
1537{
1538 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1539 u32 chain_state, dcs_pos, i;
1540
1541 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1542 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1543 for (i = 0; i < 3; i++) {
1544 if (chain_state == dcu_chain_state[i]) {
1545 *hang_state = chain_state;
1546 *hang_pos = dcs_pos;
1547 return true;
1548 }
1549 }
1550 }
1551 return false;
1552}
1553
1554#define DCU_COMPLETE_STATE 1
1555#define DCU_COMPLETE_STATE_MASK 0x3
1556#define NUM_STATUS_READS 50
1557static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1558{
1559 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1560 u32 i, hang_pos, hang_state, num_state = 6;
1561
1562 comp_state = REG_READ(ah, AR_DMADBG_6);
1563
1564 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1565 ath_dbg(ath9k_hw_common(ah), RESET,
1566 "MAC Hang signature not found at DCU complete\n");
1567 return false;
1568 }
1569
1570 chain_state = REG_READ(ah, dcs_reg);
1571 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1572 goto hang_check_iter;
1573
1574 dcs_reg = AR_DMADBG_5;
1575 num_state = 4;
1576 chain_state = REG_READ(ah, dcs_reg);
1577 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1578 goto hang_check_iter;
1579
1580 ath_dbg(ath9k_hw_common(ah), RESET,
1581 "MAC Hang signature 1 not found\n");
1582 return false;
1583
1584hang_check_iter:
1585 ath_dbg(ath9k_hw_common(ah), RESET,
1586 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1587 chain_state, comp_state, hang_state, hang_pos);
1588
1589 for (i = 0; i < NUM_STATUS_READS; i++) {
1590 chain_state = REG_READ(ah, dcs_reg);
1591 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1592 comp_state = REG_READ(ah, AR_DMADBG_6);
1593
1594 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1595 DCU_COMPLETE_STATE) ||
1596 (chain_state != hang_state))
1597 return false;
1598 }
1599
1600 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1601
1602 return true;
1603}
1604
1e516ca7
SM		 1605void ath9k_hw_check_nav(struct ath_hw *ah)
1606{
1607 struct ath_common *common = ath9k_hw_common(ah);
1608 u32 val;
1609
1610 val = REG_READ(ah, AR_NAV);
1611 if (val != 0xdeadbeef && val > 0x7fff) {
1612 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1613 REG_WRITE(ah, AR_NAV, 0);
1614 }
1615}
1616EXPORT_SYMBOL(ath9k_hw_check_nav);
1617
c9c99e5e 1618bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1619{
c9c99e5e
FF		 1620 int count = 50;
1621 u32 reg;
1622
01e18918
RM		 1623 if (AR_SREV_9300(ah))
1624 return !ath9k_hw_detect_mac_hang(ah);
1625
e17f83ea 1626 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1627 return true;
1628
1629 do {
1630 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1631
c9c99e5e
FF		 1632 if ((reg & 0x7E7FFFEF) == 0x00702400)
1633 continue;
1634
1635 switch (reg & 0x7E000B00) {
1636 case 0x1E000000:
1637 case 0x52000B00:
1638 case 0x18000B00:
1639 continue;
1640 default:
1641 return true;
1642 }
1643 } while (count-- > 0);
3b319aae 1644
c9c99e5e 1645 return false;
3b319aae 1646}
c9c99e5e 1647EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1648
15d2b585
SM		 1649static void ath9k_hw_init_mfp(struct ath_hw *ah)
1650{
1651 /* Setup MFP options for CCMP */
1652 if (AR_SREV_9280_20_OR_LATER(ah)) {
1653 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1654 * frames when constructing CCMP AAD. */
1655 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1656 0xc7ff);
1657 ah->sw_mgmt_crypto = false;
1658 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1659 /* Disable hardware crypto for management frames */
1660 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1661 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1662 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1663 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1664 ah->sw_mgmt_crypto = true;
1665 } else {
1666 ah->sw_mgmt_crypto = true;
1667 }
1668}
1669
1670static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1671 u32 macStaId1, u32 saveDefAntenna)
1672{
1673 struct ath_common *common = ath9k_hw_common(ah);
1674
1675 ENABLE_REGWRITE_BUFFER(ah);
1676
ecbbed32 1677 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585
SM		 1678 | AR_STA_ID1_RTS_USE_DEF
1679 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
ecbbed32
FF		 1680 | ah->sta_id1_defaults,
1681 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1682 ath_hw_setbssidmask(common);
1683 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1684 ath9k_hw_write_associd(ah);
1685 REG_WRITE(ah, AR_ISR, ~0);
1686 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1687
1688 REGWRITE_BUFFER_FLUSH(ah);
1689
1690 ath9k_hw_set_operating_mode(ah, ah->opmode);
1691}
1692
1693static void ath9k_hw_init_queues(struct ath_hw *ah)
1694{
1695 int i;
1696
1697 ENABLE_REGWRITE_BUFFER(ah);
1698
1699 for (i = 0; i < AR_NUM_DCU; i++)
1700 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1701
1702 REGWRITE_BUFFER_FLUSH(ah);
1703
1704 ah->intr_txqs = 0;
1705 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1706 ath9k_hw_resettxqueue(ah, i);
1707}
1708
1709/*
1710 * For big endian systems turn on swapping for descriptors
1711 */
1712static void ath9k_hw_init_desc(struct ath_hw *ah)
1713{
1714 struct ath_common *common = ath9k_hw_common(ah);
1715
1716 if (AR_SREV_9100(ah)) {
1717 u32 mask;
1718 mask = REG_READ(ah, AR_CFG);
1719 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1720 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1721 mask);
1722 } else {
1723 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1724 REG_WRITE(ah, AR_CFG, mask);
1725 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1726 REG_READ(ah, AR_CFG));
1727 }
1728 } else {
1729 if (common->bus_ops->ath_bus_type == ATH_USB) {
1730 /* Configure AR9271 target WLAN */
1731 if (AR_SREV_9271(ah))
1732 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1733 else
1734 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1735 }
1736#ifdef __BIG_ENDIAN
1737 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1738 AR_SREV_9550(ah))
1739 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1740 else
1741 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1742#endif
1743 }
1744}
1745
caed6579
SM		 1746/*
1747 * Fast channel change:
1748 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1749 */
1750static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1751{
1752 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1753 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1754 int ret;
1755
1756 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1757 goto fail;
1758
1759 if (ah->chip_fullsleep)
1760 goto fail;
1761
1762 if (!ah->curchan)
1763 goto fail;
1764
1765 if (chan->channel == ah->curchan->channel)
1766 goto fail;
1767
feb7bc99
FF		 1768 if ((ah->curchan->channelFlags | chan->channelFlags) &
1769 (CHANNEL_HALF | CHANNEL_QUARTER))
1770 goto fail;
1771
b840cffe 1772 /*
6b21fd20 1773 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1774 */
6b21fd20 1775 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1776 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1777 goto fail;
caed6579
SM		 1778
1779 if (!ath9k_hw_check_alive(ah))
1780 goto fail;
1781
1782 /*
1783 * For AR9462, make sure that calibration data for
1784 * re-using are present.
1785 */
8a90555f 1786 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1787 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1788 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1789 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1790 goto fail;
1791
1792 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1793 ah->curchan->channel, chan->channel);
1794
1795 ret = ath9k_hw_channel_change(ah, chan);
1796 if (!ret)
1797 goto fail;
1798
5955b2b0 1799 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1800 ar9003_mci_2g5g_switch(ah, false);
caed6579 1801
88033318
RM		 1802 ath9k_hw_loadnf(ah, ah->curchan);
1803 ath9k_hw_start_nfcal(ah, true);
1804
caed6579
SM		 1805 if (AR_SREV_9271(ah))
1806 ar9002_hw_load_ani_reg(ah, chan);
1807
1808 return 0;
1809fail:
1810 return -EINVAL;
1811}
1812
cbe61d8a 1813int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1814 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1815{
1510718d 1816 struct ath_common *common = ath9k_hw_common(ah);
09d8e315 1817 struct timespec ts;
f078f209 1818 u32 saveLedState;
f078f209
LR		 1819 u32 saveDefAntenna;
1820 u32 macStaId1;
46fe782c 1821 u64 tsf = 0;
09d8e315 1822 s64 usec = 0;
15d2b585 1823 int r;
caed6579 1824 bool start_mci_reset = false;
63d32967
MSS		 1825 bool save_fullsleep = ah->chip_fullsleep;
1826
5955b2b0 1827 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1828 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1829 if (start_mci_reset)
1830 return 0;
63d32967
MSS		 1831 }
1832
9ecdef4b 1833 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1834 return -EIO;
f078f209 1835
caed6579
SM		 1836 if (ah->curchan && !ah->chip_fullsleep)
1837 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1838
20bd2a09 1839 ah->caldata = caldata;
fcb9a3de 1840 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1841 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1842 /* Operating channel changed, reset channel calibration data */
1843 memset(caldata, 0, sizeof(*caldata));
1844 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1845 } else if (caldata) {
4b9b42bf 1846 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1847 }
5bc225ac 1848 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1849
caed6579
SM		 1850 if (fastcc) {
1851 r = ath9k_hw_do_fastcc(ah, chan);
1852 if (!r)
1853 return r;
f078f209
LR		 1854 }
1855
5955b2b0 1856 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1857 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1858
f078f209
LR		 1859 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1860 if (saveDefAntenna == 0)
1861 saveDefAntenna = 1;
1862
1863 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1864
09d8e315
FF		 1865 /* Save TSF before chip reset, a cold reset clears it */
1866 tsf = ath9k_hw_gettsf64(ah);
1867 getrawmonotonic(&ts);
1868 usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000;
46fe782c 1869
f078f209
LR		 1870 saveLedState = REG_READ(ah, AR_CFG_LED) &
1871 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1872 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1873
1874 ath9k_hw_mark_phy_inactive(ah);
1875
45ef6a0b
VT		 1876 ah->paprd_table_write_done = false;
1877
05020d23 1878 /* Only required on the first reset */
d7e7d229
LR		 1879 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1880 REG_WRITE(ah,
1881 AR9271_RESET_POWER_DOWN_CONTROL,
1882 AR9271_RADIO_RF_RST);
1883 udelay(50);
1884 }
1885
f078f209 1886 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1887 ath_err(common, "Chip reset failed\n");
ae8d2858 1888 return -EINVAL;
f078f209
LR		 1889 }
1890
05020d23 1891 /* Only required on the first reset */
d7e7d229
LR		 1892 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1893 ah->htc_reset_init = false;
1894 REG_WRITE(ah,
1895 AR9271_RESET_POWER_DOWN_CONTROL,
1896 AR9271_GATE_MAC_CTL);
1897 udelay(50);
1898 }
1899
46fe782c 1900 /* Restore TSF */
09d8e315
FF		 1901 getrawmonotonic(&ts);
1902 usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec;
1903 ath9k_hw_settsf64(ah, tsf + usec);
46fe782c 1904
7a37081e 1905 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1906 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1907
e9141f71
S		 1908 if (!AR_SREV_9300_20_OR_LATER(ah))
1909 ar9002_hw_enable_async_fifo(ah);
1910
25c56eec 1911 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1912 if (r)
1913 return r;
f078f209 1914
935d00cc
LB		 1915 ath9k_hw_set_rfmode(ah, chan);
1916
5955b2b0 1917 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1918 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1919
f860d526
FF		 1920 /*
1921 * Some AR91xx SoC devices frequently fail to accept TSF writes
1922 * right after the chip reset. When that happens, write a new
1923 * value after the initvals have been applied, with an offset
1924 * based on measured time difference
1925 */
1926 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1927 tsf += 1500;
1928 ath9k_hw_settsf64(ah, tsf);
1929 }
1930
15d2b585 1931 ath9k_hw_init_mfp(ah);
0ced0e17 1932
81c507a8 1933 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1934 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1935 ah->eep_ops->set_board_values(ah, chan);
a7765828 1936
15d2b585 1937 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1938
8fe65368 1939 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1940 if (r)
1941 return r;
f078f209 1942
dfdac8ac
FF		 1943 ath9k_hw_set_clockrate(ah);
1944
15d2b585 1945 ath9k_hw_init_queues(ah);
2660b81a 1946 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1947 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1948 ath9k_hw_init_qos(ah);
1949
2660b81a 1950 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1951 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1952
0005baf4 1953 ath9k_hw_init_global_settings(ah);
f078f209 1954
fe2b6afb
FF		 1955 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1956 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1957 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1958 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1959 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1960 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1961 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1962 }
1963
ca7a4deb 1964 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1965
1966 ath9k_hw_set_dma(ah);
1967
ed6ebd8b
RM		 1968 if (!ath9k_hw_mci_is_enabled(ah))
1969 REG_WRITE(ah, AR_OBS, 8);
f078f209 1970
0ce024cb 1971 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1972 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1973 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1974 }
1975
7f62a136
VT		 1976 if (ah->config.tx_intr_mitigation) {
1977 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1978 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1979 }
1980
f078f209
LR		 1981 ath9k_hw_init_bb(ah, chan);
1982
77a5a664 1983 if (caldata) {
4b9b42bf
SM		 1984 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1985 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 1986 }
ae8d2858 1987 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1988 return -EIO;
f078f209 1989
5955b2b0 1990 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 1991 return -EIO;
63d32967 1992
7d0d0df0 1993 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1994
8fe65368 1995 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1996 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1997
7d0d0df0 1998 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1999
15d2b585 2000 ath9k_hw_init_desc(ah);
f078f209 2001
dbccdd1d 2002 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 2003 ath9k_hw_btcoex_enable(ah);
2004
5955b2b0 2005 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 2006 ar9003_mci_check_bt(ah);
63d32967 2007
1fe860ed
RM		 2008 ath9k_hw_loadnf(ah, chan);
2009 ath9k_hw_start_nfcal(ah, true);
2010
51ac8cbb 2011 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 2012 ar9003_hw_bb_watchdog_config(ah);
51ac8cbb
RM		 2013 ar9003_hw_disable_phy_restart(ah);
2014 }
2015
691680b8
FF		 2016 ath9k_hw_apply_gpio_override(ah);
2017
7bdea96a 2018 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 2019 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2020
ae8d2858 2021 return 0;
f078f209 2022}
7322fd19 2023EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2024
f1dc5600
S		 2025/******************************/
2026/* Power Management (Chipset) */
2027/******************************/
2028
42d5bc3f
LR		 2029/*
2030 * Notify Power Mgt is disabled in self-generated frames.
2031 * If requested, force chip to sleep.
2032 */
31604cf0 2033static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 2034{
f1dc5600 2035 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 2036
a4a2954f 2037 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 2038 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2039 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2040 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 2041 /* xxx Required for WLAN only case ? */
2042 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2043 udelay(100);
2044 }
2577c6e8 2045
31604cf0
SM		 2046 /*
2047 * Clear the RTC force wake bit to allow the
2048 * mac to go to sleep.
2049 */
2050 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2051
153dccd4 2052 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2053 udelay(100);
2577c6e8 2054
31604cf0
SM		 2055 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2056 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2057
31604cf0
SM		 2058 /* Shutdown chip. Active low */
2059 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2060 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2061 udelay(2);
f1dc5600 2062 }
9a658d2b
LR		 2063
2064 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2065 if (AR_SREV_9300_20_OR_LATER(ah))
2066 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2067}
2068
bbd79af5
LR		 2069/*
2070 * Notify Power Management is enabled in self-generating
2071 * frames. If request, set power mode of chip to
2072 * auto/normal. Duration in units of 128us (1/8 TU).
2073 */
31604cf0 2074static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2075{
31604cf0 2076 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2077
f1dc5600 2078 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2079
31604cf0
SM		 2080 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2081 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2082 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2083 AR_RTC_FORCE_WAKE_ON_INT);
2084 } else {
2577c6e8 2085
31604cf0
SM		 2086 /* When chip goes into network sleep, it could be waken
2087 * up by MCI_INT interrupt caused by BT's HW messages
2088 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2089 * rate (~100us). This will cause chip to leave and
2090 * re-enter network sleep mode frequently, which in
2091 * consequence will have WLAN MCI HW to generate lots of
2092 * SYS_WAKING and SYS_SLEEPING messages which will make
2093 * BT CPU to busy to process.
2094 */
153dccd4
RM		 2095 if (ath9k_hw_mci_is_enabled(ah))
2096 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2097 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2098 /*
2099 * Clear the RTC force wake bit to allow the
2100 * mac to go to sleep.
2101 */
153dccd4 2102 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2103
153dccd4 2104 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2105 udelay(30);
f078f209 2106 }
9a658d2b
LR		 2107
2108 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2109 if (AR_SREV_9300_20_OR_LATER(ah))
2110 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2111}
2112
31604cf0 2113static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2114{
f1dc5600
S		 2115 u32 val;
2116 int i;
f078f209 2117
9a658d2b
LR		 2118 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2119 if (AR_SREV_9300_20_OR_LATER(ah)) {
2120 REG_WRITE(ah, AR_WA, ah->WARegVal);
2121 udelay(10);
2122 }
2123
31604cf0
SM		 2124 if ((REG_READ(ah, AR_RTC_STATUS) &
2125 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2126 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2127 return false;
f1dc5600 2128 }
31604cf0
SM		 2129 if (!AR_SREV_9300_20_OR_LATER(ah))
2130 ath9k_hw_init_pll(ah, NULL);
2131 }
2132 if (AR_SREV_9100(ah))
2133 REG_SET_BIT(ah, AR_RTC_RESET,
2134 AR_RTC_RESET_EN);
2135
2136 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2137 AR_RTC_FORCE_WAKE_EN);
2138 udelay(50);
f078f209 2139
31604cf0
SM		 2140 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2141 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2142 if (val == AR_RTC_STATUS_ON)
2143 break;
2144 udelay(50);
f1dc5600
S		 2145 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2146 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2147 }
2148 if (i == 0) {
2149 ath_err(ath9k_hw_common(ah),
2150 "Failed to wakeup in %uus\n",
2151 POWER_UP_TIME / 20);
2152 return false;
f078f209
LR		 2153 }
2154
cdbe408d
RM		 2155 if (ath9k_hw_mci_is_enabled(ah))
2156 ar9003_mci_set_power_awake(ah);
2157
f1dc5600 2158 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2159
f1dc5600 2160 return true;
f078f209
LR		 2161}
2162
9ecdef4b 2163bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2164{
c46917bb 2165 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2166 int status = true;
f1dc5600
S		 2167 static const char *modes[] = {
2168 "AWAKE",
2169 "FULL-SLEEP",
2170 "NETWORK SLEEP",
2171 "UNDEFINED"
2172 };
f1dc5600 2173
cbdec975
GJ		 2174 if (ah->power_mode == mode)
2175 return status;
2176
d2182b69 2177 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2178 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2179
2180 switch (mode) {
2181 case ATH9K_PM_AWAKE:
31604cf0 2182 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2183 break;
2184 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2185 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2186 ar9003_mci_set_full_sleep(ah);
1010911e 2187
31604cf0 2188 ath9k_set_power_sleep(ah);
2660b81a 2189 ah->chip_fullsleep = true;
f1dc5600
S		 2190 break;
2191 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2192 ath9k_set_power_network_sleep(ah);
f1dc5600 2193 break;
f078f209 2194 default:
3800276a 2195 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2196 return false;
2197 }
2660b81a 2198 ah->power_mode = mode;
f1dc5600 2199
69f4aab1
LR		 2200 /*
2201 * XXX: If this warning never comes up after a while then
2202 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2203 * ath9k_hw_setpower() return type void.
2204 */
97dcec57
SM		 2205
2206 if (!(ah->ah_flags & AH_UNPLUGGED))
2207 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2208
f1dc5600 2209 return status;
f078f209 2210}
7322fd19 2211EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2212
f1dc5600
S		 2213/*******************/
2214/* Beacon Handling */
2215/*******************/
2216
cbe61d8a 2217void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2218{
f078f209
LR		 2219 int flags = 0;
2220
7d0d0df0
S		 2221 ENABLE_REGWRITE_BUFFER(ah);
2222
2660b81a 2223 switch (ah->opmode) {
d97809db 2224 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2225 REG_SET_BIT(ah, AR_TXCFG,
2226 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2227 case NL80211_IFTYPE_MESH_POINT:
d97809db 2228 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2229 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2230 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2231 TU_TO_USEC(ah->config.dma_beacon_response_time));
2232 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2233 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2234 flags |=
2235 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2236 break;
d97809db 2237 default:
d2182b69
JP		 2238 ath_dbg(ath9k_hw_common(ah), BEACON,
2239 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2240 return;
2241 break;
f078f209
LR		 2242 }
2243
dd347f2f
FF		 2244 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2245 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2246 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2247
7d0d0df0 2248 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2249
f078f209
LR		 2250 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2251}
7322fd19 2252EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2253
cbe61d8a 2254void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2255 const struct ath9k_beacon_state *bs)
f078f209
LR		 2256{
2257 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2258 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2259 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2260
7d0d0df0
S		 2261 ENABLE_REGWRITE_BUFFER(ah);
2262
4ed15762
FF		 2263 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2264 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2265 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2266
7d0d0df0 2267 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2268
f078f209
LR		 2269 REG_RMW_FIELD(ah, AR_RSSI_THR,
2270 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2271
f29f5c08 2272 beaconintval = bs->bs_intval;
f078f209
LR		 2273
2274 if (bs->bs_sleepduration > beaconintval)
2275 beaconintval = bs->bs_sleepduration;
2276
2277 dtimperiod = bs->bs_dtimperiod;
2278 if (bs->bs_sleepduration > dtimperiod)
2279 dtimperiod = bs->bs_sleepduration;
2280
2281 if (beaconintval == dtimperiod)
2282 nextTbtt = bs->bs_nextdtim;
2283 else
2284 nextTbtt = bs->bs_nexttbtt;
2285
d2182b69
JP		 2286 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2287 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2288 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2289 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2290
7d0d0df0
S		 2291 ENABLE_REGWRITE_BUFFER(ah);
2292
4ed15762
FF		 2293 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2294 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2295
f1dc5600
S		 2296 REG_WRITE(ah, AR_SLEEP1,
2297 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2298 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2299
f1dc5600
S		 2300 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2301 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2302 else
2303 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2304
f1dc5600
S		 2305 REG_WRITE(ah, AR_SLEEP2,
2306 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2307
4ed15762
FF		 2308 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2309 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2310
7d0d0df0 2311 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2312
f1dc5600
S		 2313 REG_SET_BIT(ah, AR_TIMER_MODE,
2314 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2315 AR_DTIM_TIMER_EN);
f078f209 2316
4af9cf4f
S		 2317 /* TSF Out of Range Threshold */
2318 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2319}
7322fd19 2320EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2321
f1dc5600
S		 2322/*******************/
2323/* HW Capabilities */
2324/*******************/
2325
6054069a
FF		 2326static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2327{
2328 eeprom_chainmask &= chip_chainmask;
2329 if (eeprom_chainmask)
2330 return eeprom_chainmask;
2331 else
2332 return chip_chainmask;
2333}
2334
9a66af33
ZK		 2335/**
2336 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2337 * @ah: the atheros hardware data structure
2338 *
2339 * We enable DFS support upstream on chipsets which have passed a series
2340 * of tests. The testing requirements are going to be documented. Desired
2341 * test requirements are documented at:
2342 *
2343 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2344 *
2345 * Once a new chipset gets properly tested an individual commit can be used
2346 * to document the testing for DFS for that chipset.
2347 */
2348static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2349{
2350
2351 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2352 /* for temporary testing DFS with 9280 */
2353 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2354 /* AR9580 will likely be our first target to get testing on */
2355 case AR_SREV_VERSION_9580:
73e4937d 2356 return true;
9a66af33
ZK		 2357 default:
2358 return false;
2359 }
2360}
2361
a9a29ce6 2362int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2363{
2660b81a 2364 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2365 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2366 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2367 unsigned int chip_chainmask;
608b88cb 2368
0ff2b5c0 2369 u16 eeval;
47c80de6 2370 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2371
f74df6fb 2372 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2373 regulatory->current_rd = eeval;
f078f209 2374
2660b81a 2375 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2376 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2377 if (regulatory->current_rd == 0x64 ||
2378 regulatory->current_rd == 0x65)
2379 regulatory->current_rd += 5;
2380 else if (regulatory->current_rd == 0x41)
2381 regulatory->current_rd = 0x43;
d2182b69
JP		 2382 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2383 regulatory->current_rd);
f1dc5600 2384 }
f078f209 2385
f74df6fb 2386 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2387 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2388 ath_err(common,
2389 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2390 return -EINVAL;
2391 }
2392
d4659912
FF		 2393 if (eeval & AR5416_OPFLAGS_11A)
2394 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2395
d4659912
FF		 2396 if (eeval & AR5416_OPFLAGS_11G)
2397 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2398
e41db61d
SM		 2399 if (AR_SREV_9485(ah) ||
2400 AR_SREV_9285(ah) ||
2401 AR_SREV_9330(ah) ||
2402 AR_SREV_9565(ah))
6054069a 2403 chip_chainmask = 1;
ba5736a5
MSS		 2404 else if (AR_SREV_9462(ah))
2405 chip_chainmask = 3;
6054069a
FF		 2406 else if (!AR_SREV_9280_20_OR_LATER(ah))
2407 chip_chainmask = 7;
2408 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2409 chip_chainmask = 3;
2410 else
2411 chip_chainmask = 7;
2412
f74df6fb 2413 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2414 /*
2415 * For AR9271 we will temporarilly uses the rx chainmax as read from
2416 * the EEPROM.
2417 */
8147f5de 2418 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2419 !(eeval & AR5416_OPFLAGS_11A) &&
2420 !(AR_SREV_9271(ah)))
2421 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2422 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2423 else if (AR_SREV_9100(ah))
2424 pCap->rx_chainmask = 0x7;
8147f5de 2425 else
d7e7d229 2426 /* Use rx_chainmask from EEPROM. */
8147f5de 2427 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2428
6054069a
FF		 2429 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2430 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2431 ah->txchainmask = pCap->tx_chainmask;
2432 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2433
7a37081e 2434 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2435
02d2ebb2
FF		 2436 /* enable key search for every frame in an aggregate */
2437 if (AR_SREV_9300_20_OR_LATER(ah))
2438 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2439
ce2220d1
BR		 2440 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2441
0db156e9 2442 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2443 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2444 else
2445 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2446
5b5fa355
S		 2447 if (AR_SREV_9271(ah))
2448 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2449 else if (AR_DEVID_7010(ah))
2450 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2451 else if (AR_SREV_9300_20_OR_LATER(ah))
2452 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2453 else if (AR_SREV_9287_11_OR_LATER(ah))
2454 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2455 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2456 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2457 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2458 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2459 else
2460 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2461
1b2538b2 2462 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2463 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2464 else
f1dc5600 2465 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2466
74e13060 2467#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2468 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2469 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2470 ah->rfkill_gpio =
2471 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2472 ah->rfkill_polarity =
2473 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2474
2475 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2476 }
f1dc5600 2477#endif
d5d1154f 2478 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2479 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2480 else
2481 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2482
e7594072 2483 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2484 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2485 else
2486 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2487
ceb26445 2488 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2489 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
a4a2954f 2490 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2491 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2492
ceb26445
VT		 2493 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2494 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2495 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2496 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2497 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2498 } else {
2499 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2500 if (AR_SREV_9280_20(ah))
6b42e8d0 2501 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2502 }
1adf02ff 2503
6c84ce08
VT		 2504 if (AR_SREV_9300_20_OR_LATER(ah))
2505 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2506
6ee63f55
SB		 2507 if (AR_SREV_9300_20_OR_LATER(ah))
2508 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2509
a42acef0 2510 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2511 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2512
f85c3371 2513 if (AR_SREV_9285(ah)) {
754dc536
VT		 2514 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2515 ant_div_ctl1 =
2516 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2517 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2518 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2519 ath_info(common, "Enable LNA combining\n");
2520 }
754dc536 2521 }
f85c3371
SM		 2522 }
2523
ea066d5a
MSS		 2524 if (AR_SREV_9300_20_OR_LATER(ah)) {
2525 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2526 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2527 }
2528
06236e53 2529 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2530 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2531 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2532 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2533 ath_info(common, "Enable LNA combining\n");
2534 }
21d2c63a 2535 }
754dc536 2536
9a66af33
ZK		 2537 if (ath9k_hw_dfs_tested(ah))
2538 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2539
47c80de6
VT		 2540 tx_chainmask = pCap->tx_chainmask;
2541 rx_chainmask = pCap->rx_chainmask;
2542 while (tx_chainmask || rx_chainmask) {
2543 if (tx_chainmask & BIT(0))
2544 pCap->max_txchains++;
2545 if (rx_chainmask & BIT(0))
2546 pCap->max_rxchains++;
2547
2548 tx_chainmask >>= 1;
2549 rx_chainmask >>= 1;
2550 }
2551
a4a2954f 2552 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2553 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2554 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2555
2b5e54e2 2556 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2557 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2558 }
2559
846e438f
SM		 2560 if (AR_SREV_9462(ah))
2561 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
d687809b 2562
0f21ee8d
SM		 2563 if (AR_SREV_9300_20_OR_LATER(ah) &&
2564 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2565 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2566
81dc75b5
SM		 2567 /*
2568 * Fast channel change across bands is available
2569 * only for AR9462 and AR9565.
2570 */
2571 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2572 pCap->hw_caps |= ATH9K_HW_CAP_FCC_BAND_SWITCH;
2573
a9a29ce6 2574 return 0;
f078f209
LR		 2575}
2576
f1dc5600
S		 2577/****************************/
2578/* GPIO / RFKILL / Antennae */
2579/****************************/
f078f209 2580
cbe61d8a 2581static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2582 u32 gpio, u32 type)
2583{
2584 int addr;
2585 u32 gpio_shift, tmp;
f078f209 2586
f1dc5600
S		 2587 if (gpio > 11)
2588 addr = AR_GPIO_OUTPUT_MUX3;
2589 else if (gpio > 5)
2590 addr = AR_GPIO_OUTPUT_MUX2;
2591 else
2592 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2593
f1dc5600 2594 gpio_shift = (gpio % 6) * 5;
f078f209 2595
f1dc5600
S		 2596 if (AR_SREV_9280_20_OR_LATER(ah)
2597 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2598 REG_RMW(ah, addr, (type << gpio_shift),
2599 (0x1f << gpio_shift));
f078f209 2600 } else {
f1dc5600
S		 2601 tmp = REG_READ(ah, addr);
2602 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2603 tmp &= ~(0x1f << gpio_shift);
2604 tmp |= (type << gpio_shift);
2605 REG_WRITE(ah, addr, tmp);
f078f209 2606 }
f078f209
LR		 2607}
2608
cbe61d8a 2609void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2610{
f1dc5600 2611 u32 gpio_shift;
f078f209 2612
9680e8a3 2613 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2614
88c1f4f6
S		 2615 if (AR_DEVID_7010(ah)) {
2616 gpio_shift = gpio;
2617 REG_RMW(ah, AR7010_GPIO_OE,
2618 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2619 (AR7010_GPIO_OE_MASK << gpio_shift));
2620 return;
2621 }
f078f209 2622
88c1f4f6 2623 gpio_shift = gpio << 1;
f1dc5600
S		 2624 REG_RMW(ah,
2625 AR_GPIO_OE_OUT,
2626 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2627 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2628}
7322fd19 2629EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2630
cbe61d8a 2631u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2632{
cb33c412
SB		 2633#define MS_REG_READ(x, y) \
2634 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2635
2660b81a 2636 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2637 return 0xffffffff;
f078f209 2638
88c1f4f6
S		 2639 if (AR_DEVID_7010(ah)) {
2640 u32 val;
2641 val = REG_READ(ah, AR7010_GPIO_IN);
2642 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2643 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2644 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2645 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2646 else if (AR_SREV_9271(ah))
5b5fa355 2647 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2648 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2649 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2650 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2651 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2652 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2653 return MS_REG_READ(AR928X, gpio) != 0;
2654 else
2655 return MS_REG_READ(AR, gpio) != 0;
f078f209 2656}
7322fd19 2657EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2658
cbe61d8a 2659void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2660 u32 ah_signal_type)
f078f209 2661{
f1dc5600 2662 u32 gpio_shift;
f078f209 2663
88c1f4f6
S		 2664 if (AR_DEVID_7010(ah)) {
2665 gpio_shift = gpio;
2666 REG_RMW(ah, AR7010_GPIO_OE,
2667 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2668 (AR7010_GPIO_OE_MASK << gpio_shift));
2669 return;
2670 }
f078f209 2671
88c1f4f6 2672 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2673 gpio_shift = 2 * gpio;
f1dc5600
S		 2674 REG_RMW(ah,
2675 AR_GPIO_OE_OUT,
2676 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2677 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2678}
7322fd19 2679EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2680
cbe61d8a 2681void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2682{
88c1f4f6
S		 2683 if (AR_DEVID_7010(ah)) {
2684 val = val ? 0 : 1;
2685 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2686 AR_GPIO_BIT(gpio));
2687 return;
2688 }
2689
5b5fa355
S		 2690 if (AR_SREV_9271(ah))
2691 val = ~val;
2692
f1dc5600
S		 2693 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2694 AR_GPIO_BIT(gpio));
f078f209 2695}
7322fd19 2696EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2697
cbe61d8a 2698void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2699{
f1dc5600 2700 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2701}
7322fd19 2702EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2703
f1dc5600
S		 2704/*********************/
2705/* General Operation */
2706/*********************/
2707
cbe61d8a 2708u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2709{
f1dc5600
S		 2710 u32 bits = REG_READ(ah, AR_RX_FILTER);
2711 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2712
f1dc5600
S		 2713 if (phybits & AR_PHY_ERR_RADAR)
2714 bits |= ATH9K_RX_FILTER_PHYRADAR;
2715 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2716 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2717
f1dc5600 2718 return bits;
f078f209 2719}
7322fd19 2720EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2721
cbe61d8a 2722void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2723{
f1dc5600 2724 u32 phybits;
f078f209 2725
7d0d0df0
S		 2726 ENABLE_REGWRITE_BUFFER(ah);
2727
a4a2954f 2728 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2577c6e8
SB		 2729 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2730
7ea310be
S		 2731 REG_WRITE(ah, AR_RX_FILTER, bits);
2732
f1dc5600
S		 2733 phybits = 0;
2734 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2735 phybits |= AR_PHY_ERR_RADAR;
2736 if (bits & ATH9K_RX_FILTER_PHYERR)
2737 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2738 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2739
f1dc5600 2740 if (phybits)
ca7a4deb 2741 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2742 else
ca7a4deb 2743 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2744
2745 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2746}
7322fd19 2747EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2748
cbe61d8a 2749bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2750{
99922a45
RM		 2751 if (ath9k_hw_mci_is_enabled(ah))
2752 ar9003_mci_bt_gain_ctrl(ah);
2753
63a75b91
SB		 2754 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2755 return false;
2756
2757 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2758 ah->htc_reset_init = true;
63a75b91 2759 return true;
f1dc5600 2760}
7322fd19 2761EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2762
cbe61d8a 2763bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2764{
9ecdef4b 2765 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2766 return false;
f078f209 2767
63a75b91
SB		 2768 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2769 return false;
2770
2771 ath9k_hw_init_pll(ah, NULL);
2772 return true;
f078f209 2773}
7322fd19 2774EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2775
ca2c68cc
FF		 2776static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2777{
2778 enum eeprom_param gain_param;
2779
2780 if (IS_CHAN_2GHZ(chan))
2781 gain_param = EEP_ANTENNA_GAIN_2G;
2782 else
2783 gain_param = EEP_ANTENNA_GAIN_5G;
2784
2785 return ah->eep_ops->get_eeprom(ah, gain_param);
2786}
2787
64ea57d0
GJ		 2788void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2789 bool test)
ca2c68cc
FF		 2790{
2791 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2792 struct ieee80211_channel *channel;
2793 int chan_pwr, new_pwr, max_gain;
2794 int ant_gain, ant_reduction = 0;
2795
2796 if (!chan)
2797 return;
2798
2799 channel = chan->chan;
2800 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2801 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2802 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2803
2804 ant_gain = get_antenna_gain(ah, chan);
2805 if (ant_gain > max_gain)
2806 ant_reduction = ant_gain - max_gain;
2807
2808 ah->eep_ops->set_txpower(ah, chan,
2809 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2810 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2811}
2812
de40f316 2813void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2814{
ca2c68cc 2815 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2816 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2817 struct ieee80211_channel *channel = chan->chan;
9c204b46 2818
48ef5c42 2819 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2820 if (test)
ca2c68cc 2821 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2822
64ea57d0 2823 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2824
ca2c68cc
FF		 2825 if (test)
2826 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2827}
7322fd19 2828EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2829
cbe61d8a 2830void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2831{
2660b81a 2832 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2833}
7322fd19 2834EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2835
cbe61d8a 2836void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2837{
f1dc5600
S		 2838 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2839 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2840}
7322fd19 2841EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2842
f2b2143e 2843void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2844{
1510718d
LR		 2845 struct ath_common *common = ath9k_hw_common(ah);
2846
2847 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2848 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2849 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2850}
7322fd19 2851EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2852
1c0fc65e
BP		 2853#define ATH9K_MAX_TSF_READ 10
2854
cbe61d8a 2855u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2856{
1c0fc65e
BP		 2857 u32 tsf_lower, tsf_upper1, tsf_upper2;
2858 int i;
2859
2860 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2861 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2862 tsf_lower = REG_READ(ah, AR_TSF_L32);
2863 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2864 if (tsf_upper2 == tsf_upper1)
2865 break;
2866 tsf_upper1 = tsf_upper2;
2867 }
f078f209 2868
1c0fc65e 2869 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2870
1c0fc65e 2871 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2872}
7322fd19 2873EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2874
cbe61d8a 2875void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2876{
27abe060 2877 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2878 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2879}
7322fd19 2880EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2881
cbe61d8a 2882void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2883{
f9b604f6
GJ		 2884 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2885 AH_TSF_WRITE_TIMEOUT))
d2182b69 2886 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2887 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2888
f1dc5600
S		 2889 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2890}
7322fd19 2891EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2892
60ca9f87 2893void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 2894{
60ca9f87 2895 if (set)
2660b81a 2896 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2897 else
2660b81a 2898 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2899}
7322fd19 2900EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2901
e4744ec7 2902void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 2903{
2904 u32 macmode;
2905
e4744ec7 2906 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2907 macmode = AR_2040_JOINED_RX_CLEAR;
2908 else
2909 macmode = 0;
f078f209 2910
f1dc5600 2911 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2912}
ff155a45
VT		 2913
2914/* HW Generic timers configuration */
2915
2916static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2917{
2918 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2919 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2920 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2921 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2922 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2923 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2924 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2925 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2926 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2927 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2928 AR_NDP2_TIMER_MODE, 0x0002},
2929 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2930 AR_NDP2_TIMER_MODE, 0x0004},
2931 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2932 AR_NDP2_TIMER_MODE, 0x0008},
2933 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2934 AR_NDP2_TIMER_MODE, 0x0010},
2935 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2936 AR_NDP2_TIMER_MODE, 0x0020},
2937 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2938 AR_NDP2_TIMER_MODE, 0x0040},
2939 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2940 AR_NDP2_TIMER_MODE, 0x0080}
2941};
2942
2943/* HW generic timer primitives */
2944
dd347f2f 2945u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2946{
2947 return REG_READ(ah, AR_TSF_L32);
2948}
dd347f2f 2949EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2950
2951struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2952 void (*trigger)(void *),
2953 void (*overflow)(void *),
2954 void *arg,
2955 u8 timer_index)
2956{
2957 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2958 struct ath_gen_timer *timer;
2959
c67ce339
FF		 2960 if ((timer_index < AR_FIRST_NDP_TIMER) ||
2961 (timer_index >= ATH_MAX_GEN_TIMER))
2962 return NULL;
2963
ff155a45 2964 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 2965 if (timer == NULL)
ff155a45 2966 return NULL;
ff155a45
VT		 2967
2968 /* allocate a hardware generic timer slot */
2969 timer_table->timers[timer_index] = timer;
2970 timer->index = timer_index;
2971 timer->trigger = trigger;
2972 timer->overflow = overflow;
2973 timer->arg = arg;
2974
2975 return timer;
2976}
7322fd19 2977EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2978
cd9bf689
LR		 2979void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2980 struct ath_gen_timer *timer,
c67ce339 2981 u32 timer_next,
cd9bf689 2982 u32 timer_period)
ff155a45
VT		 2983{
2984 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 2985 u32 mask = 0;
788f6875 2986
c67ce339 2987 timer_table->timer_mask |= BIT(timer->index);
ff155a45 2988
ff155a45
VT		 2989 /*
2990 * Program generic timer registers
2991 */
2992 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2993 timer_next);
2994 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2995 timer_period);
2996 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2997 gen_tmr_configuration[timer->index].mode_mask);
2998
a4a2954f 2999 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 3000 /*
423e38e8 3001 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3002 * to use. But we still follow the old rule, 0 - 7 use tsf and
3003 * 8 - 15 use tsf2.
3004 */
3005 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3006 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3007 (1 << timer->index));
3008 else
3009 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3010 (1 << timer->index));
3011 }
3012
c67ce339
FF		 3013 if (timer->trigger)
3014 mask |= SM(AR_GENTMR_BIT(timer->index),
3015 AR_IMR_S5_GENTIMER_TRIG);
3016 if (timer->overflow)
3017 mask |= SM(AR_GENTMR_BIT(timer->index),
3018 AR_IMR_S5_GENTIMER_THRESH);
3019
3020 REG_SET_BIT(ah, AR_IMR_S5, mask);
3021
3022 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3023 ah->imask |= ATH9K_INT_GENTIMER;
3024 ath9k_hw_set_interrupts(ah);
3025 }
ff155a45 3026}
7322fd19 3027EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3028
cd9bf689 3029void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3030{
3031 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3032
ff155a45
VT		 3033 /* Clear generic timer enable bits. */
3034 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3035 gen_tmr_configuration[timer->index].mode_mask);
3036
b7f59766
SM		 3037 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3038 /*
3039 * Need to switch back to TSF if it was using TSF2.
3040 */
3041 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3042 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3043 (1 << timer->index));
3044 }
3045 }
3046
ff155a45
VT		 3047 /* Disable both trigger and thresh interrupt masks */
3048 REG_CLR_BIT(ah, AR_IMR_S5,
3049 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3050 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3051
c67ce339
FF		 3052 timer_table->timer_mask &= ~BIT(timer->index);
3053
3054 if (timer_table->timer_mask == 0) {
3055 ah->imask &= ~ATH9K_INT_GENTIMER;
3056 ath9k_hw_set_interrupts(ah);
3057 }
ff155a45 3058}
7322fd19 3059EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3060
3061void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3062{
3063 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3064
3065 /* free the hardware generic timer slot */
3066 timer_table->timers[timer->index] = NULL;
3067 kfree(timer);
3068}
7322fd19 3069EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3070
3071/*
3072 * Generic Timer Interrupts handling
3073 */
3074void ath_gen_timer_isr(struct ath_hw *ah)
3075{
3076 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3077 struct ath_gen_timer *timer;
c67ce339
FF		 3078 unsigned long trigger_mask, thresh_mask;
3079 unsigned int index;
ff155a45
VT		 3080
3081 /* get hardware generic timer interrupt status */
3082 trigger_mask = ah->intr_gen_timer_trigger;
3083 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 3084 trigger_mask &= timer_table->timer_mask;
3085 thresh_mask &= timer_table->timer_mask;
ff155a45 3086
c67ce339 3087 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3088 timer = timer_table->timers[index];
c67ce339
FF		 3089 if (!timer)
3090 continue;
3091 if (!timer->overflow)
3092 continue;
a6a172b2
FF		 3093
3094 trigger_mask &= ~BIT(index);
ff155a45
VT		 3095 timer->overflow(timer->arg);
3096 }
3097
c67ce339 3098 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3099 timer = timer_table->timers[index];
c67ce339
FF		 3100 if (!timer)
3101 continue;
3102 if (!timer->trigger)
3103 continue;
ff155a45
VT		 3104 timer->trigger(timer->arg);
3105 }
3106}
7322fd19 3107EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3108
05020d23
S		 3109/********/
3110/* HTC */
3111/********/
3112
2da4f01a
LR		 3113static struct {
3114 u32 version;
3115 const char * name;
3116} ath_mac_bb_names[] = {
3117 /* Devices with external radios */
3118 { AR_SREV_VERSION_5416_PCI, "5416" },
3119 { AR_SREV_VERSION_5416_PCIE, "5418" },
3120 { AR_SREV_VERSION_9100, "9100" },
3121 { AR_SREV_VERSION_9160, "9160" },
3122 /* Single-chip solutions */
3123 { AR_SREV_VERSION_9280, "9280" },
3124 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3125 { AR_SREV_VERSION_9287, "9287" },
3126 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3127 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3128 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3129 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3130 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3131 { AR_SREV_VERSION_9462, "9462" },
485124cb 3132 { AR_SREV_VERSION_9550, "9550" },
77fac465 3133 { AR_SREV_VERSION_9565, "9565" },
2da4f01a
LR		 3134};
3135
3136/* For devices with external radios */
3137static struct {
3138 u16 version;
3139 const char * name;
3140} ath_rf_names[] = {
3141 { 0, "5133" },
3142 { AR_RAD5133_SREV_MAJOR, "5133" },
3143 { AR_RAD5122_SREV_MAJOR, "5122" },
3144 { AR_RAD2133_SREV_MAJOR, "2133" },
3145 { AR_RAD2122_SREV_MAJOR, "2122" }
3146};
3147
3148/*
3149 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3150 */
f934c4d9 3151static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3152{
3153 int i;
3154
3155 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3156 if (ath_mac_bb_names[i].version == mac_bb_version) {
3157 return ath_mac_bb_names[i].name;
3158 }
3159 }
3160
3161 return "????";
3162}
2da4f01a
LR		 3163
3164/*
3165 * Return the RF name. "????" is returned if the RF is unknown.
3166 * Used for devices with external radios.
3167 */
f934c4d9 3168static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3169{
3170 int i;
3171
3172 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3173 if (ath_rf_names[i].version == rf_version) {
3174 return ath_rf_names[i].name;
3175 }
3176 }
3177
3178 return "????";
3179}
f934c4d9
LR		 3180
3181void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3182{
3183 int used;
3184
3185 /* chipsets >= AR9280 are single-chip */
7a37081e 3186 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3187 used = scnprintf(hw_name, len,
3188 "Atheros AR%s Rev:%x",
3189 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3190 ah->hw_version.macRev);
f934c4d9
LR		 3191 }
3192 else {
5e88ba62
ZK		 3193 used = scnprintf(hw_name, len,
3194 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3195 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3196 ah->hw_version.macRev,
3197 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3198 & AR_RADIO_SREV_MAJOR)),
3199 ah->hw_version.phyRev);
f934c4d9
LR		 3200 }
3201
3202 hw_name[used] = '\0';
3203}
3204EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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