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atheros: add ieee80211_hw to ath_common
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
af03abec 20#include "hw.h"
394cf0a1 21#include "ath9k.h"
f078f209
LR		 22#include "initvals.h"
23
4febf7b8
LR		 24#define ATH9K_CLOCK_RATE_CCK 22
25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 27
cbe61d8a
S		 28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
f1dc5600 30 enum ath9k_ht_macmode macmode);
cbe61d8a 31static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072 32 struct ar5416_eeprom_def *pEepData,
f1dc5600 33 u32 reg, u32 value);
cbe61d8a
S		 34static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
f078f209 36
f1dc5600
S		 37/********************/
38/* Helper Functions */
39/********************/
f078f209 40
cbe61d8a 41static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
f1dc5600 42{
b002a4a9 43 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 44
2660b81a 45 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 46 return clks / ATH9K_CLOCK_RATE_CCK;
47 if (conf->channel->band == IEEE80211_BAND_2GHZ)
48 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
cbe61d8a 49
4febf7b8 50 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 51}
f078f209 52
cbe61d8a 53static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
f1dc5600 54{
b002a4a9 55 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 56
4febf7b8 57 if (conf_is_ht40(conf))
f1dc5600
S		 58 return ath9k_hw_mac_usec(ah, clks) / 2;
59 else
60 return ath9k_hw_mac_usec(ah, clks);
61}
f078f209 62
cbe61d8a 63static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 64{
b002a4a9 65 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 66
2660b81a 67 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 68 return usecs *ATH9K_CLOCK_RATE_CCK;
69 if (conf->channel->band == IEEE80211_BAND_2GHZ)
70 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
71 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 72}
73
cbe61d8a 74static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 75{
b002a4a9 76 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 77
4febf7b8 78 if (conf_is_ht40(conf))
f1dc5600
S		 79 return ath9k_hw_mac_clks(ah, usecs) * 2;
80 else
81 return ath9k_hw_mac_clks(ah, usecs);
82}
f078f209 83
0caa7b14 84bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 85{
86 int i;
87
0caa7b14
S		 88 BUG_ON(timeout < AH_TIME_QUANTUM);
89
90 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 91 if ((REG_READ(ah, reg) & mask) == val)
92 return true;
93
94 udelay(AH_TIME_QUANTUM);
95 }
04bd4638 96
4d6b228d 97 DPRINTF(ah, ATH_DBG_ANY,
0caa7b14
S		 98 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
99 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 100
f1dc5600 101 return false;
f078f209
LR		 102}
103
104u32 ath9k_hw_reverse_bits(u32 val, u32 n)
105{
106 u32 retval;
107 int i;
108
109 for (i = 0, retval = 0; i < n; i++) {
110 retval = (retval << 1) | (val & 1);
111 val >>= 1;
112 }
113 return retval;
114}
115
cbe61d8a 116bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 117 u16 flags, u16 *low,
118 u16 *high)
f078f209 119{
2660b81a 120 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 121
f1dc5600
S		 122 if (flags & CHANNEL_5GHZ) {
123 *low = pCap->low_5ghz_chan;
124 *high = pCap->high_5ghz_chan;
125 return true;
f078f209 126 }
f1dc5600
S		 127 if ((flags & CHANNEL_2GHZ)) {
128 *low = pCap->low_2ghz_chan;
129 *high = pCap->high_2ghz_chan;
130 return true;
131 }
132 return false;
f078f209
LR		 133}
134
cbe61d8a 135u16 ath9k_hw_computetxtime(struct ath_hw *ah,
4f0fc7c3 136 const struct ath_rate_table *rates,
f1dc5600
S		 137 u32 frameLen, u16 rateix,
138 bool shortPreamble)
f078f209 139{
f1dc5600
S		 140 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
141 u32 kbps;
f078f209 142
e63835b0 143 kbps = rates->info[rateix].ratekbps;
f078f209 144
f1dc5600
S		 145 if (kbps == 0)
146 return 0;
f078f209 147
f1dc5600 148 switch (rates->info[rateix].phy) {
46d14a58 149 case WLAN_RC_PHY_CCK:
f1dc5600 150 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
e63835b0 151 if (shortPreamble && rates->info[rateix].short_preamble)
f1dc5600
S		 152 phyTime >>= 1;
153 numBits = frameLen << 3;
154 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
155 break;
46d14a58 156 case WLAN_RC_PHY_OFDM:
2660b81a 157 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 158 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
159 numBits = OFDM_PLCP_BITS + (frameLen << 3);
160 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
161 txTime = OFDM_SIFS_TIME_QUARTER
162 + OFDM_PREAMBLE_TIME_QUARTER
163 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 164 } else if (ah->curchan &&
165 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 166 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
167 numBits = OFDM_PLCP_BITS + (frameLen << 3);
168 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
169 txTime = OFDM_SIFS_TIME_HALF +
170 OFDM_PREAMBLE_TIME_HALF
171 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
172 } else {
173 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
174 numBits = OFDM_PLCP_BITS + (frameLen << 3);
175 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
176 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
177 + (numSymbols * OFDM_SYMBOL_TIME);
178 }
179 break;
180 default:
4d6b228d 181 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 182 "Unknown phy %u (rate ix %u)\n",
f1dc5600
S		 183 rates->info[rateix].phy, rateix);
184 txTime = 0;
185 break;
186 }
f078f209 187
f1dc5600
S		 188 return txTime;
189}
f078f209 190
cbe61d8a 191void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 192 struct ath9k_channel *chan,
193 struct chan_centers *centers)
f078f209 194{
f1dc5600 195 int8_t extoff;
f078f209 196
f1dc5600
S		 197 if (!IS_CHAN_HT40(chan)) {
198 centers->ctl_center = centers->ext_center =
199 centers->synth_center = chan->channel;
200 return;
f078f209 201 }
f078f209 202
f1dc5600
S		 203 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
204 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
205 centers->synth_center =
206 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
207 extoff = 1;
208 } else {
209 centers->synth_center =
210 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
211 extoff = -1;
212 }
f078f209 213
f1dc5600
S		 214 centers->ctl_center =
215 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
216 centers->ext_center =
217 centers->synth_center + (extoff *
2660b81a 218 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
f1dc5600 219 HT40_CHANNEL_CENTER_SHIFT : 15));
f078f209
LR		 220}
221
f1dc5600
S		 222/******************/
223/* Chip Revisions */
224/******************/
225
cbe61d8a 226static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 227{
f1dc5600 228 u32 val;
f078f209 229
f1dc5600 230 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 231
f1dc5600
S		 232 if (val == 0xFF) {
233 val = REG_READ(ah, AR_SREV);
d535a42a
S		 234 ah->hw_version.macVersion =
235 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
236 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 237 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 238 } else {
239 if (!AR_SREV_9100(ah))
d535a42a 240 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 241
d535a42a 242 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 243
d535a42a 244 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 245 ah->is_pciexpress = true;
f1dc5600 246 }
f078f209
LR		 247}
248
cbe61d8a 249static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 250{
f1dc5600
S		 251 u32 val;
252 int i;
f078f209 253
f1dc5600 254 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 255
f1dc5600
S		 256 for (i = 0; i < 8; i++)
257 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
258 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
259 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 260
f1dc5600 261 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 262}
263
f1dc5600
S		 264/************************************/
265/* HW Attach, Detach, Init Routines */
266/************************************/
267
cbe61d8a 268static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 269{
feed029c 270 if (AR_SREV_9100(ah))
f1dc5600 271 return;
f078f209 272
f1dc5600
S		 273 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
274 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
275 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 282
f1dc5600 283 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 284}
285
cbe61d8a 286static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 287{
f1dc5600
S		 288 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
289 u32 regHold[2];
290 u32 patternData[4] = { 0x55555555,
291 0xaaaaaaaa,
292 0x66666666,
293 0x99999999 };
294 int i, j;
f078f209 295
f1dc5600
S		 296 for (i = 0; i < 2; i++) {
297 u32 addr = regAddr[i];
298 u32 wrData, rdData;
f078f209 299
f1dc5600
S		 300 regHold[i] = REG_READ(ah, addr);
301 for (j = 0; j < 0x100; j++) {
302 wrData = (j << 16) | j;
303 REG_WRITE(ah, addr, wrData);
304 rdData = REG_READ(ah, addr);
305 if (rdData != wrData) {
4d6b228d 306 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 307 "address test failed "
f1dc5600 308 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 309 addr, wrData, rdData);
f1dc5600
S		 310 return false;
311 }
312 }
313 for (j = 0; j < 4; j++) {
314 wrData = patternData[j];
315 REG_WRITE(ah, addr, wrData);
316 rdData = REG_READ(ah, addr);
317 if (wrData != rdData) {
4d6b228d 318 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 319 "address test failed "
f1dc5600 320 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 321 addr, wrData, rdData);
f1dc5600
S		 322 return false;
323 }
f078f209 324 }
f1dc5600 325 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 326 }
f1dc5600 327 udelay(100);
cbe61d8a 328
f078f209
LR		 329 return true;
330}
331
f1dc5600 332static const char *ath9k_hw_devname(u16 devid)
f078f209 333{
f1dc5600
S		 334 switch (devid) {
335 case AR5416_DEVID_PCI:
f1dc5600 336 return "Atheros 5416";
392dff83
BP		 337 case AR5416_DEVID_PCIE:
338 return "Atheros 5418";
f1dc5600
S		 339 case AR9160_DEVID_PCI:
340 return "Atheros 9160";
0c1aa495
GJ		 341 case AR5416_AR9100_DEVID:
342 return "Atheros 9100";
f1dc5600
S		 343 case AR9280_DEVID_PCI:
344 case AR9280_DEVID_PCIE:
345 return "Atheros 9280";
e7594072
SB		 346 case AR9285_DEVID_PCIE:
347 return "Atheros 9285";
ac88b6ec
VN		 348 case AR5416_DEVID_AR9287_PCI:
349 case AR5416_DEVID_AR9287_PCIE:
350 return "Atheros 9287";
f078f209
LR		 351 }
352
f1dc5600
S		 353 return NULL;
354}
f078f209 355
b8b0f377 356static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 357{
358 int i;
f078f209 359
2660b81a
S		 360 ah->config.dma_beacon_response_time = 2;
361 ah->config.sw_beacon_response_time = 10;
362 ah->config.additional_swba_backoff = 0;
363 ah->config.ack_6mb = 0x0;
364 ah->config.cwm_ignore_extcca = 0;
365 ah->config.pcie_powersave_enable = 0;
2660b81a 366 ah->config.pcie_clock_req = 0;
2660b81a
S		 367 ah->config.pcie_waen = 0;
368 ah->config.analog_shiftreg = 1;
369 ah->config.ht_enable = 1;
370 ah->config.ofdm_trig_low = 200;
371 ah->config.ofdm_trig_high = 500;
372 ah->config.cck_trig_high = 200;
373 ah->config.cck_trig_low = 100;
374 ah->config.enable_ani = 1;
1cf6873a 375 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
2660b81a 376 ah->config.antenna_switch_swap = 0;
f078f209 377
f1dc5600 378 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 379 ah->config.spurchans[i][0] = AR_NO_SPUR;
380 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 381 }
382
0ef1f168 383 ah->config.intr_mitigation = true;
6158425b
LR		 384
385 /*
386 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
387 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
388 * This means we use it for all AR5416 devices, and the few
389 * minor PCI AR9280 devices out there.
390 *
391 * Serialization is required because these devices do not handle
392 * well the case of two concurrent reads/writes due to the latency
393 * involved. During one read/write another read/write can be issued
394 * on another CPU while the previous read/write may still be working
395 * on our hardware, if we hit this case the hardware poops in a loop.
396 * We prevent this by serializing reads and writes.
397 *
398 * This issue is not present on PCI-Express devices or pre-AR5416
399 * devices (legacy, 802.11abg).
400 */
401 if (num_possible_cpus() > 1)
2d6a5e95 402 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 403}
404
50aca25b 405static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 406{
608b88cb
LR		 407 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
408
409 regulatory->country_code = CTRY_DEFAULT;
410 regulatory->power_limit = MAX_RATE_POWER;
411 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
412
d535a42a 413 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 414 ah->hw_version.subvendorid = 0;
f078f209
LR		 415
416 ah->ah_flags = 0;
8df5d1b7 417 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
d535a42a 418 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
f078f209
LR		 419 if (!AR_SREV_9100(ah))
420 ah->ah_flags = AH_USE_EEPROM;
421
2660b81a 422 ah->atim_window = 0;
2660b81a
S		 423 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
424 ah->beacon_interval = 100;
425 ah->enable_32kHz_clock = DONT_USE_32KHZ;
426 ah->slottime = (u32) -1;
427 ah->acktimeout = (u32) -1;
428 ah->ctstimeout = (u32) -1;
429 ah->globaltxtimeout = (u32) -1;
430
431 ah->gbeacon_rate = 0;
f078f209 432
cbdec975 433 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 434}
435
cbe61d8a 436static int ath9k_hw_rfattach(struct ath_hw *ah)
f078f209 437{
f1dc5600
S		 438 bool rfStatus = false;
439 int ecode = 0;
f078f209 440
f1dc5600
S		 441 rfStatus = ath9k_hw_init_rf(ah, &ecode);
442 if (!rfStatus) {
4d6b228d 443 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939 444 "RF setup failed, status: %u\n", ecode);
f1dc5600
S		 445 return ecode;
446 }
f078f209 447
f1dc5600 448 return 0;
f078f209
LR		 449}
450
cbe61d8a 451static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 452{
f1dc5600
S		 453 u32 val;
454
455 REG_WRITE(ah, AR_PHY(0), 0x00000007);
456
457 val = ath9k_hw_get_radiorev(ah);
458 switch (val & AR_RADIO_SREV_MAJOR) {
459 case 0:
460 val = AR_RAD5133_SREV_MAJOR;
461 break;
462 case AR_RAD5133_SREV_MAJOR:
463 case AR_RAD5122_SREV_MAJOR:
464 case AR_RAD2133_SREV_MAJOR:
465 case AR_RAD2122_SREV_MAJOR:
466 break;
f078f209 467 default:
4d6b228d 468 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939
S		 469 "Radio Chip Rev 0x%02X not supported\n",
470 val & AR_RADIO_SREV_MAJOR);
f1dc5600 471 return -EOPNOTSUPP;
f078f209 472 }
f078f209 473
d535a42a 474 ah->hw_version.analog5GhzRev = val;
f078f209 475
f1dc5600 476 return 0;
f078f209
LR		 477}
478
cbe61d8a 479static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 480{
1510718d 481 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 482 u32 sum;
483 int i;
484 u16 eeval;
f078f209
LR		 485
486 sum = 0;
487 for (i = 0; i < 3; i++) {
f74df6fb 488 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 489 sum += eeval;
1510718d
LR		 490 common->macaddr[2 * i] = eeval >> 8;
491 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 492 }
d8baa939 493 if (sum == 0 || sum == 0xffff * 3)
f078f209 494 return -EADDRNOTAVAIL;
f078f209
LR		 495
496 return 0;
497}
498
cbe61d8a 499static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 500{
501 u32 rxgain_type;
9f804202 502
f74df6fb
S		 503 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
504 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 505
506 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 507 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 508 ar9280Modes_backoff_13db_rxgain_9280_2,
509 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
510 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 511 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 512 ar9280Modes_backoff_23db_rxgain_9280_2,
513 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
514 else
2660b81a 515 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 516 ar9280Modes_original_rxgain_9280_2,
517 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 518 } else {
2660b81a 519 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 520 ar9280Modes_original_rxgain_9280_2,
521 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 522 }
9f804202
SB		 523}
524
cbe61d8a 525static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 526{
527 u32 txgain_type;
9f804202 528
f74df6fb
S		 529 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
530 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 531
532 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 533 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 534 ar9280Modes_high_power_tx_gain_9280_2,
535 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
536 else
2660b81a 537 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 538 ar9280Modes_original_tx_gain_9280_2,
539 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 540 } else {
2660b81a 541 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 542 ar9280Modes_original_tx_gain_9280_2,
543 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 544 }
9f804202
SB		 545}
546
f637cfd6 547static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 548{
f1dc5600 549 int ecode;
f078f209 550
d8baa939 551 if (!ath9k_hw_chip_test(ah))
f1dc5600 552 return -ENODEV;
f078f209 553
f1dc5600
S		 554 ecode = ath9k_hw_rf_claim(ah);
555 if (ecode != 0)
f078f209 556 return ecode;
f078f209 557
f637cfd6 558 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 559 if (ecode != 0)
560 return ecode;
7d01b221 561
4d6b228d 562 DPRINTF(ah, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
7d01b221
S		 563 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
564
f1dc5600
S		 565 ecode = ath9k_hw_rfattach(ah);
566 if (ecode != 0)
567 return ecode;
f078f209 568
f1dc5600
S		 569 if (!AR_SREV_9100(ah)) {
570 ath9k_hw_ani_setup(ah);
f637cfd6 571 ath9k_hw_ani_init(ah);
f078f209
LR		 572 }
573
f078f209
LR		 574 return 0;
575}
576
ee2bb460
LR		 577static bool ath9k_hw_devid_supported(u16 devid)
578{
579 switch (devid) {
580 case AR5416_DEVID_PCI:
581 case AR5416_DEVID_PCIE:
582 case AR5416_AR9100_DEVID:
583 case AR9160_DEVID_PCI:
584 case AR9280_DEVID_PCI:
585 case AR9280_DEVID_PCIE:
586 case AR9285_DEVID_PCIE:
587 case AR5416_DEVID_AR9287_PCI:
588 case AR5416_DEVID_AR9287_PCIE:
589 return true;
590 default:
591 break;
592 }
593 return false;
594}
595
f9d4a668
LR		 596static bool ath9k_hw_macversion_supported(u32 macversion)
597{
598 switch (macversion) {
599 case AR_SREV_VERSION_5416_PCI:
600 case AR_SREV_VERSION_5416_PCIE:
601 case AR_SREV_VERSION_9160:
602 case AR_SREV_VERSION_9100:
603 case AR_SREV_VERSION_9280:
604 case AR_SREV_VERSION_9285:
605 case AR_SREV_VERSION_9287:
606 return true;
d7e7d229
LR		 607 /* Not yet */
608 case AR_SREV_VERSION_9271:
f9d4a668
LR		 609 default:
610 break;
611 }
612 return false;
613}
614
aa4058ae 615static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
f078f209 616{
f1dc5600
S		 617 if (AR_SREV_9160_10_OR_LATER(ah)) {
618 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a
S		 619 ah->iq_caldata.calData = &iq_cal_single_sample;
620 ah->adcgain_caldata.calData =
f1dc5600 621 &adc_gain_cal_single_sample;
2660b81a 622 ah->adcdc_caldata.calData =
f1dc5600 623 &adc_dc_cal_single_sample;
2660b81a 624 ah->adcdc_calinitdata.calData =
f1dc5600
S		 625 &adc_init_dc_cal;
626 } else {
2660b81a
S		 627 ah->iq_caldata.calData = &iq_cal_multi_sample;
628 ah->adcgain_caldata.calData =
f1dc5600 629 &adc_gain_cal_multi_sample;
2660b81a 630 ah->adcdc_caldata.calData =
f1dc5600 631 &adc_dc_cal_multi_sample;
2660b81a 632 ah->adcdc_calinitdata.calData =
f1dc5600
S		 633 &adc_init_dc_cal;
634 }
2660b81a 635 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
f1dc5600 636 }
aa4058ae 637}
f078f209 638
aa4058ae
LR		 639static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
640{
d7e7d229
LR		 641 if (AR_SREV_9271(ah)) {
642 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
643 ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
644 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
645 ARRAY_SIZE(ar9271Common_9271_1_0), 2);
646 return;
647 }
648
ac88b6ec
VN		 649 if (AR_SREV_9287_11_OR_LATER(ah)) {
650 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
651 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
652 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
653 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
654 if (ah->config.pcie_clock_req)
655 INIT_INI_ARRAY(&ah->iniPcieSerdes,
656 ar9287PciePhy_clkreq_off_L1_9287_1_1,
657 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
658 else
659 INIT_INI_ARRAY(&ah->iniPcieSerdes,
660 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
661 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
662 2);
663 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
664 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
665 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
666 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
667 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
668
669 if (ah->config.pcie_clock_req)
670 INIT_INI_ARRAY(&ah->iniPcieSerdes,
671 ar9287PciePhy_clkreq_off_L1_9287_1_0,
672 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
673 else
674 INIT_INI_ARRAY(&ah->iniPcieSerdes,
675 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
676 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
677 2);
678 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
f078f209 679
4e845168 680
2660b81a 681 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
e7594072 682 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
2660b81a 683 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
e7594072
SB		 684 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
685
2660b81a
S		 686 if (ah->config.pcie_clock_req) {
687 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 688 ar9285PciePhy_clkreq_off_L1_9285_1_2,
689 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
690 } else {
2660b81a 691 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 692 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
693 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
694 2);
695 }
696 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
2660b81a 697 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
e7594072 698 ARRAY_SIZE(ar9285Modes_9285), 6);
2660b81a 699 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
e7594072
SB		 700 ARRAY_SIZE(ar9285Common_9285), 2);
701
2660b81a
S		 702 if (ah->config.pcie_clock_req) {
703 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 704 ar9285PciePhy_clkreq_off_L1_9285,
705 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
706 } else {
2660b81a 707 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 708 ar9285PciePhy_clkreq_always_on_L1_9285,
709 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
710 }
711 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2660b81a 712 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
f1dc5600 713 ARRAY_SIZE(ar9280Modes_9280_2), 6);
2660b81a 714 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
f1dc5600 715 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 716
2660b81a
S		 717 if (ah->config.pcie_clock_req) {
718 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 719 ar9280PciePhy_clkreq_off_L1_9280,
720 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
721 } else {
2660b81a 722 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 723 ar9280PciePhy_clkreq_always_on_L1_9280,
724 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
725 }
2660b81a 726 INIT_INI_ARRAY(&ah->iniModesAdditional,
f1dc5600
S		 727 ar9280Modes_fast_clock_9280_2,
728 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
729 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 730 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
f1dc5600 731 ARRAY_SIZE(ar9280Modes_9280), 6);
2660b81a 732 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
f1dc5600
S		 733 ARRAY_SIZE(ar9280Common_9280), 2);
734 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2660b81a 735 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
f1dc5600 736 ARRAY_SIZE(ar5416Modes_9160), 6);
2660b81a 737 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
f1dc5600 738 ARRAY_SIZE(ar5416Common_9160), 2);
2660b81a 739 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
f1dc5600 740 ARRAY_SIZE(ar5416Bank0_9160), 2);
2660b81a 741 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
f1dc5600 742 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
2660b81a 743 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
f1dc5600 744 ARRAY_SIZE(ar5416Bank1_9160), 2);
2660b81a 745 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
f1dc5600 746 ARRAY_SIZE(ar5416Bank2_9160), 2);
2660b81a 747 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
f1dc5600 748 ARRAY_SIZE(ar5416Bank3_9160), 3);
2660b81a 749 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
f1dc5600 750 ARRAY_SIZE(ar5416Bank6_9160), 3);
2660b81a 751 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
f1dc5600 752 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
2660b81a 753 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
f1dc5600
S		 754 ARRAY_SIZE(ar5416Bank7_9160), 2);
755 if (AR_SREV_9160_11(ah)) {
2660b81a 756 INIT_INI_ARRAY(&ah->iniAddac,
f1dc5600
S		 757 ar5416Addac_91601_1,
758 ARRAY_SIZE(ar5416Addac_91601_1), 2);
759 } else {
2660b81a 760 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
f1dc5600
S		 761 ARRAY_SIZE(ar5416Addac_9160), 2);
762 }
763 } else if (AR_SREV_9100_OR_LATER(ah)) {
2660b81a 764 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
f1dc5600 765 ARRAY_SIZE(ar5416Modes_9100), 6);
2660b81a 766 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
f1dc5600 767 ARRAY_SIZE(ar5416Common_9100), 2);
2660b81a 768 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
f1dc5600 769 ARRAY_SIZE(ar5416Bank0_9100), 2);
2660b81a 770 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
f1dc5600 771 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
2660b81a 772 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
f1dc5600 773 ARRAY_SIZE(ar5416Bank1_9100), 2);
2660b81a 774 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
f1dc5600 775 ARRAY_SIZE(ar5416Bank2_9100), 2);
2660b81a 776 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
f1dc5600 777 ARRAY_SIZE(ar5416Bank3_9100), 3);
2660b81a 778 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
f1dc5600 779 ARRAY_SIZE(ar5416Bank6_9100), 3);
2660b81a 780 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
f1dc5600 781 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
2660b81a 782 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
f1dc5600 783 ARRAY_SIZE(ar5416Bank7_9100), 2);
2660b81a 784 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
f1dc5600
S		 785 ARRAY_SIZE(ar5416Addac_9100), 2);
786 } else {
2660b81a 787 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
f1dc5600 788 ARRAY_SIZE(ar5416Modes), 6);
2660b81a 789 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
f1dc5600 790 ARRAY_SIZE(ar5416Common), 2);
2660b81a 791 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
f1dc5600 792 ARRAY_SIZE(ar5416Bank0), 2);
2660b81a 793 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
f1dc5600 794 ARRAY_SIZE(ar5416BB_RfGain), 3);
2660b81a 795 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
f1dc5600 796 ARRAY_SIZE(ar5416Bank1), 2);
2660b81a 797 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
f1dc5600 798 ARRAY_SIZE(ar5416Bank2), 2);
2660b81a 799 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
f1dc5600 800 ARRAY_SIZE(ar5416Bank3), 3);
2660b81a 801 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
f1dc5600 802 ARRAY_SIZE(ar5416Bank6), 3);
2660b81a 803 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
f1dc5600 804 ARRAY_SIZE(ar5416Bank6TPC), 3);
2660b81a 805 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
f1dc5600 806 ARRAY_SIZE(ar5416Bank7), 2);
2660b81a 807 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
f1dc5600 808 ARRAY_SIZE(ar5416Addac), 2);
f078f209 809 }
aa4058ae 810}
f078f209 811
aa4058ae
LR		 812static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
813{
b37fa870 814 if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec
VN		 815 INIT_INI_ARRAY(&ah->iniModesRxGain,
816 ar9287Modes_rx_gain_9287_1_1,
817 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
818 else if (AR_SREV_9287_10(ah))
819 INIT_INI_ARRAY(&ah->iniModesRxGain,
820 ar9287Modes_rx_gain_9287_1_0,
821 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
822 else if (AR_SREV_9280_20(ah))
823 ath9k_hw_init_rxgain_ini(ah);
824
b37fa870 825 if (AR_SREV_9287_11_OR_LATER(ah)) {
ac88b6ec
VN		 826 INIT_INI_ARRAY(&ah->iniModesTxGain,
827 ar9287Modes_tx_gain_9287_1_1,
828 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
829 } else if (AR_SREV_9287_10(ah)) {
830 INIT_INI_ARRAY(&ah->iniModesTxGain,
831 ar9287Modes_tx_gain_9287_1_0,
832 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
833 } else if (AR_SREV_9280_20(ah)) {
834 ath9k_hw_init_txgain_ini(ah);
835 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4e845168
SB		 836 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
837
838 /* txgain table */
839 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
840 INIT_INI_ARRAY(&ah->iniModesTxGain,
841 ar9285Modes_high_power_tx_gain_9285_1_2,
842 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
843 } else {
844 INIT_INI_ARRAY(&ah->iniModesTxGain,
845 ar9285Modes_original_tx_gain_9285_1_2,
846 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
847 }
848
849 }
aa4058ae 850}
4e845168 851
aa4058ae
LR		 852static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
853{
854 u32 i, j;
06d0f066
S		 855
856 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
857 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
858
859 /* EEPROM Fixup */
2660b81a
S		 860 for (i = 0; i < ah->iniModes.ia_rows; i++) {
861 u32 reg = INI_RA(&ah->iniModes, i, 0);
f078f209 862
2660b81a
S		 863 for (j = 1; j < ah->iniModes.ia_columns; j++) {
864 u32 val = INI_RA(&ah->iniModes, i, j);
f078f209 865
2660b81a 866 INI_RA(&ah->iniModes, i, j) =
e7594072 867 ath9k_hw_ini_fixup(ah,
2660b81a 868 &ah->eeprom.def,
f1dc5600
S		 869 reg, val);
870 }
f078f209 871 }
f1dc5600 872 }
aa4058ae
LR		 873}
874
f637cfd6 875int ath9k_hw_init(struct ath_hw *ah)
aa4058ae 876{
95fafca2 877 int r = 0;
aa4058ae 878
95fafca2
LR		 879 if (!ath9k_hw_devid_supported(ah->hw_version.devid))
880 return -EOPNOTSUPP;
aa4058ae
LR		 881
882 ath9k_hw_init_defaults(ah);
883 ath9k_hw_init_config(ah);
884
885 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
4d6b228d 886 DPRINTF(ah, ATH_DBG_FATAL, "Couldn't reset chip\n");
95fafca2 887 return -EIO;
aa4058ae
LR		 888 }
889
9ecdef4b 890 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
4d6b228d 891 DPRINTF(ah, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 892 return -EIO;
aa4058ae
LR		 893 }
894
895 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
896 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
897 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
898 ah->config.serialize_regmode =
899 SER_REG_MODE_ON;
900 } else {
901 ah->config.serialize_regmode =
902 SER_REG_MODE_OFF;
903 }
904 }
905
4d6b228d 906 DPRINTF(ah, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 907 ah->config.serialize_regmode);
908
909 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
4d6b228d 910 DPRINTF(ah, ATH_DBG_FATAL,
aa4058ae
LR		 911 "Mac Chip Rev 0x%02x.%x is not supported by "
912 "this driver\n", ah->hw_version.macVersion,
913 ah->hw_version.macRev);
95fafca2 914 return -EOPNOTSUPP;
aa4058ae
LR		 915 }
916
917 if (AR_SREV_9100(ah)) {
918 ah->iq_caldata.calData = &iq_cal_multi_sample;
919 ah->supp_cals = IQ_MISMATCH_CAL;
920 ah->is_pciexpress = false;
921 }
d7e7d229
LR		 922
923 if (AR_SREV_9271(ah))
924 ah->is_pciexpress = false;
925
aa4058ae
LR		 926 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
927
928 ath9k_hw_init_cal_settings(ah);
929
930 ah->ani_function = ATH9K_ANI_ALL;
931 if (AR_SREV_9280_10_OR_LATER(ah))
932 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
933
934 ath9k_hw_init_mode_regs(ah);
935
936 if (ah->is_pciexpress)
93b1b37f 937 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 938 else
939 ath9k_hw_disablepcie(ah);
940
f637cfd6 941 r = ath9k_hw_post_init(ah);
aa4058ae 942 if (r)
95fafca2 943 return r;
aa4058ae
LR		 944
945 ath9k_hw_init_mode_gain_regs(ah);
946 ath9k_hw_fill_cap_info(ah);
947 ath9k_hw_init_11a_eeprom_fix(ah);
f6688cd8 948
4f3acf81
LR		 949 r = ath9k_hw_init_macaddr(ah);
950 if (r) {
4d6b228d 951 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939 952 "Failed to initialize MAC address\n");
95fafca2 953 return r;
f078f209
LR		 954 }
955
d7e7d229 956 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 957 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 958 else
2660b81a 959 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 960
f1dc5600 961 ath9k_init_nfcal_hist_buffer(ah);
f078f209 962
4f3acf81 963 return 0;
f078f209
LR		 964}
965
cbe61d8a 966static void ath9k_hw_init_bb(struct ath_hw *ah,
f1dc5600 967 struct ath9k_channel *chan)
f078f209 968{
f1dc5600 969 u32 synthDelay;
f078f209 970
f1dc5600 971 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 972 if (IS_CHAN_B(chan))
f1dc5600
S		 973 synthDelay = (4 * synthDelay) / 22;
974 else
975 synthDelay /= 10;
f078f209 976
f1dc5600 977 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 978
f1dc5600 979 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 980}
981
cbe61d8a 982static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 983{
f1dc5600
S		 984 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
985 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 986
f1dc5600
S		 987 REG_WRITE(ah, AR_QOS_NO_ACK,
988 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
989 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
990 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
991
992 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
993 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
994 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
995 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
996 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 997}
998
cbe61d8a 999static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 1000 struct ath9k_channel *chan)
f078f209 1001{
f1dc5600 1002 u32 pll;
f078f209 1003
f1dc5600
S		 1004 if (AR_SREV_9100(ah)) {
1005 if (chan && IS_CHAN_5GHZ(chan))
1006 pll = 0x1450;
f078f209 1007 else
f1dc5600
S		 1008 pll = 0x1458;
1009 } else {
1010 if (AR_SREV_9280_10_OR_LATER(ah)) {
1011 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1012
f1dc5600
S		 1013 if (chan && IS_CHAN_HALF_RATE(chan))
1014 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1015 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1016 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1017
f1dc5600
S		 1018 if (chan && IS_CHAN_5GHZ(chan)) {
1019 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 1020
f078f209 1021
f1dc5600
S		 1022 if (AR_SREV_9280_20(ah)) {
1023 if (((chan->channel % 20) == 0)
1024 || ((chan->channel % 10) == 0))
1025 pll = 0x2850;
1026 else
1027 pll = 0x142c;
1028 }
1029 } else {
1030 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1031 }
f078f209 1032
f1dc5600 1033 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 1034
f1dc5600 1035 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1036
f1dc5600
S		 1037 if (chan && IS_CHAN_HALF_RATE(chan))
1038 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1039 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1040 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1041
f1dc5600
S		 1042 if (chan && IS_CHAN_5GHZ(chan))
1043 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1044 else
1045 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1046 } else {
1047 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 1048
f1dc5600
S		 1049 if (chan && IS_CHAN_HALF_RATE(chan))
1050 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1051 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1052 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 1053
f1dc5600
S		 1054 if (chan && IS_CHAN_5GHZ(chan))
1055 pll |= SM(0xa, AR_RTC_PLL_DIV);
1056 else
1057 pll |= SM(0xb, AR_RTC_PLL_DIV);
1058 }
1059 }
d03a66c1 1060 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 1061
f1dc5600
S		 1062 udelay(RTC_PLL_SETTLE_DELAY);
1063
1064 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 1065}
1066
cbe61d8a 1067static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
f078f209 1068{
f078f209
LR		 1069 int rx_chainmask, tx_chainmask;
1070
2660b81a
S		 1071 rx_chainmask = ah->rxchainmask;
1072 tx_chainmask = ah->txchainmask;
f078f209
LR		 1073
1074 switch (rx_chainmask) {
1075 case 0x5:
1076 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1077 AR_PHY_SWAP_ALT_CHAIN);
1078 case 0x3:
d535a42a 1079 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
f078f209
LR		 1080 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1081 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1082 break;
1083 }
1084 case 0x1:
1085 case 0x2:
f078f209
LR		 1086 case 0x7:
1087 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1088 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1089 break;
1090 default:
1091 break;
1092 }
1093
1094 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1095 if (tx_chainmask == 0x5) {
1096 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1097 AR_PHY_SWAP_ALT_CHAIN);
1098 }
1099 if (AR_SREV_9100(ah))
1100 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1101 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1102}
1103
cbe61d8a 1104static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 1105 enum nl80211_iftype opmode)
f078f209 1106{
2660b81a 1107 ah->mask_reg = AR_IMR_TXERR |
f1dc5600
S		 1108 AR_IMR_TXURN |
1109 AR_IMR_RXERR |
1110 AR_IMR_RXORN |
1111 AR_IMR_BCNMISC;
f078f209 1112
0ef1f168 1113 if (ah->config.intr_mitigation)
2660b81a 1114 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1115 else
2660b81a 1116 ah->mask_reg |= AR_IMR_RXOK;
f078f209 1117
2660b81a 1118 ah->mask_reg |= AR_IMR_TXOK;
f078f209 1119
d97809db 1120 if (opmode == NL80211_IFTYPE_AP)
2660b81a 1121 ah->mask_reg |= AR_IMR_MIB;
f078f209 1122
2660b81a 1123 REG_WRITE(ah, AR_IMR, ah->mask_reg);
f1dc5600 1124 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1125
f1dc5600
S		 1126 if (!AR_SREV_9100(ah)) {
1127 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1128 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1129 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1130 }
f078f209
LR		 1131}
1132
cbe61d8a 1133static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1134{
f078f209 1135 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
4d6b228d 1136 DPRINTF(ah, ATH_DBG_RESET, "bad ack timeout %u\n", us);
2660b81a 1137 ah->acktimeout = (u32) -1;
f078f209
LR		 1138 return false;
1139 } else {
1140 REG_RMW_FIELD(ah, AR_TIME_OUT,
1141 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1142 ah->acktimeout = us;
f078f209
LR		 1143 return true;
1144 }
1145}
1146
cbe61d8a 1147static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
f078f209 1148{
f078f209 1149 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
4d6b228d 1150 DPRINTF(ah, ATH_DBG_RESET, "bad cts timeout %u\n", us);
2660b81a 1151 ah->ctstimeout = (u32) -1;
f078f209
LR		 1152 return false;
1153 } else {
1154 REG_RMW_FIELD(ah, AR_TIME_OUT,
1155 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1156 ah->ctstimeout = us;
f078f209
LR		 1157 return true;
1158 }
1159}
f1dc5600 1160
cbe61d8a 1161static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1162{
f078f209 1163 if (tu > 0xFFFF) {
4d6b228d 1164 DPRINTF(ah, ATH_DBG_XMIT,
04bd4638 1165 "bad global tx timeout %u\n", tu);
2660b81a 1166 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1167 return false;
1168 } else {
1169 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1170 ah->globaltxtimeout = tu;
f078f209
LR		 1171 return true;
1172 }
1173}
1174
cbe61d8a 1175static void ath9k_hw_init_user_settings(struct ath_hw *ah)
f078f209 1176{
4d6b228d 1177 DPRINTF(ah, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
2660b81a 1178 ah->misc_mode);
f078f209 1179
2660b81a 1180 if (ah->misc_mode != 0)
f1dc5600 1181 REG_WRITE(ah, AR_PCU_MISC,
2660b81a
S		 1182 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1183 if (ah->slottime != (u32) -1)
1184 ath9k_hw_setslottime(ah, ah->slottime);
1185 if (ah->acktimeout != (u32) -1)
1186 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1187 if (ah->ctstimeout != (u32) -1)
1188 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1189 if (ah->globaltxtimeout != (u32) -1)
1190 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600
S		 1191}
1192
1193const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1194{
1195 return vendorid == ATHEROS_VENDOR_ID ?
1196 ath9k_hw_devname(devid) : NULL;
1197}
1198
cbe61d8a 1199void ath9k_hw_detach(struct ath_hw *ah)
f1dc5600
S		 1200{
1201 if (!AR_SREV_9100(ah))
e70c0cfd 1202 ath9k_hw_ani_disable(ah);
f1dc5600 1203
081b35ab 1204 ath9k_hw_rf_free(ah);
9ecdef4b 1205 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1206 kfree(ah);
9db6b6a2 1207 ah = NULL;
f1dc5600
S		 1208}
1209
f1dc5600
S		 1210/*******/
1211/* INI */
1212/*******/
1213
cbe61d8a 1214static void ath9k_hw_override_ini(struct ath_hw *ah,
f1dc5600
S		 1215 struct ath9k_channel *chan)
1216{
d7e7d229
LR		 1217 u32 val;
1218
1219 if (AR_SREV_9271(ah)) {
1220 /*
1221 * Enable spectral scan to solution for issues with stuck
1222 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1223 * AR9271 1.1
1224 */
1225 if (AR_SREV_9271_10(ah)) {
1226 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1227 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1228 }
1229 else if (AR_SREV_9271_11(ah))
1230 /*
1231 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1232 * present on AR9271 1.1
1233 */
1234 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1235 return;
1236 }
1237
8aa15e15
SB		 1238 /*
1239 * Set the RX_ABORT and RX_DIS and clear if off only after
1240 * RXE is set for MAC. This prevents frames with corrupted
1241 * descriptor status.
1242 */
1243 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1244
204d7940
VT		 1245 if (AR_SREV_9280_10_OR_LATER(ah)) {
1246 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1247 (~AR_PCU_MISC_MODE2_HWWAR1);
1248
1249 if (AR_SREV_9287_10_OR_LATER(ah))
1250 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1251
1252 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1253 }
8aa15e15 1254
a8c96d3b 1255 if (!AR_SREV_5416_20_OR_LATER(ah) ||
f1dc5600
S		 1256 AR_SREV_9280_10_OR_LATER(ah))
1257 return;
d7e7d229
LR		 1258 /*
1259 * Disable BB clock gating
1260 * Necessary to avoid issues on AR5416 2.0
1261 */
f1dc5600 1262 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1263}
1264
cbe61d8a 1265static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
e7594072 1266 struct ar5416_eeprom_def *pEepData,
f1dc5600 1267 u32 reg, u32 value)
f078f209 1268{
f1dc5600 1269 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
f078f209 1270
d535a42a 1271 switch (ah->hw_version.devid) {
f1dc5600
S		 1272 case AR9280_DEVID_PCI:
1273 if (reg == 0x7894) {
4d6b228d 1274 DPRINTF(ah, ATH_DBG_EEPROM,
f1dc5600
S		 1275 "ini VAL: %x EEPROM: %x\n", value,
1276 (pBase->version & 0xff));
1277
1278 if ((pBase->version & 0xff) > 0x0a) {
4d6b228d 1279 DPRINTF(ah, ATH_DBG_EEPROM,
f1dc5600
S		 1280 "PWDCLKIND: %d\n",
1281 pBase->pwdclkind);
1282 value &= ~AR_AN_TOP2_PWDCLKIND;
1283 value |= AR_AN_TOP2_PWDCLKIND &
1284 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1285 } else {
4d6b228d 1286 DPRINTF(ah, ATH_DBG_EEPROM,
f1dc5600
S		 1287 "PWDCLKIND Earlier Rev\n");
1288 }
1289
4d6b228d 1290 DPRINTF(ah, ATH_DBG_EEPROM,
f1dc5600
S		 1291 "final ini VAL: %x\n", value);
1292 }
1293 break;
1294 }
1295
1296 return value;
f078f209
LR		 1297}
1298
cbe61d8a 1299static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072
SB		 1300 struct ar5416_eeprom_def *pEepData,
1301 u32 reg, u32 value)
1302{
2660b81a 1303 if (ah->eep_map == EEP_MAP_4KBITS)
e7594072
SB		 1304 return value;
1305 else
1306 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1307}
1308
8bd1d07f
SB		 1309static void ath9k_olc_init(struct ath_hw *ah)
1310{
1311 u32 i;
1312
db91f2e4
VN		 1313 if (OLC_FOR_AR9287_10_LATER) {
1314 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1315 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1316 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1317 AR9287_AN_TXPC0_TXPCMODE,
1318 AR9287_AN_TXPC0_TXPCMODE_S,
1319 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1320 udelay(100);
1321 } else {
1322 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1323 ah->originalGain[i] =
1324 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1325 AR_PHY_TX_GAIN);
1326 ah->PDADCdelta = 0;
1327 }
8bd1d07f
SB		 1328}
1329
3a702e49
BC		 1330static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1331 struct ath9k_channel *chan)
1332{
1333 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1334
1335 if (IS_CHAN_B(chan))
1336 ctl |= CTL_11B;
1337 else if (IS_CHAN_G(chan))
1338 ctl |= CTL_11G;
1339 else
1340 ctl |= CTL_11A;
1341
1342 return ctl;
1343}
1344
cbe61d8a 1345static int ath9k_hw_process_ini(struct ath_hw *ah,
f1dc5600
S		 1346 struct ath9k_channel *chan,
1347 enum ath9k_ht_macmode macmode)
f078f209 1348{
608b88cb 1349 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f078f209 1350 int i, regWrites = 0;
5f8e077c 1351 struct ieee80211_channel *channel = chan->chan;
f078f209 1352 u32 modesIndex, freqIndex;
f078f209
LR		 1353
1354 switch (chan->chanmode) {
1355 case CHANNEL_A:
1356 case CHANNEL_A_HT20:
1357 modesIndex = 1;
1358 freqIndex = 1;
1359 break;
1360 case CHANNEL_A_HT40PLUS:
1361 case CHANNEL_A_HT40MINUS:
1362 modesIndex = 2;
1363 freqIndex = 1;
1364 break;
1365 case CHANNEL_G:
1366 case CHANNEL_G_HT20:
1367 case CHANNEL_B:
1368 modesIndex = 4;
1369 freqIndex = 2;
1370 break;
1371 case CHANNEL_G_HT40PLUS:
1372 case CHANNEL_G_HT40MINUS:
1373 modesIndex = 3;
1374 freqIndex = 2;
1375 break;
1376
1377 default:
1378 return -EINVAL;
1379 }
1380
1381 REG_WRITE(ah, AR_PHY(0), 0x00000007);
f078f209 1382 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
f74df6fb 1383 ah->eep_ops->set_addac(ah, chan);
f078f209 1384
a8c96d3b 1385 if (AR_SREV_5416_22_OR_LATER(ah)) {
2660b81a 1386 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
f078f209
LR		 1387 } else {
1388 struct ar5416IniArray temp;
1389 u32 addacSize =
2660b81a
S		 1390 sizeof(u32) * ah->iniAddac.ia_rows *
1391 ah->iniAddac.ia_columns;
f078f209 1392
2660b81a
S		 1393 memcpy(ah->addac5416_21,
1394 ah->iniAddac.ia_array, addacSize);
f078f209 1395
2660b81a 1396 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
f078f209 1397
2660b81a
S		 1398 temp.ia_array = ah->addac5416_21;
1399 temp.ia_columns = ah->iniAddac.ia_columns;
1400 temp.ia_rows = ah->iniAddac.ia_rows;
f078f209
LR		 1401 REG_WRITE_ARRAY(&temp, 1, regWrites);
1402 }
f1dc5600 1403
f078f209
LR		 1404 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1405
2660b81a
S		 1406 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1407 u32 reg = INI_RA(&ah->iniModes, i, 0);
1408 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
f078f209 1409
f078f209
LR		 1410 REG_WRITE(ah, reg, val);
1411
1412 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1413 && ah->config.analog_shiftreg) {
f078f209
LR		 1414 udelay(100);
1415 }
1416
1417 DO_DELAY(regWrites);
1418 }
1419
ac88b6ec 1420 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1421 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
9f804202 1422
ac88b6ec
VN		 1423 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1424 AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1425 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
9f804202 1426
2660b81a
S		 1427 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1428 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1429 u32 val = INI_RA(&ah->iniCommon, i, 1);
f078f209
LR		 1430
1431 REG_WRITE(ah, reg, val);
1432
1433 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1434 && ah->config.analog_shiftreg) {
f078f209
LR		 1435 udelay(100);
1436 }
1437
1438 DO_DELAY(regWrites);
1439 }
1440
1441 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1442
1443 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
2660b81a 1444 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
f078f209
LR		 1445 regWrites);
1446 }
1447
1448 ath9k_hw_override_ini(ah, chan);
1449 ath9k_hw_set_regs(ah, chan, macmode);
1450 ath9k_hw_init_chain_masks(ah);
1451
8bd1d07f
SB		 1452 if (OLC_FOR_AR9280_20_LATER)
1453 ath9k_olc_init(ah);
1454
8fbff4b8 1455 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1456 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 1457 channel->max_antenna_gain * 2,
1458 channel->max_power * 2,
1459 min((u32) MAX_RATE_POWER,
608b88cb 1460 (u32) regulatory->power_limit));
f078f209
LR		 1461
1462 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
4d6b228d 1463 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1464 "ar5416SetRfRegs failed\n");
f078f209
LR		 1465 return -EIO;
1466 }
1467
1468 return 0;
1469}
1470
f1dc5600
S		 1471/****************************************/
1472/* Reset and Channel Switching Routines */
1473/****************************************/
1474
cbe61d8a 1475static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1476{
f1dc5600
S		 1477 u32 rfMode = 0;
1478
1479 if (chan == NULL)
1480 return;
1481
1482 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1483 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1484
1485 if (!AR_SREV_9280_10_OR_LATER(ah))
1486 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1487 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1488
1489 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1490 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1491
1492 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1493}
1494
cbe61d8a 1495static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
f1dc5600
S		 1496{
1497 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1498}
1499
cbe61d8a 1500static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 1501{
1502 u32 regval;
1503
d7e7d229
LR		 1504 /*
1505 * set AHB_MODE not to do cacheline prefetches
1506 */
f1dc5600
S		 1507 regval = REG_READ(ah, AR_AHB_MODE);
1508 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1509
d7e7d229
LR		 1510 /*
1511 * let mac dma reads be in 128 byte chunks
1512 */
f1dc5600
S		 1513 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1514 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1515
d7e7d229
LR		 1516 /*
1517 * Restore TX Trigger Level to its pre-reset value.
1518 * The initial value depends on whether aggregation is enabled, and is
1519 * adjusted whenever underruns are detected.
1520 */
2660b81a 1521 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1522
d7e7d229
LR		 1523 /*
1524 * let mac dma writes be in 128 byte chunks
1525 */
f1dc5600
S		 1526 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1527 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1528
d7e7d229
LR		 1529 /*
1530 * Setup receive FIFO threshold to hold off TX activities
1531 */
f1dc5600
S		 1532 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1533
d7e7d229
LR		 1534 /*
1535 * reduce the number of usable entries in PCU TXBUF to avoid
1536 * wrap around issues.
1537 */
f1dc5600 1538 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1539 /* For AR9285 the number of Fifos are reduced to half.
1540 * So set the usable tx buf size also to half to
1541 * avoid data/delimiter underruns
1542 */
f1dc5600
S		 1543 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1544 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1545 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1546 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1547 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1548 }
1549}
1550
cbe61d8a 1551static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1552{
1553 u32 val;
1554
1555 val = REG_READ(ah, AR_STA_ID1);
1556 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1557 switch (opmode) {
d97809db 1558 case NL80211_IFTYPE_AP:
f1dc5600
S		 1559 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1560 | AR_STA_ID1_KSRCH_MODE);
1561 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1562 break;
d97809db 1563 case NL80211_IFTYPE_ADHOC:
9cb5412b 1564 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 1565 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1566 | AR_STA_ID1_KSRCH_MODE);
1567 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1568 break;
d97809db
CM		 1569 case NL80211_IFTYPE_STATION:
1570 case NL80211_IFTYPE_MONITOR:
f1dc5600 1571 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1572 break;
f1dc5600
S		 1573 }
1574}
1575
cbe61d8a 1576static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
f1dc5600
S		 1577 u32 coef_scaled,
1578 u32 *coef_mantissa,
1579 u32 *coef_exponent)
1580{
1581 u32 coef_exp, coef_man;
1582
1583 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1584 if ((coef_scaled >> coef_exp) & 0x1)
1585 break;
1586
1587 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1588
1589 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1590
1591 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1592 *coef_exponent = coef_exp - 16;
1593}
1594
cbe61d8a 1595static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
f1dc5600
S		 1596 struct ath9k_channel *chan)
1597{
1598 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1599 u32 clockMhzScaled = 0x64000000;
1600 struct chan_centers centers;
1601
1602 if (IS_CHAN_HALF_RATE(chan))
1603 clockMhzScaled = clockMhzScaled >> 1;
1604 else if (IS_CHAN_QUARTER_RATE(chan))
1605 clockMhzScaled = clockMhzScaled >> 2;
1606
1607 ath9k_hw_get_channel_centers(ah, chan, &centers);
1608 coef_scaled = clockMhzScaled / centers.synth_center;
1609
1610 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1611 &ds_coef_exp);
1612
1613 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1614 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1615 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1616 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1617
1618 coef_scaled = (9 * coef_scaled) / 10;
1619
1620 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1621 &ds_coef_exp);
1622
1623 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1624 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1625 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1626 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1627}
1628
cbe61d8a 1629static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1630{
1631 u32 rst_flags;
1632 u32 tmpReg;
1633
70768496
S		 1634 if (AR_SREV_9100(ah)) {
1635 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1636 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1637 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1638 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1639 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1640 }
1641
f1dc5600
S		 1642 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1643 AR_RTC_FORCE_WAKE_ON_INT);
1644
1645 if (AR_SREV_9100(ah)) {
1646 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1647 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1648 } else {
1649 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1650 if (tmpReg &
1651 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1652 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1653 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1654 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1655 } else {
1656 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1657 }
1658
1659 rst_flags = AR_RTC_RC_MAC_WARM;
1660 if (type == ATH9K_RESET_COLD)
1661 rst_flags |= AR_RTC_RC_MAC_COLD;
1662 }
1663
d03a66c1 1664 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1665 udelay(50);
1666
d03a66c1 1667 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1668 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
4d6b228d 1669 DPRINTF(ah, ATH_DBG_RESET,
04bd4638 1670 "RTC stuck in MAC reset\n");
f1dc5600
S		 1671 return false;
1672 }
1673
1674 if (!AR_SREV_9100(ah))
1675 REG_WRITE(ah, AR_RC, 0);
1676
1677 ath9k_hw_init_pll(ah, NULL);
1678
1679 if (AR_SREV_9100(ah))
1680 udelay(50);
1681
1682 return true;
1683}
1684
cbe61d8a 1685static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1686{
1687 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1688 AR_RTC_FORCE_WAKE_ON_INT);
1689
1c29ce67
VT		 1690 if (!AR_SREV_9100(ah))
1691 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1692
d03a66c1 1693 REG_WRITE(ah, AR_RTC_RESET, 0);
8bd1d07f 1694 udelay(2);
1c29ce67
VT		 1695
1696 if (!AR_SREV_9100(ah))
1697 REG_WRITE(ah, AR_RC, 0);
1698
d03a66c1 1699 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1700
1701 if (!ath9k_hw_wait(ah,
1702 AR_RTC_STATUS,
1703 AR_RTC_STATUS_M,
0caa7b14
S		 1704 AR_RTC_STATUS_ON,
1705 AH_WAIT_TIMEOUT)) {
4d6b228d 1706 DPRINTF(ah, ATH_DBG_RESET, "RTC not waking up\n");
f1dc5600 1707 return false;
f078f209
LR		 1708 }
1709
f1dc5600
S		 1710 ath9k_hw_read_revisions(ah);
1711
1712 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1713}
1714
cbe61d8a 1715static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1716{
1717 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1718 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1719
1720 switch (type) {
1721 case ATH9K_RESET_POWER_ON:
1722 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1723 case ATH9K_RESET_WARM:
1724 case ATH9K_RESET_COLD:
1725 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1726 default:
1727 return false;
1728 }
f078f209
LR		 1729}
1730
cbe61d8a 1731static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
f1dc5600 1732 enum ath9k_ht_macmode macmode)
f078f209 1733{
f1dc5600 1734 u32 phymode;
e7594072 1735 u32 enableDacFifo = 0;
f078f209 1736
e7594072
SB		 1737 if (AR_SREV_9285_10_OR_LATER(ah))
1738 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1739 AR_PHY_FC_ENABLE_DAC_FIFO);
1740
f1dc5600 1741 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1742 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1743
1744 if (IS_CHAN_HT40(chan)) {
1745 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1746
f1dc5600
S		 1747 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1748 (chan->chanmode == CHANNEL_G_HT40PLUS))
1749 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1750
2660b81a 1751 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
f1dc5600 1752 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
f078f209 1753 }
f1dc5600
S		 1754 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1755
1756 ath9k_hw_set11nmac2040(ah, macmode);
f078f209 1757
f1dc5600
S		 1758 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1759 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1760}
1761
cbe61d8a 1762static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1763 struct ath9k_channel *chan)
f078f209 1764{
42abfbee 1765 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1766 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1767 return false;
1768 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1769 return false;
f078f209 1770
9ecdef4b 1771 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1772 return false;
f078f209 1773
2660b81a 1774 ah->chip_fullsleep = false;
f1dc5600 1775 ath9k_hw_init_pll(ah, chan);
f1dc5600 1776 ath9k_hw_set_rfmode(ah, chan);
f078f209 1777
f1dc5600 1778 return true;
f078f209
LR		 1779}
1780
cbe61d8a 1781static bool ath9k_hw_channel_change(struct ath_hw *ah,
f1dc5600
S		 1782 struct ath9k_channel *chan,
1783 enum ath9k_ht_macmode macmode)
f078f209 1784{
608b88cb 1785 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
5f8e077c 1786 struct ieee80211_channel *channel = chan->chan;
f078f209 1787 u32 synthDelay, qnum;
f078f209
LR		 1788
1789 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1790 if (ath9k_hw_numtxpending(ah, qnum)) {
4d6b228d 1791 DPRINTF(ah, ATH_DBG_QUEUE,
04bd4638 1792 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1793 return false;
1794 }
1795 }
1796
1797 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1798 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
0caa7b14 1799 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
4d6b228d 1800 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1801 "Could not kill baseband RX\n");
f078f209
LR		 1802 return false;
1803 }
1804
1805 ath9k_hw_set_regs(ah, chan, macmode);
1806
1807 if (AR_SREV_9280_10_OR_LATER(ah)) {
8fbff4b8 1808 ath9k_hw_ar9280_set_channel(ah, chan);
f078f209
LR		 1809 } else {
1810 if (!(ath9k_hw_set_channel(ah, chan))) {
4d6b228d 1811 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939 1812 "Failed to set channel\n");
f078f209
LR		 1813 return false;
1814 }
1815 }
1816
8fbff4b8 1817 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1818 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1819 channel->max_antenna_gain * 2,
1820 channel->max_power * 2,
1821 min((u32) MAX_RATE_POWER,
608b88cb 1822 (u32) regulatory->power_limit));
f078f209
LR		 1823
1824 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1825 if (IS_CHAN_B(chan))
f078f209
LR		 1826 synthDelay = (4 * synthDelay) / 22;
1827 else
1828 synthDelay /= 10;
1829
1830 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1831
1832 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1833
f1dc5600
S		 1834 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1835 ath9k_hw_set_delta_slope(ah, chan);
1836
1837 if (AR_SREV_9280_10_OR_LATER(ah))
1838 ath9k_hw_9280_spur_mitigate(ah, chan);
1839 else
1840 ath9k_hw_spur_mitigate(ah, chan);
1841
1842 if (!chan->oneTimeCalsDone)
1843 chan->oneTimeCalsDone = true;
1844
1845 return true;
1846}
1847
cbe61d8a 1848static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 1849{
1850 int bb_spur = AR_NO_SPUR;
1851 int freq;
1852 int bin, cur_bin;
1853 int bb_spur_off, spur_subchannel_sd;
1854 int spur_freq_sd;
1855 int spur_delta_phase;
1856 int denominator;
1857 int upper, lower, cur_vit_mask;
1858 int tmp, newVal;
1859 int i;
1860 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1861 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1862 };
1863 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1864 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1865 };
1866 int inc[4] = { 0, 100, 0, 0 };
1867 struct chan_centers centers;
1868
1869 int8_t mask_m[123];
1870 int8_t mask_p[123];
1871 int8_t mask_amt;
1872 int tmp_mask;
1873 int cur_bb_spur;
1874 bool is2GHz = IS_CHAN_2GHZ(chan);
1875
1876 memset(&mask_m, 0, sizeof(int8_t) * 123);
1877 memset(&mask_p, 0, sizeof(int8_t) * 123);
1878
1879 ath9k_hw_get_channel_centers(ah, chan, &centers);
1880 freq = centers.synth_center;
1881
2660b81a 1882 ah->config.spurmode = SPUR_ENABLE_EEPROM;
f1dc5600 1883 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 1884 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 1885
1886 if (is2GHz)
1887 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1888 else
1889 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1890
1891 if (AR_NO_SPUR == cur_bb_spur)
1892 break;
1893 cur_bb_spur = cur_bb_spur - freq;
1894
1895 if (IS_CHAN_HT40(chan)) {
1896 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1897 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1898 bb_spur = cur_bb_spur;
1899 break;
1900 }
1901 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1902 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1903 bb_spur = cur_bb_spur;
1904 break;
1905 }
1906 }
1907
1908 if (AR_NO_SPUR == bb_spur) {
1909 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1910 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1911 return;
1912 } else {
1913 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1914 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1915 }
1916
1917 bin = bb_spur * 320;
1918
1919 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1920
1921 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1922 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1923 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1924 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1925 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1926
1927 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1928 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1929 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1930 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1931 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1932 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1933
1934 if (IS_CHAN_HT40(chan)) {
1935 if (bb_spur < 0) {
1936 spur_subchannel_sd = 1;
1937 bb_spur_off = bb_spur + 10;
1938 } else {
1939 spur_subchannel_sd = 0;
1940 bb_spur_off = bb_spur - 10;
1941 }
1942 } else {
1943 spur_subchannel_sd = 0;
1944 bb_spur_off = bb_spur;
1945 }
1946
1947 if (IS_CHAN_HT40(chan))
1948 spur_delta_phase =
1949 ((bb_spur * 262144) /
1950 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1951 else
1952 spur_delta_phase =
1953 ((bb_spur * 524288) /
1954 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1955
1956 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1957 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1958
1959 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1960 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1961 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1962 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1963
1964 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1965 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1966
1967 cur_bin = -6000;
1968 upper = bin + 100;
1969 lower = bin - 100;
1970
1971 for (i = 0; i < 4; i++) {
1972 int pilot_mask = 0;
1973 int chan_mask = 0;
1974 int bp = 0;
1975 for (bp = 0; bp < 30; bp++) {
1976 if ((cur_bin > lower) && (cur_bin < upper)) {
1977 pilot_mask = pilot_mask | 0x1 << bp;
1978 chan_mask = chan_mask | 0x1 << bp;
1979 }
1980 cur_bin += 100;
1981 }
1982 cur_bin += inc[i];
1983 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1984 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1985 }
1986
1987 cur_vit_mask = 6100;
1988 upper = bin + 120;
1989 lower = bin - 120;
1990
1991 for (i = 0; i < 123; i++) {
1992 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1993
1994 /* workaround for gcc bug #37014 */
a085ff71 1995 volatile int tmp_v = abs(cur_vit_mask - bin);
f1dc5600 1996
a085ff71 1997 if (tmp_v < 75)
f1dc5600
S		 1998 mask_amt = 1;
1999 else
2000 mask_amt = 0;
2001 if (cur_vit_mask < 0)
2002 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2003 else
2004 mask_p[cur_vit_mask / 100] = mask_amt;
2005 }
2006 cur_vit_mask -= 100;
2007 }
2008
2009 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2010 | (mask_m[48] << 26) | (mask_m[49] << 24)
2011 | (mask_m[50] << 22) | (mask_m[51] << 20)
2012 | (mask_m[52] << 18) | (mask_m[53] << 16)
2013 | (mask_m[54] << 14) | (mask_m[55] << 12)
2014 | (mask_m[56] << 10) | (mask_m[57] << 8)
2015 | (mask_m[58] << 6) | (mask_m[59] << 4)
2016 | (mask_m[60] << 2) | (mask_m[61] << 0);
2017 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2018 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2019
2020 tmp_mask = (mask_m[31] << 28)
2021 | (mask_m[32] << 26) | (mask_m[33] << 24)
2022 | (mask_m[34] << 22) | (mask_m[35] << 20)
2023 | (mask_m[36] << 18) | (mask_m[37] << 16)
2024 | (mask_m[48] << 14) | (mask_m[39] << 12)
2025 | (mask_m[40] << 10) | (mask_m[41] << 8)
2026 | (mask_m[42] << 6) | (mask_m[43] << 4)
2027 | (mask_m[44] << 2) | (mask_m[45] << 0);
2028 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2029 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2030
2031 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2032 | (mask_m[18] << 26) | (mask_m[18] << 24)
2033 | (mask_m[20] << 22) | (mask_m[20] << 20)
2034 | (mask_m[22] << 18) | (mask_m[22] << 16)
2035 | (mask_m[24] << 14) | (mask_m[24] << 12)
2036 | (mask_m[25] << 10) | (mask_m[26] << 8)
2037 | (mask_m[27] << 6) | (mask_m[28] << 4)
2038 | (mask_m[29] << 2) | (mask_m[30] << 0);
2039 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2040 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2041
2042 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2043 | (mask_m[2] << 26) | (mask_m[3] << 24)
2044 | (mask_m[4] << 22) | (mask_m[5] << 20)
2045 | (mask_m[6] << 18) | (mask_m[7] << 16)
2046 | (mask_m[8] << 14) | (mask_m[9] << 12)
2047 | (mask_m[10] << 10) | (mask_m[11] << 8)
2048 | (mask_m[12] << 6) | (mask_m[13] << 4)
2049 | (mask_m[14] << 2) | (mask_m[15] << 0);
2050 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2051 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2052
2053 tmp_mask = (mask_p[15] << 28)
2054 | (mask_p[14] << 26) | (mask_p[13] << 24)
2055 | (mask_p[12] << 22) | (mask_p[11] << 20)
2056 | (mask_p[10] << 18) | (mask_p[9] << 16)
2057 | (mask_p[8] << 14) | (mask_p[7] << 12)
2058 | (mask_p[6] << 10) | (mask_p[5] << 8)
2059 | (mask_p[4] << 6) | (mask_p[3] << 4)
2060 | (mask_p[2] << 2) | (mask_p[1] << 0);
2061 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2062 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2063
f1dc5600
S		 2064 tmp_mask = (mask_p[30] << 28)
2065 | (mask_p[29] << 26) | (mask_p[28] << 24)
2066 | (mask_p[27] << 22) | (mask_p[26] << 20)
2067 | (mask_p[25] << 18) | (mask_p[24] << 16)
2068 | (mask_p[23] << 14) | (mask_p[22] << 12)
2069 | (mask_p[21] << 10) | (mask_p[20] << 8)
2070 | (mask_p[19] << 6) | (mask_p[18] << 4)
2071 | (mask_p[17] << 2) | (mask_p[16] << 0);
2072 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2073 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2074
f1dc5600
S		 2075 tmp_mask = (mask_p[45] << 28)
2076 | (mask_p[44] << 26) | (mask_p[43] << 24)
2077 | (mask_p[42] << 22) | (mask_p[41] << 20)
2078 | (mask_p[40] << 18) | (mask_p[39] << 16)
2079 | (mask_p[38] << 14) | (mask_p[37] << 12)
2080 | (mask_p[36] << 10) | (mask_p[35] << 8)
2081 | (mask_p[34] << 6) | (mask_p[33] << 4)
2082 | (mask_p[32] << 2) | (mask_p[31] << 0);
2083 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2084 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2085
f1dc5600
S		 2086 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2087 | (mask_p[59] << 26) | (mask_p[58] << 24)
2088 | (mask_p[57] << 22) | (mask_p[56] << 20)
2089 | (mask_p[55] << 18) | (mask_p[54] << 16)
2090 | (mask_p[53] << 14) | (mask_p[52] << 12)
2091 | (mask_p[51] << 10) | (mask_p[50] << 8)
2092 | (mask_p[49] << 6) | (mask_p[48] << 4)
2093 | (mask_p[47] << 2) | (mask_p[46] << 0);
2094 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2095 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2096}
2097
cbe61d8a 2098static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 2099{
f1dc5600
S		 2100 int bb_spur = AR_NO_SPUR;
2101 int bin, cur_bin;
2102 int spur_freq_sd;
2103 int spur_delta_phase;
2104 int denominator;
2105 int upper, lower, cur_vit_mask;
2106 int tmp, new;
2107 int i;
2108 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2109 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2110 };
2111 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2112 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2113 };
2114 int inc[4] = { 0, 100, 0, 0 };
f078f209 2115
f1dc5600
S		 2116 int8_t mask_m[123];
2117 int8_t mask_p[123];
2118 int8_t mask_amt;
2119 int tmp_mask;
2120 int cur_bb_spur;
2121 bool is2GHz = IS_CHAN_2GHZ(chan);
f078f209 2122
f1dc5600
S		 2123 memset(&mask_m, 0, sizeof(int8_t) * 123);
2124 memset(&mask_p, 0, sizeof(int8_t) * 123);
f078f209 2125
f1dc5600 2126 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 2127 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 2128 if (AR_NO_SPUR == cur_bb_spur)
2129 break;
2130 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2131 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2132 bb_spur = cur_bb_spur;
2133 break;
2134 }
2135 }
f078f209 2136
f1dc5600
S		 2137 if (AR_NO_SPUR == bb_spur)
2138 return;
f078f209 2139
f1dc5600 2140 bin = bb_spur * 32;
f078f209 2141
f1dc5600
S		 2142 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2143 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2144 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2145 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2146 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
f078f209 2147
f1dc5600 2148 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
f078f209 2149
f1dc5600
S		 2150 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2151 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2152 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2153 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2154 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2155 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
f078f209 2156
f1dc5600
S		 2157 spur_delta_phase = ((bb_spur * 524288) / 100) &
2158 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
f078f209 2159
f1dc5600
S		 2160 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2161 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
f078f209 2162
f1dc5600
S		 2163 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2164 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2165 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2166 REG_WRITE(ah, AR_PHY_TIMING11, new);
f078f209 2167
f1dc5600
S		 2168 cur_bin = -6000;
2169 upper = bin + 100;
2170 lower = bin - 100;
f078f209 2171
f1dc5600
S		 2172 for (i = 0; i < 4; i++) {
2173 int pilot_mask = 0;
2174 int chan_mask = 0;
2175 int bp = 0;
2176 for (bp = 0; bp < 30; bp++) {
2177 if ((cur_bin > lower) && (cur_bin < upper)) {
2178 pilot_mask = pilot_mask | 0x1 << bp;
2179 chan_mask = chan_mask | 0x1 << bp;
2180 }
2181 cur_bin += 100;
2182 }
2183 cur_bin += inc[i];
2184 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2185 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
f078f209 2186 }
f078f209 2187
f1dc5600
S		 2188 cur_vit_mask = 6100;
2189 upper = bin + 120;
2190 lower = bin - 120;
f078f209 2191
f1dc5600
S		 2192 for (i = 0; i < 123; i++) {
2193 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
f078f209 2194
f1dc5600 2195 /* workaround for gcc bug #37014 */
a085ff71 2196 volatile int tmp_v = abs(cur_vit_mask - bin);
f078f209 2197
a085ff71 2198 if (tmp_v < 75)
f1dc5600
S		 2199 mask_amt = 1;
2200 else
2201 mask_amt = 0;
2202 if (cur_vit_mask < 0)
2203 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2204 else
2205 mask_p[cur_vit_mask / 100] = mask_amt;
2206 }
2207 cur_vit_mask -= 100;
f078f209
LR		 2208 }
2209
f1dc5600
S		 2210 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2211 | (mask_m[48] << 26) | (mask_m[49] << 24)
2212 | (mask_m[50] << 22) | (mask_m[51] << 20)
2213 | (mask_m[52] << 18) | (mask_m[53] << 16)
2214 | (mask_m[54] << 14) | (mask_m[55] << 12)
2215 | (mask_m[56] << 10) | (mask_m[57] << 8)
2216 | (mask_m[58] << 6) | (mask_m[59] << 4)
2217 | (mask_m[60] << 2) | (mask_m[61] << 0);
2218 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2219 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
f078f209 2220
f1dc5600
S		 2221 tmp_mask = (mask_m[31] << 28)
2222 | (mask_m[32] << 26) | (mask_m[33] << 24)
2223 | (mask_m[34] << 22) | (mask_m[35] << 20)
2224 | (mask_m[36] << 18) | (mask_m[37] << 16)
2225 | (mask_m[48] << 14) | (mask_m[39] << 12)
2226 | (mask_m[40] << 10) | (mask_m[41] << 8)
2227 | (mask_m[42] << 6) | (mask_m[43] << 4)
2228 | (mask_m[44] << 2) | (mask_m[45] << 0);
2229 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2230 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
f078f209 2231
f1dc5600
S		 2232 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2233 | (mask_m[18] << 26) | (mask_m[18] << 24)
2234 | (mask_m[20] << 22) | (mask_m[20] << 20)
2235 | (mask_m[22] << 18) | (mask_m[22] << 16)
2236 | (mask_m[24] << 14) | (mask_m[24] << 12)
2237 | (mask_m[25] << 10) | (mask_m[26] << 8)
2238 | (mask_m[27] << 6) | (mask_m[28] << 4)
2239 | (mask_m[29] << 2) | (mask_m[30] << 0);
2240 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2241 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
f078f209 2242
f1dc5600
S		 2243 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2244 | (mask_m[2] << 26) | (mask_m[3] << 24)
2245 | (mask_m[4] << 22) | (mask_m[5] << 20)
2246 | (mask_m[6] << 18) | (mask_m[7] << 16)
2247 | (mask_m[8] << 14) | (mask_m[9] << 12)
2248 | (mask_m[10] << 10) | (mask_m[11] << 8)
2249 | (mask_m[12] << 6) | (mask_m[13] << 4)
2250 | (mask_m[14] << 2) | (mask_m[15] << 0);
2251 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2252 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
f078f209 2253
f1dc5600
S		 2254 tmp_mask = (mask_p[15] << 28)
2255 | (mask_p[14] << 26) | (mask_p[13] << 24)
2256 | (mask_p[12] << 22) | (mask_p[11] << 20)
2257 | (mask_p[10] << 18) | (mask_p[9] << 16)
2258 | (mask_p[8] << 14) | (mask_p[7] << 12)
2259 | (mask_p[6] << 10) | (mask_p[5] << 8)
2260 | (mask_p[4] << 6) | (mask_p[3] << 4)
2261 | (mask_p[2] << 2) | (mask_p[1] << 0);
2262 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2263 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2264
f1dc5600
S		 2265 tmp_mask = (mask_p[30] << 28)
2266 | (mask_p[29] << 26) | (mask_p[28] << 24)
2267 | (mask_p[27] << 22) | (mask_p[26] << 20)
2268 | (mask_p[25] << 18) | (mask_p[24] << 16)
2269 | (mask_p[23] << 14) | (mask_p[22] << 12)
2270 | (mask_p[21] << 10) | (mask_p[20] << 8)
2271 | (mask_p[19] << 6) | (mask_p[18] << 4)
2272 | (mask_p[17] << 2) | (mask_p[16] << 0);
2273 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2274 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2275
f1dc5600
S		 2276 tmp_mask = (mask_p[45] << 28)
2277 | (mask_p[44] << 26) | (mask_p[43] << 24)
2278 | (mask_p[42] << 22) | (mask_p[41] << 20)
2279 | (mask_p[40] << 18) | (mask_p[39] << 16)
2280 | (mask_p[38] << 14) | (mask_p[37] << 12)
2281 | (mask_p[36] << 10) | (mask_p[35] << 8)
2282 | (mask_p[34] << 6) | (mask_p[33] << 4)
2283 | (mask_p[32] << 2) | (mask_p[31] << 0);
2284 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2285 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2286
f1dc5600
S		 2287 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2288 | (mask_p[59] << 26) | (mask_p[58] << 24)
2289 | (mask_p[57] << 22) | (mask_p[56] << 20)
2290 | (mask_p[55] << 18) | (mask_p[54] << 16)
2291 | (mask_p[53] << 14) | (mask_p[52] << 12)
2292 | (mask_p[51] << 10) | (mask_p[50] << 8)
2293 | (mask_p[49] << 6) | (mask_p[48] << 4)
2294 | (mask_p[47] << 2) | (mask_p[46] << 0);
2295 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2296 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2297}
2298
3b319aae
JB		 2299static void ath9k_enable_rfkill(struct ath_hw *ah)
2300{
2301 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2302 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2303
2304 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2305 AR_GPIO_INPUT_MUX2_RFSILENT);
2306
2307 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2308 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2309}
2310
cbe61d8a 2311int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 2312 bool bChannelChange)
f078f209 2313{
1510718d 2314 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2315 u32 saveLedState;
ae8d2858 2316 struct ath_softc *sc = ah->ah_sc;
2660b81a 2317 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 2318 u32 saveDefAntenna;
2319 u32 macStaId1;
46fe782c 2320 u64 tsf = 0;
ae8d2858 2321 int i, rx_chainmask, r;
f078f209 2322
2660b81a
S		 2323 ah->extprotspacing = sc->ht_extprotspacing;
2324 ah->txchainmask = sc->tx_chainmask;
2325 ah->rxchainmask = sc->rx_chainmask;
f078f209 2326
9ecdef4b 2327 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 2328 return -EIO;
f078f209 2329
9ebef799 2330 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 2331 ath9k_hw_getnf(ah, curchan);
2332
2333 if (bChannelChange &&
2660b81a
S		 2334 (ah->chip_fullsleep != true) &&
2335 (ah->curchan != NULL) &&
2336 (chan->channel != ah->curchan->channel) &&
f078f209 2337 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 2338 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
0a475cc6
VT		 2339 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2340 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
f078f209 2341
ae8d2858 2342 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2660b81a 2343 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 2344 ath9k_hw_start_nfcal(ah);
ae8d2858 2345 return 0;
f078f209
LR		 2346 }
2347 }
2348
2349 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2350 if (saveDefAntenna == 0)
2351 saveDefAntenna = 1;
2352
2353 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2354
46fe782c
S		 2355 /* For chips on which RTC reset is done, save TSF before it gets cleared */
2356 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2357 tsf = ath9k_hw_gettsf64(ah);
2358
f078f209
LR		 2359 saveLedState = REG_READ(ah, AR_CFG_LED) &
2360 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2361 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2362
2363 ath9k_hw_mark_phy_inactive(ah);
2364
d7e7d229
LR		 2365 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2366 REG_WRITE(ah,
2367 AR9271_RESET_POWER_DOWN_CONTROL,
2368 AR9271_RADIO_RF_RST);
2369 udelay(50);
2370 }
2371
f078f209 2372 if (!ath9k_hw_chip_reset(ah, chan)) {
4d6b228d 2373 DPRINTF(ah, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 2374 return -EINVAL;
f078f209
LR		 2375 }
2376
d7e7d229
LR		 2377 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2378 ah->htc_reset_init = false;
2379 REG_WRITE(ah,
2380 AR9271_RESET_POWER_DOWN_CONTROL,
2381 AR9271_GATE_MAC_CTL);
2382 udelay(50);
2383 }
2384
46fe782c
S		 2385 /* Restore TSF */
2386 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2387 ath9k_hw_settsf64(ah, tsf);
2388
369391db
VT		 2389 if (AR_SREV_9280_10_OR_LATER(ah))
2390 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 2391
326bebbc 2392 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2393 /* Enable ASYNC FIFO */
2394 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2395 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2396 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2397 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2398 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2399 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2400 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2401 }
ae8d2858
LR		 2402 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2403 if (r)
2404 return r;
f078f209 2405
0ced0e17
JM		 2406 /* Setup MFP options for CCMP */
2407 if (AR_SREV_9280_20_OR_LATER(ah)) {
2408 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2409 * frames when constructing CCMP AAD. */
2410 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2411 0xc7ff);
2412 ah->sw_mgmt_crypto = false;
2413 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2414 /* Disable hardware crypto for management frames */
2415 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2416 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2417 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2418 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2419 ah->sw_mgmt_crypto = true;
2420 } else
2421 ah->sw_mgmt_crypto = true;
2422
f078f209
LR		 2423 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2424 ath9k_hw_set_delta_slope(ah, chan);
2425
2426 if (AR_SREV_9280_10_OR_LATER(ah))
2427 ath9k_hw_9280_spur_mitigate(ah, chan);
2428 else
2429 ath9k_hw_spur_mitigate(ah, chan);
2430
d6509151 2431 ah->eep_ops->set_board_values(ah, chan);
f078f209
LR		 2432
2433 ath9k_hw_decrease_chain_power(ah, chan);
2434
1510718d
LR		 2435 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2436 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 2437 | macStaId1
2438 | AR_STA_ID1_RTS_USE_DEF
2660b81a 2439 | (ah->config.
60b67f51 2440 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 2441 | ah->sta_id1_defaults);
2442 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2443
13b81559 2444 ath_hw_setbssidmask(common);
f078f209
LR		 2445
2446 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2447
3453ad88 2448 ath9k_hw_write_associd(ah);
f078f209
LR		 2449
2450 REG_WRITE(ah, AR_ISR, ~0);
2451
2452 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2453
8fbff4b8
VT		 2454 if (AR_SREV_9280_10_OR_LATER(ah))
2455 ath9k_hw_ar9280_set_channel(ah, chan);
2456 else
ae8d2858
LR		 2457 if (!(ath9k_hw_set_channel(ah, chan)))
2458 return -EIO;
f078f209
LR		 2459
2460 for (i = 0; i < AR_NUM_DCU; i++)
2461 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2462
2660b81a
S		 2463 ah->intr_txqs = 0;
2464 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 2465 ath9k_hw_resettxqueue(ah, i);
2466
2660b81a 2467 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 2468 ath9k_hw_init_qos(ah);
2469
2660b81a 2470 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 2471 ath9k_enable_rfkill(ah);
3b319aae 2472
f078f209
LR		 2473 ath9k_hw_init_user_settings(ah);
2474
326bebbc 2475 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2476 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2477 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2478 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2479 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2480 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2481 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2482
2483 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2484 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2485
2486 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2487 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2488 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2489 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2490 }
326bebbc 2491 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2492 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2493 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2494 }
2495
f078f209
LR		 2496 REG_WRITE(ah, AR_STA_ID1,
2497 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2498
2499 ath9k_hw_set_dma(ah);
2500
2501 REG_WRITE(ah, AR_OBS, 8);
2502
0ef1f168 2503 if (ah->config.intr_mitigation) {
f078f209
LR		 2504 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2505 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2506 }
2507
2508 ath9k_hw_init_bb(ah, chan);
2509
ae8d2858 2510 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2511 return -EIO;
f078f209 2512
2660b81a 2513 rx_chainmask = ah->rxchainmask;
f078f209
LR		 2514 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2515 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2516 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2517 }
2518
2519 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2520
d7e7d229
LR		 2521 /*
2522 * For big endian systems turn on swapping for descriptors
2523 */
f078f209
LR		 2524 if (AR_SREV_9100(ah)) {
2525 u32 mask;
2526 mask = REG_READ(ah, AR_CFG);
2527 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
4d6b228d 2528 DPRINTF(ah, ATH_DBG_RESET,
04bd4638 2529 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2530 } else {
2531 mask =
2532 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2533 REG_WRITE(ah, AR_CFG, mask);
4d6b228d 2534 DPRINTF(ah, ATH_DBG_RESET,
04bd4638 2535 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2536 }
2537 } else {
d7e7d229
LR		 2538 /* Configure AR9271 target WLAN */
2539 if (AR_SREV_9271(ah))
2540 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 2541#ifdef __BIG_ENDIAN
d7e7d229
LR		 2542 else
2543 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 2544#endif
2545 }
2546
766ec4a9 2547 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 2548 ath9k_hw_btcoex_enable(ah);
2549
ae8d2858 2550 return 0;
f078f209
LR		 2551}
2552
f1dc5600
S		 2553/************************/
2554/* Key Cache Management */
2555/************************/
f078f209 2556
cbe61d8a 2557bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 2558{
f1dc5600 2559 u32 keyType;
f078f209 2560
2660b81a 2561 if (entry >= ah->caps.keycache_size) {
4d6b228d 2562 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939 2563 "keychache entry %u out of range\n", entry);
f078f209
LR		 2564 return false;
2565 }
2566
f1dc5600 2567 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2568
f1dc5600
S		 2569 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2570 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2571 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2572 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2573 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2574 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2575 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2576 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2577
f1dc5600
S		 2578 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2579 u16 micentry = entry + 64;
f078f209 2580
f1dc5600
S		 2581 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2582 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2583 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2584 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2585
f078f209
LR		 2586 }
2587
f078f209
LR		 2588 return true;
2589}
2590
cbe61d8a 2591bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 2592{
f1dc5600 2593 u32 macHi, macLo;
f078f209 2594
2660b81a 2595 if (entry >= ah->caps.keycache_size) {
4d6b228d 2596 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939 2597 "keychache entry %u out of range\n", entry);
f1dc5600 2598 return false;
f078f209
LR		 2599 }
2600
f1dc5600
S		 2601 if (mac != NULL) {
2602 macHi = (mac[5] << 8) | mac[4];
2603 macLo = (mac[3] << 24) |
2604 (mac[2] << 16) |
2605 (mac[1] << 8) |
2606 mac[0];
2607 macLo >>= 1;
2608 macLo |= (macHi & 1) << 31;
2609 macHi >>= 1;
f078f209 2610 } else {
f1dc5600 2611 macLo = macHi = 0;
f078f209 2612 }
f1dc5600
S		 2613 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2614 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2615
f1dc5600 2616 return true;
f078f209
LR		 2617}
2618
cbe61d8a 2619bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 2620 const struct ath9k_keyval *k,
e0caf9ea 2621 const u8 *mac)
f078f209 2622{
2660b81a 2623 const struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600
S		 2624 u32 key0, key1, key2, key3, key4;
2625 u32 keyType;
f078f209 2626
f1dc5600 2627 if (entry >= pCap->keycache_size) {
4d6b228d 2628 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939 2629 "keycache entry %u out of range\n", entry);
f1dc5600 2630 return false;
f078f209
LR		 2631 }
2632
f1dc5600
S		 2633 switch (k->kv_type) {
2634 case ATH9K_CIPHER_AES_OCB:
2635 keyType = AR_KEYTABLE_TYPE_AES;
2636 break;
2637 case ATH9K_CIPHER_AES_CCM:
2638 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
4d6b228d 2639 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 2640 "AES-CCM not supported by mac rev 0x%x\n",
d535a42a 2641 ah->hw_version.macRev);
f1dc5600
S		 2642 return false;
2643 }
2644 keyType = AR_KEYTABLE_TYPE_CCM;
2645 break;
2646 case ATH9K_CIPHER_TKIP:
2647 keyType = AR_KEYTABLE_TYPE_TKIP;
2648 if (ATH9K_IS_MIC_ENABLED(ah)
2649 && entry + 64 >= pCap->keycache_size) {
4d6b228d 2650 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 2651 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2652 return false;
2653 }
2654 break;
2655 case ATH9K_CIPHER_WEP:
e31a16d6 2656 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
4d6b228d 2657 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 2658 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2659 return false;
2660 }
e31a16d6 2661 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 2662 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 2663 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 2664 keyType = AR_KEYTABLE_TYPE_104;
2665 else
2666 keyType = AR_KEYTABLE_TYPE_128;
2667 break;
2668 case ATH9K_CIPHER_CLR:
2669 keyType = AR_KEYTABLE_TYPE_CLR;
2670 break;
2671 default:
4d6b228d 2672 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 2673 "cipher %u not supported\n", k->kv_type);
f1dc5600 2674 return false;
f078f209
LR		 2675 }
2676
e0caf9ea
JM		 2677 key0 = get_unaligned_le32(k->kv_val + 0);
2678 key1 = get_unaligned_le16(k->kv_val + 4);
2679 key2 = get_unaligned_le32(k->kv_val + 6);
2680 key3 = get_unaligned_le16(k->kv_val + 10);
2681 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 2682 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 2683 key4 &= 0xff;
f078f209 2684
672903b3
JM		 2685 /*
2686 * Note: Key cache registers access special memory area that requires
2687 * two 32-bit writes to actually update the values in the internal
2688 * memory. Consequently, the exact order and pairs used here must be
2689 * maintained.
2690 */
2691
f1dc5600
S		 2692 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2693 u16 micentry = entry + 64;
f078f209 2694
672903b3
JM		 2695 /*
2696 * Write inverted key[47:0] first to avoid Michael MIC errors
2697 * on frames that could be sent or received at the same time.
2698 * The correct key will be written in the end once everything
2699 * else is ready.
2700 */
f1dc5600
S		 2701 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2702 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 2703
2704 /* Write key[95:48] */
f1dc5600
S		 2705 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2706 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2707
2708 /* Write key[127:96] and key type */
f1dc5600
S		 2709 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2710 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 2711
2712 /* Write MAC address for the entry */
f1dc5600 2713 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2714
2660b81a 2715 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 2716 /*
2717 * TKIP uses two key cache entries:
2718 * Michael MIC TX/RX keys in the same key cache entry
2719 * (idx = main index + 64):
2720 * key0 [31:0] = RX key [31:0]
2721 * key1 [15:0] = TX key [31:16]
2722 * key1 [31:16] = reserved
2723 * key2 [31:0] = RX key [63:32]
2724 * key3 [15:0] = TX key [15:0]
2725 * key3 [31:16] = reserved
2726 * key4 [31:0] = TX key [63:32]
2727 */
f1dc5600 2728 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2729
f1dc5600
S		 2730 mic0 = get_unaligned_le32(k->kv_mic + 0);
2731 mic2 = get_unaligned_le32(k->kv_mic + 4);
2732 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2733 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2734 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 2735
2736 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 2737 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2738 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 2739
2740 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 2741 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2742 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 2743
2744 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2745 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2746 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2747 AR_KEYTABLE_TYPE_CLR);
f078f209 2748
f1dc5600 2749 } else {
672903b3
JM		 2750 /*
2751 * TKIP uses four key cache entries (two for group
2752 * keys):
2753 * Michael MIC TX/RX keys are in different key cache
2754 * entries (idx = main index + 64 for TX and
2755 * main index + 32 + 96 for RX):
2756 * key0 [31:0] = TX/RX MIC key [31:0]
2757 * key1 [31:0] = reserved
2758 * key2 [31:0] = TX/RX MIC key [63:32]
2759 * key3 [31:0] = reserved
2760 * key4 [31:0] = reserved
2761 *
2762 * Upper layer code will call this function separately
2763 * for TX and RX keys when these registers offsets are
2764 * used.
2765 */
f1dc5600 2766 u32 mic0, mic2;
f078f209 2767
f1dc5600
S		 2768 mic0 = get_unaligned_le32(k->kv_mic + 0);
2769 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 2770
2771 /* Write MIC key[31:0] */
f1dc5600
S		 2772 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2773 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 2774
2775 /* Write MIC key[63:32] */
f1dc5600
S		 2776 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2777 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 2778
2779 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2780 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2781 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2782 AR_KEYTABLE_TYPE_CLR);
2783 }
672903b3
JM		 2784
2785 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 2786 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2787 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 2788
2789 /*
2790 * Write the correct (un-inverted) key[47:0] last to enable
2791 * TKIP now that all other registers are set with correct
2792 * values.
2793 */
f1dc5600
S		 2794 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2795 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2796 } else {
672903b3 2797 /* Write key[47:0] */
f1dc5600
S		 2798 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2799 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 2800
2801 /* Write key[95:48] */
f1dc5600
S		 2802 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2803 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2804
2805 /* Write key[127:96] and key type */
f1dc5600
S		 2806 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2807 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2808
672903b3 2809 /* Write MAC address for the entry */
f1dc5600
S		 2810 (void) ath9k_hw_keysetmac(ah, entry, mac);
2811 }
f078f209 2812
f078f209
LR		 2813 return true;
2814}
2815
cbe61d8a 2816bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 2817{
2660b81a 2818 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 2819 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2820 if (val & AR_KEYTABLE_VALID)
2821 return true;
2822 }
2823 return false;
f078f209
LR		 2824}
2825
f1dc5600
S		 2826/******************************/
2827/* Power Management (Chipset) */
2828/******************************/
2829
cbe61d8a 2830static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2831{
f1dc5600
S		 2832 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2833 if (setChip) {
2834 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2835 AR_RTC_FORCE_WAKE_EN);
2836 if (!AR_SREV_9100(ah))
2837 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2838
d03a66c1 2839 REG_CLR_BIT(ah, (AR_RTC_RESET),
f1dc5600
S		 2840 AR_RTC_RESET_EN);
2841 }
f078f209
LR		 2842}
2843
cbe61d8a 2844static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2845{
f1dc5600
S		 2846 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2847 if (setChip) {
2660b81a 2848 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2849
f1dc5600
S		 2850 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2851 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2852 AR_RTC_FORCE_WAKE_ON_INT);
2853 } else {
2854 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2855 AR_RTC_FORCE_WAKE_EN);
f078f209 2856 }
f078f209 2857 }
f078f209
LR		 2858}
2859
cbe61d8a 2860static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2861{
f1dc5600
S		 2862 u32 val;
2863 int i;
f078f209 2864
f1dc5600
S		 2865 if (setChip) {
2866 if ((REG_READ(ah, AR_RTC_STATUS) &
2867 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2868 if (ath9k_hw_set_reset_reg(ah,
2869 ATH9K_RESET_POWER_ON) != true) {
2870 return false;
2871 }
2872 }
2873 if (AR_SREV_9100(ah))
2874 REG_SET_BIT(ah, AR_RTC_RESET,
2875 AR_RTC_RESET_EN);
f078f209 2876
f1dc5600
S		 2877 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2878 AR_RTC_FORCE_WAKE_EN);
2879 udelay(50);
f078f209 2880
f1dc5600
S		 2881 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2882 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2883 if (val == AR_RTC_STATUS_ON)
2884 break;
2885 udelay(50);
2886 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2887 AR_RTC_FORCE_WAKE_EN);
f078f209 2888 }
f1dc5600 2889 if (i == 0) {
4d6b228d 2890 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 2891 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
f1dc5600 2892 return false;
f078f209 2893 }
f078f209
LR		 2894 }
2895
f1dc5600 2896 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2897
f1dc5600 2898 return true;
f078f209
LR		 2899}
2900
9ecdef4b 2901bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2902{
cbe61d8a 2903 int status = true, setChip = true;
f1dc5600
S		 2904 static const char *modes[] = {
2905 "AWAKE",
2906 "FULL-SLEEP",
2907 "NETWORK SLEEP",
2908 "UNDEFINED"
2909 };
f1dc5600 2910
cbdec975
GJ		 2911 if (ah->power_mode == mode)
2912 return status;
2913
4d6b228d 2914 DPRINTF(ah, ATH_DBG_RESET, "%s -> %s\n",
d8baa939 2915 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2916
2917 switch (mode) {
2918 case ATH9K_PM_AWAKE:
2919 status = ath9k_hw_set_power_awake(ah, setChip);
2920 break;
2921 case ATH9K_PM_FULL_SLEEP:
2922 ath9k_set_power_sleep(ah, setChip);
2660b81a 2923 ah->chip_fullsleep = true;
f1dc5600
S		 2924 break;
2925 case ATH9K_PM_NETWORK_SLEEP:
2926 ath9k_set_power_network_sleep(ah, setChip);
2927 break;
f078f209 2928 default:
4d6b228d 2929 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 2930 "Unknown power mode %u\n", mode);
f078f209
LR		 2931 return false;
2932 }
2660b81a 2933 ah->power_mode = mode;
f1dc5600
S		 2934
2935 return status;
f078f209
LR		 2936}
2937
24c1a280
LR		 2938/*
2939 * Helper for ASPM support.
2940 *
2941 * Disable PLL when in L0s as well as receiver clock when in L1.
2942 * This power saving option must be enabled through the SerDes.
2943 *
2944 * Programming the SerDes must go through the same 288 bit serial shift
2945 * register as the other analog registers. Hence the 9 writes.
2946 */
93b1b37f 2947void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
f078f209 2948{
f1dc5600 2949 u8 i;
93b1b37f 2950 u32 val;
f078f209 2951
2660b81a 2952 if (ah->is_pciexpress != true)
f1dc5600 2953 return;
f078f209 2954
24c1a280 2955 /* Do not touch SerDes registers */
2660b81a 2956 if (ah->config.pcie_powersave_enable == 2)
f1dc5600
S		 2957 return;
2958
24c1a280 2959 /* Nothing to do on restore for 11N */
93b1b37f
VN		 2960 if (!restore) {
2961 if (AR_SREV_9280_20_OR_LATER(ah)) {
2962 /*
2963 * AR9280 2.0 or later chips use SerDes values from the
2964 * initvals.h initialized depending on chipset during
2965 * ath9k_hw_init()
2966 */
2967 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2968 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2969 INI_RA(&ah->iniPcieSerdes, i, 1));
2970 }
2971 } else if (AR_SREV_9280(ah) &&
2972 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2973 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2974 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2975
2976 /* RX shut off when elecidle is asserted */
2977 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2978 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2979 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2980
2981 /* Shut off CLKREQ active in L1 */
2982 if (ah->config.pcie_clock_req)
2983 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2984 else
2985 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
f1dc5600 2986
93b1b37f
VN		 2987 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2988 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2989 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
f1dc5600 2990
93b1b37f
VN		 2991 /* Load the new settings */
2992 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f1dc5600 2993
93b1b37f
VN		 2994 } else {
2995 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2996 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
f1dc5600 2997
93b1b37f
VN		 2998 /* RX shut off when elecidle is asserted */
2999 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3000 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3001 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
f1dc5600 3002
93b1b37f
VN		 3003 /*
3004 * Ignore ah->ah_config.pcie_clock_req setting for
3005 * pre-AR9280 11n
3006 */
3007 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
24c1a280 3008
93b1b37f
VN		 3009 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3010 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3011 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
24c1a280 3012
93b1b37f
VN		 3013 /* Load the new settings */
3014 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3015 }
24c1a280 3016
93b1b37f 3017 udelay(1000);
24c1a280 3018
93b1b37f
VN		 3019 /* set bit 19 to allow forcing of pcie core into L1 state */
3020 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
f078f209 3021
93b1b37f
VN		 3022 /* Several PCIe massages to ensure proper behaviour */
3023 if (ah->config.pcie_waen) {
3024 val = ah->config.pcie_waen;
3025 if (!power_off)
3026 val &= (~AR_WA_D3_L1_DISABLE);
3027 } else {
3028 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3029 AR_SREV_9287(ah)) {
3030 val = AR9285_WA_DEFAULT;
3031 if (!power_off)
3032 val &= (~AR_WA_D3_L1_DISABLE);
3033 } else if (AR_SREV_9280(ah)) {
3034 /*
3035 * On AR9280 chips bit 22 of 0x4004 needs to be
3036 * set otherwise card may disappear.
3037 */
3038 val = AR9280_WA_DEFAULT;
3039 if (!power_off)
3040 val &= (~AR_WA_D3_L1_DISABLE);
3041 } else
3042 val = AR_WA_DEFAULT;
3043 }
6d08b9b9 3044
93b1b37f
VN		 3045 REG_WRITE(ah, AR_WA, val);
3046 }
f1dc5600 3047
93b1b37f 3048 if (power_off) {
24c1a280 3049 /*
93b1b37f
VN		 3050 * Set PCIe workaround bits
3051 * bit 14 in WA register (disable L1) should only
3052 * be set when device enters D3 and be cleared
3053 * when device comes back to D0.
24c1a280 3054 */
93b1b37f
VN		 3055 if (ah->config.pcie_waen) {
3056 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
3057 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3058 } else {
3059 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3060 AR_SREV_9287(ah)) &&
3061 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
3062 (AR_SREV_9280(ah) &&
3063 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
3064 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3065 }
3066 }
f1dc5600 3067 }
f078f209
LR		 3068}
3069
f1dc5600
S		 3070/**********************/
3071/* Interrupt Handling */
3072/**********************/
3073
cbe61d8a 3074bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 3075{
3076 u32 host_isr;
3077
3078 if (AR_SREV_9100(ah))
3079 return true;
3080
3081 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3082 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3083 return true;
3084
3085 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3086 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3087 && (host_isr != AR_INTR_SPURIOUS))
3088 return true;
3089
3090 return false;
3091}
3092
cbe61d8a 3093bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 3094{
3095 u32 isr = 0;
3096 u32 mask2 = 0;
2660b81a 3097 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 3098 u32 sync_cause = 0;
3099 bool fatal_int = false;
3100
3101 if (!AR_SREV_9100(ah)) {
3102 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3103 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3104 == AR_RTC_STATUS_ON) {
3105 isr = REG_READ(ah, AR_ISR);
3106 }
3107 }
3108
f1dc5600
S		 3109 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3110 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 3111
3112 *masked = 0;
3113
3114 if (!isr && !sync_cause)
3115 return false;
3116 } else {
3117 *masked = 0;
3118 isr = REG_READ(ah, AR_ISR);
3119 }
3120
3121 if (isr) {
f078f209
LR		 3122 if (isr & AR_ISR_BCNMISC) {
3123 u32 isr2;
3124 isr2 = REG_READ(ah, AR_ISR_S2);
3125 if (isr2 & AR_ISR_S2_TIM)
3126 mask2 |= ATH9K_INT_TIM;
3127 if (isr2 & AR_ISR_S2_DTIM)
3128 mask2 |= ATH9K_INT_DTIM;
3129 if (isr2 & AR_ISR_S2_DTIMSYNC)
3130 mask2 |= ATH9K_INT_DTIMSYNC;
3131 if (isr2 & (AR_ISR_S2_CABEND))
3132 mask2 |= ATH9K_INT_CABEND;
3133 if (isr2 & AR_ISR_S2_GTT)
3134 mask2 |= ATH9K_INT_GTT;
3135 if (isr2 & AR_ISR_S2_CST)
3136 mask2 |= ATH9K_INT_CST;
4af9cf4f
S		 3137 if (isr2 & AR_ISR_S2_TSFOOR)
3138 mask2 |= ATH9K_INT_TSFOOR;
f078f209
LR		 3139 }
3140
3141 isr = REG_READ(ah, AR_ISR_RAC);
3142 if (isr == 0xffffffff) {
3143 *masked = 0;
3144 return false;
3145 }
3146
3147 *masked = isr & ATH9K_INT_COMMON;
3148
0ef1f168 3149 if (ah->config.intr_mitigation) {
f078f209
LR		 3150 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3151 *masked |= ATH9K_INT_RX;
3152 }
3153
3154 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3155 *masked |= ATH9K_INT_RX;
3156 if (isr &
3157 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3158 AR_ISR_TXEOL)) {
3159 u32 s0_s, s1_s;
3160
3161 *masked |= ATH9K_INT_TX;
3162
3163 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 3164 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3165 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 3166
3167 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 3168 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3169 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 3170 }
3171
3172 if (isr & AR_ISR_RXORN) {
4d6b228d 3173 DPRINTF(ah, ATH_DBG_INTERRUPT,
04bd4638 3174 "receive FIFO overrun interrupt\n");
f078f209
LR		 3175 }
3176
3177 if (!AR_SREV_9100(ah)) {
60b67f51 3178 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3179 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3180 if (isr5 & AR_ISR_S5_TIM_TIMER)
3181 *masked |= ATH9K_INT_TIM_TIMER;
3182 }
3183 }
3184
3185 *masked |= mask2;
3186 }
f1dc5600 3187
f078f209
LR		 3188 if (AR_SREV_9100(ah))
3189 return true;
f1dc5600 3190
ff155a45
VT		 3191 if (isr & AR_ISR_GENTMR) {
3192 u32 s5_s;
3193
3194 s5_s = REG_READ(ah, AR_ISR_S5_S);
3195 if (isr & AR_ISR_GENTMR) {
3196 ah->intr_gen_timer_trigger =
3197 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3198
3199 ah->intr_gen_timer_thresh =
3200 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3201
3202 if (ah->intr_gen_timer_trigger)
3203 *masked |= ATH9K_INT_GENTIMER;
3204
3205 }
3206 }
3207
f078f209
LR		 3208 if (sync_cause) {
3209 fatal_int =
3210 (sync_cause &
3211 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3212 ? true : false;
3213
3214 if (fatal_int) {
3215 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
4d6b228d 3216 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 3217 "received PCI FATAL interrupt\n");
f078f209
LR		 3218 }
3219 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
4d6b228d 3220 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 3221 "received PCI PERR interrupt\n");
f078f209 3222 }
a89bff9a 3223 *masked |= ATH9K_INT_FATAL;
f078f209
LR		 3224 }
3225 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
4d6b228d 3226 DPRINTF(ah, ATH_DBG_INTERRUPT,
04bd4638 3227 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 3228 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3229 REG_WRITE(ah, AR_RC, 0);
3230 *masked |= ATH9K_INT_FATAL;
3231 }
3232 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
4d6b228d 3233 DPRINTF(ah, ATH_DBG_INTERRUPT,
04bd4638 3234 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 3235 }
3236
3237 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3238 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3239 }
f1dc5600 3240
f078f209
LR		 3241 return true;
3242}
3243
cbe61d8a 3244enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 3245{
2660b81a 3246 u32 omask = ah->mask_reg;
f078f209 3247 u32 mask, mask2;
2660b81a 3248 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 3249
4d6b228d 3250 DPRINTF(ah, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 3251
3252 if (omask & ATH9K_INT_GLOBAL) {
4d6b228d 3253 DPRINTF(ah, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 3254 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3255 (void) REG_READ(ah, AR_IER);
3256 if (!AR_SREV_9100(ah)) {
3257 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3258 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3259
3260 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3261 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3262 }
3263 }
3264
3265 mask = ints & ATH9K_INT_COMMON;
3266 mask2 = 0;
3267
3268 if (ints & ATH9K_INT_TX) {
2660b81a 3269 if (ah->txok_interrupt_mask)
f078f209 3270 mask |= AR_IMR_TXOK;
2660b81a 3271 if (ah->txdesc_interrupt_mask)
f078f209 3272 mask |= AR_IMR_TXDESC;
2660b81a 3273 if (ah->txerr_interrupt_mask)
f078f209 3274 mask |= AR_IMR_TXERR;
2660b81a 3275 if (ah->txeol_interrupt_mask)
f078f209
LR		 3276 mask |= AR_IMR_TXEOL;
3277 }
3278 if (ints & ATH9K_INT_RX) {
3279 mask |= AR_IMR_RXERR;
0ef1f168 3280 if (ah->config.intr_mitigation)
f078f209
LR		 3281 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3282 else
3283 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 3284 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 3285 mask |= AR_IMR_GENTMR;
3286 }
3287
3288 if (ints & (ATH9K_INT_BMISC)) {
3289 mask |= AR_IMR_BCNMISC;
3290 if (ints & ATH9K_INT_TIM)
3291 mask2 |= AR_IMR_S2_TIM;
3292 if (ints & ATH9K_INT_DTIM)
3293 mask2 |= AR_IMR_S2_DTIM;
3294 if (ints & ATH9K_INT_DTIMSYNC)
3295 mask2 |= AR_IMR_S2_DTIMSYNC;
3296 if (ints & ATH9K_INT_CABEND)
4af9cf4f
S		 3297 mask2 |= AR_IMR_S2_CABEND;
3298 if (ints & ATH9K_INT_TSFOOR)
3299 mask2 |= AR_IMR_S2_TSFOOR;
f078f209
LR		 3300 }
3301
3302 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3303 mask |= AR_IMR_BCNMISC;
3304 if (ints & ATH9K_INT_GTT)
3305 mask2 |= AR_IMR_S2_GTT;
3306 if (ints & ATH9K_INT_CST)
3307 mask2 |= AR_IMR_S2_CST;
3308 }
3309
4d6b228d 3310 DPRINTF(ah, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 3311 REG_WRITE(ah, AR_IMR, mask);
3312 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3313 AR_IMR_S2_DTIM |
3314 AR_IMR_S2_DTIMSYNC |
3315 AR_IMR_S2_CABEND |
3316 AR_IMR_S2_CABTO |
3317 AR_IMR_S2_TSFOOR |
3318 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3319 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2660b81a 3320 ah->mask_reg = ints;
f078f209 3321
60b67f51 3322 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3323 if (ints & ATH9K_INT_TIM_TIMER)
3324 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3325 else
3326 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3327 }
3328
3329 if (ints & ATH9K_INT_GLOBAL) {
4d6b228d 3330 DPRINTF(ah, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 3331 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3332 if (!AR_SREV_9100(ah)) {
3333 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3334 AR_INTR_MAC_IRQ);
3335 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3336
3337
3338 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3339 AR_INTR_SYNC_DEFAULT);
3340 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3341 AR_INTR_SYNC_DEFAULT);
3342 }
4d6b228d 3343 DPRINTF(ah, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
f078f209
LR		 3344 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3345 }
3346
3347 return omask;
3348}
3349
f1dc5600
S		 3350/*******************/
3351/* Beacon Handling */
3352/*******************/
3353
cbe61d8a 3354void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 3355{
f078f209
LR		 3356 int flags = 0;
3357
2660b81a 3358 ah->beacon_interval = beacon_period;
f078f209 3359
2660b81a 3360 switch (ah->opmode) {
d97809db
CM		 3361 case NL80211_IFTYPE_STATION:
3362 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 3363 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3364 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3365 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3366 flags |= AR_TBTT_TIMER_EN;
3367 break;
d97809db 3368 case NL80211_IFTYPE_ADHOC:
9cb5412b 3369 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 3370 REG_SET_BIT(ah, AR_TXCFG,
3371 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3372 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3373 TU_TO_USEC(next_beacon +
2660b81a
S		 3374 (ah->atim_window ? ah->
3375 atim_window : 1)));
f078f209 3376 flags |= AR_NDP_TIMER_EN;
d97809db 3377 case NL80211_IFTYPE_AP:
f078f209
LR		 3378 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3379 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3380 TU_TO_USEC(next_beacon -
2660b81a 3381 ah->config.
60b67f51 3382 dma_beacon_response_time));
f078f209
LR		 3383 REG_WRITE(ah, AR_NEXT_SWBA,
3384 TU_TO_USEC(next_beacon -
2660b81a 3385 ah->config.
60b67f51 3386 sw_beacon_response_time));
f078f209
LR		 3387 flags |=
3388 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3389 break;
d97809db 3390 default:
4d6b228d 3391 DPRINTF(ah, ATH_DBG_BEACON,
d97809db 3392 "%s: unsupported opmode: %d\n",
2660b81a 3393 __func__, ah->opmode);
d97809db
CM		 3394 return;
3395 break;
f078f209
LR		 3396 }
3397
3398 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3399 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3400 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3401 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3402
3403 beacon_period &= ~ATH9K_BEACON_ENA;
3404 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3405 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3406 ath9k_hw_reset_tsf(ah);
3407 }
3408
3409 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3410}
3411
cbe61d8a 3412void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 3413 const struct ath9k_beacon_state *bs)
f078f209
LR		 3414{
3415 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 3416 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 3417
3418 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3419
3420 REG_WRITE(ah, AR_BEACON_PERIOD,
3421 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3422 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3423 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3424
3425 REG_RMW_FIELD(ah, AR_RSSI_THR,
3426 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3427
3428 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3429
3430 if (bs->bs_sleepduration > beaconintval)
3431 beaconintval = bs->bs_sleepduration;
3432
3433 dtimperiod = bs->bs_dtimperiod;
3434 if (bs->bs_sleepduration > dtimperiod)
3435 dtimperiod = bs->bs_sleepduration;
3436
3437 if (beaconintval == dtimperiod)
3438 nextTbtt = bs->bs_nextdtim;
3439 else
3440 nextTbtt = bs->bs_nexttbtt;
3441
4d6b228d
LR		 3442 DPRINTF(ah, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3443 DPRINTF(ah, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3444 DPRINTF(ah, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3445 DPRINTF(ah, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3446
f1dc5600
S		 3447 REG_WRITE(ah, AR_NEXT_DTIM,
3448 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3449 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3450
f1dc5600
S		 3451 REG_WRITE(ah, AR_SLEEP1,
3452 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3453 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3454
f1dc5600
S		 3455 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3456 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3457 else
3458 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3459
f1dc5600
S		 3460 REG_WRITE(ah, AR_SLEEP2,
3461 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3462
f1dc5600
S		 3463 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3464 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3465
f1dc5600
S		 3466 REG_SET_BIT(ah, AR_TIMER_MODE,
3467 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3468 AR_DTIM_TIMER_EN);
f078f209 3469
4af9cf4f
S		 3470 /* TSF Out of Range Threshold */
3471 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209
LR		 3472}
3473
f1dc5600
S		 3474/*******************/
3475/* HW Capabilities */
3476/*******************/
3477
eef7a574 3478void ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 3479{
2660b81a 3480 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 3481 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
766ec4a9 3482 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 3483
f1dc5600 3484 u16 capField = 0, eeval;
f078f209 3485
f74df6fb 3486 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 3487 regulatory->current_rd = eeval;
f078f209 3488
f74df6fb 3489 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 3490 if (AR_SREV_9285_10_OR_LATER(ah))
3491 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 3492 regulatory->current_rd_ext = eeval;
f078f209 3493
f74df6fb 3494 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 3495
2660b81a 3496 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 3497 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 3498 if (regulatory->current_rd == 0x64 ||
3499 regulatory->current_rd == 0x65)
3500 regulatory->current_rd += 5;
3501 else if (regulatory->current_rd == 0x41)
3502 regulatory->current_rd = 0x43;
4d6b228d 3503 DPRINTF(ah, ATH_DBG_REGULATORY,
608b88cb 3504 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 3505 }
f078f209 3506
f74df6fb 3507 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
f1dc5600 3508 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3509
f1dc5600
S		 3510 if (eeval & AR5416_OPFLAGS_11A) {
3511 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 3512 if (ah->config.ht_enable) {
f1dc5600
S		 3513 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3514 set_bit(ATH9K_MODE_11NA_HT20,
3515 pCap->wireless_modes);
3516 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3517 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3518 pCap->wireless_modes);
3519 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3520 pCap->wireless_modes);
3521 }
f078f209 3522 }
f078f209
LR		 3523 }
3524
f1dc5600 3525 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 3526 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 3527 if (ah->config.ht_enable) {
f1dc5600
S		 3528 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3529 set_bit(ATH9K_MODE_11NG_HT20,
3530 pCap->wireless_modes);
3531 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3532 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3533 pCap->wireless_modes);
3534 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3535 pCap->wireless_modes);
3536 }
3537 }
f078f209 3538 }
f1dc5600 3539
f74df6fb 3540 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 3541 /*
3542 * For AR9271 we will temporarilly uses the rx chainmax as read from
3543 * the EEPROM.
3544 */
8147f5de 3545 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 3546 !(eeval & AR5416_OPFLAGS_11A) &&
3547 !(AR_SREV_9271(ah)))
3548 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 3549 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3550 else
d7e7d229 3551 /* Use rx_chainmask from EEPROM. */
8147f5de 3552 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 3553
d535a42a 3554 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 3555 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3556
f1dc5600
S		 3557 pCap->low_2ghz_chan = 2312;
3558 pCap->high_2ghz_chan = 2732;
f078f209 3559
f1dc5600
S		 3560 pCap->low_5ghz_chan = 4920;
3561 pCap->high_5ghz_chan = 6100;
f078f209 3562
f1dc5600
S		 3563 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3564 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3565 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3566
f1dc5600
S		 3567 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3568 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3569 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3570
2660b81a 3571 if (ah->config.ht_enable)
f1dc5600
S		 3572 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3573 else
3574 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3575
f1dc5600
S		 3576 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3577 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3578 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3579 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3580
f1dc5600
S		 3581 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3582 pCap->total_queues =
3583 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3584 else
3585 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3586
f1dc5600
S		 3587 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3588 pCap->keycache_size =
3589 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3590 else
3591 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3592
f1dc5600 3593 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f1dc5600 3594 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3595
cb33c412
SB		 3596 if (AR_SREV_9285_10_OR_LATER(ah))
3597 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3598 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3599 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3600 else
3601 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3602
f1dc5600
S		 3603 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3604 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3605 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3606 } else {
3607 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3608 }
3609
f1dc5600
S		 3610 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3611
e97275cb 3612#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 3613 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3614 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3615 ah->rfkill_gpio =
3616 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3617 ah->rfkill_polarity =
3618 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 3619
3620 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3621 }
f1dc5600 3622#endif
f078f209 3623
a3ca95fb 3624 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3625
e7594072 3626 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3627 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3628 else
3629 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3630
608b88cb 3631 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 3632 pCap->reg_cap =
3633 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3634 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3635 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3636 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3637 } else {
f1dc5600
S		 3638 pCap->reg_cap =
3639 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3640 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3641 }
f078f209 3642
f1dc5600
S		 3643 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3644
3645 pCap->num_antcfg_5ghz =
f74df6fb 3646 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3647 pCap->num_antcfg_2ghz =
f74df6fb 3648 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3649
fe12946e 3650 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 3651 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 3652 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3653 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 3654
8c8f9ba7 3655 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 3656 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3657 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 3658 } else {
766ec4a9 3659 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 3660 }
22f25d0d 3661 } else {
766ec4a9 3662 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 3663 }
f078f209
LR		 3664}
3665
cbe61d8a 3666bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3667 u32 capability, u32 *result)
f078f209 3668{
608b88cb 3669 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 3670 switch (type) {
3671 case ATH9K_CAP_CIPHER:
3672 switch (capability) {
3673 case ATH9K_CIPHER_AES_CCM:
3674 case ATH9K_CIPHER_AES_OCB:
3675 case ATH9K_CIPHER_TKIP:
3676 case ATH9K_CIPHER_WEP:
3677 case ATH9K_CIPHER_MIC:
3678 case ATH9K_CIPHER_CLR:
3679 return true;
3680 default:
3681 return false;
3682 }
3683 case ATH9K_CAP_TKIP_MIC:
3684 switch (capability) {
3685 case 0:
3686 return true;
3687 case 1:
2660b81a 3688 return (ah->sta_id1_defaults &
f1dc5600
S		 3689 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3690 false;
3691 }
3692 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 3693 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 3694 false : true;
f1dc5600
S		 3695 case ATH9K_CAP_DIVERSITY:
3696 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3697 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3698 true : false;
f1dc5600
S		 3699 case ATH9K_CAP_MCAST_KEYSRCH:
3700 switch (capability) {
3701 case 0:
3702 return true;
3703 case 1:
3704 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3705 return false;
3706 } else {
2660b81a 3707 return (ah->sta_id1_defaults &
f1dc5600
S		 3708 AR_STA_ID1_MCAST_KSRCH) ? true :
3709 false;
3710 }
3711 }
3712 return false;
f1dc5600
S		 3713 case ATH9K_CAP_TXPOW:
3714 switch (capability) {
3715 case 0:
3716 return 0;
3717 case 1:
608b88cb 3718 *result = regulatory->power_limit;
f1dc5600
S		 3719 return 0;
3720 case 2:
608b88cb 3721 *result = regulatory->max_power_level;
f1dc5600
S		 3722 return 0;
3723 case 3:
608b88cb 3724 *result = regulatory->tp_scale;
f1dc5600
S		 3725 return 0;
3726 }
3727 return false;
8bd1d07f
SB		 3728 case ATH9K_CAP_DS:
3729 return (AR_SREV_9280_20_OR_LATER(ah) &&
3730 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3731 ? false : true;
f1dc5600
S		 3732 default:
3733 return false;
f078f209 3734 }
f078f209
LR		 3735}
3736
cbe61d8a 3737bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3738 u32 capability, u32 setting, int *status)
f078f209 3739{
f1dc5600 3740 u32 v;
f078f209 3741
f1dc5600
S		 3742 switch (type) {
3743 case ATH9K_CAP_TKIP_MIC:
3744 if (setting)
2660b81a 3745 ah->sta_id1_defaults |=
f1dc5600
S		 3746 AR_STA_ID1_CRPT_MIC_ENABLE;
3747 else
2660b81a 3748 ah->sta_id1_defaults &=
f1dc5600
S		 3749 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3750 return true;
3751 case ATH9K_CAP_DIVERSITY:
3752 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3753 if (setting)
3754 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3755 else
3756 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3757 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3758 return true;
3759 case ATH9K_CAP_MCAST_KEYSRCH:
3760 if (setting)
2660b81a 3761 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3762 else
2660b81a 3763 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3764 return true;
f1dc5600
S		 3765 default:
3766 return false;
f078f209
LR		 3767 }
3768}
3769
f1dc5600
S		 3770/****************************/
3771/* GPIO / RFKILL / Antennae */
3772/****************************/
f078f209 3773
cbe61d8a 3774static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 3775 u32 gpio, u32 type)
3776{
3777 int addr;
3778 u32 gpio_shift, tmp;
f078f209 3779
f1dc5600
S		 3780 if (gpio > 11)
3781 addr = AR_GPIO_OUTPUT_MUX3;
3782 else if (gpio > 5)
3783 addr = AR_GPIO_OUTPUT_MUX2;
3784 else
3785 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3786
f1dc5600 3787 gpio_shift = (gpio % 6) * 5;
f078f209 3788
f1dc5600
S		 3789 if (AR_SREV_9280_20_OR_LATER(ah)
3790 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3791 REG_RMW(ah, addr, (type << gpio_shift),
3792 (0x1f << gpio_shift));
f078f209 3793 } else {
f1dc5600
S		 3794 tmp = REG_READ(ah, addr);
3795 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3796 tmp &= ~(0x1f << gpio_shift);
3797 tmp |= (type << gpio_shift);
3798 REG_WRITE(ah, addr, tmp);
f078f209 3799 }
f078f209
LR		 3800}
3801
cbe61d8a 3802void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 3803{
f1dc5600 3804 u32 gpio_shift;
f078f209 3805
2660b81a 3806 ASSERT(gpio < ah->caps.num_gpio_pins);
f078f209 3807
f1dc5600 3808 gpio_shift = gpio << 1;
f078f209 3809
f1dc5600
S		 3810 REG_RMW(ah,
3811 AR_GPIO_OE_OUT,
3812 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3813 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3814}
3815
cbe61d8a 3816u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 3817{
cb33c412
SB		 3818#define MS_REG_READ(x, y) \
3819 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3820
2660b81a 3821 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 3822 return 0xffffffff;
f078f209 3823
ac88b6ec
VN		 3824 if (AR_SREV_9287_10_OR_LATER(ah))
3825 return MS_REG_READ(AR9287, gpio) != 0;
3826 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 3827 return MS_REG_READ(AR9285, gpio) != 0;
3828 else if (AR_SREV_9280_10_OR_LATER(ah))
3829 return MS_REG_READ(AR928X, gpio) != 0;
3830 else
3831 return MS_REG_READ(AR, gpio) != 0;
f078f209
LR		 3832}
3833
cbe61d8a 3834void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 3835 u32 ah_signal_type)
f078f209 3836{
f1dc5600 3837 u32 gpio_shift;
f078f209 3838
f1dc5600 3839 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3840
f1dc5600 3841 gpio_shift = 2 * gpio;
f078f209 3842
f1dc5600
S		 3843 REG_RMW(ah,
3844 AR_GPIO_OE_OUT,
3845 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3846 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3847}
3848
cbe61d8a 3849void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 3850{
f1dc5600
S		 3851 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3852 AR_GPIO_BIT(gpio));
f078f209
LR		 3853}
3854
cbe61d8a 3855u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 3856{
f1dc5600 3857 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209
LR		 3858}
3859
cbe61d8a 3860void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 3861{
f1dc5600 3862 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209
LR		 3863}
3864
cbe61d8a 3865bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
f1dc5600
S		 3866 enum ath9k_ant_setting settings,
3867 struct ath9k_channel *chan,
3868 u8 *tx_chainmask,
3869 u8 *rx_chainmask,
3870 u8 *antenna_cfgd)
f078f209 3871{
f1dc5600 3872 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
f078f209 3873
f1dc5600
S		 3874 if (AR_SREV_9280(ah)) {
3875 if (!tx_chainmask_cfg) {
f078f209 3876
f1dc5600
S		 3877 tx_chainmask_cfg = *tx_chainmask;
3878 rx_chainmask_cfg = *rx_chainmask;
3879 }
f078f209 3880
f1dc5600
S		 3881 switch (settings) {
3882 case ATH9K_ANT_FIXED_A:
3883 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3884 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3885 *antenna_cfgd = true;
3886 break;
3887 case ATH9K_ANT_FIXED_B:
2660b81a 3888 if (ah->caps.tx_chainmask >
f1dc5600
S		 3889 ATH9K_ANTENNA1_CHAINMASK) {
3890 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3891 }
3892 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3893 *antenna_cfgd = true;
3894 break;
3895 case ATH9K_ANT_VARIABLE:
3896 *tx_chainmask = tx_chainmask_cfg;
3897 *rx_chainmask = rx_chainmask_cfg;
3898 *antenna_cfgd = true;
3899 break;
3900 default:
3901 break;
3902 }
3903 } else {
1cf6873a 3904 ah->config.diversity_control = settings;
f078f209 3905 }
f078f209 3906
f1dc5600 3907 return true;
f078f209
LR		 3908}
3909
f1dc5600
S		 3910/*********************/
3911/* General Operation */
3912/*********************/
3913
cbe61d8a 3914u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 3915{
f1dc5600
S		 3916 u32 bits = REG_READ(ah, AR_RX_FILTER);
3917 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3918
f1dc5600
S		 3919 if (phybits & AR_PHY_ERR_RADAR)
3920 bits |= ATH9K_RX_FILTER_PHYRADAR;
3921 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3922 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3923
f1dc5600 3924 return bits;
f078f209
LR		 3925}
3926
cbe61d8a 3927void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 3928{
f1dc5600 3929 u32 phybits;
f078f209 3930
7ea310be
S		 3931 REG_WRITE(ah, AR_RX_FILTER, bits);
3932
f1dc5600
S		 3933 phybits = 0;
3934 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3935 phybits |= AR_PHY_ERR_RADAR;
3936 if (bits & ATH9K_RX_FILTER_PHYERR)
3937 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3938 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3939
f1dc5600
S		 3940 if (phybits)
3941 REG_WRITE(ah, AR_RXCFG,
3942 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3943 else
3944 REG_WRITE(ah, AR_RXCFG,
3945 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3946}
f078f209 3947
cbe61d8a 3948bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600
S		 3949{
3950 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3951}
f078f209 3952
cbe61d8a 3953bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 3954{
9ecdef4b 3955 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 3956 return false;
f078f209 3957
f1dc5600 3958 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
f078f209
LR		 3959}
3960
8fbff4b8 3961void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 3962{
608b88cb 3963 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 3964 struct ath9k_channel *chan = ah->curchan;
5f8e077c 3965 struct ieee80211_channel *channel = chan->chan;
f078f209 3966
608b88cb 3967 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 3968
8fbff4b8 3969 ah->eep_ops->set_txpower(ah, chan,
608b88cb 3970 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 3971 channel->max_antenna_gain * 2,
3972 channel->max_power * 2,
3973 min((u32) MAX_RATE_POWER,
608b88cb 3974 (u32) regulatory->power_limit));
6f255425
LR		 3975}
3976
cbe61d8a 3977void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 3978{
1510718d 3979 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
f078f209
LR		 3980}
3981
cbe61d8a 3982void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 3983{
2660b81a 3984 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209
LR		 3985}
3986
cbe61d8a 3987void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 3988{
f1dc5600
S		 3989 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3990 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209
LR		 3991}
3992
f2b2143e 3993void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 3994{
1510718d
LR		 3995 struct ath_common *common = ath9k_hw_common(ah);
3996
3997 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3998 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3999 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 4000}
4001
cbe61d8a 4002u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 4003{
f1dc5600 4004 u64 tsf;
f078f209 4005
f1dc5600
S		 4006 tsf = REG_READ(ah, AR_TSF_U32);
4007 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 4008
f1dc5600
S		 4009 return tsf;
4010}
f078f209 4011
cbe61d8a 4012void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 4013{
27abe060 4014 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 4015 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060
AF		 4016}
4017
cbe61d8a 4018void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 4019{
f9b604f6
GJ		 4020 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4021 AH_TSF_WRITE_TIMEOUT))
4d6b228d 4022 DPRINTF(ah, ATH_DBG_RESET,
f9b604f6
GJ		 4023 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4024
f1dc5600
S		 4025 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4026}
f078f209 4027
54e4cec6 4028void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 4029{
f1dc5600 4030 if (setting)
2660b81a 4031 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 4032 else
2660b81a 4033 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 4034}
f078f209 4035
cbe61d8a 4036bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f1dc5600 4037{
f1dc5600 4038 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4d6b228d 4039 DPRINTF(ah, ATH_DBG_RESET, "bad slot time %u\n", us);
2660b81a 4040 ah->slottime = (u32) -1;
f1dc5600
S		 4041 return false;
4042 } else {
4043 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
2660b81a 4044 ah->slottime = us;
f1dc5600 4045 return true;
f078f209 4046 }
f1dc5600
S		 4047}
4048
cbe61d8a 4049void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
f1dc5600
S		 4050{
4051 u32 macmode;
4052
4053 if (mode == ATH9K_HT_MACMODE_2040 &&
2660b81a 4054 !ah->config.cwm_ignore_extcca)
f1dc5600
S		 4055 macmode = AR_2040_JOINED_RX_CLEAR;
4056 else
4057 macmode = 0;
f078f209 4058
f1dc5600 4059 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 4060}
ff155a45
VT		 4061
4062/* HW Generic timers configuration */
4063
4064static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4065{
4066 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4067 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4068 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4069 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4070 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4071 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4072 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4073 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4074 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4075 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4076 AR_NDP2_TIMER_MODE, 0x0002},
4077 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4078 AR_NDP2_TIMER_MODE, 0x0004},
4079 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4080 AR_NDP2_TIMER_MODE, 0x0008},
4081 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4082 AR_NDP2_TIMER_MODE, 0x0010},
4083 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4084 AR_NDP2_TIMER_MODE, 0x0020},
4085 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4086 AR_NDP2_TIMER_MODE, 0x0040},
4087 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4088 AR_NDP2_TIMER_MODE, 0x0080}
4089};
4090
4091/* HW generic timer primitives */
4092
4093/* compute and clear index of rightmost 1 */
4094static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4095{
4096 u32 b;
4097
4098 b = *mask;
4099 b &= (0-b);
4100 *mask &= ~b;
4101 b *= debruijn32;
4102 b >>= 27;
4103
4104 return timer_table->gen_timer_index[b];
4105}
4106
1773912b 4107u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 4108{
4109 return REG_READ(ah, AR_TSF_L32);
4110}
4111
4112struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4113 void (*trigger)(void *),
4114 void (*overflow)(void *),
4115 void *arg,
4116 u8 timer_index)
4117{
4118 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4119 struct ath_gen_timer *timer;
4120
4121 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4122
4123 if (timer == NULL) {
4124 printk(KERN_DEBUG "Failed to allocate memory"
4125 "for hw timer[%d]\n", timer_index);
4126 return NULL;
4127 }
4128
4129 /* allocate a hardware generic timer slot */
4130 timer_table->timers[timer_index] = timer;
4131 timer->index = timer_index;
4132 timer->trigger = trigger;
4133 timer->overflow = overflow;
4134 timer->arg = arg;
4135
4136 return timer;
4137}
4138
4139void ath_gen_timer_start(struct ath_hw *ah,
4140 struct ath_gen_timer *timer,
4141 u32 timer_next, u32 timer_period)
4142{
4143 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4144 u32 tsf;
4145
4146 BUG_ON(!timer_period);
4147
4148 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4149
4150 tsf = ath9k_hw_gettsf32(ah);
4151
4d6b228d 4152 DPRINTF(ah, ATH_DBG_HWTIMER, "curent tsf %x period %x"
ff155a45
VT		 4153 "timer_next %x\n", tsf, timer_period, timer_next);
4154
4155 /*
4156 * Pull timer_next forward if the current TSF already passed it
4157 * because of software latency
4158 */
4159 if (timer_next < tsf)
4160 timer_next = tsf + timer_period;
4161
4162 /*
4163 * Program generic timer registers
4164 */
4165 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4166 timer_next);
4167 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4168 timer_period);
4169 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4170 gen_tmr_configuration[timer->index].mode_mask);
4171
4172 /* Enable both trigger and thresh interrupt masks */
4173 REG_SET_BIT(ah, AR_IMR_S5,
4174 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4175 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4176
4177 if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
4178 ath9k_hw_set_interrupts(ah, 0);
4179 ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
4180 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4181 }
4182}
4183
4184void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4185{
4186 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4187
4188 if ((timer->index < AR_FIRST_NDP_TIMER) ||
4189 (timer->index >= ATH_MAX_GEN_TIMER)) {
4190 return;
4191 }
4192
4193 /* Clear generic timer enable bits. */
4194 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4195 gen_tmr_configuration[timer->index].mode_mask);
4196
4197 /* Disable both trigger and thresh interrupt masks */
4198 REG_CLR_BIT(ah, AR_IMR_S5,
4199 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4200 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4201
4202 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4203
4204 /* if no timer is enabled, turn off interrupt mask */
4205 if (timer_table->timer_mask.val == 0) {
4206 ath9k_hw_set_interrupts(ah, 0);
4207 ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
4208 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4209 }
4210}
4211
4212void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4213{
4214 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4215
4216 /* free the hardware generic timer slot */
4217 timer_table->timers[timer->index] = NULL;
4218 kfree(timer);
4219}
4220
4221/*
4222 * Generic Timer Interrupts handling
4223 */
4224void ath_gen_timer_isr(struct ath_hw *ah)
4225{
4226 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4227 struct ath_gen_timer *timer;
4228 u32 trigger_mask, thresh_mask, index;
4229
4230 /* get hardware generic timer interrupt status */
4231 trigger_mask = ah->intr_gen_timer_trigger;
4232 thresh_mask = ah->intr_gen_timer_thresh;
4233 trigger_mask &= timer_table->timer_mask.val;
4234 thresh_mask &= timer_table->timer_mask.val;
4235
4236 trigger_mask &= ~thresh_mask;
4237
4238 while (thresh_mask) {
4239 index = rightmost_index(timer_table, &thresh_mask);
4240 timer = timer_table->timers[index];
4241 BUG_ON(!timer);
4d6b228d 4242 DPRINTF(ah, ATH_DBG_HWTIMER,
ff155a45
VT		 4243 "TSF overflow for Gen timer %d\n", index);
4244 timer->overflow(timer->arg);
4245 }
4246
4247 while (trigger_mask) {
4248 index = rightmost_index(timer_table, &trigger_mask);
4249 timer = timer_table->timers[index];
4250 BUG_ON(!timer);
4d6b228d 4251 DPRINTF(ah, ATH_DBG_HWTIMER,
ff155a45
VT		 4252 "Gen timer[%d] trigger\n", index);
4253 timer->trigger(timer->arg);
4254 }
4255}
Linux kernel - Deliverables
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