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ath9k_hw: split the generic hardware code by hardware family
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
af03abec 20#include "hw.h"
d70357d5 21#include "hw-ops.h"
cfe8cba9 22#include "rc.h"
af01c04e 23#include "ar9002_initvals.h"
f078f209 24
4febf7b8
LR		 25#define ATH9K_CLOCK_RATE_CCK 22
26#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 28
cbe61d8a 29static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 30
7322fd19
LR		 31MODULE_AUTHOR("Atheros Communications");
32MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
33MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
34MODULE_LICENSE("Dual BSD/GPL");
35
36static int __init ath9k_init(void)
37{
38 return 0;
39}
40module_init(ath9k_init);
41
42static void __exit ath9k_exit(void)
43{
44 return;
45}
46module_exit(ath9k_exit);
47
d70357d5
LR		 48/* Private hardware callbacks */
49
50static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
51{
52 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
53}
54
55static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
56{
57 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
58}
59
60static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
61{
62 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
63
64 return priv_ops->macversion_supported(ah->hw_version.macVersion);
65}
66
64773964
LR		 67static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
68 struct ath9k_channel *chan)
69{
70 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
71}
72
f1dc5600
S		 73/********************/
74/* Helper Functions */
75/********************/
f078f209 76
cbe61d8a 77static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 78{
b002a4a9 79 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 80
2660b81a 81 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 82 return usecs *ATH9K_CLOCK_RATE_CCK;
83 if (conf->channel->band == IEEE80211_BAND_2GHZ)
84 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
85 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 86}
87
cbe61d8a 88static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 89{
b002a4a9 90 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 91
4febf7b8 92 if (conf_is_ht40(conf))
f1dc5600
S		 93 return ath9k_hw_mac_clks(ah, usecs) * 2;
94 else
95 return ath9k_hw_mac_clks(ah, usecs);
96}
f078f209 97
0caa7b14 98bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 99{
100 int i;
101
0caa7b14
S		 102 BUG_ON(timeout < AH_TIME_QUANTUM);
103
104 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 105 if ((REG_READ(ah, reg) & mask) == val)
106 return true;
107
108 udelay(AH_TIME_QUANTUM);
109 }
04bd4638 110
c46917bb
LR		 111 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
112 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
113 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 114
f1dc5600 115 return false;
f078f209 116}
7322fd19 117EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 118
119u32 ath9k_hw_reverse_bits(u32 val, u32 n)
120{
121 u32 retval;
122 int i;
123
124 for (i = 0, retval = 0; i < n; i++) {
125 retval = (retval << 1) | (val & 1);
126 val >>= 1;
127 }
128 return retval;
129}
130
cbe61d8a 131bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 132 u16 flags, u16 *low,
133 u16 *high)
f078f209 134{
2660b81a 135 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 136
f1dc5600
S		 137 if (flags & CHANNEL_5GHZ) {
138 *low = pCap->low_5ghz_chan;
139 *high = pCap->high_5ghz_chan;
140 return true;
f078f209 141 }
f1dc5600
S		 142 if ((flags & CHANNEL_2GHZ)) {
143 *low = pCap->low_2ghz_chan;
144 *high = pCap->high_2ghz_chan;
145 return true;
146 }
147 return false;
f078f209
LR		 148}
149
cbe61d8a 150u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 151 u8 phy, int kbps,
f1dc5600
S		 152 u32 frameLen, u16 rateix,
153 bool shortPreamble)
f078f209 154{
f1dc5600 155 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 156
f1dc5600
S		 157 if (kbps == 0)
158 return 0;
f078f209 159
545750d3 160 switch (phy) {
46d14a58 161 case WLAN_RC_PHY_CCK:
f1dc5600 162 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 163 if (shortPreamble)
f1dc5600
S		 164 phyTime >>= 1;
165 numBits = frameLen << 3;
166 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
167 break;
46d14a58 168 case WLAN_RC_PHY_OFDM:
2660b81a 169 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 170 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
171 numBits = OFDM_PLCP_BITS + (frameLen << 3);
172 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
173 txTime = OFDM_SIFS_TIME_QUARTER
174 + OFDM_PREAMBLE_TIME_QUARTER
175 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 176 } else if (ah->curchan &&
177 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 178 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
179 numBits = OFDM_PLCP_BITS + (frameLen << 3);
180 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
181 txTime = OFDM_SIFS_TIME_HALF +
182 OFDM_PREAMBLE_TIME_HALF
183 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
184 } else {
185 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
186 numBits = OFDM_PLCP_BITS + (frameLen << 3);
187 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
188 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
189 + (numSymbols * OFDM_SYMBOL_TIME);
190 }
191 break;
192 default:
c46917bb 193 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 194 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 195 txTime = 0;
196 break;
197 }
f078f209 198
f1dc5600
S		 199 return txTime;
200}
7322fd19 201EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 202
cbe61d8a 203void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 204 struct ath9k_channel *chan,
205 struct chan_centers *centers)
f078f209 206{
f1dc5600 207 int8_t extoff;
f078f209 208
f1dc5600
S		 209 if (!IS_CHAN_HT40(chan)) {
210 centers->ctl_center = centers->ext_center =
211 centers->synth_center = chan->channel;
212 return;
f078f209 213 }
f078f209 214
f1dc5600
S		 215 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
216 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
217 centers->synth_center =
218 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
219 extoff = 1;
220 } else {
221 centers->synth_center =
222 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
223 extoff = -1;
224 }
f078f209 225
f1dc5600
S		 226 centers->ctl_center =
227 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 228 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 229 centers->ext_center =
6420014c 230 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 231}
232
f1dc5600
S		 233/******************/
234/* Chip Revisions */
235/******************/
236
cbe61d8a 237static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 238{
f1dc5600 239 u32 val;
f078f209 240
f1dc5600 241 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 242
f1dc5600
S		 243 if (val == 0xFF) {
244 val = REG_READ(ah, AR_SREV);
d535a42a
S		 245 ah->hw_version.macVersion =
246 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
247 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 248 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 249 } else {
250 if (!AR_SREV_9100(ah))
d535a42a 251 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 252
d535a42a 253 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 254
d535a42a 255 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 256 ah->is_pciexpress = true;
f1dc5600 257 }
f078f209
LR		 258}
259
cbe61d8a 260static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 261{
f1dc5600
S		 262 u32 val;
263 int i;
f078f209 264
f1dc5600 265 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 266
f1dc5600
S		 267 for (i = 0; i < 8; i++)
268 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
269 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
270 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 271
f1dc5600 272 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 273}
274
f1dc5600
S		 275/************************************/
276/* HW Attach, Detach, Init Routines */
277/************************************/
278
cbe61d8a 279static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 280{
feed029c 281 if (AR_SREV_9100(ah))
f1dc5600 282 return;
f078f209 283
f1dc5600
S		 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 293
f1dc5600 294 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 295}
296
1f3f0618 297/* This should work for all families including legacy */
cbe61d8a 298static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 299{
c46917bb 300 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 301 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600
S		 302 u32 regHold[2];
303 u32 patternData[4] = { 0x55555555,
304 0xaaaaaaaa,
305 0x66666666,
306 0x99999999 };
1f3f0618 307 int i, j, loop_max;
f078f209 308
1f3f0618
SB		 309 if (!AR_SREV_9300_20_OR_LATER(ah)) {
310 loop_max = 2;
311 regAddr[1] = AR_PHY_BASE + (8 << 2);
312 } else
313 loop_max = 1;
314
315 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 316 u32 addr = regAddr[i];
317 u32 wrData, rdData;
f078f209 318
f1dc5600
S		 319 regHold[i] = REG_READ(ah, addr);
320 for (j = 0; j < 0x100; j++) {
321 wrData = (j << 16) | j;
322 REG_WRITE(ah, addr, wrData);
323 rdData = REG_READ(ah, addr);
324 if (rdData != wrData) {
c46917bb
LR		 325 ath_print(common, ATH_DBG_FATAL,
326 "address test failed "
327 "addr: 0x%08x - wr:0x%08x != "
328 "rd:0x%08x\n",
329 addr, wrData, rdData);
f1dc5600
S		 330 return false;
331 }
332 }
333 for (j = 0; j < 4; j++) {
334 wrData = patternData[j];
335 REG_WRITE(ah, addr, wrData);
336 rdData = REG_READ(ah, addr);
337 if (wrData != rdData) {
c46917bb
LR		 338 ath_print(common, ATH_DBG_FATAL,
339 "address test failed "
340 "addr: 0x%08x - wr:0x%08x != "
341 "rd:0x%08x\n",
342 addr, wrData, rdData);
f1dc5600
S		 343 return false;
344 }
f078f209 345 }
f1dc5600 346 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 347 }
f1dc5600 348 udelay(100);
cbe61d8a 349
f078f209
LR		 350 return true;
351}
352
b8b0f377 353static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 354{
355 int i;
f078f209 356
2660b81a
S		 357 ah->config.dma_beacon_response_time = 2;
358 ah->config.sw_beacon_response_time = 10;
359 ah->config.additional_swba_backoff = 0;
360 ah->config.ack_6mb = 0x0;
361 ah->config.cwm_ignore_extcca = 0;
362 ah->config.pcie_powersave_enable = 0;
2660b81a 363 ah->config.pcie_clock_req = 0;
2660b81a
S		 364 ah->config.pcie_waen = 0;
365 ah->config.analog_shiftreg = 1;
2660b81a
S		 366 ah->config.ofdm_trig_low = 200;
367 ah->config.ofdm_trig_high = 500;
368 ah->config.cck_trig_high = 200;
369 ah->config.cck_trig_low = 100;
31a0bd3c
LR		 370
371 /*
372 * For now ANI is disabled for AR9003, it is still
373 * being tested.
374 */
375 if (!AR_SREV_9300_20_OR_LATER(ah))
376 ah->config.enable_ani = 1;
f078f209 377
f1dc5600 378 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 379 ah->config.spurchans[i][0] = AR_NO_SPUR;
380 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 381 }
382
5ffaf8a3
LR		 383 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
384 ah->config.ht_enable = 1;
385 else
386 ah->config.ht_enable = 0;
387
0ce024cb 388 ah->config.rx_intr_mitigation = true;
6158425b
LR		 389
390 /*
391 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
392 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
393 * This means we use it for all AR5416 devices, and the few
394 * minor PCI AR9280 devices out there.
395 *
396 * Serialization is required because these devices do not handle
397 * well the case of two concurrent reads/writes due to the latency
398 * involved. During one read/write another read/write can be issued
399 * on another CPU while the previous read/write may still be working
400 * on our hardware, if we hit this case the hardware poops in a loop.
401 * We prevent this by serializing reads and writes.
402 *
403 * This issue is not present on PCI-Express devices or pre-AR5416
404 * devices (legacy, 802.11abg).
405 */
406 if (num_possible_cpus() > 1)
2d6a5e95 407 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 408}
409
50aca25b 410static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 411{
608b88cb
LR		 412 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
413
414 regulatory->country_code = CTRY_DEFAULT;
415 regulatory->power_limit = MAX_RATE_POWER;
416 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
417
d535a42a 418 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 419 ah->hw_version.subvendorid = 0;
f078f209
LR		 420
421 ah->ah_flags = 0;
f078f209
LR		 422 if (!AR_SREV_9100(ah))
423 ah->ah_flags = AH_USE_EEPROM;
424
2660b81a 425 ah->atim_window = 0;
2660b81a
S		 426 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
427 ah->beacon_interval = 100;
428 ah->enable_32kHz_clock = DONT_USE_32KHZ;
429 ah->slottime = (u32) -1;
2660b81a 430 ah->globaltxtimeout = (u32) -1;
cbdec975 431 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 432}
433
cbe61d8a 434static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 435{
f1dc5600
S		 436 u32 val;
437
438 REG_WRITE(ah, AR_PHY(0), 0x00000007);
439
440 val = ath9k_hw_get_radiorev(ah);
441 switch (val & AR_RADIO_SREV_MAJOR) {
442 case 0:
443 val = AR_RAD5133_SREV_MAJOR;
444 break;
445 case AR_RAD5133_SREV_MAJOR:
446 case AR_RAD5122_SREV_MAJOR:
447 case AR_RAD2133_SREV_MAJOR:
448 case AR_RAD2122_SREV_MAJOR:
449 break;
f078f209 450 default:
c46917bb
LR		 451 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
452 "Radio Chip Rev 0x%02X not supported\n",
453 val & AR_RADIO_SREV_MAJOR);
f1dc5600 454 return -EOPNOTSUPP;
f078f209 455 }
f078f209 456
d535a42a 457 ah->hw_version.analog5GhzRev = val;
f078f209 458
f1dc5600 459 return 0;
f078f209
LR		 460}
461
cbe61d8a 462static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 463{
1510718d 464 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 465 u32 sum;
466 int i;
467 u16 eeval;
f078f209
LR		 468
469 sum = 0;
470 for (i = 0; i < 3; i++) {
f74df6fb 471 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 472 sum += eeval;
1510718d
LR		 473 common->macaddr[2 * i] = eeval >> 8;
474 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 475 }
d8baa939 476 if (sum == 0 || sum == 0xffff * 3)
f078f209 477 return -EADDRNOTAVAIL;
f078f209
LR		 478
479 return 0;
480}
481
cbe61d8a 482static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 483{
484 u32 rxgain_type;
9f804202 485
f74df6fb
S		 486 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
487 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 488
489 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 490 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 491 ar9280Modes_backoff_13db_rxgain_9280_2,
492 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
493 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 494 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 495 ar9280Modes_backoff_23db_rxgain_9280_2,
496 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
497 else
2660b81a 498 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 499 ar9280Modes_original_rxgain_9280_2,
500 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 501 } else {
2660b81a 502 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 503 ar9280Modes_original_rxgain_9280_2,
504 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 505 }
9f804202
SB		 506}
507
cbe61d8a 508static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 509{
510 u32 txgain_type;
9f804202 511
f74df6fb
S		 512 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
513 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 514
515 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 516 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 517 ar9280Modes_high_power_tx_gain_9280_2,
518 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
519 else
2660b81a 520 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 521 ar9280Modes_original_tx_gain_9280_2,
522 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 523 } else {
2660b81a 524 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 525 ar9280Modes_original_tx_gain_9280_2,
526 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 527 }
9f804202
SB		 528}
529
f637cfd6 530static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 531{
f1dc5600 532 int ecode;
f078f209 533
527d485f
S		 534 if (!AR_SREV_9271(ah)) {
535 if (!ath9k_hw_chip_test(ah))
536 return -ENODEV;
537 }
f078f209 538
f1dc5600
S		 539 ecode = ath9k_hw_rf_claim(ah);
540 if (ecode != 0)
f078f209 541 return ecode;
f078f209 542
f637cfd6 543 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 544 if (ecode != 0)
545 return ecode;
7d01b221 546
c46917bb
LR		 547 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
548 "Eeprom VER: %d, REV: %d\n",
549 ah->eep_ops->get_eeprom_ver(ah),
550 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 551
8fe65368
LR		 552 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
553 if (ecode) {
554 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
555 "Failed allocating banks for "
556 "external radio\n");
557 return ecode;
574d6b12 558 }
f078f209 559
f1dc5600
S		 560 if (!AR_SREV_9100(ah)) {
561 ath9k_hw_ani_setup(ah);
f637cfd6 562 ath9k_hw_ani_init(ah);
f078f209
LR		 563 }
564
f078f209
LR		 565 return 0;
566}
567
aa4058ae
LR		 568static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
569{
b37fa870 570 if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec
VN		 571 INIT_INI_ARRAY(&ah->iniModesRxGain,
572 ar9287Modes_rx_gain_9287_1_1,
573 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
574 else if (AR_SREV_9287_10(ah))
575 INIT_INI_ARRAY(&ah->iniModesRxGain,
576 ar9287Modes_rx_gain_9287_1_0,
577 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
578 else if (AR_SREV_9280_20(ah))
579 ath9k_hw_init_rxgain_ini(ah);
580
b37fa870 581 if (AR_SREV_9287_11_OR_LATER(ah)) {
ac88b6ec
VN		 582 INIT_INI_ARRAY(&ah->iniModesTxGain,
583 ar9287Modes_tx_gain_9287_1_1,
584 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
585 } else if (AR_SREV_9287_10(ah)) {
586 INIT_INI_ARRAY(&ah->iniModesTxGain,
587 ar9287Modes_tx_gain_9287_1_0,
588 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
589 } else if (AR_SREV_9280_20(ah)) {
590 ath9k_hw_init_txgain_ini(ah);
591 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4e845168
SB		 592 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
593
594 /* txgain table */
595 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
53bc7aa0
VN		 596 if (AR_SREV_9285E_20(ah)) {
597 INIT_INI_ARRAY(&ah->iniModesTxGain,
598 ar9285Modes_XE2_0_high_power,
599 ARRAY_SIZE(
600 ar9285Modes_XE2_0_high_power), 6);
601 } else {
602 INIT_INI_ARRAY(&ah->iniModesTxGain,
603 ar9285Modes_high_power_tx_gain_9285_1_2,
604 ARRAY_SIZE(
605 ar9285Modes_high_power_tx_gain_9285_1_2), 6);
606 }
4e845168 607 } else {
53bc7aa0
VN		 608 if (AR_SREV_9285E_20(ah)) {
609 INIT_INI_ARRAY(&ah->iniModesTxGain,
610 ar9285Modes_XE2_0_normal_power,
611 ARRAY_SIZE(
612 ar9285Modes_XE2_0_normal_power), 6);
613 } else {
614 INIT_INI_ARRAY(&ah->iniModesTxGain,
615 ar9285Modes_original_tx_gain_9285_1_2,
616 ARRAY_SIZE(
617 ar9285Modes_original_tx_gain_9285_1_2), 6);
618 }
4e845168 619 }
4e845168 620 }
aa4058ae 621}
4e845168 622
aa8bc9ef 623static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
aa4058ae 624{
2eb46d9b
PR		 625 struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
626 struct ath_common *common = ath9k_hw_common(ah);
f078f209 627
2eb46d9b 628 ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
939ad86d 629 !AR_SREV_9285(ah) && !AR_SREV_9271(ah) &&
2eb46d9b
PR		 630 ((pBase->version & 0xff) > 0x0a) &&
631 (pBase->pwdclkind == 0);
f078f209 632
2eb46d9b
PR		 633 if (ah->need_an_top2_fixup)
634 ath_print(common, ATH_DBG_EEPROM,
635 "needs fixup for AR_AN_TOP2 register\n");
aa4058ae
LR		 636}
637
8525f280
LR		 638static void ath9k_hw_attach_ops(struct ath_hw *ah)
639{
640 if (AR_SREV_9300_20_OR_LATER(ah))
641 ar9003_hw_attach_ops(ah);
642 else
643 ar9002_hw_attach_ops(ah);
644}
645
d70357d5
LR		 646/* Called for all hardware families */
647static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 648{
c46917bb 649 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 650 int r = 0;
aa4058ae 651
bab1f62e
LR		 652 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
653 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
aa4058ae
LR		 654
655 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 656 ath_print(common, ATH_DBG_FATAL,
657 "Couldn't reset chip\n");
95fafca2 658 return -EIO;
aa4058ae
LR		 659 }
660
bab1f62e
LR		 661 ath9k_hw_init_defaults(ah);
662 ath9k_hw_init_config(ah);
663
8525f280 664 ath9k_hw_attach_ops(ah);
d70357d5 665
9ecdef4b 666 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 667 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 668 return -EIO;
aa4058ae
LR		 669 }
670
671 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
672 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
673 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
674 ah->config.serialize_regmode =
675 SER_REG_MODE_ON;
676 } else {
677 ah->config.serialize_regmode =
678 SER_REG_MODE_OFF;
679 }
680 }
681
c46917bb 682 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 683 ah->config.serialize_regmode);
684
f4709fdf
LR		 685 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
686 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
687 else
688 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
689
d70357d5 690 if (!ath9k_hw_macversion_supported(ah)) {
c46917bb
LR		 691 ath_print(common, ATH_DBG_FATAL,
692 "Mac Chip Rev 0x%02x.%x is not supported by "
693 "this driver\n", ah->hw_version.macVersion,
694 ah->hw_version.macRev);
95fafca2 695 return -EOPNOTSUPP;
aa4058ae
LR		 696 }
697
0df13da4 698 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
d7e7d229
LR		 699 ah->is_pciexpress = false;
700
aa4058ae 701 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 702 ath9k_hw_init_cal_settings(ah);
703
704 ah->ani_function = ATH9K_ANI_ALL;
31a0bd3c 705 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae
LR		 706 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
707
708 ath9k_hw_init_mode_regs(ah);
709
710 if (ah->is_pciexpress)
93b1b37f 711 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 712 else
713 ath9k_hw_disablepcie(ah);
714
193cd458
S		 715 /* Support for Japan ch.14 (2484) spread */
716 if (AR_SREV_9287_11_OR_LATER(ah)) {
717 INIT_INI_ARRAY(&ah->iniCckfirNormal,
718 ar9287Common_normal_cck_fir_coeff_92871_1,
719 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
720 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
721 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
722 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
723 }
724
f637cfd6 725 r = ath9k_hw_post_init(ah);
aa4058ae 726 if (r)
95fafca2 727 return r;
aa4058ae
LR		 728
729 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 730 r = ath9k_hw_fill_cap_info(ah);
731 if (r)
732 return r;
733
aa8bc9ef 734 ath9k_hw_init_eeprom_fix(ah);
f6688cd8 735
4f3acf81
LR		 736 r = ath9k_hw_init_macaddr(ah);
737 if (r) {
c46917bb
LR		 738 ath_print(common, ATH_DBG_FATAL,
739 "Failed to initialize MAC address\n");
95fafca2 740 return r;
f078f209
LR		 741 }
742
d7e7d229 743 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 744 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 745 else
2660b81a 746 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 747
641d9921
FF		 748 if (AR_SREV_9300_20_OR_LATER(ah))
749 ar9003_hw_set_nf_limits(ah);
750
f1dc5600 751 ath9k_init_nfcal_hist_buffer(ah);
f078f209 752
211f5859
LR		 753 common->state = ATH_HW_INITIALIZED;
754
4f3acf81 755 return 0;
f078f209
LR		 756}
757
d70357d5
LR		 758int ath9k_hw_init(struct ath_hw *ah)
759{
760 int ret;
761 struct ath_common *common = ath9k_hw_common(ah);
762
763 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
764 switch (ah->hw_version.devid) {
765 case AR5416_DEVID_PCI:
766 case AR5416_DEVID_PCIE:
767 case AR5416_AR9100_DEVID:
768 case AR9160_DEVID_PCI:
769 case AR9280_DEVID_PCI:
770 case AR9280_DEVID_PCIE:
771 case AR9285_DEVID_PCIE:
db3cc53a
SB		 772 case AR9287_DEVID_PCI:
773 case AR9287_DEVID_PCIE:
d70357d5 774 case AR2427_DEVID_PCIE:
db3cc53a 775 case AR9300_DEVID_PCIE:
d70357d5
LR		 776 break;
777 default:
778 if (common->bus_ops->ath_bus_type == ATH_USB)
779 break;
780 ath_print(common, ATH_DBG_FATAL,
781 "Hardware device ID 0x%04x not supported\n",
782 ah->hw_version.devid);
783 return -EOPNOTSUPP;
784 }
785
786 ret = __ath9k_hw_init(ah);
787 if (ret) {
788 ath_print(common, ATH_DBG_FATAL,
789 "Unable to initialize hardware; "
790 "initialization status: %d\n", ret);
791 return ret;
792 }
793
794 return 0;
795}
796EXPORT_SYMBOL(ath9k_hw_init);
797
cbe61d8a 798static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 799{
f1dc5600
S		 800 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
801 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 802
f1dc5600
S		 803 REG_WRITE(ah, AR_QOS_NO_ACK,
804 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
805 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
806 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
807
808 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
809 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
810 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
811 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
812 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 813}
814
cbe61d8a 815static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 816 struct ath9k_channel *chan)
f078f209 817{
64773964 818 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 819
d03a66c1 820 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 821
c75724d1
LR		 822 /* Switch the core clock for ar9271 to 117Mhz */
823 if (AR_SREV_9271(ah)) {
25e2ab17
S		 824 udelay(500);
825 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 826 }
827
f1dc5600
S		 828 udelay(RTC_PLL_SETTLE_DELAY);
829
830 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 831}
832
cbe61d8a 833static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 834 enum nl80211_iftype opmode)
f078f209 835{
152d530d 836 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 837 AR_IMR_TXURN |
838 AR_IMR_RXERR |
839 AR_IMR_RXORN |
840 AR_IMR_BCNMISC;
f078f209 841
0ce024cb 842 if (ah->config.rx_intr_mitigation)
152d530d 843 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 844 else
152d530d 845 imr_reg |= AR_IMR_RXOK;
f078f209 846
152d530d 847 imr_reg |= AR_IMR_TXOK;
f078f209 848
d97809db 849 if (opmode == NL80211_IFTYPE_AP)
152d530d 850 imr_reg |= AR_IMR_MIB;
f078f209 851
152d530d 852 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 853 ah->imrs2_reg |= AR_IMR_S2_GTT;
854 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 855
f1dc5600
S		 856 if (!AR_SREV_9100(ah)) {
857 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
858 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
859 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
860 }
f078f209
LR		 861}
862
0005baf4 863static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 864{
0005baf4
FF		 865 u32 val = ath9k_hw_mac_to_clks(ah, us);
866 val = min(val, (u32) 0xFFFF);
867 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 868}
869
0005baf4 870static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 871{
0005baf4
FF		 872 u32 val = ath9k_hw_mac_to_clks(ah, us);
873 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
874 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
875}
876
877static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
878{
879 u32 val = ath9k_hw_mac_to_clks(ah, us);
880 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
881 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 882}
f1dc5600 883
cbe61d8a 884static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 885{
f078f209 886 if (tu > 0xFFFF) {
c46917bb
LR		 887 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
888 "bad global tx timeout %u\n", tu);
2660b81a 889 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 890 return false;
891 } else {
892 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 893 ah->globaltxtimeout = tu;
f078f209
LR		 894 return true;
895 }
896}
897
0005baf4 898void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 899{
0005baf4
FF		 900 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
901 int acktimeout;
e239d859 902 int slottime;
0005baf4
FF		 903 int sifstime;
904
c46917bb
LR		 905 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
906 ah->misc_mode);
f078f209 907
2660b81a 908 if (ah->misc_mode != 0)
f1dc5600 909 REG_WRITE(ah, AR_PCU_MISC,
2660b81a 910 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
0005baf4
FF		 911
912 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
913 sifstime = 16;
914 else
915 sifstime = 10;
916
e239d859
FF		 917 /* As defined by IEEE 802.11-2007 17.3.8.6 */
918 slottime = ah->slottime + 3 * ah->coverage_class;
919 acktimeout = slottime + sifstime;
42c4568a
FF		 920
921 /*
922 * Workaround for early ACK timeouts, add an offset to match the
923 * initval's 64us ack timeout value.
924 * This was initially only meant to work around an issue with delayed
925 * BA frames in some implementations, but it has been found to fix ACK
926 * timeout issues in other cases as well.
927 */
928 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
929 acktimeout += 64 - sifstime - ah->slottime;
930
e239d859 931 ath9k_hw_setslottime(ah, slottime);
0005baf4
FF		 932 ath9k_hw_set_ack_timeout(ah, acktimeout);
933 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 934 if (ah->globaltxtimeout != (u32) -1)
935 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 936}
0005baf4 937EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 938
285f2dda 939void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 940{
211f5859
LR		 941 struct ath_common *common = ath9k_hw_common(ah);
942
736b3a27 943 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 944 goto free_hw;
945
f1dc5600 946 if (!AR_SREV_9100(ah))
e70c0cfd 947 ath9k_hw_ani_disable(ah);
f1dc5600 948
9ecdef4b 949 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 950
951free_hw:
8fe65368 952 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 953}
285f2dda 954EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 955
f1dc5600
S		 956/*******/
957/* INI */
958/*******/
959
8fe65368 960u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 961{
962 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
963
964 if (IS_CHAN_B(chan))
965 ctl |= CTL_11B;
966 else if (IS_CHAN_G(chan))
967 ctl |= CTL_11G;
968 else
969 ctl |= CTL_11A;
970
971 return ctl;
972}
973
f1dc5600
S		 974/****************************************/
975/* Reset and Channel Switching Routines */
976/****************************************/
977
cbe61d8a 978static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 979{
980 u32 regval;
981
d7e7d229
LR		 982 /*
983 * set AHB_MODE not to do cacheline prefetches
984 */
f1dc5600
S		 985 regval = REG_READ(ah, AR_AHB_MODE);
986 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
987
d7e7d229
LR		 988 /*
989 * let mac dma reads be in 128 byte chunks
990 */
f1dc5600
S		 991 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
992 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
993
d7e7d229
LR		 994 /*
995 * Restore TX Trigger Level to its pre-reset value.
996 * The initial value depends on whether aggregation is enabled, and is
997 * adjusted whenever underruns are detected.
998 */
2660b81a 999 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1000
d7e7d229
LR		 1001 /*
1002 * let mac dma writes be in 128 byte chunks
1003 */
f1dc5600
S		 1004 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1005 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1006
d7e7d229
LR		 1007 /*
1008 * Setup receive FIFO threshold to hold off TX activities
1009 */
f1dc5600
S		 1010 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1011
d7e7d229
LR		 1012 /*
1013 * reduce the number of usable entries in PCU TXBUF to avoid
1014 * wrap around issues.
1015 */
f1dc5600 1016 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1017 /* For AR9285 the number of Fifos are reduced to half.
1018 * So set the usable tx buf size also to half to
1019 * avoid data/delimiter underruns
1020 */
f1dc5600
S		 1021 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1022 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1023 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1024 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1025 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1026 }
1027}
1028
cbe61d8a 1029static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1030{
1031 u32 val;
1032
1033 val = REG_READ(ah, AR_STA_ID1);
1034 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1035 switch (opmode) {
d97809db 1036 case NL80211_IFTYPE_AP:
f1dc5600
S		 1037 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1038 | AR_STA_ID1_KSRCH_MODE);
1039 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1040 break;
d97809db 1041 case NL80211_IFTYPE_ADHOC:
9cb5412b 1042 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 1043 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1044 | AR_STA_ID1_KSRCH_MODE);
1045 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1046 break;
d97809db
CM		 1047 case NL80211_IFTYPE_STATION:
1048 case NL80211_IFTYPE_MONITOR:
f1dc5600 1049 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1050 break;
f1dc5600
S		 1051 }
1052}
1053
8fe65368
LR		 1054void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1055 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1056{
1057 u32 coef_exp, coef_man;
1058
1059 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1060 if ((coef_scaled >> coef_exp) & 0x1)
1061 break;
1062
1063 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1064
1065 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1066
1067 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1068 *coef_exponent = coef_exp - 16;
1069}
1070
cbe61d8a 1071static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1072{
1073 u32 rst_flags;
1074 u32 tmpReg;
1075
70768496
S		 1076 if (AR_SREV_9100(ah)) {
1077 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1078 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1079 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1080 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1081 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1082 }
1083
f1dc5600
S		 1084 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1085 AR_RTC_FORCE_WAKE_ON_INT);
1086
1087 if (AR_SREV_9100(ah)) {
1088 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1089 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1090 } else {
1091 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1092 if (tmpReg &
1093 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1094 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1095 u32 val;
f1dc5600 1096 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1097
1098 val = AR_RC_HOSTIF;
1099 if (!AR_SREV_9300_20_OR_LATER(ah))
1100 val |= AR_RC_AHB;
1101 REG_WRITE(ah, AR_RC, val);
1102
1103 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1104 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1105
1106 rst_flags = AR_RTC_RC_MAC_WARM;
1107 if (type == ATH9K_RESET_COLD)
1108 rst_flags |= AR_RTC_RC_MAC_COLD;
1109 }
1110
d03a66c1 1111 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1112 udelay(50);
1113
d03a66c1 1114 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1115 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1116 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1117 "RTC stuck in MAC reset\n");
f1dc5600
S		 1118 return false;
1119 }
1120
1121 if (!AR_SREV_9100(ah))
1122 REG_WRITE(ah, AR_RC, 0);
1123
f1dc5600
S		 1124 if (AR_SREV_9100(ah))
1125 udelay(50);
1126
1127 return true;
1128}
1129
cbe61d8a 1130static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1131{
1132 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1133 AR_RTC_FORCE_WAKE_ON_INT);
1134
42d5bc3f 1135 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1136 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1137
d03a66c1 1138 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1139
84e2169b
SB		 1140 if (!AR_SREV_9300_20_OR_LATER(ah))
1141 udelay(2);
1142
1143 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1144 REG_WRITE(ah, AR_RC, 0);
1145
d03a66c1 1146 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1147
1148 if (!ath9k_hw_wait(ah,
1149 AR_RTC_STATUS,
1150 AR_RTC_STATUS_M,
0caa7b14
S		 1151 AR_RTC_STATUS_ON,
1152 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1153 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1154 "RTC not waking up\n");
f1dc5600 1155 return false;
f078f209
LR		 1156 }
1157
f1dc5600
S		 1158 ath9k_hw_read_revisions(ah);
1159
1160 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1161}
1162
cbe61d8a 1163static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1164{
1165 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1166 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1167
1168 switch (type) {
1169 case ATH9K_RESET_POWER_ON:
1170 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1171 case ATH9K_RESET_WARM:
1172 case ATH9K_RESET_COLD:
1173 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1174 default:
1175 return false;
1176 }
f078f209
LR		 1177}
1178
cbe61d8a 1179static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1180 struct ath9k_channel *chan)
f078f209 1181{
42abfbee 1182 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1183 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1184 return false;
1185 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1186 return false;
f078f209 1187
9ecdef4b 1188 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1189 return false;
f078f209 1190
2660b81a 1191 ah->chip_fullsleep = false;
f1dc5600 1192 ath9k_hw_init_pll(ah, chan);
f1dc5600 1193 ath9k_hw_set_rfmode(ah, chan);
f078f209 1194
f1dc5600 1195 return true;
f078f209
LR		 1196}
1197
cbe61d8a 1198static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1199 struct ath9k_channel *chan)
f078f209 1200{
608b88cb 1201 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1202 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1203 struct ieee80211_channel *channel = chan->chan;
8fe65368 1204 u32 qnum;
0a3b7bac 1205 int r;
f078f209
LR		 1206
1207 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1208 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1209 ath_print(common, ATH_DBG_QUEUE,
1210 "Transmit frames pending on "
1211 "queue %d\n", qnum);
f078f209
LR		 1212 return false;
1213 }
1214 }
1215
8fe65368 1216 if (!ath9k_hw_rfbus_req(ah)) {
c46917bb
LR		 1217 ath_print(common, ATH_DBG_FATAL,
1218 "Could not kill baseband RX\n");
f078f209
LR		 1219 return false;
1220 }
1221
8fe65368 1222 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1223
8fe65368 1224 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1225 if (r) {
1226 ath_print(common, ATH_DBG_FATAL,
1227 "Failed to set channel\n");
1228 return false;
f078f209
LR		 1229 }
1230
8fbff4b8 1231 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1232 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1233 channel->max_antenna_gain * 2,
1234 channel->max_power * 2,
1235 min((u32) MAX_RATE_POWER,
608b88cb 1236 (u32) regulatory->power_limit));
f078f209 1237
8fe65368 1238 ath9k_hw_rfbus_done(ah);
f078f209 1239
f1dc5600
S		 1240 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1241 ath9k_hw_set_delta_slope(ah, chan);
1242
8fe65368 1243 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600
S		 1244
1245 if (!chan->oneTimeCalsDone)
1246 chan->oneTimeCalsDone = true;
1247
1248 return true;
1249}
1250
cbe61d8a 1251int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 1252 bool bChannelChange)
f078f209 1253{
1510718d 1254 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1255 u32 saveLedState;
2660b81a 1256 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1257 u32 saveDefAntenna;
1258 u32 macStaId1;
46fe782c 1259 u64 tsf = 0;
8fe65368 1260 int i, r;
f078f209 1261
43c27613
LR		 1262 ah->txchainmask = common->tx_chainmask;
1263 ah->rxchainmask = common->rx_chainmask;
f078f209 1264
9ecdef4b 1265 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1266 return -EIO;
f078f209 1267
9ebef799 1268 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1269 ath9k_hw_getnf(ah, curchan);
1270
1271 if (bChannelChange &&
2660b81a
S		 1272 (ah->chip_fullsleep != true) &&
1273 (ah->curchan != NULL) &&
1274 (chan->channel != ah->curchan->channel) &&
f078f209 1275 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1276 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
0a475cc6
VT		 1277 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1278 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
f078f209 1279
25c56eec 1280 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1281 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 1282 ath9k_hw_start_nfcal(ah);
ae8d2858 1283 return 0;
f078f209
LR		 1284 }
1285 }
1286
1287 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1288 if (saveDefAntenna == 0)
1289 saveDefAntenna = 1;
1290
1291 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1292
46fe782c
S		 1293 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1294 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1295 tsf = ath9k_hw_gettsf64(ah);
1296
f078f209
LR		 1297 saveLedState = REG_READ(ah, AR_CFG_LED) &
1298 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1299 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1300
1301 ath9k_hw_mark_phy_inactive(ah);
1302
05020d23 1303 /* Only required on the first reset */
d7e7d229
LR		 1304 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1305 REG_WRITE(ah,
1306 AR9271_RESET_POWER_DOWN_CONTROL,
1307 AR9271_RADIO_RF_RST);
1308 udelay(50);
1309 }
1310
f078f209 1311 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1312 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1313 return -EINVAL;
f078f209
LR		 1314 }
1315
05020d23 1316 /* Only required on the first reset */
d7e7d229
LR		 1317 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1318 ah->htc_reset_init = false;
1319 REG_WRITE(ah,
1320 AR9271_RESET_POWER_DOWN_CONTROL,
1321 AR9271_GATE_MAC_CTL);
1322 udelay(50);
1323 }
1324
46fe782c
S		 1325 /* Restore TSF */
1326 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1327 ath9k_hw_settsf64(ah, tsf);
1328
369391db
VT		 1329 if (AR_SREV_9280_10_OR_LATER(ah))
1330 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1331
25c56eec 1332 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1333 if (r)
1334 return r;
f078f209 1335
0ced0e17
JM		 1336 /* Setup MFP options for CCMP */
1337 if (AR_SREV_9280_20_OR_LATER(ah)) {
1338 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1339 * frames when constructing CCMP AAD. */
1340 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1341 0xc7ff);
1342 ah->sw_mgmt_crypto = false;
1343 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1344 /* Disable hardware crypto for management frames */
1345 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1346 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1347 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1348 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1349 ah->sw_mgmt_crypto = true;
1350 } else
1351 ah->sw_mgmt_crypto = true;
1352
f078f209
LR		 1353 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1354 ath9k_hw_set_delta_slope(ah, chan);
1355
8fe65368 1356 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1357 ah->eep_ops->set_board_values(ah, chan);
a7765828 1358
1510718d
LR		 1359 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1360 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1361 | macStaId1
1362 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1363 | (ah->config.
60b67f51 1364 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 1365 | ah->sta_id1_defaults);
1366 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 1367
13b81559 1368 ath_hw_setbssidmask(common);
f078f209
LR		 1369
1370 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1371
3453ad88 1372 ath9k_hw_write_associd(ah);
f078f209
LR		 1373
1374 REG_WRITE(ah, AR_ISR, ~0);
1375
1376 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1377
8fe65368 1378 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1379 if (r)
1380 return r;
f078f209
LR		 1381
1382 for (i = 0; i < AR_NUM_DCU; i++)
1383 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1384
2660b81a
S		 1385 ah->intr_txqs = 0;
1386 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 1387 ath9k_hw_resettxqueue(ah, i);
1388
2660b81a 1389 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 1390 ath9k_hw_init_qos(ah);
1391
2660b81a 1392 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 1393 ath9k_enable_rfkill(ah);
3b319aae 1394
0005baf4 1395 ath9k_hw_init_global_settings(ah);
f078f209 1396
326bebbc 1397 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 1398 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
1399 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
1400 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
1401 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
1402 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
1403 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
1404
1405 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
1406 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
1407
1408 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1409 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1410 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1411 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1412 }
326bebbc 1413 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 1414 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1415 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1416 }
1417
f078f209
LR		 1418 REG_WRITE(ah, AR_STA_ID1,
1419 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1420
1421 ath9k_hw_set_dma(ah);
1422
1423 REG_WRITE(ah, AR_OBS, 8);
1424
0ce024cb 1425 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1426 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1427 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1428 }
1429
1430 ath9k_hw_init_bb(ah, chan);
1431
ae8d2858 1432 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1433 return -EIO;
f078f209 1434
8fe65368 1435 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1436 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1437
d7e7d229
LR		 1438 /*
1439 * For big endian systems turn on swapping for descriptors
1440 */
f078f209
LR		 1441 if (AR_SREV_9100(ah)) {
1442 u32 mask;
1443 mask = REG_READ(ah, AR_CFG);
1444 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 1445 ath_print(common, ATH_DBG_RESET,
04bd4638 1446 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1447 } else {
1448 mask =
1449 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1450 REG_WRITE(ah, AR_CFG, mask);
c46917bb 1451 ath_print(common, ATH_DBG_RESET,
04bd4638 1452 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1453 }
1454 } else {
d7e7d229
LR		 1455 /* Configure AR9271 target WLAN */
1456 if (AR_SREV_9271(ah))
1457 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 1458#ifdef __BIG_ENDIAN
d7e7d229
LR		 1459 else
1460 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1461#endif
1462 }
1463
766ec4a9 1464 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1465 ath9k_hw_btcoex_enable(ah);
1466
ae8d2858 1467 return 0;
f078f209 1468}
7322fd19 1469EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1470
f1dc5600
S		 1471/************************/
1472/* Key Cache Management */
1473/************************/
f078f209 1474
cbe61d8a 1475bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 1476{
f1dc5600 1477 u32 keyType;
f078f209 1478
2660b81a 1479 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1480 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1481 "keychache entry %u out of range\n", entry);
f078f209
LR		 1482 return false;
1483 }
1484
f1dc5600 1485 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 1486
f1dc5600
S		 1487 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1488 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1489 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1490 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1491 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1492 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1493 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1494 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 1495
f1dc5600
S		 1496 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1497 u16 micentry = entry + 64;
f078f209 1498
f1dc5600
S		 1499 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1500 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1501 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1502 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 1503
f078f209
LR		 1504 }
1505
f078f209
LR		 1506 return true;
1507}
7322fd19 1508EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 1509
cbe61d8a 1510bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 1511{
f1dc5600 1512 u32 macHi, macLo;
f078f209 1513
2660b81a 1514 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1515 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1516 "keychache entry %u out of range\n", entry);
f1dc5600 1517 return false;
f078f209
LR		 1518 }
1519
f1dc5600
S		 1520 if (mac != NULL) {
1521 macHi = (mac[5] << 8) | mac[4];
1522 macLo = (mac[3] << 24) |
1523 (mac[2] << 16) |
1524 (mac[1] << 8) |
1525 mac[0];
1526 macLo >>= 1;
1527 macLo |= (macHi & 1) << 31;
1528 macHi >>= 1;
f078f209 1529 } else {
f1dc5600 1530 macLo = macHi = 0;
f078f209 1531 }
f1dc5600
S		 1532 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1533 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 1534
f1dc5600 1535 return true;
f078f209 1536}
7322fd19 1537EXPORT_SYMBOL(ath9k_hw_keysetmac);
f078f209 1538
cbe61d8a 1539bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 1540 const struct ath9k_keyval *k,
e0caf9ea 1541 const u8 *mac)
f078f209 1542{
2660b81a 1543 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1544 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 1545 u32 key0, key1, key2, key3, key4;
1546 u32 keyType;
f078f209 1547
f1dc5600 1548 if (entry >= pCap->keycache_size) {
c46917bb
LR		 1549 ath_print(common, ATH_DBG_FATAL,
1550 "keycache entry %u out of range\n", entry);
f1dc5600 1551 return false;
f078f209
LR		 1552 }
1553
f1dc5600
S		 1554 switch (k->kv_type) {
1555 case ATH9K_CIPHER_AES_OCB:
1556 keyType = AR_KEYTABLE_TYPE_AES;
1557 break;
1558 case ATH9K_CIPHER_AES_CCM:
1559 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 1560 ath_print(common, ATH_DBG_ANY,
1561 "AES-CCM not supported by mac rev 0x%x\n",
1562 ah->hw_version.macRev);
f1dc5600
S		 1563 return false;
1564 }
1565 keyType = AR_KEYTABLE_TYPE_CCM;
1566 break;
1567 case ATH9K_CIPHER_TKIP:
1568 keyType = AR_KEYTABLE_TYPE_TKIP;
1569 if (ATH9K_IS_MIC_ENABLED(ah)
1570 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 1571 ath_print(common, ATH_DBG_ANY,
1572 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 1573 return false;
1574 }
1575 break;
1576 case ATH9K_CIPHER_WEP:
e31a16d6 1577 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 1578 ath_print(common, ATH_DBG_ANY,
1579 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 1580 return false;
1581 }
e31a16d6 1582 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 1583 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 1584 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 1585 keyType = AR_KEYTABLE_TYPE_104;
1586 else
1587 keyType = AR_KEYTABLE_TYPE_128;
1588 break;
1589 case ATH9K_CIPHER_CLR:
1590 keyType = AR_KEYTABLE_TYPE_CLR;
1591 break;
1592 default:
c46917bb
LR		 1593 ath_print(common, ATH_DBG_FATAL,
1594 "cipher %u not supported\n", k->kv_type);
f1dc5600 1595 return false;
f078f209
LR		 1596 }
1597
e0caf9ea
JM		 1598 key0 = get_unaligned_le32(k->kv_val + 0);
1599 key1 = get_unaligned_le16(k->kv_val + 4);
1600 key2 = get_unaligned_le32(k->kv_val + 6);
1601 key3 = get_unaligned_le16(k->kv_val + 10);
1602 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 1603 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 1604 key4 &= 0xff;
f078f209 1605
672903b3
JM		 1606 /*
1607 * Note: Key cache registers access special memory area that requires
1608 * two 32-bit writes to actually update the values in the internal
1609 * memory. Consequently, the exact order and pairs used here must be
1610 * maintained.
1611 */
1612
f1dc5600
S		 1613 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1614 u16 micentry = entry + 64;
f078f209 1615
672903b3
JM		 1616 /*
1617 * Write inverted key[47:0] first to avoid Michael MIC errors
1618 * on frames that could be sent or received at the same time.
1619 * The correct key will be written in the end once everything
1620 * else is ready.
1621 */
f1dc5600
S		 1622 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1623 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 1624
1625 /* Write key[95:48] */
f1dc5600
S		 1626 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1627 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1628
1629 /* Write key[127:96] and key type */
f1dc5600
S		 1630 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1631 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 1632
1633 /* Write MAC address for the entry */
f1dc5600 1634 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 1635
2660b81a 1636 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 1637 /*
1638 * TKIP uses two key cache entries:
1639 * Michael MIC TX/RX keys in the same key cache entry
1640 * (idx = main index + 64):
1641 * key0 [31:0] = RX key [31:0]
1642 * key1 [15:0] = TX key [31:16]
1643 * key1 [31:16] = reserved
1644 * key2 [31:0] = RX key [63:32]
1645 * key3 [15:0] = TX key [15:0]
1646 * key3 [31:16] = reserved
1647 * key4 [31:0] = TX key [63:32]
1648 */
f1dc5600 1649 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 1650
f1dc5600
S		 1651 mic0 = get_unaligned_le32(k->kv_mic + 0);
1652 mic2 = get_unaligned_le32(k->kv_mic + 4);
1653 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1654 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1655 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 1656
1657 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 1658 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1659 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 1660
1661 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 1662 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1663 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 1664
1665 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1666 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1667 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1668 AR_KEYTABLE_TYPE_CLR);
f078f209 1669
f1dc5600 1670 } else {
672903b3
JM		 1671 /*
1672 * TKIP uses four key cache entries (two for group
1673 * keys):
1674 * Michael MIC TX/RX keys are in different key cache
1675 * entries (idx = main index + 64 for TX and
1676 * main index + 32 + 96 for RX):
1677 * key0 [31:0] = TX/RX MIC key [31:0]
1678 * key1 [31:0] = reserved
1679 * key2 [31:0] = TX/RX MIC key [63:32]
1680 * key3 [31:0] = reserved
1681 * key4 [31:0] = reserved
1682 *
1683 * Upper layer code will call this function separately
1684 * for TX and RX keys when these registers offsets are
1685 * used.
1686 */
f1dc5600 1687 u32 mic0, mic2;
f078f209 1688
f1dc5600
S		 1689 mic0 = get_unaligned_le32(k->kv_mic + 0);
1690 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 1691
1692 /* Write MIC key[31:0] */
f1dc5600
S		 1693 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1694 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 1695
1696 /* Write MIC key[63:32] */
f1dc5600
S		 1697 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1698 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 1699
1700 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1701 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1702 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1703 AR_KEYTABLE_TYPE_CLR);
1704 }
672903b3
JM		 1705
1706 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 1707 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1708 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 1709
1710 /*
1711 * Write the correct (un-inverted) key[47:0] last to enable
1712 * TKIP now that all other registers are set with correct
1713 * values.
1714 */
f1dc5600
S		 1715 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1716 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1717 } else {
672903b3 1718 /* Write key[47:0] */
f1dc5600
S		 1719 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1720 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 1721
1722 /* Write key[95:48] */
f1dc5600
S		 1723 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1724 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1725
1726 /* Write key[127:96] and key type */
f1dc5600
S		 1727 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1728 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 1729
672903b3 1730 /* Write MAC address for the entry */
f1dc5600
S		 1731 (void) ath9k_hw_keysetmac(ah, entry, mac);
1732 }
f078f209 1733
f078f209
LR		 1734 return true;
1735}
7322fd19 1736EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 1737
cbe61d8a 1738bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 1739{
2660b81a 1740 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 1741 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1742 if (val & AR_KEYTABLE_VALID)
1743 return true;
1744 }
1745 return false;
f078f209 1746}
7322fd19 1747EXPORT_SYMBOL(ath9k_hw_keyisvalid);
f078f209 1748
f1dc5600
S		 1749/******************************/
1750/* Power Management (Chipset) */
1751/******************************/
1752
42d5bc3f
LR		 1753/*
1754 * Notify Power Mgt is disabled in self-generated frames.
1755 * If requested, force chip to sleep.
1756 */
cbe61d8a 1757static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1758{
f1dc5600
S		 1759 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1760 if (setChip) {
42d5bc3f
LR		 1761 /*
1762 * Clear the RTC force wake bit to allow the
1763 * mac to go to sleep.
1764 */
f1dc5600
S		 1765 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1766 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1767 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1768 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1769
42d5bc3f 1770 /* Shutdown chip. Active low */
14b3af38 1771 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1772 REG_CLR_BIT(ah, (AR_RTC_RESET),
1773 AR_RTC_RESET_EN);
f1dc5600 1774 }
f078f209
LR		 1775}
1776
bbd79af5
LR		 1777/*
1778 * Notify Power Management is enabled in self-generating
1779 * frames. If request, set power mode of chip to
1780 * auto/normal. Duration in units of 128us (1/8 TU).
1781 */
cbe61d8a 1782static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1783{
f1dc5600
S		 1784 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1785 if (setChip) {
2660b81a 1786 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1787
f1dc5600 1788 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1789 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1790 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1791 AR_RTC_FORCE_WAKE_ON_INT);
1792 } else {
bbd79af5
LR		 1793 /*
1794 * Clear the RTC force wake bit to allow the
1795 * mac to go to sleep.
1796 */
f1dc5600
S		 1797 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1798 AR_RTC_FORCE_WAKE_EN);
f078f209 1799 }
f078f209 1800 }
f078f209
LR		 1801}
1802
cbe61d8a 1803static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1804{
f1dc5600
S		 1805 u32 val;
1806 int i;
f078f209 1807
f1dc5600
S		 1808 if (setChip) {
1809 if ((REG_READ(ah, AR_RTC_STATUS) &
1810 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1811 if (ath9k_hw_set_reset_reg(ah,
1812 ATH9K_RESET_POWER_ON) != true) {
1813 return false;
1814 }
e041228f
LR		 1815 if (!AR_SREV_9300_20_OR_LATER(ah))
1816 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1817 }
1818 if (AR_SREV_9100(ah))
1819 REG_SET_BIT(ah, AR_RTC_RESET,
1820 AR_RTC_RESET_EN);
f078f209 1821
f1dc5600
S		 1822 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1823 AR_RTC_FORCE_WAKE_EN);
1824 udelay(50);
f078f209 1825
f1dc5600
S		 1826 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1827 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1828 if (val == AR_RTC_STATUS_ON)
1829 break;
1830 udelay(50);
1831 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1832 AR_RTC_FORCE_WAKE_EN);
f078f209 1833 }
f1dc5600 1834 if (i == 0) {
c46917bb
LR		 1835 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1836 "Failed to wakeup in %uus\n",
1837 POWER_UP_TIME / 20);
f1dc5600 1838 return false;
f078f209 1839 }
f078f209
LR		 1840 }
1841
f1dc5600 1842 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1843
f1dc5600 1844 return true;
f078f209
LR		 1845}
1846
9ecdef4b 1847bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1848{
c46917bb 1849 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1850 int status = true, setChip = true;
f1dc5600
S		 1851 static const char *modes[] = {
1852 "AWAKE",
1853 "FULL-SLEEP",
1854 "NETWORK SLEEP",
1855 "UNDEFINED"
1856 };
f1dc5600 1857
cbdec975
GJ		 1858 if (ah->power_mode == mode)
1859 return status;
1860
c46917bb
LR		 1861 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1862 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1863
1864 switch (mode) {
1865 case ATH9K_PM_AWAKE:
1866 status = ath9k_hw_set_power_awake(ah, setChip);
1867 break;
1868 case ATH9K_PM_FULL_SLEEP:
1869 ath9k_set_power_sleep(ah, setChip);
2660b81a 1870 ah->chip_fullsleep = true;
f1dc5600
S		 1871 break;
1872 case ATH9K_PM_NETWORK_SLEEP:
1873 ath9k_set_power_network_sleep(ah, setChip);
1874 break;
f078f209 1875 default:
c46917bb
LR		 1876 ath_print(common, ATH_DBG_FATAL,
1877 "Unknown power mode %u\n", mode);
f078f209
LR		 1878 return false;
1879 }
2660b81a 1880 ah->power_mode = mode;
f1dc5600
S		 1881
1882 return status;
f078f209 1883}
7322fd19 1884EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1885
f1dc5600
S		 1886/**********************/
1887/* Interrupt Handling */
1888/**********************/
1889
cbe61d8a 1890bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 1891{
1892 u32 host_isr;
1893
1894 if (AR_SREV_9100(ah))
1895 return true;
1896
1897 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
1898 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
1899 return true;
1900
1901 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1902 if ((host_isr & AR_INTR_SYNC_DEFAULT)
1903 && (host_isr != AR_INTR_SPURIOUS))
1904 return true;
1905
1906 return false;
1907}
7322fd19 1908EXPORT_SYMBOL(ath9k_hw_intrpend);
f078f209 1909
cbe61d8a 1910bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 1911{
1912 u32 isr = 0;
1913 u32 mask2 = 0;
2660b81a 1914 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 1915 u32 sync_cause = 0;
1916 bool fatal_int = false;
c46917bb 1917 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 1918
1919 if (!AR_SREV_9100(ah)) {
1920 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
1921 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
1922 == AR_RTC_STATUS_ON) {
1923 isr = REG_READ(ah, AR_ISR);
1924 }
1925 }
1926
f1dc5600
S		 1927 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
1928 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 1929
1930 *masked = 0;
1931
1932 if (!isr && !sync_cause)
1933 return false;
1934 } else {
1935 *masked = 0;
1936 isr = REG_READ(ah, AR_ISR);
1937 }
1938
1939 if (isr) {
f078f209
LR		 1940 if (isr & AR_ISR_BCNMISC) {
1941 u32 isr2;
1942 isr2 = REG_READ(ah, AR_ISR_S2);
1943 if (isr2 & AR_ISR_S2_TIM)
1944 mask2 |= ATH9K_INT_TIM;
1945 if (isr2 & AR_ISR_S2_DTIM)
1946 mask2 |= ATH9K_INT_DTIM;
1947 if (isr2 & AR_ISR_S2_DTIMSYNC)
1948 mask2 |= ATH9K_INT_DTIMSYNC;
1949 if (isr2 & (AR_ISR_S2_CABEND))
1950 mask2 |= ATH9K_INT_CABEND;
1951 if (isr2 & AR_ISR_S2_GTT)
1952 mask2 |= ATH9K_INT_GTT;
1953 if (isr2 & AR_ISR_S2_CST)
1954 mask2 |= ATH9K_INT_CST;
4af9cf4f
S		 1955 if (isr2 & AR_ISR_S2_TSFOOR)
1956 mask2 |= ATH9K_INT_TSFOOR;
f078f209
LR		 1957 }
1958
1959 isr = REG_READ(ah, AR_ISR_RAC);
1960 if (isr == 0xffffffff) {
1961 *masked = 0;
1962 return false;
1963 }
1964
1965 *masked = isr & ATH9K_INT_COMMON;
1966
0ce024cb 1967 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1968 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
1969 *masked |= ATH9K_INT_RX;
1970 }
1971
1972 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
1973 *masked |= ATH9K_INT_RX;
1974 if (isr &
1975 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
1976 AR_ISR_TXEOL)) {
1977 u32 s0_s, s1_s;
1978
1979 *masked |= ATH9K_INT_TX;
1980
1981 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 1982 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
1983 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 1984
1985 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 1986 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
1987 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 1988 }
1989
1990 if (isr & AR_ISR_RXORN) {
c46917bb
LR		 1991 ath_print(common, ATH_DBG_INTERRUPT,
1992 "receive FIFO overrun interrupt\n");
f078f209
LR		 1993 }
1994
1995 if (!AR_SREV_9100(ah)) {
60b67f51 1996 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 1997 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
1998 if (isr5 & AR_ISR_S5_TIM_TIMER)
1999 *masked |= ATH9K_INT_TIM_TIMER;
2000 }
2001 }
2002
2003 *masked |= mask2;
2004 }
f1dc5600 2005
f078f209
LR		 2006 if (AR_SREV_9100(ah))
2007 return true;
f1dc5600 2008
ff155a45
VT		 2009 if (isr & AR_ISR_GENTMR) {
2010 u32 s5_s;
2011
2012 s5_s = REG_READ(ah, AR_ISR_S5_S);
2013 if (isr & AR_ISR_GENTMR) {
2014 ah->intr_gen_timer_trigger =
2015 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2016
2017 ah->intr_gen_timer_thresh =
2018 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2019
2020 if (ah->intr_gen_timer_trigger)
2021 *masked |= ATH9K_INT_GENTIMER;
2022
2023 }
2024 }
2025
f078f209
LR		 2026 if (sync_cause) {
2027 fatal_int =
2028 (sync_cause &
2029 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2030 ? true : false;
2031
2032 if (fatal_int) {
2033 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
c46917bb
LR		 2034 ath_print(common, ATH_DBG_ANY,
2035 "received PCI FATAL interrupt\n");
f078f209
LR		 2036 }
2037 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
c46917bb
LR		 2038 ath_print(common, ATH_DBG_ANY,
2039 "received PCI PERR interrupt\n");
f078f209 2040 }
a89bff9a 2041 *masked |= ATH9K_INT_FATAL;
f078f209
LR		 2042 }
2043 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
c46917bb
LR		 2044 ath_print(common, ATH_DBG_INTERRUPT,
2045 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 2046 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2047 REG_WRITE(ah, AR_RC, 0);
2048 *masked |= ATH9K_INT_FATAL;
2049 }
2050 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
c46917bb
LR		 2051 ath_print(common, ATH_DBG_INTERRUPT,
2052 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 2053 }
2054
2055 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2056 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2057 }
f1dc5600 2058
f078f209
LR		 2059 return true;
2060}
7322fd19 2061EXPORT_SYMBOL(ath9k_hw_getisr);
f078f209 2062
cbe61d8a 2063enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 2064{
152d530d 2065 enum ath9k_int omask = ah->imask;
f078f209 2066 u32 mask, mask2;
2660b81a 2067 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2068 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2069
c46917bb 2070 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 2071
2072 if (omask & ATH9K_INT_GLOBAL) {
c46917bb 2073 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 2074 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2075 (void) REG_READ(ah, AR_IER);
2076 if (!AR_SREV_9100(ah)) {
2077 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2078 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2079
2080 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2081 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2082 }
2083 }
2084
2085 mask = ints & ATH9K_INT_COMMON;
2086 mask2 = 0;
2087
2088 if (ints & ATH9K_INT_TX) {
2660b81a 2089 if (ah->txok_interrupt_mask)
f078f209 2090 mask |= AR_IMR_TXOK;
2660b81a 2091 if (ah->txdesc_interrupt_mask)
f078f209 2092 mask |= AR_IMR_TXDESC;
2660b81a 2093 if (ah->txerr_interrupt_mask)
f078f209 2094 mask |= AR_IMR_TXERR;
2660b81a 2095 if (ah->txeol_interrupt_mask)
f078f209
LR		 2096 mask |= AR_IMR_TXEOL;
2097 }
2098 if (ints & ATH9K_INT_RX) {
2099 mask |= AR_IMR_RXERR;
0ce024cb 2100 if (ah->config.rx_intr_mitigation)
f078f209
LR		 2101 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2102 else
2103 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 2104 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 2105 mask |= AR_IMR_GENTMR;
2106 }
2107
2108 if (ints & (ATH9K_INT_BMISC)) {
2109 mask |= AR_IMR_BCNMISC;
2110 if (ints & ATH9K_INT_TIM)
2111 mask2 |= AR_IMR_S2_TIM;
2112 if (ints & ATH9K_INT_DTIM)
2113 mask2 |= AR_IMR_S2_DTIM;
2114 if (ints & ATH9K_INT_DTIMSYNC)
2115 mask2 |= AR_IMR_S2_DTIMSYNC;
2116 if (ints & ATH9K_INT_CABEND)
4af9cf4f
S		 2117 mask2 |= AR_IMR_S2_CABEND;
2118 if (ints & ATH9K_INT_TSFOOR)
2119 mask2 |= AR_IMR_S2_TSFOOR;
f078f209
LR		 2120 }
2121
2122 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2123 mask |= AR_IMR_BCNMISC;
2124 if (ints & ATH9K_INT_GTT)
2125 mask2 |= AR_IMR_S2_GTT;
2126 if (ints & ATH9K_INT_CST)
2127 mask2 |= AR_IMR_S2_CST;
2128 }
2129
c46917bb 2130 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209 2131 REG_WRITE(ah, AR_IMR, mask);
74bad5cb
PR		 2132 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2133 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2134 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2135 ah->imrs2_reg |= mask2;
2136 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 2137
60b67f51 2138 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2139 if (ints & ATH9K_INT_TIM_TIMER)
2140 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2141 else
2142 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2143 }
2144
2145 if (ints & ATH9K_INT_GLOBAL) {
c46917bb 2146 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 2147 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2148 if (!AR_SREV_9100(ah)) {
2149 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2150 AR_INTR_MAC_IRQ);
2151 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2152
2153
2154 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2155 AR_INTR_SYNC_DEFAULT);
2156 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2157 AR_INTR_SYNC_DEFAULT);
2158 }
c46917bb
LR		 2159 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2160 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
f078f209
LR		 2161 }
2162
2163 return omask;
2164}
7322fd19 2165EXPORT_SYMBOL(ath9k_hw_set_interrupts);
f078f209 2166
f1dc5600
S		 2167/*******************/
2168/* Beacon Handling */
2169/*******************/
2170
cbe61d8a 2171void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2172{
f078f209
LR		 2173 int flags = 0;
2174
2660b81a 2175 ah->beacon_interval = beacon_period;
f078f209 2176
2660b81a 2177 switch (ah->opmode) {
d97809db
CM		 2178 case NL80211_IFTYPE_STATION:
2179 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 2180 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2181 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2182 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2183 flags |= AR_TBTT_TIMER_EN;
2184 break;
d97809db 2185 case NL80211_IFTYPE_ADHOC:
9cb5412b 2186 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 2187 REG_SET_BIT(ah, AR_TXCFG,
2188 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2189 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2190 TU_TO_USEC(next_beacon +
2660b81a
S		 2191 (ah->atim_window ? ah->
2192 atim_window : 1)));
f078f209 2193 flags |= AR_NDP_TIMER_EN;
d97809db 2194 case NL80211_IFTYPE_AP:
f078f209
LR		 2195 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2196 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2197 TU_TO_USEC(next_beacon -
2660b81a 2198 ah->config.
60b67f51 2199 dma_beacon_response_time));
f078f209
LR		 2200 REG_WRITE(ah, AR_NEXT_SWBA,
2201 TU_TO_USEC(next_beacon -
2660b81a 2202 ah->config.
60b67f51 2203 sw_beacon_response_time));
f078f209
LR		 2204 flags |=
2205 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2206 break;
d97809db 2207 default:
c46917bb
LR		 2208 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2209 "%s: unsupported opmode: %d\n",
2210 __func__, ah->opmode);
d97809db
CM		 2211 return;
2212 break;
f078f209
LR		 2213 }
2214
2215 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2216 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2217 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2218 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2219
2220 beacon_period &= ~ATH9K_BEACON_ENA;
2221 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 2222 ath9k_hw_reset_tsf(ah);
2223 }
2224
2225 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2226}
7322fd19 2227EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2228
cbe61d8a 2229void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2230 const struct ath9k_beacon_state *bs)
f078f209
LR		 2231{
2232 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2233 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2234 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 2235
2236 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2237
2238 REG_WRITE(ah, AR_BEACON_PERIOD,
2239 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2240 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2241 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2242
2243 REG_RMW_FIELD(ah, AR_RSSI_THR,
2244 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2245
2246 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
2247
2248 if (bs->bs_sleepduration > beaconintval)
2249 beaconintval = bs->bs_sleepduration;
2250
2251 dtimperiod = bs->bs_dtimperiod;
2252 if (bs->bs_sleepduration > dtimperiod)
2253 dtimperiod = bs->bs_sleepduration;
2254
2255 if (beaconintval == dtimperiod)
2256 nextTbtt = bs->bs_nextdtim;
2257 else
2258 nextTbtt = bs->bs_nexttbtt;
2259
c46917bb
LR		 2260 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2261 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2262 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2263 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2264
f1dc5600
S		 2265 REG_WRITE(ah, AR_NEXT_DTIM,
2266 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2267 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 2268
f1dc5600
S		 2269 REG_WRITE(ah, AR_SLEEP1,
2270 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2271 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2272
f1dc5600
S		 2273 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2274 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2275 else
2276 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2277
f1dc5600
S		 2278 REG_WRITE(ah, AR_SLEEP2,
2279 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2280
f1dc5600
S		 2281 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2282 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2283
f1dc5600
S		 2284 REG_SET_BIT(ah, AR_TIMER_MODE,
2285 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2286 AR_DTIM_TIMER_EN);
f078f209 2287
4af9cf4f
S		 2288 /* TSF Out of Range Threshold */
2289 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2290}
7322fd19 2291EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2292
f1dc5600
S		 2293/*******************/
2294/* HW Capabilities */
2295/*******************/
2296
a9a29ce6 2297int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2298{
2660b81a 2299 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2300 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2301 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 2302 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 2303
f1dc5600 2304 u16 capField = 0, eeval;
f078f209 2305
f74df6fb 2306 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2307 regulatory->current_rd = eeval;
f078f209 2308
f74df6fb 2309 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 2310 if (AR_SREV_9285_10_OR_LATER(ah))
2311 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 2312 regulatory->current_rd_ext = eeval;
f078f209 2313
f74df6fb 2314 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 2315
2660b81a 2316 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2317 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2318 if (regulatory->current_rd == 0x64 ||
2319 regulatory->current_rd == 0x65)
2320 regulatory->current_rd += 5;
2321 else if (regulatory->current_rd == 0x41)
2322 regulatory->current_rd = 0x43;
c46917bb
LR		 2323 ath_print(common, ATH_DBG_REGULATORY,
2324 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 2325 }
f078f209 2326
f74df6fb 2327 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6
GJ		 2328 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2329 ath_print(common, ATH_DBG_FATAL,
2330 "no band has been marked as supported in EEPROM.\n");
2331 return -EINVAL;
2332 }
2333
f1dc5600 2334 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 2335
f1dc5600
S		 2336 if (eeval & AR5416_OPFLAGS_11A) {
2337 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 2338 if (ah->config.ht_enable) {
f1dc5600
S		 2339 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2340 set_bit(ATH9K_MODE_11NA_HT20,
2341 pCap->wireless_modes);
2342 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2343 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2344 pCap->wireless_modes);
2345 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2346 pCap->wireless_modes);
2347 }
f078f209 2348 }
f078f209
LR		 2349 }
2350
f1dc5600 2351 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 2352 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 2353 if (ah->config.ht_enable) {
f1dc5600
S		 2354 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2355 set_bit(ATH9K_MODE_11NG_HT20,
2356 pCap->wireless_modes);
2357 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2358 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2359 pCap->wireless_modes);
2360 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2361 pCap->wireless_modes);
2362 }
2363 }
f078f209 2364 }
f1dc5600 2365
f74df6fb 2366 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2367 /*
2368 * For AR9271 we will temporarilly uses the rx chainmax as read from
2369 * the EEPROM.
2370 */
8147f5de 2371 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2372 !(eeval & AR5416_OPFLAGS_11A) &&
2373 !(AR_SREV_9271(ah)))
2374 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 2375 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2376 else
d7e7d229 2377 /* Use rx_chainmask from EEPROM. */
8147f5de 2378 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2379
d535a42a 2380 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 2381 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2382
f1dc5600
S		 2383 pCap->low_2ghz_chan = 2312;
2384 pCap->high_2ghz_chan = 2732;
f078f209 2385
f1dc5600
S		 2386 pCap->low_5ghz_chan = 4920;
2387 pCap->high_5ghz_chan = 6100;
f078f209 2388
f1dc5600
S		 2389 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2390 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2391 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 2392
f1dc5600
S		 2393 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2394 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2395 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 2396
2660b81a 2397 if (ah->config.ht_enable)
f1dc5600
S		 2398 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2399 else
2400 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2401
f1dc5600
S		 2402 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2403 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2404 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2405 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 2406
f1dc5600
S		 2407 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2408 pCap->total_queues =
2409 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2410 else
2411 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 2412
f1dc5600
S		 2413 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2414 pCap->keycache_size =
2415 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2416 else
2417 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 2418
f1dc5600 2419 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f4709fdf
LR		 2420
2421 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2422 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2423 else
2424 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 2425
5b5fa355
S		 2426 if (AR_SREV_9271(ah))
2427 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2428 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2429 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2430 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 2431 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2432 else
2433 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2434
f1dc5600
S		 2435 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2436 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2437 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2438 } else {
2439 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 2440 }
2441
f1dc5600
S		 2442 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2443
e97275cb 2444#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2445 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2446 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2447 ah->rfkill_gpio =
2448 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2449 ah->rfkill_polarity =
2450 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2451
2452 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2453 }
f1dc5600 2454#endif
bde748a4
VN		 2455 if (AR_SREV_9271(ah))
2456 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2457 else
2458 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2459
e7594072 2460 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2461 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2462 else
2463 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2464
608b88cb 2465 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 2466 pCap->reg_cap =
2467 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2468 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2469 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2470 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 2471 } else {
f1dc5600
S		 2472 pCap->reg_cap =
2473 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2474 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 2475 }
f078f209 2476
ebb90cfc
SB		 2477 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2478 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2479 AR_SREV_5416(ah))
2480 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 2481
2482 pCap->num_antcfg_5ghz =
f74df6fb 2483 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 2484 pCap->num_antcfg_2ghz =
f74df6fb 2485 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 2486
fe12946e 2487 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 2488 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 2489 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2490 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 2491
8c8f9ba7 2492 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 2493 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2494 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 2495 } else {
766ec4a9 2496 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 2497 }
22f25d0d 2498 } else {
766ec4a9 2499 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 2500 }
a9a29ce6 2501
ceb26445 2502 if (AR_SREV_9300_20_OR_LATER(ah)) {
1adf02ff 2503 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
ceb26445
VT		 2504 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2505 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2506 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3
VT		 2507 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2508 } else {
2509 pCap->tx_desc_len = sizeof(struct ath_desc);
ceb26445 2510 }
1adf02ff 2511
a9a29ce6 2512 return 0;
f078f209
LR		 2513}
2514
cbe61d8a 2515bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2516 u32 capability, u32 *result)
f078f209 2517{
608b88cb 2518 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 2519 switch (type) {
2520 case ATH9K_CAP_CIPHER:
2521 switch (capability) {
2522 case ATH9K_CIPHER_AES_CCM:
2523 case ATH9K_CIPHER_AES_OCB:
2524 case ATH9K_CIPHER_TKIP:
2525 case ATH9K_CIPHER_WEP:
2526 case ATH9K_CIPHER_MIC:
2527 case ATH9K_CIPHER_CLR:
2528 return true;
2529 default:
2530 return false;
2531 }
2532 case ATH9K_CAP_TKIP_MIC:
2533 switch (capability) {
2534 case 0:
2535 return true;
2536 case 1:
2660b81a 2537 return (ah->sta_id1_defaults &
f1dc5600
S		 2538 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2539 false;
2540 }
2541 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 2542 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 2543 false : true;
f1dc5600
S		 2544 case ATH9K_CAP_MCAST_KEYSRCH:
2545 switch (capability) {
2546 case 0:
2547 return true;
2548 case 1:
2549 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2550 return false;
2551 } else {
2660b81a 2552 return (ah->sta_id1_defaults &
f1dc5600
S		 2553 AR_STA_ID1_MCAST_KSRCH) ? true :
2554 false;
2555 }
2556 }
2557 return false;
f1dc5600
S		 2558 case ATH9K_CAP_TXPOW:
2559 switch (capability) {
2560 case 0:
2561 return 0;
2562 case 1:
608b88cb 2563 *result = regulatory->power_limit;
f1dc5600
S		 2564 return 0;
2565 case 2:
608b88cb 2566 *result = regulatory->max_power_level;
f1dc5600
S		 2567 return 0;
2568 case 3:
608b88cb 2569 *result = regulatory->tp_scale;
f1dc5600
S		 2570 return 0;
2571 }
2572 return false;
8bd1d07f
SB		 2573 case ATH9K_CAP_DS:
2574 return (AR_SREV_9280_20_OR_LATER(ah) &&
2575 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2576 ? false : true;
f1dc5600
S		 2577 default:
2578 return false;
f078f209 2579 }
f078f209 2580}
7322fd19 2581EXPORT_SYMBOL(ath9k_hw_getcapability);
f078f209 2582
cbe61d8a 2583bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2584 u32 capability, u32 setting, int *status)
f078f209 2585{
f1dc5600
S		 2586 switch (type) {
2587 case ATH9K_CAP_TKIP_MIC:
2588 if (setting)
2660b81a 2589 ah->sta_id1_defaults |=
f1dc5600
S		 2590 AR_STA_ID1_CRPT_MIC_ENABLE;
2591 else
2660b81a 2592 ah->sta_id1_defaults &=
f1dc5600
S		 2593 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2594 return true;
f1dc5600
S		 2595 case ATH9K_CAP_MCAST_KEYSRCH:
2596 if (setting)
2660b81a 2597 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2598 else
2660b81a 2599 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2600 return true;
f1dc5600
S		 2601 default:
2602 return false;
f078f209
LR		 2603 }
2604}
7322fd19 2605EXPORT_SYMBOL(ath9k_hw_setcapability);
f078f209 2606
f1dc5600
S		 2607/****************************/
2608/* GPIO / RFKILL / Antennae */
2609/****************************/
f078f209 2610
cbe61d8a 2611static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2612 u32 gpio, u32 type)
2613{
2614 int addr;
2615 u32 gpio_shift, tmp;
f078f209 2616
f1dc5600
S		 2617 if (gpio > 11)
2618 addr = AR_GPIO_OUTPUT_MUX3;
2619 else if (gpio > 5)
2620 addr = AR_GPIO_OUTPUT_MUX2;
2621 else
2622 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2623
f1dc5600 2624 gpio_shift = (gpio % 6) * 5;
f078f209 2625
f1dc5600
S		 2626 if (AR_SREV_9280_20_OR_LATER(ah)
2627 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2628 REG_RMW(ah, addr, (type << gpio_shift),
2629 (0x1f << gpio_shift));
f078f209 2630 } else {
f1dc5600
S		 2631 tmp = REG_READ(ah, addr);
2632 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2633 tmp &= ~(0x1f << gpio_shift);
2634 tmp |= (type << gpio_shift);
2635 REG_WRITE(ah, addr, tmp);
f078f209 2636 }
f078f209
LR		 2637}
2638
cbe61d8a 2639void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2640{
f1dc5600 2641 u32 gpio_shift;
f078f209 2642
9680e8a3 2643 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2644
f1dc5600 2645 gpio_shift = gpio << 1;
f078f209 2646
f1dc5600
S		 2647 REG_RMW(ah,
2648 AR_GPIO_OE_OUT,
2649 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2650 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2651}
7322fd19 2652EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2653
cbe61d8a 2654u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2655{
cb33c412
SB		 2656#define MS_REG_READ(x, y) \
2657 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2658
2660b81a 2659 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2660 return 0xffffffff;
f078f209 2661
783dfca1
FF		 2662 if (AR_SREV_9300_20_OR_LATER(ah))
2663 return MS_REG_READ(AR9300, gpio) != 0;
2664 else if (AR_SREV_9271(ah))
5b5fa355
S		 2665 return MS_REG_READ(AR9271, gpio) != 0;
2666 else if (AR_SREV_9287_10_OR_LATER(ah))
ac88b6ec
VN		 2667 return MS_REG_READ(AR9287, gpio) != 0;
2668 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2669 return MS_REG_READ(AR9285, gpio) != 0;
2670 else if (AR_SREV_9280_10_OR_LATER(ah))
2671 return MS_REG_READ(AR928X, gpio) != 0;
2672 else
2673 return MS_REG_READ(AR, gpio) != 0;
f078f209 2674}
7322fd19 2675EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2676
cbe61d8a 2677void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2678 u32 ah_signal_type)
f078f209 2679{
f1dc5600 2680 u32 gpio_shift;
f078f209 2681
f1dc5600 2682 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 2683
f1dc5600 2684 gpio_shift = 2 * gpio;
f078f209 2685
f1dc5600
S		 2686 REG_RMW(ah,
2687 AR_GPIO_OE_OUT,
2688 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2689 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2690}
7322fd19 2691EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2692
cbe61d8a 2693void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2694{
5b5fa355
S		 2695 if (AR_SREV_9271(ah))
2696 val = ~val;
2697
f1dc5600
S		 2698 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2699 AR_GPIO_BIT(gpio));
f078f209 2700}
7322fd19 2701EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2702
cbe61d8a 2703u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2704{
f1dc5600 2705 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2706}
7322fd19 2707EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2708
cbe61d8a 2709void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2710{
f1dc5600 2711 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2712}
7322fd19 2713EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2714
f1dc5600
S		 2715/*********************/
2716/* General Operation */
2717/*********************/
2718
cbe61d8a 2719u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2720{
f1dc5600
S		 2721 u32 bits = REG_READ(ah, AR_RX_FILTER);
2722 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2723
f1dc5600
S		 2724 if (phybits & AR_PHY_ERR_RADAR)
2725 bits |= ATH9K_RX_FILTER_PHYRADAR;
2726 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2727 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2728
f1dc5600 2729 return bits;
f078f209 2730}
7322fd19 2731EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2732
cbe61d8a 2733void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2734{
f1dc5600 2735 u32 phybits;
f078f209 2736
7ea310be
S		 2737 REG_WRITE(ah, AR_RX_FILTER, bits);
2738
f1dc5600
S		 2739 phybits = 0;
2740 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2741 phybits |= AR_PHY_ERR_RADAR;
2742 if (bits & ATH9K_RX_FILTER_PHYERR)
2743 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2744 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2745
f1dc5600
S		 2746 if (phybits)
2747 REG_WRITE(ah, AR_RXCFG,
2748 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2749 else
2750 REG_WRITE(ah, AR_RXCFG,
2751 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2752}
7322fd19 2753EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2754
cbe61d8a 2755bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2756{
63a75b91
SB		 2757 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2758 return false;
2759
2760 ath9k_hw_init_pll(ah, NULL);
2761 return true;
f1dc5600 2762}
7322fd19 2763EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2764
cbe61d8a 2765bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2766{
9ecdef4b 2767 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2768 return false;
f078f209 2769
63a75b91
SB		 2770 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2771 return false;
2772
2773 ath9k_hw_init_pll(ah, NULL);
2774 return true;
f078f209 2775}
7322fd19 2776EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2777
8fbff4b8 2778void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 2779{
608b88cb 2780 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2781 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2782 struct ieee80211_channel *channel = chan->chan;
f078f209 2783
608b88cb 2784 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2785
8fbff4b8 2786 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2787 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2788 channel->max_antenna_gain * 2,
2789 channel->max_power * 2,
2790 min((u32) MAX_RATE_POWER,
608b88cb 2791 (u32) regulatory->power_limit));
6f255425 2792}
7322fd19 2793EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2794
cbe61d8a 2795void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 2796{
1510718d 2797 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
f078f209 2798}
7322fd19 2799EXPORT_SYMBOL(ath9k_hw_setmac);
f078f209 2800
cbe61d8a 2801void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2802{
2660b81a 2803 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2804}
7322fd19 2805EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2806
cbe61d8a 2807void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2808{
f1dc5600
S		 2809 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2810 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2811}
7322fd19 2812EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2813
f2b2143e 2814void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2815{
1510718d
LR		 2816 struct ath_common *common = ath9k_hw_common(ah);
2817
2818 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2819 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2820 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2821}
7322fd19 2822EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2823
cbe61d8a 2824u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2825{
f1dc5600 2826 u64 tsf;
f078f209 2827
f1dc5600
S		 2828 tsf = REG_READ(ah, AR_TSF_U32);
2829 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 2830
f1dc5600
S		 2831 return tsf;
2832}
7322fd19 2833EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2834
cbe61d8a 2835void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2836{
27abe060 2837 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2838 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2839}
7322fd19 2840EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2841
cbe61d8a 2842void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2843{
f9b604f6
GJ		 2844 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2845 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 2846 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2847 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2848
f1dc5600
S		 2849 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2850}
7322fd19 2851EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2852
54e4cec6 2853void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2854{
f1dc5600 2855 if (setting)
2660b81a 2856 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2857 else
2660b81a 2858 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2859}
7322fd19 2860EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2861
30cbd422
LR		 2862/*
2863 * Extend 15-bit time stamp from rx descriptor to
2864 * a full 64-bit TSF using the current h/w TSF.
2865*/
2866u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2867{
2868 u64 tsf;
2869
2870 tsf = ath9k_hw_gettsf64(ah);
2871 if ((tsf & 0x7fff) < rstamp)
2872 tsf -= 0x8000;
2873 return (tsf & ~0x7fff) | rstamp;
2874}
2875EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2876
25c56eec 2877void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2878{
25c56eec 2879 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2880 u32 macmode;
2881
25c56eec 2882 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2883 macmode = AR_2040_JOINED_RX_CLEAR;
2884 else
2885 macmode = 0;
f078f209 2886
f1dc5600 2887 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2888}
ff155a45
VT		 2889
2890/* HW Generic timers configuration */
2891
2892static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2893{
2894 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2895 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2896 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2897 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2898 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2899 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2900 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2901 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2902 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2903 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2904 AR_NDP2_TIMER_MODE, 0x0002},
2905 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2906 AR_NDP2_TIMER_MODE, 0x0004},
2907 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2908 AR_NDP2_TIMER_MODE, 0x0008},
2909 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2910 AR_NDP2_TIMER_MODE, 0x0010},
2911 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2912 AR_NDP2_TIMER_MODE, 0x0020},
2913 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2914 AR_NDP2_TIMER_MODE, 0x0040},
2915 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2916 AR_NDP2_TIMER_MODE, 0x0080}
2917};
2918
2919/* HW generic timer primitives */
2920
2921/* compute and clear index of rightmost 1 */
2922static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2923{
2924 u32 b;
2925
2926 b = *mask;
2927 b &= (0-b);
2928 *mask &= ~b;
2929 b *= debruijn32;
2930 b >>= 27;
2931
2932 return timer_table->gen_timer_index[b];
2933}
2934
1773912b 2935u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2936{
2937 return REG_READ(ah, AR_TSF_L32);
2938}
7322fd19 2939EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2940
2941struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2942 void (*trigger)(void *),
2943 void (*overflow)(void *),
2944 void *arg,
2945 u8 timer_index)
2946{
2947 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2948 struct ath_gen_timer *timer;
2949
2950 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2951
2952 if (timer == NULL) {
c46917bb
LR		 2953 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2954 "Failed to allocate memory"
2955 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 2956 return NULL;
2957 }
2958
2959 /* allocate a hardware generic timer slot */
2960 timer_table->timers[timer_index] = timer;
2961 timer->index = timer_index;
2962 timer->trigger = trigger;
2963 timer->overflow = overflow;
2964 timer->arg = arg;
2965
2966 return timer;
2967}
7322fd19 2968EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2969
cd9bf689
LR		 2970void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2971 struct ath_gen_timer *timer,
2972 u32 timer_next,
2973 u32 timer_period)
ff155a45
VT		 2974{
2975 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2976 u32 tsf;
2977
2978 BUG_ON(!timer_period);
2979
2980 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2981
2982 tsf = ath9k_hw_gettsf32(ah);
2983
c46917bb
LR		 2984 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2985 "curent tsf %x period %x"
2986 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 2987
2988 /*
2989 * Pull timer_next forward if the current TSF already passed it
2990 * because of software latency
2991 */
2992 if (timer_next < tsf)
2993 timer_next = tsf + timer_period;
2994
2995 /*
2996 * Program generic timer registers
2997 */
2998 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2999 timer_next);
3000 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3001 timer_period);
3002 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3003 gen_tmr_configuration[timer->index].mode_mask);
3004
3005 /* Enable both trigger and thresh interrupt masks */
3006 REG_SET_BIT(ah, AR_IMR_S5,
3007 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3008 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 3009}
7322fd19 3010EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3011
cd9bf689 3012void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3013{
3014 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3015
3016 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3017 (timer->index >= ATH_MAX_GEN_TIMER)) {
3018 return;
3019 }
3020
3021 /* Clear generic timer enable bits. */
3022 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3023 gen_tmr_configuration[timer->index].mode_mask);
3024
3025 /* Disable both trigger and thresh interrupt masks */
3026 REG_CLR_BIT(ah, AR_IMR_S5,
3027 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3028 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3029
3030 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3031}
7322fd19 3032EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3033
3034void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3035{
3036 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3037
3038 /* free the hardware generic timer slot */
3039 timer_table->timers[timer->index] = NULL;
3040 kfree(timer);
3041}
7322fd19 3042EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3043
3044/*
3045 * Generic Timer Interrupts handling
3046 */
3047void ath_gen_timer_isr(struct ath_hw *ah)
3048{
3049 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3050 struct ath_gen_timer *timer;
c46917bb 3051 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3052 u32 trigger_mask, thresh_mask, index;
3053
3054 /* get hardware generic timer interrupt status */
3055 trigger_mask = ah->intr_gen_timer_trigger;
3056 thresh_mask = ah->intr_gen_timer_thresh;
3057 trigger_mask &= timer_table->timer_mask.val;
3058 thresh_mask &= timer_table->timer_mask.val;
3059
3060 trigger_mask &= ~thresh_mask;
3061
3062 while (thresh_mask) {
3063 index = rightmost_index(timer_table, &thresh_mask);
3064 timer = timer_table->timers[index];
3065 BUG_ON(!timer);
c46917bb
LR		 3066 ath_print(common, ATH_DBG_HWTIMER,
3067 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 3068 timer->overflow(timer->arg);
3069 }
3070
3071 while (trigger_mask) {
3072 index = rightmost_index(timer_table, &trigger_mask);
3073 timer = timer_table->timers[index];
3074 BUG_ON(!timer);
c46917bb
LR		 3075 ath_print(common, ATH_DBG_HWTIMER,
3076 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3077 timer->trigger(timer->arg);
3078 }
3079}
7322fd19 3080EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3081
05020d23
S		 3082/********/
3083/* HTC */
3084/********/
3085
3086void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3087{
3088 ah->htc_reset_init = true;
3089}
3090EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3091
2da4f01a
LR		 3092static struct {
3093 u32 version;
3094 const char * name;
3095} ath_mac_bb_names[] = {
3096 /* Devices with external radios */
3097 { AR_SREV_VERSION_5416_PCI, "5416" },
3098 { AR_SREV_VERSION_5416_PCIE, "5418" },
3099 { AR_SREV_VERSION_9100, "9100" },
3100 { AR_SREV_VERSION_9160, "9160" },
3101 /* Single-chip solutions */
3102 { AR_SREV_VERSION_9280, "9280" },
3103 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3104 { AR_SREV_VERSION_9287, "9287" },
3105 { AR_SREV_VERSION_9271, "9271" },
2da4f01a
LR		 3106};
3107
3108/* For devices with external radios */
3109static struct {
3110 u16 version;
3111 const char * name;
3112} ath_rf_names[] = {
3113 { 0, "5133" },
3114 { AR_RAD5133_SREV_MAJOR, "5133" },
3115 { AR_RAD5122_SREV_MAJOR, "5122" },
3116 { AR_RAD2133_SREV_MAJOR, "2133" },
3117 { AR_RAD2122_SREV_MAJOR, "2122" }
3118};
3119
3120/*
3121 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3122 */
f934c4d9 3123static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3124{
3125 int i;
3126
3127 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3128 if (ath_mac_bb_names[i].version == mac_bb_version) {
3129 return ath_mac_bb_names[i].name;
3130 }
3131 }
3132
3133 return "????";
3134}
2da4f01a
LR		 3135
3136/*
3137 * Return the RF name. "????" is returned if the RF is unknown.
3138 * Used for devices with external radios.
3139 */
f934c4d9 3140static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3141{
3142 int i;
3143
3144 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3145 if (ath_rf_names[i].version == rf_version) {
3146 return ath_rf_names[i].name;
3147 }
3148 }
3149
3150 return "????";
3151}
f934c4d9
LR		 3152
3153void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3154{
3155 int used;
3156
3157 /* chipsets >= AR9280 are single-chip */
3158 if (AR_SREV_9280_10_OR_LATER(ah)) {
3159 used = snprintf(hw_name, len,
3160 "Atheros AR%s Rev:%x",
3161 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3162 ah->hw_version.macRev);
3163 }
3164 else {
3165 used = snprintf(hw_name, len,
3166 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3167 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3168 ah->hw_version.macRev,
3169 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3170 AR_RADIO_SREV_MAJOR)),
3171 ah->hw_version.phyRev);
3172 }
3173
3174 hw_name[used] = '\0';
3175}
3176EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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