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ath9k_hw: bail out early on ath9k_hw_init_rf()
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
af03abec 20#include "hw.h"
cfe8cba9 21#include "rc.h"
f078f209
LR		 22#include "initvals.h"
23
4febf7b8
LR		 24#define ATH9K_CLOCK_RATE_CCK 22
25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 27
cbe61d8a 28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
25c56eec 29static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
cbe61d8a 30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072 31 struct ar5416_eeprom_def *pEepData,
f1dc5600 32 u32 reg, u32 value);
cbe61d8a
S		 33static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
34static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
f078f209 35
7322fd19
LR		 36MODULE_AUTHOR("Atheros Communications");
37MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
38MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
39MODULE_LICENSE("Dual BSD/GPL");
40
41static int __init ath9k_init(void)
42{
43 return 0;
44}
45module_init(ath9k_init);
46
47static void __exit ath9k_exit(void)
48{
49 return;
50}
51module_exit(ath9k_exit);
52
f1dc5600
S		 53/********************/
54/* Helper Functions */
55/********************/
f078f209 56
cbe61d8a 57static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
f1dc5600 58{
b002a4a9 59 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 60
2660b81a 61 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 62 return clks / ATH9K_CLOCK_RATE_CCK;
63 if (conf->channel->band == IEEE80211_BAND_2GHZ)
64 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
cbe61d8a 65
4febf7b8 66 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 67}
f078f209 68
cbe61d8a 69static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
f1dc5600 70{
b002a4a9 71 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 72
4febf7b8 73 if (conf_is_ht40(conf))
f1dc5600
S		 74 return ath9k_hw_mac_usec(ah, clks) / 2;
75 else
76 return ath9k_hw_mac_usec(ah, clks);
77}
f078f209 78
cbe61d8a 79static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 80{
b002a4a9 81 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 82
2660b81a 83 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 84 return usecs *ATH9K_CLOCK_RATE_CCK;
85 if (conf->channel->band == IEEE80211_BAND_2GHZ)
86 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
87 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 88}
89
cbe61d8a 90static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 91{
b002a4a9 92 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 93
4febf7b8 94 if (conf_is_ht40(conf))
f1dc5600
S		 95 return ath9k_hw_mac_clks(ah, usecs) * 2;
96 else
97 return ath9k_hw_mac_clks(ah, usecs);
98}
f078f209 99
0caa7b14 100bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 101{
102 int i;
103
0caa7b14
S		 104 BUG_ON(timeout < AH_TIME_QUANTUM);
105
106 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 107 if ((REG_READ(ah, reg) & mask) == val)
108 return true;
109
110 udelay(AH_TIME_QUANTUM);
111 }
04bd4638 112
c46917bb
LR		 113 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
114 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
115 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 116
f1dc5600 117 return false;
f078f209 118}
7322fd19 119EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 120
121u32 ath9k_hw_reverse_bits(u32 val, u32 n)
122{
123 u32 retval;
124 int i;
125
126 for (i = 0, retval = 0; i < n; i++) {
127 retval = (retval << 1) | (val & 1);
128 val >>= 1;
129 }
130 return retval;
131}
132
cbe61d8a 133bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 134 u16 flags, u16 *low,
135 u16 *high)
f078f209 136{
2660b81a 137 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 138
f1dc5600
S		 139 if (flags & CHANNEL_5GHZ) {
140 *low = pCap->low_5ghz_chan;
141 *high = pCap->high_5ghz_chan;
142 return true;
f078f209 143 }
f1dc5600
S		 144 if ((flags & CHANNEL_2GHZ)) {
145 *low = pCap->low_2ghz_chan;
146 *high = pCap->high_2ghz_chan;
147 return true;
148 }
149 return false;
f078f209
LR		 150}
151
cbe61d8a 152u16 ath9k_hw_computetxtime(struct ath_hw *ah,
4f0fc7c3 153 const struct ath_rate_table *rates,
f1dc5600
S		 154 u32 frameLen, u16 rateix,
155 bool shortPreamble)
f078f209 156{
f1dc5600
S		 157 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
158 u32 kbps;
f078f209 159
e63835b0 160 kbps = rates->info[rateix].ratekbps;
f078f209 161
f1dc5600
S		 162 if (kbps == 0)
163 return 0;
f078f209 164
f1dc5600 165 switch (rates->info[rateix].phy) {
46d14a58 166 case WLAN_RC_PHY_CCK:
f1dc5600 167 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
e63835b0 168 if (shortPreamble && rates->info[rateix].short_preamble)
f1dc5600
S		 169 phyTime >>= 1;
170 numBits = frameLen << 3;
171 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
172 break;
46d14a58 173 case WLAN_RC_PHY_OFDM:
2660b81a 174 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 175 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
176 numBits = OFDM_PLCP_BITS + (frameLen << 3);
177 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
178 txTime = OFDM_SIFS_TIME_QUARTER
179 + OFDM_PREAMBLE_TIME_QUARTER
180 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 181 } else if (ah->curchan &&
182 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 183 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
184 numBits = OFDM_PLCP_BITS + (frameLen << 3);
185 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
186 txTime = OFDM_SIFS_TIME_HALF +
187 OFDM_PREAMBLE_TIME_HALF
188 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
189 } else {
190 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
191 numBits = OFDM_PLCP_BITS + (frameLen << 3);
192 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
193 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
194 + (numSymbols * OFDM_SYMBOL_TIME);
195 }
196 break;
197 default:
c46917bb
LR		 198 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
199 "Unknown phy %u (rate ix %u)\n",
200 rates->info[rateix].phy, rateix);
f1dc5600
S		 201 txTime = 0;
202 break;
203 }
f078f209 204
f1dc5600
S		 205 return txTime;
206}
7322fd19 207EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 208
cbe61d8a 209void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 210 struct ath9k_channel *chan,
211 struct chan_centers *centers)
f078f209 212{
f1dc5600 213 int8_t extoff;
f078f209 214
f1dc5600
S		 215 if (!IS_CHAN_HT40(chan)) {
216 centers->ctl_center = centers->ext_center =
217 centers->synth_center = chan->channel;
218 return;
f078f209 219 }
f078f209 220
f1dc5600
S		 221 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
222 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
223 centers->synth_center =
224 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
225 extoff = 1;
226 } else {
227 centers->synth_center =
228 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
229 extoff = -1;
230 }
f078f209 231
f1dc5600
S		 232 centers->ctl_center =
233 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 234 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 235 centers->ext_center =
6420014c 236 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 237}
238
f1dc5600
S		 239/******************/
240/* Chip Revisions */
241/******************/
242
cbe61d8a 243static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 244{
f1dc5600 245 u32 val;
f078f209 246
f1dc5600 247 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 248
f1dc5600
S		 249 if (val == 0xFF) {
250 val = REG_READ(ah, AR_SREV);
d535a42a
S		 251 ah->hw_version.macVersion =
252 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
253 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 254 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 255 } else {
256 if (!AR_SREV_9100(ah))
d535a42a 257 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 258
d535a42a 259 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 260
d535a42a 261 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 262 ah->is_pciexpress = true;
f1dc5600 263 }
f078f209
LR		 264}
265
cbe61d8a 266static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 267{
f1dc5600
S		 268 u32 val;
269 int i;
f078f209 270
f1dc5600 271 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 272
f1dc5600
S		 273 for (i = 0; i < 8; i++)
274 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
275 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
276 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 277
f1dc5600 278 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 279}
280
f1dc5600
S		 281/************************************/
282/* HW Attach, Detach, Init Routines */
283/************************************/
284
cbe61d8a 285static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 286{
feed029c 287 if (AR_SREV_9100(ah))
f1dc5600 288 return;
f078f209 289
f1dc5600
S		 290 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
298 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 299
f1dc5600 300 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 301}
302
cbe61d8a 303static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 304{
c46917bb 305 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 306 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
307 u32 regHold[2];
308 u32 patternData[4] = { 0x55555555,
309 0xaaaaaaaa,
310 0x66666666,
311 0x99999999 };
312 int i, j;
f078f209 313
f1dc5600
S		 314 for (i = 0; i < 2; i++) {
315 u32 addr = regAddr[i];
316 u32 wrData, rdData;
f078f209 317
f1dc5600
S		 318 regHold[i] = REG_READ(ah, addr);
319 for (j = 0; j < 0x100; j++) {
320 wrData = (j << 16) | j;
321 REG_WRITE(ah, addr, wrData);
322 rdData = REG_READ(ah, addr);
323 if (rdData != wrData) {
c46917bb
LR		 324 ath_print(common, ATH_DBG_FATAL,
325 "address test failed "
326 "addr: 0x%08x - wr:0x%08x != "
327 "rd:0x%08x\n",
328 addr, wrData, rdData);
f1dc5600
S		 329 return false;
330 }
331 }
332 for (j = 0; j < 4; j++) {
333 wrData = patternData[j];
334 REG_WRITE(ah, addr, wrData);
335 rdData = REG_READ(ah, addr);
336 if (wrData != rdData) {
c46917bb
LR		 337 ath_print(common, ATH_DBG_FATAL,
338 "address test failed "
339 "addr: 0x%08x - wr:0x%08x != "
340 "rd:0x%08x\n",
341 addr, wrData, rdData);
f1dc5600
S		 342 return false;
343 }
f078f209 344 }
f1dc5600 345 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 346 }
f1dc5600 347 udelay(100);
cbe61d8a 348
f078f209
LR		 349 return true;
350}
351
f1dc5600 352static const char *ath9k_hw_devname(u16 devid)
f078f209 353{
f1dc5600
S		 354 switch (devid) {
355 case AR5416_DEVID_PCI:
f1dc5600 356 return "Atheros 5416";
392dff83
BP		 357 case AR5416_DEVID_PCIE:
358 return "Atheros 5418";
f1dc5600
S		 359 case AR9160_DEVID_PCI:
360 return "Atheros 9160";
0c1aa495
GJ		 361 case AR5416_AR9100_DEVID:
362 return "Atheros 9100";
f1dc5600
S		 363 case AR9280_DEVID_PCI:
364 case AR9280_DEVID_PCIE:
365 return "Atheros 9280";
e7594072
SB		 366 case AR9285_DEVID_PCIE:
367 return "Atheros 9285";
ac88b6ec
VN		 368 case AR5416_DEVID_AR9287_PCI:
369 case AR5416_DEVID_AR9287_PCIE:
370 return "Atheros 9287";
f078f209
LR		 371 }
372
f1dc5600
S		 373 return NULL;
374}
f078f209 375
b8b0f377 376static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 377{
378 int i;
f078f209 379
2660b81a
S		 380 ah->config.dma_beacon_response_time = 2;
381 ah->config.sw_beacon_response_time = 10;
382 ah->config.additional_swba_backoff = 0;
383 ah->config.ack_6mb = 0x0;
384 ah->config.cwm_ignore_extcca = 0;
385 ah->config.pcie_powersave_enable = 0;
2660b81a 386 ah->config.pcie_clock_req = 0;
2660b81a
S		 387 ah->config.pcie_waen = 0;
388 ah->config.analog_shiftreg = 1;
389 ah->config.ht_enable = 1;
390 ah->config.ofdm_trig_low = 200;
391 ah->config.ofdm_trig_high = 500;
392 ah->config.cck_trig_high = 200;
393 ah->config.cck_trig_low = 100;
394 ah->config.enable_ani = 1;
1cf6873a 395 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
2660b81a 396 ah->config.antenna_switch_swap = 0;
f078f209 397
f1dc5600 398 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 399 ah->config.spurchans[i][0] = AR_NO_SPUR;
400 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 401 }
402
0ef1f168 403 ah->config.intr_mitigation = true;
6158425b
LR		 404
405 /*
406 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
407 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
408 * This means we use it for all AR5416 devices, and the few
409 * minor PCI AR9280 devices out there.
410 *
411 * Serialization is required because these devices do not handle
412 * well the case of two concurrent reads/writes due to the latency
413 * involved. During one read/write another read/write can be issued
414 * on another CPU while the previous read/write may still be working
415 * on our hardware, if we hit this case the hardware poops in a loop.
416 * We prevent this by serializing reads and writes.
417 *
418 * This issue is not present on PCI-Express devices or pre-AR5416
419 * devices (legacy, 802.11abg).
420 */
421 if (num_possible_cpus() > 1)
2d6a5e95 422 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209 423}
7322fd19 424EXPORT_SYMBOL(ath9k_hw_init);
f078f209 425
50aca25b 426static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 427{
608b88cb
LR		 428 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
429
430 regulatory->country_code = CTRY_DEFAULT;
431 regulatory->power_limit = MAX_RATE_POWER;
432 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
433
d535a42a 434 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 435 ah->hw_version.subvendorid = 0;
f078f209
LR		 436
437 ah->ah_flags = 0;
8df5d1b7 438 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
d535a42a 439 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
f078f209
LR		 440 if (!AR_SREV_9100(ah))
441 ah->ah_flags = AH_USE_EEPROM;
442
2660b81a 443 ah->atim_window = 0;
2660b81a
S		 444 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
445 ah->beacon_interval = 100;
446 ah->enable_32kHz_clock = DONT_USE_32KHZ;
447 ah->slottime = (u32) -1;
448 ah->acktimeout = (u32) -1;
449 ah->ctstimeout = (u32) -1;
450 ah->globaltxtimeout = (u32) -1;
451
452 ah->gbeacon_rate = 0;
f078f209 453
cbdec975 454 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 455}
456
cbe61d8a 457static int ath9k_hw_rfattach(struct ath_hw *ah)
f078f209 458{
f1dc5600
S		 459 bool rfStatus = false;
460 int ecode = 0;
f078f209 461
f1dc5600
S		 462 rfStatus = ath9k_hw_init_rf(ah, &ecode);
463 if (!rfStatus) {
c46917bb
LR		 464 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
465 "RF setup failed, status: %u\n", ecode);
f1dc5600
S		 466 return ecode;
467 }
f078f209 468
f1dc5600 469 return 0;
f078f209
LR		 470}
471
cbe61d8a 472static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 473{
f1dc5600
S		 474 u32 val;
475
476 REG_WRITE(ah, AR_PHY(0), 0x00000007);
477
478 val = ath9k_hw_get_radiorev(ah);
479 switch (val & AR_RADIO_SREV_MAJOR) {
480 case 0:
481 val = AR_RAD5133_SREV_MAJOR;
482 break;
483 case AR_RAD5133_SREV_MAJOR:
484 case AR_RAD5122_SREV_MAJOR:
485 case AR_RAD2133_SREV_MAJOR:
486 case AR_RAD2122_SREV_MAJOR:
487 break;
f078f209 488 default:
c46917bb
LR		 489 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
490 "Radio Chip Rev 0x%02X not supported\n",
491 val & AR_RADIO_SREV_MAJOR);
f1dc5600 492 return -EOPNOTSUPP;
f078f209 493 }
f078f209 494
d535a42a 495 ah->hw_version.analog5GhzRev = val;
f078f209 496
f1dc5600 497 return 0;
f078f209
LR		 498}
499
cbe61d8a 500static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 501{
1510718d 502 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 503 u32 sum;
504 int i;
505 u16 eeval;
f078f209
LR		 506
507 sum = 0;
508 for (i = 0; i < 3; i++) {
f74df6fb 509 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 510 sum += eeval;
1510718d
LR		 511 common->macaddr[2 * i] = eeval >> 8;
512 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 513 }
d8baa939 514 if (sum == 0 || sum == 0xffff * 3)
f078f209 515 return -EADDRNOTAVAIL;
f078f209
LR		 516
517 return 0;
518}
519
cbe61d8a 520static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 521{
522 u32 rxgain_type;
9f804202 523
f74df6fb
S		 524 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
525 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 526
527 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 528 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 529 ar9280Modes_backoff_13db_rxgain_9280_2,
530 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
531 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 532 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 533 ar9280Modes_backoff_23db_rxgain_9280_2,
534 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
535 else
2660b81a 536 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 537 ar9280Modes_original_rxgain_9280_2,
538 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 539 } else {
2660b81a 540 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 541 ar9280Modes_original_rxgain_9280_2,
542 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 543 }
9f804202
SB		 544}
545
cbe61d8a 546static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 547{
548 u32 txgain_type;
9f804202 549
f74df6fb
S		 550 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
551 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 552
553 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 554 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 555 ar9280Modes_high_power_tx_gain_9280_2,
556 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
557 else
2660b81a 558 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 559 ar9280Modes_original_tx_gain_9280_2,
560 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 561 } else {
2660b81a 562 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 563 ar9280Modes_original_tx_gain_9280_2,
564 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 565 }
9f804202
SB		 566}
567
f637cfd6 568static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 569{
f1dc5600 570 int ecode;
f078f209 571
d8baa939 572 if (!ath9k_hw_chip_test(ah))
f1dc5600 573 return -ENODEV;
f078f209 574
f1dc5600
S		 575 ecode = ath9k_hw_rf_claim(ah);
576 if (ecode != 0)
f078f209 577 return ecode;
f078f209 578
f637cfd6 579 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 580 if (ecode != 0)
581 return ecode;
7d01b221 582
c46917bb
LR		 583 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
584 "Eeprom VER: %d, REV: %d\n",
585 ah->eep_ops->get_eeprom_ver(ah),
586 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 587
f1dc5600
S		 588 ecode = ath9k_hw_rfattach(ah);
589 if (ecode != 0)
590 return ecode;
f078f209 591
f1dc5600
S		 592 if (!AR_SREV_9100(ah)) {
593 ath9k_hw_ani_setup(ah);
f637cfd6 594 ath9k_hw_ani_init(ah);
f078f209
LR		 595 }
596
f078f209
LR		 597 return 0;
598}
599
ee2bb460
LR		 600static bool ath9k_hw_devid_supported(u16 devid)
601{
602 switch (devid) {
603 case AR5416_DEVID_PCI:
604 case AR5416_DEVID_PCIE:
605 case AR5416_AR9100_DEVID:
606 case AR9160_DEVID_PCI:
607 case AR9280_DEVID_PCI:
608 case AR9280_DEVID_PCIE:
609 case AR9285_DEVID_PCIE:
610 case AR5416_DEVID_AR9287_PCI:
611 case AR5416_DEVID_AR9287_PCIE:
7976b426 612 case AR9271_USB:
ee2bb460
LR		 613 return true;
614 default:
615 break;
616 }
617 return false;
618}
619
f9d4a668
LR		 620static bool ath9k_hw_macversion_supported(u32 macversion)
621{
622 switch (macversion) {
623 case AR_SREV_VERSION_5416_PCI:
624 case AR_SREV_VERSION_5416_PCIE:
625 case AR_SREV_VERSION_9160:
626 case AR_SREV_VERSION_9100:
627 case AR_SREV_VERSION_9280:
628 case AR_SREV_VERSION_9285:
629 case AR_SREV_VERSION_9287:
d7e7d229 630 case AR_SREV_VERSION_9271:
7976b426 631 return true;
f9d4a668
LR		 632 default:
633 break;
634 }
635 return false;
636}
637
aa4058ae 638static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
f078f209 639{
f1dc5600
S		 640 if (AR_SREV_9160_10_OR_LATER(ah)) {
641 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a
S		 642 ah->iq_caldata.calData = &iq_cal_single_sample;
643 ah->adcgain_caldata.calData =
f1dc5600 644 &adc_gain_cal_single_sample;
2660b81a 645 ah->adcdc_caldata.calData =
f1dc5600 646 &adc_dc_cal_single_sample;
2660b81a 647 ah->adcdc_calinitdata.calData =
f1dc5600
S		 648 &adc_init_dc_cal;
649 } else {
2660b81a
S		 650 ah->iq_caldata.calData = &iq_cal_multi_sample;
651 ah->adcgain_caldata.calData =
f1dc5600 652 &adc_gain_cal_multi_sample;
2660b81a 653 ah->adcdc_caldata.calData =
f1dc5600 654 &adc_dc_cal_multi_sample;
2660b81a 655 ah->adcdc_calinitdata.calData =
f1dc5600
S		 656 &adc_init_dc_cal;
657 }
2660b81a 658 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
f1dc5600 659 }
aa4058ae 660}
f078f209 661
aa4058ae
LR		 662static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
663{
d7e7d229 664 if (AR_SREV_9271(ah)) {
8564328d
LR		 665 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
666 ARRAY_SIZE(ar9271Modes_9271), 6);
667 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
668 ARRAY_SIZE(ar9271Common_9271), 2);
669 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
670 ar9271Modes_9271_1_0_only,
671 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
d7e7d229
LR		 672 return;
673 }
674
ac88b6ec
VN		 675 if (AR_SREV_9287_11_OR_LATER(ah)) {
676 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
677 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
678 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
679 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
680 if (ah->config.pcie_clock_req)
681 INIT_INI_ARRAY(&ah->iniPcieSerdes,
682 ar9287PciePhy_clkreq_off_L1_9287_1_1,
683 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
684 else
685 INIT_INI_ARRAY(&ah->iniPcieSerdes,
686 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
687 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
688 2);
689 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
690 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
691 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
692 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
693 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
694
695 if (ah->config.pcie_clock_req)
696 INIT_INI_ARRAY(&ah->iniPcieSerdes,
697 ar9287PciePhy_clkreq_off_L1_9287_1_0,
698 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
699 else
700 INIT_INI_ARRAY(&ah->iniPcieSerdes,
701 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
702 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
703 2);
704 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
f078f209 705
4e845168 706
2660b81a 707 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
e7594072 708 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
2660b81a 709 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
e7594072
SB		 710 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
711
2660b81a
S		 712 if (ah->config.pcie_clock_req) {
713 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 714 ar9285PciePhy_clkreq_off_L1_9285_1_2,
715 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
716 } else {
2660b81a 717 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 718 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
719 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
720 2);
721 }
722 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
2660b81a 723 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
e7594072 724 ARRAY_SIZE(ar9285Modes_9285), 6);
2660b81a 725 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
e7594072
SB		 726 ARRAY_SIZE(ar9285Common_9285), 2);
727
2660b81a
S		 728 if (ah->config.pcie_clock_req) {
729 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 730 ar9285PciePhy_clkreq_off_L1_9285,
731 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
732 } else {
2660b81a 733 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 734 ar9285PciePhy_clkreq_always_on_L1_9285,
735 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
736 }
737 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2660b81a 738 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
f1dc5600 739 ARRAY_SIZE(ar9280Modes_9280_2), 6);
2660b81a 740 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
f1dc5600 741 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 742
2660b81a
S		 743 if (ah->config.pcie_clock_req) {
744 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 745 ar9280PciePhy_clkreq_off_L1_9280,
746 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
747 } else {
2660b81a 748 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 749 ar9280PciePhy_clkreq_always_on_L1_9280,
750 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
751 }
2660b81a 752 INIT_INI_ARRAY(&ah->iniModesAdditional,
f1dc5600
S		 753 ar9280Modes_fast_clock_9280_2,
754 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
755 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 756 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
f1dc5600 757 ARRAY_SIZE(ar9280Modes_9280), 6);
2660b81a 758 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
f1dc5600
S		 759 ARRAY_SIZE(ar9280Common_9280), 2);
760 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2660b81a 761 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
f1dc5600 762 ARRAY_SIZE(ar5416Modes_9160), 6);
2660b81a 763 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
f1dc5600 764 ARRAY_SIZE(ar5416Common_9160), 2);
2660b81a 765 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
f1dc5600 766 ARRAY_SIZE(ar5416Bank0_9160), 2);
2660b81a 767 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
f1dc5600 768 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
2660b81a 769 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
f1dc5600 770 ARRAY_SIZE(ar5416Bank1_9160), 2);
2660b81a 771 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
f1dc5600 772 ARRAY_SIZE(ar5416Bank2_9160), 2);
2660b81a 773 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
f1dc5600 774 ARRAY_SIZE(ar5416Bank3_9160), 3);
2660b81a 775 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
f1dc5600 776 ARRAY_SIZE(ar5416Bank6_9160), 3);
2660b81a 777 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
f1dc5600 778 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
2660b81a 779 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
f1dc5600
S		 780 ARRAY_SIZE(ar5416Bank7_9160), 2);
781 if (AR_SREV_9160_11(ah)) {
2660b81a 782 INIT_INI_ARRAY(&ah->iniAddac,
f1dc5600
S		 783 ar5416Addac_91601_1,
784 ARRAY_SIZE(ar5416Addac_91601_1), 2);
785 } else {
2660b81a 786 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
f1dc5600
S		 787 ARRAY_SIZE(ar5416Addac_9160), 2);
788 }
789 } else if (AR_SREV_9100_OR_LATER(ah)) {
2660b81a 790 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
f1dc5600 791 ARRAY_SIZE(ar5416Modes_9100), 6);
2660b81a 792 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
f1dc5600 793 ARRAY_SIZE(ar5416Common_9100), 2);
2660b81a 794 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
f1dc5600 795 ARRAY_SIZE(ar5416Bank0_9100), 2);
2660b81a 796 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
f1dc5600 797 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
2660b81a 798 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
f1dc5600 799 ARRAY_SIZE(ar5416Bank1_9100), 2);
2660b81a 800 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
f1dc5600 801 ARRAY_SIZE(ar5416Bank2_9100), 2);
2660b81a 802 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
f1dc5600 803 ARRAY_SIZE(ar5416Bank3_9100), 3);
2660b81a 804 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
f1dc5600 805 ARRAY_SIZE(ar5416Bank6_9100), 3);
2660b81a 806 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
f1dc5600 807 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
2660b81a 808 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
f1dc5600 809 ARRAY_SIZE(ar5416Bank7_9100), 2);
2660b81a 810 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
f1dc5600
S		 811 ARRAY_SIZE(ar5416Addac_9100), 2);
812 } else {
2660b81a 813 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
f1dc5600 814 ARRAY_SIZE(ar5416Modes), 6);
2660b81a 815 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
f1dc5600 816 ARRAY_SIZE(ar5416Common), 2);
2660b81a 817 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
f1dc5600 818 ARRAY_SIZE(ar5416Bank0), 2);
2660b81a 819 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
f1dc5600 820 ARRAY_SIZE(ar5416BB_RfGain), 3);
2660b81a 821 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
f1dc5600 822 ARRAY_SIZE(ar5416Bank1), 2);
2660b81a 823 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
f1dc5600 824 ARRAY_SIZE(ar5416Bank2), 2);
2660b81a 825 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
f1dc5600 826 ARRAY_SIZE(ar5416Bank3), 3);
2660b81a 827 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
f1dc5600 828 ARRAY_SIZE(ar5416Bank6), 3);
2660b81a 829 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
f1dc5600 830 ARRAY_SIZE(ar5416Bank6TPC), 3);
2660b81a 831 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
f1dc5600 832 ARRAY_SIZE(ar5416Bank7), 2);
2660b81a 833 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
f1dc5600 834 ARRAY_SIZE(ar5416Addac), 2);
f078f209 835 }
aa4058ae 836}
f078f209 837
aa4058ae
LR		 838static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
839{
b37fa870 840 if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec
VN		 841 INIT_INI_ARRAY(&ah->iniModesRxGain,
842 ar9287Modes_rx_gain_9287_1_1,
843 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
844 else if (AR_SREV_9287_10(ah))
845 INIT_INI_ARRAY(&ah->iniModesRxGain,
846 ar9287Modes_rx_gain_9287_1_0,
847 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
848 else if (AR_SREV_9280_20(ah))
849 ath9k_hw_init_rxgain_ini(ah);
850
b37fa870 851 if (AR_SREV_9287_11_OR_LATER(ah)) {
ac88b6ec
VN		 852 INIT_INI_ARRAY(&ah->iniModesTxGain,
853 ar9287Modes_tx_gain_9287_1_1,
854 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
855 } else if (AR_SREV_9287_10(ah)) {
856 INIT_INI_ARRAY(&ah->iniModesTxGain,
857 ar9287Modes_tx_gain_9287_1_0,
858 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
859 } else if (AR_SREV_9280_20(ah)) {
860 ath9k_hw_init_txgain_ini(ah);
861 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4e845168
SB		 862 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
863
864 /* txgain table */
865 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
866 INIT_INI_ARRAY(&ah->iniModesTxGain,
867 ar9285Modes_high_power_tx_gain_9285_1_2,
868 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
869 } else {
870 INIT_INI_ARRAY(&ah->iniModesTxGain,
871 ar9285Modes_original_tx_gain_9285_1_2,
872 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
873 }
874
875 }
aa4058ae 876}
4e845168 877
aa4058ae
LR		 878static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
879{
880 u32 i, j;
06d0f066
S		 881
882 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
883 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
884
885 /* EEPROM Fixup */
2660b81a
S		 886 for (i = 0; i < ah->iniModes.ia_rows; i++) {
887 u32 reg = INI_RA(&ah->iniModes, i, 0);
f078f209 888
2660b81a
S		 889 for (j = 1; j < ah->iniModes.ia_columns; j++) {
890 u32 val = INI_RA(&ah->iniModes, i, j);
f078f209 891
2660b81a 892 INI_RA(&ah->iniModes, i, j) =
e7594072 893 ath9k_hw_ini_fixup(ah,
2660b81a 894 &ah->eeprom.def,
f1dc5600
S		 895 reg, val);
896 }
f078f209 897 }
f1dc5600 898 }
aa4058ae
LR		 899}
900
f637cfd6 901int ath9k_hw_init(struct ath_hw *ah)
aa4058ae 902{
c46917bb 903 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 904 int r = 0;
aa4058ae 905
3ca34038
LR		 906 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
907 ath_print(common, ATH_DBG_FATAL,
908 "Unsupported device ID: 0x%0x\n",
909 ah->hw_version.devid);
95fafca2 910 return -EOPNOTSUPP;
3ca34038 911 }
aa4058ae
LR		 912
913 ath9k_hw_init_defaults(ah);
914 ath9k_hw_init_config(ah);
915
916 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 917 ath_print(common, ATH_DBG_FATAL,
918 "Couldn't reset chip\n");
95fafca2 919 return -EIO;
aa4058ae
LR		 920 }
921
9ecdef4b 922 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 923 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 924 return -EIO;
aa4058ae
LR		 925 }
926
927 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
928 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
929 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
930 ah->config.serialize_regmode =
931 SER_REG_MODE_ON;
932 } else {
933 ah->config.serialize_regmode =
934 SER_REG_MODE_OFF;
935 }
936 }
937
c46917bb 938 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 939 ah->config.serialize_regmode);
940
941 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
c46917bb
LR		 942 ath_print(common, ATH_DBG_FATAL,
943 "Mac Chip Rev 0x%02x.%x is not supported by "
944 "this driver\n", ah->hw_version.macVersion,
945 ah->hw_version.macRev);
95fafca2 946 return -EOPNOTSUPP;
aa4058ae
LR		 947 }
948
949 if (AR_SREV_9100(ah)) {
950 ah->iq_caldata.calData = &iq_cal_multi_sample;
951 ah->supp_cals = IQ_MISMATCH_CAL;
952 ah->is_pciexpress = false;
953 }
d7e7d229
LR		 954
955 if (AR_SREV_9271(ah))
956 ah->is_pciexpress = false;
957
aa4058ae
LR		 958 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
959
960 ath9k_hw_init_cal_settings(ah);
961
962 ah->ani_function = ATH9K_ANI_ALL;
963 if (AR_SREV_9280_10_OR_LATER(ah))
964 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
965
966 ath9k_hw_init_mode_regs(ah);
967
968 if (ah->is_pciexpress)
93b1b37f 969 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 970 else
971 ath9k_hw_disablepcie(ah);
972
193cd458
S		 973 /* Support for Japan ch.14 (2484) spread */
974 if (AR_SREV_9287_11_OR_LATER(ah)) {
975 INIT_INI_ARRAY(&ah->iniCckfirNormal,
976 ar9287Common_normal_cck_fir_coeff_92871_1,
977 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
978 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
979 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
980 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
981 }
982
f637cfd6 983 r = ath9k_hw_post_init(ah);
aa4058ae 984 if (r)
95fafca2 985 return r;
aa4058ae
LR		 986
987 ath9k_hw_init_mode_gain_regs(ah);
988 ath9k_hw_fill_cap_info(ah);
989 ath9k_hw_init_11a_eeprom_fix(ah);
f6688cd8 990
4f3acf81
LR		 991 r = ath9k_hw_init_macaddr(ah);
992 if (r) {
c46917bb
LR		 993 ath_print(common, ATH_DBG_FATAL,
994 "Failed to initialize MAC address\n");
95fafca2 995 return r;
f078f209
LR		 996 }
997
d7e7d229 998 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 999 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 1000 else
2660b81a 1001 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 1002
f1dc5600 1003 ath9k_init_nfcal_hist_buffer(ah);
f078f209 1004
211f5859
LR		 1005 common->state = ATH_HW_INITIALIZED;
1006
4f3acf81 1007 return 0;
f078f209
LR		 1008}
1009
cbe61d8a 1010static void ath9k_hw_init_bb(struct ath_hw *ah,
f1dc5600 1011 struct ath9k_channel *chan)
f078f209 1012{
f1dc5600 1013 u32 synthDelay;
f078f209 1014
f1dc5600 1015 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1016 if (IS_CHAN_B(chan))
f1dc5600
S		 1017 synthDelay = (4 * synthDelay) / 22;
1018 else
1019 synthDelay /= 10;
f078f209 1020
f1dc5600 1021 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 1022
f1dc5600 1023 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 1024}
1025
cbe61d8a 1026static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 1027{
f1dc5600
S		 1028 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1029 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 1030
f1dc5600
S		 1031 REG_WRITE(ah, AR_QOS_NO_ACK,
1032 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1033 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1034 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1035
1036 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1037 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1038 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1039 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1040 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 1041}
1042
c75724d1
LR		 1043static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
1044{
1045 u32 lcr;
1046 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
1047
1048 lcr = REG_READ(ah , 0x5100c);
1049 lcr |= 0x80;
1050
1051 REG_WRITE(ah, 0x5100c, lcr);
1052 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1053 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1054
1055 lcr &= ~0x80;
1056 REG_WRITE(ah, 0x5100c, lcr);
1057}
1058
cbe61d8a 1059static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 1060 struct ath9k_channel *chan)
f078f209 1061{
f1dc5600 1062 u32 pll;
f078f209 1063
f1dc5600
S		 1064 if (AR_SREV_9100(ah)) {
1065 if (chan && IS_CHAN_5GHZ(chan))
1066 pll = 0x1450;
f078f209 1067 else
f1dc5600
S		 1068 pll = 0x1458;
1069 } else {
1070 if (AR_SREV_9280_10_OR_LATER(ah)) {
1071 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1072
f1dc5600
S		 1073 if (chan && IS_CHAN_HALF_RATE(chan))
1074 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1075 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1076 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1077
f1dc5600
S		 1078 if (chan && IS_CHAN_5GHZ(chan)) {
1079 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 1080
f078f209 1081
f1dc5600
S		 1082 if (AR_SREV_9280_20(ah)) {
1083 if (((chan->channel % 20) == 0)
1084 || ((chan->channel % 10) == 0))
1085 pll = 0x2850;
1086 else
1087 pll = 0x142c;
1088 }
1089 } else {
1090 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1091 }
f078f209 1092
f1dc5600 1093 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 1094
f1dc5600 1095 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1096
f1dc5600
S		 1097 if (chan && IS_CHAN_HALF_RATE(chan))
1098 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1099 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1100 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1101
f1dc5600
S		 1102 if (chan && IS_CHAN_5GHZ(chan))
1103 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1104 else
1105 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1106 } else {
1107 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 1108
f1dc5600
S		 1109 if (chan && IS_CHAN_HALF_RATE(chan))
1110 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1111 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1112 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 1113
f1dc5600
S		 1114 if (chan && IS_CHAN_5GHZ(chan))
1115 pll |= SM(0xa, AR_RTC_PLL_DIV);
1116 else
1117 pll |= SM(0xb, AR_RTC_PLL_DIV);
1118 }
1119 }
d03a66c1 1120 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 1121
c75724d1
LR		 1122 /* Switch the core clock for ar9271 to 117Mhz */
1123 if (AR_SREV_9271(ah)) {
1124 if ((pll == 0x142c) || (pll == 0x2850) ) {
1125 udelay(500);
1126 /* set CLKOBS to output AHB clock */
1127 REG_WRITE(ah, 0x7020, 0xe);
1128 /*
1129 * 0x304: 117Mhz, ahb_ratio: 1x1
1130 * 0x306: 40Mhz, ahb_ratio: 1x1
1131 */
1132 REG_WRITE(ah, 0x50040, 0x304);
1133 /*
1134 * makes adjustments for the baud dividor to keep the
1135 * targetted baud rate based on the used core clock.
1136 */
1137 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1138 AR9271_TARGET_BAUD_RATE);
1139 }
1140 }
1141
f1dc5600
S		 1142 udelay(RTC_PLL_SETTLE_DELAY);
1143
1144 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 1145}
1146
cbe61d8a 1147static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
f078f209 1148{
f078f209
LR		 1149 int rx_chainmask, tx_chainmask;
1150
2660b81a
S		 1151 rx_chainmask = ah->rxchainmask;
1152 tx_chainmask = ah->txchainmask;
f078f209
LR		 1153
1154 switch (rx_chainmask) {
1155 case 0x5:
1156 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1157 AR_PHY_SWAP_ALT_CHAIN);
1158 case 0x3:
d535a42a 1159 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
f078f209
LR		 1160 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1161 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1162 break;
1163 }
1164 case 0x1:
1165 case 0x2:
f078f209
LR		 1166 case 0x7:
1167 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1168 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1169 break;
1170 default:
1171 break;
1172 }
1173
1174 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1175 if (tx_chainmask == 0x5) {
1176 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1177 AR_PHY_SWAP_ALT_CHAIN);
1178 }
1179 if (AR_SREV_9100(ah))
1180 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1181 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1182}
1183
cbe61d8a 1184static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 1185 enum nl80211_iftype opmode)
f078f209 1186{
2660b81a 1187 ah->mask_reg = AR_IMR_TXERR |
f1dc5600
S		 1188 AR_IMR_TXURN |
1189 AR_IMR_RXERR |
1190 AR_IMR_RXORN |
1191 AR_IMR_BCNMISC;
f078f209 1192
0ef1f168 1193 if (ah->config.intr_mitigation)
2660b81a 1194 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1195 else
2660b81a 1196 ah->mask_reg |= AR_IMR_RXOK;
f078f209 1197
2660b81a 1198 ah->mask_reg |= AR_IMR_TXOK;
f078f209 1199
d97809db 1200 if (opmode == NL80211_IFTYPE_AP)
2660b81a 1201 ah->mask_reg |= AR_IMR_MIB;
f078f209 1202
2660b81a 1203 REG_WRITE(ah, AR_IMR, ah->mask_reg);
f1dc5600 1204 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1205
f1dc5600
S		 1206 if (!AR_SREV_9100(ah)) {
1207 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1208 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1209 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1210 }
f078f209
LR		 1211}
1212
cbe61d8a 1213static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1214{
f078f209 1215 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
c46917bb
LR		 1216 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1217 "bad ack timeout %u\n", us);
2660b81a 1218 ah->acktimeout = (u32) -1;
f078f209
LR		 1219 return false;
1220 } else {
1221 REG_RMW_FIELD(ah, AR_TIME_OUT,
1222 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1223 ah->acktimeout = us;
f078f209
LR		 1224 return true;
1225 }
1226}
1227
cbe61d8a 1228static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
f078f209 1229{
f078f209 1230 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
c46917bb
LR		 1231 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1232 "bad cts timeout %u\n", us);
2660b81a 1233 ah->ctstimeout = (u32) -1;
f078f209
LR		 1234 return false;
1235 } else {
1236 REG_RMW_FIELD(ah, AR_TIME_OUT,
1237 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1238 ah->ctstimeout = us;
f078f209
LR		 1239 return true;
1240 }
1241}
f1dc5600 1242
cbe61d8a 1243static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1244{
f078f209 1245 if (tu > 0xFFFF) {
c46917bb
LR		 1246 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1247 "bad global tx timeout %u\n", tu);
2660b81a 1248 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1249 return false;
1250 } else {
1251 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1252 ah->globaltxtimeout = tu;
f078f209
LR		 1253 return true;
1254 }
1255}
1256
cbe61d8a 1257static void ath9k_hw_init_user_settings(struct ath_hw *ah)
f078f209 1258{
c46917bb
LR		 1259 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1260 ah->misc_mode);
f078f209 1261
2660b81a 1262 if (ah->misc_mode != 0)
f1dc5600 1263 REG_WRITE(ah, AR_PCU_MISC,
2660b81a
S		 1264 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1265 if (ah->slottime != (u32) -1)
1266 ath9k_hw_setslottime(ah, ah->slottime);
1267 if (ah->acktimeout != (u32) -1)
1268 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1269 if (ah->ctstimeout != (u32) -1)
1270 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1271 if (ah->globaltxtimeout != (u32) -1)
1272 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600
S		 1273}
1274
1275const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1276{
1277 return vendorid == ATHEROS_VENDOR_ID ?
1278 ath9k_hw_devname(devid) : NULL;
1279}
1280
cbe61d8a 1281void ath9k_hw_detach(struct ath_hw *ah)
f1dc5600 1282{
211f5859
LR		 1283 struct ath_common *common = ath9k_hw_common(ah);
1284
1285 if (common->state <= ATH_HW_INITIALIZED)
1286 goto free_hw;
1287
f1dc5600 1288 if (!AR_SREV_9100(ah))
e70c0cfd 1289 ath9k_hw_ani_disable(ah);
f1dc5600 1290
9ecdef4b 1291 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 1292
1293free_hw:
1294 ath9k_hw_rf_free(ah);
f1dc5600 1295 kfree(ah);
9db6b6a2 1296 ah = NULL;
f1dc5600 1297}
7322fd19 1298EXPORT_SYMBOL(ath9k_hw_detach);
f1dc5600 1299
f1dc5600
S		 1300/*******/
1301/* INI */
1302/*******/
1303
cbe61d8a 1304static void ath9k_hw_override_ini(struct ath_hw *ah,
f1dc5600
S		 1305 struct ath9k_channel *chan)
1306{
d7e7d229
LR		 1307 u32 val;
1308
1309 if (AR_SREV_9271(ah)) {
1310 /*
1311 * Enable spectral scan to solution for issues with stuck
1312 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1313 * AR9271 1.1
1314 */
1315 if (AR_SREV_9271_10(ah)) {
ec11bb88
LR		 1316 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1317 AR_PHY_SPECTRAL_SCAN_ENABLE;
d7e7d229
LR		 1318 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1319 }
1320 else if (AR_SREV_9271_11(ah))
1321 /*
1322 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1323 * present on AR9271 1.1
1324 */
1325 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1326 return;
1327 }
1328
8aa15e15
SB		 1329 /*
1330 * Set the RX_ABORT and RX_DIS and clear if off only after
1331 * RXE is set for MAC. This prevents frames with corrupted
1332 * descriptor status.
1333 */
1334 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1335
204d7940
VT		 1336 if (AR_SREV_9280_10_OR_LATER(ah)) {
1337 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1338 (~AR_PCU_MISC_MODE2_HWWAR1);
1339
1340 if (AR_SREV_9287_10_OR_LATER(ah))
1341 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1342
1343 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1344 }
8aa15e15 1345
a8c96d3b 1346 if (!AR_SREV_5416_20_OR_LATER(ah) ||
f1dc5600
S		 1347 AR_SREV_9280_10_OR_LATER(ah))
1348 return;
d7e7d229
LR		 1349 /*
1350 * Disable BB clock gating
1351 * Necessary to avoid issues on AR5416 2.0
1352 */
f1dc5600 1353 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1354}
1355
cbe61d8a 1356static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
e7594072 1357 struct ar5416_eeprom_def *pEepData,
f1dc5600 1358 u32 reg, u32 value)
f078f209 1359{
f1dc5600 1360 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
c46917bb 1361 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1362
d535a42a 1363 switch (ah->hw_version.devid) {
f1dc5600
S		 1364 case AR9280_DEVID_PCI:
1365 if (reg == 0x7894) {
c46917bb 1366 ath_print(common, ATH_DBG_EEPROM,
f1dc5600
S		 1367 "ini VAL: %x EEPROM: %x\n", value,
1368 (pBase->version & 0xff));
1369
1370 if ((pBase->version & 0xff) > 0x0a) {
c46917bb
LR		 1371 ath_print(common, ATH_DBG_EEPROM,
1372 "PWDCLKIND: %d\n",
1373 pBase->pwdclkind);
f1dc5600
S		 1374 value &= ~AR_AN_TOP2_PWDCLKIND;
1375 value |= AR_AN_TOP2_PWDCLKIND &
1376 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1377 } else {
c46917bb
LR		 1378 ath_print(common, ATH_DBG_EEPROM,
1379 "PWDCLKIND Earlier Rev\n");
f1dc5600
S		 1380 }
1381
c46917bb
LR		 1382 ath_print(common, ATH_DBG_EEPROM,
1383 "final ini VAL: %x\n", value);
f1dc5600
S		 1384 }
1385 break;
1386 }
1387
1388 return value;
f078f209
LR		 1389}
1390
cbe61d8a 1391static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072
SB		 1392 struct ar5416_eeprom_def *pEepData,
1393 u32 reg, u32 value)
1394{
2660b81a 1395 if (ah->eep_map == EEP_MAP_4KBITS)
e7594072
SB		 1396 return value;
1397 else
1398 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1399}
1400
8bd1d07f
SB		 1401static void ath9k_olc_init(struct ath_hw *ah)
1402{
1403 u32 i;
1404
db91f2e4
VN		 1405 if (OLC_FOR_AR9287_10_LATER) {
1406 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1407 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1408 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1409 AR9287_AN_TXPC0_TXPCMODE,
1410 AR9287_AN_TXPC0_TXPCMODE_S,
1411 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1412 udelay(100);
1413 } else {
1414 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1415 ah->originalGain[i] =
1416 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1417 AR_PHY_TX_GAIN);
1418 ah->PDADCdelta = 0;
1419 }
8bd1d07f
SB		 1420}
1421
3a702e49
BC		 1422static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1423 struct ath9k_channel *chan)
1424{
1425 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1426
1427 if (IS_CHAN_B(chan))
1428 ctl |= CTL_11B;
1429 else if (IS_CHAN_G(chan))
1430 ctl |= CTL_11G;
1431 else
1432 ctl |= CTL_11A;
1433
1434 return ctl;
1435}
1436
cbe61d8a 1437static int ath9k_hw_process_ini(struct ath_hw *ah,
25c56eec 1438 struct ath9k_channel *chan)
f078f209 1439{
608b88cb 1440 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f078f209 1441 int i, regWrites = 0;
5f8e077c 1442 struct ieee80211_channel *channel = chan->chan;
f078f209 1443 u32 modesIndex, freqIndex;
f078f209
LR		 1444
1445 switch (chan->chanmode) {
1446 case CHANNEL_A:
1447 case CHANNEL_A_HT20:
1448 modesIndex = 1;
1449 freqIndex = 1;
1450 break;
1451 case CHANNEL_A_HT40PLUS:
1452 case CHANNEL_A_HT40MINUS:
1453 modesIndex = 2;
1454 freqIndex = 1;
1455 break;
1456 case CHANNEL_G:
1457 case CHANNEL_G_HT20:
1458 case CHANNEL_B:
1459 modesIndex = 4;
1460 freqIndex = 2;
1461 break;
1462 case CHANNEL_G_HT40PLUS:
1463 case CHANNEL_G_HT40MINUS:
1464 modesIndex = 3;
1465 freqIndex = 2;
1466 break;
1467
1468 default:
1469 return -EINVAL;
1470 }
1471
1472 REG_WRITE(ah, AR_PHY(0), 0x00000007);
f078f209 1473 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
f74df6fb 1474 ah->eep_ops->set_addac(ah, chan);
f078f209 1475
a8c96d3b 1476 if (AR_SREV_5416_22_OR_LATER(ah)) {
2660b81a 1477 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
f078f209
LR		 1478 } else {
1479 struct ar5416IniArray temp;
1480 u32 addacSize =
2660b81a
S		 1481 sizeof(u32) * ah->iniAddac.ia_rows *
1482 ah->iniAddac.ia_columns;
f078f209 1483
2660b81a
S		 1484 memcpy(ah->addac5416_21,
1485 ah->iniAddac.ia_array, addacSize);
f078f209 1486
2660b81a 1487 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
f078f209 1488
2660b81a
S		 1489 temp.ia_array = ah->addac5416_21;
1490 temp.ia_columns = ah->iniAddac.ia_columns;
1491 temp.ia_rows = ah->iniAddac.ia_rows;
f078f209
LR		 1492 REG_WRITE_ARRAY(&temp, 1, regWrites);
1493 }
f1dc5600 1494
f078f209
LR		 1495 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1496
2660b81a
S		 1497 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1498 u32 reg = INI_RA(&ah->iniModes, i, 0);
1499 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
f078f209 1500
f078f209
LR		 1501 REG_WRITE(ah, reg, val);
1502
1503 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1504 && ah->config.analog_shiftreg) {
f078f209
LR		 1505 udelay(100);
1506 }
1507
1508 DO_DELAY(regWrites);
1509 }
1510
ac88b6ec 1511 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1512 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
9f804202 1513
ac88b6ec
VN		 1514 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1515 AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1516 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
9f804202 1517
2660b81a
S		 1518 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1519 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1520 u32 val = INI_RA(&ah->iniCommon, i, 1);
f078f209
LR		 1521
1522 REG_WRITE(ah, reg, val);
1523
1524 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1525 && ah->config.analog_shiftreg) {
f078f209
LR		 1526 udelay(100);
1527 }
1528
1529 DO_DELAY(regWrites);
1530 }
1531
1532 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1533
8564328d
LR		 1534 if (AR_SREV_9271_10(ah))
1535 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1536 modesIndex, regWrites);
1537
f078f209 1538 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
2660b81a 1539 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
f078f209
LR		 1540 regWrites);
1541 }
1542
1543 ath9k_hw_override_ini(ah, chan);
25c56eec 1544 ath9k_hw_set_regs(ah, chan);
f078f209
LR		 1545 ath9k_hw_init_chain_masks(ah);
1546
8bd1d07f
SB		 1547 if (OLC_FOR_AR9280_20_LATER)
1548 ath9k_olc_init(ah);
1549
8fbff4b8 1550 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1551 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 1552 channel->max_antenna_gain * 2,
1553 channel->max_power * 2,
1554 min((u32) MAX_RATE_POWER,
608b88cb 1555 (u32) regulatory->power_limit));
f078f209
LR		 1556
1557 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
c46917bb
LR		 1558 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1559 "ar5416SetRfRegs failed\n");
f078f209
LR		 1560 return -EIO;
1561 }
1562
1563 return 0;
1564}
1565
f1dc5600
S		 1566/****************************************/
1567/* Reset and Channel Switching Routines */
1568/****************************************/
1569
cbe61d8a 1570static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1571{
f1dc5600
S		 1572 u32 rfMode = 0;
1573
1574 if (chan == NULL)
1575 return;
1576
1577 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1578 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1579
1580 if (!AR_SREV_9280_10_OR_LATER(ah))
1581 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1582 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1583
1584 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1585 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1586
1587 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1588}
1589
cbe61d8a 1590static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
f1dc5600
S		 1591{
1592 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1593}
1594
cbe61d8a 1595static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 1596{
1597 u32 regval;
1598
d7e7d229
LR		 1599 /*
1600 * set AHB_MODE not to do cacheline prefetches
1601 */
f1dc5600
S		 1602 regval = REG_READ(ah, AR_AHB_MODE);
1603 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1604
d7e7d229
LR		 1605 /*
1606 * let mac dma reads be in 128 byte chunks
1607 */
f1dc5600
S		 1608 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1609 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1610
d7e7d229
LR		 1611 /*
1612 * Restore TX Trigger Level to its pre-reset value.
1613 * The initial value depends on whether aggregation is enabled, and is
1614 * adjusted whenever underruns are detected.
1615 */
2660b81a 1616 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1617
d7e7d229
LR		 1618 /*
1619 * let mac dma writes be in 128 byte chunks
1620 */
f1dc5600
S		 1621 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1622 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1623
d7e7d229
LR		 1624 /*
1625 * Setup receive FIFO threshold to hold off TX activities
1626 */
f1dc5600
S		 1627 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1628
d7e7d229
LR		 1629 /*
1630 * reduce the number of usable entries in PCU TXBUF to avoid
1631 * wrap around issues.
1632 */
f1dc5600 1633 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1634 /* For AR9285 the number of Fifos are reduced to half.
1635 * So set the usable tx buf size also to half to
1636 * avoid data/delimiter underruns
1637 */
f1dc5600
S		 1638 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1639 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1640 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1641 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1642 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1643 }
1644}
1645
cbe61d8a 1646static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1647{
1648 u32 val;
1649
1650 val = REG_READ(ah, AR_STA_ID1);
1651 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1652 switch (opmode) {
d97809db 1653 case NL80211_IFTYPE_AP:
f1dc5600
S		 1654 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1655 | AR_STA_ID1_KSRCH_MODE);
1656 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1657 break;
d97809db 1658 case NL80211_IFTYPE_ADHOC:
9cb5412b 1659 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 1660 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1661 | AR_STA_ID1_KSRCH_MODE);
1662 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1663 break;
d97809db
CM		 1664 case NL80211_IFTYPE_STATION:
1665 case NL80211_IFTYPE_MONITOR:
f1dc5600 1666 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1667 break;
f1dc5600
S		 1668 }
1669}
1670
cbe61d8a 1671static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
f1dc5600
S		 1672 u32 coef_scaled,
1673 u32 *coef_mantissa,
1674 u32 *coef_exponent)
1675{
1676 u32 coef_exp, coef_man;
1677
1678 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1679 if ((coef_scaled >> coef_exp) & 0x1)
1680 break;
1681
1682 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1683
1684 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1685
1686 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1687 *coef_exponent = coef_exp - 16;
1688}
1689
cbe61d8a 1690static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
f1dc5600
S		 1691 struct ath9k_channel *chan)
1692{
1693 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1694 u32 clockMhzScaled = 0x64000000;
1695 struct chan_centers centers;
1696
1697 if (IS_CHAN_HALF_RATE(chan))
1698 clockMhzScaled = clockMhzScaled >> 1;
1699 else if (IS_CHAN_QUARTER_RATE(chan))
1700 clockMhzScaled = clockMhzScaled >> 2;
1701
1702 ath9k_hw_get_channel_centers(ah, chan, &centers);
1703 coef_scaled = clockMhzScaled / centers.synth_center;
1704
1705 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1706 &ds_coef_exp);
1707
1708 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1709 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1710 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1711 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1712
1713 coef_scaled = (9 * coef_scaled) / 10;
1714
1715 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1716 &ds_coef_exp);
1717
1718 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1719 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1720 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1721 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1722}
1723
cbe61d8a 1724static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1725{
1726 u32 rst_flags;
1727 u32 tmpReg;
1728
70768496
S		 1729 if (AR_SREV_9100(ah)) {
1730 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1731 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1732 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1733 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1734 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1735 }
1736
f1dc5600
S		 1737 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1738 AR_RTC_FORCE_WAKE_ON_INT);
1739
1740 if (AR_SREV_9100(ah)) {
1741 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1742 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1743 } else {
1744 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1745 if (tmpReg &
1746 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1747 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1748 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1749 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1750 } else {
1751 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1752 }
1753
1754 rst_flags = AR_RTC_RC_MAC_WARM;
1755 if (type == ATH9K_RESET_COLD)
1756 rst_flags |= AR_RTC_RC_MAC_COLD;
1757 }
1758
d03a66c1 1759 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1760 udelay(50);
1761
d03a66c1 1762 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1763 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1764 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1765 "RTC stuck in MAC reset\n");
f1dc5600
S		 1766 return false;
1767 }
1768
1769 if (!AR_SREV_9100(ah))
1770 REG_WRITE(ah, AR_RC, 0);
1771
f1dc5600
S		 1772 if (AR_SREV_9100(ah))
1773 udelay(50);
1774
1775 return true;
1776}
1777
cbe61d8a 1778static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1779{
1780 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1781 AR_RTC_FORCE_WAKE_ON_INT);
1782
1c29ce67
VT		 1783 if (!AR_SREV_9100(ah))
1784 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1785
d03a66c1 1786 REG_WRITE(ah, AR_RTC_RESET, 0);
8bd1d07f 1787 udelay(2);
1c29ce67
VT		 1788
1789 if (!AR_SREV_9100(ah))
1790 REG_WRITE(ah, AR_RC, 0);
1791
d03a66c1 1792 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1793
1794 if (!ath9k_hw_wait(ah,
1795 AR_RTC_STATUS,
1796 AR_RTC_STATUS_M,
0caa7b14
S		 1797 AR_RTC_STATUS_ON,
1798 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1799 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1800 "RTC not waking up\n");
f1dc5600 1801 return false;
f078f209
LR		 1802 }
1803
f1dc5600
S		 1804 ath9k_hw_read_revisions(ah);
1805
1806 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1807}
1808
cbe61d8a 1809static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1810{
1811 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1812 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1813
1814 switch (type) {
1815 case ATH9K_RESET_POWER_ON:
1816 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1817 case ATH9K_RESET_WARM:
1818 case ATH9K_RESET_COLD:
1819 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1820 default:
1821 return false;
1822 }
f078f209
LR		 1823}
1824
25c56eec 1825static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1826{
f1dc5600 1827 u32 phymode;
e7594072 1828 u32 enableDacFifo = 0;
f078f209 1829
e7594072
SB		 1830 if (AR_SREV_9285_10_OR_LATER(ah))
1831 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1832 AR_PHY_FC_ENABLE_DAC_FIFO);
1833
f1dc5600 1834 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1835 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1836
1837 if (IS_CHAN_HT40(chan)) {
1838 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1839
f1dc5600
S		 1840 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1841 (chan->chanmode == CHANNEL_G_HT40PLUS))
1842 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1843
f078f209 1844 }
f1dc5600
S		 1845 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1846
25c56eec 1847 ath9k_hw_set11nmac2040(ah);
f078f209 1848
f1dc5600
S		 1849 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1850 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1851}
1852
cbe61d8a 1853static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1854 struct ath9k_channel *chan)
f078f209 1855{
42abfbee 1856 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1857 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1858 return false;
1859 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1860 return false;
f078f209 1861
9ecdef4b 1862 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1863 return false;
f078f209 1864
2660b81a 1865 ah->chip_fullsleep = false;
f1dc5600 1866 ath9k_hw_init_pll(ah, chan);
f1dc5600 1867 ath9k_hw_set_rfmode(ah, chan);
f078f209 1868
f1dc5600 1869 return true;
f078f209
LR		 1870}
1871
cbe61d8a 1872static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1873 struct ath9k_channel *chan)
f078f209 1874{
608b88cb 1875 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1876 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1877 struct ieee80211_channel *channel = chan->chan;
f078f209 1878 u32 synthDelay, qnum;
f078f209
LR		 1879
1880 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1881 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1882 ath_print(common, ATH_DBG_QUEUE,
1883 "Transmit frames pending on "
1884 "queue %d\n", qnum);
f078f209
LR		 1885 return false;
1886 }
1887 }
1888
1889 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1890 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
0caa7b14 1891 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1892 ath_print(common, ATH_DBG_FATAL,
1893 "Could not kill baseband RX\n");
f078f209
LR		 1894 return false;
1895 }
1896
25c56eec 1897 ath9k_hw_set_regs(ah, chan);
f078f209
LR		 1898
1899 if (AR_SREV_9280_10_OR_LATER(ah)) {
8fbff4b8 1900 ath9k_hw_ar9280_set_channel(ah, chan);
f078f209
LR		 1901 } else {
1902 if (!(ath9k_hw_set_channel(ah, chan))) {
c46917bb
LR		 1903 ath_print(common, ATH_DBG_FATAL,
1904 "Failed to set channel\n");
f078f209
LR		 1905 return false;
1906 }
1907 }
1908
8fbff4b8 1909 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1910 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1911 channel->max_antenna_gain * 2,
1912 channel->max_power * 2,
1913 min((u32) MAX_RATE_POWER,
608b88cb 1914 (u32) regulatory->power_limit));
f078f209
LR		 1915
1916 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1917 if (IS_CHAN_B(chan))
f078f209
LR		 1918 synthDelay = (4 * synthDelay) / 22;
1919 else
1920 synthDelay /= 10;
1921
1922 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1923
1924 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1925
f1dc5600
S		 1926 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1927 ath9k_hw_set_delta_slope(ah, chan);
1928
1929 if (AR_SREV_9280_10_OR_LATER(ah))
1930 ath9k_hw_9280_spur_mitigate(ah, chan);
1931 else
1932 ath9k_hw_spur_mitigate(ah, chan);
1933
1934 if (!chan->oneTimeCalsDone)
1935 chan->oneTimeCalsDone = true;
1936
1937 return true;
1938}
1939
cbe61d8a 1940static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 1941{
1942 int bb_spur = AR_NO_SPUR;
1943 int freq;
1944 int bin, cur_bin;
1945 int bb_spur_off, spur_subchannel_sd;
1946 int spur_freq_sd;
1947 int spur_delta_phase;
1948 int denominator;
1949 int upper, lower, cur_vit_mask;
1950 int tmp, newVal;
1951 int i;
1952 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1953 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1954 };
1955 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1956 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1957 };
1958 int inc[4] = { 0, 100, 0, 0 };
1959 struct chan_centers centers;
1960
1961 int8_t mask_m[123];
1962 int8_t mask_p[123];
1963 int8_t mask_amt;
1964 int tmp_mask;
1965 int cur_bb_spur;
1966 bool is2GHz = IS_CHAN_2GHZ(chan);
1967
1968 memset(&mask_m, 0, sizeof(int8_t) * 123);
1969 memset(&mask_p, 0, sizeof(int8_t) * 123);
1970
1971 ath9k_hw_get_channel_centers(ah, chan, &centers);
1972 freq = centers.synth_center;
1973
2660b81a 1974 ah->config.spurmode = SPUR_ENABLE_EEPROM;
f1dc5600 1975 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 1976 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 1977
1978 if (is2GHz)
1979 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1980 else
1981 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1982
1983 if (AR_NO_SPUR == cur_bb_spur)
1984 break;
1985 cur_bb_spur = cur_bb_spur - freq;
1986
1987 if (IS_CHAN_HT40(chan)) {
1988 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1989 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1990 bb_spur = cur_bb_spur;
1991 break;
1992 }
1993 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1994 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1995 bb_spur = cur_bb_spur;
1996 break;
1997 }
1998 }
1999
2000 if (AR_NO_SPUR == bb_spur) {
2001 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
2002 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
2003 return;
2004 } else {
2005 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
2006 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
2007 }
2008
2009 bin = bb_spur * 320;
2010
2011 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2012
2013 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2014 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2015 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2016 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2017 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
2018
2019 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2020 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2021 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2022 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2023 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2024 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
2025
2026 if (IS_CHAN_HT40(chan)) {
2027 if (bb_spur < 0) {
2028 spur_subchannel_sd = 1;
2029 bb_spur_off = bb_spur + 10;
2030 } else {
2031 spur_subchannel_sd = 0;
2032 bb_spur_off = bb_spur - 10;
2033 }
2034 } else {
2035 spur_subchannel_sd = 0;
2036 bb_spur_off = bb_spur;
2037 }
2038
2039 if (IS_CHAN_HT40(chan))
2040 spur_delta_phase =
2041 ((bb_spur * 262144) /
2042 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2043 else
2044 spur_delta_phase =
2045 ((bb_spur * 524288) /
2046 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2047
2048 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
2049 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
2050
2051 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2052 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2053 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2054 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
2055
2056 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
2057 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
2058
2059 cur_bin = -6000;
2060 upper = bin + 100;
2061 lower = bin - 100;
2062
2063 for (i = 0; i < 4; i++) {
2064 int pilot_mask = 0;
2065 int chan_mask = 0;
2066 int bp = 0;
2067 for (bp = 0; bp < 30; bp++) {
2068 if ((cur_bin > lower) && (cur_bin < upper)) {
2069 pilot_mask = pilot_mask | 0x1 << bp;
2070 chan_mask = chan_mask | 0x1 << bp;
2071 }
2072 cur_bin += 100;
2073 }
2074 cur_bin += inc[i];
2075 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2076 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2077 }
2078
2079 cur_vit_mask = 6100;
2080 upper = bin + 120;
2081 lower = bin - 120;
2082
2083 for (i = 0; i < 123; i++) {
2084 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2085
2086 /* workaround for gcc bug #37014 */
a085ff71 2087 volatile int tmp_v = abs(cur_vit_mask - bin);
f1dc5600 2088
a085ff71 2089 if (tmp_v < 75)
f1dc5600
S		 2090 mask_amt = 1;
2091 else
2092 mask_amt = 0;
2093 if (cur_vit_mask < 0)
2094 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2095 else
2096 mask_p[cur_vit_mask / 100] = mask_amt;
2097 }
2098 cur_vit_mask -= 100;
2099 }
2100
2101 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2102 | (mask_m[48] << 26) | (mask_m[49] << 24)
2103 | (mask_m[50] << 22) | (mask_m[51] << 20)
2104 | (mask_m[52] << 18) | (mask_m[53] << 16)
2105 | (mask_m[54] << 14) | (mask_m[55] << 12)
2106 | (mask_m[56] << 10) | (mask_m[57] << 8)
2107 | (mask_m[58] << 6) | (mask_m[59] << 4)
2108 | (mask_m[60] << 2) | (mask_m[61] << 0);
2109 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2110 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2111
2112 tmp_mask = (mask_m[31] << 28)
2113 | (mask_m[32] << 26) | (mask_m[33] << 24)
2114 | (mask_m[34] << 22) | (mask_m[35] << 20)
2115 | (mask_m[36] << 18) | (mask_m[37] << 16)
2116 | (mask_m[48] << 14) | (mask_m[39] << 12)
2117 | (mask_m[40] << 10) | (mask_m[41] << 8)
2118 | (mask_m[42] << 6) | (mask_m[43] << 4)
2119 | (mask_m[44] << 2) | (mask_m[45] << 0);
2120 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2121 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2122
2123 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2124 | (mask_m[18] << 26) | (mask_m[18] << 24)
2125 | (mask_m[20] << 22) | (mask_m[20] << 20)
2126 | (mask_m[22] << 18) | (mask_m[22] << 16)
2127 | (mask_m[24] << 14) | (mask_m[24] << 12)
2128 | (mask_m[25] << 10) | (mask_m[26] << 8)
2129 | (mask_m[27] << 6) | (mask_m[28] << 4)
2130 | (mask_m[29] << 2) | (mask_m[30] << 0);
2131 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2132 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2133
2134 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2135 | (mask_m[2] << 26) | (mask_m[3] << 24)
2136 | (mask_m[4] << 22) | (mask_m[5] << 20)
2137 | (mask_m[6] << 18) | (mask_m[7] << 16)
2138 | (mask_m[8] << 14) | (mask_m[9] << 12)
2139 | (mask_m[10] << 10) | (mask_m[11] << 8)
2140 | (mask_m[12] << 6) | (mask_m[13] << 4)
2141 | (mask_m[14] << 2) | (mask_m[15] << 0);
2142 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2143 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2144
2145 tmp_mask = (mask_p[15] << 28)
2146 | (mask_p[14] << 26) | (mask_p[13] << 24)
2147 | (mask_p[12] << 22) | (mask_p[11] << 20)
2148 | (mask_p[10] << 18) | (mask_p[9] << 16)
2149 | (mask_p[8] << 14) | (mask_p[7] << 12)
2150 | (mask_p[6] << 10) | (mask_p[5] << 8)
2151 | (mask_p[4] << 6) | (mask_p[3] << 4)
2152 | (mask_p[2] << 2) | (mask_p[1] << 0);
2153 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2154 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2155
f1dc5600
S		 2156 tmp_mask = (mask_p[30] << 28)
2157 | (mask_p[29] << 26) | (mask_p[28] << 24)
2158 | (mask_p[27] << 22) | (mask_p[26] << 20)
2159 | (mask_p[25] << 18) | (mask_p[24] << 16)
2160 | (mask_p[23] << 14) | (mask_p[22] << 12)
2161 | (mask_p[21] << 10) | (mask_p[20] << 8)
2162 | (mask_p[19] << 6) | (mask_p[18] << 4)
2163 | (mask_p[17] << 2) | (mask_p[16] << 0);
2164 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2165 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2166
f1dc5600
S		 2167 tmp_mask = (mask_p[45] << 28)
2168 | (mask_p[44] << 26) | (mask_p[43] << 24)
2169 | (mask_p[42] << 22) | (mask_p[41] << 20)
2170 | (mask_p[40] << 18) | (mask_p[39] << 16)
2171 | (mask_p[38] << 14) | (mask_p[37] << 12)
2172 | (mask_p[36] << 10) | (mask_p[35] << 8)
2173 | (mask_p[34] << 6) | (mask_p[33] << 4)
2174 | (mask_p[32] << 2) | (mask_p[31] << 0);
2175 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2176 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2177
f1dc5600
S		 2178 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2179 | (mask_p[59] << 26) | (mask_p[58] << 24)
2180 | (mask_p[57] << 22) | (mask_p[56] << 20)
2181 | (mask_p[55] << 18) | (mask_p[54] << 16)
2182 | (mask_p[53] << 14) | (mask_p[52] << 12)
2183 | (mask_p[51] << 10) | (mask_p[50] << 8)
2184 | (mask_p[49] << 6) | (mask_p[48] << 4)
2185 | (mask_p[47] << 2) | (mask_p[46] << 0);
2186 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2187 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2188}
2189
cbe61d8a 2190static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 2191{
f1dc5600
S		 2192 int bb_spur = AR_NO_SPUR;
2193 int bin, cur_bin;
2194 int spur_freq_sd;
2195 int spur_delta_phase;
2196 int denominator;
2197 int upper, lower, cur_vit_mask;
2198 int tmp, new;
2199 int i;
2200 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2201 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2202 };
2203 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2204 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2205 };
2206 int inc[4] = { 0, 100, 0, 0 };
f078f209 2207
f1dc5600
S		 2208 int8_t mask_m[123];
2209 int8_t mask_p[123];
2210 int8_t mask_amt;
2211 int tmp_mask;
2212 int cur_bb_spur;
2213 bool is2GHz = IS_CHAN_2GHZ(chan);
f078f209 2214
f1dc5600
S		 2215 memset(&mask_m, 0, sizeof(int8_t) * 123);
2216 memset(&mask_p, 0, sizeof(int8_t) * 123);
f078f209 2217
f1dc5600 2218 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 2219 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 2220 if (AR_NO_SPUR == cur_bb_spur)
2221 break;
2222 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2223 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2224 bb_spur = cur_bb_spur;
2225 break;
2226 }
2227 }
f078f209 2228
f1dc5600
S		 2229 if (AR_NO_SPUR == bb_spur)
2230 return;
f078f209 2231
f1dc5600 2232 bin = bb_spur * 32;
f078f209 2233
f1dc5600
S		 2234 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2235 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2236 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2237 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2238 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
f078f209 2239
f1dc5600 2240 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
f078f209 2241
f1dc5600
S		 2242 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2243 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2244 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2245 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2246 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2247 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
f078f209 2248
f1dc5600
S		 2249 spur_delta_phase = ((bb_spur * 524288) / 100) &
2250 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
f078f209 2251
f1dc5600
S		 2252 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2253 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
f078f209 2254
f1dc5600
S		 2255 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2256 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2257 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2258 REG_WRITE(ah, AR_PHY_TIMING11, new);
f078f209 2259
f1dc5600
S		 2260 cur_bin = -6000;
2261 upper = bin + 100;
2262 lower = bin - 100;
f078f209 2263
f1dc5600
S		 2264 for (i = 0; i < 4; i++) {
2265 int pilot_mask = 0;
2266 int chan_mask = 0;
2267 int bp = 0;
2268 for (bp = 0; bp < 30; bp++) {
2269 if ((cur_bin > lower) && (cur_bin < upper)) {
2270 pilot_mask = pilot_mask | 0x1 << bp;
2271 chan_mask = chan_mask | 0x1 << bp;
2272 }
2273 cur_bin += 100;
2274 }
2275 cur_bin += inc[i];
2276 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2277 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
f078f209 2278 }
f078f209 2279
f1dc5600
S		 2280 cur_vit_mask = 6100;
2281 upper = bin + 120;
2282 lower = bin - 120;
f078f209 2283
f1dc5600
S		 2284 for (i = 0; i < 123; i++) {
2285 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
f078f209 2286
f1dc5600 2287 /* workaround for gcc bug #37014 */
a085ff71 2288 volatile int tmp_v = abs(cur_vit_mask - bin);
f078f209 2289
a085ff71 2290 if (tmp_v < 75)
f1dc5600
S		 2291 mask_amt = 1;
2292 else
2293 mask_amt = 0;
2294 if (cur_vit_mask < 0)
2295 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2296 else
2297 mask_p[cur_vit_mask / 100] = mask_amt;
2298 }
2299 cur_vit_mask -= 100;
f078f209
LR		 2300 }
2301
f1dc5600
S		 2302 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2303 | (mask_m[48] << 26) | (mask_m[49] << 24)
2304 | (mask_m[50] << 22) | (mask_m[51] << 20)
2305 | (mask_m[52] << 18) | (mask_m[53] << 16)
2306 | (mask_m[54] << 14) | (mask_m[55] << 12)
2307 | (mask_m[56] << 10) | (mask_m[57] << 8)
2308 | (mask_m[58] << 6) | (mask_m[59] << 4)
2309 | (mask_m[60] << 2) | (mask_m[61] << 0);
2310 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2311 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
f078f209 2312
f1dc5600
S		 2313 tmp_mask = (mask_m[31] << 28)
2314 | (mask_m[32] << 26) | (mask_m[33] << 24)
2315 | (mask_m[34] << 22) | (mask_m[35] << 20)
2316 | (mask_m[36] << 18) | (mask_m[37] << 16)
2317 | (mask_m[48] << 14) | (mask_m[39] << 12)
2318 | (mask_m[40] << 10) | (mask_m[41] << 8)
2319 | (mask_m[42] << 6) | (mask_m[43] << 4)
2320 | (mask_m[44] << 2) | (mask_m[45] << 0);
2321 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2322 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
f078f209 2323
f1dc5600
S		 2324 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2325 | (mask_m[18] << 26) | (mask_m[18] << 24)
2326 | (mask_m[20] << 22) | (mask_m[20] << 20)
2327 | (mask_m[22] << 18) | (mask_m[22] << 16)
2328 | (mask_m[24] << 14) | (mask_m[24] << 12)
2329 | (mask_m[25] << 10) | (mask_m[26] << 8)
2330 | (mask_m[27] << 6) | (mask_m[28] << 4)
2331 | (mask_m[29] << 2) | (mask_m[30] << 0);
2332 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2333 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
f078f209 2334
f1dc5600
S		 2335 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2336 | (mask_m[2] << 26) | (mask_m[3] << 24)
2337 | (mask_m[4] << 22) | (mask_m[5] << 20)
2338 | (mask_m[6] << 18) | (mask_m[7] << 16)
2339 | (mask_m[8] << 14) | (mask_m[9] << 12)
2340 | (mask_m[10] << 10) | (mask_m[11] << 8)
2341 | (mask_m[12] << 6) | (mask_m[13] << 4)
2342 | (mask_m[14] << 2) | (mask_m[15] << 0);
2343 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2344 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
f078f209 2345
f1dc5600
S		 2346 tmp_mask = (mask_p[15] << 28)
2347 | (mask_p[14] << 26) | (mask_p[13] << 24)
2348 | (mask_p[12] << 22) | (mask_p[11] << 20)
2349 | (mask_p[10] << 18) | (mask_p[9] << 16)
2350 | (mask_p[8] << 14) | (mask_p[7] << 12)
2351 | (mask_p[6] << 10) | (mask_p[5] << 8)
2352 | (mask_p[4] << 6) | (mask_p[3] << 4)
2353 | (mask_p[2] << 2) | (mask_p[1] << 0);
2354 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2355 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2356
f1dc5600
S		 2357 tmp_mask = (mask_p[30] << 28)
2358 | (mask_p[29] << 26) | (mask_p[28] << 24)
2359 | (mask_p[27] << 22) | (mask_p[26] << 20)
2360 | (mask_p[25] << 18) | (mask_p[24] << 16)
2361 | (mask_p[23] << 14) | (mask_p[22] << 12)
2362 | (mask_p[21] << 10) | (mask_p[20] << 8)
2363 | (mask_p[19] << 6) | (mask_p[18] << 4)
2364 | (mask_p[17] << 2) | (mask_p[16] << 0);
2365 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2366 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2367
f1dc5600
S		 2368 tmp_mask = (mask_p[45] << 28)
2369 | (mask_p[44] << 26) | (mask_p[43] << 24)
2370 | (mask_p[42] << 22) | (mask_p[41] << 20)
2371 | (mask_p[40] << 18) | (mask_p[39] << 16)
2372 | (mask_p[38] << 14) | (mask_p[37] << 12)
2373 | (mask_p[36] << 10) | (mask_p[35] << 8)
2374 | (mask_p[34] << 6) | (mask_p[33] << 4)
2375 | (mask_p[32] << 2) | (mask_p[31] << 0);
2376 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2377 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2378
f1dc5600
S		 2379 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2380 | (mask_p[59] << 26) | (mask_p[58] << 24)
2381 | (mask_p[57] << 22) | (mask_p[56] << 20)
2382 | (mask_p[55] << 18) | (mask_p[54] << 16)
2383 | (mask_p[53] << 14) | (mask_p[52] << 12)
2384 | (mask_p[51] << 10) | (mask_p[50] << 8)
2385 | (mask_p[49] << 6) | (mask_p[48] << 4)
2386 | (mask_p[47] << 2) | (mask_p[46] << 0);
2387 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2388 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2389}
2390
3b319aae
JB		 2391static void ath9k_enable_rfkill(struct ath_hw *ah)
2392{
2393 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2394 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2395
2396 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2397 AR_GPIO_INPUT_MUX2_RFSILENT);
2398
2399 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2400 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2401}
2402
cbe61d8a 2403int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 2404 bool bChannelChange)
f078f209 2405{
1510718d 2406 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2407 u32 saveLedState;
2660b81a 2408 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 2409 u32 saveDefAntenna;
2410 u32 macStaId1;
46fe782c 2411 u64 tsf = 0;
ae8d2858 2412 int i, rx_chainmask, r;
f078f209 2413
43c27613
LR		 2414 ah->txchainmask = common->tx_chainmask;
2415 ah->rxchainmask = common->rx_chainmask;
f078f209 2416
9ecdef4b 2417 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 2418 return -EIO;
f078f209 2419
9ebef799 2420 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 2421 ath9k_hw_getnf(ah, curchan);
2422
2423 if (bChannelChange &&
2660b81a
S		 2424 (ah->chip_fullsleep != true) &&
2425 (ah->curchan != NULL) &&
2426 (chan->channel != ah->curchan->channel) &&
f078f209 2427 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 2428 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
0a475cc6
VT		 2429 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2430 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
f078f209 2431
25c56eec 2432 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 2433 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 2434 ath9k_hw_start_nfcal(ah);
ae8d2858 2435 return 0;
f078f209
LR		 2436 }
2437 }
2438
2439 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2440 if (saveDefAntenna == 0)
2441 saveDefAntenna = 1;
2442
2443 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2444
46fe782c
S		 2445 /* For chips on which RTC reset is done, save TSF before it gets cleared */
2446 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2447 tsf = ath9k_hw_gettsf64(ah);
2448
f078f209
LR		 2449 saveLedState = REG_READ(ah, AR_CFG_LED) &
2450 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2451 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2452
2453 ath9k_hw_mark_phy_inactive(ah);
2454
d7e7d229
LR		 2455 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2456 REG_WRITE(ah,
2457 AR9271_RESET_POWER_DOWN_CONTROL,
2458 AR9271_RADIO_RF_RST);
2459 udelay(50);
2460 }
2461
f078f209 2462 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 2463 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 2464 return -EINVAL;
f078f209
LR		 2465 }
2466
d7e7d229
LR		 2467 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2468 ah->htc_reset_init = false;
2469 REG_WRITE(ah,
2470 AR9271_RESET_POWER_DOWN_CONTROL,
2471 AR9271_GATE_MAC_CTL);
2472 udelay(50);
2473 }
2474
46fe782c
S		 2475 /* Restore TSF */
2476 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2477 ath9k_hw_settsf64(ah, tsf);
2478
369391db
VT		 2479 if (AR_SREV_9280_10_OR_LATER(ah))
2480 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 2481
326bebbc 2482 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2483 /* Enable ASYNC FIFO */
2484 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2485 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2486 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2487 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2488 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2489 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2490 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2491 }
25c56eec 2492 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 2493 if (r)
2494 return r;
f078f209 2495
0ced0e17
JM		 2496 /* Setup MFP options for CCMP */
2497 if (AR_SREV_9280_20_OR_LATER(ah)) {
2498 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2499 * frames when constructing CCMP AAD. */
2500 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2501 0xc7ff);
2502 ah->sw_mgmt_crypto = false;
2503 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2504 /* Disable hardware crypto for management frames */
2505 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2506 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2507 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2508 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2509 ah->sw_mgmt_crypto = true;
2510 } else
2511 ah->sw_mgmt_crypto = true;
2512
f078f209
LR		 2513 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2514 ath9k_hw_set_delta_slope(ah, chan);
2515
2516 if (AR_SREV_9280_10_OR_LATER(ah))
2517 ath9k_hw_9280_spur_mitigate(ah, chan);
2518 else
2519 ath9k_hw_spur_mitigate(ah, chan);
2520
d6509151 2521 ah->eep_ops->set_board_values(ah, chan);
f078f209
LR		 2522
2523 ath9k_hw_decrease_chain_power(ah, chan);
2524
1510718d
LR		 2525 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2526 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 2527 | macStaId1
2528 | AR_STA_ID1_RTS_USE_DEF
2660b81a 2529 | (ah->config.
60b67f51 2530 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 2531 | ah->sta_id1_defaults);
2532 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2533
13b81559 2534 ath_hw_setbssidmask(common);
f078f209
LR		 2535
2536 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2537
3453ad88 2538 ath9k_hw_write_associd(ah);
f078f209
LR		 2539
2540 REG_WRITE(ah, AR_ISR, ~0);
2541
2542 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2543
8fbff4b8
VT		 2544 if (AR_SREV_9280_10_OR_LATER(ah))
2545 ath9k_hw_ar9280_set_channel(ah, chan);
2546 else
ae8d2858
LR		 2547 if (!(ath9k_hw_set_channel(ah, chan)))
2548 return -EIO;
f078f209
LR		 2549
2550 for (i = 0; i < AR_NUM_DCU; i++)
2551 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2552
2660b81a
S		 2553 ah->intr_txqs = 0;
2554 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 2555 ath9k_hw_resettxqueue(ah, i);
2556
2660b81a 2557 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 2558 ath9k_hw_init_qos(ah);
2559
2660b81a 2560 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 2561 ath9k_enable_rfkill(ah);
3b319aae 2562
f078f209
LR		 2563 ath9k_hw_init_user_settings(ah);
2564
326bebbc 2565 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2566 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2567 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2568 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2569 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2570 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2571 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2572
2573 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2574 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2575
2576 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2577 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2578 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2579 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2580 }
326bebbc 2581 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2582 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2583 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2584 }
2585
f078f209
LR		 2586 REG_WRITE(ah, AR_STA_ID1,
2587 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2588
2589 ath9k_hw_set_dma(ah);
2590
2591 REG_WRITE(ah, AR_OBS, 8);
2592
0ef1f168 2593 if (ah->config.intr_mitigation) {
f078f209
LR		 2594 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2595 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2596 }
2597
2598 ath9k_hw_init_bb(ah, chan);
2599
ae8d2858 2600 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2601 return -EIO;
f078f209 2602
2660b81a 2603 rx_chainmask = ah->rxchainmask;
f078f209
LR		 2604 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2605 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2606 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2607 }
2608
2609 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2610
d7e7d229
LR		 2611 /*
2612 * For big endian systems turn on swapping for descriptors
2613 */
f078f209
LR		 2614 if (AR_SREV_9100(ah)) {
2615 u32 mask;
2616 mask = REG_READ(ah, AR_CFG);
2617 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 2618 ath_print(common, ATH_DBG_RESET,
04bd4638 2619 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2620 } else {
2621 mask =
2622 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2623 REG_WRITE(ah, AR_CFG, mask);
c46917bb 2624 ath_print(common, ATH_DBG_RESET,
04bd4638 2625 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2626 }
2627 } else {
d7e7d229
LR		 2628 /* Configure AR9271 target WLAN */
2629 if (AR_SREV_9271(ah))
2630 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 2631#ifdef __BIG_ENDIAN
d7e7d229
LR		 2632 else
2633 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 2634#endif
2635 }
2636
766ec4a9 2637 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 2638 ath9k_hw_btcoex_enable(ah);
2639
ae8d2858 2640 return 0;
f078f209 2641}
7322fd19 2642EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2643
f1dc5600
S		 2644/************************/
2645/* Key Cache Management */
2646/************************/
f078f209 2647
cbe61d8a 2648bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 2649{
f1dc5600 2650 u32 keyType;
f078f209 2651
2660b81a 2652 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 2653 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2654 "keychache entry %u out of range\n", entry);
f078f209
LR		 2655 return false;
2656 }
2657
f1dc5600 2658 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2659
f1dc5600
S		 2660 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2661 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2662 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2663 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2664 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2665 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2666 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2667 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2668
f1dc5600
S		 2669 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2670 u16 micentry = entry + 64;
f078f209 2671
f1dc5600
S		 2672 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2673 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2674 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2675 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2676
f078f209
LR		 2677 }
2678
f078f209
LR		 2679 return true;
2680}
7322fd19 2681EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 2682
cbe61d8a 2683bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 2684{
f1dc5600 2685 u32 macHi, macLo;
f078f209 2686
2660b81a 2687 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 2688 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2689 "keychache entry %u out of range\n", entry);
f1dc5600 2690 return false;
f078f209
LR		 2691 }
2692
f1dc5600
S		 2693 if (mac != NULL) {
2694 macHi = (mac[5] << 8) | mac[4];
2695 macLo = (mac[3] << 24) |
2696 (mac[2] << 16) |
2697 (mac[1] << 8) |
2698 mac[0];
2699 macLo >>= 1;
2700 macLo |= (macHi & 1) << 31;
2701 macHi >>= 1;
f078f209 2702 } else {
f1dc5600 2703 macLo = macHi = 0;
f078f209 2704 }
f1dc5600
S		 2705 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2706 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2707
f1dc5600 2708 return true;
f078f209 2709}
7322fd19 2710EXPORT_SYMBOL(ath9k_hw_keysetmac);
f078f209 2711
cbe61d8a 2712bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 2713 const struct ath9k_keyval *k,
e0caf9ea 2714 const u8 *mac)
f078f209 2715{
2660b81a 2716 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2717 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 2718 u32 key0, key1, key2, key3, key4;
2719 u32 keyType;
f078f209 2720
f1dc5600 2721 if (entry >= pCap->keycache_size) {
c46917bb
LR		 2722 ath_print(common, ATH_DBG_FATAL,
2723 "keycache entry %u out of range\n", entry);
f1dc5600 2724 return false;
f078f209
LR		 2725 }
2726
f1dc5600
S		 2727 switch (k->kv_type) {
2728 case ATH9K_CIPHER_AES_OCB:
2729 keyType = AR_KEYTABLE_TYPE_AES;
2730 break;
2731 case ATH9K_CIPHER_AES_CCM:
2732 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 2733 ath_print(common, ATH_DBG_ANY,
2734 "AES-CCM not supported by mac rev 0x%x\n",
2735 ah->hw_version.macRev);
f1dc5600
S		 2736 return false;
2737 }
2738 keyType = AR_KEYTABLE_TYPE_CCM;
2739 break;
2740 case ATH9K_CIPHER_TKIP:
2741 keyType = AR_KEYTABLE_TYPE_TKIP;
2742 if (ATH9K_IS_MIC_ENABLED(ah)
2743 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 2744 ath_print(common, ATH_DBG_ANY,
2745 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2746 return false;
2747 }
2748 break;
2749 case ATH9K_CIPHER_WEP:
e31a16d6 2750 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 2751 ath_print(common, ATH_DBG_ANY,
2752 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2753 return false;
2754 }
e31a16d6 2755 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 2756 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 2757 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 2758 keyType = AR_KEYTABLE_TYPE_104;
2759 else
2760 keyType = AR_KEYTABLE_TYPE_128;
2761 break;
2762 case ATH9K_CIPHER_CLR:
2763 keyType = AR_KEYTABLE_TYPE_CLR;
2764 break;
2765 default:
c46917bb
LR		 2766 ath_print(common, ATH_DBG_FATAL,
2767 "cipher %u not supported\n", k->kv_type);
f1dc5600 2768 return false;
f078f209
LR		 2769 }
2770
e0caf9ea
JM		 2771 key0 = get_unaligned_le32(k->kv_val + 0);
2772 key1 = get_unaligned_le16(k->kv_val + 4);
2773 key2 = get_unaligned_le32(k->kv_val + 6);
2774 key3 = get_unaligned_le16(k->kv_val + 10);
2775 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 2776 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 2777 key4 &= 0xff;
f078f209 2778
672903b3
JM		 2779 /*
2780 * Note: Key cache registers access special memory area that requires
2781 * two 32-bit writes to actually update the values in the internal
2782 * memory. Consequently, the exact order and pairs used here must be
2783 * maintained.
2784 */
2785
f1dc5600
S		 2786 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2787 u16 micentry = entry + 64;
f078f209 2788
672903b3
JM		 2789 /*
2790 * Write inverted key[47:0] first to avoid Michael MIC errors
2791 * on frames that could be sent or received at the same time.
2792 * The correct key will be written in the end once everything
2793 * else is ready.
2794 */
f1dc5600
S		 2795 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2796 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 2797
2798 /* Write key[95:48] */
f1dc5600
S		 2799 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2800 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2801
2802 /* Write key[127:96] and key type */
f1dc5600
S		 2803 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2804 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 2805
2806 /* Write MAC address for the entry */
f1dc5600 2807 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2808
2660b81a 2809 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 2810 /*
2811 * TKIP uses two key cache entries:
2812 * Michael MIC TX/RX keys in the same key cache entry
2813 * (idx = main index + 64):
2814 * key0 [31:0] = RX key [31:0]
2815 * key1 [15:0] = TX key [31:16]
2816 * key1 [31:16] = reserved
2817 * key2 [31:0] = RX key [63:32]
2818 * key3 [15:0] = TX key [15:0]
2819 * key3 [31:16] = reserved
2820 * key4 [31:0] = TX key [63:32]
2821 */
f1dc5600 2822 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2823
f1dc5600
S		 2824 mic0 = get_unaligned_le32(k->kv_mic + 0);
2825 mic2 = get_unaligned_le32(k->kv_mic + 4);
2826 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2827 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2828 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 2829
2830 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 2831 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2832 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 2833
2834 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 2835 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2836 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 2837
2838 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2839 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2840 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2841 AR_KEYTABLE_TYPE_CLR);
f078f209 2842
f1dc5600 2843 } else {
672903b3
JM		 2844 /*
2845 * TKIP uses four key cache entries (two for group
2846 * keys):
2847 * Michael MIC TX/RX keys are in different key cache
2848 * entries (idx = main index + 64 for TX and
2849 * main index + 32 + 96 for RX):
2850 * key0 [31:0] = TX/RX MIC key [31:0]
2851 * key1 [31:0] = reserved
2852 * key2 [31:0] = TX/RX MIC key [63:32]
2853 * key3 [31:0] = reserved
2854 * key4 [31:0] = reserved
2855 *
2856 * Upper layer code will call this function separately
2857 * for TX and RX keys when these registers offsets are
2858 * used.
2859 */
f1dc5600 2860 u32 mic0, mic2;
f078f209 2861
f1dc5600
S		 2862 mic0 = get_unaligned_le32(k->kv_mic + 0);
2863 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 2864
2865 /* Write MIC key[31:0] */
f1dc5600
S		 2866 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2867 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 2868
2869 /* Write MIC key[63:32] */
f1dc5600
S		 2870 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2871 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 2872
2873 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2874 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2875 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2876 AR_KEYTABLE_TYPE_CLR);
2877 }
672903b3
JM		 2878
2879 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 2880 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2881 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 2882
2883 /*
2884 * Write the correct (un-inverted) key[47:0] last to enable
2885 * TKIP now that all other registers are set with correct
2886 * values.
2887 */
f1dc5600
S		 2888 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2889 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2890 } else {
672903b3 2891 /* Write key[47:0] */
f1dc5600
S		 2892 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2893 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 2894
2895 /* Write key[95:48] */
f1dc5600
S		 2896 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2897 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2898
2899 /* Write key[127:96] and key type */
f1dc5600
S		 2900 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2901 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2902
672903b3 2903 /* Write MAC address for the entry */
f1dc5600
S		 2904 (void) ath9k_hw_keysetmac(ah, entry, mac);
2905 }
f078f209 2906
f078f209
LR		 2907 return true;
2908}
7322fd19 2909EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 2910
cbe61d8a 2911bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 2912{
2660b81a 2913 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 2914 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2915 if (val & AR_KEYTABLE_VALID)
2916 return true;
2917 }
2918 return false;
f078f209 2919}
7322fd19 2920EXPORT_SYMBOL(ath9k_hw_keyisvalid);
f078f209 2921
f1dc5600
S		 2922/******************************/
2923/* Power Management (Chipset) */
2924/******************************/
2925
cbe61d8a 2926static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2927{
f1dc5600
S		 2928 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2929 if (setChip) {
2930 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2931 AR_RTC_FORCE_WAKE_EN);
2932 if (!AR_SREV_9100(ah))
2933 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2934
4921be80
S		 2935 if(!AR_SREV_5416(ah))
2936 REG_CLR_BIT(ah, (AR_RTC_RESET),
2937 AR_RTC_RESET_EN);
f1dc5600 2938 }
f078f209
LR		 2939}
2940
cbe61d8a 2941static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2942{
f1dc5600
S		 2943 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2944 if (setChip) {
2660b81a 2945 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2946
f1dc5600
S		 2947 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2948 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2949 AR_RTC_FORCE_WAKE_ON_INT);
2950 } else {
2951 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2952 AR_RTC_FORCE_WAKE_EN);
f078f209 2953 }
f078f209 2954 }
f078f209
LR		 2955}
2956
cbe61d8a 2957static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2958{
f1dc5600
S		 2959 u32 val;
2960 int i;
f078f209 2961
f1dc5600
S		 2962 if (setChip) {
2963 if ((REG_READ(ah, AR_RTC_STATUS) &
2964 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2965 if (ath9k_hw_set_reset_reg(ah,
2966 ATH9K_RESET_POWER_ON) != true) {
2967 return false;
2968 }
63a75b91 2969 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 2970 }
2971 if (AR_SREV_9100(ah))
2972 REG_SET_BIT(ah, AR_RTC_RESET,
2973 AR_RTC_RESET_EN);
f078f209 2974
f1dc5600
S		 2975 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2976 AR_RTC_FORCE_WAKE_EN);
2977 udelay(50);
f078f209 2978
f1dc5600
S		 2979 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2980 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2981 if (val == AR_RTC_STATUS_ON)
2982 break;
2983 udelay(50);
2984 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2985 AR_RTC_FORCE_WAKE_EN);
f078f209 2986 }
f1dc5600 2987 if (i == 0) {
c46917bb
LR		 2988 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2989 "Failed to wakeup in %uus\n",
2990 POWER_UP_TIME / 20);
f1dc5600 2991 return false;
f078f209 2992 }
f078f209
LR		 2993 }
2994
f1dc5600 2995 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2996
f1dc5600 2997 return true;
f078f209
LR		 2998}
2999
9ecdef4b 3000bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 3001{
c46917bb 3002 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 3003 int status = true, setChip = true;
f1dc5600
S		 3004 static const char *modes[] = {
3005 "AWAKE",
3006 "FULL-SLEEP",
3007 "NETWORK SLEEP",
3008 "UNDEFINED"
3009 };
f1dc5600 3010
cbdec975
GJ		 3011 if (ah->power_mode == mode)
3012 return status;
3013
c46917bb
LR		 3014 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
3015 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 3016
3017 switch (mode) {
3018 case ATH9K_PM_AWAKE:
3019 status = ath9k_hw_set_power_awake(ah, setChip);
3020 break;
3021 case ATH9K_PM_FULL_SLEEP:
3022 ath9k_set_power_sleep(ah, setChip);
2660b81a 3023 ah->chip_fullsleep = true;
f1dc5600
S		 3024 break;
3025 case ATH9K_PM_NETWORK_SLEEP:
3026 ath9k_set_power_network_sleep(ah, setChip);
3027 break;
f078f209 3028 default:
c46917bb
LR		 3029 ath_print(common, ATH_DBG_FATAL,
3030 "Unknown power mode %u\n", mode);
f078f209
LR		 3031 return false;
3032 }
2660b81a 3033 ah->power_mode = mode;
f1dc5600
S		 3034
3035 return status;
f078f209 3036}
7322fd19 3037EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 3038
24c1a280
LR		 3039/*
3040 * Helper for ASPM support.
3041 *
3042 * Disable PLL when in L0s as well as receiver clock when in L1.
3043 * This power saving option must be enabled through the SerDes.
3044 *
3045 * Programming the SerDes must go through the same 288 bit serial shift
3046 * register as the other analog registers. Hence the 9 writes.
3047 */
93b1b37f 3048void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
f078f209 3049{
f1dc5600 3050 u8 i;
93b1b37f 3051 u32 val;
f078f209 3052
2660b81a 3053 if (ah->is_pciexpress != true)
f1dc5600 3054 return;
f078f209 3055
24c1a280 3056 /* Do not touch SerDes registers */
2660b81a 3057 if (ah->config.pcie_powersave_enable == 2)
f1dc5600
S		 3058 return;
3059
24c1a280 3060 /* Nothing to do on restore for 11N */
93b1b37f
VN		 3061 if (!restore) {
3062 if (AR_SREV_9280_20_OR_LATER(ah)) {
3063 /*
3064 * AR9280 2.0 or later chips use SerDes values from the
3065 * initvals.h initialized depending on chipset during
3066 * ath9k_hw_init()
3067 */
3068 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
3069 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
3070 INI_RA(&ah->iniPcieSerdes, i, 1));
3071 }
3072 } else if (AR_SREV_9280(ah) &&
3073 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
3074 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3075 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3076
3077 /* RX shut off when elecidle is asserted */
3078 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3079 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3080 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3081
3082 /* Shut off CLKREQ active in L1 */
3083 if (ah->config.pcie_clock_req)
3084 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3085 else
3086 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
f1dc5600 3087
93b1b37f
VN		 3088 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3089 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3090 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
f1dc5600 3091
93b1b37f
VN		 3092 /* Load the new settings */
3093 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f1dc5600 3094
93b1b37f
VN		 3095 } else {
3096 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3097 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
f1dc5600 3098
93b1b37f
VN		 3099 /* RX shut off when elecidle is asserted */
3100 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3101 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3102 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
f1dc5600 3103
93b1b37f
VN		 3104 /*
3105 * Ignore ah->ah_config.pcie_clock_req setting for
3106 * pre-AR9280 11n
3107 */
3108 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
24c1a280 3109
93b1b37f
VN		 3110 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3111 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3112 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
24c1a280 3113
93b1b37f
VN		 3114 /* Load the new settings */
3115 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3116 }
24c1a280 3117
93b1b37f 3118 udelay(1000);
24c1a280 3119
93b1b37f
VN		 3120 /* set bit 19 to allow forcing of pcie core into L1 state */
3121 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
f078f209 3122
93b1b37f
VN		 3123 /* Several PCIe massages to ensure proper behaviour */
3124 if (ah->config.pcie_waen) {
3125 val = ah->config.pcie_waen;
3126 if (!power_off)
3127 val &= (~AR_WA_D3_L1_DISABLE);
3128 } else {
3129 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3130 AR_SREV_9287(ah)) {
3131 val = AR9285_WA_DEFAULT;
3132 if (!power_off)
3133 val &= (~AR_WA_D3_L1_DISABLE);
3134 } else if (AR_SREV_9280(ah)) {
3135 /*
3136 * On AR9280 chips bit 22 of 0x4004 needs to be
3137 * set otherwise card may disappear.
3138 */
3139 val = AR9280_WA_DEFAULT;
3140 if (!power_off)
3141 val &= (~AR_WA_D3_L1_DISABLE);
3142 } else
3143 val = AR_WA_DEFAULT;
3144 }
6d08b9b9 3145
93b1b37f
VN		 3146 REG_WRITE(ah, AR_WA, val);
3147 }
f1dc5600 3148
93b1b37f 3149 if (power_off) {
24c1a280 3150 /*
93b1b37f
VN		 3151 * Set PCIe workaround bits
3152 * bit 14 in WA register (disable L1) should only
3153 * be set when device enters D3 and be cleared
3154 * when device comes back to D0.
24c1a280 3155 */
93b1b37f
VN		 3156 if (ah->config.pcie_waen) {
3157 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
3158 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3159 } else {
3160 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3161 AR_SREV_9287(ah)) &&
3162 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
3163 (AR_SREV_9280(ah) &&
3164 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
3165 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3166 }
3167 }
f1dc5600 3168 }
f078f209 3169}
7322fd19 3170EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
f078f209 3171
f1dc5600
S		 3172/**********************/
3173/* Interrupt Handling */
3174/**********************/
3175
cbe61d8a 3176bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 3177{
3178 u32 host_isr;
3179
3180 if (AR_SREV_9100(ah))
3181 return true;
3182
3183 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3184 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3185 return true;
3186
3187 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3188 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3189 && (host_isr != AR_INTR_SPURIOUS))
3190 return true;
3191
3192 return false;
3193}
7322fd19 3194EXPORT_SYMBOL(ath9k_hw_intrpend);
f078f209 3195
cbe61d8a 3196bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 3197{
3198 u32 isr = 0;
3199 u32 mask2 = 0;
2660b81a 3200 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 3201 u32 sync_cause = 0;
3202 bool fatal_int = false;
c46917bb 3203 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 3204
3205 if (!AR_SREV_9100(ah)) {
3206 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3207 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3208 == AR_RTC_STATUS_ON) {
3209 isr = REG_READ(ah, AR_ISR);
3210 }
3211 }
3212
f1dc5600
S		 3213 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3214 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 3215
3216 *masked = 0;
3217
3218 if (!isr && !sync_cause)
3219 return false;
3220 } else {
3221 *masked = 0;
3222 isr = REG_READ(ah, AR_ISR);
3223 }
3224
3225 if (isr) {
f078f209
LR		 3226 if (isr & AR_ISR_BCNMISC) {
3227 u32 isr2;
3228 isr2 = REG_READ(ah, AR_ISR_S2);
3229 if (isr2 & AR_ISR_S2_TIM)
3230 mask2 |= ATH9K_INT_TIM;
3231 if (isr2 & AR_ISR_S2_DTIM)
3232 mask2 |= ATH9K_INT_DTIM;
3233 if (isr2 & AR_ISR_S2_DTIMSYNC)
3234 mask2 |= ATH9K_INT_DTIMSYNC;
3235 if (isr2 & (AR_ISR_S2_CABEND))
3236 mask2 |= ATH9K_INT_CABEND;
3237 if (isr2 & AR_ISR_S2_GTT)
3238 mask2 |= ATH9K_INT_GTT;
3239 if (isr2 & AR_ISR_S2_CST)
3240 mask2 |= ATH9K_INT_CST;
4af9cf4f
S		 3241 if (isr2 & AR_ISR_S2_TSFOOR)
3242 mask2 |= ATH9K_INT_TSFOOR;
f078f209
LR		 3243 }
3244
3245 isr = REG_READ(ah, AR_ISR_RAC);
3246 if (isr == 0xffffffff) {
3247 *masked = 0;
3248 return false;
3249 }
3250
3251 *masked = isr & ATH9K_INT_COMMON;
3252
0ef1f168 3253 if (ah->config.intr_mitigation) {
f078f209
LR		 3254 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3255 *masked |= ATH9K_INT_RX;
3256 }
3257
3258 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3259 *masked |= ATH9K_INT_RX;
3260 if (isr &
3261 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3262 AR_ISR_TXEOL)) {
3263 u32 s0_s, s1_s;
3264
3265 *masked |= ATH9K_INT_TX;
3266
3267 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 3268 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3269 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 3270
3271 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 3272 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3273 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 3274 }
3275
3276 if (isr & AR_ISR_RXORN) {
c46917bb
LR		 3277 ath_print(common, ATH_DBG_INTERRUPT,
3278 "receive FIFO overrun interrupt\n");
f078f209
LR		 3279 }
3280
3281 if (!AR_SREV_9100(ah)) {
60b67f51 3282 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3283 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3284 if (isr5 & AR_ISR_S5_TIM_TIMER)
3285 *masked |= ATH9K_INT_TIM_TIMER;
3286 }
3287 }
3288
3289 *masked |= mask2;
3290 }
f1dc5600 3291
f078f209
LR		 3292 if (AR_SREV_9100(ah))
3293 return true;
f1dc5600 3294
ff155a45
VT		 3295 if (isr & AR_ISR_GENTMR) {
3296 u32 s5_s;
3297
3298 s5_s = REG_READ(ah, AR_ISR_S5_S);
3299 if (isr & AR_ISR_GENTMR) {
3300 ah->intr_gen_timer_trigger =
3301 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3302
3303 ah->intr_gen_timer_thresh =
3304 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3305
3306 if (ah->intr_gen_timer_trigger)
3307 *masked |= ATH9K_INT_GENTIMER;
3308
3309 }
3310 }
3311
f078f209
LR		 3312 if (sync_cause) {
3313 fatal_int =
3314 (sync_cause &
3315 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3316 ? true : false;
3317
3318 if (fatal_int) {
3319 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
c46917bb
LR		 3320 ath_print(common, ATH_DBG_ANY,
3321 "received PCI FATAL interrupt\n");
f078f209
LR		 3322 }
3323 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
c46917bb
LR		 3324 ath_print(common, ATH_DBG_ANY,
3325 "received PCI PERR interrupt\n");
f078f209 3326 }
a89bff9a 3327 *masked |= ATH9K_INT_FATAL;
f078f209
LR		 3328 }
3329 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
c46917bb
LR		 3330 ath_print(common, ATH_DBG_INTERRUPT,
3331 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 3332 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3333 REG_WRITE(ah, AR_RC, 0);
3334 *masked |= ATH9K_INT_FATAL;
3335 }
3336 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
c46917bb
LR		 3337 ath_print(common, ATH_DBG_INTERRUPT,
3338 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 3339 }
3340
3341 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3342 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3343 }
f1dc5600 3344
f078f209
LR		 3345 return true;
3346}
7322fd19 3347EXPORT_SYMBOL(ath9k_hw_getisr);
f078f209 3348
cbe61d8a 3349enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 3350{
2660b81a 3351 u32 omask = ah->mask_reg;
f078f209 3352 u32 mask, mask2;
2660b81a 3353 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 3354 struct ath_common *common = ath9k_hw_common(ah);
f078f209 3355
c46917bb 3356 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 3357
3358 if (omask & ATH9K_INT_GLOBAL) {
c46917bb 3359 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 3360 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3361 (void) REG_READ(ah, AR_IER);
3362 if (!AR_SREV_9100(ah)) {
3363 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3364 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3365
3366 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3367 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3368 }
3369 }
3370
3371 mask = ints & ATH9K_INT_COMMON;
3372 mask2 = 0;
3373
3374 if (ints & ATH9K_INT_TX) {
2660b81a 3375 if (ah->txok_interrupt_mask)
f078f209 3376 mask |= AR_IMR_TXOK;
2660b81a 3377 if (ah->txdesc_interrupt_mask)
f078f209 3378 mask |= AR_IMR_TXDESC;
2660b81a 3379 if (ah->txerr_interrupt_mask)
f078f209 3380 mask |= AR_IMR_TXERR;
2660b81a 3381 if (ah->txeol_interrupt_mask)
f078f209
LR		 3382 mask |= AR_IMR_TXEOL;
3383 }
3384 if (ints & ATH9K_INT_RX) {
3385 mask |= AR_IMR_RXERR;
0ef1f168 3386 if (ah->config.intr_mitigation)
f078f209
LR		 3387 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3388 else
3389 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 3390 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 3391 mask |= AR_IMR_GENTMR;
3392 }
3393
3394 if (ints & (ATH9K_INT_BMISC)) {
3395 mask |= AR_IMR_BCNMISC;
3396 if (ints & ATH9K_INT_TIM)
3397 mask2 |= AR_IMR_S2_TIM;
3398 if (ints & ATH9K_INT_DTIM)
3399 mask2 |= AR_IMR_S2_DTIM;
3400 if (ints & ATH9K_INT_DTIMSYNC)
3401 mask2 |= AR_IMR_S2_DTIMSYNC;
3402 if (ints & ATH9K_INT_CABEND)
4af9cf4f
S		 3403 mask2 |= AR_IMR_S2_CABEND;
3404 if (ints & ATH9K_INT_TSFOOR)
3405 mask2 |= AR_IMR_S2_TSFOOR;
f078f209
LR		 3406 }
3407
3408 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3409 mask |= AR_IMR_BCNMISC;
3410 if (ints & ATH9K_INT_GTT)
3411 mask2 |= AR_IMR_S2_GTT;
3412 if (ints & ATH9K_INT_CST)
3413 mask2 |= AR_IMR_S2_CST;
3414 }
3415
c46917bb 3416 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 3417 REG_WRITE(ah, AR_IMR, mask);
3418 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3419 AR_IMR_S2_DTIM |
3420 AR_IMR_S2_DTIMSYNC |
3421 AR_IMR_S2_CABEND |
3422 AR_IMR_S2_CABTO |
3423 AR_IMR_S2_TSFOOR |
3424 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3425 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2660b81a 3426 ah->mask_reg = ints;
f078f209 3427
60b67f51 3428 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3429 if (ints & ATH9K_INT_TIM_TIMER)
3430 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3431 else
3432 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3433 }
3434
3435 if (ints & ATH9K_INT_GLOBAL) {
c46917bb 3436 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 3437 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3438 if (!AR_SREV_9100(ah)) {
3439 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3440 AR_INTR_MAC_IRQ);
3441 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3442
3443
3444 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3445 AR_INTR_SYNC_DEFAULT);
3446 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3447 AR_INTR_SYNC_DEFAULT);
3448 }
c46917bb
LR		 3449 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3450 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
f078f209
LR		 3451 }
3452
3453 return omask;
3454}
7322fd19 3455EXPORT_SYMBOL(ath9k_hw_set_interrupts);
f078f209 3456
f1dc5600
S		 3457/*******************/
3458/* Beacon Handling */
3459/*******************/
3460
cbe61d8a 3461void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 3462{
f078f209
LR		 3463 int flags = 0;
3464
2660b81a 3465 ah->beacon_interval = beacon_period;
f078f209 3466
2660b81a 3467 switch (ah->opmode) {
d97809db
CM		 3468 case NL80211_IFTYPE_STATION:
3469 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 3470 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3471 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3472 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3473 flags |= AR_TBTT_TIMER_EN;
3474 break;
d97809db 3475 case NL80211_IFTYPE_ADHOC:
9cb5412b 3476 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 3477 REG_SET_BIT(ah, AR_TXCFG,
3478 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3479 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3480 TU_TO_USEC(next_beacon +
2660b81a
S		 3481 (ah->atim_window ? ah->
3482 atim_window : 1)));
f078f209 3483 flags |= AR_NDP_TIMER_EN;
d97809db 3484 case NL80211_IFTYPE_AP:
f078f209
LR		 3485 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3486 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3487 TU_TO_USEC(next_beacon -
2660b81a 3488 ah->config.
60b67f51 3489 dma_beacon_response_time));
f078f209
LR		 3490 REG_WRITE(ah, AR_NEXT_SWBA,
3491 TU_TO_USEC(next_beacon -
2660b81a 3492 ah->config.
60b67f51 3493 sw_beacon_response_time));
f078f209
LR		 3494 flags |=
3495 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3496 break;
d97809db 3497 default:
c46917bb
LR		 3498 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3499 "%s: unsupported opmode: %d\n",
3500 __func__, ah->opmode);
d97809db
CM		 3501 return;
3502 break;
f078f209
LR		 3503 }
3504
3505 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3506 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3507 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3508 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3509
3510 beacon_period &= ~ATH9K_BEACON_ENA;
3511 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 3512 ath9k_hw_reset_tsf(ah);
3513 }
3514
3515 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3516}
7322fd19 3517EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 3518
cbe61d8a 3519void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 3520 const struct ath9k_beacon_state *bs)
f078f209
LR		 3521{
3522 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 3523 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 3524 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 3525
3526 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3527
3528 REG_WRITE(ah, AR_BEACON_PERIOD,
3529 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3530 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3531 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3532
3533 REG_RMW_FIELD(ah, AR_RSSI_THR,
3534 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3535
3536 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3537
3538 if (bs->bs_sleepduration > beaconintval)
3539 beaconintval = bs->bs_sleepduration;
3540
3541 dtimperiod = bs->bs_dtimperiod;
3542 if (bs->bs_sleepduration > dtimperiod)
3543 dtimperiod = bs->bs_sleepduration;
3544
3545 if (beaconintval == dtimperiod)
3546 nextTbtt = bs->bs_nextdtim;
3547 else
3548 nextTbtt = bs->bs_nexttbtt;
3549
c46917bb
LR		 3550 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3551 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3552 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3553 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3554
f1dc5600
S		 3555 REG_WRITE(ah, AR_NEXT_DTIM,
3556 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3557 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3558
f1dc5600
S		 3559 REG_WRITE(ah, AR_SLEEP1,
3560 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3561 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3562
f1dc5600
S		 3563 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3564 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3565 else
3566 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3567
f1dc5600
S		 3568 REG_WRITE(ah, AR_SLEEP2,
3569 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3570
f1dc5600
S		 3571 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3572 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3573
f1dc5600
S		 3574 REG_SET_BIT(ah, AR_TIMER_MODE,
3575 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3576 AR_DTIM_TIMER_EN);
f078f209 3577
4af9cf4f
S		 3578 /* TSF Out of Range Threshold */
3579 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 3580}
7322fd19 3581EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 3582
f1dc5600
S		 3583/*******************/
3584/* HW Capabilities */
3585/*******************/
3586
eef7a574 3587void ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 3588{
2660b81a 3589 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 3590 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 3591 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 3592 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 3593
f1dc5600 3594 u16 capField = 0, eeval;
f078f209 3595
f74df6fb 3596 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 3597 regulatory->current_rd = eeval;
f078f209 3598
f74df6fb 3599 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 3600 if (AR_SREV_9285_10_OR_LATER(ah))
3601 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 3602 regulatory->current_rd_ext = eeval;
f078f209 3603
f74df6fb 3604 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 3605
2660b81a 3606 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 3607 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 3608 if (regulatory->current_rd == 0x64 ||
3609 regulatory->current_rd == 0x65)
3610 regulatory->current_rd += 5;
3611 else if (regulatory->current_rd == 0x41)
3612 regulatory->current_rd = 0x43;
c46917bb
LR		 3613 ath_print(common, ATH_DBG_REGULATORY,
3614 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 3615 }
f078f209 3616
f74df6fb 3617 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
f1dc5600 3618 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3619
f1dc5600
S		 3620 if (eeval & AR5416_OPFLAGS_11A) {
3621 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 3622 if (ah->config.ht_enable) {
f1dc5600
S		 3623 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3624 set_bit(ATH9K_MODE_11NA_HT20,
3625 pCap->wireless_modes);
3626 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3627 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3628 pCap->wireless_modes);
3629 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3630 pCap->wireless_modes);
3631 }
f078f209 3632 }
f078f209
LR		 3633 }
3634
f1dc5600 3635 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 3636 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 3637 if (ah->config.ht_enable) {
f1dc5600
S		 3638 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3639 set_bit(ATH9K_MODE_11NG_HT20,
3640 pCap->wireless_modes);
3641 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3642 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3643 pCap->wireless_modes);
3644 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3645 pCap->wireless_modes);
3646 }
3647 }
f078f209 3648 }
f1dc5600 3649
f74df6fb 3650 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 3651 /*
3652 * For AR9271 we will temporarilly uses the rx chainmax as read from
3653 * the EEPROM.
3654 */
8147f5de 3655 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 3656 !(eeval & AR5416_OPFLAGS_11A) &&
3657 !(AR_SREV_9271(ah)))
3658 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 3659 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3660 else
d7e7d229 3661 /* Use rx_chainmask from EEPROM. */
8147f5de 3662 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 3663
d535a42a 3664 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 3665 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3666
f1dc5600
S		 3667 pCap->low_2ghz_chan = 2312;
3668 pCap->high_2ghz_chan = 2732;
f078f209 3669
f1dc5600
S		 3670 pCap->low_5ghz_chan = 4920;
3671 pCap->high_5ghz_chan = 6100;
f078f209 3672
f1dc5600
S		 3673 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3674 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3675 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3676
f1dc5600
S		 3677 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3678 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3679 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3680
2660b81a 3681 if (ah->config.ht_enable)
f1dc5600
S		 3682 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3683 else
3684 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3685
f1dc5600
S		 3686 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3687 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3688 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3689 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3690
f1dc5600
S		 3691 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3692 pCap->total_queues =
3693 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3694 else
3695 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3696
f1dc5600
S		 3697 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3698 pCap->keycache_size =
3699 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3700 else
3701 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3702
f1dc5600 3703 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f1dc5600 3704 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3705
cb33c412
SB		 3706 if (AR_SREV_9285_10_OR_LATER(ah))
3707 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3708 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3709 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3710 else
3711 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3712
f1dc5600
S		 3713 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3714 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3715 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3716 } else {
3717 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3718 }
3719
f1dc5600
S		 3720 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3721
e97275cb 3722#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 3723 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3724 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3725 ah->rfkill_gpio =
3726 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3727 ah->rfkill_polarity =
3728 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 3729
3730 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3731 }
f1dc5600 3732#endif
f078f209 3733
a3ca95fb 3734 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3735
e7594072 3736 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3737 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3738 else
3739 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3740
608b88cb 3741 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 3742 pCap->reg_cap =
3743 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3744 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3745 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3746 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3747 } else {
f1dc5600
S		 3748 pCap->reg_cap =
3749 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3750 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3751 }
f078f209 3752
ebb90cfc
SB		 3753 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3754 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3755 AR_SREV_5416(ah))
3756 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 3757
3758 pCap->num_antcfg_5ghz =
f74df6fb 3759 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3760 pCap->num_antcfg_2ghz =
f74df6fb 3761 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3762
fe12946e 3763 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 3764 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 3765 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3766 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 3767
8c8f9ba7 3768 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 3769 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3770 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 3771 } else {
766ec4a9 3772 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 3773 }
22f25d0d 3774 } else {
766ec4a9 3775 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 3776 }
f078f209
LR		 3777}
3778
cbe61d8a 3779bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3780 u32 capability, u32 *result)
f078f209 3781{
608b88cb 3782 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 3783 switch (type) {
3784 case ATH9K_CAP_CIPHER:
3785 switch (capability) {
3786 case ATH9K_CIPHER_AES_CCM:
3787 case ATH9K_CIPHER_AES_OCB:
3788 case ATH9K_CIPHER_TKIP:
3789 case ATH9K_CIPHER_WEP:
3790 case ATH9K_CIPHER_MIC:
3791 case ATH9K_CIPHER_CLR:
3792 return true;
3793 default:
3794 return false;
3795 }
3796 case ATH9K_CAP_TKIP_MIC:
3797 switch (capability) {
3798 case 0:
3799 return true;
3800 case 1:
2660b81a 3801 return (ah->sta_id1_defaults &
f1dc5600
S		 3802 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3803 false;
3804 }
3805 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 3806 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 3807 false : true;
f1dc5600
S		 3808 case ATH9K_CAP_DIVERSITY:
3809 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3810 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3811 true : false;
f1dc5600
S		 3812 case ATH9K_CAP_MCAST_KEYSRCH:
3813 switch (capability) {
3814 case 0:
3815 return true;
3816 case 1:
3817 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3818 return false;
3819 } else {
2660b81a 3820 return (ah->sta_id1_defaults &
f1dc5600
S		 3821 AR_STA_ID1_MCAST_KSRCH) ? true :
3822 false;
3823 }
3824 }
3825 return false;
f1dc5600
S		 3826 case ATH9K_CAP_TXPOW:
3827 switch (capability) {
3828 case 0:
3829 return 0;
3830 case 1:
608b88cb 3831 *result = regulatory->power_limit;
f1dc5600
S		 3832 return 0;
3833 case 2:
608b88cb 3834 *result = regulatory->max_power_level;
f1dc5600
S		 3835 return 0;
3836 case 3:
608b88cb 3837 *result = regulatory->tp_scale;
f1dc5600
S		 3838 return 0;
3839 }
3840 return false;
8bd1d07f
SB		 3841 case ATH9K_CAP_DS:
3842 return (AR_SREV_9280_20_OR_LATER(ah) &&
3843 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3844 ? false : true;
f1dc5600
S		 3845 default:
3846 return false;
f078f209 3847 }
f078f209 3848}
7322fd19 3849EXPORT_SYMBOL(ath9k_hw_getcapability);
f078f209 3850
cbe61d8a 3851bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3852 u32 capability, u32 setting, int *status)
f078f209 3853{
f1dc5600 3854 u32 v;
f078f209 3855
f1dc5600
S		 3856 switch (type) {
3857 case ATH9K_CAP_TKIP_MIC:
3858 if (setting)
2660b81a 3859 ah->sta_id1_defaults |=
f1dc5600
S		 3860 AR_STA_ID1_CRPT_MIC_ENABLE;
3861 else
2660b81a 3862 ah->sta_id1_defaults &=
f1dc5600
S		 3863 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3864 return true;
3865 case ATH9K_CAP_DIVERSITY:
3866 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3867 if (setting)
3868 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3869 else
3870 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3871 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3872 return true;
3873 case ATH9K_CAP_MCAST_KEYSRCH:
3874 if (setting)
2660b81a 3875 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3876 else
2660b81a 3877 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3878 return true;
f1dc5600
S		 3879 default:
3880 return false;
f078f209
LR		 3881 }
3882}
7322fd19 3883EXPORT_SYMBOL(ath9k_hw_setcapability);
f078f209 3884
f1dc5600
S		 3885/****************************/
3886/* GPIO / RFKILL / Antennae */
3887/****************************/
f078f209 3888
cbe61d8a 3889static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 3890 u32 gpio, u32 type)
3891{
3892 int addr;
3893 u32 gpio_shift, tmp;
f078f209 3894
f1dc5600
S		 3895 if (gpio > 11)
3896 addr = AR_GPIO_OUTPUT_MUX3;
3897 else if (gpio > 5)
3898 addr = AR_GPIO_OUTPUT_MUX2;
3899 else
3900 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3901
f1dc5600 3902 gpio_shift = (gpio % 6) * 5;
f078f209 3903
f1dc5600
S		 3904 if (AR_SREV_9280_20_OR_LATER(ah)
3905 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3906 REG_RMW(ah, addr, (type << gpio_shift),
3907 (0x1f << gpio_shift));
f078f209 3908 } else {
f1dc5600
S		 3909 tmp = REG_READ(ah, addr);
3910 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3911 tmp &= ~(0x1f << gpio_shift);
3912 tmp |= (type << gpio_shift);
3913 REG_WRITE(ah, addr, tmp);
f078f209 3914 }
f078f209
LR		 3915}
3916
cbe61d8a 3917void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 3918{
f1dc5600 3919 u32 gpio_shift;
f078f209 3920
9680e8a3 3921 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 3922
f1dc5600 3923 gpio_shift = gpio << 1;
f078f209 3924
f1dc5600
S		 3925 REG_RMW(ah,
3926 AR_GPIO_OE_OUT,
3927 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3928 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 3929}
7322fd19 3930EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 3931
cbe61d8a 3932u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 3933{
cb33c412
SB		 3934#define MS_REG_READ(x, y) \
3935 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3936
2660b81a 3937 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 3938 return 0xffffffff;
f078f209 3939
ac88b6ec
VN		 3940 if (AR_SREV_9287_10_OR_LATER(ah))
3941 return MS_REG_READ(AR9287, gpio) != 0;
3942 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 3943 return MS_REG_READ(AR9285, gpio) != 0;
3944 else if (AR_SREV_9280_10_OR_LATER(ah))
3945 return MS_REG_READ(AR928X, gpio) != 0;
3946 else
3947 return MS_REG_READ(AR, gpio) != 0;
f078f209 3948}
7322fd19 3949EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 3950
cbe61d8a 3951void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 3952 u32 ah_signal_type)
f078f209 3953{
f1dc5600 3954 u32 gpio_shift;
f078f209 3955
f1dc5600 3956 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3957
f1dc5600 3958 gpio_shift = 2 * gpio;
f078f209 3959
f1dc5600
S		 3960 REG_RMW(ah,
3961 AR_GPIO_OE_OUT,
3962 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3963 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 3964}
7322fd19 3965EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 3966
cbe61d8a 3967void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 3968{
f1dc5600
S		 3969 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3970 AR_GPIO_BIT(gpio));
f078f209 3971}
7322fd19 3972EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 3973
cbe61d8a 3974u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 3975{
f1dc5600 3976 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 3977}
7322fd19 3978EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 3979
cbe61d8a 3980void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 3981{
f1dc5600 3982 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 3983}
7322fd19 3984EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 3985
cbe61d8a 3986bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
f1dc5600
S		 3987 enum ath9k_ant_setting settings,
3988 struct ath9k_channel *chan,
3989 u8 *tx_chainmask,
3990 u8 *rx_chainmask,
3991 u8 *antenna_cfgd)
f078f209 3992{
f1dc5600 3993 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
f078f209 3994
f1dc5600
S		 3995 if (AR_SREV_9280(ah)) {
3996 if (!tx_chainmask_cfg) {
f078f209 3997
f1dc5600
S		 3998 tx_chainmask_cfg = *tx_chainmask;
3999 rx_chainmask_cfg = *rx_chainmask;
4000 }
f078f209 4001
f1dc5600
S		 4002 switch (settings) {
4003 case ATH9K_ANT_FIXED_A:
4004 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
4005 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
4006 *antenna_cfgd = true;
4007 break;
4008 case ATH9K_ANT_FIXED_B:
2660b81a 4009 if (ah->caps.tx_chainmask >
f1dc5600
S		 4010 ATH9K_ANTENNA1_CHAINMASK) {
4011 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
4012 }
4013 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
4014 *antenna_cfgd = true;
4015 break;
4016 case ATH9K_ANT_VARIABLE:
4017 *tx_chainmask = tx_chainmask_cfg;
4018 *rx_chainmask = rx_chainmask_cfg;
4019 *antenna_cfgd = true;
4020 break;
4021 default:
4022 break;
4023 }
4024 } else {
1cf6873a 4025 ah->config.diversity_control = settings;
f078f209 4026 }
f078f209 4027
f1dc5600 4028 return true;
f078f209
LR		 4029}
4030
f1dc5600
S		 4031/*********************/
4032/* General Operation */
4033/*********************/
4034
cbe61d8a 4035u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 4036{
f1dc5600
S		 4037 u32 bits = REG_READ(ah, AR_RX_FILTER);
4038 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 4039
f1dc5600
S		 4040 if (phybits & AR_PHY_ERR_RADAR)
4041 bits |= ATH9K_RX_FILTER_PHYRADAR;
4042 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
4043 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 4044
f1dc5600 4045 return bits;
f078f209 4046}
7322fd19 4047EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 4048
cbe61d8a 4049void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 4050{
f1dc5600 4051 u32 phybits;
f078f209 4052
7ea310be
S		 4053 REG_WRITE(ah, AR_RX_FILTER, bits);
4054
f1dc5600
S		 4055 phybits = 0;
4056 if (bits & ATH9K_RX_FILTER_PHYRADAR)
4057 phybits |= AR_PHY_ERR_RADAR;
4058 if (bits & ATH9K_RX_FILTER_PHYERR)
4059 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
4060 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 4061
f1dc5600
S		 4062 if (phybits)
4063 REG_WRITE(ah, AR_RXCFG,
4064 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
4065 else
4066 REG_WRITE(ah, AR_RXCFG,
4067 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
4068}
7322fd19 4069EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 4070
cbe61d8a 4071bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 4072{
63a75b91
SB		 4073 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
4074 return false;
4075
4076 ath9k_hw_init_pll(ah, NULL);
4077 return true;
f1dc5600 4078}
7322fd19 4079EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 4080
cbe61d8a 4081bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 4082{
9ecdef4b 4083 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 4084 return false;
f078f209 4085
63a75b91
SB		 4086 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
4087 return false;
4088
4089 ath9k_hw_init_pll(ah, NULL);
4090 return true;
f078f209 4091}
7322fd19 4092EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 4093
8fbff4b8 4094void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 4095{
608b88cb 4096 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 4097 struct ath9k_channel *chan = ah->curchan;
5f8e077c 4098 struct ieee80211_channel *channel = chan->chan;
f078f209 4099
608b88cb 4100 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 4101
8fbff4b8 4102 ah->eep_ops->set_txpower(ah, chan,
608b88cb 4103 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 4104 channel->max_antenna_gain * 2,
4105 channel->max_power * 2,
4106 min((u32) MAX_RATE_POWER,
608b88cb 4107 (u32) regulatory->power_limit));
6f255425 4108}
7322fd19 4109EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 4110
cbe61d8a 4111void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 4112{
1510718d 4113 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
f078f209 4114}
7322fd19 4115EXPORT_SYMBOL(ath9k_hw_setmac);
f078f209 4116
cbe61d8a 4117void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 4118{
2660b81a 4119 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 4120}
7322fd19 4121EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 4122
cbe61d8a 4123void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 4124{
f1dc5600
S		 4125 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4126 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 4127}
7322fd19 4128EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 4129
f2b2143e 4130void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 4131{
1510718d
LR		 4132 struct ath_common *common = ath9k_hw_common(ah);
4133
4134 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
4135 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
4136 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 4137}
7322fd19 4138EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 4139
cbe61d8a 4140u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 4141{
f1dc5600 4142 u64 tsf;
f078f209 4143
f1dc5600
S		 4144 tsf = REG_READ(ah, AR_TSF_U32);
4145 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 4146
f1dc5600
S		 4147 return tsf;
4148}
7322fd19 4149EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 4150
cbe61d8a 4151void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 4152{
27abe060 4153 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 4154 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 4155}
7322fd19 4156EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 4157
cbe61d8a 4158void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 4159{
f9b604f6
GJ		 4160 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4161 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 4162 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4163 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 4164
f1dc5600
S		 4165 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4166}
7322fd19 4167EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 4168
54e4cec6 4169void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 4170{
f1dc5600 4171 if (setting)
2660b81a 4172 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 4173 else
2660b81a 4174 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 4175}
7322fd19 4176EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 4177
cbe61d8a 4178bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f1dc5600 4179{
f1dc5600 4180 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
c46917bb
LR		 4181 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4182 "bad slot time %u\n", us);
2660b81a 4183 ah->slottime = (u32) -1;
f1dc5600
S		 4184 return false;
4185 } else {
4186 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
2660b81a 4187 ah->slottime = us;
f1dc5600 4188 return true;
f078f209 4189 }
f1dc5600 4190}
7322fd19 4191EXPORT_SYMBOL(ath9k_hw_setslottime);
f1dc5600 4192
25c56eec 4193void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 4194{
25c56eec 4195 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 4196 u32 macmode;
4197
25c56eec 4198 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 4199 macmode = AR_2040_JOINED_RX_CLEAR;
4200 else
4201 macmode = 0;
f078f209 4202
f1dc5600 4203 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 4204}
ff155a45
VT		 4205
4206/* HW Generic timers configuration */
4207
4208static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4209{
4210 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4211 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4212 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4213 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4214 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4215 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4216 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4217 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4218 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4219 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4220 AR_NDP2_TIMER_MODE, 0x0002},
4221 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4222 AR_NDP2_TIMER_MODE, 0x0004},
4223 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4224 AR_NDP2_TIMER_MODE, 0x0008},
4225 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4226 AR_NDP2_TIMER_MODE, 0x0010},
4227 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4228 AR_NDP2_TIMER_MODE, 0x0020},
4229 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4230 AR_NDP2_TIMER_MODE, 0x0040},
4231 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4232 AR_NDP2_TIMER_MODE, 0x0080}
4233};
4234
4235/* HW generic timer primitives */
4236
4237/* compute and clear index of rightmost 1 */
4238static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4239{
4240 u32 b;
4241
4242 b = *mask;
4243 b &= (0-b);
4244 *mask &= ~b;
4245 b *= debruijn32;
4246 b >>= 27;
4247
4248 return timer_table->gen_timer_index[b];
4249}
4250
1773912b 4251u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 4252{
4253 return REG_READ(ah, AR_TSF_L32);
4254}
7322fd19 4255EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 4256
4257struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4258 void (*trigger)(void *),
4259 void (*overflow)(void *),
4260 void *arg,
4261 u8 timer_index)
4262{
4263 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4264 struct ath_gen_timer *timer;
4265
4266 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4267
4268 if (timer == NULL) {
c46917bb
LR		 4269 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
4270 "Failed to allocate memory"
4271 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 4272 return NULL;
4273 }
4274
4275 /* allocate a hardware generic timer slot */
4276 timer_table->timers[timer_index] = timer;
4277 timer->index = timer_index;
4278 timer->trigger = trigger;
4279 timer->overflow = overflow;
4280 timer->arg = arg;
4281
4282 return timer;
4283}
7322fd19 4284EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 4285
cd9bf689
LR		 4286void ath9k_hw_gen_timer_start(struct ath_hw *ah,
4287 struct ath_gen_timer *timer,
4288 u32 timer_next,
4289 u32 timer_period)
ff155a45
VT		 4290{
4291 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4292 u32 tsf;
4293
4294 BUG_ON(!timer_period);
4295
4296 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4297
4298 tsf = ath9k_hw_gettsf32(ah);
4299
c46917bb
LR		 4300 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
4301 "curent tsf %x period %x"
4302 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 4303
4304 /*
4305 * Pull timer_next forward if the current TSF already passed it
4306 * because of software latency
4307 */
4308 if (timer_next < tsf)
4309 timer_next = tsf + timer_period;
4310
4311 /*
4312 * Program generic timer registers
4313 */
4314 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4315 timer_next);
4316 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4317 timer_period);
4318 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4319 gen_tmr_configuration[timer->index].mode_mask);
4320
4321 /* Enable both trigger and thresh interrupt masks */
4322 REG_SET_BIT(ah, AR_IMR_S5,
4323 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4324 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 4325}
7322fd19 4326EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 4327
cd9bf689 4328void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 4329{
4330 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4331
4332 if ((timer->index < AR_FIRST_NDP_TIMER) ||
4333 (timer->index >= ATH_MAX_GEN_TIMER)) {
4334 return;
4335 }
4336
4337 /* Clear generic timer enable bits. */
4338 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4339 gen_tmr_configuration[timer->index].mode_mask);
4340
4341 /* Disable both trigger and thresh interrupt masks */
4342 REG_CLR_BIT(ah, AR_IMR_S5,
4343 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4344 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4345
4346 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 4347}
7322fd19 4348EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 4349
4350void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4351{
4352 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4353
4354 /* free the hardware generic timer slot */
4355 timer_table->timers[timer->index] = NULL;
4356 kfree(timer);
4357}
7322fd19 4358EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 4359
4360/*
4361 * Generic Timer Interrupts handling
4362 */
4363void ath_gen_timer_isr(struct ath_hw *ah)
4364{
4365 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4366 struct ath_gen_timer *timer;
c46917bb 4367 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 4368 u32 trigger_mask, thresh_mask, index;
4369
4370 /* get hardware generic timer interrupt status */
4371 trigger_mask = ah->intr_gen_timer_trigger;
4372 thresh_mask = ah->intr_gen_timer_thresh;
4373 trigger_mask &= timer_table->timer_mask.val;
4374 thresh_mask &= timer_table->timer_mask.val;
4375
4376 trigger_mask &= ~thresh_mask;
4377
4378 while (thresh_mask) {
4379 index = rightmost_index(timer_table, &thresh_mask);
4380 timer = timer_table->timers[index];
4381 BUG_ON(!timer);
c46917bb
LR		 4382 ath_print(common, ATH_DBG_HWTIMER,
4383 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 4384 timer->overflow(timer->arg);
4385 }
4386
4387 while (trigger_mask) {
4388 index = rightmost_index(timer_table, &trigger_mask);
4389 timer = timer_table->timers[index];
4390 BUG_ON(!timer);
c46917bb
LR		 4391 ath_print(common, ATH_DBG_HWTIMER,
4392 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 4393 timer->trigger(timer->arg);
4394 }
4395}
7322fd19 4396EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a
LR		 4397
4398static struct {
4399 u32 version;
4400 const char * name;
4401} ath_mac_bb_names[] = {
4402 /* Devices with external radios */
4403 { AR_SREV_VERSION_5416_PCI, "5416" },
4404 { AR_SREV_VERSION_5416_PCIE, "5418" },
4405 { AR_SREV_VERSION_9100, "9100" },
4406 { AR_SREV_VERSION_9160, "9160" },
4407 /* Single-chip solutions */
4408 { AR_SREV_VERSION_9280, "9280" },
4409 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 4410 { AR_SREV_VERSION_9287, "9287" },
4411 { AR_SREV_VERSION_9271, "9271" },
2da4f01a
LR		 4412};
4413
4414/* For devices with external radios */
4415static struct {
4416 u16 version;
4417 const char * name;
4418} ath_rf_names[] = {
4419 { 0, "5133" },
4420 { AR_RAD5133_SREV_MAJOR, "5133" },
4421 { AR_RAD5122_SREV_MAJOR, "5122" },
4422 { AR_RAD2133_SREV_MAJOR, "2133" },
4423 { AR_RAD2122_SREV_MAJOR, "2122" }
4424};
4425
4426/*
4427 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
4428 */
f934c4d9 4429static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 4430{
4431 int i;
4432
4433 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
4434 if (ath_mac_bb_names[i].version == mac_bb_version) {
4435 return ath_mac_bb_names[i].name;
4436 }
4437 }
4438
4439 return "????";
4440}
2da4f01a
LR		 4441
4442/*
4443 * Return the RF name. "????" is returned if the RF is unknown.
4444 * Used for devices with external radios.
4445 */
f934c4d9 4446static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 4447{
4448 int i;
4449
4450 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
4451 if (ath_rf_names[i].version == rf_version) {
4452 return ath_rf_names[i].name;
4453 }
4454 }
4455
4456 return "????";
4457}
f934c4d9
LR		 4458
4459void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
4460{
4461 int used;
4462
4463 /* chipsets >= AR9280 are single-chip */
4464 if (AR_SREV_9280_10_OR_LATER(ah)) {
4465 used = snprintf(hw_name, len,
4466 "Atheros AR%s Rev:%x",
4467 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
4468 ah->hw_version.macRev);
4469 }
4470 else {
4471 used = snprintf(hw_name, len,
4472 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
4473 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
4474 ah->hw_version.macRev,
4475 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
4476 AR_RADIO_SREV_MAJOR)),
4477 ah->hw_version.phyRev);
4478 }
4479
4480 hw_name[used] = '\0';
4481}
4482EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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