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ath9k_hw: move the cck channel 14 INI to the AR9002 hw code
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
af03abec 20#include "hw.h"
d70357d5 21#include "hw-ops.h"
cfe8cba9 22#include "rc.h"
af01c04e 23#include "ar9002_initvals.h"
f078f209 24
4febf7b8
LR		 25#define ATH9K_CLOCK_RATE_CCK 22
26#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 28
cbe61d8a 29static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 30
7322fd19
LR		 31MODULE_AUTHOR("Atheros Communications");
32MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
33MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
34MODULE_LICENSE("Dual BSD/GPL");
35
36static int __init ath9k_init(void)
37{
38 return 0;
39}
40module_init(ath9k_init);
41
42static void __exit ath9k_exit(void)
43{
44 return;
45}
46module_exit(ath9k_exit);
47
d70357d5
LR		 48/* Private hardware callbacks */
49
50static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
51{
52 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
53}
54
55static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
56{
57 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
58}
59
60static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
61{
62 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
63
64 return priv_ops->macversion_supported(ah->hw_version.macVersion);
65}
66
64773964
LR		 67static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
68 struct ath9k_channel *chan)
69{
70 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
71}
72
f1dc5600
S		 73/********************/
74/* Helper Functions */
75/********************/
f078f209 76
cbe61d8a 77static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 78{
b002a4a9 79 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 80
2660b81a 81 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 82 return usecs *ATH9K_CLOCK_RATE_CCK;
83 if (conf->channel->band == IEEE80211_BAND_2GHZ)
84 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
85 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 86}
87
cbe61d8a 88static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 89{
b002a4a9 90 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 91
4febf7b8 92 if (conf_is_ht40(conf))
f1dc5600
S		 93 return ath9k_hw_mac_clks(ah, usecs) * 2;
94 else
95 return ath9k_hw_mac_clks(ah, usecs);
96}
f078f209 97
0caa7b14 98bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 99{
100 int i;
101
0caa7b14
S		 102 BUG_ON(timeout < AH_TIME_QUANTUM);
103
104 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 105 if ((REG_READ(ah, reg) & mask) == val)
106 return true;
107
108 udelay(AH_TIME_QUANTUM);
109 }
04bd4638 110
c46917bb
LR		 111 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
112 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
113 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 114
f1dc5600 115 return false;
f078f209 116}
7322fd19 117EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 118
119u32 ath9k_hw_reverse_bits(u32 val, u32 n)
120{
121 u32 retval;
122 int i;
123
124 for (i = 0, retval = 0; i < n; i++) {
125 retval = (retval << 1) | (val & 1);
126 val >>= 1;
127 }
128 return retval;
129}
130
cbe61d8a 131bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 132 u16 flags, u16 *low,
133 u16 *high)
f078f209 134{
2660b81a 135 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 136
f1dc5600
S		 137 if (flags & CHANNEL_5GHZ) {
138 *low = pCap->low_5ghz_chan;
139 *high = pCap->high_5ghz_chan;
140 return true;
f078f209 141 }
f1dc5600
S		 142 if ((flags & CHANNEL_2GHZ)) {
143 *low = pCap->low_2ghz_chan;
144 *high = pCap->high_2ghz_chan;
145 return true;
146 }
147 return false;
f078f209
LR		 148}
149
cbe61d8a 150u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 151 u8 phy, int kbps,
f1dc5600
S		 152 u32 frameLen, u16 rateix,
153 bool shortPreamble)
f078f209 154{
f1dc5600 155 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 156
f1dc5600
S		 157 if (kbps == 0)
158 return 0;
f078f209 159
545750d3 160 switch (phy) {
46d14a58 161 case WLAN_RC_PHY_CCK:
f1dc5600 162 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 163 if (shortPreamble)
f1dc5600
S		 164 phyTime >>= 1;
165 numBits = frameLen << 3;
166 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
167 break;
46d14a58 168 case WLAN_RC_PHY_OFDM:
2660b81a 169 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 170 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
171 numBits = OFDM_PLCP_BITS + (frameLen << 3);
172 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
173 txTime = OFDM_SIFS_TIME_QUARTER
174 + OFDM_PREAMBLE_TIME_QUARTER
175 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 176 } else if (ah->curchan &&
177 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 178 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
179 numBits = OFDM_PLCP_BITS + (frameLen << 3);
180 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
181 txTime = OFDM_SIFS_TIME_HALF +
182 OFDM_PREAMBLE_TIME_HALF
183 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
184 } else {
185 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
186 numBits = OFDM_PLCP_BITS + (frameLen << 3);
187 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
188 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
189 + (numSymbols * OFDM_SYMBOL_TIME);
190 }
191 break;
192 default:
c46917bb 193 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 194 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 195 txTime = 0;
196 break;
197 }
f078f209 198
f1dc5600
S		 199 return txTime;
200}
7322fd19 201EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 202
cbe61d8a 203void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 204 struct ath9k_channel *chan,
205 struct chan_centers *centers)
f078f209 206{
f1dc5600 207 int8_t extoff;
f078f209 208
f1dc5600
S		 209 if (!IS_CHAN_HT40(chan)) {
210 centers->ctl_center = centers->ext_center =
211 centers->synth_center = chan->channel;
212 return;
f078f209 213 }
f078f209 214
f1dc5600
S		 215 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
216 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
217 centers->synth_center =
218 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
219 extoff = 1;
220 } else {
221 centers->synth_center =
222 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
223 extoff = -1;
224 }
f078f209 225
f1dc5600
S		 226 centers->ctl_center =
227 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 228 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 229 centers->ext_center =
6420014c 230 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 231}
232
f1dc5600
S		 233/******************/
234/* Chip Revisions */
235/******************/
236
cbe61d8a 237static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 238{
f1dc5600 239 u32 val;
f078f209 240
f1dc5600 241 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 242
f1dc5600
S		 243 if (val == 0xFF) {
244 val = REG_READ(ah, AR_SREV);
d535a42a
S		 245 ah->hw_version.macVersion =
246 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
247 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 248 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 249 } else {
250 if (!AR_SREV_9100(ah))
d535a42a 251 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 252
d535a42a 253 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 254
d535a42a 255 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 256 ah->is_pciexpress = true;
f1dc5600 257 }
f078f209
LR		 258}
259
cbe61d8a 260static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 261{
f1dc5600
S		 262 u32 val;
263 int i;
f078f209 264
f1dc5600 265 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 266
f1dc5600
S		 267 for (i = 0; i < 8; i++)
268 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
269 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
270 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 271
f1dc5600 272 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 273}
274
f1dc5600
S		 275/************************************/
276/* HW Attach, Detach, Init Routines */
277/************************************/
278
cbe61d8a 279static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 280{
feed029c 281 if (AR_SREV_9100(ah))
f1dc5600 282 return;
f078f209 283
f1dc5600
S		 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 293
f1dc5600 294 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 295}
296
1f3f0618 297/* This should work for all families including legacy */
cbe61d8a 298static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 299{
c46917bb 300 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 301 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600
S		 302 u32 regHold[2];
303 u32 patternData[4] = { 0x55555555,
304 0xaaaaaaaa,
305 0x66666666,
306 0x99999999 };
1f3f0618 307 int i, j, loop_max;
f078f209 308
1f3f0618
SB		 309 if (!AR_SREV_9300_20_OR_LATER(ah)) {
310 loop_max = 2;
311 regAddr[1] = AR_PHY_BASE + (8 << 2);
312 } else
313 loop_max = 1;
314
315 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 316 u32 addr = regAddr[i];
317 u32 wrData, rdData;
f078f209 318
f1dc5600
S		 319 regHold[i] = REG_READ(ah, addr);
320 for (j = 0; j < 0x100; j++) {
321 wrData = (j << 16) | j;
322 REG_WRITE(ah, addr, wrData);
323 rdData = REG_READ(ah, addr);
324 if (rdData != wrData) {
c46917bb
LR		 325 ath_print(common, ATH_DBG_FATAL,
326 "address test failed "
327 "addr: 0x%08x - wr:0x%08x != "
328 "rd:0x%08x\n",
329 addr, wrData, rdData);
f1dc5600
S		 330 return false;
331 }
332 }
333 for (j = 0; j < 4; j++) {
334 wrData = patternData[j];
335 REG_WRITE(ah, addr, wrData);
336 rdData = REG_READ(ah, addr);
337 if (wrData != rdData) {
c46917bb
LR		 338 ath_print(common, ATH_DBG_FATAL,
339 "address test failed "
340 "addr: 0x%08x - wr:0x%08x != "
341 "rd:0x%08x\n",
342 addr, wrData, rdData);
f1dc5600
S		 343 return false;
344 }
f078f209 345 }
f1dc5600 346 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 347 }
f1dc5600 348 udelay(100);
cbe61d8a 349
f078f209
LR		 350 return true;
351}
352
b8b0f377 353static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 354{
355 int i;
f078f209 356
2660b81a
S		 357 ah->config.dma_beacon_response_time = 2;
358 ah->config.sw_beacon_response_time = 10;
359 ah->config.additional_swba_backoff = 0;
360 ah->config.ack_6mb = 0x0;
361 ah->config.cwm_ignore_extcca = 0;
362 ah->config.pcie_powersave_enable = 0;
2660b81a 363 ah->config.pcie_clock_req = 0;
2660b81a
S		 364 ah->config.pcie_waen = 0;
365 ah->config.analog_shiftreg = 1;
2660b81a
S		 366 ah->config.ofdm_trig_low = 200;
367 ah->config.ofdm_trig_high = 500;
368 ah->config.cck_trig_high = 200;
369 ah->config.cck_trig_low = 100;
31a0bd3c
LR		 370
371 /*
372 * For now ANI is disabled for AR9003, it is still
373 * being tested.
374 */
375 if (!AR_SREV_9300_20_OR_LATER(ah))
376 ah->config.enable_ani = 1;
f078f209 377
f1dc5600 378 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 379 ah->config.spurchans[i][0] = AR_NO_SPUR;
380 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 381 }
382
5ffaf8a3
LR		 383 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
384 ah->config.ht_enable = 1;
385 else
386 ah->config.ht_enable = 0;
387
0ce024cb 388 ah->config.rx_intr_mitigation = true;
6158425b
LR		 389
390 /*
391 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
392 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
393 * This means we use it for all AR5416 devices, and the few
394 * minor PCI AR9280 devices out there.
395 *
396 * Serialization is required because these devices do not handle
397 * well the case of two concurrent reads/writes due to the latency
398 * involved. During one read/write another read/write can be issued
399 * on another CPU while the previous read/write may still be working
400 * on our hardware, if we hit this case the hardware poops in a loop.
401 * We prevent this by serializing reads and writes.
402 *
403 * This issue is not present on PCI-Express devices or pre-AR5416
404 * devices (legacy, 802.11abg).
405 */
406 if (num_possible_cpus() > 1)
2d6a5e95 407 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 408}
409
50aca25b 410static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 411{
608b88cb
LR		 412 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
413
414 regulatory->country_code = CTRY_DEFAULT;
415 regulatory->power_limit = MAX_RATE_POWER;
416 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
417
d535a42a 418 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 419 ah->hw_version.subvendorid = 0;
f078f209
LR		 420
421 ah->ah_flags = 0;
f078f209
LR		 422 if (!AR_SREV_9100(ah))
423 ah->ah_flags = AH_USE_EEPROM;
424
2660b81a 425 ah->atim_window = 0;
2660b81a
S		 426 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
427 ah->beacon_interval = 100;
428 ah->enable_32kHz_clock = DONT_USE_32KHZ;
429 ah->slottime = (u32) -1;
2660b81a 430 ah->globaltxtimeout = (u32) -1;
cbdec975 431 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 432}
433
cbe61d8a 434static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 435{
f1dc5600
S		 436 u32 val;
437
438 REG_WRITE(ah, AR_PHY(0), 0x00000007);
439
440 val = ath9k_hw_get_radiorev(ah);
441 switch (val & AR_RADIO_SREV_MAJOR) {
442 case 0:
443 val = AR_RAD5133_SREV_MAJOR;
444 break;
445 case AR_RAD5133_SREV_MAJOR:
446 case AR_RAD5122_SREV_MAJOR:
447 case AR_RAD2133_SREV_MAJOR:
448 case AR_RAD2122_SREV_MAJOR:
449 break;
f078f209 450 default:
c46917bb
LR		 451 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
452 "Radio Chip Rev 0x%02X not supported\n",
453 val & AR_RADIO_SREV_MAJOR);
f1dc5600 454 return -EOPNOTSUPP;
f078f209 455 }
f078f209 456
d535a42a 457 ah->hw_version.analog5GhzRev = val;
f078f209 458
f1dc5600 459 return 0;
f078f209
LR		 460}
461
cbe61d8a 462static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 463{
1510718d 464 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 465 u32 sum;
466 int i;
467 u16 eeval;
f078f209
LR		 468
469 sum = 0;
470 for (i = 0; i < 3; i++) {
f74df6fb 471 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 472 sum += eeval;
1510718d
LR		 473 common->macaddr[2 * i] = eeval >> 8;
474 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 475 }
d8baa939 476 if (sum == 0 || sum == 0xffff * 3)
f078f209 477 return -EADDRNOTAVAIL;
f078f209
LR		 478
479 return 0;
480}
481
cbe61d8a 482static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 483{
484 u32 rxgain_type;
9f804202 485
f74df6fb
S		 486 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
487 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 488
489 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 490 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 491 ar9280Modes_backoff_13db_rxgain_9280_2,
492 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
493 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 494 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 495 ar9280Modes_backoff_23db_rxgain_9280_2,
496 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
497 else
2660b81a 498 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 499 ar9280Modes_original_rxgain_9280_2,
500 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 501 } else {
2660b81a 502 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 503 ar9280Modes_original_rxgain_9280_2,
504 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 505 }
9f804202
SB		 506}
507
cbe61d8a 508static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 509{
510 u32 txgain_type;
9f804202 511
f74df6fb
S		 512 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
513 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 514
515 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 516 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 517 ar9280Modes_high_power_tx_gain_9280_2,
518 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
519 else
2660b81a 520 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 521 ar9280Modes_original_tx_gain_9280_2,
522 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 523 } else {
2660b81a 524 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 525 ar9280Modes_original_tx_gain_9280_2,
526 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 527 }
9f804202
SB		 528}
529
f637cfd6 530static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 531{
f1dc5600 532 int ecode;
f078f209 533
527d485f
S		 534 if (!AR_SREV_9271(ah)) {
535 if (!ath9k_hw_chip_test(ah))
536 return -ENODEV;
537 }
f078f209 538
f1dc5600
S		 539 ecode = ath9k_hw_rf_claim(ah);
540 if (ecode != 0)
f078f209 541 return ecode;
f078f209 542
f637cfd6 543 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 544 if (ecode != 0)
545 return ecode;
7d01b221 546
c46917bb
LR		 547 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
548 "Eeprom VER: %d, REV: %d\n",
549 ah->eep_ops->get_eeprom_ver(ah),
550 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 551
8fe65368
LR		 552 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
553 if (ecode) {
554 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
555 "Failed allocating banks for "
556 "external radio\n");
557 return ecode;
574d6b12 558 }
f078f209 559
f1dc5600
S		 560 if (!AR_SREV_9100(ah)) {
561 ath9k_hw_ani_setup(ah);
f637cfd6 562 ath9k_hw_ani_init(ah);
f078f209
LR		 563 }
564
f078f209
LR		 565 return 0;
566}
567
aa4058ae
LR		 568static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
569{
b37fa870 570 if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec
VN		 571 INIT_INI_ARRAY(&ah->iniModesRxGain,
572 ar9287Modes_rx_gain_9287_1_1,
573 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
574 else if (AR_SREV_9287_10(ah))
575 INIT_INI_ARRAY(&ah->iniModesRxGain,
576 ar9287Modes_rx_gain_9287_1_0,
577 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
578 else if (AR_SREV_9280_20(ah))
579 ath9k_hw_init_rxgain_ini(ah);
580
b37fa870 581 if (AR_SREV_9287_11_OR_LATER(ah)) {
ac88b6ec
VN		 582 INIT_INI_ARRAY(&ah->iniModesTxGain,
583 ar9287Modes_tx_gain_9287_1_1,
584 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
585 } else if (AR_SREV_9287_10(ah)) {
586 INIT_INI_ARRAY(&ah->iniModesTxGain,
587 ar9287Modes_tx_gain_9287_1_0,
588 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
589 } else if (AR_SREV_9280_20(ah)) {
590 ath9k_hw_init_txgain_ini(ah);
591 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4e845168
SB		 592 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
593
594 /* txgain table */
595 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
53bc7aa0
VN		 596 if (AR_SREV_9285E_20(ah)) {
597 INIT_INI_ARRAY(&ah->iniModesTxGain,
598 ar9285Modes_XE2_0_high_power,
599 ARRAY_SIZE(
600 ar9285Modes_XE2_0_high_power), 6);
601 } else {
602 INIT_INI_ARRAY(&ah->iniModesTxGain,
603 ar9285Modes_high_power_tx_gain_9285_1_2,
604 ARRAY_SIZE(
605 ar9285Modes_high_power_tx_gain_9285_1_2), 6);
606 }
4e845168 607 } else {
53bc7aa0
VN		 608 if (AR_SREV_9285E_20(ah)) {
609 INIT_INI_ARRAY(&ah->iniModesTxGain,
610 ar9285Modes_XE2_0_normal_power,
611 ARRAY_SIZE(
612 ar9285Modes_XE2_0_normal_power), 6);
613 } else {
614 INIT_INI_ARRAY(&ah->iniModesTxGain,
615 ar9285Modes_original_tx_gain_9285_1_2,
616 ARRAY_SIZE(
617 ar9285Modes_original_tx_gain_9285_1_2), 6);
618 }
4e845168 619 }
4e845168 620 }
aa4058ae 621}
4e845168 622
aa8bc9ef 623static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
aa4058ae 624{
2eb46d9b
PR		 625 struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
626 struct ath_common *common = ath9k_hw_common(ah);
f078f209 627
2eb46d9b 628 ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
939ad86d 629 !AR_SREV_9285(ah) && !AR_SREV_9271(ah) &&
2eb46d9b
PR		 630 ((pBase->version & 0xff) > 0x0a) &&
631 (pBase->pwdclkind == 0);
f078f209 632
2eb46d9b
PR		 633 if (ah->need_an_top2_fixup)
634 ath_print(common, ATH_DBG_EEPROM,
635 "needs fixup for AR_AN_TOP2 register\n");
aa4058ae
LR		 636}
637
8525f280
LR		 638static void ath9k_hw_attach_ops(struct ath_hw *ah)
639{
640 if (AR_SREV_9300_20_OR_LATER(ah))
641 ar9003_hw_attach_ops(ah);
642 else
643 ar9002_hw_attach_ops(ah);
644}
645
d70357d5
LR		 646/* Called for all hardware families */
647static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 648{
c46917bb 649 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 650 int r = 0;
aa4058ae 651
bab1f62e
LR		 652 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
653 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
aa4058ae
LR		 654
655 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 656 ath_print(common, ATH_DBG_FATAL,
657 "Couldn't reset chip\n");
95fafca2 658 return -EIO;
aa4058ae
LR		 659 }
660
bab1f62e
LR		 661 ath9k_hw_init_defaults(ah);
662 ath9k_hw_init_config(ah);
663
8525f280 664 ath9k_hw_attach_ops(ah);
d70357d5 665
9ecdef4b 666 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 667 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 668 return -EIO;
aa4058ae
LR		 669 }
670
671 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
672 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
673 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
674 ah->config.serialize_regmode =
675 SER_REG_MODE_ON;
676 } else {
677 ah->config.serialize_regmode =
678 SER_REG_MODE_OFF;
679 }
680 }
681
c46917bb 682 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 683 ah->config.serialize_regmode);
684
f4709fdf
LR		 685 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
686 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
687 else
688 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
689
d70357d5 690 if (!ath9k_hw_macversion_supported(ah)) {
c46917bb
LR		 691 ath_print(common, ATH_DBG_FATAL,
692 "Mac Chip Rev 0x%02x.%x is not supported by "
693 "this driver\n", ah->hw_version.macVersion,
694 ah->hw_version.macRev);
95fafca2 695 return -EOPNOTSUPP;
aa4058ae
LR		 696 }
697
0df13da4 698 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
d7e7d229
LR		 699 ah->is_pciexpress = false;
700
aa4058ae 701 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 702 ath9k_hw_init_cal_settings(ah);
703
704 ah->ani_function = ATH9K_ANI_ALL;
31a0bd3c 705 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae
LR		 706 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
707
708 ath9k_hw_init_mode_regs(ah);
709
710 if (ah->is_pciexpress)
93b1b37f 711 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 712 else
713 ath9k_hw_disablepcie(ah);
714
d8f492b7
LR		 715 if (!AR_SREV_9300_20_OR_LATER(ah))
716 ar9002_hw_cck_chan14_spread(ah);
193cd458 717
f637cfd6 718 r = ath9k_hw_post_init(ah);
aa4058ae 719 if (r)
95fafca2 720 return r;
aa4058ae
LR		 721
722 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 723 r = ath9k_hw_fill_cap_info(ah);
724 if (r)
725 return r;
726
aa8bc9ef 727 ath9k_hw_init_eeprom_fix(ah);
f6688cd8 728
4f3acf81
LR		 729 r = ath9k_hw_init_macaddr(ah);
730 if (r) {
c46917bb
LR		 731 ath_print(common, ATH_DBG_FATAL,
732 "Failed to initialize MAC address\n");
95fafca2 733 return r;
f078f209
LR		 734 }
735
d7e7d229 736 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 737 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 738 else
2660b81a 739 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 740
641d9921
FF		 741 if (AR_SREV_9300_20_OR_LATER(ah))
742 ar9003_hw_set_nf_limits(ah);
743
f1dc5600 744 ath9k_init_nfcal_hist_buffer(ah);
f078f209 745
211f5859
LR		 746 common->state = ATH_HW_INITIALIZED;
747
4f3acf81 748 return 0;
f078f209
LR		 749}
750
d70357d5
LR		 751int ath9k_hw_init(struct ath_hw *ah)
752{
753 int ret;
754 struct ath_common *common = ath9k_hw_common(ah);
755
756 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
757 switch (ah->hw_version.devid) {
758 case AR5416_DEVID_PCI:
759 case AR5416_DEVID_PCIE:
760 case AR5416_AR9100_DEVID:
761 case AR9160_DEVID_PCI:
762 case AR9280_DEVID_PCI:
763 case AR9280_DEVID_PCIE:
764 case AR9285_DEVID_PCIE:
db3cc53a
SB		 765 case AR9287_DEVID_PCI:
766 case AR9287_DEVID_PCIE:
d70357d5 767 case AR2427_DEVID_PCIE:
db3cc53a 768 case AR9300_DEVID_PCIE:
d70357d5
LR		 769 break;
770 default:
771 if (common->bus_ops->ath_bus_type == ATH_USB)
772 break;
773 ath_print(common, ATH_DBG_FATAL,
774 "Hardware device ID 0x%04x not supported\n",
775 ah->hw_version.devid);
776 return -EOPNOTSUPP;
777 }
778
779 ret = __ath9k_hw_init(ah);
780 if (ret) {
781 ath_print(common, ATH_DBG_FATAL,
782 "Unable to initialize hardware; "
783 "initialization status: %d\n", ret);
784 return ret;
785 }
786
787 return 0;
788}
789EXPORT_SYMBOL(ath9k_hw_init);
790
cbe61d8a 791static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 792{
f1dc5600
S		 793 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
794 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 795
f1dc5600
S		 796 REG_WRITE(ah, AR_QOS_NO_ACK,
797 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
798 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
799 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
800
801 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
802 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
803 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
804 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
805 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 806}
807
cbe61d8a 808static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 809 struct ath9k_channel *chan)
f078f209 810{
64773964 811 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 812
d03a66c1 813 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 814
c75724d1
LR		 815 /* Switch the core clock for ar9271 to 117Mhz */
816 if (AR_SREV_9271(ah)) {
25e2ab17
S		 817 udelay(500);
818 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 819 }
820
f1dc5600
S		 821 udelay(RTC_PLL_SETTLE_DELAY);
822
823 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 824}
825
cbe61d8a 826static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 827 enum nl80211_iftype opmode)
f078f209 828{
152d530d 829 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 830 AR_IMR_TXURN |
831 AR_IMR_RXERR |
832 AR_IMR_RXORN |
833 AR_IMR_BCNMISC;
f078f209 834
0ce024cb 835 if (ah->config.rx_intr_mitigation)
152d530d 836 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 837 else
152d530d 838 imr_reg |= AR_IMR_RXOK;
f078f209 839
152d530d 840 imr_reg |= AR_IMR_TXOK;
f078f209 841
d97809db 842 if (opmode == NL80211_IFTYPE_AP)
152d530d 843 imr_reg |= AR_IMR_MIB;
f078f209 844
152d530d 845 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 846 ah->imrs2_reg |= AR_IMR_S2_GTT;
847 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 848
f1dc5600
S		 849 if (!AR_SREV_9100(ah)) {
850 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
851 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
852 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
853 }
f078f209
LR		 854}
855
0005baf4 856static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 857{
0005baf4
FF		 858 u32 val = ath9k_hw_mac_to_clks(ah, us);
859 val = min(val, (u32) 0xFFFF);
860 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 861}
862
0005baf4 863static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 864{
0005baf4
FF		 865 u32 val = ath9k_hw_mac_to_clks(ah, us);
866 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
867 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
868}
869
870static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
871{
872 u32 val = ath9k_hw_mac_to_clks(ah, us);
873 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
874 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 875}
f1dc5600 876
cbe61d8a 877static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 878{
f078f209 879 if (tu > 0xFFFF) {
c46917bb
LR		 880 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
881 "bad global tx timeout %u\n", tu);
2660b81a 882 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 883 return false;
884 } else {
885 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 886 ah->globaltxtimeout = tu;
f078f209
LR		 887 return true;
888 }
889}
890
0005baf4 891void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 892{
0005baf4
FF		 893 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
894 int acktimeout;
e239d859 895 int slottime;
0005baf4
FF		 896 int sifstime;
897
c46917bb
LR		 898 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
899 ah->misc_mode);
f078f209 900
2660b81a 901 if (ah->misc_mode != 0)
f1dc5600 902 REG_WRITE(ah, AR_PCU_MISC,
2660b81a 903 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
0005baf4
FF		 904
905 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
906 sifstime = 16;
907 else
908 sifstime = 10;
909
e239d859
FF		 910 /* As defined by IEEE 802.11-2007 17.3.8.6 */
911 slottime = ah->slottime + 3 * ah->coverage_class;
912 acktimeout = slottime + sifstime;
42c4568a
FF		 913
914 /*
915 * Workaround for early ACK timeouts, add an offset to match the
916 * initval's 64us ack timeout value.
917 * This was initially only meant to work around an issue with delayed
918 * BA frames in some implementations, but it has been found to fix ACK
919 * timeout issues in other cases as well.
920 */
921 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
922 acktimeout += 64 - sifstime - ah->slottime;
923
e239d859 924 ath9k_hw_setslottime(ah, slottime);
0005baf4
FF		 925 ath9k_hw_set_ack_timeout(ah, acktimeout);
926 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 927 if (ah->globaltxtimeout != (u32) -1)
928 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 929}
0005baf4 930EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 931
285f2dda 932void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 933{
211f5859
LR		 934 struct ath_common *common = ath9k_hw_common(ah);
935
736b3a27 936 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 937 goto free_hw;
938
f1dc5600 939 if (!AR_SREV_9100(ah))
e70c0cfd 940 ath9k_hw_ani_disable(ah);
f1dc5600 941
9ecdef4b 942 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 943
944free_hw:
8fe65368 945 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 946}
285f2dda 947EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 948
f1dc5600
S		 949/*******/
950/* INI */
951/*******/
952
8fe65368 953u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 954{
955 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
956
957 if (IS_CHAN_B(chan))
958 ctl |= CTL_11B;
959 else if (IS_CHAN_G(chan))
960 ctl |= CTL_11G;
961 else
962 ctl |= CTL_11A;
963
964 return ctl;
965}
966
f1dc5600
S		 967/****************************************/
968/* Reset and Channel Switching Routines */
969/****************************************/
970
cbe61d8a 971static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 972{
973 u32 regval;
974
d7e7d229
LR		 975 /*
976 * set AHB_MODE not to do cacheline prefetches
977 */
f1dc5600
S		 978 regval = REG_READ(ah, AR_AHB_MODE);
979 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
980
d7e7d229
LR		 981 /*
982 * let mac dma reads be in 128 byte chunks
983 */
f1dc5600
S		 984 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
985 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
986
d7e7d229
LR		 987 /*
988 * Restore TX Trigger Level to its pre-reset value.
989 * The initial value depends on whether aggregation is enabled, and is
990 * adjusted whenever underruns are detected.
991 */
2660b81a 992 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 993
d7e7d229
LR		 994 /*
995 * let mac dma writes be in 128 byte chunks
996 */
f1dc5600
S		 997 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
998 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
999
d7e7d229
LR		 1000 /*
1001 * Setup receive FIFO threshold to hold off TX activities
1002 */
f1dc5600
S		 1003 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1004
d7e7d229
LR		 1005 /*
1006 * reduce the number of usable entries in PCU TXBUF to avoid
1007 * wrap around issues.
1008 */
f1dc5600 1009 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1010 /* For AR9285 the number of Fifos are reduced to half.
1011 * So set the usable tx buf size also to half to
1012 * avoid data/delimiter underruns
1013 */
f1dc5600
S		 1014 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1015 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1016 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1017 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1018 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1019 }
1020}
1021
cbe61d8a 1022static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1023{
1024 u32 val;
1025
1026 val = REG_READ(ah, AR_STA_ID1);
1027 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1028 switch (opmode) {
d97809db 1029 case NL80211_IFTYPE_AP:
f1dc5600
S		 1030 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1031 | AR_STA_ID1_KSRCH_MODE);
1032 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1033 break;
d97809db 1034 case NL80211_IFTYPE_ADHOC:
9cb5412b 1035 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 1036 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1037 | AR_STA_ID1_KSRCH_MODE);
1038 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1039 break;
d97809db
CM		 1040 case NL80211_IFTYPE_STATION:
1041 case NL80211_IFTYPE_MONITOR:
f1dc5600 1042 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1043 break;
f1dc5600
S		 1044 }
1045}
1046
8fe65368
LR		 1047void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1048 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1049{
1050 u32 coef_exp, coef_man;
1051
1052 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1053 if ((coef_scaled >> coef_exp) & 0x1)
1054 break;
1055
1056 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1057
1058 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1059
1060 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1061 *coef_exponent = coef_exp - 16;
1062}
1063
cbe61d8a 1064static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1065{
1066 u32 rst_flags;
1067 u32 tmpReg;
1068
70768496
S		 1069 if (AR_SREV_9100(ah)) {
1070 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1071 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1072 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1073 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1074 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1075 }
1076
f1dc5600
S		 1077 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1078 AR_RTC_FORCE_WAKE_ON_INT);
1079
1080 if (AR_SREV_9100(ah)) {
1081 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1082 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1083 } else {
1084 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1085 if (tmpReg &
1086 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1087 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1088 u32 val;
f1dc5600 1089 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1090
1091 val = AR_RC_HOSTIF;
1092 if (!AR_SREV_9300_20_OR_LATER(ah))
1093 val |= AR_RC_AHB;
1094 REG_WRITE(ah, AR_RC, val);
1095
1096 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1097 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1098
1099 rst_flags = AR_RTC_RC_MAC_WARM;
1100 if (type == ATH9K_RESET_COLD)
1101 rst_flags |= AR_RTC_RC_MAC_COLD;
1102 }
1103
d03a66c1 1104 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1105 udelay(50);
1106
d03a66c1 1107 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1108 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1109 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1110 "RTC stuck in MAC reset\n");
f1dc5600
S		 1111 return false;
1112 }
1113
1114 if (!AR_SREV_9100(ah))
1115 REG_WRITE(ah, AR_RC, 0);
1116
f1dc5600
S		 1117 if (AR_SREV_9100(ah))
1118 udelay(50);
1119
1120 return true;
1121}
1122
cbe61d8a 1123static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1124{
1125 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1126 AR_RTC_FORCE_WAKE_ON_INT);
1127
42d5bc3f 1128 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1129 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1130
d03a66c1 1131 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1132
84e2169b
SB		 1133 if (!AR_SREV_9300_20_OR_LATER(ah))
1134 udelay(2);
1135
1136 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1137 REG_WRITE(ah, AR_RC, 0);
1138
d03a66c1 1139 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1140
1141 if (!ath9k_hw_wait(ah,
1142 AR_RTC_STATUS,
1143 AR_RTC_STATUS_M,
0caa7b14
S		 1144 AR_RTC_STATUS_ON,
1145 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1146 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1147 "RTC not waking up\n");
f1dc5600 1148 return false;
f078f209
LR		 1149 }
1150
f1dc5600
S		 1151 ath9k_hw_read_revisions(ah);
1152
1153 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1154}
1155
cbe61d8a 1156static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1157{
1158 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1159 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1160
1161 switch (type) {
1162 case ATH9K_RESET_POWER_ON:
1163 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1164 case ATH9K_RESET_WARM:
1165 case ATH9K_RESET_COLD:
1166 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1167 default:
1168 return false;
1169 }
f078f209
LR		 1170}
1171
cbe61d8a 1172static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1173 struct ath9k_channel *chan)
f078f209 1174{
42abfbee 1175 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1176 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1177 return false;
1178 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1179 return false;
f078f209 1180
9ecdef4b 1181 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1182 return false;
f078f209 1183
2660b81a 1184 ah->chip_fullsleep = false;
f1dc5600 1185 ath9k_hw_init_pll(ah, chan);
f1dc5600 1186 ath9k_hw_set_rfmode(ah, chan);
f078f209 1187
f1dc5600 1188 return true;
f078f209
LR		 1189}
1190
cbe61d8a 1191static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1192 struct ath9k_channel *chan)
f078f209 1193{
608b88cb 1194 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1195 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1196 struct ieee80211_channel *channel = chan->chan;
8fe65368 1197 u32 qnum;
0a3b7bac 1198 int r;
f078f209
LR		 1199
1200 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1201 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1202 ath_print(common, ATH_DBG_QUEUE,
1203 "Transmit frames pending on "
1204 "queue %d\n", qnum);
f078f209
LR		 1205 return false;
1206 }
1207 }
1208
8fe65368 1209 if (!ath9k_hw_rfbus_req(ah)) {
c46917bb
LR		 1210 ath_print(common, ATH_DBG_FATAL,
1211 "Could not kill baseband RX\n");
f078f209
LR		 1212 return false;
1213 }
1214
8fe65368 1215 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1216
8fe65368 1217 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1218 if (r) {
1219 ath_print(common, ATH_DBG_FATAL,
1220 "Failed to set channel\n");
1221 return false;
f078f209
LR		 1222 }
1223
8fbff4b8 1224 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1225 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1226 channel->max_antenna_gain * 2,
1227 channel->max_power * 2,
1228 min((u32) MAX_RATE_POWER,
608b88cb 1229 (u32) regulatory->power_limit));
f078f209 1230
8fe65368 1231 ath9k_hw_rfbus_done(ah);
f078f209 1232
f1dc5600
S		 1233 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1234 ath9k_hw_set_delta_slope(ah, chan);
1235
8fe65368 1236 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600
S		 1237
1238 if (!chan->oneTimeCalsDone)
1239 chan->oneTimeCalsDone = true;
1240
1241 return true;
1242}
1243
cbe61d8a 1244int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 1245 bool bChannelChange)
f078f209 1246{
1510718d 1247 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1248 u32 saveLedState;
2660b81a 1249 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1250 u32 saveDefAntenna;
1251 u32 macStaId1;
46fe782c 1252 u64 tsf = 0;
8fe65368 1253 int i, r;
f078f209 1254
43c27613
LR		 1255 ah->txchainmask = common->tx_chainmask;
1256 ah->rxchainmask = common->rx_chainmask;
f078f209 1257
9ecdef4b 1258 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1259 return -EIO;
f078f209 1260
9ebef799 1261 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1262 ath9k_hw_getnf(ah, curchan);
1263
1264 if (bChannelChange &&
2660b81a
S		 1265 (ah->chip_fullsleep != true) &&
1266 (ah->curchan != NULL) &&
1267 (chan->channel != ah->curchan->channel) &&
f078f209 1268 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1269 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
0a475cc6
VT		 1270 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1271 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
f078f209 1272
25c56eec 1273 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1274 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 1275 ath9k_hw_start_nfcal(ah);
ae8d2858 1276 return 0;
f078f209
LR		 1277 }
1278 }
1279
1280 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1281 if (saveDefAntenna == 0)
1282 saveDefAntenna = 1;
1283
1284 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1285
46fe782c
S		 1286 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1287 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1288 tsf = ath9k_hw_gettsf64(ah);
1289
f078f209
LR		 1290 saveLedState = REG_READ(ah, AR_CFG_LED) &
1291 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1292 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1293
1294 ath9k_hw_mark_phy_inactive(ah);
1295
05020d23 1296 /* Only required on the first reset */
d7e7d229
LR		 1297 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1298 REG_WRITE(ah,
1299 AR9271_RESET_POWER_DOWN_CONTROL,
1300 AR9271_RADIO_RF_RST);
1301 udelay(50);
1302 }
1303
f078f209 1304 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1305 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1306 return -EINVAL;
f078f209
LR		 1307 }
1308
05020d23 1309 /* Only required on the first reset */
d7e7d229
LR		 1310 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1311 ah->htc_reset_init = false;
1312 REG_WRITE(ah,
1313 AR9271_RESET_POWER_DOWN_CONTROL,
1314 AR9271_GATE_MAC_CTL);
1315 udelay(50);
1316 }
1317
46fe782c
S		 1318 /* Restore TSF */
1319 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1320 ath9k_hw_settsf64(ah, tsf);
1321
369391db
VT		 1322 if (AR_SREV_9280_10_OR_LATER(ah))
1323 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1324
25c56eec 1325 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1326 if (r)
1327 return r;
f078f209 1328
0ced0e17
JM		 1329 /* Setup MFP options for CCMP */
1330 if (AR_SREV_9280_20_OR_LATER(ah)) {
1331 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1332 * frames when constructing CCMP AAD. */
1333 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1334 0xc7ff);
1335 ah->sw_mgmt_crypto = false;
1336 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1337 /* Disable hardware crypto for management frames */
1338 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1339 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1340 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1341 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1342 ah->sw_mgmt_crypto = true;
1343 } else
1344 ah->sw_mgmt_crypto = true;
1345
f078f209
LR		 1346 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1347 ath9k_hw_set_delta_slope(ah, chan);
1348
8fe65368 1349 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1350 ah->eep_ops->set_board_values(ah, chan);
a7765828 1351
1510718d
LR		 1352 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1353 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1354 | macStaId1
1355 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1356 | (ah->config.
60b67f51 1357 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 1358 | ah->sta_id1_defaults);
1359 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 1360
13b81559 1361 ath_hw_setbssidmask(common);
f078f209
LR		 1362
1363 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1364
3453ad88 1365 ath9k_hw_write_associd(ah);
f078f209
LR		 1366
1367 REG_WRITE(ah, AR_ISR, ~0);
1368
1369 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1370
8fe65368 1371 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1372 if (r)
1373 return r;
f078f209
LR		 1374
1375 for (i = 0; i < AR_NUM_DCU; i++)
1376 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1377
2660b81a
S		 1378 ah->intr_txqs = 0;
1379 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 1380 ath9k_hw_resettxqueue(ah, i);
1381
2660b81a 1382 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 1383 ath9k_hw_init_qos(ah);
1384
2660b81a 1385 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 1386 ath9k_enable_rfkill(ah);
3b319aae 1387
0005baf4 1388 ath9k_hw_init_global_settings(ah);
f078f209 1389
326bebbc 1390 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 1391 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
1392 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
1393 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
1394 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
1395 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
1396 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
1397
1398 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
1399 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
1400
1401 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1402 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1403 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1404 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1405 }
326bebbc 1406 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 1407 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1408 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1409 }
1410
f078f209
LR		 1411 REG_WRITE(ah, AR_STA_ID1,
1412 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1413
1414 ath9k_hw_set_dma(ah);
1415
1416 REG_WRITE(ah, AR_OBS, 8);
1417
0ce024cb 1418 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1419 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1420 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1421 }
1422
1423 ath9k_hw_init_bb(ah, chan);
1424
ae8d2858 1425 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1426 return -EIO;
f078f209 1427
8fe65368 1428 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1429 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1430
d7e7d229
LR		 1431 /*
1432 * For big endian systems turn on swapping for descriptors
1433 */
f078f209
LR		 1434 if (AR_SREV_9100(ah)) {
1435 u32 mask;
1436 mask = REG_READ(ah, AR_CFG);
1437 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 1438 ath_print(common, ATH_DBG_RESET,
04bd4638 1439 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1440 } else {
1441 mask =
1442 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1443 REG_WRITE(ah, AR_CFG, mask);
c46917bb 1444 ath_print(common, ATH_DBG_RESET,
04bd4638 1445 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1446 }
1447 } else {
d7e7d229
LR		 1448 /* Configure AR9271 target WLAN */
1449 if (AR_SREV_9271(ah))
1450 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 1451#ifdef __BIG_ENDIAN
d7e7d229
LR		 1452 else
1453 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1454#endif
1455 }
1456
766ec4a9 1457 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1458 ath9k_hw_btcoex_enable(ah);
1459
ae8d2858 1460 return 0;
f078f209 1461}
7322fd19 1462EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1463
f1dc5600
S		 1464/************************/
1465/* Key Cache Management */
1466/************************/
f078f209 1467
cbe61d8a 1468bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 1469{
f1dc5600 1470 u32 keyType;
f078f209 1471
2660b81a 1472 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1473 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1474 "keychache entry %u out of range\n", entry);
f078f209
LR		 1475 return false;
1476 }
1477
f1dc5600 1478 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 1479
f1dc5600
S		 1480 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1481 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1482 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1483 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1484 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1485 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1486 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1487 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 1488
f1dc5600
S		 1489 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1490 u16 micentry = entry + 64;
f078f209 1491
f1dc5600
S		 1492 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1493 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1494 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1495 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 1496
f078f209
LR		 1497 }
1498
f078f209
LR		 1499 return true;
1500}
7322fd19 1501EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 1502
cbe61d8a 1503bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 1504{
f1dc5600 1505 u32 macHi, macLo;
f078f209 1506
2660b81a 1507 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1508 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1509 "keychache entry %u out of range\n", entry);
f1dc5600 1510 return false;
f078f209
LR		 1511 }
1512
f1dc5600
S		 1513 if (mac != NULL) {
1514 macHi = (mac[5] << 8) | mac[4];
1515 macLo = (mac[3] << 24) |
1516 (mac[2] << 16) |
1517 (mac[1] << 8) |
1518 mac[0];
1519 macLo >>= 1;
1520 macLo |= (macHi & 1) << 31;
1521 macHi >>= 1;
f078f209 1522 } else {
f1dc5600 1523 macLo = macHi = 0;
f078f209 1524 }
f1dc5600
S		 1525 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1526 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 1527
f1dc5600 1528 return true;
f078f209 1529}
7322fd19 1530EXPORT_SYMBOL(ath9k_hw_keysetmac);
f078f209 1531
cbe61d8a 1532bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 1533 const struct ath9k_keyval *k,
e0caf9ea 1534 const u8 *mac)
f078f209 1535{
2660b81a 1536 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1537 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 1538 u32 key0, key1, key2, key3, key4;
1539 u32 keyType;
f078f209 1540
f1dc5600 1541 if (entry >= pCap->keycache_size) {
c46917bb
LR		 1542 ath_print(common, ATH_DBG_FATAL,
1543 "keycache entry %u out of range\n", entry);
f1dc5600 1544 return false;
f078f209
LR		 1545 }
1546
f1dc5600
S		 1547 switch (k->kv_type) {
1548 case ATH9K_CIPHER_AES_OCB:
1549 keyType = AR_KEYTABLE_TYPE_AES;
1550 break;
1551 case ATH9K_CIPHER_AES_CCM:
1552 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 1553 ath_print(common, ATH_DBG_ANY,
1554 "AES-CCM not supported by mac rev 0x%x\n",
1555 ah->hw_version.macRev);
f1dc5600
S		 1556 return false;
1557 }
1558 keyType = AR_KEYTABLE_TYPE_CCM;
1559 break;
1560 case ATH9K_CIPHER_TKIP:
1561 keyType = AR_KEYTABLE_TYPE_TKIP;
1562 if (ATH9K_IS_MIC_ENABLED(ah)
1563 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 1564 ath_print(common, ATH_DBG_ANY,
1565 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 1566 return false;
1567 }
1568 break;
1569 case ATH9K_CIPHER_WEP:
e31a16d6 1570 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 1571 ath_print(common, ATH_DBG_ANY,
1572 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 1573 return false;
1574 }
e31a16d6 1575 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 1576 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 1577 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 1578 keyType = AR_KEYTABLE_TYPE_104;
1579 else
1580 keyType = AR_KEYTABLE_TYPE_128;
1581 break;
1582 case ATH9K_CIPHER_CLR:
1583 keyType = AR_KEYTABLE_TYPE_CLR;
1584 break;
1585 default:
c46917bb
LR		 1586 ath_print(common, ATH_DBG_FATAL,
1587 "cipher %u not supported\n", k->kv_type);
f1dc5600 1588 return false;
f078f209
LR		 1589 }
1590
e0caf9ea
JM		 1591 key0 = get_unaligned_le32(k->kv_val + 0);
1592 key1 = get_unaligned_le16(k->kv_val + 4);
1593 key2 = get_unaligned_le32(k->kv_val + 6);
1594 key3 = get_unaligned_le16(k->kv_val + 10);
1595 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 1596 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 1597 key4 &= 0xff;
f078f209 1598
672903b3
JM		 1599 /*
1600 * Note: Key cache registers access special memory area that requires
1601 * two 32-bit writes to actually update the values in the internal
1602 * memory. Consequently, the exact order and pairs used here must be
1603 * maintained.
1604 */
1605
f1dc5600
S		 1606 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1607 u16 micentry = entry + 64;
f078f209 1608
672903b3
JM		 1609 /*
1610 * Write inverted key[47:0] first to avoid Michael MIC errors
1611 * on frames that could be sent or received at the same time.
1612 * The correct key will be written in the end once everything
1613 * else is ready.
1614 */
f1dc5600
S		 1615 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1616 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 1617
1618 /* Write key[95:48] */
f1dc5600
S		 1619 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1620 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1621
1622 /* Write key[127:96] and key type */
f1dc5600
S		 1623 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1624 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 1625
1626 /* Write MAC address for the entry */
f1dc5600 1627 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 1628
2660b81a 1629 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 1630 /*
1631 * TKIP uses two key cache entries:
1632 * Michael MIC TX/RX keys in the same key cache entry
1633 * (idx = main index + 64):
1634 * key0 [31:0] = RX key [31:0]
1635 * key1 [15:0] = TX key [31:16]
1636 * key1 [31:16] = reserved
1637 * key2 [31:0] = RX key [63:32]
1638 * key3 [15:0] = TX key [15:0]
1639 * key3 [31:16] = reserved
1640 * key4 [31:0] = TX key [63:32]
1641 */
f1dc5600 1642 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 1643
f1dc5600
S		 1644 mic0 = get_unaligned_le32(k->kv_mic + 0);
1645 mic2 = get_unaligned_le32(k->kv_mic + 4);
1646 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1647 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1648 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 1649
1650 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 1651 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1652 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 1653
1654 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 1655 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1656 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 1657
1658 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1659 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1660 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1661 AR_KEYTABLE_TYPE_CLR);
f078f209 1662
f1dc5600 1663 } else {
672903b3
JM		 1664 /*
1665 * TKIP uses four key cache entries (two for group
1666 * keys):
1667 * Michael MIC TX/RX keys are in different key cache
1668 * entries (idx = main index + 64 for TX and
1669 * main index + 32 + 96 for RX):
1670 * key0 [31:0] = TX/RX MIC key [31:0]
1671 * key1 [31:0] = reserved
1672 * key2 [31:0] = TX/RX MIC key [63:32]
1673 * key3 [31:0] = reserved
1674 * key4 [31:0] = reserved
1675 *
1676 * Upper layer code will call this function separately
1677 * for TX and RX keys when these registers offsets are
1678 * used.
1679 */
f1dc5600 1680 u32 mic0, mic2;
f078f209 1681
f1dc5600
S		 1682 mic0 = get_unaligned_le32(k->kv_mic + 0);
1683 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 1684
1685 /* Write MIC key[31:0] */
f1dc5600
S		 1686 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1687 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 1688
1689 /* Write MIC key[63:32] */
f1dc5600
S		 1690 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1691 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 1692
1693 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1694 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1695 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1696 AR_KEYTABLE_TYPE_CLR);
1697 }
672903b3
JM		 1698
1699 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 1700 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1701 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 1702
1703 /*
1704 * Write the correct (un-inverted) key[47:0] last to enable
1705 * TKIP now that all other registers are set with correct
1706 * values.
1707 */
f1dc5600
S		 1708 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1709 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1710 } else {
672903b3 1711 /* Write key[47:0] */
f1dc5600
S		 1712 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1713 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 1714
1715 /* Write key[95:48] */
f1dc5600
S		 1716 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1717 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1718
1719 /* Write key[127:96] and key type */
f1dc5600
S		 1720 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1721 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 1722
672903b3 1723 /* Write MAC address for the entry */
f1dc5600
S		 1724 (void) ath9k_hw_keysetmac(ah, entry, mac);
1725 }
f078f209 1726
f078f209
LR		 1727 return true;
1728}
7322fd19 1729EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 1730
cbe61d8a 1731bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 1732{
2660b81a 1733 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 1734 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1735 if (val & AR_KEYTABLE_VALID)
1736 return true;
1737 }
1738 return false;
f078f209 1739}
7322fd19 1740EXPORT_SYMBOL(ath9k_hw_keyisvalid);
f078f209 1741
f1dc5600
S		 1742/******************************/
1743/* Power Management (Chipset) */
1744/******************************/
1745
42d5bc3f
LR		 1746/*
1747 * Notify Power Mgt is disabled in self-generated frames.
1748 * If requested, force chip to sleep.
1749 */
cbe61d8a 1750static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1751{
f1dc5600
S		 1752 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1753 if (setChip) {
42d5bc3f
LR		 1754 /*
1755 * Clear the RTC force wake bit to allow the
1756 * mac to go to sleep.
1757 */
f1dc5600
S		 1758 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1759 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1760 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1761 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1762
42d5bc3f 1763 /* Shutdown chip. Active low */
14b3af38 1764 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1765 REG_CLR_BIT(ah, (AR_RTC_RESET),
1766 AR_RTC_RESET_EN);
f1dc5600 1767 }
f078f209
LR		 1768}
1769
bbd79af5
LR		 1770/*
1771 * Notify Power Management is enabled in self-generating
1772 * frames. If request, set power mode of chip to
1773 * auto/normal. Duration in units of 128us (1/8 TU).
1774 */
cbe61d8a 1775static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1776{
f1dc5600
S		 1777 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1778 if (setChip) {
2660b81a 1779 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1780
f1dc5600 1781 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1782 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1783 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1784 AR_RTC_FORCE_WAKE_ON_INT);
1785 } else {
bbd79af5
LR		 1786 /*
1787 * Clear the RTC force wake bit to allow the
1788 * mac to go to sleep.
1789 */
f1dc5600
S		 1790 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1791 AR_RTC_FORCE_WAKE_EN);
f078f209 1792 }
f078f209 1793 }
f078f209
LR		 1794}
1795
cbe61d8a 1796static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1797{
f1dc5600
S		 1798 u32 val;
1799 int i;
f078f209 1800
f1dc5600
S		 1801 if (setChip) {
1802 if ((REG_READ(ah, AR_RTC_STATUS) &
1803 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1804 if (ath9k_hw_set_reset_reg(ah,
1805 ATH9K_RESET_POWER_ON) != true) {
1806 return false;
1807 }
e041228f
LR		 1808 if (!AR_SREV_9300_20_OR_LATER(ah))
1809 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1810 }
1811 if (AR_SREV_9100(ah))
1812 REG_SET_BIT(ah, AR_RTC_RESET,
1813 AR_RTC_RESET_EN);
f078f209 1814
f1dc5600
S		 1815 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1816 AR_RTC_FORCE_WAKE_EN);
1817 udelay(50);
f078f209 1818
f1dc5600
S		 1819 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1820 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1821 if (val == AR_RTC_STATUS_ON)
1822 break;
1823 udelay(50);
1824 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1825 AR_RTC_FORCE_WAKE_EN);
f078f209 1826 }
f1dc5600 1827 if (i == 0) {
c46917bb
LR		 1828 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1829 "Failed to wakeup in %uus\n",
1830 POWER_UP_TIME / 20);
f1dc5600 1831 return false;
f078f209 1832 }
f078f209
LR		 1833 }
1834
f1dc5600 1835 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1836
f1dc5600 1837 return true;
f078f209
LR		 1838}
1839
9ecdef4b 1840bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1841{
c46917bb 1842 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1843 int status = true, setChip = true;
f1dc5600
S		 1844 static const char *modes[] = {
1845 "AWAKE",
1846 "FULL-SLEEP",
1847 "NETWORK SLEEP",
1848 "UNDEFINED"
1849 };
f1dc5600 1850
cbdec975
GJ		 1851 if (ah->power_mode == mode)
1852 return status;
1853
c46917bb
LR		 1854 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1855 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1856
1857 switch (mode) {
1858 case ATH9K_PM_AWAKE:
1859 status = ath9k_hw_set_power_awake(ah, setChip);
1860 break;
1861 case ATH9K_PM_FULL_SLEEP:
1862 ath9k_set_power_sleep(ah, setChip);
2660b81a 1863 ah->chip_fullsleep = true;
f1dc5600
S		 1864 break;
1865 case ATH9K_PM_NETWORK_SLEEP:
1866 ath9k_set_power_network_sleep(ah, setChip);
1867 break;
f078f209 1868 default:
c46917bb
LR		 1869 ath_print(common, ATH_DBG_FATAL,
1870 "Unknown power mode %u\n", mode);
f078f209
LR		 1871 return false;
1872 }
2660b81a 1873 ah->power_mode = mode;
f1dc5600
S		 1874
1875 return status;
f078f209 1876}
7322fd19 1877EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1878
f1dc5600
S		 1879/**********************/
1880/* Interrupt Handling */
1881/**********************/
1882
cbe61d8a 1883bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 1884{
1885 u32 host_isr;
1886
1887 if (AR_SREV_9100(ah))
1888 return true;
1889
1890 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
1891 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
1892 return true;
1893
1894 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1895 if ((host_isr & AR_INTR_SYNC_DEFAULT)
1896 && (host_isr != AR_INTR_SPURIOUS))
1897 return true;
1898
1899 return false;
1900}
7322fd19 1901EXPORT_SYMBOL(ath9k_hw_intrpend);
f078f209 1902
cbe61d8a 1903bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 1904{
1905 u32 isr = 0;
1906 u32 mask2 = 0;
2660b81a 1907 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 1908 u32 sync_cause = 0;
1909 bool fatal_int = false;
c46917bb 1910 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 1911
1912 if (!AR_SREV_9100(ah)) {
1913 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
1914 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
1915 == AR_RTC_STATUS_ON) {
1916 isr = REG_READ(ah, AR_ISR);
1917 }
1918 }
1919
f1dc5600
S		 1920 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
1921 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 1922
1923 *masked = 0;
1924
1925 if (!isr && !sync_cause)
1926 return false;
1927 } else {
1928 *masked = 0;
1929 isr = REG_READ(ah, AR_ISR);
1930 }
1931
1932 if (isr) {
f078f209
LR		 1933 if (isr & AR_ISR_BCNMISC) {
1934 u32 isr2;
1935 isr2 = REG_READ(ah, AR_ISR_S2);
1936 if (isr2 & AR_ISR_S2_TIM)
1937 mask2 |= ATH9K_INT_TIM;
1938 if (isr2 & AR_ISR_S2_DTIM)
1939 mask2 |= ATH9K_INT_DTIM;
1940 if (isr2 & AR_ISR_S2_DTIMSYNC)
1941 mask2 |= ATH9K_INT_DTIMSYNC;
1942 if (isr2 & (AR_ISR_S2_CABEND))
1943 mask2 |= ATH9K_INT_CABEND;
1944 if (isr2 & AR_ISR_S2_GTT)
1945 mask2 |= ATH9K_INT_GTT;
1946 if (isr2 & AR_ISR_S2_CST)
1947 mask2 |= ATH9K_INT_CST;
4af9cf4f
S		 1948 if (isr2 & AR_ISR_S2_TSFOOR)
1949 mask2 |= ATH9K_INT_TSFOOR;
f078f209
LR		 1950 }
1951
1952 isr = REG_READ(ah, AR_ISR_RAC);
1953 if (isr == 0xffffffff) {
1954 *masked = 0;
1955 return false;
1956 }
1957
1958 *masked = isr & ATH9K_INT_COMMON;
1959
0ce024cb 1960 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1961 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
1962 *masked |= ATH9K_INT_RX;
1963 }
1964
1965 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
1966 *masked |= ATH9K_INT_RX;
1967 if (isr &
1968 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
1969 AR_ISR_TXEOL)) {
1970 u32 s0_s, s1_s;
1971
1972 *masked |= ATH9K_INT_TX;
1973
1974 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 1975 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
1976 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 1977
1978 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 1979 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
1980 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 1981 }
1982
1983 if (isr & AR_ISR_RXORN) {
c46917bb
LR		 1984 ath_print(common, ATH_DBG_INTERRUPT,
1985 "receive FIFO overrun interrupt\n");
f078f209
LR		 1986 }
1987
1988 if (!AR_SREV_9100(ah)) {
60b67f51 1989 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 1990 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
1991 if (isr5 & AR_ISR_S5_TIM_TIMER)
1992 *masked |= ATH9K_INT_TIM_TIMER;
1993 }
1994 }
1995
1996 *masked |= mask2;
1997 }
f1dc5600 1998
f078f209
LR		 1999 if (AR_SREV_9100(ah))
2000 return true;
f1dc5600 2001
ff155a45
VT		 2002 if (isr & AR_ISR_GENTMR) {
2003 u32 s5_s;
2004
2005 s5_s = REG_READ(ah, AR_ISR_S5_S);
2006 if (isr & AR_ISR_GENTMR) {
2007 ah->intr_gen_timer_trigger =
2008 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2009
2010 ah->intr_gen_timer_thresh =
2011 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2012
2013 if (ah->intr_gen_timer_trigger)
2014 *masked |= ATH9K_INT_GENTIMER;
2015
2016 }
2017 }
2018
f078f209
LR		 2019 if (sync_cause) {
2020 fatal_int =
2021 (sync_cause &
2022 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2023 ? true : false;
2024
2025 if (fatal_int) {
2026 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
c46917bb
LR		 2027 ath_print(common, ATH_DBG_ANY,
2028 "received PCI FATAL interrupt\n");
f078f209
LR		 2029 }
2030 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
c46917bb
LR		 2031 ath_print(common, ATH_DBG_ANY,
2032 "received PCI PERR interrupt\n");
f078f209 2033 }
a89bff9a 2034 *masked |= ATH9K_INT_FATAL;
f078f209
LR		 2035 }
2036 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
c46917bb
LR		 2037 ath_print(common, ATH_DBG_INTERRUPT,
2038 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 2039 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2040 REG_WRITE(ah, AR_RC, 0);
2041 *masked |= ATH9K_INT_FATAL;
2042 }
2043 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
c46917bb
LR		 2044 ath_print(common, ATH_DBG_INTERRUPT,
2045 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 2046 }
2047
2048 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2049 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2050 }
f1dc5600 2051
f078f209
LR		 2052 return true;
2053}
7322fd19 2054EXPORT_SYMBOL(ath9k_hw_getisr);
f078f209 2055
cbe61d8a 2056enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 2057{
152d530d 2058 enum ath9k_int omask = ah->imask;
f078f209 2059 u32 mask, mask2;
2660b81a 2060 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2061 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2062
c46917bb 2063 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 2064
2065 if (omask & ATH9K_INT_GLOBAL) {
c46917bb 2066 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 2067 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2068 (void) REG_READ(ah, AR_IER);
2069 if (!AR_SREV_9100(ah)) {
2070 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2071 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2072
2073 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2074 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2075 }
2076 }
2077
2078 mask = ints & ATH9K_INT_COMMON;
2079 mask2 = 0;
2080
2081 if (ints & ATH9K_INT_TX) {
2660b81a 2082 if (ah->txok_interrupt_mask)
f078f209 2083 mask |= AR_IMR_TXOK;
2660b81a 2084 if (ah->txdesc_interrupt_mask)
f078f209 2085 mask |= AR_IMR_TXDESC;
2660b81a 2086 if (ah->txerr_interrupt_mask)
f078f209 2087 mask |= AR_IMR_TXERR;
2660b81a 2088 if (ah->txeol_interrupt_mask)
f078f209
LR		 2089 mask |= AR_IMR_TXEOL;
2090 }
2091 if (ints & ATH9K_INT_RX) {
2092 mask |= AR_IMR_RXERR;
0ce024cb 2093 if (ah->config.rx_intr_mitigation)
f078f209
LR		 2094 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2095 else
2096 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 2097 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 2098 mask |= AR_IMR_GENTMR;
2099 }
2100
2101 if (ints & (ATH9K_INT_BMISC)) {
2102 mask |= AR_IMR_BCNMISC;
2103 if (ints & ATH9K_INT_TIM)
2104 mask2 |= AR_IMR_S2_TIM;
2105 if (ints & ATH9K_INT_DTIM)
2106 mask2 |= AR_IMR_S2_DTIM;
2107 if (ints & ATH9K_INT_DTIMSYNC)
2108 mask2 |= AR_IMR_S2_DTIMSYNC;
2109 if (ints & ATH9K_INT_CABEND)
4af9cf4f
S		 2110 mask2 |= AR_IMR_S2_CABEND;
2111 if (ints & ATH9K_INT_TSFOOR)
2112 mask2 |= AR_IMR_S2_TSFOOR;
f078f209
LR		 2113 }
2114
2115 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2116 mask |= AR_IMR_BCNMISC;
2117 if (ints & ATH9K_INT_GTT)
2118 mask2 |= AR_IMR_S2_GTT;
2119 if (ints & ATH9K_INT_CST)
2120 mask2 |= AR_IMR_S2_CST;
2121 }
2122
c46917bb 2123 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209 2124 REG_WRITE(ah, AR_IMR, mask);
74bad5cb
PR		 2125 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2126 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2127 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2128 ah->imrs2_reg |= mask2;
2129 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 2130
60b67f51 2131 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2132 if (ints & ATH9K_INT_TIM_TIMER)
2133 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2134 else
2135 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2136 }
2137
2138 if (ints & ATH9K_INT_GLOBAL) {
c46917bb 2139 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 2140 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2141 if (!AR_SREV_9100(ah)) {
2142 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2143 AR_INTR_MAC_IRQ);
2144 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2145
2146
2147 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2148 AR_INTR_SYNC_DEFAULT);
2149 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2150 AR_INTR_SYNC_DEFAULT);
2151 }
c46917bb
LR		 2152 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2153 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
f078f209
LR		 2154 }
2155
2156 return omask;
2157}
7322fd19 2158EXPORT_SYMBOL(ath9k_hw_set_interrupts);
f078f209 2159
f1dc5600
S		 2160/*******************/
2161/* Beacon Handling */
2162/*******************/
2163
cbe61d8a 2164void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2165{
f078f209
LR		 2166 int flags = 0;
2167
2660b81a 2168 ah->beacon_interval = beacon_period;
f078f209 2169
2660b81a 2170 switch (ah->opmode) {
d97809db
CM		 2171 case NL80211_IFTYPE_STATION:
2172 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 2173 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2174 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2175 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2176 flags |= AR_TBTT_TIMER_EN;
2177 break;
d97809db 2178 case NL80211_IFTYPE_ADHOC:
9cb5412b 2179 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 2180 REG_SET_BIT(ah, AR_TXCFG,
2181 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2182 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2183 TU_TO_USEC(next_beacon +
2660b81a
S		 2184 (ah->atim_window ? ah->
2185 atim_window : 1)));
f078f209 2186 flags |= AR_NDP_TIMER_EN;
d97809db 2187 case NL80211_IFTYPE_AP:
f078f209
LR		 2188 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2189 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2190 TU_TO_USEC(next_beacon -
2660b81a 2191 ah->config.
60b67f51 2192 dma_beacon_response_time));
f078f209
LR		 2193 REG_WRITE(ah, AR_NEXT_SWBA,
2194 TU_TO_USEC(next_beacon -
2660b81a 2195 ah->config.
60b67f51 2196 sw_beacon_response_time));
f078f209
LR		 2197 flags |=
2198 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2199 break;
d97809db 2200 default:
c46917bb
LR		 2201 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2202 "%s: unsupported opmode: %d\n",
2203 __func__, ah->opmode);
d97809db
CM		 2204 return;
2205 break;
f078f209
LR		 2206 }
2207
2208 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2209 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2210 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2211 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2212
2213 beacon_period &= ~ATH9K_BEACON_ENA;
2214 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 2215 ath9k_hw_reset_tsf(ah);
2216 }
2217
2218 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2219}
7322fd19 2220EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2221
cbe61d8a 2222void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2223 const struct ath9k_beacon_state *bs)
f078f209
LR		 2224{
2225 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2226 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2227 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 2228
2229 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2230
2231 REG_WRITE(ah, AR_BEACON_PERIOD,
2232 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2233 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2234 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2235
2236 REG_RMW_FIELD(ah, AR_RSSI_THR,
2237 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2238
2239 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
2240
2241 if (bs->bs_sleepduration > beaconintval)
2242 beaconintval = bs->bs_sleepduration;
2243
2244 dtimperiod = bs->bs_dtimperiod;
2245 if (bs->bs_sleepduration > dtimperiod)
2246 dtimperiod = bs->bs_sleepduration;
2247
2248 if (beaconintval == dtimperiod)
2249 nextTbtt = bs->bs_nextdtim;
2250 else
2251 nextTbtt = bs->bs_nexttbtt;
2252
c46917bb
LR		 2253 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2254 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2255 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2256 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2257
f1dc5600
S		 2258 REG_WRITE(ah, AR_NEXT_DTIM,
2259 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2260 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 2261
f1dc5600
S		 2262 REG_WRITE(ah, AR_SLEEP1,
2263 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2264 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2265
f1dc5600
S		 2266 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2267 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2268 else
2269 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2270
f1dc5600
S		 2271 REG_WRITE(ah, AR_SLEEP2,
2272 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2273
f1dc5600
S		 2274 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2275 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2276
f1dc5600
S		 2277 REG_SET_BIT(ah, AR_TIMER_MODE,
2278 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2279 AR_DTIM_TIMER_EN);
f078f209 2280
4af9cf4f
S		 2281 /* TSF Out of Range Threshold */
2282 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2283}
7322fd19 2284EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2285
f1dc5600
S		 2286/*******************/
2287/* HW Capabilities */
2288/*******************/
2289
a9a29ce6 2290int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2291{
2660b81a 2292 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2293 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2294 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 2295 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 2296
f1dc5600 2297 u16 capField = 0, eeval;
f078f209 2298
f74df6fb 2299 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2300 regulatory->current_rd = eeval;
f078f209 2301
f74df6fb 2302 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 2303 if (AR_SREV_9285_10_OR_LATER(ah))
2304 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 2305 regulatory->current_rd_ext = eeval;
f078f209 2306
f74df6fb 2307 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 2308
2660b81a 2309 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2310 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2311 if (regulatory->current_rd == 0x64 ||
2312 regulatory->current_rd == 0x65)
2313 regulatory->current_rd += 5;
2314 else if (regulatory->current_rd == 0x41)
2315 regulatory->current_rd = 0x43;
c46917bb
LR		 2316 ath_print(common, ATH_DBG_REGULATORY,
2317 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 2318 }
f078f209 2319
f74df6fb 2320 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6
GJ		 2321 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2322 ath_print(common, ATH_DBG_FATAL,
2323 "no band has been marked as supported in EEPROM.\n");
2324 return -EINVAL;
2325 }
2326
f1dc5600 2327 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 2328
f1dc5600
S		 2329 if (eeval & AR5416_OPFLAGS_11A) {
2330 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 2331 if (ah->config.ht_enable) {
f1dc5600
S		 2332 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2333 set_bit(ATH9K_MODE_11NA_HT20,
2334 pCap->wireless_modes);
2335 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2336 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2337 pCap->wireless_modes);
2338 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2339 pCap->wireless_modes);
2340 }
f078f209 2341 }
f078f209
LR		 2342 }
2343
f1dc5600 2344 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 2345 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 2346 if (ah->config.ht_enable) {
f1dc5600
S		 2347 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2348 set_bit(ATH9K_MODE_11NG_HT20,
2349 pCap->wireless_modes);
2350 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2351 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2352 pCap->wireless_modes);
2353 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2354 pCap->wireless_modes);
2355 }
2356 }
f078f209 2357 }
f1dc5600 2358
f74df6fb 2359 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2360 /*
2361 * For AR9271 we will temporarilly uses the rx chainmax as read from
2362 * the EEPROM.
2363 */
8147f5de 2364 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2365 !(eeval & AR5416_OPFLAGS_11A) &&
2366 !(AR_SREV_9271(ah)))
2367 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 2368 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2369 else
d7e7d229 2370 /* Use rx_chainmask from EEPROM. */
8147f5de 2371 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2372
d535a42a 2373 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 2374 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2375
f1dc5600
S		 2376 pCap->low_2ghz_chan = 2312;
2377 pCap->high_2ghz_chan = 2732;
f078f209 2378
f1dc5600
S		 2379 pCap->low_5ghz_chan = 4920;
2380 pCap->high_5ghz_chan = 6100;
f078f209 2381
f1dc5600
S		 2382 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2383 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2384 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 2385
f1dc5600
S		 2386 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2387 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2388 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 2389
2660b81a 2390 if (ah->config.ht_enable)
f1dc5600
S		 2391 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2392 else
2393 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2394
f1dc5600
S		 2395 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2396 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2397 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2398 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 2399
f1dc5600
S		 2400 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2401 pCap->total_queues =
2402 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2403 else
2404 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 2405
f1dc5600
S		 2406 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2407 pCap->keycache_size =
2408 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2409 else
2410 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 2411
f1dc5600 2412 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f4709fdf
LR		 2413
2414 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2415 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2416 else
2417 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 2418
5b5fa355
S		 2419 if (AR_SREV_9271(ah))
2420 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2421 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2422 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2423 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 2424 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2425 else
2426 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2427
f1dc5600
S		 2428 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2429 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2430 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2431 } else {
2432 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 2433 }
2434
f1dc5600
S		 2435 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2436
e97275cb 2437#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2438 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2439 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2440 ah->rfkill_gpio =
2441 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2442 ah->rfkill_polarity =
2443 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2444
2445 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2446 }
f1dc5600 2447#endif
bde748a4
VN		 2448 if (AR_SREV_9271(ah))
2449 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2450 else
2451 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2452
e7594072 2453 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2454 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2455 else
2456 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2457
608b88cb 2458 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 2459 pCap->reg_cap =
2460 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2461 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2462 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2463 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 2464 } else {
f1dc5600
S		 2465 pCap->reg_cap =
2466 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2467 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 2468 }
f078f209 2469
ebb90cfc
SB		 2470 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2471 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2472 AR_SREV_5416(ah))
2473 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 2474
2475 pCap->num_antcfg_5ghz =
f74df6fb 2476 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 2477 pCap->num_antcfg_2ghz =
f74df6fb 2478 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 2479
fe12946e 2480 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 2481 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 2482 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2483 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 2484
8c8f9ba7 2485 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 2486 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2487 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 2488 } else {
766ec4a9 2489 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 2490 }
22f25d0d 2491 } else {
766ec4a9 2492 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 2493 }
a9a29ce6 2494
ceb26445 2495 if (AR_SREV_9300_20_OR_LATER(ah)) {
1adf02ff 2496 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
ceb26445
VT		 2497 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2498 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2499 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3
VT		 2500 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2501 } else {
2502 pCap->tx_desc_len = sizeof(struct ath_desc);
ceb26445 2503 }
1adf02ff 2504
a9a29ce6 2505 return 0;
f078f209
LR		 2506}
2507
cbe61d8a 2508bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2509 u32 capability, u32 *result)
f078f209 2510{
608b88cb 2511 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 2512 switch (type) {
2513 case ATH9K_CAP_CIPHER:
2514 switch (capability) {
2515 case ATH9K_CIPHER_AES_CCM:
2516 case ATH9K_CIPHER_AES_OCB:
2517 case ATH9K_CIPHER_TKIP:
2518 case ATH9K_CIPHER_WEP:
2519 case ATH9K_CIPHER_MIC:
2520 case ATH9K_CIPHER_CLR:
2521 return true;
2522 default:
2523 return false;
2524 }
2525 case ATH9K_CAP_TKIP_MIC:
2526 switch (capability) {
2527 case 0:
2528 return true;
2529 case 1:
2660b81a 2530 return (ah->sta_id1_defaults &
f1dc5600
S		 2531 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2532 false;
2533 }
2534 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 2535 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 2536 false : true;
f1dc5600
S		 2537 case ATH9K_CAP_MCAST_KEYSRCH:
2538 switch (capability) {
2539 case 0:
2540 return true;
2541 case 1:
2542 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2543 return false;
2544 } else {
2660b81a 2545 return (ah->sta_id1_defaults &
f1dc5600
S		 2546 AR_STA_ID1_MCAST_KSRCH) ? true :
2547 false;
2548 }
2549 }
2550 return false;
f1dc5600
S		 2551 case ATH9K_CAP_TXPOW:
2552 switch (capability) {
2553 case 0:
2554 return 0;
2555 case 1:
608b88cb 2556 *result = regulatory->power_limit;
f1dc5600
S		 2557 return 0;
2558 case 2:
608b88cb 2559 *result = regulatory->max_power_level;
f1dc5600
S		 2560 return 0;
2561 case 3:
608b88cb 2562 *result = regulatory->tp_scale;
f1dc5600
S		 2563 return 0;
2564 }
2565 return false;
8bd1d07f
SB		 2566 case ATH9K_CAP_DS:
2567 return (AR_SREV_9280_20_OR_LATER(ah) &&
2568 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2569 ? false : true;
f1dc5600
S		 2570 default:
2571 return false;
f078f209 2572 }
f078f209 2573}
7322fd19 2574EXPORT_SYMBOL(ath9k_hw_getcapability);
f078f209 2575
cbe61d8a 2576bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2577 u32 capability, u32 setting, int *status)
f078f209 2578{
f1dc5600
S		 2579 switch (type) {
2580 case ATH9K_CAP_TKIP_MIC:
2581 if (setting)
2660b81a 2582 ah->sta_id1_defaults |=
f1dc5600
S		 2583 AR_STA_ID1_CRPT_MIC_ENABLE;
2584 else
2660b81a 2585 ah->sta_id1_defaults &=
f1dc5600
S		 2586 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2587 return true;
f1dc5600
S		 2588 case ATH9K_CAP_MCAST_KEYSRCH:
2589 if (setting)
2660b81a 2590 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2591 else
2660b81a 2592 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2593 return true;
f1dc5600
S		 2594 default:
2595 return false;
f078f209
LR		 2596 }
2597}
7322fd19 2598EXPORT_SYMBOL(ath9k_hw_setcapability);
f078f209 2599
f1dc5600
S		 2600/****************************/
2601/* GPIO / RFKILL / Antennae */
2602/****************************/
f078f209 2603
cbe61d8a 2604static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2605 u32 gpio, u32 type)
2606{
2607 int addr;
2608 u32 gpio_shift, tmp;
f078f209 2609
f1dc5600
S		 2610 if (gpio > 11)
2611 addr = AR_GPIO_OUTPUT_MUX3;
2612 else if (gpio > 5)
2613 addr = AR_GPIO_OUTPUT_MUX2;
2614 else
2615 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2616
f1dc5600 2617 gpio_shift = (gpio % 6) * 5;
f078f209 2618
f1dc5600
S		 2619 if (AR_SREV_9280_20_OR_LATER(ah)
2620 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2621 REG_RMW(ah, addr, (type << gpio_shift),
2622 (0x1f << gpio_shift));
f078f209 2623 } else {
f1dc5600
S		 2624 tmp = REG_READ(ah, addr);
2625 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2626 tmp &= ~(0x1f << gpio_shift);
2627 tmp |= (type << gpio_shift);
2628 REG_WRITE(ah, addr, tmp);
f078f209 2629 }
f078f209
LR		 2630}
2631
cbe61d8a 2632void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2633{
f1dc5600 2634 u32 gpio_shift;
f078f209 2635
9680e8a3 2636 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2637
f1dc5600 2638 gpio_shift = gpio << 1;
f078f209 2639
f1dc5600
S		 2640 REG_RMW(ah,
2641 AR_GPIO_OE_OUT,
2642 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2643 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2644}
7322fd19 2645EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2646
cbe61d8a 2647u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2648{
cb33c412
SB		 2649#define MS_REG_READ(x, y) \
2650 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2651
2660b81a 2652 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2653 return 0xffffffff;
f078f209 2654
783dfca1
FF		 2655 if (AR_SREV_9300_20_OR_LATER(ah))
2656 return MS_REG_READ(AR9300, gpio) != 0;
2657 else if (AR_SREV_9271(ah))
5b5fa355
S		 2658 return MS_REG_READ(AR9271, gpio) != 0;
2659 else if (AR_SREV_9287_10_OR_LATER(ah))
ac88b6ec
VN		 2660 return MS_REG_READ(AR9287, gpio) != 0;
2661 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2662 return MS_REG_READ(AR9285, gpio) != 0;
2663 else if (AR_SREV_9280_10_OR_LATER(ah))
2664 return MS_REG_READ(AR928X, gpio) != 0;
2665 else
2666 return MS_REG_READ(AR, gpio) != 0;
f078f209 2667}
7322fd19 2668EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2669
cbe61d8a 2670void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2671 u32 ah_signal_type)
f078f209 2672{
f1dc5600 2673 u32 gpio_shift;
f078f209 2674
f1dc5600 2675 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 2676
f1dc5600 2677 gpio_shift = 2 * gpio;
f078f209 2678
f1dc5600
S		 2679 REG_RMW(ah,
2680 AR_GPIO_OE_OUT,
2681 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2682 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2683}
7322fd19 2684EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2685
cbe61d8a 2686void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2687{
5b5fa355
S		 2688 if (AR_SREV_9271(ah))
2689 val = ~val;
2690
f1dc5600
S		 2691 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2692 AR_GPIO_BIT(gpio));
f078f209 2693}
7322fd19 2694EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2695
cbe61d8a 2696u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2697{
f1dc5600 2698 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2699}
7322fd19 2700EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2701
cbe61d8a 2702void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2703{
f1dc5600 2704 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2705}
7322fd19 2706EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2707
f1dc5600
S		 2708/*********************/
2709/* General Operation */
2710/*********************/
2711
cbe61d8a 2712u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2713{
f1dc5600
S		 2714 u32 bits = REG_READ(ah, AR_RX_FILTER);
2715 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2716
f1dc5600
S		 2717 if (phybits & AR_PHY_ERR_RADAR)
2718 bits |= ATH9K_RX_FILTER_PHYRADAR;
2719 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2720 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2721
f1dc5600 2722 return bits;
f078f209 2723}
7322fd19 2724EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2725
cbe61d8a 2726void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2727{
f1dc5600 2728 u32 phybits;
f078f209 2729
7ea310be
S		 2730 REG_WRITE(ah, AR_RX_FILTER, bits);
2731
f1dc5600
S		 2732 phybits = 0;
2733 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2734 phybits |= AR_PHY_ERR_RADAR;
2735 if (bits & ATH9K_RX_FILTER_PHYERR)
2736 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2737 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2738
f1dc5600
S		 2739 if (phybits)
2740 REG_WRITE(ah, AR_RXCFG,
2741 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2742 else
2743 REG_WRITE(ah, AR_RXCFG,
2744 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2745}
7322fd19 2746EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2747
cbe61d8a 2748bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2749{
63a75b91
SB		 2750 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2751 return false;
2752
2753 ath9k_hw_init_pll(ah, NULL);
2754 return true;
f1dc5600 2755}
7322fd19 2756EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2757
cbe61d8a 2758bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2759{
9ecdef4b 2760 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2761 return false;
f078f209 2762
63a75b91
SB		 2763 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2764 return false;
2765
2766 ath9k_hw_init_pll(ah, NULL);
2767 return true;
f078f209 2768}
7322fd19 2769EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2770
8fbff4b8 2771void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 2772{
608b88cb 2773 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2774 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2775 struct ieee80211_channel *channel = chan->chan;
f078f209 2776
608b88cb 2777 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2778
8fbff4b8 2779 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2780 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2781 channel->max_antenna_gain * 2,
2782 channel->max_power * 2,
2783 min((u32) MAX_RATE_POWER,
608b88cb 2784 (u32) regulatory->power_limit));
6f255425 2785}
7322fd19 2786EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2787
cbe61d8a 2788void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 2789{
1510718d 2790 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
f078f209 2791}
7322fd19 2792EXPORT_SYMBOL(ath9k_hw_setmac);
f078f209 2793
cbe61d8a 2794void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2795{
2660b81a 2796 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2797}
7322fd19 2798EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2799
cbe61d8a 2800void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2801{
f1dc5600
S		 2802 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2803 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2804}
7322fd19 2805EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2806
f2b2143e 2807void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2808{
1510718d
LR		 2809 struct ath_common *common = ath9k_hw_common(ah);
2810
2811 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2812 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2813 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2814}
7322fd19 2815EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2816
cbe61d8a 2817u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2818{
f1dc5600 2819 u64 tsf;
f078f209 2820
f1dc5600
S		 2821 tsf = REG_READ(ah, AR_TSF_U32);
2822 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 2823
f1dc5600
S		 2824 return tsf;
2825}
7322fd19 2826EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2827
cbe61d8a 2828void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2829{
27abe060 2830 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2831 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2832}
7322fd19 2833EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2834
cbe61d8a 2835void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2836{
f9b604f6
GJ		 2837 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2838 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 2839 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2840 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2841
f1dc5600
S		 2842 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2843}
7322fd19 2844EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2845
54e4cec6 2846void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2847{
f1dc5600 2848 if (setting)
2660b81a 2849 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2850 else
2660b81a 2851 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2852}
7322fd19 2853EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2854
30cbd422
LR		 2855/*
2856 * Extend 15-bit time stamp from rx descriptor to
2857 * a full 64-bit TSF using the current h/w TSF.
2858*/
2859u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2860{
2861 u64 tsf;
2862
2863 tsf = ath9k_hw_gettsf64(ah);
2864 if ((tsf & 0x7fff) < rstamp)
2865 tsf -= 0x8000;
2866 return (tsf & ~0x7fff) | rstamp;
2867}
2868EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2869
25c56eec 2870void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2871{
25c56eec 2872 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2873 u32 macmode;
2874
25c56eec 2875 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2876 macmode = AR_2040_JOINED_RX_CLEAR;
2877 else
2878 macmode = 0;
f078f209 2879
f1dc5600 2880 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2881}
ff155a45
VT		 2882
2883/* HW Generic timers configuration */
2884
2885static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2886{
2887 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2888 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2889 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2890 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2891 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2892 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2893 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2894 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2895 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2896 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2897 AR_NDP2_TIMER_MODE, 0x0002},
2898 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2899 AR_NDP2_TIMER_MODE, 0x0004},
2900 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2901 AR_NDP2_TIMER_MODE, 0x0008},
2902 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2903 AR_NDP2_TIMER_MODE, 0x0010},
2904 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2905 AR_NDP2_TIMER_MODE, 0x0020},
2906 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2907 AR_NDP2_TIMER_MODE, 0x0040},
2908 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2909 AR_NDP2_TIMER_MODE, 0x0080}
2910};
2911
2912/* HW generic timer primitives */
2913
2914/* compute and clear index of rightmost 1 */
2915static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2916{
2917 u32 b;
2918
2919 b = *mask;
2920 b &= (0-b);
2921 *mask &= ~b;
2922 b *= debruijn32;
2923 b >>= 27;
2924
2925 return timer_table->gen_timer_index[b];
2926}
2927
1773912b 2928u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2929{
2930 return REG_READ(ah, AR_TSF_L32);
2931}
7322fd19 2932EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2933
2934struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2935 void (*trigger)(void *),
2936 void (*overflow)(void *),
2937 void *arg,
2938 u8 timer_index)
2939{
2940 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2941 struct ath_gen_timer *timer;
2942
2943 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2944
2945 if (timer == NULL) {
c46917bb
LR		 2946 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2947 "Failed to allocate memory"
2948 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 2949 return NULL;
2950 }
2951
2952 /* allocate a hardware generic timer slot */
2953 timer_table->timers[timer_index] = timer;
2954 timer->index = timer_index;
2955 timer->trigger = trigger;
2956 timer->overflow = overflow;
2957 timer->arg = arg;
2958
2959 return timer;
2960}
7322fd19 2961EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2962
cd9bf689
LR		 2963void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2964 struct ath_gen_timer *timer,
2965 u32 timer_next,
2966 u32 timer_period)
ff155a45
VT		 2967{
2968 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2969 u32 tsf;
2970
2971 BUG_ON(!timer_period);
2972
2973 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2974
2975 tsf = ath9k_hw_gettsf32(ah);
2976
c46917bb
LR		 2977 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2978 "curent tsf %x period %x"
2979 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 2980
2981 /*
2982 * Pull timer_next forward if the current TSF already passed it
2983 * because of software latency
2984 */
2985 if (timer_next < tsf)
2986 timer_next = tsf + timer_period;
2987
2988 /*
2989 * Program generic timer registers
2990 */
2991 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2992 timer_next);
2993 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2994 timer_period);
2995 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2996 gen_tmr_configuration[timer->index].mode_mask);
2997
2998 /* Enable both trigger and thresh interrupt masks */
2999 REG_SET_BIT(ah, AR_IMR_S5,
3000 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3001 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 3002}
7322fd19 3003EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3004
cd9bf689 3005void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3006{
3007 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3008
3009 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3010 (timer->index >= ATH_MAX_GEN_TIMER)) {
3011 return;
3012 }
3013
3014 /* Clear generic timer enable bits. */
3015 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3016 gen_tmr_configuration[timer->index].mode_mask);
3017
3018 /* Disable both trigger and thresh interrupt masks */
3019 REG_CLR_BIT(ah, AR_IMR_S5,
3020 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3021 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3022
3023 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3024}
7322fd19 3025EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3026
3027void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3028{
3029 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3030
3031 /* free the hardware generic timer slot */
3032 timer_table->timers[timer->index] = NULL;
3033 kfree(timer);
3034}
7322fd19 3035EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3036
3037/*
3038 * Generic Timer Interrupts handling
3039 */
3040void ath_gen_timer_isr(struct ath_hw *ah)
3041{
3042 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3043 struct ath_gen_timer *timer;
c46917bb 3044 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3045 u32 trigger_mask, thresh_mask, index;
3046
3047 /* get hardware generic timer interrupt status */
3048 trigger_mask = ah->intr_gen_timer_trigger;
3049 thresh_mask = ah->intr_gen_timer_thresh;
3050 trigger_mask &= timer_table->timer_mask.val;
3051 thresh_mask &= timer_table->timer_mask.val;
3052
3053 trigger_mask &= ~thresh_mask;
3054
3055 while (thresh_mask) {
3056 index = rightmost_index(timer_table, &thresh_mask);
3057 timer = timer_table->timers[index];
3058 BUG_ON(!timer);
c46917bb
LR		 3059 ath_print(common, ATH_DBG_HWTIMER,
3060 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 3061 timer->overflow(timer->arg);
3062 }
3063
3064 while (trigger_mask) {
3065 index = rightmost_index(timer_table, &trigger_mask);
3066 timer = timer_table->timers[index];
3067 BUG_ON(!timer);
c46917bb
LR		 3068 ath_print(common, ATH_DBG_HWTIMER,
3069 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3070 timer->trigger(timer->arg);
3071 }
3072}
7322fd19 3073EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3074
05020d23
S		 3075/********/
3076/* HTC */
3077/********/
3078
3079void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3080{
3081 ah->htc_reset_init = true;
3082}
3083EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3084
2da4f01a
LR		 3085static struct {
3086 u32 version;
3087 const char * name;
3088} ath_mac_bb_names[] = {
3089 /* Devices with external radios */
3090 { AR_SREV_VERSION_5416_PCI, "5416" },
3091 { AR_SREV_VERSION_5416_PCIE, "5418" },
3092 { AR_SREV_VERSION_9100, "9100" },
3093 { AR_SREV_VERSION_9160, "9160" },
3094 /* Single-chip solutions */
3095 { AR_SREV_VERSION_9280, "9280" },
3096 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3097 { AR_SREV_VERSION_9287, "9287" },
3098 { AR_SREV_VERSION_9271, "9271" },
2da4f01a
LR		 3099};
3100
3101/* For devices with external radios */
3102static struct {
3103 u16 version;
3104 const char * name;
3105} ath_rf_names[] = {
3106 { 0, "5133" },
3107 { AR_RAD5133_SREV_MAJOR, "5133" },
3108 { AR_RAD5122_SREV_MAJOR, "5122" },
3109 { AR_RAD2133_SREV_MAJOR, "2133" },
3110 { AR_RAD2122_SREV_MAJOR, "2122" }
3111};
3112
3113/*
3114 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3115 */
f934c4d9 3116static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3117{
3118 int i;
3119
3120 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3121 if (ath_mac_bb_names[i].version == mac_bb_version) {
3122 return ath_mac_bb_names[i].name;
3123 }
3124 }
3125
3126 return "????";
3127}
2da4f01a
LR		 3128
3129/*
3130 * Return the RF name. "????" is returned if the RF is unknown.
3131 * Used for devices with external radios.
3132 */
f934c4d9 3133static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3134{
3135 int i;
3136
3137 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3138 if (ath_rf_names[i].version == rf_version) {
3139 return ath_rf_names[i].name;
3140 }
3141 }
3142
3143 return "????";
3144}
f934c4d9
LR		 3145
3146void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3147{
3148 int used;
3149
3150 /* chipsets >= AR9280 are single-chip */
3151 if (AR_SREV_9280_10_OR_LATER(ah)) {
3152 used = snprintf(hw_name, len,
3153 "Atheros AR%s Rev:%x",
3154 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3155 ah->hw_version.macRev);
3156 }
3157 else {
3158 used = snprintf(hw_name, len,
3159 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3160 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3161 ah->hw_version.macRev,
3162 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3163 AR_RADIO_SREV_MAJOR)),
3164 ah->hw_version.phyRev);
3165 }
3166
3167 hw_name[used] = '\0';
3168}
3169EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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