Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
18 | #include <asm/unaligned.h> | |
19 | ||
af03abec | 20 | #include "hw.h" |
d70357d5 | 21 | #include "hw-ops.h" |
cfe8cba9 | 22 | #include "rc.h" |
f078f209 LR |
23 | #include "initvals.h" |
24 | ||
4febf7b8 LR |
25 | #define ATH9K_CLOCK_RATE_CCK 22 |
26 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 | |
27 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 | |
f078f209 | 28 | |
d70357d5 LR |
29 | static void ar9002_hw_attach_ops(struct ath_hw *ah); |
30 | ||
cbe61d8a | 31 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
f078f209 | 32 | |
7322fd19 LR |
33 | MODULE_AUTHOR("Atheros Communications"); |
34 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
35 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
36 | MODULE_LICENSE("Dual BSD/GPL"); | |
37 | ||
38 | static int __init ath9k_init(void) | |
39 | { | |
40 | return 0; | |
41 | } | |
42 | module_init(ath9k_init); | |
43 | ||
44 | static void __exit ath9k_exit(void) | |
45 | { | |
46 | return; | |
47 | } | |
48 | module_exit(ath9k_exit); | |
49 | ||
d70357d5 LR |
50 | /* Private hardware callbacks */ |
51 | ||
52 | static void ath9k_hw_init_cal_settings(struct ath_hw *ah) | |
53 | { | |
54 | ath9k_hw_private_ops(ah)->init_cal_settings(ah); | |
55 | } | |
56 | ||
57 | static void ath9k_hw_init_mode_regs(struct ath_hw *ah) | |
58 | { | |
59 | ath9k_hw_private_ops(ah)->init_mode_regs(ah); | |
60 | } | |
61 | ||
62 | static bool ath9k_hw_macversion_supported(struct ath_hw *ah) | |
63 | { | |
64 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | |
65 | ||
66 | return priv_ops->macversion_supported(ah->hw_version.macVersion); | |
67 | } | |
68 | ||
f1dc5600 S |
69 | /********************/ |
70 | /* Helper Functions */ | |
71 | /********************/ | |
f078f209 | 72 | |
cbe61d8a | 73 | static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) |
f1dc5600 | 74 | { |
b002a4a9 | 75 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
cbe61d8a | 76 | |
2660b81a | 77 | if (!ah->curchan) /* should really check for CCK instead */ |
4febf7b8 LR |
78 | return usecs *ATH9K_CLOCK_RATE_CCK; |
79 | if (conf->channel->band == IEEE80211_BAND_2GHZ) | |
80 | return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; | |
81 | return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; | |
f1dc5600 S |
82 | } |
83 | ||
cbe61d8a | 84 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
f1dc5600 | 85 | { |
b002a4a9 | 86 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
cbe61d8a | 87 | |
4febf7b8 | 88 | if (conf_is_ht40(conf)) |
f1dc5600 S |
89 | return ath9k_hw_mac_clks(ah, usecs) * 2; |
90 | else | |
91 | return ath9k_hw_mac_clks(ah, usecs); | |
92 | } | |
f078f209 | 93 | |
0caa7b14 | 94 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
f078f209 LR |
95 | { |
96 | int i; | |
97 | ||
0caa7b14 S |
98 | BUG_ON(timeout < AH_TIME_QUANTUM); |
99 | ||
100 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { | |
f078f209 LR |
101 | if ((REG_READ(ah, reg) & mask) == val) |
102 | return true; | |
103 | ||
104 | udelay(AH_TIME_QUANTUM); | |
105 | } | |
04bd4638 | 106 | |
c46917bb LR |
107 | ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, |
108 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", | |
109 | timeout, reg, REG_READ(ah, reg), mask, val); | |
f078f209 | 110 | |
f1dc5600 | 111 | return false; |
f078f209 | 112 | } |
7322fd19 | 113 | EXPORT_SYMBOL(ath9k_hw_wait); |
f078f209 LR |
114 | |
115 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) | |
116 | { | |
117 | u32 retval; | |
118 | int i; | |
119 | ||
120 | for (i = 0, retval = 0; i < n; i++) { | |
121 | retval = (retval << 1) | (val & 1); | |
122 | val >>= 1; | |
123 | } | |
124 | return retval; | |
125 | } | |
126 | ||
cbe61d8a | 127 | bool ath9k_get_channel_edges(struct ath_hw *ah, |
f1dc5600 S |
128 | u16 flags, u16 *low, |
129 | u16 *high) | |
f078f209 | 130 | { |
2660b81a | 131 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 | 132 | |
f1dc5600 S |
133 | if (flags & CHANNEL_5GHZ) { |
134 | *low = pCap->low_5ghz_chan; | |
135 | *high = pCap->high_5ghz_chan; | |
136 | return true; | |
f078f209 | 137 | } |
f1dc5600 S |
138 | if ((flags & CHANNEL_2GHZ)) { |
139 | *low = pCap->low_2ghz_chan; | |
140 | *high = pCap->high_2ghz_chan; | |
141 | return true; | |
142 | } | |
143 | return false; | |
f078f209 LR |
144 | } |
145 | ||
cbe61d8a | 146 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 147 | u8 phy, int kbps, |
f1dc5600 S |
148 | u32 frameLen, u16 rateix, |
149 | bool shortPreamble) | |
f078f209 | 150 | { |
f1dc5600 | 151 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
f078f209 | 152 | |
f1dc5600 S |
153 | if (kbps == 0) |
154 | return 0; | |
f078f209 | 155 | |
545750d3 | 156 | switch (phy) { |
46d14a58 | 157 | case WLAN_RC_PHY_CCK: |
f1dc5600 | 158 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
545750d3 | 159 | if (shortPreamble) |
f1dc5600 S |
160 | phyTime >>= 1; |
161 | numBits = frameLen << 3; | |
162 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); | |
163 | break; | |
46d14a58 | 164 | case WLAN_RC_PHY_OFDM: |
2660b81a | 165 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
f1dc5600 S |
166 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
167 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
168 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
169 | txTime = OFDM_SIFS_TIME_QUARTER | |
170 | + OFDM_PREAMBLE_TIME_QUARTER | |
171 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); | |
2660b81a S |
172 | } else if (ah->curchan && |
173 | IS_CHAN_HALF_RATE(ah->curchan)) { | |
f1dc5600 S |
174 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
175 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
176 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
177 | txTime = OFDM_SIFS_TIME_HALF + | |
178 | OFDM_PREAMBLE_TIME_HALF | |
179 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); | |
180 | } else { | |
181 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; | |
182 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
183 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
184 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME | |
185 | + (numSymbols * OFDM_SYMBOL_TIME); | |
186 | } | |
187 | break; | |
188 | default: | |
c46917bb | 189 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
545750d3 | 190 | "Unknown phy %u (rate ix %u)\n", phy, rateix); |
f1dc5600 S |
191 | txTime = 0; |
192 | break; | |
193 | } | |
f078f209 | 194 | |
f1dc5600 S |
195 | return txTime; |
196 | } | |
7322fd19 | 197 | EXPORT_SYMBOL(ath9k_hw_computetxtime); |
f078f209 | 198 | |
cbe61d8a | 199 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
f1dc5600 S |
200 | struct ath9k_channel *chan, |
201 | struct chan_centers *centers) | |
f078f209 | 202 | { |
f1dc5600 | 203 | int8_t extoff; |
f078f209 | 204 | |
f1dc5600 S |
205 | if (!IS_CHAN_HT40(chan)) { |
206 | centers->ctl_center = centers->ext_center = | |
207 | centers->synth_center = chan->channel; | |
208 | return; | |
f078f209 | 209 | } |
f078f209 | 210 | |
f1dc5600 S |
211 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
212 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { | |
213 | centers->synth_center = | |
214 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; | |
215 | extoff = 1; | |
216 | } else { | |
217 | centers->synth_center = | |
218 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; | |
219 | extoff = -1; | |
220 | } | |
f078f209 | 221 | |
f1dc5600 S |
222 | centers->ctl_center = |
223 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); | |
6420014c | 224 | /* 25 MHz spacing is supported by hw but not on upper layers */ |
f1dc5600 | 225 | centers->ext_center = |
6420014c | 226 | centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); |
f078f209 LR |
227 | } |
228 | ||
f1dc5600 S |
229 | /******************/ |
230 | /* Chip Revisions */ | |
231 | /******************/ | |
232 | ||
cbe61d8a | 233 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
f078f209 | 234 | { |
f1dc5600 | 235 | u32 val; |
f078f209 | 236 | |
f1dc5600 | 237 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
f078f209 | 238 | |
f1dc5600 S |
239 | if (val == 0xFF) { |
240 | val = REG_READ(ah, AR_SREV); | |
d535a42a S |
241 | ah->hw_version.macVersion = |
242 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; | |
243 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | |
2660b81a | 244 | ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; |
f1dc5600 S |
245 | } else { |
246 | if (!AR_SREV_9100(ah)) | |
d535a42a | 247 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
f078f209 | 248 | |
d535a42a | 249 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
f078f209 | 250 | |
d535a42a | 251 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
2660b81a | 252 | ah->is_pciexpress = true; |
f1dc5600 | 253 | } |
f078f209 LR |
254 | } |
255 | ||
cbe61d8a | 256 | static int ath9k_hw_get_radiorev(struct ath_hw *ah) |
f078f209 | 257 | { |
f1dc5600 S |
258 | u32 val; |
259 | int i; | |
f078f209 | 260 | |
f1dc5600 | 261 | REG_WRITE(ah, AR_PHY(0x36), 0x00007058); |
f078f209 | 262 | |
f1dc5600 S |
263 | for (i = 0; i < 8; i++) |
264 | REG_WRITE(ah, AR_PHY(0x20), 0x00010000); | |
265 | val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; | |
266 | val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); | |
f078f209 | 267 | |
f1dc5600 | 268 | return ath9k_hw_reverse_bits(val, 8); |
f078f209 LR |
269 | } |
270 | ||
f1dc5600 S |
271 | /************************************/ |
272 | /* HW Attach, Detach, Init Routines */ | |
273 | /************************************/ | |
274 | ||
cbe61d8a | 275 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
f078f209 | 276 | { |
feed029c | 277 | if (AR_SREV_9100(ah)) |
f1dc5600 | 278 | return; |
f078f209 | 279 | |
f1dc5600 S |
280 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
281 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
282 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); | |
283 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); | |
284 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); | |
285 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); | |
286 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | |
287 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
288 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); | |
f078f209 | 289 | |
f1dc5600 | 290 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
f078f209 LR |
291 | } |
292 | ||
cbe61d8a | 293 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
f078f209 | 294 | { |
c46917bb | 295 | struct ath_common *common = ath9k_hw_common(ah); |
f1dc5600 S |
296 | u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; |
297 | u32 regHold[2]; | |
298 | u32 patternData[4] = { 0x55555555, | |
299 | 0xaaaaaaaa, | |
300 | 0x66666666, | |
301 | 0x99999999 }; | |
302 | int i, j; | |
f078f209 | 303 | |
f1dc5600 S |
304 | for (i = 0; i < 2; i++) { |
305 | u32 addr = regAddr[i]; | |
306 | u32 wrData, rdData; | |
f078f209 | 307 | |
f1dc5600 S |
308 | regHold[i] = REG_READ(ah, addr); |
309 | for (j = 0; j < 0x100; j++) { | |
310 | wrData = (j << 16) | j; | |
311 | REG_WRITE(ah, addr, wrData); | |
312 | rdData = REG_READ(ah, addr); | |
313 | if (rdData != wrData) { | |
c46917bb LR |
314 | ath_print(common, ATH_DBG_FATAL, |
315 | "address test failed " | |
316 | "addr: 0x%08x - wr:0x%08x != " | |
317 | "rd:0x%08x\n", | |
318 | addr, wrData, rdData); | |
f1dc5600 S |
319 | return false; |
320 | } | |
321 | } | |
322 | for (j = 0; j < 4; j++) { | |
323 | wrData = patternData[j]; | |
324 | REG_WRITE(ah, addr, wrData); | |
325 | rdData = REG_READ(ah, addr); | |
326 | if (wrData != rdData) { | |
c46917bb LR |
327 | ath_print(common, ATH_DBG_FATAL, |
328 | "address test failed " | |
329 | "addr: 0x%08x - wr:0x%08x != " | |
330 | "rd:0x%08x\n", | |
331 | addr, wrData, rdData); | |
f1dc5600 S |
332 | return false; |
333 | } | |
f078f209 | 334 | } |
f1dc5600 | 335 | REG_WRITE(ah, regAddr[i], regHold[i]); |
f078f209 | 336 | } |
f1dc5600 | 337 | udelay(100); |
cbe61d8a | 338 | |
f078f209 LR |
339 | return true; |
340 | } | |
341 | ||
b8b0f377 | 342 | static void ath9k_hw_init_config(struct ath_hw *ah) |
f1dc5600 S |
343 | { |
344 | int i; | |
f078f209 | 345 | |
2660b81a S |
346 | ah->config.dma_beacon_response_time = 2; |
347 | ah->config.sw_beacon_response_time = 10; | |
348 | ah->config.additional_swba_backoff = 0; | |
349 | ah->config.ack_6mb = 0x0; | |
350 | ah->config.cwm_ignore_extcca = 0; | |
351 | ah->config.pcie_powersave_enable = 0; | |
2660b81a | 352 | ah->config.pcie_clock_req = 0; |
2660b81a S |
353 | ah->config.pcie_waen = 0; |
354 | ah->config.analog_shiftreg = 1; | |
2660b81a S |
355 | ah->config.ofdm_trig_low = 200; |
356 | ah->config.ofdm_trig_high = 500; | |
357 | ah->config.cck_trig_high = 200; | |
358 | ah->config.cck_trig_low = 100; | |
359 | ah->config.enable_ani = 1; | |
f078f209 | 360 | |
f1dc5600 | 361 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
2660b81a S |
362 | ah->config.spurchans[i][0] = AR_NO_SPUR; |
363 | ah->config.spurchans[i][1] = AR_NO_SPUR; | |
f078f209 LR |
364 | } |
365 | ||
5ffaf8a3 LR |
366 | if (ah->hw_version.devid != AR2427_DEVID_PCIE) |
367 | ah->config.ht_enable = 1; | |
368 | else | |
369 | ah->config.ht_enable = 0; | |
370 | ||
0ce024cb | 371 | ah->config.rx_intr_mitigation = true; |
6158425b LR |
372 | |
373 | /* | |
374 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) | |
375 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). | |
376 | * This means we use it for all AR5416 devices, and the few | |
377 | * minor PCI AR9280 devices out there. | |
378 | * | |
379 | * Serialization is required because these devices do not handle | |
380 | * well the case of two concurrent reads/writes due to the latency | |
381 | * involved. During one read/write another read/write can be issued | |
382 | * on another CPU while the previous read/write may still be working | |
383 | * on our hardware, if we hit this case the hardware poops in a loop. | |
384 | * We prevent this by serializing reads and writes. | |
385 | * | |
386 | * This issue is not present on PCI-Express devices or pre-AR5416 | |
387 | * devices (legacy, 802.11abg). | |
388 | */ | |
389 | if (num_possible_cpus() > 1) | |
2d6a5e95 | 390 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
f078f209 LR |
391 | } |
392 | ||
50aca25b | 393 | static void ath9k_hw_init_defaults(struct ath_hw *ah) |
f078f209 | 394 | { |
608b88cb LR |
395 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
396 | ||
397 | regulatory->country_code = CTRY_DEFAULT; | |
398 | regulatory->power_limit = MAX_RATE_POWER; | |
399 | regulatory->tp_scale = ATH9K_TP_SCALE_MAX; | |
400 | ||
d535a42a | 401 | ah->hw_version.magic = AR5416_MAGIC; |
d535a42a | 402 | ah->hw_version.subvendorid = 0; |
f078f209 LR |
403 | |
404 | ah->ah_flags = 0; | |
8df5d1b7 | 405 | if (ah->hw_version.devid == AR5416_AR9100_DEVID) |
d535a42a | 406 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; |
f078f209 LR |
407 | if (!AR_SREV_9100(ah)) |
408 | ah->ah_flags = AH_USE_EEPROM; | |
409 | ||
2660b81a | 410 | ah->atim_window = 0; |
2660b81a S |
411 | ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; |
412 | ah->beacon_interval = 100; | |
413 | ah->enable_32kHz_clock = DONT_USE_32KHZ; | |
414 | ah->slottime = (u32) -1; | |
2660b81a | 415 | ah->globaltxtimeout = (u32) -1; |
cbdec975 | 416 | ah->power_mode = ATH9K_PM_UNDEFINED; |
f078f209 LR |
417 | } |
418 | ||
cbe61d8a | 419 | static int ath9k_hw_rf_claim(struct ath_hw *ah) |
f078f209 | 420 | { |
f1dc5600 S |
421 | u32 val; |
422 | ||
423 | REG_WRITE(ah, AR_PHY(0), 0x00000007); | |
424 | ||
425 | val = ath9k_hw_get_radiorev(ah); | |
426 | switch (val & AR_RADIO_SREV_MAJOR) { | |
427 | case 0: | |
428 | val = AR_RAD5133_SREV_MAJOR; | |
429 | break; | |
430 | case AR_RAD5133_SREV_MAJOR: | |
431 | case AR_RAD5122_SREV_MAJOR: | |
432 | case AR_RAD2133_SREV_MAJOR: | |
433 | case AR_RAD2122_SREV_MAJOR: | |
434 | break; | |
f078f209 | 435 | default: |
c46917bb LR |
436 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
437 | "Radio Chip Rev 0x%02X not supported\n", | |
438 | val & AR_RADIO_SREV_MAJOR); | |
f1dc5600 | 439 | return -EOPNOTSUPP; |
f078f209 | 440 | } |
f078f209 | 441 | |
d535a42a | 442 | ah->hw_version.analog5GhzRev = val; |
f078f209 | 443 | |
f1dc5600 | 444 | return 0; |
f078f209 LR |
445 | } |
446 | ||
cbe61d8a | 447 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
f078f209 | 448 | { |
1510718d | 449 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
450 | u32 sum; |
451 | int i; | |
452 | u16 eeval; | |
f078f209 LR |
453 | |
454 | sum = 0; | |
455 | for (i = 0; i < 3; i++) { | |
f74df6fb | 456 | eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); |
f078f209 | 457 | sum += eeval; |
1510718d LR |
458 | common->macaddr[2 * i] = eeval >> 8; |
459 | common->macaddr[2 * i + 1] = eeval & 0xff; | |
f078f209 | 460 | } |
d8baa939 | 461 | if (sum == 0 || sum == 0xffff * 3) |
f078f209 | 462 | return -EADDRNOTAVAIL; |
f078f209 LR |
463 | |
464 | return 0; | |
465 | } | |
466 | ||
cbe61d8a | 467 | static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) |
9f804202 SB |
468 | { |
469 | u32 rxgain_type; | |
9f804202 | 470 | |
f74df6fb S |
471 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { |
472 | rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); | |
9f804202 SB |
473 | |
474 | if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) | |
2660b81a | 475 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
9f804202 SB |
476 | ar9280Modes_backoff_13db_rxgain_9280_2, |
477 | ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); | |
478 | else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) | |
2660b81a | 479 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
9f804202 SB |
480 | ar9280Modes_backoff_23db_rxgain_9280_2, |
481 | ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); | |
482 | else | |
2660b81a | 483 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
9f804202 SB |
484 | ar9280Modes_original_rxgain_9280_2, |
485 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); | |
cbe61d8a | 486 | } else { |
2660b81a | 487 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
9f804202 SB |
488 | ar9280Modes_original_rxgain_9280_2, |
489 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); | |
cbe61d8a | 490 | } |
9f804202 SB |
491 | } |
492 | ||
cbe61d8a | 493 | static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) |
9f804202 SB |
494 | { |
495 | u32 txgain_type; | |
9f804202 | 496 | |
f74df6fb S |
497 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { |
498 | txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); | |
9f804202 SB |
499 | |
500 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) | |
2660b81a | 501 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
9f804202 SB |
502 | ar9280Modes_high_power_tx_gain_9280_2, |
503 | ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); | |
504 | else | |
2660b81a | 505 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
9f804202 SB |
506 | ar9280Modes_original_tx_gain_9280_2, |
507 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); | |
cbe61d8a | 508 | } else { |
2660b81a | 509 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
9f804202 SB |
510 | ar9280Modes_original_tx_gain_9280_2, |
511 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); | |
cbe61d8a | 512 | } |
9f804202 SB |
513 | } |
514 | ||
f637cfd6 | 515 | static int ath9k_hw_post_init(struct ath_hw *ah) |
f078f209 | 516 | { |
f1dc5600 | 517 | int ecode; |
f078f209 | 518 | |
527d485f S |
519 | if (!AR_SREV_9271(ah)) { |
520 | if (!ath9k_hw_chip_test(ah)) | |
521 | return -ENODEV; | |
522 | } | |
f078f209 | 523 | |
f1dc5600 S |
524 | ecode = ath9k_hw_rf_claim(ah); |
525 | if (ecode != 0) | |
f078f209 | 526 | return ecode; |
f078f209 | 527 | |
f637cfd6 | 528 | ecode = ath9k_hw_eeprom_init(ah); |
f1dc5600 S |
529 | if (ecode != 0) |
530 | return ecode; | |
7d01b221 | 531 | |
c46917bb LR |
532 | ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, |
533 | "Eeprom VER: %d, REV: %d\n", | |
534 | ah->eep_ops->get_eeprom_ver(ah), | |
535 | ah->eep_ops->get_eeprom_rev(ah)); | |
7d01b221 | 536 | |
8fe65368 LR |
537 | ecode = ath9k_hw_rf_alloc_ext_banks(ah); |
538 | if (ecode) { | |
539 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, | |
540 | "Failed allocating banks for " | |
541 | "external radio\n"); | |
542 | return ecode; | |
574d6b12 | 543 | } |
f078f209 | 544 | |
f1dc5600 S |
545 | if (!AR_SREV_9100(ah)) { |
546 | ath9k_hw_ani_setup(ah); | |
f637cfd6 | 547 | ath9k_hw_ani_init(ah); |
f078f209 LR |
548 | } |
549 | ||
f078f209 LR |
550 | return 0; |
551 | } | |
552 | ||
d70357d5 | 553 | static bool ar9002_hw_macversion_supported(u32 macversion) |
f9d4a668 LR |
554 | { |
555 | switch (macversion) { | |
556 | case AR_SREV_VERSION_5416_PCI: | |
557 | case AR_SREV_VERSION_5416_PCIE: | |
558 | case AR_SREV_VERSION_9160: | |
559 | case AR_SREV_VERSION_9100: | |
560 | case AR_SREV_VERSION_9280: | |
561 | case AR_SREV_VERSION_9285: | |
562 | case AR_SREV_VERSION_9287: | |
d7e7d229 | 563 | case AR_SREV_VERSION_9271: |
7976b426 | 564 | return true; |
f9d4a668 LR |
565 | default: |
566 | break; | |
567 | } | |
568 | return false; | |
569 | } | |
570 | ||
d70357d5 | 571 | static void ar9002_hw_init_cal_settings(struct ath_hw *ah) |
f078f209 | 572 | { |
f1dc5600 S |
573 | if (AR_SREV_9160_10_OR_LATER(ah)) { |
574 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
2660b81a S |
575 | ah->iq_caldata.calData = &iq_cal_single_sample; |
576 | ah->adcgain_caldata.calData = | |
f1dc5600 | 577 | &adc_gain_cal_single_sample; |
2660b81a | 578 | ah->adcdc_caldata.calData = |
f1dc5600 | 579 | &adc_dc_cal_single_sample; |
2660b81a | 580 | ah->adcdc_calinitdata.calData = |
f1dc5600 S |
581 | &adc_init_dc_cal; |
582 | } else { | |
2660b81a S |
583 | ah->iq_caldata.calData = &iq_cal_multi_sample; |
584 | ah->adcgain_caldata.calData = | |
f1dc5600 | 585 | &adc_gain_cal_multi_sample; |
2660b81a | 586 | ah->adcdc_caldata.calData = |
f1dc5600 | 587 | &adc_dc_cal_multi_sample; |
2660b81a | 588 | ah->adcdc_calinitdata.calData = |
f1dc5600 S |
589 | &adc_init_dc_cal; |
590 | } | |
2660b81a | 591 | ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; |
f1dc5600 | 592 | } |
aa4058ae | 593 | } |
f078f209 | 594 | |
d70357d5 | 595 | static void ar9002_hw_init_mode_regs(struct ath_hw *ah) |
aa4058ae | 596 | { |
d7e7d229 | 597 | if (AR_SREV_9271(ah)) { |
8564328d LR |
598 | INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, |
599 | ARRAY_SIZE(ar9271Modes_9271), 6); | |
600 | INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, | |
601 | ARRAY_SIZE(ar9271Common_9271), 2); | |
70807e99 S |
602 | INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271, |
603 | ar9271Common_normal_cck_fir_coeff_9271, | |
604 | ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2); | |
605 | INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271, | |
606 | ar9271Common_japan_2484_cck_fir_coeff_9271, | |
607 | ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2); | |
8564328d LR |
608 | INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, |
609 | ar9271Modes_9271_1_0_only, | |
610 | ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6); | |
70807e99 S |
611 | INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg, |
612 | ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6); | |
613 | INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271, | |
614 | ar9271Modes_high_power_tx_gain_9271, | |
615 | ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6); | |
616 | INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, | |
617 | ar9271Modes_normal_power_tx_gain_9271, | |
618 | ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6); | |
d7e7d229 LR |
619 | return; |
620 | } | |
621 | ||
ac88b6ec VN |
622 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
623 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, | |
624 | ARRAY_SIZE(ar9287Modes_9287_1_1), 6); | |
625 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, | |
626 | ARRAY_SIZE(ar9287Common_9287_1_1), 2); | |
627 | if (ah->config.pcie_clock_req) | |
628 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
629 | ar9287PciePhy_clkreq_off_L1_9287_1_1, | |
630 | ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2); | |
631 | else | |
632 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
633 | ar9287PciePhy_clkreq_always_on_L1_9287_1_1, | |
634 | ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1), | |
635 | 2); | |
636 | } else if (AR_SREV_9287_10_OR_LATER(ah)) { | |
637 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0, | |
638 | ARRAY_SIZE(ar9287Modes_9287_1_0), 6); | |
639 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0, | |
640 | ARRAY_SIZE(ar9287Common_9287_1_0), 2); | |
641 | ||
642 | if (ah->config.pcie_clock_req) | |
643 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
644 | ar9287PciePhy_clkreq_off_L1_9287_1_0, | |
645 | ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2); | |
646 | else | |
647 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
648 | ar9287PciePhy_clkreq_always_on_L1_9287_1_0, | |
649 | ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0), | |
650 | 2); | |
651 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { | |
f078f209 | 652 | |
4e845168 | 653 | |
2660b81a | 654 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, |
e7594072 | 655 | ARRAY_SIZE(ar9285Modes_9285_1_2), 6); |
2660b81a | 656 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, |
e7594072 SB |
657 | ARRAY_SIZE(ar9285Common_9285_1_2), 2); |
658 | ||
2660b81a S |
659 | if (ah->config.pcie_clock_req) { |
660 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
e7594072 SB |
661 | ar9285PciePhy_clkreq_off_L1_9285_1_2, |
662 | ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); | |
663 | } else { | |
2660b81a | 664 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
e7594072 SB |
665 | ar9285PciePhy_clkreq_always_on_L1_9285_1_2, |
666 | ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), | |
667 | 2); | |
668 | } | |
669 | } else if (AR_SREV_9285_10_OR_LATER(ah)) { | |
2660b81a | 670 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285, |
e7594072 | 671 | ARRAY_SIZE(ar9285Modes_9285), 6); |
2660b81a | 672 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285, |
e7594072 SB |
673 | ARRAY_SIZE(ar9285Common_9285), 2); |
674 | ||
2660b81a S |
675 | if (ah->config.pcie_clock_req) { |
676 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
e7594072 SB |
677 | ar9285PciePhy_clkreq_off_L1_9285, |
678 | ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); | |
679 | } else { | |
2660b81a | 680 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
e7594072 SB |
681 | ar9285PciePhy_clkreq_always_on_L1_9285, |
682 | ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); | |
683 | } | |
684 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { | |
2660b81a | 685 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, |
f1dc5600 | 686 | ARRAY_SIZE(ar9280Modes_9280_2), 6); |
2660b81a | 687 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, |
f1dc5600 | 688 | ARRAY_SIZE(ar9280Common_9280_2), 2); |
f078f209 | 689 | |
2660b81a S |
690 | if (ah->config.pcie_clock_req) { |
691 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
f1dc5600 S |
692 | ar9280PciePhy_clkreq_off_L1_9280, |
693 | ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); | |
694 | } else { | |
2660b81a | 695 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
f1dc5600 S |
696 | ar9280PciePhy_clkreq_always_on_L1_9280, |
697 | ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); | |
698 | } | |
2660b81a | 699 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
f1dc5600 S |
700 | ar9280Modes_fast_clock_9280_2, |
701 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); | |
702 | } else if (AR_SREV_9280_10_OR_LATER(ah)) { | |
2660b81a | 703 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280, |
f1dc5600 | 704 | ARRAY_SIZE(ar9280Modes_9280), 6); |
2660b81a | 705 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280, |
f1dc5600 S |
706 | ARRAY_SIZE(ar9280Common_9280), 2); |
707 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | |
2660b81a | 708 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, |
f1dc5600 | 709 | ARRAY_SIZE(ar5416Modes_9160), 6); |
2660b81a | 710 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, |
f1dc5600 | 711 | ARRAY_SIZE(ar5416Common_9160), 2); |
2660b81a | 712 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, |
f1dc5600 | 713 | ARRAY_SIZE(ar5416Bank0_9160), 2); |
2660b81a | 714 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, |
f1dc5600 | 715 | ARRAY_SIZE(ar5416BB_RfGain_9160), 3); |
2660b81a | 716 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, |
f1dc5600 | 717 | ARRAY_SIZE(ar5416Bank1_9160), 2); |
2660b81a | 718 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, |
f1dc5600 | 719 | ARRAY_SIZE(ar5416Bank2_9160), 2); |
2660b81a | 720 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, |
f1dc5600 | 721 | ARRAY_SIZE(ar5416Bank3_9160), 3); |
2660b81a | 722 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, |
f1dc5600 | 723 | ARRAY_SIZE(ar5416Bank6_9160), 3); |
2660b81a | 724 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, |
f1dc5600 | 725 | ARRAY_SIZE(ar5416Bank6TPC_9160), 3); |
2660b81a | 726 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, |
f1dc5600 S |
727 | ARRAY_SIZE(ar5416Bank7_9160), 2); |
728 | if (AR_SREV_9160_11(ah)) { | |
2660b81a | 729 | INIT_INI_ARRAY(&ah->iniAddac, |
f1dc5600 S |
730 | ar5416Addac_91601_1, |
731 | ARRAY_SIZE(ar5416Addac_91601_1), 2); | |
732 | } else { | |
2660b81a | 733 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, |
f1dc5600 S |
734 | ARRAY_SIZE(ar5416Addac_9160), 2); |
735 | } | |
736 | } else if (AR_SREV_9100_OR_LATER(ah)) { | |
2660b81a | 737 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, |
f1dc5600 | 738 | ARRAY_SIZE(ar5416Modes_9100), 6); |
2660b81a | 739 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, |
f1dc5600 | 740 | ARRAY_SIZE(ar5416Common_9100), 2); |
2660b81a | 741 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, |
f1dc5600 | 742 | ARRAY_SIZE(ar5416Bank0_9100), 2); |
2660b81a | 743 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, |
f1dc5600 | 744 | ARRAY_SIZE(ar5416BB_RfGain_9100), 3); |
2660b81a | 745 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, |
f1dc5600 | 746 | ARRAY_SIZE(ar5416Bank1_9100), 2); |
2660b81a | 747 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, |
f1dc5600 | 748 | ARRAY_SIZE(ar5416Bank2_9100), 2); |
2660b81a | 749 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, |
f1dc5600 | 750 | ARRAY_SIZE(ar5416Bank3_9100), 3); |
2660b81a | 751 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, |
f1dc5600 | 752 | ARRAY_SIZE(ar5416Bank6_9100), 3); |
2660b81a | 753 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, |
f1dc5600 | 754 | ARRAY_SIZE(ar5416Bank6TPC_9100), 3); |
2660b81a | 755 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, |
f1dc5600 | 756 | ARRAY_SIZE(ar5416Bank7_9100), 2); |
2660b81a | 757 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, |
f1dc5600 S |
758 | ARRAY_SIZE(ar5416Addac_9100), 2); |
759 | } else { | |
2660b81a | 760 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, |
f1dc5600 | 761 | ARRAY_SIZE(ar5416Modes), 6); |
2660b81a | 762 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, |
f1dc5600 | 763 | ARRAY_SIZE(ar5416Common), 2); |
2660b81a | 764 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, |
f1dc5600 | 765 | ARRAY_SIZE(ar5416Bank0), 2); |
2660b81a | 766 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, |
f1dc5600 | 767 | ARRAY_SIZE(ar5416BB_RfGain), 3); |
2660b81a | 768 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, |
f1dc5600 | 769 | ARRAY_SIZE(ar5416Bank1), 2); |
2660b81a | 770 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, |
f1dc5600 | 771 | ARRAY_SIZE(ar5416Bank2), 2); |
2660b81a | 772 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, |
f1dc5600 | 773 | ARRAY_SIZE(ar5416Bank3), 3); |
2660b81a | 774 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, |
f1dc5600 | 775 | ARRAY_SIZE(ar5416Bank6), 3); |
2660b81a | 776 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, |
f1dc5600 | 777 | ARRAY_SIZE(ar5416Bank6TPC), 3); |
2660b81a | 778 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, |
f1dc5600 | 779 | ARRAY_SIZE(ar5416Bank7), 2); |
2660b81a | 780 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, |
f1dc5600 | 781 | ARRAY_SIZE(ar5416Addac), 2); |
f078f209 | 782 | } |
aa4058ae | 783 | } |
f078f209 | 784 | |
aa4058ae LR |
785 | static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) |
786 | { | |
b37fa870 | 787 | if (AR_SREV_9287_11_OR_LATER(ah)) |
ac88b6ec VN |
788 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
789 | ar9287Modes_rx_gain_9287_1_1, | |
790 | ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6); | |
791 | else if (AR_SREV_9287_10(ah)) | |
792 | INIT_INI_ARRAY(&ah->iniModesRxGain, | |
793 | ar9287Modes_rx_gain_9287_1_0, | |
794 | ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6); | |
795 | else if (AR_SREV_9280_20(ah)) | |
796 | ath9k_hw_init_rxgain_ini(ah); | |
797 | ||
b37fa870 | 798 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
ac88b6ec VN |
799 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
800 | ar9287Modes_tx_gain_9287_1_1, | |
801 | ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6); | |
802 | } else if (AR_SREV_9287_10(ah)) { | |
803 | INIT_INI_ARRAY(&ah->iniModesTxGain, | |
804 | ar9287Modes_tx_gain_9287_1_0, | |
805 | ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6); | |
806 | } else if (AR_SREV_9280_20(ah)) { | |
807 | ath9k_hw_init_txgain_ini(ah); | |
808 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { | |
4e845168 SB |
809 | u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); |
810 | ||
811 | /* txgain table */ | |
812 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { | |
53bc7aa0 VN |
813 | if (AR_SREV_9285E_20(ah)) { |
814 | INIT_INI_ARRAY(&ah->iniModesTxGain, | |
815 | ar9285Modes_XE2_0_high_power, | |
816 | ARRAY_SIZE( | |
817 | ar9285Modes_XE2_0_high_power), 6); | |
818 | } else { | |
819 | INIT_INI_ARRAY(&ah->iniModesTxGain, | |
820 | ar9285Modes_high_power_tx_gain_9285_1_2, | |
821 | ARRAY_SIZE( | |
822 | ar9285Modes_high_power_tx_gain_9285_1_2), 6); | |
823 | } | |
4e845168 | 824 | } else { |
53bc7aa0 VN |
825 | if (AR_SREV_9285E_20(ah)) { |
826 | INIT_INI_ARRAY(&ah->iniModesTxGain, | |
827 | ar9285Modes_XE2_0_normal_power, | |
828 | ARRAY_SIZE( | |
829 | ar9285Modes_XE2_0_normal_power), 6); | |
830 | } else { | |
831 | INIT_INI_ARRAY(&ah->iniModesTxGain, | |
832 | ar9285Modes_original_tx_gain_9285_1_2, | |
833 | ARRAY_SIZE( | |
834 | ar9285Modes_original_tx_gain_9285_1_2), 6); | |
835 | } | |
4e845168 | 836 | } |
4e845168 | 837 | } |
aa4058ae | 838 | } |
4e845168 | 839 | |
aa8bc9ef | 840 | static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah) |
aa4058ae | 841 | { |
2eb46d9b PR |
842 | struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader); |
843 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 844 | |
2eb46d9b PR |
845 | ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) && |
846 | (ah->eep_map != EEP_MAP_4KBITS) && | |
847 | ((pBase->version & 0xff) > 0x0a) && | |
848 | (pBase->pwdclkind == 0); | |
f078f209 | 849 | |
2eb46d9b PR |
850 | if (ah->need_an_top2_fixup) |
851 | ath_print(common, ATH_DBG_EEPROM, | |
852 | "needs fixup for AR_AN_TOP2 register\n"); | |
aa4058ae LR |
853 | } |
854 | ||
d70357d5 LR |
855 | /* Called for all hardware families */ |
856 | static int __ath9k_hw_init(struct ath_hw *ah) | |
aa4058ae | 857 | { |
c46917bb | 858 | struct ath_common *common = ath9k_hw_common(ah); |
95fafca2 | 859 | int r = 0; |
aa4058ae | 860 | |
aa4058ae LR |
861 | ath9k_hw_init_defaults(ah); |
862 | ath9k_hw_init_config(ah); | |
863 | ||
864 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { | |
c46917bb LR |
865 | ath_print(common, ATH_DBG_FATAL, |
866 | "Couldn't reset chip\n"); | |
95fafca2 | 867 | return -EIO; |
aa4058ae LR |
868 | } |
869 | ||
d70357d5 LR |
870 | ar9002_hw_attach_ops(ah); |
871 | ||
9ecdef4b | 872 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
c46917bb | 873 | ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); |
95fafca2 | 874 | return -EIO; |
aa4058ae LR |
875 | } |
876 | ||
877 | if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { | |
878 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || | |
879 | (AR_SREV_9280(ah) && !ah->is_pciexpress)) { | |
880 | ah->config.serialize_regmode = | |
881 | SER_REG_MODE_ON; | |
882 | } else { | |
883 | ah->config.serialize_regmode = | |
884 | SER_REG_MODE_OFF; | |
885 | } | |
886 | } | |
887 | ||
c46917bb | 888 | ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", |
aa4058ae LR |
889 | ah->config.serialize_regmode); |
890 | ||
f4709fdf LR |
891 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
892 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; | |
893 | else | |
894 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; | |
895 | ||
d70357d5 | 896 | if (!ath9k_hw_macversion_supported(ah)) { |
c46917bb LR |
897 | ath_print(common, ATH_DBG_FATAL, |
898 | "Mac Chip Rev 0x%02x.%x is not supported by " | |
899 | "this driver\n", ah->hw_version.macVersion, | |
900 | ah->hw_version.macRev); | |
95fafca2 | 901 | return -EOPNOTSUPP; |
aa4058ae LR |
902 | } |
903 | ||
904 | if (AR_SREV_9100(ah)) { | |
905 | ah->iq_caldata.calData = &iq_cal_multi_sample; | |
906 | ah->supp_cals = IQ_MISMATCH_CAL; | |
907 | ah->is_pciexpress = false; | |
908 | } | |
d7e7d229 LR |
909 | |
910 | if (AR_SREV_9271(ah)) | |
911 | ah->is_pciexpress = false; | |
912 | ||
aa4058ae | 913 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
aa4058ae LR |
914 | ath9k_hw_init_cal_settings(ah); |
915 | ||
916 | ah->ani_function = ATH9K_ANI_ALL; | |
8fe65368 | 917 | if (AR_SREV_9280_10_OR_LATER(ah)) |
aa4058ae LR |
918 | ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; |
919 | ||
920 | ath9k_hw_init_mode_regs(ah); | |
921 | ||
922 | if (ah->is_pciexpress) | |
93b1b37f | 923 | ath9k_hw_configpcipowersave(ah, 0, 0); |
aa4058ae LR |
924 | else |
925 | ath9k_hw_disablepcie(ah); | |
926 | ||
193cd458 S |
927 | /* Support for Japan ch.14 (2484) spread */ |
928 | if (AR_SREV_9287_11_OR_LATER(ah)) { | |
929 | INIT_INI_ARRAY(&ah->iniCckfirNormal, | |
930 | ar9287Common_normal_cck_fir_coeff_92871_1, | |
931 | ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2); | |
932 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, | |
933 | ar9287Common_japan_2484_cck_fir_coeff_92871_1, | |
934 | ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2); | |
935 | } | |
936 | ||
f637cfd6 | 937 | r = ath9k_hw_post_init(ah); |
aa4058ae | 938 | if (r) |
95fafca2 | 939 | return r; |
aa4058ae LR |
940 | |
941 | ath9k_hw_init_mode_gain_regs(ah); | |
a9a29ce6 GJ |
942 | r = ath9k_hw_fill_cap_info(ah); |
943 | if (r) | |
944 | return r; | |
945 | ||
aa8bc9ef | 946 | ath9k_hw_init_eeprom_fix(ah); |
f6688cd8 | 947 | |
4f3acf81 LR |
948 | r = ath9k_hw_init_macaddr(ah); |
949 | if (r) { | |
c46917bb LR |
950 | ath_print(common, ATH_DBG_FATAL, |
951 | "Failed to initialize MAC address\n"); | |
95fafca2 | 952 | return r; |
f078f209 LR |
953 | } |
954 | ||
d7e7d229 | 955 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
2660b81a | 956 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); |
f1dc5600 | 957 | else |
2660b81a | 958 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); |
f078f209 | 959 | |
f1dc5600 | 960 | ath9k_init_nfcal_hist_buffer(ah); |
f078f209 | 961 | |
211f5859 LR |
962 | common->state = ATH_HW_INITIALIZED; |
963 | ||
4f3acf81 | 964 | return 0; |
f078f209 LR |
965 | } |
966 | ||
d70357d5 LR |
967 | int ath9k_hw_init(struct ath_hw *ah) |
968 | { | |
969 | int ret; | |
970 | struct ath_common *common = ath9k_hw_common(ah); | |
971 | ||
972 | /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ | |
973 | switch (ah->hw_version.devid) { | |
974 | case AR5416_DEVID_PCI: | |
975 | case AR5416_DEVID_PCIE: | |
976 | case AR5416_AR9100_DEVID: | |
977 | case AR9160_DEVID_PCI: | |
978 | case AR9280_DEVID_PCI: | |
979 | case AR9280_DEVID_PCIE: | |
980 | case AR9285_DEVID_PCIE: | |
981 | case AR5416_DEVID_AR9287_PCI: | |
982 | case AR5416_DEVID_AR9287_PCIE: | |
983 | case AR2427_DEVID_PCIE: | |
984 | break; | |
985 | default: | |
986 | if (common->bus_ops->ath_bus_type == ATH_USB) | |
987 | break; | |
988 | ath_print(common, ATH_DBG_FATAL, | |
989 | "Hardware device ID 0x%04x not supported\n", | |
990 | ah->hw_version.devid); | |
991 | return -EOPNOTSUPP; | |
992 | } | |
993 | ||
994 | ret = __ath9k_hw_init(ah); | |
995 | if (ret) { | |
996 | ath_print(common, ATH_DBG_FATAL, | |
997 | "Unable to initialize hardware; " | |
998 | "initialization status: %d\n", ret); | |
999 | return ret; | |
1000 | } | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | EXPORT_SYMBOL(ath9k_hw_init); | |
1005 | ||
cbe61d8a | 1006 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
f078f209 | 1007 | { |
f1dc5600 S |
1008 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
1009 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); | |
f078f209 | 1010 | |
f1dc5600 S |
1011 | REG_WRITE(ah, AR_QOS_NO_ACK, |
1012 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | | |
1013 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | | |
1014 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); | |
1015 | ||
1016 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); | |
1017 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); | |
1018 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); | |
1019 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); | |
1020 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); | |
f078f209 LR |
1021 | } |
1022 | ||
cbe61d8a | 1023 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
f1dc5600 | 1024 | struct ath9k_channel *chan) |
f078f209 | 1025 | { |
f1dc5600 | 1026 | u32 pll; |
f078f209 | 1027 | |
f1dc5600 S |
1028 | if (AR_SREV_9100(ah)) { |
1029 | if (chan && IS_CHAN_5GHZ(chan)) | |
1030 | pll = 0x1450; | |
f078f209 | 1031 | else |
f1dc5600 S |
1032 | pll = 0x1458; |
1033 | } else { | |
1034 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
1035 | pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); | |
f078f209 | 1036 | |
f1dc5600 S |
1037 | if (chan && IS_CHAN_HALF_RATE(chan)) |
1038 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); | |
1039 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
1040 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); | |
f078f209 | 1041 | |
f1dc5600 S |
1042 | if (chan && IS_CHAN_5GHZ(chan)) { |
1043 | pll |= SM(0x28, AR_RTC_9160_PLL_DIV); | |
f078f209 | 1044 | |
f078f209 | 1045 | |
f1dc5600 S |
1046 | if (AR_SREV_9280_20(ah)) { |
1047 | if (((chan->channel % 20) == 0) | |
1048 | || ((chan->channel % 10) == 0)) | |
1049 | pll = 0x2850; | |
1050 | else | |
1051 | pll = 0x142c; | |
1052 | } | |
1053 | } else { | |
1054 | pll |= SM(0x2c, AR_RTC_9160_PLL_DIV); | |
1055 | } | |
f078f209 | 1056 | |
f1dc5600 | 1057 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
f078f209 | 1058 | |
f1dc5600 | 1059 | pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); |
f078f209 | 1060 | |
f1dc5600 S |
1061 | if (chan && IS_CHAN_HALF_RATE(chan)) |
1062 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); | |
1063 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
1064 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); | |
f078f209 | 1065 | |
f1dc5600 S |
1066 | if (chan && IS_CHAN_5GHZ(chan)) |
1067 | pll |= SM(0x50, AR_RTC_9160_PLL_DIV); | |
1068 | else | |
1069 | pll |= SM(0x58, AR_RTC_9160_PLL_DIV); | |
1070 | } else { | |
1071 | pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; | |
f078f209 | 1072 | |
f1dc5600 S |
1073 | if (chan && IS_CHAN_HALF_RATE(chan)) |
1074 | pll |= SM(0x1, AR_RTC_PLL_CLKSEL); | |
1075 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
1076 | pll |= SM(0x2, AR_RTC_PLL_CLKSEL); | |
f078f209 | 1077 | |
f1dc5600 S |
1078 | if (chan && IS_CHAN_5GHZ(chan)) |
1079 | pll |= SM(0xa, AR_RTC_PLL_DIV); | |
1080 | else | |
1081 | pll |= SM(0xb, AR_RTC_PLL_DIV); | |
1082 | } | |
1083 | } | |
d03a66c1 | 1084 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
f078f209 | 1085 | |
c75724d1 LR |
1086 | /* Switch the core clock for ar9271 to 117Mhz */ |
1087 | if (AR_SREV_9271(ah)) { | |
25e2ab17 S |
1088 | udelay(500); |
1089 | REG_WRITE(ah, 0x50040, 0x304); | |
c75724d1 LR |
1090 | } |
1091 | ||
f1dc5600 S |
1092 | udelay(RTC_PLL_SETTLE_DELAY); |
1093 | ||
1094 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); | |
f078f209 LR |
1095 | } |
1096 | ||
cbe61d8a | 1097 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
d97809db | 1098 | enum nl80211_iftype opmode) |
f078f209 | 1099 | { |
152d530d | 1100 | u32 imr_reg = AR_IMR_TXERR | |
f1dc5600 S |
1101 | AR_IMR_TXURN | |
1102 | AR_IMR_RXERR | | |
1103 | AR_IMR_RXORN | | |
1104 | AR_IMR_BCNMISC; | |
f078f209 | 1105 | |
0ce024cb | 1106 | if (ah->config.rx_intr_mitigation) |
152d530d | 1107 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; |
f078f209 | 1108 | else |
152d530d | 1109 | imr_reg |= AR_IMR_RXOK; |
f078f209 | 1110 | |
152d530d | 1111 | imr_reg |= AR_IMR_TXOK; |
f078f209 | 1112 | |
d97809db | 1113 | if (opmode == NL80211_IFTYPE_AP) |
152d530d | 1114 | imr_reg |= AR_IMR_MIB; |
f078f209 | 1115 | |
152d530d | 1116 | REG_WRITE(ah, AR_IMR, imr_reg); |
74bad5cb PR |
1117 | ah->imrs2_reg |= AR_IMR_S2_GTT; |
1118 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); | |
f078f209 | 1119 | |
f1dc5600 S |
1120 | if (!AR_SREV_9100(ah)) { |
1121 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); | |
1122 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); | |
1123 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); | |
1124 | } | |
f078f209 LR |
1125 | } |
1126 | ||
0005baf4 | 1127 | static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
f078f209 | 1128 | { |
0005baf4 FF |
1129 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
1130 | val = min(val, (u32) 0xFFFF); | |
1131 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); | |
f078f209 LR |
1132 | } |
1133 | ||
0005baf4 | 1134 | static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
f078f209 | 1135 | { |
0005baf4 FF |
1136 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
1137 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); | |
1138 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); | |
1139 | } | |
1140 | ||
1141 | static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) | |
1142 | { | |
1143 | u32 val = ath9k_hw_mac_to_clks(ah, us); | |
1144 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); | |
1145 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); | |
f078f209 | 1146 | } |
f1dc5600 | 1147 | |
cbe61d8a | 1148 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
f078f209 | 1149 | { |
f078f209 | 1150 | if (tu > 0xFFFF) { |
c46917bb LR |
1151 | ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, |
1152 | "bad global tx timeout %u\n", tu); | |
2660b81a | 1153 | ah->globaltxtimeout = (u32) -1; |
f078f209 LR |
1154 | return false; |
1155 | } else { | |
1156 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); | |
2660b81a | 1157 | ah->globaltxtimeout = tu; |
f078f209 LR |
1158 | return true; |
1159 | } | |
1160 | } | |
1161 | ||
0005baf4 | 1162 | void ath9k_hw_init_global_settings(struct ath_hw *ah) |
f078f209 | 1163 | { |
0005baf4 FF |
1164 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
1165 | int acktimeout; | |
e239d859 | 1166 | int slottime; |
0005baf4 FF |
1167 | int sifstime; |
1168 | ||
c46917bb LR |
1169 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", |
1170 | ah->misc_mode); | |
f078f209 | 1171 | |
2660b81a | 1172 | if (ah->misc_mode != 0) |
f1dc5600 | 1173 | REG_WRITE(ah, AR_PCU_MISC, |
2660b81a | 1174 | REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); |
0005baf4 FF |
1175 | |
1176 | if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) | |
1177 | sifstime = 16; | |
1178 | else | |
1179 | sifstime = 10; | |
1180 | ||
e239d859 FF |
1181 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ |
1182 | slottime = ah->slottime + 3 * ah->coverage_class; | |
1183 | acktimeout = slottime + sifstime; | |
42c4568a FF |
1184 | |
1185 | /* | |
1186 | * Workaround for early ACK timeouts, add an offset to match the | |
1187 | * initval's 64us ack timeout value. | |
1188 | * This was initially only meant to work around an issue with delayed | |
1189 | * BA frames in some implementations, but it has been found to fix ACK | |
1190 | * timeout issues in other cases as well. | |
1191 | */ | |
1192 | if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) | |
1193 | acktimeout += 64 - sifstime - ah->slottime; | |
1194 | ||
e239d859 | 1195 | ath9k_hw_setslottime(ah, slottime); |
0005baf4 FF |
1196 | ath9k_hw_set_ack_timeout(ah, acktimeout); |
1197 | ath9k_hw_set_cts_timeout(ah, acktimeout); | |
2660b81a S |
1198 | if (ah->globaltxtimeout != (u32) -1) |
1199 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); | |
f1dc5600 | 1200 | } |
0005baf4 | 1201 | EXPORT_SYMBOL(ath9k_hw_init_global_settings); |
f1dc5600 | 1202 | |
285f2dda | 1203 | void ath9k_hw_deinit(struct ath_hw *ah) |
f1dc5600 | 1204 | { |
211f5859 LR |
1205 | struct ath_common *common = ath9k_hw_common(ah); |
1206 | ||
736b3a27 | 1207 | if (common->state < ATH_HW_INITIALIZED) |
211f5859 LR |
1208 | goto free_hw; |
1209 | ||
f1dc5600 | 1210 | if (!AR_SREV_9100(ah)) |
e70c0cfd | 1211 | ath9k_hw_ani_disable(ah); |
f1dc5600 | 1212 | |
9ecdef4b | 1213 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
211f5859 LR |
1214 | |
1215 | free_hw: | |
8fe65368 | 1216 | ath9k_hw_rf_free_ext_banks(ah); |
f1dc5600 | 1217 | } |
285f2dda | 1218 | EXPORT_SYMBOL(ath9k_hw_deinit); |
f1dc5600 | 1219 | |
f1dc5600 S |
1220 | /*******/ |
1221 | /* INI */ | |
1222 | /*******/ | |
1223 | ||
8fe65368 | 1224 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) |
3a702e49 BC |
1225 | { |
1226 | u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); | |
1227 | ||
1228 | if (IS_CHAN_B(chan)) | |
1229 | ctl |= CTL_11B; | |
1230 | else if (IS_CHAN_G(chan)) | |
1231 | ctl |= CTL_11G; | |
1232 | else | |
1233 | ctl |= CTL_11A; | |
1234 | ||
1235 | return ctl; | |
1236 | } | |
1237 | ||
f1dc5600 S |
1238 | /****************************************/ |
1239 | /* Reset and Channel Switching Routines */ | |
1240 | /****************************************/ | |
1241 | ||
cbe61d8a | 1242 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
f1dc5600 S |
1243 | { |
1244 | u32 regval; | |
1245 | ||
d7e7d229 LR |
1246 | /* |
1247 | * set AHB_MODE not to do cacheline prefetches | |
1248 | */ | |
f1dc5600 S |
1249 | regval = REG_READ(ah, AR_AHB_MODE); |
1250 | REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); | |
1251 | ||
d7e7d229 LR |
1252 | /* |
1253 | * let mac dma reads be in 128 byte chunks | |
1254 | */ | |
f1dc5600 S |
1255 | regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; |
1256 | REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); | |
1257 | ||
d7e7d229 LR |
1258 | /* |
1259 | * Restore TX Trigger Level to its pre-reset value. | |
1260 | * The initial value depends on whether aggregation is enabled, and is | |
1261 | * adjusted whenever underruns are detected. | |
1262 | */ | |
2660b81a | 1263 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); |
f1dc5600 | 1264 | |
d7e7d229 LR |
1265 | /* |
1266 | * let mac dma writes be in 128 byte chunks | |
1267 | */ | |
f1dc5600 S |
1268 | regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; |
1269 | REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); | |
1270 | ||
d7e7d229 LR |
1271 | /* |
1272 | * Setup receive FIFO threshold to hold off TX activities | |
1273 | */ | |
f1dc5600 S |
1274 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
1275 | ||
d7e7d229 LR |
1276 | /* |
1277 | * reduce the number of usable entries in PCU TXBUF to avoid | |
1278 | * wrap around issues. | |
1279 | */ | |
f1dc5600 | 1280 | if (AR_SREV_9285(ah)) { |
d7e7d229 LR |
1281 | /* For AR9285 the number of Fifos are reduced to half. |
1282 | * So set the usable tx buf size also to half to | |
1283 | * avoid data/delimiter underruns | |
1284 | */ | |
f1dc5600 S |
1285 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
1286 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); | |
d7e7d229 | 1287 | } else if (!AR_SREV_9271(ah)) { |
f1dc5600 S |
1288 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
1289 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); | |
1290 | } | |
1291 | } | |
1292 | ||
cbe61d8a | 1293 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
f1dc5600 S |
1294 | { |
1295 | u32 val; | |
1296 | ||
1297 | val = REG_READ(ah, AR_STA_ID1); | |
1298 | val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); | |
1299 | switch (opmode) { | |
d97809db | 1300 | case NL80211_IFTYPE_AP: |
f1dc5600 S |
1301 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP |
1302 | | AR_STA_ID1_KSRCH_MODE); | |
1303 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
f078f209 | 1304 | break; |
d97809db | 1305 | case NL80211_IFTYPE_ADHOC: |
9cb5412b | 1306 | case NL80211_IFTYPE_MESH_POINT: |
f1dc5600 S |
1307 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC |
1308 | | AR_STA_ID1_KSRCH_MODE); | |
1309 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
f078f209 | 1310 | break; |
d97809db CM |
1311 | case NL80211_IFTYPE_STATION: |
1312 | case NL80211_IFTYPE_MONITOR: | |
f1dc5600 | 1313 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); |
f078f209 | 1314 | break; |
f1dc5600 S |
1315 | } |
1316 | } | |
1317 | ||
8fe65368 LR |
1318 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
1319 | u32 *coef_mantissa, u32 *coef_exponent) | |
f1dc5600 S |
1320 | { |
1321 | u32 coef_exp, coef_man; | |
1322 | ||
1323 | for (coef_exp = 31; coef_exp > 0; coef_exp--) | |
1324 | if ((coef_scaled >> coef_exp) & 0x1) | |
1325 | break; | |
1326 | ||
1327 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); | |
1328 | ||
1329 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); | |
1330 | ||
1331 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); | |
1332 | *coef_exponent = coef_exp - 16; | |
1333 | } | |
1334 | ||
cbe61d8a | 1335 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
f1dc5600 S |
1336 | { |
1337 | u32 rst_flags; | |
1338 | u32 tmpReg; | |
1339 | ||
70768496 S |
1340 | if (AR_SREV_9100(ah)) { |
1341 | u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); | |
1342 | val &= ~AR_RTC_DERIVED_CLK_PERIOD; | |
1343 | val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); | |
1344 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); | |
1345 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); | |
1346 | } | |
1347 | ||
f1dc5600 S |
1348 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
1349 | AR_RTC_FORCE_WAKE_ON_INT); | |
1350 | ||
1351 | if (AR_SREV_9100(ah)) { | |
1352 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | | |
1353 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; | |
1354 | } else { | |
1355 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
1356 | if (tmpReg & | |
1357 | (AR_INTR_SYNC_LOCAL_TIMEOUT | | |
1358 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { | |
42d5bc3f | 1359 | u32 val; |
f1dc5600 | 1360 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
42d5bc3f LR |
1361 | |
1362 | val = AR_RC_HOSTIF; | |
1363 | if (!AR_SREV_9300_20_OR_LATER(ah)) | |
1364 | val |= AR_RC_AHB; | |
1365 | REG_WRITE(ah, AR_RC, val); | |
1366 | ||
1367 | } else if (!AR_SREV_9300_20_OR_LATER(ah)) | |
f1dc5600 | 1368 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
f1dc5600 S |
1369 | |
1370 | rst_flags = AR_RTC_RC_MAC_WARM; | |
1371 | if (type == ATH9K_RESET_COLD) | |
1372 | rst_flags |= AR_RTC_RC_MAC_COLD; | |
1373 | } | |
1374 | ||
d03a66c1 | 1375 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
f1dc5600 S |
1376 | udelay(50); |
1377 | ||
d03a66c1 | 1378 | REG_WRITE(ah, AR_RTC_RC, 0); |
0caa7b14 | 1379 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
c46917bb LR |
1380 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
1381 | "RTC stuck in MAC reset\n"); | |
f1dc5600 S |
1382 | return false; |
1383 | } | |
1384 | ||
1385 | if (!AR_SREV_9100(ah)) | |
1386 | REG_WRITE(ah, AR_RC, 0); | |
1387 | ||
f1dc5600 S |
1388 | if (AR_SREV_9100(ah)) |
1389 | udelay(50); | |
1390 | ||
1391 | return true; | |
1392 | } | |
1393 | ||
cbe61d8a | 1394 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
f1dc5600 S |
1395 | { |
1396 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | | |
1397 | AR_RTC_FORCE_WAKE_ON_INT); | |
1398 | ||
42d5bc3f | 1399 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
1c29ce67 VT |
1400 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
1401 | ||
d03a66c1 | 1402 | REG_WRITE(ah, AR_RTC_RESET, 0); |
8bd1d07f | 1403 | udelay(2); |
1c29ce67 VT |
1404 | |
1405 | if (!AR_SREV_9100(ah)) | |
1406 | REG_WRITE(ah, AR_RC, 0); | |
1407 | ||
d03a66c1 | 1408 | REG_WRITE(ah, AR_RTC_RESET, 1); |
f1dc5600 S |
1409 | |
1410 | if (!ath9k_hw_wait(ah, | |
1411 | AR_RTC_STATUS, | |
1412 | AR_RTC_STATUS_M, | |
0caa7b14 S |
1413 | AR_RTC_STATUS_ON, |
1414 | AH_WAIT_TIMEOUT)) { | |
c46917bb LR |
1415 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
1416 | "RTC not waking up\n"); | |
f1dc5600 | 1417 | return false; |
f078f209 LR |
1418 | } |
1419 | ||
f1dc5600 S |
1420 | ath9k_hw_read_revisions(ah); |
1421 | ||
1422 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); | |
1423 | } | |
1424 | ||
cbe61d8a | 1425 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
f1dc5600 S |
1426 | { |
1427 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, | |
1428 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); | |
1429 | ||
1430 | switch (type) { | |
1431 | case ATH9K_RESET_POWER_ON: | |
1432 | return ath9k_hw_set_reset_power_on(ah); | |
f1dc5600 S |
1433 | case ATH9K_RESET_WARM: |
1434 | case ATH9K_RESET_COLD: | |
1435 | return ath9k_hw_set_reset(ah, type); | |
f1dc5600 S |
1436 | default: |
1437 | return false; | |
1438 | } | |
f078f209 LR |
1439 | } |
1440 | ||
cbe61d8a | 1441 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
f1dc5600 | 1442 | struct ath9k_channel *chan) |
f078f209 | 1443 | { |
42abfbee | 1444 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { |
8bd1d07f SB |
1445 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) |
1446 | return false; | |
1447 | } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) | |
f1dc5600 | 1448 | return false; |
f078f209 | 1449 | |
9ecdef4b | 1450 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 1451 | return false; |
f078f209 | 1452 | |
2660b81a | 1453 | ah->chip_fullsleep = false; |
f1dc5600 | 1454 | ath9k_hw_init_pll(ah, chan); |
f1dc5600 | 1455 | ath9k_hw_set_rfmode(ah, chan); |
f078f209 | 1456 | |
f1dc5600 | 1457 | return true; |
f078f209 LR |
1458 | } |
1459 | ||
cbe61d8a | 1460 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
25c56eec | 1461 | struct ath9k_channel *chan) |
f078f209 | 1462 | { |
608b88cb | 1463 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
c46917bb | 1464 | struct ath_common *common = ath9k_hw_common(ah); |
5f8e077c | 1465 | struct ieee80211_channel *channel = chan->chan; |
8fe65368 | 1466 | u32 qnum; |
0a3b7bac | 1467 | int r; |
f078f209 LR |
1468 | |
1469 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { | |
1470 | if (ath9k_hw_numtxpending(ah, qnum)) { | |
c46917bb LR |
1471 | ath_print(common, ATH_DBG_QUEUE, |
1472 | "Transmit frames pending on " | |
1473 | "queue %d\n", qnum); | |
f078f209 LR |
1474 | return false; |
1475 | } | |
1476 | } | |
1477 | ||
8fe65368 | 1478 | if (!ath9k_hw_rfbus_req(ah)) { |
c46917bb LR |
1479 | ath_print(common, ATH_DBG_FATAL, |
1480 | "Could not kill baseband RX\n"); | |
f078f209 LR |
1481 | return false; |
1482 | } | |
1483 | ||
8fe65368 | 1484 | ath9k_hw_set_channel_regs(ah, chan); |
f078f209 | 1485 | |
8fe65368 | 1486 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac LR |
1487 | if (r) { |
1488 | ath_print(common, ATH_DBG_FATAL, | |
1489 | "Failed to set channel\n"); | |
1490 | return false; | |
f078f209 LR |
1491 | } |
1492 | ||
8fbff4b8 | 1493 | ah->eep_ops->set_txpower(ah, chan, |
608b88cb | 1494 | ath9k_regd_get_ctl(regulatory, chan), |
f74df6fb S |
1495 | channel->max_antenna_gain * 2, |
1496 | channel->max_power * 2, | |
1497 | min((u32) MAX_RATE_POWER, | |
608b88cb | 1498 | (u32) regulatory->power_limit)); |
f078f209 | 1499 | |
8fe65368 | 1500 | ath9k_hw_rfbus_done(ah); |
f078f209 | 1501 | |
f1dc5600 S |
1502 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
1503 | ath9k_hw_set_delta_slope(ah, chan); | |
1504 | ||
8fe65368 | 1505 | ath9k_hw_spur_mitigate_freq(ah, chan); |
f1dc5600 S |
1506 | |
1507 | if (!chan->oneTimeCalsDone) | |
1508 | chan->oneTimeCalsDone = true; | |
1509 | ||
1510 | return true; | |
1511 | } | |
1512 | ||
cbe61d8a | 1513 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
ae8d2858 | 1514 | bool bChannelChange) |
f078f209 | 1515 | { |
1510718d | 1516 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1517 | u32 saveLedState; |
2660b81a | 1518 | struct ath9k_channel *curchan = ah->curchan; |
f078f209 LR |
1519 | u32 saveDefAntenna; |
1520 | u32 macStaId1; | |
46fe782c | 1521 | u64 tsf = 0; |
8fe65368 | 1522 | int i, r; |
f078f209 | 1523 | |
43c27613 LR |
1524 | ah->txchainmask = common->tx_chainmask; |
1525 | ah->rxchainmask = common->rx_chainmask; | |
f078f209 | 1526 | |
9ecdef4b | 1527 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
ae8d2858 | 1528 | return -EIO; |
f078f209 | 1529 | |
9ebef799 | 1530 | if (curchan && !ah->chip_fullsleep) |
f078f209 LR |
1531 | ath9k_hw_getnf(ah, curchan); |
1532 | ||
1533 | if (bChannelChange && | |
2660b81a S |
1534 | (ah->chip_fullsleep != true) && |
1535 | (ah->curchan != NULL) && | |
1536 | (chan->channel != ah->curchan->channel) && | |
f078f209 | 1537 | ((chan->channelFlags & CHANNEL_ALL) == |
2660b81a | 1538 | (ah->curchan->channelFlags & CHANNEL_ALL)) && |
0a475cc6 VT |
1539 | !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) || |
1540 | IS_CHAN_A_5MHZ_SPACED(ah->curchan))) { | |
f078f209 | 1541 | |
25c56eec | 1542 | if (ath9k_hw_channel_change(ah, chan)) { |
2660b81a | 1543 | ath9k_hw_loadnf(ah, ah->curchan); |
f078f209 | 1544 | ath9k_hw_start_nfcal(ah); |
ae8d2858 | 1545 | return 0; |
f078f209 LR |
1546 | } |
1547 | } | |
1548 | ||
1549 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); | |
1550 | if (saveDefAntenna == 0) | |
1551 | saveDefAntenna = 1; | |
1552 | ||
1553 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; | |
1554 | ||
46fe782c S |
1555 | /* For chips on which RTC reset is done, save TSF before it gets cleared */ |
1556 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) | |
1557 | tsf = ath9k_hw_gettsf64(ah); | |
1558 | ||
f078f209 LR |
1559 | saveLedState = REG_READ(ah, AR_CFG_LED) & |
1560 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | | |
1561 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); | |
1562 | ||
1563 | ath9k_hw_mark_phy_inactive(ah); | |
1564 | ||
05020d23 | 1565 | /* Only required on the first reset */ |
d7e7d229 LR |
1566 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1567 | REG_WRITE(ah, | |
1568 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1569 | AR9271_RADIO_RF_RST); | |
1570 | udelay(50); | |
1571 | } | |
1572 | ||
f078f209 | 1573 | if (!ath9k_hw_chip_reset(ah, chan)) { |
c46917bb | 1574 | ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); |
ae8d2858 | 1575 | return -EINVAL; |
f078f209 LR |
1576 | } |
1577 | ||
05020d23 | 1578 | /* Only required on the first reset */ |
d7e7d229 LR |
1579 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1580 | ah->htc_reset_init = false; | |
1581 | REG_WRITE(ah, | |
1582 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1583 | AR9271_GATE_MAC_CTL); | |
1584 | udelay(50); | |
1585 | } | |
1586 | ||
46fe782c S |
1587 | /* Restore TSF */ |
1588 | if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) | |
1589 | ath9k_hw_settsf64(ah, tsf); | |
1590 | ||
369391db VT |
1591 | if (AR_SREV_9280_10_OR_LATER(ah)) |
1592 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); | |
f078f209 | 1593 | |
25c56eec | 1594 | r = ath9k_hw_process_ini(ah, chan); |
ae8d2858 LR |
1595 | if (r) |
1596 | return r; | |
f078f209 | 1597 | |
0ced0e17 JM |
1598 | /* Setup MFP options for CCMP */ |
1599 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
1600 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt | |
1601 | * frames when constructing CCMP AAD. */ | |
1602 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, | |
1603 | 0xc7ff); | |
1604 | ah->sw_mgmt_crypto = false; | |
1605 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | |
1606 | /* Disable hardware crypto for management frames */ | |
1607 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, | |
1608 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); | |
1609 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, | |
1610 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); | |
1611 | ah->sw_mgmt_crypto = true; | |
1612 | } else | |
1613 | ah->sw_mgmt_crypto = true; | |
1614 | ||
f078f209 LR |
1615 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
1616 | ath9k_hw_set_delta_slope(ah, chan); | |
1617 | ||
8fe65368 | 1618 | ath9k_hw_spur_mitigate_freq(ah, chan); |
d6509151 | 1619 | ah->eep_ops->set_board_values(ah, chan); |
a7765828 | 1620 | |
1510718d LR |
1621 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); |
1622 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) | |
f078f209 LR |
1623 | | macStaId1 |
1624 | | AR_STA_ID1_RTS_USE_DEF | |
2660b81a | 1625 | | (ah->config. |
60b67f51 | 1626 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
2660b81a S |
1627 | | ah->sta_id1_defaults); |
1628 | ath9k_hw_set_operating_mode(ah, ah->opmode); | |
f078f209 | 1629 | |
13b81559 | 1630 | ath_hw_setbssidmask(common); |
f078f209 LR |
1631 | |
1632 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); | |
1633 | ||
3453ad88 | 1634 | ath9k_hw_write_associd(ah); |
f078f209 LR |
1635 | |
1636 | REG_WRITE(ah, AR_ISR, ~0); | |
1637 | ||
1638 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); | |
1639 | ||
8fe65368 | 1640 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac LR |
1641 | if (r) |
1642 | return r; | |
f078f209 LR |
1643 | |
1644 | for (i = 0; i < AR_NUM_DCU; i++) | |
1645 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); | |
1646 | ||
2660b81a S |
1647 | ah->intr_txqs = 0; |
1648 | for (i = 0; i < ah->caps.total_queues; i++) | |
f078f209 LR |
1649 | ath9k_hw_resettxqueue(ah, i); |
1650 | ||
2660b81a | 1651 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
f078f209 LR |
1652 | ath9k_hw_init_qos(ah); |
1653 | ||
2660b81a | 1654 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
500c064d | 1655 | ath9k_enable_rfkill(ah); |
3b319aae | 1656 | |
0005baf4 | 1657 | ath9k_hw_init_global_settings(ah); |
f078f209 | 1658 | |
326bebbc | 1659 | if (AR_SREV_9287_12_OR_LATER(ah)) { |
ac88b6ec VN |
1660 | REG_WRITE(ah, AR_D_GBL_IFS_SIFS, |
1661 | AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); | |
1662 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, | |
1663 | AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); | |
1664 | REG_WRITE(ah, AR_D_GBL_IFS_EIFS, | |
1665 | AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); | |
1666 | ||
1667 | REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); | |
1668 | REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); | |
1669 | ||
1670 | REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, | |
1671 | AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); | |
1672 | REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, | |
1673 | AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); | |
1674 | } | |
326bebbc | 1675 | if (AR_SREV_9287_12_OR_LATER(ah)) { |
ac88b6ec VN |
1676 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, |
1677 | AR_PCU_MISC_MODE2_ENABLE_AGGWEP); | |
1678 | } | |
1679 | ||
f078f209 LR |
1680 | REG_WRITE(ah, AR_STA_ID1, |
1681 | REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); | |
1682 | ||
1683 | ath9k_hw_set_dma(ah); | |
1684 | ||
1685 | REG_WRITE(ah, AR_OBS, 8); | |
1686 | ||
0ce024cb | 1687 | if (ah->config.rx_intr_mitigation) { |
f078f209 LR |
1688 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); |
1689 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); | |
1690 | } | |
1691 | ||
1692 | ath9k_hw_init_bb(ah, chan); | |
1693 | ||
ae8d2858 | 1694 | if (!ath9k_hw_init_cal(ah, chan)) |
6badaaf7 | 1695 | return -EIO; |
f078f209 | 1696 | |
8fe65368 | 1697 | ath9k_hw_restore_chainmask(ah); |
f078f209 LR |
1698 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); |
1699 | ||
d7e7d229 LR |
1700 | /* |
1701 | * For big endian systems turn on swapping for descriptors | |
1702 | */ | |
f078f209 LR |
1703 | if (AR_SREV_9100(ah)) { |
1704 | u32 mask; | |
1705 | mask = REG_READ(ah, AR_CFG); | |
1706 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { | |
c46917bb | 1707 | ath_print(common, ATH_DBG_RESET, |
04bd4638 | 1708 | "CFG Byte Swap Set 0x%x\n", mask); |
f078f209 LR |
1709 | } else { |
1710 | mask = | |
1711 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; | |
1712 | REG_WRITE(ah, AR_CFG, mask); | |
c46917bb | 1713 | ath_print(common, ATH_DBG_RESET, |
04bd4638 | 1714 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); |
f078f209 LR |
1715 | } |
1716 | } else { | |
d7e7d229 LR |
1717 | /* Configure AR9271 target WLAN */ |
1718 | if (AR_SREV_9271(ah)) | |
1719 | REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); | |
f078f209 | 1720 | #ifdef __BIG_ENDIAN |
d7e7d229 LR |
1721 | else |
1722 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
f078f209 LR |
1723 | #endif |
1724 | } | |
1725 | ||
766ec4a9 | 1726 | if (ah->btcoex_hw.enabled) |
42cc41ed VT |
1727 | ath9k_hw_btcoex_enable(ah); |
1728 | ||
ae8d2858 | 1729 | return 0; |
f078f209 | 1730 | } |
7322fd19 | 1731 | EXPORT_SYMBOL(ath9k_hw_reset); |
f078f209 | 1732 | |
f1dc5600 S |
1733 | /************************/ |
1734 | /* Key Cache Management */ | |
1735 | /************************/ | |
f078f209 | 1736 | |
cbe61d8a | 1737 | bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) |
f078f209 | 1738 | { |
f1dc5600 | 1739 | u32 keyType; |
f078f209 | 1740 | |
2660b81a | 1741 | if (entry >= ah->caps.keycache_size) { |
c46917bb LR |
1742 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
1743 | "keychache entry %u out of range\n", entry); | |
f078f209 LR |
1744 | return false; |
1745 | } | |
1746 | ||
f1dc5600 | 1747 | keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); |
f078f209 | 1748 | |
f1dc5600 S |
1749 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); |
1750 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); | |
1751 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); | |
1752 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); | |
1753 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); | |
1754 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); | |
1755 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); | |
1756 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); | |
f078f209 | 1757 | |
f1dc5600 S |
1758 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
1759 | u16 micentry = entry + 64; | |
f078f209 | 1760 | |
f1dc5600 S |
1761 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); |
1762 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); | |
1763 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); | |
1764 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); | |
f078f209 | 1765 | |
f078f209 LR |
1766 | } |
1767 | ||
f078f209 LR |
1768 | return true; |
1769 | } | |
7322fd19 | 1770 | EXPORT_SYMBOL(ath9k_hw_keyreset); |
f078f209 | 1771 | |
cbe61d8a | 1772 | bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) |
f078f209 | 1773 | { |
f1dc5600 | 1774 | u32 macHi, macLo; |
f078f209 | 1775 | |
2660b81a | 1776 | if (entry >= ah->caps.keycache_size) { |
c46917bb LR |
1777 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
1778 | "keychache entry %u out of range\n", entry); | |
f1dc5600 | 1779 | return false; |
f078f209 LR |
1780 | } |
1781 | ||
f1dc5600 S |
1782 | if (mac != NULL) { |
1783 | macHi = (mac[5] << 8) | mac[4]; | |
1784 | macLo = (mac[3] << 24) | | |
1785 | (mac[2] << 16) | | |
1786 | (mac[1] << 8) | | |
1787 | mac[0]; | |
1788 | macLo >>= 1; | |
1789 | macLo |= (macHi & 1) << 31; | |
1790 | macHi >>= 1; | |
f078f209 | 1791 | } else { |
f1dc5600 | 1792 | macLo = macHi = 0; |
f078f209 | 1793 | } |
f1dc5600 S |
1794 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); |
1795 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); | |
f078f209 | 1796 | |
f1dc5600 | 1797 | return true; |
f078f209 | 1798 | } |
7322fd19 | 1799 | EXPORT_SYMBOL(ath9k_hw_keysetmac); |
f078f209 | 1800 | |
cbe61d8a | 1801 | bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, |
f1dc5600 | 1802 | const struct ath9k_keyval *k, |
e0caf9ea | 1803 | const u8 *mac) |
f078f209 | 1804 | { |
2660b81a | 1805 | const struct ath9k_hw_capabilities *pCap = &ah->caps; |
c46917bb | 1806 | struct ath_common *common = ath9k_hw_common(ah); |
f1dc5600 S |
1807 | u32 key0, key1, key2, key3, key4; |
1808 | u32 keyType; | |
f078f209 | 1809 | |
f1dc5600 | 1810 | if (entry >= pCap->keycache_size) { |
c46917bb LR |
1811 | ath_print(common, ATH_DBG_FATAL, |
1812 | "keycache entry %u out of range\n", entry); | |
f1dc5600 | 1813 | return false; |
f078f209 LR |
1814 | } |
1815 | ||
f1dc5600 S |
1816 | switch (k->kv_type) { |
1817 | case ATH9K_CIPHER_AES_OCB: | |
1818 | keyType = AR_KEYTABLE_TYPE_AES; | |
1819 | break; | |
1820 | case ATH9K_CIPHER_AES_CCM: | |
1821 | if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { | |
c46917bb LR |
1822 | ath_print(common, ATH_DBG_ANY, |
1823 | "AES-CCM not supported by mac rev 0x%x\n", | |
1824 | ah->hw_version.macRev); | |
f1dc5600 S |
1825 | return false; |
1826 | } | |
1827 | keyType = AR_KEYTABLE_TYPE_CCM; | |
1828 | break; | |
1829 | case ATH9K_CIPHER_TKIP: | |
1830 | keyType = AR_KEYTABLE_TYPE_TKIP; | |
1831 | if (ATH9K_IS_MIC_ENABLED(ah) | |
1832 | && entry + 64 >= pCap->keycache_size) { | |
c46917bb LR |
1833 | ath_print(common, ATH_DBG_ANY, |
1834 | "entry %u inappropriate for TKIP\n", entry); | |
f1dc5600 S |
1835 | return false; |
1836 | } | |
1837 | break; | |
1838 | case ATH9K_CIPHER_WEP: | |
e31a16d6 | 1839 | if (k->kv_len < WLAN_KEY_LEN_WEP40) { |
c46917bb LR |
1840 | ath_print(common, ATH_DBG_ANY, |
1841 | "WEP key length %u too small\n", k->kv_len); | |
f1dc5600 S |
1842 | return false; |
1843 | } | |
e31a16d6 | 1844 | if (k->kv_len <= WLAN_KEY_LEN_WEP40) |
f1dc5600 | 1845 | keyType = AR_KEYTABLE_TYPE_40; |
e31a16d6 | 1846 | else if (k->kv_len <= WLAN_KEY_LEN_WEP104) |
f1dc5600 S |
1847 | keyType = AR_KEYTABLE_TYPE_104; |
1848 | else | |
1849 | keyType = AR_KEYTABLE_TYPE_128; | |
1850 | break; | |
1851 | case ATH9K_CIPHER_CLR: | |
1852 | keyType = AR_KEYTABLE_TYPE_CLR; | |
1853 | break; | |
1854 | default: | |
c46917bb LR |
1855 | ath_print(common, ATH_DBG_FATAL, |
1856 | "cipher %u not supported\n", k->kv_type); | |
f1dc5600 | 1857 | return false; |
f078f209 LR |
1858 | } |
1859 | ||
e0caf9ea JM |
1860 | key0 = get_unaligned_le32(k->kv_val + 0); |
1861 | key1 = get_unaligned_le16(k->kv_val + 4); | |
1862 | key2 = get_unaligned_le32(k->kv_val + 6); | |
1863 | key3 = get_unaligned_le16(k->kv_val + 10); | |
1864 | key4 = get_unaligned_le32(k->kv_val + 12); | |
e31a16d6 | 1865 | if (k->kv_len <= WLAN_KEY_LEN_WEP104) |
f1dc5600 | 1866 | key4 &= 0xff; |
f078f209 | 1867 | |
672903b3 JM |
1868 | /* |
1869 | * Note: Key cache registers access special memory area that requires | |
1870 | * two 32-bit writes to actually update the values in the internal | |
1871 | * memory. Consequently, the exact order and pairs used here must be | |
1872 | * maintained. | |
1873 | */ | |
1874 | ||
f1dc5600 S |
1875 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
1876 | u16 micentry = entry + 64; | |
f078f209 | 1877 | |
672903b3 JM |
1878 | /* |
1879 | * Write inverted key[47:0] first to avoid Michael MIC errors | |
1880 | * on frames that could be sent or received at the same time. | |
1881 | * The correct key will be written in the end once everything | |
1882 | * else is ready. | |
1883 | */ | |
f1dc5600 S |
1884 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); |
1885 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); | |
672903b3 JM |
1886 | |
1887 | /* Write key[95:48] */ | |
f1dc5600 S |
1888 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
1889 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); | |
672903b3 JM |
1890 | |
1891 | /* Write key[127:96] and key type */ | |
f1dc5600 S |
1892 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
1893 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); | |
672903b3 JM |
1894 | |
1895 | /* Write MAC address for the entry */ | |
f1dc5600 | 1896 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
f078f209 | 1897 | |
2660b81a | 1898 | if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { |
672903b3 JM |
1899 | /* |
1900 | * TKIP uses two key cache entries: | |
1901 | * Michael MIC TX/RX keys in the same key cache entry | |
1902 | * (idx = main index + 64): | |
1903 | * key0 [31:0] = RX key [31:0] | |
1904 | * key1 [15:0] = TX key [31:16] | |
1905 | * key1 [31:16] = reserved | |
1906 | * key2 [31:0] = RX key [63:32] | |
1907 | * key3 [15:0] = TX key [15:0] | |
1908 | * key3 [31:16] = reserved | |
1909 | * key4 [31:0] = TX key [63:32] | |
1910 | */ | |
f1dc5600 | 1911 | u32 mic0, mic1, mic2, mic3, mic4; |
f078f209 | 1912 | |
f1dc5600 S |
1913 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
1914 | mic2 = get_unaligned_le32(k->kv_mic + 4); | |
1915 | mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; | |
1916 | mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; | |
1917 | mic4 = get_unaligned_le32(k->kv_txmic + 4); | |
672903b3 JM |
1918 | |
1919 | /* Write RX[31:0] and TX[31:16] */ | |
f1dc5600 S |
1920 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); |
1921 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); | |
672903b3 JM |
1922 | |
1923 | /* Write RX[63:32] and TX[15:0] */ | |
f1dc5600 S |
1924 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); |
1925 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); | |
672903b3 JM |
1926 | |
1927 | /* Write TX[63:32] and keyType(reserved) */ | |
f1dc5600 S |
1928 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); |
1929 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), | |
1930 | AR_KEYTABLE_TYPE_CLR); | |
f078f209 | 1931 | |
f1dc5600 | 1932 | } else { |
672903b3 JM |
1933 | /* |
1934 | * TKIP uses four key cache entries (two for group | |
1935 | * keys): | |
1936 | * Michael MIC TX/RX keys are in different key cache | |
1937 | * entries (idx = main index + 64 for TX and | |
1938 | * main index + 32 + 96 for RX): | |
1939 | * key0 [31:0] = TX/RX MIC key [31:0] | |
1940 | * key1 [31:0] = reserved | |
1941 | * key2 [31:0] = TX/RX MIC key [63:32] | |
1942 | * key3 [31:0] = reserved | |
1943 | * key4 [31:0] = reserved | |
1944 | * | |
1945 | * Upper layer code will call this function separately | |
1946 | * for TX and RX keys when these registers offsets are | |
1947 | * used. | |
1948 | */ | |
f1dc5600 | 1949 | u32 mic0, mic2; |
f078f209 | 1950 | |
f1dc5600 S |
1951 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
1952 | mic2 = get_unaligned_le32(k->kv_mic + 4); | |
672903b3 JM |
1953 | |
1954 | /* Write MIC key[31:0] */ | |
f1dc5600 S |
1955 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); |
1956 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); | |
672903b3 JM |
1957 | |
1958 | /* Write MIC key[63:32] */ | |
f1dc5600 S |
1959 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); |
1960 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); | |
672903b3 JM |
1961 | |
1962 | /* Write TX[63:32] and keyType(reserved) */ | |
f1dc5600 S |
1963 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); |
1964 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), | |
1965 | AR_KEYTABLE_TYPE_CLR); | |
1966 | } | |
672903b3 JM |
1967 | |
1968 | /* MAC address registers are reserved for the MIC entry */ | |
f1dc5600 S |
1969 | REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); |
1970 | REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); | |
672903b3 JM |
1971 | |
1972 | /* | |
1973 | * Write the correct (un-inverted) key[47:0] last to enable | |
1974 | * TKIP now that all other registers are set with correct | |
1975 | * values. | |
1976 | */ | |
f1dc5600 S |
1977 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
1978 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); | |
1979 | } else { | |
672903b3 | 1980 | /* Write key[47:0] */ |
f1dc5600 S |
1981 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
1982 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); | |
672903b3 JM |
1983 | |
1984 | /* Write key[95:48] */ | |
f1dc5600 S |
1985 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
1986 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); | |
672903b3 JM |
1987 | |
1988 | /* Write key[127:96] and key type */ | |
f1dc5600 S |
1989 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
1990 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); | |
f078f209 | 1991 | |
672903b3 | 1992 | /* Write MAC address for the entry */ |
f1dc5600 S |
1993 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
1994 | } | |
f078f209 | 1995 | |
f078f209 LR |
1996 | return true; |
1997 | } | |
7322fd19 | 1998 | EXPORT_SYMBOL(ath9k_hw_set_keycache_entry); |
f078f209 | 1999 | |
cbe61d8a | 2000 | bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) |
f078f209 | 2001 | { |
2660b81a | 2002 | if (entry < ah->caps.keycache_size) { |
f1dc5600 S |
2003 | u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); |
2004 | if (val & AR_KEYTABLE_VALID) | |
2005 | return true; | |
2006 | } | |
2007 | return false; | |
f078f209 | 2008 | } |
7322fd19 | 2009 | EXPORT_SYMBOL(ath9k_hw_keyisvalid); |
f078f209 | 2010 | |
f1dc5600 S |
2011 | /******************************/ |
2012 | /* Power Management (Chipset) */ | |
2013 | /******************************/ | |
2014 | ||
42d5bc3f LR |
2015 | /* |
2016 | * Notify Power Mgt is disabled in self-generated frames. | |
2017 | * If requested, force chip to sleep. | |
2018 | */ | |
cbe61d8a | 2019 | static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) |
f078f209 | 2020 | { |
f1dc5600 S |
2021 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
2022 | if (setChip) { | |
42d5bc3f LR |
2023 | /* |
2024 | * Clear the RTC force wake bit to allow the | |
2025 | * mac to go to sleep. | |
2026 | */ | |
f1dc5600 S |
2027 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
2028 | AR_RTC_FORCE_WAKE_EN); | |
42d5bc3f | 2029 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
f1dc5600 | 2030 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
f078f209 | 2031 | |
42d5bc3f | 2032 | /* Shutdown chip. Active low */ |
14b3af38 | 2033 | if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) |
4921be80 S |
2034 | REG_CLR_BIT(ah, (AR_RTC_RESET), |
2035 | AR_RTC_RESET_EN); | |
f1dc5600 | 2036 | } |
f078f209 LR |
2037 | } |
2038 | ||
cbe61d8a | 2039 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) |
f078f209 | 2040 | { |
f1dc5600 S |
2041 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
2042 | if (setChip) { | |
2660b81a | 2043 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 | 2044 | |
f1dc5600 S |
2045 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
2046 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, | |
2047 | AR_RTC_FORCE_WAKE_ON_INT); | |
2048 | } else { | |
2049 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, | |
2050 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 2051 | } |
f078f209 | 2052 | } |
f078f209 LR |
2053 | } |
2054 | ||
cbe61d8a | 2055 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) |
f078f209 | 2056 | { |
f1dc5600 S |
2057 | u32 val; |
2058 | int i; | |
f078f209 | 2059 | |
f1dc5600 S |
2060 | if (setChip) { |
2061 | if ((REG_READ(ah, AR_RTC_STATUS) & | |
2062 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { | |
2063 | if (ath9k_hw_set_reset_reg(ah, | |
2064 | ATH9K_RESET_POWER_ON) != true) { | |
2065 | return false; | |
2066 | } | |
e041228f LR |
2067 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
2068 | ath9k_hw_init_pll(ah, NULL); | |
f1dc5600 S |
2069 | } |
2070 | if (AR_SREV_9100(ah)) | |
2071 | REG_SET_BIT(ah, AR_RTC_RESET, | |
2072 | AR_RTC_RESET_EN); | |
f078f209 | 2073 | |
f1dc5600 S |
2074 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
2075 | AR_RTC_FORCE_WAKE_EN); | |
2076 | udelay(50); | |
f078f209 | 2077 | |
f1dc5600 S |
2078 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
2079 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; | |
2080 | if (val == AR_RTC_STATUS_ON) | |
2081 | break; | |
2082 | udelay(50); | |
2083 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, | |
2084 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 2085 | } |
f1dc5600 | 2086 | if (i == 0) { |
c46917bb LR |
2087 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
2088 | "Failed to wakeup in %uus\n", | |
2089 | POWER_UP_TIME / 20); | |
f1dc5600 | 2090 | return false; |
f078f209 | 2091 | } |
f078f209 LR |
2092 | } |
2093 | ||
f1dc5600 | 2094 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
f078f209 | 2095 | |
f1dc5600 | 2096 | return true; |
f078f209 LR |
2097 | } |
2098 | ||
9ecdef4b | 2099 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
f078f209 | 2100 | { |
c46917bb | 2101 | struct ath_common *common = ath9k_hw_common(ah); |
cbe61d8a | 2102 | int status = true, setChip = true; |
f1dc5600 S |
2103 | static const char *modes[] = { |
2104 | "AWAKE", | |
2105 | "FULL-SLEEP", | |
2106 | "NETWORK SLEEP", | |
2107 | "UNDEFINED" | |
2108 | }; | |
f1dc5600 | 2109 | |
cbdec975 GJ |
2110 | if (ah->power_mode == mode) |
2111 | return status; | |
2112 | ||
c46917bb LR |
2113 | ath_print(common, ATH_DBG_RESET, "%s -> %s\n", |
2114 | modes[ah->power_mode], modes[mode]); | |
f1dc5600 S |
2115 | |
2116 | switch (mode) { | |
2117 | case ATH9K_PM_AWAKE: | |
2118 | status = ath9k_hw_set_power_awake(ah, setChip); | |
2119 | break; | |
2120 | case ATH9K_PM_FULL_SLEEP: | |
2121 | ath9k_set_power_sleep(ah, setChip); | |
2660b81a | 2122 | ah->chip_fullsleep = true; |
f1dc5600 S |
2123 | break; |
2124 | case ATH9K_PM_NETWORK_SLEEP: | |
2125 | ath9k_set_power_network_sleep(ah, setChip); | |
2126 | break; | |
f078f209 | 2127 | default: |
c46917bb LR |
2128 | ath_print(common, ATH_DBG_FATAL, |
2129 | "Unknown power mode %u\n", mode); | |
f078f209 LR |
2130 | return false; |
2131 | } | |
2660b81a | 2132 | ah->power_mode = mode; |
f1dc5600 S |
2133 | |
2134 | return status; | |
f078f209 | 2135 | } |
7322fd19 | 2136 | EXPORT_SYMBOL(ath9k_hw_setpower); |
f078f209 | 2137 | |
24c1a280 LR |
2138 | /* |
2139 | * Helper for ASPM support. | |
2140 | * | |
2141 | * Disable PLL when in L0s as well as receiver clock when in L1. | |
2142 | * This power saving option must be enabled through the SerDes. | |
2143 | * | |
2144 | * Programming the SerDes must go through the same 288 bit serial shift | |
2145 | * register as the other analog registers. Hence the 9 writes. | |
2146 | */ | |
d70357d5 LR |
2147 | static void ar9002_hw_configpcipowersave(struct ath_hw *ah, |
2148 | int restore, | |
2149 | int power_off) | |
f078f209 | 2150 | { |
f1dc5600 | 2151 | u8 i; |
93b1b37f | 2152 | u32 val; |
f078f209 | 2153 | |
2660b81a | 2154 | if (ah->is_pciexpress != true) |
f1dc5600 | 2155 | return; |
f078f209 | 2156 | |
24c1a280 | 2157 | /* Do not touch SerDes registers */ |
2660b81a | 2158 | if (ah->config.pcie_powersave_enable == 2) |
f1dc5600 S |
2159 | return; |
2160 | ||
24c1a280 | 2161 | /* Nothing to do on restore for 11N */ |
93b1b37f VN |
2162 | if (!restore) { |
2163 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
2164 | /* | |
2165 | * AR9280 2.0 or later chips use SerDes values from the | |
2166 | * initvals.h initialized depending on chipset during | |
d70357d5 | 2167 | * __ath9k_hw_init() |
93b1b37f VN |
2168 | */ |
2169 | for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { | |
2170 | REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), | |
2171 | INI_RA(&ah->iniPcieSerdes, i, 1)); | |
2172 | } | |
2173 | } else if (AR_SREV_9280(ah) && | |
2174 | (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) { | |
2175 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); | |
2176 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
2177 | ||
2178 | /* RX shut off when elecidle is asserted */ | |
2179 | REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); | |
2180 | REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); | |
2181 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); | |
2182 | ||
2183 | /* Shut off CLKREQ active in L1 */ | |
2184 | if (ah->config.pcie_clock_req) | |
2185 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); | |
2186 | else | |
2187 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); | |
f1dc5600 | 2188 | |
93b1b37f VN |
2189 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
2190 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
2191 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); | |
f1dc5600 | 2192 | |
93b1b37f VN |
2193 | /* Load the new settings */ |
2194 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); | |
f1dc5600 | 2195 | |
93b1b37f VN |
2196 | } else { |
2197 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); | |
2198 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
f1dc5600 | 2199 | |
93b1b37f VN |
2200 | /* RX shut off when elecidle is asserted */ |
2201 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); | |
2202 | REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); | |
2203 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); | |
f1dc5600 | 2204 | |
93b1b37f VN |
2205 | /* |
2206 | * Ignore ah->ah_config.pcie_clock_req setting for | |
2207 | * pre-AR9280 11n | |
2208 | */ | |
2209 | REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); | |
24c1a280 | 2210 | |
93b1b37f VN |
2211 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
2212 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
2213 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); | |
24c1a280 | 2214 | |
93b1b37f VN |
2215 | /* Load the new settings */ |
2216 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); | |
2217 | } | |
24c1a280 | 2218 | |
93b1b37f | 2219 | udelay(1000); |
24c1a280 | 2220 | |
93b1b37f VN |
2221 | /* set bit 19 to allow forcing of pcie core into L1 state */ |
2222 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); | |
f078f209 | 2223 | |
93b1b37f VN |
2224 | /* Several PCIe massages to ensure proper behaviour */ |
2225 | if (ah->config.pcie_waen) { | |
2226 | val = ah->config.pcie_waen; | |
2227 | if (!power_off) | |
2228 | val &= (~AR_WA_D3_L1_DISABLE); | |
2229 | } else { | |
2230 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || | |
2231 | AR_SREV_9287(ah)) { | |
2232 | val = AR9285_WA_DEFAULT; | |
2233 | if (!power_off) | |
2234 | val &= (~AR_WA_D3_L1_DISABLE); | |
2235 | } else if (AR_SREV_9280(ah)) { | |
2236 | /* | |
2237 | * On AR9280 chips bit 22 of 0x4004 needs to be | |
2238 | * set otherwise card may disappear. | |
2239 | */ | |
2240 | val = AR9280_WA_DEFAULT; | |
2241 | if (!power_off) | |
2242 | val &= (~AR_WA_D3_L1_DISABLE); | |
2243 | } else | |
2244 | val = AR_WA_DEFAULT; | |
2245 | } | |
6d08b9b9 | 2246 | |
93b1b37f VN |
2247 | REG_WRITE(ah, AR_WA, val); |
2248 | } | |
f1dc5600 | 2249 | |
93b1b37f | 2250 | if (power_off) { |
24c1a280 | 2251 | /* |
93b1b37f VN |
2252 | * Set PCIe workaround bits |
2253 | * bit 14 in WA register (disable L1) should only | |
2254 | * be set when device enters D3 and be cleared | |
2255 | * when device comes back to D0. | |
24c1a280 | 2256 | */ |
93b1b37f VN |
2257 | if (ah->config.pcie_waen) { |
2258 | if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) | |
2259 | REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); | |
2260 | } else { | |
2261 | if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) || | |
2262 | AR_SREV_9287(ah)) && | |
2263 | (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || | |
2264 | (AR_SREV_9280(ah) && | |
2265 | (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { | |
2266 | REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); | |
2267 | } | |
2268 | } | |
f1dc5600 | 2269 | } |
f078f209 LR |
2270 | } |
2271 | ||
f1dc5600 S |
2272 | /**********************/ |
2273 | /* Interrupt Handling */ | |
2274 | /**********************/ | |
2275 | ||
cbe61d8a | 2276 | bool ath9k_hw_intrpend(struct ath_hw *ah) |
f078f209 LR |
2277 | { |
2278 | u32 host_isr; | |
2279 | ||
2280 | if (AR_SREV_9100(ah)) | |
2281 | return true; | |
2282 | ||
2283 | host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); | |
2284 | if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS)) | |
2285 | return true; | |
2286 | ||
2287 | host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
2288 | if ((host_isr & AR_INTR_SYNC_DEFAULT) | |
2289 | && (host_isr != AR_INTR_SPURIOUS)) | |
2290 | return true; | |
2291 | ||
2292 | return false; | |
2293 | } | |
7322fd19 | 2294 | EXPORT_SYMBOL(ath9k_hw_intrpend); |
f078f209 | 2295 | |
cbe61d8a | 2296 | bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) |
f078f209 LR |
2297 | { |
2298 | u32 isr = 0; | |
2299 | u32 mask2 = 0; | |
2660b81a | 2300 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 LR |
2301 | u32 sync_cause = 0; |
2302 | bool fatal_int = false; | |
c46917bb | 2303 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
2304 | |
2305 | if (!AR_SREV_9100(ah)) { | |
2306 | if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { | |
2307 | if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) | |
2308 | == AR_RTC_STATUS_ON) { | |
2309 | isr = REG_READ(ah, AR_ISR); | |
2310 | } | |
2311 | } | |
2312 | ||
f1dc5600 S |
2313 | sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & |
2314 | AR_INTR_SYNC_DEFAULT; | |
f078f209 LR |
2315 | |
2316 | *masked = 0; | |
2317 | ||
2318 | if (!isr && !sync_cause) | |
2319 | return false; | |
2320 | } else { | |
2321 | *masked = 0; | |
2322 | isr = REG_READ(ah, AR_ISR); | |
2323 | } | |
2324 | ||
2325 | if (isr) { | |
f078f209 LR |
2326 | if (isr & AR_ISR_BCNMISC) { |
2327 | u32 isr2; | |
2328 | isr2 = REG_READ(ah, AR_ISR_S2); | |
2329 | if (isr2 & AR_ISR_S2_TIM) | |
2330 | mask2 |= ATH9K_INT_TIM; | |
2331 | if (isr2 & AR_ISR_S2_DTIM) | |
2332 | mask2 |= ATH9K_INT_DTIM; | |
2333 | if (isr2 & AR_ISR_S2_DTIMSYNC) | |
2334 | mask2 |= ATH9K_INT_DTIMSYNC; | |
2335 | if (isr2 & (AR_ISR_S2_CABEND)) | |
2336 | mask2 |= ATH9K_INT_CABEND; | |
2337 | if (isr2 & AR_ISR_S2_GTT) | |
2338 | mask2 |= ATH9K_INT_GTT; | |
2339 | if (isr2 & AR_ISR_S2_CST) | |
2340 | mask2 |= ATH9K_INT_CST; | |
4af9cf4f S |
2341 | if (isr2 & AR_ISR_S2_TSFOOR) |
2342 | mask2 |= ATH9K_INT_TSFOOR; | |
f078f209 LR |
2343 | } |
2344 | ||
2345 | isr = REG_READ(ah, AR_ISR_RAC); | |
2346 | if (isr == 0xffffffff) { | |
2347 | *masked = 0; | |
2348 | return false; | |
2349 | } | |
2350 | ||
2351 | *masked = isr & ATH9K_INT_COMMON; | |
2352 | ||
0ce024cb | 2353 | if (ah->config.rx_intr_mitigation) { |
f078f209 LR |
2354 | if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) |
2355 | *masked |= ATH9K_INT_RX; | |
2356 | } | |
2357 | ||
2358 | if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) | |
2359 | *masked |= ATH9K_INT_RX; | |
2360 | if (isr & | |
2361 | (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | | |
2362 | AR_ISR_TXEOL)) { | |
2363 | u32 s0_s, s1_s; | |
2364 | ||
2365 | *masked |= ATH9K_INT_TX; | |
2366 | ||
2367 | s0_s = REG_READ(ah, AR_ISR_S0_S); | |
2660b81a S |
2368 | ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); |
2369 | ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); | |
f078f209 LR |
2370 | |
2371 | s1_s = REG_READ(ah, AR_ISR_S1_S); | |
2660b81a S |
2372 | ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); |
2373 | ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); | |
f078f209 LR |
2374 | } |
2375 | ||
2376 | if (isr & AR_ISR_RXORN) { | |
c46917bb LR |
2377 | ath_print(common, ATH_DBG_INTERRUPT, |
2378 | "receive FIFO overrun interrupt\n"); | |
f078f209 LR |
2379 | } |
2380 | ||
2381 | if (!AR_SREV_9100(ah)) { | |
60b67f51 | 2382 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
f078f209 LR |
2383 | u32 isr5 = REG_READ(ah, AR_ISR_S5_S); |
2384 | if (isr5 & AR_ISR_S5_TIM_TIMER) | |
2385 | *masked |= ATH9K_INT_TIM_TIMER; | |
2386 | } | |
2387 | } | |
2388 | ||
2389 | *masked |= mask2; | |
2390 | } | |
f1dc5600 | 2391 | |
f078f209 LR |
2392 | if (AR_SREV_9100(ah)) |
2393 | return true; | |
f1dc5600 | 2394 | |
ff155a45 VT |
2395 | if (isr & AR_ISR_GENTMR) { |
2396 | u32 s5_s; | |
2397 | ||
2398 | s5_s = REG_READ(ah, AR_ISR_S5_S); | |
2399 | if (isr & AR_ISR_GENTMR) { | |
2400 | ah->intr_gen_timer_trigger = | |
2401 | MS(s5_s, AR_ISR_S5_GENTIMER_TRIG); | |
2402 | ||
2403 | ah->intr_gen_timer_thresh = | |
2404 | MS(s5_s, AR_ISR_S5_GENTIMER_THRESH); | |
2405 | ||
2406 | if (ah->intr_gen_timer_trigger) | |
2407 | *masked |= ATH9K_INT_GENTIMER; | |
2408 | ||
2409 | } | |
2410 | } | |
2411 | ||
f078f209 LR |
2412 | if (sync_cause) { |
2413 | fatal_int = | |
2414 | (sync_cause & | |
2415 | (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) | |
2416 | ? true : false; | |
2417 | ||
2418 | if (fatal_int) { | |
2419 | if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { | |
c46917bb LR |
2420 | ath_print(common, ATH_DBG_ANY, |
2421 | "received PCI FATAL interrupt\n"); | |
f078f209 LR |
2422 | } |
2423 | if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { | |
c46917bb LR |
2424 | ath_print(common, ATH_DBG_ANY, |
2425 | "received PCI PERR interrupt\n"); | |
f078f209 | 2426 | } |
a89bff9a | 2427 | *masked |= ATH9K_INT_FATAL; |
f078f209 LR |
2428 | } |
2429 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { | |
c46917bb LR |
2430 | ath_print(common, ATH_DBG_INTERRUPT, |
2431 | "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); | |
f078f209 LR |
2432 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); |
2433 | REG_WRITE(ah, AR_RC, 0); | |
2434 | *masked |= ATH9K_INT_FATAL; | |
2435 | } | |
2436 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { | |
c46917bb LR |
2437 | ath_print(common, ATH_DBG_INTERRUPT, |
2438 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); | |
f078f209 LR |
2439 | } |
2440 | ||
2441 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); | |
2442 | (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); | |
2443 | } | |
f1dc5600 | 2444 | |
f078f209 LR |
2445 | return true; |
2446 | } | |
7322fd19 | 2447 | EXPORT_SYMBOL(ath9k_hw_getisr); |
f078f209 | 2448 | |
cbe61d8a | 2449 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) |
f078f209 | 2450 | { |
152d530d | 2451 | enum ath9k_int omask = ah->imask; |
f078f209 | 2452 | u32 mask, mask2; |
2660b81a | 2453 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
c46917bb | 2454 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 2455 | |
c46917bb | 2456 | ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); |
f078f209 LR |
2457 | |
2458 | if (omask & ATH9K_INT_GLOBAL) { | |
c46917bb | 2459 | ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n"); |
f078f209 LR |
2460 | REG_WRITE(ah, AR_IER, AR_IER_DISABLE); |
2461 | (void) REG_READ(ah, AR_IER); | |
2462 | if (!AR_SREV_9100(ah)) { | |
2463 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); | |
2464 | (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); | |
2465 | ||
2466 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); | |
2467 | (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); | |
2468 | } | |
2469 | } | |
2470 | ||
2471 | mask = ints & ATH9K_INT_COMMON; | |
2472 | mask2 = 0; | |
2473 | ||
2474 | if (ints & ATH9K_INT_TX) { | |
2660b81a | 2475 | if (ah->txok_interrupt_mask) |
f078f209 | 2476 | mask |= AR_IMR_TXOK; |
2660b81a | 2477 | if (ah->txdesc_interrupt_mask) |
f078f209 | 2478 | mask |= AR_IMR_TXDESC; |
2660b81a | 2479 | if (ah->txerr_interrupt_mask) |
f078f209 | 2480 | mask |= AR_IMR_TXERR; |
2660b81a | 2481 | if (ah->txeol_interrupt_mask) |
f078f209 LR |
2482 | mask |= AR_IMR_TXEOL; |
2483 | } | |
2484 | if (ints & ATH9K_INT_RX) { | |
2485 | mask |= AR_IMR_RXERR; | |
0ce024cb | 2486 | if (ah->config.rx_intr_mitigation) |
f078f209 LR |
2487 | mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; |
2488 | else | |
2489 | mask |= AR_IMR_RXOK | AR_IMR_RXDESC; | |
60b67f51 | 2490 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
f078f209 LR |
2491 | mask |= AR_IMR_GENTMR; |
2492 | } | |
2493 | ||
2494 | if (ints & (ATH9K_INT_BMISC)) { | |
2495 | mask |= AR_IMR_BCNMISC; | |
2496 | if (ints & ATH9K_INT_TIM) | |
2497 | mask2 |= AR_IMR_S2_TIM; | |
2498 | if (ints & ATH9K_INT_DTIM) | |
2499 | mask2 |= AR_IMR_S2_DTIM; | |
2500 | if (ints & ATH9K_INT_DTIMSYNC) | |
2501 | mask2 |= AR_IMR_S2_DTIMSYNC; | |
2502 | if (ints & ATH9K_INT_CABEND) | |
4af9cf4f S |
2503 | mask2 |= AR_IMR_S2_CABEND; |
2504 | if (ints & ATH9K_INT_TSFOOR) | |
2505 | mask2 |= AR_IMR_S2_TSFOOR; | |
f078f209 LR |
2506 | } |
2507 | ||
2508 | if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { | |
2509 | mask |= AR_IMR_BCNMISC; | |
2510 | if (ints & ATH9K_INT_GTT) | |
2511 | mask2 |= AR_IMR_S2_GTT; | |
2512 | if (ints & ATH9K_INT_CST) | |
2513 | mask2 |= AR_IMR_S2_CST; | |
2514 | } | |
2515 | ||
c46917bb | 2516 | ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); |
f078f209 | 2517 | REG_WRITE(ah, AR_IMR, mask); |
74bad5cb PR |
2518 | ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | |
2519 | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | | |
2520 | AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); | |
2521 | ah->imrs2_reg |= mask2; | |
2522 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); | |
f078f209 | 2523 | |
60b67f51 | 2524 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
f078f209 LR |
2525 | if (ints & ATH9K_INT_TIM_TIMER) |
2526 | REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); | |
2527 | else | |
2528 | REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); | |
2529 | } | |
2530 | ||
2531 | if (ints & ATH9K_INT_GLOBAL) { | |
c46917bb | 2532 | ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n"); |
f078f209 LR |
2533 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); |
2534 | if (!AR_SREV_9100(ah)) { | |
2535 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, | |
2536 | AR_INTR_MAC_IRQ); | |
2537 | REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); | |
2538 | ||
2539 | ||
2540 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, | |
2541 | AR_INTR_SYNC_DEFAULT); | |
2542 | REG_WRITE(ah, AR_INTR_SYNC_MASK, | |
2543 | AR_INTR_SYNC_DEFAULT); | |
2544 | } | |
c46917bb LR |
2545 | ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", |
2546 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); | |
f078f209 LR |
2547 | } |
2548 | ||
2549 | return omask; | |
2550 | } | |
7322fd19 | 2551 | EXPORT_SYMBOL(ath9k_hw_set_interrupts); |
f078f209 | 2552 | |
f1dc5600 S |
2553 | /*******************/ |
2554 | /* Beacon Handling */ | |
2555 | /*******************/ | |
2556 | ||
cbe61d8a | 2557 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
f078f209 | 2558 | { |
f078f209 LR |
2559 | int flags = 0; |
2560 | ||
2660b81a | 2561 | ah->beacon_interval = beacon_period; |
f078f209 | 2562 | |
2660b81a | 2563 | switch (ah->opmode) { |
d97809db CM |
2564 | case NL80211_IFTYPE_STATION: |
2565 | case NL80211_IFTYPE_MONITOR: | |
f078f209 LR |
2566 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
2567 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); | |
2568 | REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); | |
2569 | flags |= AR_TBTT_TIMER_EN; | |
2570 | break; | |
d97809db | 2571 | case NL80211_IFTYPE_ADHOC: |
9cb5412b | 2572 | case NL80211_IFTYPE_MESH_POINT: |
f078f209 LR |
2573 | REG_SET_BIT(ah, AR_TXCFG, |
2574 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); | |
2575 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, | |
2576 | TU_TO_USEC(next_beacon + | |
2660b81a S |
2577 | (ah->atim_window ? ah-> |
2578 | atim_window : 1))); | |
f078f209 | 2579 | flags |= AR_NDP_TIMER_EN; |
d97809db | 2580 | case NL80211_IFTYPE_AP: |
f078f209 LR |
2581 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
2582 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, | |
2583 | TU_TO_USEC(next_beacon - | |
2660b81a | 2584 | ah->config. |
60b67f51 | 2585 | dma_beacon_response_time)); |
f078f209 LR |
2586 | REG_WRITE(ah, AR_NEXT_SWBA, |
2587 | TU_TO_USEC(next_beacon - | |
2660b81a | 2588 | ah->config. |
60b67f51 | 2589 | sw_beacon_response_time)); |
f078f209 LR |
2590 | flags |= |
2591 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; | |
2592 | break; | |
d97809db | 2593 | default: |
c46917bb LR |
2594 | ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, |
2595 | "%s: unsupported opmode: %d\n", | |
2596 | __func__, ah->opmode); | |
d97809db CM |
2597 | return; |
2598 | break; | |
f078f209 LR |
2599 | } |
2600 | ||
2601 | REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | |
2602 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | |
2603 | REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); | |
2604 | REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); | |
2605 | ||
2606 | beacon_period &= ~ATH9K_BEACON_ENA; | |
2607 | if (beacon_period & ATH9K_BEACON_RESET_TSF) { | |
f078f209 LR |
2608 | ath9k_hw_reset_tsf(ah); |
2609 | } | |
2610 | ||
2611 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); | |
2612 | } | |
7322fd19 | 2613 | EXPORT_SYMBOL(ath9k_hw_beaconinit); |
f078f209 | 2614 | |
cbe61d8a | 2615 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
f1dc5600 | 2616 | const struct ath9k_beacon_state *bs) |
f078f209 LR |
2617 | { |
2618 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; | |
2660b81a | 2619 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
c46917bb | 2620 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
2621 | |
2622 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); | |
2623 | ||
2624 | REG_WRITE(ah, AR_BEACON_PERIOD, | |
2625 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | |
2626 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, | |
2627 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | |
2628 | ||
2629 | REG_RMW_FIELD(ah, AR_RSSI_THR, | |
2630 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); | |
2631 | ||
2632 | beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; | |
2633 | ||
2634 | if (bs->bs_sleepduration > beaconintval) | |
2635 | beaconintval = bs->bs_sleepduration; | |
2636 | ||
2637 | dtimperiod = bs->bs_dtimperiod; | |
2638 | if (bs->bs_sleepduration > dtimperiod) | |
2639 | dtimperiod = bs->bs_sleepduration; | |
2640 | ||
2641 | if (beaconintval == dtimperiod) | |
2642 | nextTbtt = bs->bs_nextdtim; | |
2643 | else | |
2644 | nextTbtt = bs->bs_nexttbtt; | |
2645 | ||
c46917bb LR |
2646 | ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
2647 | ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); | |
2648 | ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); | |
2649 | ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); | |
f078f209 | 2650 | |
f1dc5600 S |
2651 | REG_WRITE(ah, AR_NEXT_DTIM, |
2652 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); | |
2653 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); | |
f078f209 | 2654 | |
f1dc5600 S |
2655 | REG_WRITE(ah, AR_SLEEP1, |
2656 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) | |
2657 | | AR_SLEEP1_ASSUME_DTIM); | |
f078f209 | 2658 | |
f1dc5600 S |
2659 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
2660 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); | |
2661 | else | |
2662 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; | |
f078f209 | 2663 | |
f1dc5600 S |
2664 | REG_WRITE(ah, AR_SLEEP2, |
2665 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); | |
f078f209 | 2666 | |
f1dc5600 S |
2667 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); |
2668 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); | |
f078f209 | 2669 | |
f1dc5600 S |
2670 | REG_SET_BIT(ah, AR_TIMER_MODE, |
2671 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | | |
2672 | AR_DTIM_TIMER_EN); | |
f078f209 | 2673 | |
4af9cf4f S |
2674 | /* TSF Out of Range Threshold */ |
2675 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); | |
f078f209 | 2676 | } |
7322fd19 | 2677 | EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); |
f078f209 | 2678 | |
f1dc5600 S |
2679 | /*******************/ |
2680 | /* HW Capabilities */ | |
2681 | /*******************/ | |
2682 | ||
a9a29ce6 | 2683 | int ath9k_hw_fill_cap_info(struct ath_hw *ah) |
f078f209 | 2684 | { |
2660b81a | 2685 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
608b88cb | 2686 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
c46917bb | 2687 | struct ath_common *common = ath9k_hw_common(ah); |
766ec4a9 | 2688 | struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; |
608b88cb | 2689 | |
f1dc5600 | 2690 | u16 capField = 0, eeval; |
f078f209 | 2691 | |
f74df6fb | 2692 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
608b88cb | 2693 | regulatory->current_rd = eeval; |
f078f209 | 2694 | |
f74df6fb | 2695 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); |
fec0de11 S |
2696 | if (AR_SREV_9285_10_OR_LATER(ah)) |
2697 | eeval |= AR9285_RDEXT_DEFAULT; | |
608b88cb | 2698 | regulatory->current_rd_ext = eeval; |
f078f209 | 2699 | |
f74df6fb | 2700 | capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); |
f1dc5600 | 2701 | |
2660b81a | 2702 | if (ah->opmode != NL80211_IFTYPE_AP && |
d535a42a | 2703 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
608b88cb LR |
2704 | if (regulatory->current_rd == 0x64 || |
2705 | regulatory->current_rd == 0x65) | |
2706 | regulatory->current_rd += 5; | |
2707 | else if (regulatory->current_rd == 0x41) | |
2708 | regulatory->current_rd = 0x43; | |
c46917bb LR |
2709 | ath_print(common, ATH_DBG_REGULATORY, |
2710 | "regdomain mapped to 0x%x\n", regulatory->current_rd); | |
f1dc5600 | 2711 | } |
f078f209 | 2712 | |
f74df6fb | 2713 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
a9a29ce6 GJ |
2714 | if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { |
2715 | ath_print(common, ATH_DBG_FATAL, | |
2716 | "no band has been marked as supported in EEPROM.\n"); | |
2717 | return -EINVAL; | |
2718 | } | |
2719 | ||
f1dc5600 | 2720 | bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); |
f078f209 | 2721 | |
f1dc5600 S |
2722 | if (eeval & AR5416_OPFLAGS_11A) { |
2723 | set_bit(ATH9K_MODE_11A, pCap->wireless_modes); | |
2660b81a | 2724 | if (ah->config.ht_enable) { |
f1dc5600 S |
2725 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) |
2726 | set_bit(ATH9K_MODE_11NA_HT20, | |
2727 | pCap->wireless_modes); | |
2728 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { | |
2729 | set_bit(ATH9K_MODE_11NA_HT40PLUS, | |
2730 | pCap->wireless_modes); | |
2731 | set_bit(ATH9K_MODE_11NA_HT40MINUS, | |
2732 | pCap->wireless_modes); | |
2733 | } | |
f078f209 | 2734 | } |
f078f209 LR |
2735 | } |
2736 | ||
f1dc5600 | 2737 | if (eeval & AR5416_OPFLAGS_11G) { |
f1dc5600 | 2738 | set_bit(ATH9K_MODE_11G, pCap->wireless_modes); |
2660b81a | 2739 | if (ah->config.ht_enable) { |
f1dc5600 S |
2740 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) |
2741 | set_bit(ATH9K_MODE_11NG_HT20, | |
2742 | pCap->wireless_modes); | |
2743 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { | |
2744 | set_bit(ATH9K_MODE_11NG_HT40PLUS, | |
2745 | pCap->wireless_modes); | |
2746 | set_bit(ATH9K_MODE_11NG_HT40MINUS, | |
2747 | pCap->wireless_modes); | |
2748 | } | |
2749 | } | |
f078f209 | 2750 | } |
f1dc5600 | 2751 | |
f74df6fb | 2752 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
d7e7d229 LR |
2753 | /* |
2754 | * For AR9271 we will temporarilly uses the rx chainmax as read from | |
2755 | * the EEPROM. | |
2756 | */ | |
8147f5de | 2757 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
d7e7d229 LR |
2758 | !(eeval & AR5416_OPFLAGS_11A) && |
2759 | !(AR_SREV_9271(ah))) | |
2760 | /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ | |
8147f5de S |
2761 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; |
2762 | else | |
d7e7d229 | 2763 | /* Use rx_chainmask from EEPROM. */ |
8147f5de | 2764 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); |
f078f209 | 2765 | |
d535a42a | 2766 | if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) |
2660b81a | 2767 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
f078f209 | 2768 | |
f1dc5600 S |
2769 | pCap->low_2ghz_chan = 2312; |
2770 | pCap->high_2ghz_chan = 2732; | |
f078f209 | 2771 | |
f1dc5600 S |
2772 | pCap->low_5ghz_chan = 4920; |
2773 | pCap->high_5ghz_chan = 6100; | |
f078f209 | 2774 | |
f1dc5600 S |
2775 | pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; |
2776 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; | |
2777 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; | |
f078f209 | 2778 | |
f1dc5600 S |
2779 | pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; |
2780 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; | |
2781 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; | |
f078f209 | 2782 | |
2660b81a | 2783 | if (ah->config.ht_enable) |
f1dc5600 S |
2784 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
2785 | else | |
2786 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; | |
f078f209 | 2787 | |
f1dc5600 S |
2788 | pCap->hw_caps |= ATH9K_HW_CAP_GTT; |
2789 | pCap->hw_caps |= ATH9K_HW_CAP_VEOL; | |
2790 | pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; | |
2791 | pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; | |
f078f209 | 2792 | |
f1dc5600 S |
2793 | if (capField & AR_EEPROM_EEPCAP_MAXQCU) |
2794 | pCap->total_queues = | |
2795 | MS(capField, AR_EEPROM_EEPCAP_MAXQCU); | |
2796 | else | |
2797 | pCap->total_queues = ATH9K_NUM_TX_QUEUES; | |
f078f209 | 2798 | |
f1dc5600 S |
2799 | if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) |
2800 | pCap->keycache_size = | |
2801 | 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); | |
2802 | else | |
2803 | pCap->keycache_size = AR_KEYTABLE_SIZE; | |
f078f209 | 2804 | |
f1dc5600 | 2805 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; |
f4709fdf LR |
2806 | |
2807 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) | |
2808 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; | |
2809 | else | |
2810 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; | |
f078f209 | 2811 | |
5b5fa355 S |
2812 | if (AR_SREV_9271(ah)) |
2813 | pCap->num_gpio_pins = AR9271_NUM_GPIO; | |
2814 | else if (AR_SREV_9285_10_OR_LATER(ah)) | |
cb33c412 SB |
2815 | pCap->num_gpio_pins = AR9285_NUM_GPIO; |
2816 | else if (AR_SREV_9280_10_OR_LATER(ah)) | |
f1dc5600 S |
2817 | pCap->num_gpio_pins = AR928X_NUM_GPIO; |
2818 | else | |
2819 | pCap->num_gpio_pins = AR_NUM_GPIO; | |
f078f209 | 2820 | |
f1dc5600 S |
2821 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { |
2822 | pCap->hw_caps |= ATH9K_HW_CAP_CST; | |
2823 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; | |
2824 | } else { | |
2825 | pCap->rts_aggr_limit = (8 * 1024); | |
f078f209 LR |
2826 | } |
2827 | ||
f1dc5600 S |
2828 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; |
2829 | ||
e97275cb | 2830 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
2660b81a S |
2831 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
2832 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { | |
2833 | ah->rfkill_gpio = | |
2834 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); | |
2835 | ah->rfkill_polarity = | |
2836 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); | |
f1dc5600 S |
2837 | |
2838 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; | |
f078f209 | 2839 | } |
f1dc5600 | 2840 | #endif |
bde748a4 VN |
2841 | if (AR_SREV_9271(ah)) |
2842 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; | |
2843 | else | |
2844 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; | |
f078f209 | 2845 | |
e7594072 | 2846 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
f1dc5600 S |
2847 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
2848 | else | |
2849 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; | |
f078f209 | 2850 | |
608b88cb | 2851 | if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { |
f1dc5600 S |
2852 | pCap->reg_cap = |
2853 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | |
2854 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | | |
2855 | AR_EEPROM_EEREGCAP_EN_KK_U2 | | |
2856 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; | |
f078f209 | 2857 | } else { |
f1dc5600 S |
2858 | pCap->reg_cap = |
2859 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | |
2860 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; | |
f078f209 | 2861 | } |
f078f209 | 2862 | |
ebb90cfc SB |
2863 | /* Advertise midband for AR5416 with FCC midband set in eeprom */ |
2864 | if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && | |
2865 | AR_SREV_5416(ah)) | |
2866 | pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; | |
f1dc5600 S |
2867 | |
2868 | pCap->num_antcfg_5ghz = | |
f74df6fb | 2869 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); |
f1dc5600 | 2870 | pCap->num_antcfg_2ghz = |
f74df6fb | 2871 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); |
f078f209 | 2872 | |
fe12946e | 2873 | if (AR_SREV_9280_10_OR_LATER(ah) && |
a36cfbca | 2874 | ath9k_hw_btcoex_supported(ah)) { |
766ec4a9 LR |
2875 | btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; |
2876 | btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; | |
22f25d0d | 2877 | |
8c8f9ba7 | 2878 | if (AR_SREV_9285(ah)) { |
766ec4a9 LR |
2879 | btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; |
2880 | btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; | |
8c8f9ba7 | 2881 | } else { |
766ec4a9 | 2882 | btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; |
8c8f9ba7 | 2883 | } |
22f25d0d | 2884 | } else { |
766ec4a9 | 2885 | btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; |
c97c92d9 | 2886 | } |
a9a29ce6 GJ |
2887 | |
2888 | return 0; | |
f078f209 LR |
2889 | } |
2890 | ||
cbe61d8a | 2891 | bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
f1dc5600 | 2892 | u32 capability, u32 *result) |
f078f209 | 2893 | { |
608b88cb | 2894 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
f1dc5600 S |
2895 | switch (type) { |
2896 | case ATH9K_CAP_CIPHER: | |
2897 | switch (capability) { | |
2898 | case ATH9K_CIPHER_AES_CCM: | |
2899 | case ATH9K_CIPHER_AES_OCB: | |
2900 | case ATH9K_CIPHER_TKIP: | |
2901 | case ATH9K_CIPHER_WEP: | |
2902 | case ATH9K_CIPHER_MIC: | |
2903 | case ATH9K_CIPHER_CLR: | |
2904 | return true; | |
2905 | default: | |
2906 | return false; | |
2907 | } | |
2908 | case ATH9K_CAP_TKIP_MIC: | |
2909 | switch (capability) { | |
2910 | case 0: | |
2911 | return true; | |
2912 | case 1: | |
2660b81a | 2913 | return (ah->sta_id1_defaults & |
f1dc5600 S |
2914 | AR_STA_ID1_CRPT_MIC_ENABLE) ? true : |
2915 | false; | |
2916 | } | |
2917 | case ATH9K_CAP_TKIP_SPLIT: | |
2660b81a | 2918 | return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? |
f1dc5600 | 2919 | false : true; |
f1dc5600 S |
2920 | case ATH9K_CAP_MCAST_KEYSRCH: |
2921 | switch (capability) { | |
2922 | case 0: | |
2923 | return true; | |
2924 | case 1: | |
2925 | if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { | |
2926 | return false; | |
2927 | } else { | |
2660b81a | 2928 | return (ah->sta_id1_defaults & |
f1dc5600 S |
2929 | AR_STA_ID1_MCAST_KSRCH) ? true : |
2930 | false; | |
2931 | } | |
2932 | } | |
2933 | return false; | |
f1dc5600 S |
2934 | case ATH9K_CAP_TXPOW: |
2935 | switch (capability) { | |
2936 | case 0: | |
2937 | return 0; | |
2938 | case 1: | |
608b88cb | 2939 | *result = regulatory->power_limit; |
f1dc5600 S |
2940 | return 0; |
2941 | case 2: | |
608b88cb | 2942 | *result = regulatory->max_power_level; |
f1dc5600 S |
2943 | return 0; |
2944 | case 3: | |
608b88cb | 2945 | *result = regulatory->tp_scale; |
f1dc5600 S |
2946 | return 0; |
2947 | } | |
2948 | return false; | |
8bd1d07f SB |
2949 | case ATH9K_CAP_DS: |
2950 | return (AR_SREV_9280_20_OR_LATER(ah) && | |
2951 | (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1)) | |
2952 | ? false : true; | |
f1dc5600 S |
2953 | default: |
2954 | return false; | |
f078f209 | 2955 | } |
f078f209 | 2956 | } |
7322fd19 | 2957 | EXPORT_SYMBOL(ath9k_hw_getcapability); |
f078f209 | 2958 | |
cbe61d8a | 2959 | bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
f1dc5600 | 2960 | u32 capability, u32 setting, int *status) |
f078f209 | 2961 | { |
f1dc5600 S |
2962 | switch (type) { |
2963 | case ATH9K_CAP_TKIP_MIC: | |
2964 | if (setting) | |
2660b81a | 2965 | ah->sta_id1_defaults |= |
f1dc5600 S |
2966 | AR_STA_ID1_CRPT_MIC_ENABLE; |
2967 | else | |
2660b81a | 2968 | ah->sta_id1_defaults &= |
f1dc5600 S |
2969 | ~AR_STA_ID1_CRPT_MIC_ENABLE; |
2970 | return true; | |
f1dc5600 S |
2971 | case ATH9K_CAP_MCAST_KEYSRCH: |
2972 | if (setting) | |
2660b81a | 2973 | ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; |
f1dc5600 | 2974 | else |
2660b81a | 2975 | ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; |
f1dc5600 | 2976 | return true; |
f1dc5600 S |
2977 | default: |
2978 | return false; | |
f078f209 LR |
2979 | } |
2980 | } | |
7322fd19 | 2981 | EXPORT_SYMBOL(ath9k_hw_setcapability); |
f078f209 | 2982 | |
f1dc5600 S |
2983 | /****************************/ |
2984 | /* GPIO / RFKILL / Antennae */ | |
2985 | /****************************/ | |
f078f209 | 2986 | |
cbe61d8a | 2987 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, |
f1dc5600 S |
2988 | u32 gpio, u32 type) |
2989 | { | |
2990 | int addr; | |
2991 | u32 gpio_shift, tmp; | |
f078f209 | 2992 | |
f1dc5600 S |
2993 | if (gpio > 11) |
2994 | addr = AR_GPIO_OUTPUT_MUX3; | |
2995 | else if (gpio > 5) | |
2996 | addr = AR_GPIO_OUTPUT_MUX2; | |
2997 | else | |
2998 | addr = AR_GPIO_OUTPUT_MUX1; | |
f078f209 | 2999 | |
f1dc5600 | 3000 | gpio_shift = (gpio % 6) * 5; |
f078f209 | 3001 | |
f1dc5600 S |
3002 | if (AR_SREV_9280_20_OR_LATER(ah) |
3003 | || (addr != AR_GPIO_OUTPUT_MUX1)) { | |
3004 | REG_RMW(ah, addr, (type << gpio_shift), | |
3005 | (0x1f << gpio_shift)); | |
f078f209 | 3006 | } else { |
f1dc5600 S |
3007 | tmp = REG_READ(ah, addr); |
3008 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); | |
3009 | tmp &= ~(0x1f << gpio_shift); | |
3010 | tmp |= (type << gpio_shift); | |
3011 | REG_WRITE(ah, addr, tmp); | |
f078f209 | 3012 | } |
f078f209 LR |
3013 | } |
3014 | ||
cbe61d8a | 3015 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) |
f078f209 | 3016 | { |
f1dc5600 | 3017 | u32 gpio_shift; |
f078f209 | 3018 | |
9680e8a3 | 3019 | BUG_ON(gpio >= ah->caps.num_gpio_pins); |
f078f209 | 3020 | |
f1dc5600 | 3021 | gpio_shift = gpio << 1; |
f078f209 | 3022 | |
f1dc5600 S |
3023 | REG_RMW(ah, |
3024 | AR_GPIO_OE_OUT, | |
3025 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), | |
3026 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 | 3027 | } |
7322fd19 | 3028 | EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); |
f078f209 | 3029 | |
cbe61d8a | 3030 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
f078f209 | 3031 | { |
cb33c412 SB |
3032 | #define MS_REG_READ(x, y) \ |
3033 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) | |
3034 | ||
2660b81a | 3035 | if (gpio >= ah->caps.num_gpio_pins) |
f1dc5600 | 3036 | return 0xffffffff; |
f078f209 | 3037 | |
783dfca1 FF |
3038 | if (AR_SREV_9300_20_OR_LATER(ah)) |
3039 | return MS_REG_READ(AR9300, gpio) != 0; | |
3040 | else if (AR_SREV_9271(ah)) | |
5b5fa355 S |
3041 | return MS_REG_READ(AR9271, gpio) != 0; |
3042 | else if (AR_SREV_9287_10_OR_LATER(ah)) | |
ac88b6ec VN |
3043 | return MS_REG_READ(AR9287, gpio) != 0; |
3044 | else if (AR_SREV_9285_10_OR_LATER(ah)) | |
cb33c412 SB |
3045 | return MS_REG_READ(AR9285, gpio) != 0; |
3046 | else if (AR_SREV_9280_10_OR_LATER(ah)) | |
3047 | return MS_REG_READ(AR928X, gpio) != 0; | |
3048 | else | |
3049 | return MS_REG_READ(AR, gpio) != 0; | |
f078f209 | 3050 | } |
7322fd19 | 3051 | EXPORT_SYMBOL(ath9k_hw_gpio_get); |
f078f209 | 3052 | |
cbe61d8a | 3053 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
f1dc5600 | 3054 | u32 ah_signal_type) |
f078f209 | 3055 | { |
f1dc5600 | 3056 | u32 gpio_shift; |
f078f209 | 3057 | |
f1dc5600 | 3058 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
f078f209 | 3059 | |
f1dc5600 | 3060 | gpio_shift = 2 * gpio; |
f078f209 | 3061 | |
f1dc5600 S |
3062 | REG_RMW(ah, |
3063 | AR_GPIO_OE_OUT, | |
3064 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), | |
3065 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 | 3066 | } |
7322fd19 | 3067 | EXPORT_SYMBOL(ath9k_hw_cfg_output); |
f078f209 | 3068 | |
cbe61d8a | 3069 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
f078f209 | 3070 | { |
5b5fa355 S |
3071 | if (AR_SREV_9271(ah)) |
3072 | val = ~val; | |
3073 | ||
f1dc5600 S |
3074 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
3075 | AR_GPIO_BIT(gpio)); | |
f078f209 | 3076 | } |
7322fd19 | 3077 | EXPORT_SYMBOL(ath9k_hw_set_gpio); |
f078f209 | 3078 | |
cbe61d8a | 3079 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah) |
f078f209 | 3080 | { |
f1dc5600 | 3081 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; |
f078f209 | 3082 | } |
7322fd19 | 3083 | EXPORT_SYMBOL(ath9k_hw_getdefantenna); |
f078f209 | 3084 | |
cbe61d8a | 3085 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
f078f209 | 3086 | { |
f1dc5600 | 3087 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
f078f209 | 3088 | } |
7322fd19 | 3089 | EXPORT_SYMBOL(ath9k_hw_setantenna); |
f078f209 | 3090 | |
f1dc5600 S |
3091 | /*********************/ |
3092 | /* General Operation */ | |
3093 | /*********************/ | |
3094 | ||
cbe61d8a | 3095 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
f078f209 | 3096 | { |
f1dc5600 S |
3097 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
3098 | u32 phybits = REG_READ(ah, AR_PHY_ERR); | |
f078f209 | 3099 | |
f1dc5600 S |
3100 | if (phybits & AR_PHY_ERR_RADAR) |
3101 | bits |= ATH9K_RX_FILTER_PHYRADAR; | |
3102 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) | |
3103 | bits |= ATH9K_RX_FILTER_PHYERR; | |
dc2222a8 | 3104 | |
f1dc5600 | 3105 | return bits; |
f078f209 | 3106 | } |
7322fd19 | 3107 | EXPORT_SYMBOL(ath9k_hw_getrxfilter); |
f078f209 | 3108 | |
cbe61d8a | 3109 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
f078f209 | 3110 | { |
f1dc5600 | 3111 | u32 phybits; |
f078f209 | 3112 | |
7ea310be S |
3113 | REG_WRITE(ah, AR_RX_FILTER, bits); |
3114 | ||
f1dc5600 S |
3115 | phybits = 0; |
3116 | if (bits & ATH9K_RX_FILTER_PHYRADAR) | |
3117 | phybits |= AR_PHY_ERR_RADAR; | |
3118 | if (bits & ATH9K_RX_FILTER_PHYERR) | |
3119 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; | |
3120 | REG_WRITE(ah, AR_PHY_ERR, phybits); | |
f078f209 | 3121 | |
f1dc5600 S |
3122 | if (phybits) |
3123 | REG_WRITE(ah, AR_RXCFG, | |
3124 | REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); | |
3125 | else | |
3126 | REG_WRITE(ah, AR_RXCFG, | |
3127 | REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); | |
3128 | } | |
7322fd19 | 3129 | EXPORT_SYMBOL(ath9k_hw_setrxfilter); |
f078f209 | 3130 | |
cbe61d8a | 3131 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
f1dc5600 | 3132 | { |
63a75b91 SB |
3133 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
3134 | return false; | |
3135 | ||
3136 | ath9k_hw_init_pll(ah, NULL); | |
3137 | return true; | |
f1dc5600 | 3138 | } |
7322fd19 | 3139 | EXPORT_SYMBOL(ath9k_hw_phy_disable); |
f078f209 | 3140 | |
cbe61d8a | 3141 | bool ath9k_hw_disable(struct ath_hw *ah) |
f1dc5600 | 3142 | { |
9ecdef4b | 3143 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 3144 | return false; |
f078f209 | 3145 | |
63a75b91 SB |
3146 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) |
3147 | return false; | |
3148 | ||
3149 | ath9k_hw_init_pll(ah, NULL); | |
3150 | return true; | |
f078f209 | 3151 | } |
7322fd19 | 3152 | EXPORT_SYMBOL(ath9k_hw_disable); |
f078f209 | 3153 | |
8fbff4b8 | 3154 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) |
f078f209 | 3155 | { |
608b88cb | 3156 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
2660b81a | 3157 | struct ath9k_channel *chan = ah->curchan; |
5f8e077c | 3158 | struct ieee80211_channel *channel = chan->chan; |
f078f209 | 3159 | |
608b88cb | 3160 | regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); |
6f255425 | 3161 | |
8fbff4b8 | 3162 | ah->eep_ops->set_txpower(ah, chan, |
608b88cb | 3163 | ath9k_regd_get_ctl(regulatory, chan), |
8fbff4b8 VT |
3164 | channel->max_antenna_gain * 2, |
3165 | channel->max_power * 2, | |
3166 | min((u32) MAX_RATE_POWER, | |
608b88cb | 3167 | (u32) regulatory->power_limit)); |
6f255425 | 3168 | } |
7322fd19 | 3169 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
6f255425 | 3170 | |
cbe61d8a | 3171 | void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) |
f078f209 | 3172 | { |
1510718d | 3173 | memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN); |
f078f209 | 3174 | } |
7322fd19 | 3175 | EXPORT_SYMBOL(ath9k_hw_setmac); |
f078f209 | 3176 | |
cbe61d8a | 3177 | void ath9k_hw_setopmode(struct ath_hw *ah) |
f078f209 | 3178 | { |
2660b81a | 3179 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
f078f209 | 3180 | } |
7322fd19 | 3181 | EXPORT_SYMBOL(ath9k_hw_setopmode); |
f078f209 | 3182 | |
cbe61d8a | 3183 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
f078f209 | 3184 | { |
f1dc5600 S |
3185 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
3186 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); | |
f078f209 | 3187 | } |
7322fd19 | 3188 | EXPORT_SYMBOL(ath9k_hw_setmcastfilter); |
f078f209 | 3189 | |
f2b2143e | 3190 | void ath9k_hw_write_associd(struct ath_hw *ah) |
f078f209 | 3191 | { |
1510718d LR |
3192 | struct ath_common *common = ath9k_hw_common(ah); |
3193 | ||
3194 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); | |
3195 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | | |
3196 | ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); | |
f078f209 | 3197 | } |
7322fd19 | 3198 | EXPORT_SYMBOL(ath9k_hw_write_associd); |
f078f209 | 3199 | |
cbe61d8a | 3200 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
f078f209 | 3201 | { |
f1dc5600 | 3202 | u64 tsf; |
f078f209 | 3203 | |
f1dc5600 S |
3204 | tsf = REG_READ(ah, AR_TSF_U32); |
3205 | tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); | |
f078f209 | 3206 | |
f1dc5600 S |
3207 | return tsf; |
3208 | } | |
7322fd19 | 3209 | EXPORT_SYMBOL(ath9k_hw_gettsf64); |
f078f209 | 3210 | |
cbe61d8a | 3211 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
27abe060 | 3212 | { |
27abe060 | 3213 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
b9a16197 | 3214 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
27abe060 | 3215 | } |
7322fd19 | 3216 | EXPORT_SYMBOL(ath9k_hw_settsf64); |
27abe060 | 3217 | |
cbe61d8a | 3218 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
f1dc5600 | 3219 | { |
f9b604f6 GJ |
3220 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
3221 | AH_TSF_WRITE_TIMEOUT)) | |
c46917bb LR |
3222 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
3223 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); | |
f9b604f6 | 3224 | |
f1dc5600 S |
3225 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
3226 | } | |
7322fd19 | 3227 | EXPORT_SYMBOL(ath9k_hw_reset_tsf); |
f078f209 | 3228 | |
54e4cec6 | 3229 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) |
f1dc5600 | 3230 | { |
f1dc5600 | 3231 | if (setting) |
2660b81a | 3232 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
f1dc5600 | 3233 | else |
2660b81a | 3234 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
f1dc5600 | 3235 | } |
7322fd19 | 3236 | EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); |
f078f209 | 3237 | |
30cbd422 LR |
3238 | /* |
3239 | * Extend 15-bit time stamp from rx descriptor to | |
3240 | * a full 64-bit TSF using the current h/w TSF. | |
3241 | */ | |
3242 | u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp) | |
3243 | { | |
3244 | u64 tsf; | |
3245 | ||
3246 | tsf = ath9k_hw_gettsf64(ah); | |
3247 | if ((tsf & 0x7fff) < rstamp) | |
3248 | tsf -= 0x8000; | |
3249 | return (tsf & ~0x7fff) | rstamp; | |
3250 | } | |
3251 | EXPORT_SYMBOL(ath9k_hw_extend_tsf); | |
3252 | ||
25c56eec | 3253 | void ath9k_hw_set11nmac2040(struct ath_hw *ah) |
f1dc5600 | 3254 | { |
25c56eec | 3255 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
f1dc5600 S |
3256 | u32 macmode; |
3257 | ||
25c56eec | 3258 | if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) |
f1dc5600 S |
3259 | macmode = AR_2040_JOINED_RX_CLEAR; |
3260 | else | |
3261 | macmode = 0; | |
f078f209 | 3262 | |
f1dc5600 | 3263 | REG_WRITE(ah, AR_2040_MODE, macmode); |
f078f209 | 3264 | } |
ff155a45 VT |
3265 | |
3266 | /* HW Generic timers configuration */ | |
3267 | ||
3268 | static const struct ath_gen_timer_configuration gen_tmr_configuration[] = | |
3269 | { | |
3270 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3271 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3272 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3273 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3274 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3275 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3276 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3277 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3278 | {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, | |
3279 | {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, | |
3280 | AR_NDP2_TIMER_MODE, 0x0002}, | |
3281 | {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, | |
3282 | AR_NDP2_TIMER_MODE, 0x0004}, | |
3283 | {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, | |
3284 | AR_NDP2_TIMER_MODE, 0x0008}, | |
3285 | {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, | |
3286 | AR_NDP2_TIMER_MODE, 0x0010}, | |
3287 | {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, | |
3288 | AR_NDP2_TIMER_MODE, 0x0020}, | |
3289 | {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, | |
3290 | AR_NDP2_TIMER_MODE, 0x0040}, | |
3291 | {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, | |
3292 | AR_NDP2_TIMER_MODE, 0x0080} | |
3293 | }; | |
3294 | ||
3295 | /* HW generic timer primitives */ | |
3296 | ||
3297 | /* compute and clear index of rightmost 1 */ | |
3298 | static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) | |
3299 | { | |
3300 | u32 b; | |
3301 | ||
3302 | b = *mask; | |
3303 | b &= (0-b); | |
3304 | *mask &= ~b; | |
3305 | b *= debruijn32; | |
3306 | b >>= 27; | |
3307 | ||
3308 | return timer_table->gen_timer_index[b]; | |
3309 | } | |
3310 | ||
1773912b | 3311 | u32 ath9k_hw_gettsf32(struct ath_hw *ah) |
ff155a45 VT |
3312 | { |
3313 | return REG_READ(ah, AR_TSF_L32); | |
3314 | } | |
7322fd19 | 3315 | EXPORT_SYMBOL(ath9k_hw_gettsf32); |
ff155a45 VT |
3316 | |
3317 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
3318 | void (*trigger)(void *), | |
3319 | void (*overflow)(void *), | |
3320 | void *arg, | |
3321 | u8 timer_index) | |
3322 | { | |
3323 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3324 | struct ath_gen_timer *timer; | |
3325 | ||
3326 | timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); | |
3327 | ||
3328 | if (timer == NULL) { | |
c46917bb LR |
3329 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
3330 | "Failed to allocate memory" | |
3331 | "for hw timer[%d]\n", timer_index); | |
ff155a45 VT |
3332 | return NULL; |
3333 | } | |
3334 | ||
3335 | /* allocate a hardware generic timer slot */ | |
3336 | timer_table->timers[timer_index] = timer; | |
3337 | timer->index = timer_index; | |
3338 | timer->trigger = trigger; | |
3339 | timer->overflow = overflow; | |
3340 | timer->arg = arg; | |
3341 | ||
3342 | return timer; | |
3343 | } | |
7322fd19 | 3344 | EXPORT_SYMBOL(ath_gen_timer_alloc); |
ff155a45 | 3345 | |
cd9bf689 LR |
3346 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
3347 | struct ath_gen_timer *timer, | |
3348 | u32 timer_next, | |
3349 | u32 timer_period) | |
ff155a45 VT |
3350 | { |
3351 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3352 | u32 tsf; | |
3353 | ||
3354 | BUG_ON(!timer_period); | |
3355 | ||
3356 | set_bit(timer->index, &timer_table->timer_mask.timer_bits); | |
3357 | ||
3358 | tsf = ath9k_hw_gettsf32(ah); | |
3359 | ||
c46917bb LR |
3360 | ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, |
3361 | "curent tsf %x period %x" | |
3362 | "timer_next %x\n", tsf, timer_period, timer_next); | |
ff155a45 VT |
3363 | |
3364 | /* | |
3365 | * Pull timer_next forward if the current TSF already passed it | |
3366 | * because of software latency | |
3367 | */ | |
3368 | if (timer_next < tsf) | |
3369 | timer_next = tsf + timer_period; | |
3370 | ||
3371 | /* | |
3372 | * Program generic timer registers | |
3373 | */ | |
3374 | REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, | |
3375 | timer_next); | |
3376 | REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, | |
3377 | timer_period); | |
3378 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
3379 | gen_tmr_configuration[timer->index].mode_mask); | |
3380 | ||
3381 | /* Enable both trigger and thresh interrupt masks */ | |
3382 | REG_SET_BIT(ah, AR_IMR_S5, | |
3383 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | |
3384 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); | |
ff155a45 | 3385 | } |
7322fd19 | 3386 | EXPORT_SYMBOL(ath9k_hw_gen_timer_start); |
ff155a45 | 3387 | |
cd9bf689 | 3388 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) |
ff155a45 VT |
3389 | { |
3390 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3391 | ||
3392 | if ((timer->index < AR_FIRST_NDP_TIMER) || | |
3393 | (timer->index >= ATH_MAX_GEN_TIMER)) { | |
3394 | return; | |
3395 | } | |
3396 | ||
3397 | /* Clear generic timer enable bits. */ | |
3398 | REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
3399 | gen_tmr_configuration[timer->index].mode_mask); | |
3400 | ||
3401 | /* Disable both trigger and thresh interrupt masks */ | |
3402 | REG_CLR_BIT(ah, AR_IMR_S5, | |
3403 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | |
3404 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); | |
3405 | ||
3406 | clear_bit(timer->index, &timer_table->timer_mask.timer_bits); | |
ff155a45 | 3407 | } |
7322fd19 | 3408 | EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); |
ff155a45 VT |
3409 | |
3410 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) | |
3411 | { | |
3412 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3413 | ||
3414 | /* free the hardware generic timer slot */ | |
3415 | timer_table->timers[timer->index] = NULL; | |
3416 | kfree(timer); | |
3417 | } | |
7322fd19 | 3418 | EXPORT_SYMBOL(ath_gen_timer_free); |
ff155a45 VT |
3419 | |
3420 | /* | |
3421 | * Generic Timer Interrupts handling | |
3422 | */ | |
3423 | void ath_gen_timer_isr(struct ath_hw *ah) | |
3424 | { | |
3425 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3426 | struct ath_gen_timer *timer; | |
c46917bb | 3427 | struct ath_common *common = ath9k_hw_common(ah); |
ff155a45 VT |
3428 | u32 trigger_mask, thresh_mask, index; |
3429 | ||
3430 | /* get hardware generic timer interrupt status */ | |
3431 | trigger_mask = ah->intr_gen_timer_trigger; | |
3432 | thresh_mask = ah->intr_gen_timer_thresh; | |
3433 | trigger_mask &= timer_table->timer_mask.val; | |
3434 | thresh_mask &= timer_table->timer_mask.val; | |
3435 | ||
3436 | trigger_mask &= ~thresh_mask; | |
3437 | ||
3438 | while (thresh_mask) { | |
3439 | index = rightmost_index(timer_table, &thresh_mask); | |
3440 | timer = timer_table->timers[index]; | |
3441 | BUG_ON(!timer); | |
c46917bb LR |
3442 | ath_print(common, ATH_DBG_HWTIMER, |
3443 | "TSF overflow for Gen timer %d\n", index); | |
ff155a45 VT |
3444 | timer->overflow(timer->arg); |
3445 | } | |
3446 | ||
3447 | while (trigger_mask) { | |
3448 | index = rightmost_index(timer_table, &trigger_mask); | |
3449 | timer = timer_table->timers[index]; | |
3450 | BUG_ON(!timer); | |
c46917bb LR |
3451 | ath_print(common, ATH_DBG_HWTIMER, |
3452 | "Gen timer[%d] trigger\n", index); | |
ff155a45 VT |
3453 | timer->trigger(timer->arg); |
3454 | } | |
3455 | } | |
7322fd19 | 3456 | EXPORT_SYMBOL(ath_gen_timer_isr); |
2da4f01a | 3457 | |
05020d23 S |
3458 | /********/ |
3459 | /* HTC */ | |
3460 | /********/ | |
3461 | ||
3462 | void ath9k_hw_htc_resetinit(struct ath_hw *ah) | |
3463 | { | |
3464 | ah->htc_reset_init = true; | |
3465 | } | |
3466 | EXPORT_SYMBOL(ath9k_hw_htc_resetinit); | |
3467 | ||
2da4f01a LR |
3468 | static struct { |
3469 | u32 version; | |
3470 | const char * name; | |
3471 | } ath_mac_bb_names[] = { | |
3472 | /* Devices with external radios */ | |
3473 | { AR_SREV_VERSION_5416_PCI, "5416" }, | |
3474 | { AR_SREV_VERSION_5416_PCIE, "5418" }, | |
3475 | { AR_SREV_VERSION_9100, "9100" }, | |
3476 | { AR_SREV_VERSION_9160, "9160" }, | |
3477 | /* Single-chip solutions */ | |
3478 | { AR_SREV_VERSION_9280, "9280" }, | |
3479 | { AR_SREV_VERSION_9285, "9285" }, | |
11158472 LR |
3480 | { AR_SREV_VERSION_9287, "9287" }, |
3481 | { AR_SREV_VERSION_9271, "9271" }, | |
2da4f01a LR |
3482 | }; |
3483 | ||
3484 | /* For devices with external radios */ | |
3485 | static struct { | |
3486 | u16 version; | |
3487 | const char * name; | |
3488 | } ath_rf_names[] = { | |
3489 | { 0, "5133" }, | |
3490 | { AR_RAD5133_SREV_MAJOR, "5133" }, | |
3491 | { AR_RAD5122_SREV_MAJOR, "5122" }, | |
3492 | { AR_RAD2133_SREV_MAJOR, "2133" }, | |
3493 | { AR_RAD2122_SREV_MAJOR, "2122" } | |
3494 | }; | |
3495 | ||
3496 | /* | |
3497 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. | |
3498 | */ | |
f934c4d9 | 3499 | static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) |
2da4f01a LR |
3500 | { |
3501 | int i; | |
3502 | ||
3503 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { | |
3504 | if (ath_mac_bb_names[i].version == mac_bb_version) { | |
3505 | return ath_mac_bb_names[i].name; | |
3506 | } | |
3507 | } | |
3508 | ||
3509 | return "????"; | |
3510 | } | |
2da4f01a LR |
3511 | |
3512 | /* | |
3513 | * Return the RF name. "????" is returned if the RF is unknown. | |
3514 | * Used for devices with external radios. | |
3515 | */ | |
f934c4d9 | 3516 | static const char *ath9k_hw_rf_name(u16 rf_version) |
2da4f01a LR |
3517 | { |
3518 | int i; | |
3519 | ||
3520 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { | |
3521 | if (ath_rf_names[i].version == rf_version) { | |
3522 | return ath_rf_names[i].name; | |
3523 | } | |
3524 | } | |
3525 | ||
3526 | return "????"; | |
3527 | } | |
f934c4d9 LR |
3528 | |
3529 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) | |
3530 | { | |
3531 | int used; | |
3532 | ||
3533 | /* chipsets >= AR9280 are single-chip */ | |
3534 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
3535 | used = snprintf(hw_name, len, | |
3536 | "Atheros AR%s Rev:%x", | |
3537 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
3538 | ah->hw_version.macRev); | |
3539 | } | |
3540 | else { | |
3541 | used = snprintf(hw_name, len, | |
3542 | "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", | |
3543 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
3544 | ah->hw_version.macRev, | |
3545 | ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & | |
3546 | AR_RADIO_SREV_MAJOR)), | |
3547 | ah->hw_version.phyRev); | |
3548 | } | |
3549 | ||
3550 | hw_name[used] = '\0'; | |
3551 | } | |
3552 | EXPORT_SYMBOL(ath9k_hw_name); | |
d70357d5 LR |
3553 | |
3554 | /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */ | |
3555 | static void ar9002_hw_attach_ops(struct ath_hw *ah) | |
3556 | { | |
3557 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | |
3558 | struct ath_hw_ops *ops = ath9k_hw_ops(ah); | |
3559 | ||
3560 | priv_ops->init_cal_settings = ar9002_hw_init_cal_settings; | |
3561 | priv_ops->init_mode_regs = ar9002_hw_init_mode_regs; | |
3562 | priv_ops->macversion_supported = ar9002_hw_macversion_supported; | |
3563 | ||
3564 | ops->config_pci_powersave = ar9002_hw_configpcipowersave; | |
8fe65368 LR |
3565 | |
3566 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
3567 | ar9002_hw_attach_phy_ops(ah); | |
3568 | else | |
3569 | ar5008_hw_attach_phy_ops(ah); | |
d70357d5 | 3570 | } |