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ath9k: Move private HW callbacks to hw-ops.h
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
f078f209
LR		 22#include <asm/unaligned.h>
23
af03abec 24#include "hw.h"
d70357d5 25#include "hw-ops.h"
cfe8cba9 26#include "rc.h"
b622a720 27#include "ar9003_mac.h"
f4701b5a 28#include "ar9003_mci.h"
362cd03f 29#include "ar9003_phy.h"
462e58f2
BG		 30#include "debug.h"
31#include "ath9k.h"
f078f209 32
cbe61d8a 33static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 34
7322fd19
LR		 35MODULE_AUTHOR("Atheros Communications");
36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38MODULE_LICENSE("Dual BSD/GPL");
39
dfdac8ac 40static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 41{
dfdac8ac 42 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 43 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 44 unsigned int clockrate;
cbe61d8a 45
087b6ff6
FF		 46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
48 clockrate = 117;
e4744ec7 49 else if (!chan) /* should really check for CCK instead */
dfdac8ac 50 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 51 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 55 else
dfdac8ac
FF		 56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
57
beae416b
MN		 58 if (chan) {
59 if (IS_CHAN_HT40(chan))
60 clockrate *= 2;
e4744ec7 61 if (IS_CHAN_HALF_RATE(chan))
906c7205 62 clockrate /= 2;
e4744ec7 63 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 64 clockrate /= 4;
65 }
66
dfdac8ac 67 common->clockrate = clockrate;
f1dc5600
S		 68}
69
cbe61d8a 70static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 71{
dfdac8ac 72 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 73
dfdac8ac 74 return usecs * common->clockrate;
f1dc5600 75}
f078f209 76
0caa7b14 77bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 78{
79 int i;
80
0caa7b14
S		 81 BUG_ON(timeout < AH_TIME_QUANTUM);
82
83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 84 if ((REG_READ(ah, reg) & mask) == val)
85 return true;
86
87 udelay(AH_TIME_QUANTUM);
88 }
04bd4638 89
d2182b69 90 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
92 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 93
f1dc5600 94 return false;
f078f209 95}
7322fd19 96EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 97
7c5adc8d
FF		 98void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
99 int hw_delay)
100{
1a5e6326 101 hw_delay /= 10;
7c5adc8d
FF		 102
103 if (IS_CHAN_HALF_RATE(chan))
104 hw_delay *= 2;
105 else if (IS_CHAN_QUARTER_RATE(chan))
106 hw_delay *= 4;
107
108 udelay(hw_delay + BASE_ACTIVATE_DELAY);
109}
110
0166b4be 111void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 112 int column, unsigned int *writecnt)
113{
114 int r;
115
116 ENABLE_REGWRITE_BUFFER(ah);
117 for (r = 0; r < array->ia_rows; r++) {
118 REG_WRITE(ah, INI_RA(array, r, 0),
119 INI_RA(array, r, column));
120 DO_DELAY(*writecnt);
121 }
122 REGWRITE_BUFFER_FLUSH(ah);
123}
124
f078f209
LR		 125u32 ath9k_hw_reverse_bits(u32 val, u32 n)
126{
127 u32 retval;
128 int i;
129
130 for (i = 0, retval = 0; i < n; i++) {
131 retval = (retval << 1) | (val & 1);
132 val >>= 1;
133 }
134 return retval;
135}
136
cbe61d8a 137u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 138 u8 phy, int kbps,
f1dc5600
S		 139 u32 frameLen, u16 rateix,
140 bool shortPreamble)
f078f209 141{
f1dc5600 142 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 143
f1dc5600
S		 144 if (kbps == 0)
145 return 0;
f078f209 146
545750d3 147 switch (phy) {
46d14a58 148 case WLAN_RC_PHY_CCK:
f1dc5600 149 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 150 if (shortPreamble)
f1dc5600
S		 151 phyTime >>= 1;
152 numBits = frameLen << 3;
153 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
154 break;
46d14a58 155 case WLAN_RC_PHY_OFDM:
2660b81a 156 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 157 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
158 numBits = OFDM_PLCP_BITS + (frameLen << 3);
159 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
160 txTime = OFDM_SIFS_TIME_QUARTER
161 + OFDM_PREAMBLE_TIME_QUARTER
162 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 163 } else if (ah->curchan &&
164 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 165 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
166 numBits = OFDM_PLCP_BITS + (frameLen << 3);
167 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
168 txTime = OFDM_SIFS_TIME_HALF +
169 OFDM_PREAMBLE_TIME_HALF
170 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
171 } else {
172 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
173 numBits = OFDM_PLCP_BITS + (frameLen << 3);
174 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
175 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
176 + (numSymbols * OFDM_SYMBOL_TIME);
177 }
178 break;
179 default:
3800276a
JP		 180 ath_err(ath9k_hw_common(ah),
181 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 182 txTime = 0;
183 break;
184 }
f078f209 185
f1dc5600
S		 186 return txTime;
187}
7322fd19 188EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 189
cbe61d8a 190void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 191 struct ath9k_channel *chan,
192 struct chan_centers *centers)
f078f209 193{
f1dc5600 194 int8_t extoff;
f078f209 195
f1dc5600
S		 196 if (!IS_CHAN_HT40(chan)) {
197 centers->ctl_center = centers->ext_center =
198 centers->synth_center = chan->channel;
199 return;
f078f209 200 }
f078f209 201
8896934c 202 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 203 centers->synth_center =
204 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
205 extoff = 1;
206 } else {
207 centers->synth_center =
208 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
209 extoff = -1;
210 }
f078f209 211
f1dc5600
S		 212 centers->ctl_center =
213 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 214 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 215 centers->ext_center =
6420014c 216 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 217}
218
f1dc5600
S		 219/******************/
220/* Chip Revisions */
221/******************/
222
cbe61d8a 223static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 224{
f1dc5600 225 u32 val;
f078f209 226
ecb1d385
VT		 227 switch (ah->hw_version.devid) {
228 case AR5416_AR9100_DEVID:
229 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
230 break;
3762561a
GJ		 231 case AR9300_DEVID_AR9330:
232 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
233 if (ah->get_mac_revision) {
234 ah->hw_version.macRev = ah->get_mac_revision();
235 } else {
236 val = REG_READ(ah, AR_SREV);
237 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
238 }
239 return;
ecb1d385
VT		 240 case AR9300_DEVID_AR9340:
241 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
242 val = REG_READ(ah, AR_SREV);
243 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
244 return;
813831dc
GJ		 245 case AR9300_DEVID_QCA955X:
246 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
247 return;
ecb1d385
VT		 248 }
249
f1dc5600 250 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 251
f1dc5600
S		 252 if (val == 0xFF) {
253 val = REG_READ(ah, AR_SREV);
d535a42a
S		 254 ah->hw_version.macVersion =
255 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
256 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 257
77fac465 258 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 259 ah->is_pciexpress = true;
260 else
261 ah->is_pciexpress = (val &
262 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 263 } else {
264 if (!AR_SREV_9100(ah))
d535a42a 265 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 266
d535a42a 267 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 268
d535a42a 269 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 270 ah->is_pciexpress = true;
f1dc5600 271 }
f078f209
LR		 272}
273
f1dc5600
S		 274/************************************/
275/* HW Attach, Detach, Init Routines */
276/************************************/
277
cbe61d8a 278static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 279{
040b74f7 280 if (!AR_SREV_5416(ah))
f1dc5600 281 return;
f078f209 282
f1dc5600
S		 283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 292
f1dc5600 293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 294}
295
1f3f0618 296/* This should work for all families including legacy */
cbe61d8a 297static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 298{
c46917bb 299 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 300 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 301 u32 regHold[2];
07b2fa5a
JP		 302 static const u32 patternData[4] = {
303 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
304 };
1f3f0618 305 int i, j, loop_max;
f078f209 306
1f3f0618
SB		 307 if (!AR_SREV_9300_20_OR_LATER(ah)) {
308 loop_max = 2;
309 regAddr[1] = AR_PHY_BASE + (8 << 2);
310 } else
311 loop_max = 1;
312
313 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 314 u32 addr = regAddr[i];
315 u32 wrData, rdData;
f078f209 316
f1dc5600
S		 317 regHold[i] = REG_READ(ah, addr);
318 for (j = 0; j < 0x100; j++) {
319 wrData = (j << 16) | j;
320 REG_WRITE(ah, addr, wrData);
321 rdData = REG_READ(ah, addr);
322 if (rdData != wrData) {
3800276a
JP		 323 ath_err(common,
324 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
325 addr, wrData, rdData);
f1dc5600
S		 326 return false;
327 }
328 }
329 for (j = 0; j < 4; j++) {
330 wrData = patternData[j];
331 REG_WRITE(ah, addr, wrData);
332 rdData = REG_READ(ah, addr);
333 if (wrData != rdData) {
3800276a
JP		 334 ath_err(common,
335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
336 addr, wrData, rdData);
f1dc5600
S		 337 return false;
338 }
f078f209 339 }
f1dc5600 340 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 341 }
f1dc5600 342 udelay(100);
cbe61d8a 343
f078f209
LR		 344 return true;
345}
346
b8b0f377 347static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 348{
689e756f
FF		 349 ah->config.dma_beacon_response_time = 1;
350 ah->config.sw_beacon_response_time = 6;
2660b81a
S		 351 ah->config.ack_6mb = 0x0;
352 ah->config.cwm_ignore_extcca = 0;
2660b81a 353 ah->config.analog_shiftreg = 1;
f078f209 354
0ce024cb 355 ah->config.rx_intr_mitigation = true;
6158425b
LR		 356
357 /*
358 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
359 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
360 * This means we use it for all AR5416 devices, and the few
361 * minor PCI AR9280 devices out there.
362 *
363 * Serialization is required because these devices do not handle
364 * well the case of two concurrent reads/writes due to the latency
365 * involved. During one read/write another read/write can be issued
366 * on another CPU while the previous read/write may still be working
367 * on our hardware, if we hit this case the hardware poops in a loop.
368 * We prevent this by serializing reads and writes.
369 *
370 * This issue is not present on PCI-Express devices or pre-AR5416
371 * devices (legacy, 802.11abg).
372 */
373 if (num_possible_cpus() > 1)
2d6a5e95 374 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 375}
376
50aca25b 377static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 378{
608b88cb
LR		 379 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
380
381 regulatory->country_code = CTRY_DEFAULT;
382 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 383
d535a42a 384 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 385 ah->hw_version.subvendorid = 0;
f078f209 386
16f2411f
FF		 387 ah->sta_id1_defaults =
388 AR_STA_ID1_CRPT_MIC_ENABLE |
389 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 390 if (AR_SREV_9100(ah))
391 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
e3f2acc7 392 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 393 ah->globaltxtimeout = (u32) -1;
cbdec975 394 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 395 ah->htc_reset_init = true;
f078f209
LR		 396}
397
cbe61d8a 398static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 399{
1510718d 400 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 401 u32 sum;
402 int i;
403 u16 eeval;
07b2fa5a 404 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 405
406 sum = 0;
407 for (i = 0; i < 3; i++) {
49101676 408 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 409 sum += eeval;
1510718d
LR		 410 common->macaddr[2 * i] = eeval >> 8;
411 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 412 }
d8baa939 413 if (sum == 0 || sum == 0xffff * 3)
f078f209 414 return -EADDRNOTAVAIL;
f078f209
LR		 415
416 return 0;
417}
418
f637cfd6 419static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 420{
6cae913d 421 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 422 int ecode;
f078f209 423
6cae913d 424 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 425 if (!ath9k_hw_chip_test(ah))
426 return -ENODEV;
427 }
f078f209 428
ebd5a14a
LR		 429 if (!AR_SREV_9300_20_OR_LATER(ah)) {
430 ecode = ar9002_hw_rf_claim(ah);
431 if (ecode != 0)
432 return ecode;
433 }
f078f209 434
f637cfd6 435 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 436 if (ecode != 0)
437 return ecode;
7d01b221 438
d2182b69 439 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 440 ah->eep_ops->get_eeprom_ver(ah),
441 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 442
e323300d 443 ath9k_hw_ani_init(ah);
f078f209 444
d3b371cb
SM		 445 /*
446 * EEPROM needs to be initialized before we do this.
447 * This is required for regulatory compliance.
448 */
0c7c2bb4 449 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 450 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
451 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 452 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
453 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 454 }
455 }
456
f078f209
LR		 457 return 0;
458}
459
c1b976d2 460static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 461{
c1b976d2
FF		 462 if (!AR_SREV_9300_20_OR_LATER(ah))
463 return ar9002_hw_attach_ops(ah);
464
465 ar9003_hw_attach_ops(ah);
466 return 0;
aa4058ae
LR		 467}
468
d70357d5
LR		 469/* Called for all hardware families */
470static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 471{
c46917bb 472 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 473 int r = 0;
aa4058ae 474
ac45c12d
SB		 475 ath9k_hw_read_revisions(ah);
476
0a8d7cb0
SB		 477 /*
478 * Read back AR_WA into a permanent copy and set bits 14 and 17.
479 * We need to do this to avoid RMW of this register. We cannot
480 * read the reg when chip is asleep.
481 */
27251e00
SM		 482 if (AR_SREV_9300_20_OR_LATER(ah)) {
483 ah->WARegVal = REG_READ(ah, AR_WA);
484 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
485 AR_WA_ASPM_TIMER_BASED_DISABLE);
486 }
0a8d7cb0 487
aa4058ae 488 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 489 ath_err(common, "Couldn't reset chip\n");
95fafca2 490 return -EIO;
aa4058ae
LR		 491 }
492
a4a2954f
SM		 493 if (AR_SREV_9565(ah)) {
494 ah->WARegVal |= AR_WA_BIT22;
495 REG_WRITE(ah, AR_WA, ah->WARegVal);
496 }
497
bab1f62e
LR		 498 ath9k_hw_init_defaults(ah);
499 ath9k_hw_init_config(ah);
500
c1b976d2
FF		 501 r = ath9k_hw_attach_ops(ah);
502 if (r)
503 return r;
d70357d5 504
9ecdef4b 505 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 506 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 507 return -EIO;
aa4058ae
LR		 508 }
509
f3eef645 510 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
aa4058ae 511 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
7508b657 512 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
4c85ab11 513 !ah->is_pciexpress)) {
aa4058ae
LR		 514 ah->config.serialize_regmode =
515 SER_REG_MODE_ON;
516 } else {
517 ah->config.serialize_regmode =
518 SER_REG_MODE_OFF;
519 }
520 }
521
d2182b69 522 ath_dbg(common, RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 523 ah->config.serialize_regmode);
524
f4709fdf
LR		 525 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
526 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
527 else
528 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
529
6da5a720
FF		 530 switch (ah->hw_version.macVersion) {
531 case AR_SREV_VERSION_5416_PCI:
532 case AR_SREV_VERSION_5416_PCIE:
533 case AR_SREV_VERSION_9160:
534 case AR_SREV_VERSION_9100:
535 case AR_SREV_VERSION_9280:
536 case AR_SREV_VERSION_9285:
537 case AR_SREV_VERSION_9287:
538 case AR_SREV_VERSION_9271:
539 case AR_SREV_VERSION_9300:
2c8e5937 540 case AR_SREV_VERSION_9330:
6da5a720 541 case AR_SREV_VERSION_9485:
bca04689 542 case AR_SREV_VERSION_9340:
423e38e8 543 case AR_SREV_VERSION_9462:
2b943a33 544 case AR_SREV_VERSION_9550:
77fac465 545 case AR_SREV_VERSION_9565:
6da5a720
FF		 546 break;
547 default:
3800276a
JP		 548 ath_err(common,
549 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
550 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 551 return -EOPNOTSUPP;
aa4058ae
LR		 552 }
553
2c8e5937 554 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 555 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 556 ah->is_pciexpress = false;
557
aa4058ae 558 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 559 ath9k_hw_init_cal_settings(ah);
560
561 ah->ani_function = ATH9K_ANI_ALL;
e36b27af
LR		 562 if (!AR_SREV_9300_20_OR_LATER(ah))
563 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae 564
69ce674b 565 if (!ah->is_pciexpress)
aa4058ae
LR		 566 ath9k_hw_disablepcie(ah);
567
f637cfd6 568 r = ath9k_hw_post_init(ah);
aa4058ae 569 if (r)
95fafca2 570 return r;
aa4058ae
LR		 571
572 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 573 r = ath9k_hw_fill_cap_info(ah);
574 if (r)
575 return r;
576
4f3acf81
LR		 577 r = ath9k_hw_init_macaddr(ah);
578 if (r) {
3800276a 579 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 580 return r;
f078f209
LR		 581 }
582
d7e7d229 583 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 584 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 585 else
2660b81a 586 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 587
4598702d 588 ath9k_hw_init_hang_checks(ah);
f078f209 589
211f5859
LR		 590 common->state = ATH_HW_INITIALIZED;
591
4f3acf81 592 return 0;
f078f209
LR		 593}
594
d70357d5 595int ath9k_hw_init(struct ath_hw *ah)
f078f209 596{
d70357d5
LR		 597 int ret;
598 struct ath_common *common = ath9k_hw_common(ah);
f078f209 599
77fac465 600 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 601 switch (ah->hw_version.devid) {
602 case AR5416_DEVID_PCI:
603 case AR5416_DEVID_PCIE:
604 case AR5416_AR9100_DEVID:
605 case AR9160_DEVID_PCI:
606 case AR9280_DEVID_PCI:
607 case AR9280_DEVID_PCIE:
608 case AR9285_DEVID_PCIE:
db3cc53a
SB		 609 case AR9287_DEVID_PCI:
610 case AR9287_DEVID_PCIE:
d70357d5 611 case AR2427_DEVID_PCIE:
db3cc53a 612 case AR9300_DEVID_PCIE:
3050c914 613 case AR9300_DEVID_AR9485_PCIE:
999a7a88 614 case AR9300_DEVID_AR9330:
bca04689 615 case AR9300_DEVID_AR9340:
2b943a33 616 case AR9300_DEVID_QCA955X:
5a63ef0f 617 case AR9300_DEVID_AR9580:
423e38e8 618 case AR9300_DEVID_AR9462:
d4e5979c 619 case AR9485_DEVID_AR1111:
77fac465 620 case AR9300_DEVID_AR9565:
d70357d5
LR		 621 break;
622 default:
623 if (common->bus_ops->ath_bus_type == ATH_USB)
624 break;
3800276a
JP		 625 ath_err(common, "Hardware device ID 0x%04x not supported\n",
626 ah->hw_version.devid);
d70357d5
LR		 627 return -EOPNOTSUPP;
628 }
f078f209 629
d70357d5
LR		 630 ret = __ath9k_hw_init(ah);
631 if (ret) {
3800276a
JP		 632 ath_err(common,
633 "Unable to initialize hardware; initialization status: %d\n",
634 ret);
d70357d5
LR		 635 return ret;
636 }
f078f209 637
d70357d5 638 return 0;
f078f209 639}
d70357d5 640EXPORT_SYMBOL(ath9k_hw_init);
f078f209 641
cbe61d8a 642static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 643{
7d0d0df0
S		 644 ENABLE_REGWRITE_BUFFER(ah);
645
f1dc5600
S		 646 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
647 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 648
f1dc5600
S		 649 REG_WRITE(ah, AR_QOS_NO_ACK,
650 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
651 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
652 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
653
654 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
655 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
656 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
657 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
658 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 659
660 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 661}
662
b84628eb 663u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 664{
f18e3c6b
MSS		 665 struct ath_common *common = ath9k_hw_common(ah);
666 int i = 0;
667
ca7a4deb
FF		 668 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
669 udelay(100);
670 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 671
f18e3c6b
MSS		 672 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
673
ca7a4deb 674 udelay(100);
b1415819 675
f18e3c6b
MSS		 676 if (WARN_ON_ONCE(i >= 100)) {
677 ath_err(common, "PLL4 meaurement not done\n");
678 break;
679 }
680
681 i++;
682 }
683
ca7a4deb 684 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 685}
686EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
687
cbe61d8a 688static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 689 struct ath9k_channel *chan)
f078f209 690{
d09b17f7
VT		 691 u32 pll;
692
a4a2954f 693 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 694 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
695 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
696 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
697 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
698 AR_CH0_DPLL2_KD, 0x40);
699 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
700 AR_CH0_DPLL2_KI, 0x4);
22983c30 701
3dfd7f60
VT		 702 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
703 AR_CH0_BB_DPLL1_REFDIV, 0x5);
704 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
705 AR_CH0_BB_DPLL1_NINI, 0x58);
706 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
707 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 708
709 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 710 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
711 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
712 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 713 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 714 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 715
3dfd7f60 716 /* program BB PLL phase_shift to 0x6 */
22983c30 717 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 718 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
719
720 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
721 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 722 udelay(1000);
a5415d62
GJ		 723 } else if (AR_SREV_9330(ah)) {
724 u32 ddr_dpll2, pll_control2, kd;
725
726 if (ah->is_clk_25mhz) {
727 ddr_dpll2 = 0x18e82f01;
728 pll_control2 = 0xe04a3d;
729 kd = 0x1d;
730 } else {
731 ddr_dpll2 = 0x19e82f01;
732 pll_control2 = 0x886666;
733 kd = 0x3d;
734 }
735
736 /* program DDR PLL ki and kd value */
737 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
738
739 /* program DDR PLL phase_shift */
740 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
741 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
742
743 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
744 udelay(1000);
745
746 /* program refdiv, nint, frac to RTC register */
747 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
748
749 /* program BB PLL kd and ki value */
750 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
751 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
752
753 /* program BB PLL phase_shift */
754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
755 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
fc05a317 756 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 757 u32 regval, pll2_divint, pll2_divfrac, refdiv;
758
759 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
760 udelay(1000);
761
762 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
763 udelay(100);
764
765 if (ah->is_clk_25mhz) {
766 pll2_divint = 0x54;
767 pll2_divfrac = 0x1eb85;
768 refdiv = 3;
769 } else {
fc05a317
GJ		 770 if (AR_SREV_9340(ah)) {
771 pll2_divint = 88;
772 pll2_divfrac = 0;
773 refdiv = 5;
774 } else {
775 pll2_divint = 0x11;
776 pll2_divfrac = 0x26666;
777 refdiv = 1;
778 }
0b488ac6
VT		 779 }
780
781 regval = REG_READ(ah, AR_PHY_PLL_MODE);
782 regval |= (0x1 << 16);
783 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
784 udelay(100);
785
786 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
787 (pll2_divint << 18) | pll2_divfrac);
788 udelay(100);
789
790 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317
GJ		 791 if (AR_SREV_9340(ah))
792 regval = (regval & 0x80071fff) | (0x1 << 30) |
793 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
794 else
795 regval = (regval & 0x80071fff) | (0x3 << 30) |
796 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
0b488ac6
VT		 797 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
798 REG_WRITE(ah, AR_PHY_PLL_MODE,
799 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
800 udelay(1000);
22983c30 801 }
d09b17f7
VT		 802
803 pll = ath9k_hw_compute_pll_control(ah, chan);
8565f8bf
SM		 804 if (AR_SREV_9565(ah))
805 pll |= 0x40000;
d03a66c1 806 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 807
fc05a317
GJ		 808 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
809 AR_SREV_9550(ah))
3dfd7f60
VT		 810 udelay(1000);
811
c75724d1
LR		 812 /* Switch the core clock for ar9271 to 117Mhz */
813 if (AR_SREV_9271(ah)) {
25e2ab17
S		 814 udelay(500);
815 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 816 }
817
f1dc5600
S		 818 udelay(RTC_PLL_SETTLE_DELAY);
819
820 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6 821
fc05a317 822 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 823 if (ah->is_clk_25mhz) {
824 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
825 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
826 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
827 } else {
828 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
829 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
830 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
831 }
832 udelay(100);
833 }
f078f209
LR		 834}
835
cbe61d8a 836static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 837 enum nl80211_iftype opmode)
f078f209 838{
79d1d2b8 839 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 840 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 841 AR_IMR_TXURN |
842 AR_IMR_RXERR |
843 AR_IMR_RXORN |
844 AR_IMR_BCNMISC;
f078f209 845
3b8a0577 846 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
79d1d2b8
VT		 847 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
848
66860240
VT		 849 if (AR_SREV_9300_20_OR_LATER(ah)) {
850 imr_reg |= AR_IMR_RXOK_HP;
851 if (ah->config.rx_intr_mitigation)
852 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
853 else
854 imr_reg |= AR_IMR_RXOK_LP;
f078f209 855
66860240
VT		 856 } else {
857 if (ah->config.rx_intr_mitigation)
858 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
859 else
860 imr_reg |= AR_IMR_RXOK;
861 }
f078f209 862
66860240
VT		 863 if (ah->config.tx_intr_mitigation)
864 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
865 else
866 imr_reg |= AR_IMR_TXOK;
f078f209 867
7d0d0df0
S		 868 ENABLE_REGWRITE_BUFFER(ah);
869
152d530d 870 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 871 ah->imrs2_reg |= AR_IMR_S2_GTT;
872 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 873
f1dc5600
S		 874 if (!AR_SREV_9100(ah)) {
875 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 876 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 877 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
878 }
66860240 879
7d0d0df0 880 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 881
66860240
VT		 882 if (AR_SREV_9300_20_OR_LATER(ah)) {
883 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
884 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
885 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
886 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
887 }
f078f209
LR		 888}
889
b6ba41bb
FF		 890static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
891{
892 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
893 val = min(val, (u32) 0xFFFF);
894 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
895}
896
0005baf4 897static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 898{
0005baf4
FF		 899 u32 val = ath9k_hw_mac_to_clks(ah, us);
900 val = min(val, (u32) 0xFFFF);
901 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 902}
903
0005baf4 904static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 905{
0005baf4
FF		 906 u32 val = ath9k_hw_mac_to_clks(ah, us);
907 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
908 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
909}
910
911static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
912{
913 u32 val = ath9k_hw_mac_to_clks(ah, us);
914 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
915 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 916}
f1dc5600 917
cbe61d8a 918static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 919{
f078f209 920 if (tu > 0xFFFF) {
d2182b69
JP		 921 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
922 tu);
2660b81a 923 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 924 return false;
925 } else {
926 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 927 ah->globaltxtimeout = tu;
f078f209
LR		 928 return true;
929 }
930}
931
0005baf4 932void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 933{
b6ba41bb 934 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 935 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 936 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 937 int slottime;
0005baf4 938 int sifstime;
b6ba41bb
FF		 939 int rx_lat = 0, tx_lat = 0, eifs = 0;
940 u32 reg;
0005baf4 941
d2182b69 942 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 943 ah->misc_mode);
f078f209 944
b6ba41bb
FF		 945 if (!chan)
946 return;
947
2660b81a 948 if (ah->misc_mode != 0)
ca7a4deb 949 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 950
81a91d57
RM		 951 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
952 rx_lat = 41;
953 else
954 rx_lat = 37;
b6ba41bb
FF		 955 tx_lat = 54;
956
e88e4861
FF		 957 if (IS_CHAN_5GHZ(chan))
958 sifstime = 16;
959 else
960 sifstime = 10;
961
b6ba41bb
FF		 962 if (IS_CHAN_HALF_RATE(chan)) {
963 eifs = 175;
964 rx_lat *= 2;
965 tx_lat *= 2;
966 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
967 tx_lat += 11;
968
92367fe7 969 sifstime = 32;
e115b7ec 970 ack_offset = 16;
b6ba41bb 971 slottime = 13;
b6ba41bb
FF		 972 } else if (IS_CHAN_QUARTER_RATE(chan)) {
973 eifs = 340;
81a91d57 974 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 975 tx_lat *= 4;
976 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
977 tx_lat += 22;
978
92367fe7 979 sifstime = 64;
e115b7ec 980 ack_offset = 32;
b6ba41bb 981 slottime = 21;
b6ba41bb 982 } else {
a7be039d
RM		 983 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
984 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
985 reg = AR_USEC_ASYNC_FIFO;
986 } else {
987 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
988 common->clockrate;
989 reg = REG_READ(ah, AR_USEC);
990 }
b6ba41bb
FF		 991 rx_lat = MS(reg, AR_USEC_RX_LAT);
992 tx_lat = MS(reg, AR_USEC_TX_LAT);
993
994 slottime = ah->slottime;
b6ba41bb 995 }
0005baf4 996
e239d859 997 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 998 slottime += 3 * ah->coverage_class;
999 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1000 ctstimeout = acktimeout;
42c4568a
FF		 1001
1002 /*
1003 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1004 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1005 * This was initially only meant to work around an issue with delayed
1006 * BA frames in some implementations, but it has been found to fix ACK
1007 * timeout issues in other cases as well.
1008 */
e4744ec7 1009 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1010 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1011 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1012 ctstimeout += 48 - sifstime - ah->slottime;
1013 }
1014
b6ba41bb
FF		 1015 ath9k_hw_set_sifs_time(ah, sifstime);
1016 ath9k_hw_setslottime(ah, slottime);
0005baf4 1017 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1018 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1019 if (ah->globaltxtimeout != (u32) -1)
1020 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1021
1022 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1023 REG_RMW(ah, AR_USEC,
1024 (common->clockrate - 1) |
1025 SM(rx_lat, AR_USEC_RX_LAT) |
1026 SM(tx_lat, AR_USEC_TX_LAT),
1027 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1028
f1dc5600 1029}
0005baf4 1030EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1031
285f2dda 1032void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1033{
211f5859
LR		 1034 struct ath_common *common = ath9k_hw_common(ah);
1035
736b3a27 1036 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1037 return;
211f5859 1038
9ecdef4b 1039 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1040}
285f2dda 1041EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1042
f1dc5600
S		 1043/*******/
1044/* INI */
1045/*******/
1046
8fe65368 1047u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1048{
1049 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1050
6b21fd20 1051 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1052 ctl |= CTL_11G;
1053 else
1054 ctl |= CTL_11A;
1055
1056 return ctl;
1057}
1058
f1dc5600
S		 1059/****************************************/
1060/* Reset and Channel Switching Routines */
1061/****************************************/
f1dc5600 1062
cbe61d8a 1063static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1064{
57b32227 1065 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1066 int txbuf_size;
f1dc5600 1067
7d0d0df0
S		 1068 ENABLE_REGWRITE_BUFFER(ah);
1069
d7e7d229
LR		 1070 /*
1071 * set AHB_MODE not to do cacheline prefetches
1072 */
ca7a4deb
FF		 1073 if (!AR_SREV_9300_20_OR_LATER(ah))
1074 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1075
d7e7d229
LR		 1076 /*
1077 * let mac dma reads be in 128 byte chunks
1078 */
ca7a4deb 1079 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1080
7d0d0df0 1081 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1082
d7e7d229
LR		 1083 /*
1084 * Restore TX Trigger Level to its pre-reset value.
1085 * The initial value depends on whether aggregation is enabled, and is
1086 * adjusted whenever underruns are detected.
1087 */
57b32227
FF		 1088 if (!AR_SREV_9300_20_OR_LATER(ah))
1089 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1090
7d0d0df0 1091 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1092
d7e7d229
LR		 1093 /*
1094 * let mac dma writes be in 128 byte chunks
1095 */
ca7a4deb 1096 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1097
d7e7d229
LR		 1098 /*
1099 * Setup receive FIFO threshold to hold off TX activities
1100 */
f1dc5600
S		 1101 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1102
57b32227
FF		 1103 if (AR_SREV_9300_20_OR_LATER(ah)) {
1104 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1105 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1106
1107 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1108 ah->caps.rx_status_len);
1109 }
1110
d7e7d229
LR		 1111 /*
1112 * reduce the number of usable entries in PCU TXBUF to avoid
1113 * wrap around issues.
1114 */
f1dc5600 1115 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1116 /* For AR9285 the number of Fifos are reduced to half.
1117 * So set the usable tx buf size also to half to
1118 * avoid data/delimiter underruns
1119 */
86c157b3
FF		 1120 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1121 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1122 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1123 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1124 } else {
1125 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1126 }
744d4025 1127
86c157b3
FF		 1128 if (!AR_SREV_9271(ah))
1129 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1130
7d0d0df0 1131 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1132
744d4025
VT		 1133 if (AR_SREV_9300_20_OR_LATER(ah))
1134 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1135}
1136
cbe61d8a 1137static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1138{
ca7a4deb
FF		 1139 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1140 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1141
f1dc5600 1142 switch (opmode) {
d97809db 1143 case NL80211_IFTYPE_ADHOC:
ca7a4deb 1144 set |= AR_STA_ID1_ADHOC;
f1dc5600 1145 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1146 break;
2664d666 1147 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1148 case NL80211_IFTYPE_AP:
1149 set |= AR_STA_ID1_STA_AP;
1150 /* fall through */
d97809db 1151 case NL80211_IFTYPE_STATION:
ca7a4deb 1152 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1153 break;
5f841b41 1154 default:
ca7a4deb
FF		 1155 if (!ah->is_monitoring)
1156 set = 0;
5f841b41 1157 break;
f1dc5600 1158 }
ca7a4deb 1159 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1160}
1161
8fe65368
LR		 1162void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1163 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1164{
1165 u32 coef_exp, coef_man;
1166
1167 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1168 if ((coef_scaled >> coef_exp) & 0x1)
1169 break;
1170
1171 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1172
1173 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1174
1175 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1176 *coef_exponent = coef_exp - 16;
1177}
1178
d7df7a55
SM		 1179/* AR9330 WAR:
1180 * call external reset function to reset WMAC if:
1181 * - doing a cold reset
1182 * - we have pending frames in the TX queues.
1183 */
1184static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1185{
1186 int i, npend = 0;
1187
1188 for (i = 0; i < AR_NUM_QCU; i++) {
1189 npend = ath9k_hw_numtxpending(ah, i);
1190 if (npend)
1191 break;
1192 }
1193
1194 if (ah->external_reset &&
1195 (npend || type == ATH9K_RESET_COLD)) {
1196 int reset_err = 0;
1197
1198 ath_dbg(ath9k_hw_common(ah), RESET,
1199 "reset MAC via external reset\n");
1200
1201 reset_err = ah->external_reset();
1202 if (reset_err) {
1203 ath_err(ath9k_hw_common(ah),
1204 "External reset failed, err=%d\n",
1205 reset_err);
1206 return false;
1207 }
1208
1209 REG_WRITE(ah, AR_RTC_RESET, 1);
1210 }
1211
1212 return true;
1213}
1214
cbe61d8a 1215static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1216{
1217 u32 rst_flags;
1218 u32 tmpReg;
1219
70768496 1220 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1221 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1222 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1223 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1224 }
1225
7d0d0df0
S		 1226 ENABLE_REGWRITE_BUFFER(ah);
1227
9a658d2b
LR		 1228 if (AR_SREV_9300_20_OR_LATER(ah)) {
1229 REG_WRITE(ah, AR_WA, ah->WARegVal);
1230 udelay(10);
1231 }
1232
f1dc5600
S		 1233 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1234 AR_RTC_FORCE_WAKE_ON_INT);
1235
1236 if (AR_SREV_9100(ah)) {
1237 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1238 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1239 } else {
1240 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1241 if (AR_SREV_9340(ah))
1242 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1243 else
1244 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1245 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1246
1247 if (tmpReg) {
42d5bc3f 1248 u32 val;
f1dc5600 1249 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1250
1251 val = AR_RC_HOSTIF;
1252 if (!AR_SREV_9300_20_OR_LATER(ah))
1253 val |= AR_RC_AHB;
1254 REG_WRITE(ah, AR_RC, val);
1255
1256 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1257 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1258
1259 rst_flags = AR_RTC_RC_MAC_WARM;
1260 if (type == ATH9K_RESET_COLD)
1261 rst_flags |= AR_RTC_RC_MAC_COLD;
1262 }
1263
7d95847c 1264 if (AR_SREV_9330(ah)) {
d7df7a55
SM		 1265 if (!ath9k_hw_ar9330_reset_war(ah, type))
1266 return false;
7d95847c
GJ		 1267 }
1268
3863495b 1269 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1270 ar9003_mci_check_gpm_offset(ah);
3863495b 1271
d03a66c1 1272 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1273
1274 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1275
4dc78c43
SM		 1276 if (AR_SREV_9300_20_OR_LATER(ah))
1277 udelay(50);
1278 else if (AR_SREV_9100(ah))
1279 udelay(10000);
1280 else
1281 udelay(100);
f1dc5600 1282
d03a66c1 1283 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1284 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1285 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1286 return false;
1287 }
1288
1289 if (!AR_SREV_9100(ah))
1290 REG_WRITE(ah, AR_RC, 0);
1291
f1dc5600
S		 1292 if (AR_SREV_9100(ah))
1293 udelay(50);
1294
1295 return true;
1296}
1297
cbe61d8a 1298static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1299{
7d0d0df0
S		 1300 ENABLE_REGWRITE_BUFFER(ah);
1301
9a658d2b
LR		 1302 if (AR_SREV_9300_20_OR_LATER(ah)) {
1303 REG_WRITE(ah, AR_WA, ah->WARegVal);
1304 udelay(10);
1305 }
1306
f1dc5600
S		 1307 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1308 AR_RTC_FORCE_WAKE_ON_INT);
1309
42d5bc3f 1310 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1311 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1312
d03a66c1 1313 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1314
7d0d0df0 1315 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1316
afe36533 1317 udelay(2);
84e2169b
SB		 1318
1319 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1320 REG_WRITE(ah, AR_RC, 0);
1321
d03a66c1 1322 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1323
1324 if (!ath9k_hw_wait(ah,
1325 AR_RTC_STATUS,
1326 AR_RTC_STATUS_M,
0caa7b14
S		 1327 AR_RTC_STATUS_ON,
1328 AH_WAIT_TIMEOUT)) {
d2182b69 1329 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1330 return false;
f078f209
LR		 1331 }
1332
f1dc5600
S		 1333 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1334}
1335
cbe61d8a 1336static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1337{
7a9233ff 1338 bool ret = false;
2577c6e8 1339
9a658d2b
LR		 1340 if (AR_SREV_9300_20_OR_LATER(ah)) {
1341 REG_WRITE(ah, AR_WA, ah->WARegVal);
1342 udelay(10);
1343 }
1344
f1dc5600
S		 1345 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1346 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1347
ceb26a60
FF		 1348 if (!ah->reset_power_on)
1349 type = ATH9K_RESET_POWER_ON;
1350
f1dc5600
S		 1351 switch (type) {
1352 case ATH9K_RESET_POWER_ON:
7a9233ff 1353 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1354 if (ret)
ceb26a60 1355 ah->reset_power_on = true;
7a9233ff 1356 break;
f1dc5600
S		 1357 case ATH9K_RESET_WARM:
1358 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1359 ret = ath9k_hw_set_reset(ah, type);
1360 break;
f1dc5600 1361 default:
7a9233ff 1362 break;
f1dc5600 1363 }
7a9233ff 1364
7a9233ff 1365 return ret;
f078f209
LR		 1366}
1367
cbe61d8a 1368static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1369 struct ath9k_channel *chan)
f078f209 1370{
9c083af8
FF		 1371 int reset_type = ATH9K_RESET_WARM;
1372
1373 if (AR_SREV_9280(ah)) {
1374 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1375 reset_type = ATH9K_RESET_POWER_ON;
1376 else
1377 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1378 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1379 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1380 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1381
1382 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1383 return false;
f078f209 1384
9ecdef4b 1385 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1386 return false;
f078f209 1387
2660b81a 1388 ah->chip_fullsleep = false;
bfc441a4
FF		 1389
1390 if (AR_SREV_9330(ah))
1391 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1392 ath9k_hw_init_pll(ah, chan);
f078f209 1393
f1dc5600 1394 return true;
f078f209
LR		 1395}
1396
cbe61d8a 1397static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1398 struct ath9k_channel *chan)
f078f209 1399{
c46917bb 1400 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1401 struct ath9k_hw_capabilities *pCap = &ah->caps;
1402 bool band_switch = false, mode_diff = false;
70e89a71 1403 u8 ini_reloaded = 0;
8fe65368 1404 u32 qnum;
0a3b7bac 1405 int r;
5f0c04ea 1406
b840cffe 1407 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1408 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1409 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1410 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1411 }
f078f209
LR		 1412
1413 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1414 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1415 ath_dbg(common, QUEUE,
226afe68 1416 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1417 return false;
1418 }
1419 }
1420
8fe65368 1421 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1422 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1423 return false;
1424 }
1425
b840cffe 1426 if (band_switch || mode_diff) {
5f0c04ea
RM		 1427 ath9k_hw_mark_phy_inactive(ah);
1428 udelay(5);
1429
5f35c0fa
SM		 1430 if (band_switch)
1431 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1432
1433 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1434 ath_err(common, "Failed to do fast channel change\n");
1435 return false;
1436 }
1437 }
1438
8fe65368 1439 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1440
8fe65368 1441 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1442 if (r) {
3800276a 1443 ath_err(common, "Failed to set channel\n");
0a3b7bac 1444 return false;
f078f209 1445 }
dfdac8ac 1446 ath9k_hw_set_clockrate(ah);
64ea57d0 1447 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1448
81c507a8 1449 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1450 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1451
70e89a71
SM		 1452 if (band_switch || ini_reloaded)
1453 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1454
70e89a71
SM		 1455 ath9k_hw_init_bb(ah, chan);
1456 ath9k_hw_rfbus_done(ah);
5f0c04ea 1457
70e89a71
SM		 1458 if (band_switch || ini_reloaded) {
1459 ah->ah_flags |= AH_FASTCC;
1460 ath9k_hw_init_cal(ah, chan);
a126ff51 1461 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1462 }
1463
f1dc5600
S		 1464 return true;
1465}
1466
691680b8
FF		 1467static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1468{
1469 u32 gpio_mask = ah->gpio_mask;
1470 int i;
1471
1472 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1473 if (!(gpio_mask & 1))
1474 continue;
1475
1476 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1477 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1478 }
1479}
1480
1e516ca7
SM		 1481void ath9k_hw_check_nav(struct ath_hw *ah)
1482{
1483 struct ath_common *common = ath9k_hw_common(ah);
1484 u32 val;
1485
1486 val = REG_READ(ah, AR_NAV);
1487 if (val != 0xdeadbeef && val > 0x7fff) {
1488 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1489 REG_WRITE(ah, AR_NAV, 0);
1490 }
1491}
1492EXPORT_SYMBOL(ath9k_hw_check_nav);
1493
c9c99e5e 1494bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1495{
c9c99e5e
FF		 1496 int count = 50;
1497 u32 reg;
1498
01e18918
RM		 1499 if (AR_SREV_9300(ah))
1500 return !ath9k_hw_detect_mac_hang(ah);
1501
e17f83ea 1502 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1503 return true;
1504
1505 do {
1506 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1507
c9c99e5e
FF		 1508 if ((reg & 0x7E7FFFEF) == 0x00702400)
1509 continue;
1510
1511 switch (reg & 0x7E000B00) {
1512 case 0x1E000000:
1513 case 0x52000B00:
1514 case 0x18000B00:
1515 continue;
1516 default:
1517 return true;
1518 }
1519 } while (count-- > 0);
3b319aae 1520
c9c99e5e 1521 return false;
3b319aae 1522}
c9c99e5e 1523EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1524
15d2b585
SM		 1525static void ath9k_hw_init_mfp(struct ath_hw *ah)
1526{
1527 /* Setup MFP options for CCMP */
1528 if (AR_SREV_9280_20_OR_LATER(ah)) {
1529 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1530 * frames when constructing CCMP AAD. */
1531 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1532 0xc7ff);
1533 ah->sw_mgmt_crypto = false;
1534 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1535 /* Disable hardware crypto for management frames */
1536 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1537 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1538 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1539 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1540 ah->sw_mgmt_crypto = true;
1541 } else {
1542 ah->sw_mgmt_crypto = true;
1543 }
1544}
1545
1546static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1547 u32 macStaId1, u32 saveDefAntenna)
1548{
1549 struct ath_common *common = ath9k_hw_common(ah);
1550
1551 ENABLE_REGWRITE_BUFFER(ah);
1552
ecbbed32 1553 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585
SM		 1554 | AR_STA_ID1_RTS_USE_DEF
1555 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
ecbbed32
FF		 1556 | ah->sta_id1_defaults,
1557 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1558 ath_hw_setbssidmask(common);
1559 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1560 ath9k_hw_write_associd(ah);
1561 REG_WRITE(ah, AR_ISR, ~0);
1562 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1563
1564 REGWRITE_BUFFER_FLUSH(ah);
1565
1566 ath9k_hw_set_operating_mode(ah, ah->opmode);
1567}
1568
1569static void ath9k_hw_init_queues(struct ath_hw *ah)
1570{
1571 int i;
1572
1573 ENABLE_REGWRITE_BUFFER(ah);
1574
1575 for (i = 0; i < AR_NUM_DCU; i++)
1576 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1577
1578 REGWRITE_BUFFER_FLUSH(ah);
1579
1580 ah->intr_txqs = 0;
1581 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1582 ath9k_hw_resettxqueue(ah, i);
1583}
1584
1585/*
1586 * For big endian systems turn on swapping for descriptors
1587 */
1588static void ath9k_hw_init_desc(struct ath_hw *ah)
1589{
1590 struct ath_common *common = ath9k_hw_common(ah);
1591
1592 if (AR_SREV_9100(ah)) {
1593 u32 mask;
1594 mask = REG_READ(ah, AR_CFG);
1595 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1596 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1597 mask);
1598 } else {
1599 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1600 REG_WRITE(ah, AR_CFG, mask);
1601 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1602 REG_READ(ah, AR_CFG));
1603 }
1604 } else {
1605 if (common->bus_ops->ath_bus_type == ATH_USB) {
1606 /* Configure AR9271 target WLAN */
1607 if (AR_SREV_9271(ah))
1608 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1609 else
1610 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1611 }
1612#ifdef __BIG_ENDIAN
1613 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1614 AR_SREV_9550(ah))
1615 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1616 else
1617 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1618#endif
1619 }
1620}
1621
caed6579
SM		 1622/*
1623 * Fast channel change:
1624 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1625 */
1626static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1627{
1628 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1629 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1630 int ret;
1631
1632 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1633 goto fail;
1634
1635 if (ah->chip_fullsleep)
1636 goto fail;
1637
1638 if (!ah->curchan)
1639 goto fail;
1640
1641 if (chan->channel == ah->curchan->channel)
1642 goto fail;
1643
feb7bc99
FF		 1644 if ((ah->curchan->channelFlags | chan->channelFlags) &
1645 (CHANNEL_HALF | CHANNEL_QUARTER))
1646 goto fail;
1647
b840cffe 1648 /*
6b21fd20 1649 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1650 */
6b21fd20 1651 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1652 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1653 goto fail;
caed6579
SM		 1654
1655 if (!ath9k_hw_check_alive(ah))
1656 goto fail;
1657
1658 /*
1659 * For AR9462, make sure that calibration data for
1660 * re-using are present.
1661 */
8a90555f 1662 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1663 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1664 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1665 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1666 goto fail;
1667
1668 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1669 ah->curchan->channel, chan->channel);
1670
1671 ret = ath9k_hw_channel_change(ah, chan);
1672 if (!ret)
1673 goto fail;
1674
5955b2b0 1675 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1676 ar9003_mci_2g5g_switch(ah, false);
caed6579 1677
88033318
RM		 1678 ath9k_hw_loadnf(ah, ah->curchan);
1679 ath9k_hw_start_nfcal(ah, true);
1680
caed6579
SM		 1681 if (AR_SREV_9271(ah))
1682 ar9002_hw_load_ani_reg(ah, chan);
1683
1684 return 0;
1685fail:
1686 return -EINVAL;
1687}
1688
cbe61d8a 1689int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1690 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1691{
1510718d 1692 struct ath_common *common = ath9k_hw_common(ah);
09d8e315 1693 struct timespec ts;
f078f209 1694 u32 saveLedState;
f078f209
LR		 1695 u32 saveDefAntenna;
1696 u32 macStaId1;
46fe782c 1697 u64 tsf = 0;
09d8e315 1698 s64 usec = 0;
15d2b585 1699 int r;
caed6579 1700 bool start_mci_reset = false;
63d32967
MSS		 1701 bool save_fullsleep = ah->chip_fullsleep;
1702
5955b2b0 1703 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1704 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1705 if (start_mci_reset)
1706 return 0;
63d32967
MSS		 1707 }
1708
9ecdef4b 1709 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1710 return -EIO;
f078f209 1711
caed6579
SM		 1712 if (ah->curchan && !ah->chip_fullsleep)
1713 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1714
20bd2a09 1715 ah->caldata = caldata;
fcb9a3de 1716 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1717 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1718 /* Operating channel changed, reset channel calibration data */
1719 memset(caldata, 0, sizeof(*caldata));
1720 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1721 } else if (caldata) {
4b9b42bf 1722 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1723 }
5bc225ac 1724 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1725
caed6579
SM		 1726 if (fastcc) {
1727 r = ath9k_hw_do_fastcc(ah, chan);
1728 if (!r)
1729 return r;
f078f209
LR		 1730 }
1731
5955b2b0 1732 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1733 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1734
f078f209
LR		 1735 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1736 if (saveDefAntenna == 0)
1737 saveDefAntenna = 1;
1738
1739 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1740
09d8e315
FF		 1741 /* Save TSF before chip reset, a cold reset clears it */
1742 tsf = ath9k_hw_gettsf64(ah);
1743 getrawmonotonic(&ts);
cca213fd 1744 usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000;
46fe782c 1745
f078f209
LR		 1746 saveLedState = REG_READ(ah, AR_CFG_LED) &
1747 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1748 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1749
1750 ath9k_hw_mark_phy_inactive(ah);
1751
45ef6a0b
VT		 1752 ah->paprd_table_write_done = false;
1753
05020d23 1754 /* Only required on the first reset */
d7e7d229
LR		 1755 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1756 REG_WRITE(ah,
1757 AR9271_RESET_POWER_DOWN_CONTROL,
1758 AR9271_RADIO_RF_RST);
1759 udelay(50);
1760 }
1761
f078f209 1762 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1763 ath_err(common, "Chip reset failed\n");
ae8d2858 1764 return -EINVAL;
f078f209
LR		 1765 }
1766
05020d23 1767 /* Only required on the first reset */
d7e7d229
LR		 1768 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1769 ah->htc_reset_init = false;
1770 REG_WRITE(ah,
1771 AR9271_RESET_POWER_DOWN_CONTROL,
1772 AR9271_GATE_MAC_CTL);
1773 udelay(50);
1774 }
1775
46fe782c 1776 /* Restore TSF */
09d8e315 1777 getrawmonotonic(&ts);
cca213fd 1778 usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000 - usec;
09d8e315 1779 ath9k_hw_settsf64(ah, tsf + usec);
46fe782c 1780
7a37081e 1781 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1782 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1783
e9141f71
S		 1784 if (!AR_SREV_9300_20_OR_LATER(ah))
1785 ar9002_hw_enable_async_fifo(ah);
1786
25c56eec 1787 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1788 if (r)
1789 return r;
f078f209 1790
935d00cc
LB		 1791 ath9k_hw_set_rfmode(ah, chan);
1792
5955b2b0 1793 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1794 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1795
f860d526
FF		 1796 /*
1797 * Some AR91xx SoC devices frequently fail to accept TSF writes
1798 * right after the chip reset. When that happens, write a new
1799 * value after the initvals have been applied, with an offset
1800 * based on measured time difference
1801 */
1802 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1803 tsf += 1500;
1804 ath9k_hw_settsf64(ah, tsf);
1805 }
1806
15d2b585 1807 ath9k_hw_init_mfp(ah);
0ced0e17 1808
81c507a8 1809 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1810 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1811 ah->eep_ops->set_board_values(ah, chan);
a7765828 1812
15d2b585 1813 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1814
8fe65368 1815 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1816 if (r)
1817 return r;
f078f209 1818
dfdac8ac
FF		 1819 ath9k_hw_set_clockrate(ah);
1820
15d2b585 1821 ath9k_hw_init_queues(ah);
2660b81a 1822 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1823 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1824 ath9k_hw_init_qos(ah);
1825
2660b81a 1826 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1827 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1828
0005baf4 1829 ath9k_hw_init_global_settings(ah);
f078f209 1830
fe2b6afb
FF		 1831 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1832 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1833 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1834 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1835 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1836 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1837 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1838 }
1839
ca7a4deb 1840 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1841
1842 ath9k_hw_set_dma(ah);
1843
ed6ebd8b
RM		 1844 if (!ath9k_hw_mci_is_enabled(ah))
1845 REG_WRITE(ah, AR_OBS, 8);
f078f209 1846
0ce024cb 1847 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1848 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1849 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1850 }
1851
7f62a136
VT		 1852 if (ah->config.tx_intr_mitigation) {
1853 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1854 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1855 }
1856
f078f209
LR		 1857 ath9k_hw_init_bb(ah, chan);
1858
77a5a664 1859 if (caldata) {
4b9b42bf
SM		 1860 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1861 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 1862 }
ae8d2858 1863 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1864 return -EIO;
f078f209 1865
5955b2b0 1866 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 1867 return -EIO;
63d32967 1868
7d0d0df0 1869 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1870
8fe65368 1871 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1872 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1873
7d0d0df0 1874 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1875
15d2b585 1876 ath9k_hw_init_desc(ah);
f078f209 1877
dbccdd1d 1878 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 1879 ath9k_hw_btcoex_enable(ah);
1880
5955b2b0 1881 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1882 ar9003_mci_check_bt(ah);
63d32967 1883
1fe860ed
RM		 1884 ath9k_hw_loadnf(ah, chan);
1885 ath9k_hw_start_nfcal(ah, true);
1886
a7abaf7d 1887 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 1888 ar9003_hw_bb_watchdog_config(ah);
a7abaf7d
SM		 1889
1890 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
51ac8cbb 1891 ar9003_hw_disable_phy_restart(ah);
51ac8cbb 1892
691680b8
FF		 1893 ath9k_hw_apply_gpio_override(ah);
1894
7bdea96a 1895 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 1896 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
1897
ae8d2858 1898 return 0;
f078f209 1899}
7322fd19 1900EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1901
f1dc5600
S		 1902/******************************/
1903/* Power Management (Chipset) */
1904/******************************/
1905
42d5bc3f
LR		 1906/*
1907 * Notify Power Mgt is disabled in self-generated frames.
1908 * If requested, force chip to sleep.
1909 */
31604cf0 1910static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 1911{
f1dc5600 1912 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 1913
a4a2954f 1914 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 1915 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
1916 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
1917 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 1918 /* xxx Required for WLAN only case ? */
1919 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1920 udelay(100);
1921 }
2577c6e8 1922
31604cf0
SM		 1923 /*
1924 * Clear the RTC force wake bit to allow the
1925 * mac to go to sleep.
1926 */
1927 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1928
153dccd4 1929 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 1930 udelay(100);
2577c6e8 1931
31604cf0
SM		 1932 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1933 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1934
31604cf0
SM		 1935 /* Shutdown chip. Active low */
1936 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
1937 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1938 udelay(2);
f1dc5600 1939 }
9a658d2b
LR		 1940
1941 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 1942 if (AR_SREV_9300_20_OR_LATER(ah))
1943 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1944}
1945
bbd79af5
LR		 1946/*
1947 * Notify Power Management is enabled in self-generating
1948 * frames. If request, set power mode of chip to
1949 * auto/normal. Duration in units of 128us (1/8 TU).
1950 */
31604cf0 1951static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 1952{
31604cf0 1953 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 1954
f1dc5600 1955 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1956
31604cf0
SM		 1957 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1958 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1959 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1960 AR_RTC_FORCE_WAKE_ON_INT);
1961 } else {
2577c6e8 1962
31604cf0
SM		 1963 /* When chip goes into network sleep, it could be waken
1964 * up by MCI_INT interrupt caused by BT's HW messages
1965 * (LNA_xxx, CONT_xxx) which chould be in a very fast
1966 * rate (~100us). This will cause chip to leave and
1967 * re-enter network sleep mode frequently, which in
1968 * consequence will have WLAN MCI HW to generate lots of
1969 * SYS_WAKING and SYS_SLEEPING messages which will make
1970 * BT CPU to busy to process.
1971 */
153dccd4
RM		 1972 if (ath9k_hw_mci_is_enabled(ah))
1973 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
1974 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 1975 /*
1976 * Clear the RTC force wake bit to allow the
1977 * mac to go to sleep.
1978 */
153dccd4 1979 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 1980
153dccd4 1981 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 1982 udelay(30);
f078f209 1983 }
9a658d2b
LR		 1984
1985 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1986 if (AR_SREV_9300_20_OR_LATER(ah))
1987 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1988}
1989
31604cf0 1990static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 1991{
f1dc5600
S		 1992 u32 val;
1993 int i;
f078f209 1994
9a658d2b
LR		 1995 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1996 if (AR_SREV_9300_20_OR_LATER(ah)) {
1997 REG_WRITE(ah, AR_WA, ah->WARegVal);
1998 udelay(10);
1999 }
2000
31604cf0
SM		 2001 if ((REG_READ(ah, AR_RTC_STATUS) &
2002 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2003 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2004 return false;
f1dc5600 2005 }
31604cf0
SM		 2006 if (!AR_SREV_9300_20_OR_LATER(ah))
2007 ath9k_hw_init_pll(ah, NULL);
2008 }
2009 if (AR_SREV_9100(ah))
2010 REG_SET_BIT(ah, AR_RTC_RESET,
2011 AR_RTC_RESET_EN);
2012
2013 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2014 AR_RTC_FORCE_WAKE_EN);
2015 udelay(50);
f078f209 2016
31604cf0
SM		 2017 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2018 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2019 if (val == AR_RTC_STATUS_ON)
2020 break;
2021 udelay(50);
f1dc5600
S		 2022 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2023 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2024 }
2025 if (i == 0) {
2026 ath_err(ath9k_hw_common(ah),
2027 "Failed to wakeup in %uus\n",
2028 POWER_UP_TIME / 20);
2029 return false;
f078f209
LR		 2030 }
2031
cdbe408d
RM		 2032 if (ath9k_hw_mci_is_enabled(ah))
2033 ar9003_mci_set_power_awake(ah);
2034
f1dc5600 2035 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2036
f1dc5600 2037 return true;
f078f209
LR		 2038}
2039
9ecdef4b 2040bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2041{
c46917bb 2042 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2043 int status = true;
f1dc5600
S		 2044 static const char *modes[] = {
2045 "AWAKE",
2046 "FULL-SLEEP",
2047 "NETWORK SLEEP",
2048 "UNDEFINED"
2049 };
f1dc5600 2050
cbdec975
GJ		 2051 if (ah->power_mode == mode)
2052 return status;
2053
d2182b69 2054 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2055 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2056
2057 switch (mode) {
2058 case ATH9K_PM_AWAKE:
31604cf0 2059 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2060 break;
2061 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2062 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2063 ar9003_mci_set_full_sleep(ah);
1010911e 2064
31604cf0 2065 ath9k_set_power_sleep(ah);
2660b81a 2066 ah->chip_fullsleep = true;
f1dc5600
S		 2067 break;
2068 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2069 ath9k_set_power_network_sleep(ah);
f1dc5600 2070 break;
f078f209 2071 default:
3800276a 2072 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2073 return false;
2074 }
2660b81a 2075 ah->power_mode = mode;
f1dc5600 2076
69f4aab1
LR		 2077 /*
2078 * XXX: If this warning never comes up after a while then
2079 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2080 * ath9k_hw_setpower() return type void.
2081 */
97dcec57
SM		 2082
2083 if (!(ah->ah_flags & AH_UNPLUGGED))
2084 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2085
f1dc5600 2086 return status;
f078f209 2087}
7322fd19 2088EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2089
f1dc5600
S		 2090/*******************/
2091/* Beacon Handling */
2092/*******************/
2093
cbe61d8a 2094void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2095{
f078f209
LR		 2096 int flags = 0;
2097
7d0d0df0
S		 2098 ENABLE_REGWRITE_BUFFER(ah);
2099
2660b81a 2100 switch (ah->opmode) {
d97809db 2101 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2102 REG_SET_BIT(ah, AR_TXCFG,
2103 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2104 case NL80211_IFTYPE_MESH_POINT:
d97809db 2105 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2106 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2107 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2108 TU_TO_USEC(ah->config.dma_beacon_response_time));
2109 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2110 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2111 flags |=
2112 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2113 break;
d97809db 2114 default:
d2182b69
JP		 2115 ath_dbg(ath9k_hw_common(ah), BEACON,
2116 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2117 return;
2118 break;
f078f209
LR		 2119 }
2120
dd347f2f
FF		 2121 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2122 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2123 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2124
7d0d0df0 2125 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2126
f078f209
LR		 2127 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2128}
7322fd19 2129EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2130
cbe61d8a 2131void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2132 const struct ath9k_beacon_state *bs)
f078f209
LR		 2133{
2134 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2135 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2136 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2137
7d0d0df0
S		 2138 ENABLE_REGWRITE_BUFFER(ah);
2139
4ed15762
FF		 2140 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2141 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2142 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2143
7d0d0df0 2144 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2145
f078f209
LR		 2146 REG_RMW_FIELD(ah, AR_RSSI_THR,
2147 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2148
f29f5c08 2149 beaconintval = bs->bs_intval;
f078f209
LR		 2150
2151 if (bs->bs_sleepduration > beaconintval)
2152 beaconintval = bs->bs_sleepduration;
2153
2154 dtimperiod = bs->bs_dtimperiod;
2155 if (bs->bs_sleepduration > dtimperiod)
2156 dtimperiod = bs->bs_sleepduration;
2157
2158 if (beaconintval == dtimperiod)
2159 nextTbtt = bs->bs_nextdtim;
2160 else
2161 nextTbtt = bs->bs_nexttbtt;
2162
d2182b69
JP		 2163 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2164 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2165 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2166 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2167
7d0d0df0
S		 2168 ENABLE_REGWRITE_BUFFER(ah);
2169
4ed15762
FF		 2170 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2171 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2172
f1dc5600
S		 2173 REG_WRITE(ah, AR_SLEEP1,
2174 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2175 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2176
f1dc5600
S		 2177 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2178 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2179 else
2180 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2181
f1dc5600
S		 2182 REG_WRITE(ah, AR_SLEEP2,
2183 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2184
4ed15762
FF		 2185 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2186 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2187
7d0d0df0 2188 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2189
f1dc5600
S		 2190 REG_SET_BIT(ah, AR_TIMER_MODE,
2191 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2192 AR_DTIM_TIMER_EN);
f078f209 2193
4af9cf4f
S		 2194 /* TSF Out of Range Threshold */
2195 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2196}
7322fd19 2197EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2198
f1dc5600
S		 2199/*******************/
2200/* HW Capabilities */
2201/*******************/
2202
6054069a
FF		 2203static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2204{
2205 eeprom_chainmask &= chip_chainmask;
2206 if (eeprom_chainmask)
2207 return eeprom_chainmask;
2208 else
2209 return chip_chainmask;
2210}
2211
9a66af33
ZK		 2212/**
2213 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2214 * @ah: the atheros hardware data structure
2215 *
2216 * We enable DFS support upstream on chipsets which have passed a series
2217 * of tests. The testing requirements are going to be documented. Desired
2218 * test requirements are documented at:
2219 *
2220 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2221 *
2222 * Once a new chipset gets properly tested an individual commit can be used
2223 * to document the testing for DFS for that chipset.
2224 */
2225static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2226{
2227
2228 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2229 /* for temporary testing DFS with 9280 */
2230 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2231 /* AR9580 will likely be our first target to get testing on */
2232 case AR_SREV_VERSION_9580:
73e4937d 2233 return true;
9a66af33
ZK		 2234 default:
2235 return false;
2236 }
2237}
2238
a9a29ce6 2239int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2240{
2660b81a 2241 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2242 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2243 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2244 unsigned int chip_chainmask;
608b88cb 2245
0ff2b5c0 2246 u16 eeval;
47c80de6 2247 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2248
f74df6fb 2249 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2250 regulatory->current_rd = eeval;
f078f209 2251
2660b81a 2252 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2253 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2254 if (regulatory->current_rd == 0x64 ||
2255 regulatory->current_rd == 0x65)
2256 regulatory->current_rd += 5;
2257 else if (regulatory->current_rd == 0x41)
2258 regulatory->current_rd = 0x43;
d2182b69
JP		 2259 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2260 regulatory->current_rd);
f1dc5600 2261 }
f078f209 2262
f74df6fb 2263 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2264 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2265 ath_err(common,
2266 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2267 return -EINVAL;
2268 }
2269
d4659912
FF		 2270 if (eeval & AR5416_OPFLAGS_11A)
2271 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2272
d4659912
FF		 2273 if (eeval & AR5416_OPFLAGS_11G)
2274 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2275
e41db61d
SM		 2276 if (AR_SREV_9485(ah) ||
2277 AR_SREV_9285(ah) ||
2278 AR_SREV_9330(ah) ||
2279 AR_SREV_9565(ah))
6054069a 2280 chip_chainmask = 1;
ba5736a5
MSS		 2281 else if (AR_SREV_9462(ah))
2282 chip_chainmask = 3;
6054069a
FF		 2283 else if (!AR_SREV_9280_20_OR_LATER(ah))
2284 chip_chainmask = 7;
2285 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2286 chip_chainmask = 3;
2287 else
2288 chip_chainmask = 7;
2289
f74df6fb 2290 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2291 /*
2292 * For AR9271 we will temporarilly uses the rx chainmax as read from
2293 * the EEPROM.
2294 */
8147f5de 2295 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2296 !(eeval & AR5416_OPFLAGS_11A) &&
2297 !(AR_SREV_9271(ah)))
2298 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2299 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2300 else if (AR_SREV_9100(ah))
2301 pCap->rx_chainmask = 0x7;
8147f5de 2302 else
d7e7d229 2303 /* Use rx_chainmask from EEPROM. */
8147f5de 2304 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2305
6054069a
FF		 2306 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2307 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2308 ah->txchainmask = pCap->tx_chainmask;
2309 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2310
7a37081e 2311 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2312
02d2ebb2
FF		 2313 /* enable key search for every frame in an aggregate */
2314 if (AR_SREV_9300_20_OR_LATER(ah))
2315 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2316
ce2220d1
BR		 2317 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2318
0db156e9 2319 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2320 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2321 else
2322 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2323
5b5fa355
S		 2324 if (AR_SREV_9271(ah))
2325 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2326 else if (AR_DEVID_7010(ah))
2327 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2328 else if (AR_SREV_9300_20_OR_LATER(ah))
2329 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2330 else if (AR_SREV_9287_11_OR_LATER(ah))
2331 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2332 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2333 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2334 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2335 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2336 else
2337 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2338
1b2538b2 2339 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2340 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2341 else
f1dc5600 2342 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2343
74e13060 2344#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2345 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2346 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2347 ah->rfkill_gpio =
2348 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2349 ah->rfkill_polarity =
2350 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2351
2352 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2353 }
f1dc5600 2354#endif
d5d1154f 2355 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2356 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2357 else
2358 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2359
e7594072 2360 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2361 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2362 else
2363 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2364
ceb26445 2365 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2366 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
a4a2954f 2367 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2368 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2369
ceb26445
VT		 2370 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2371 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2372 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2373 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2374 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2375 } else {
2376 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2377 if (AR_SREV_9280_20(ah))
6b42e8d0 2378 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2379 }
1adf02ff 2380
6c84ce08
VT		 2381 if (AR_SREV_9300_20_OR_LATER(ah))
2382 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2383
6ee63f55
SB		 2384 if (AR_SREV_9300_20_OR_LATER(ah))
2385 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2386
a42acef0 2387 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2388 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2389
f85c3371 2390 if (AR_SREV_9285(ah)) {
754dc536
VT		 2391 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2392 ant_div_ctl1 =
2393 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2394 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2395 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2396 ath_info(common, "Enable LNA combining\n");
2397 }
754dc536 2398 }
f85c3371
SM		 2399 }
2400
ea066d5a
MSS		 2401 if (AR_SREV_9300_20_OR_LATER(ah)) {
2402 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2403 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2404 }
2405
06236e53 2406 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2407 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2408 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2409 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2410 ath_info(common, "Enable LNA combining\n");
2411 }
21d2c63a 2412 }
754dc536 2413
9a66af33
ZK		 2414 if (ath9k_hw_dfs_tested(ah))
2415 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2416
47c80de6
VT		 2417 tx_chainmask = pCap->tx_chainmask;
2418 rx_chainmask = pCap->rx_chainmask;
2419 while (tx_chainmask || rx_chainmask) {
2420 if (tx_chainmask & BIT(0))
2421 pCap->max_txchains++;
2422 if (rx_chainmask & BIT(0))
2423 pCap->max_rxchains++;
2424
2425 tx_chainmask >>= 1;
2426 rx_chainmask >>= 1;
2427 }
2428
a4a2954f 2429 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2430 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2431 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2432
2b5e54e2 2433 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2434 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2435 }
2436
846e438f
SM		 2437 if (AR_SREV_9462(ah))
2438 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
d687809b 2439
0f21ee8d
SM		 2440 if (AR_SREV_9300_20_OR_LATER(ah) &&
2441 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2442 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2443
81dc75b5
SM		 2444 /*
2445 * Fast channel change across bands is available
2446 * only for AR9462 and AR9565.
2447 */
2448 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2449 pCap->hw_caps |= ATH9K_HW_CAP_FCC_BAND_SWITCH;
2450
a9a29ce6 2451 return 0;
f078f209
LR		 2452}
2453
f1dc5600
S		 2454/****************************/
2455/* GPIO / RFKILL / Antennae */
2456/****************************/
f078f209 2457
cbe61d8a 2458static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2459 u32 gpio, u32 type)
2460{
2461 int addr;
2462 u32 gpio_shift, tmp;
f078f209 2463
f1dc5600
S		 2464 if (gpio > 11)
2465 addr = AR_GPIO_OUTPUT_MUX3;
2466 else if (gpio > 5)
2467 addr = AR_GPIO_OUTPUT_MUX2;
2468 else
2469 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2470
f1dc5600 2471 gpio_shift = (gpio % 6) * 5;
f078f209 2472
f1dc5600
S		 2473 if (AR_SREV_9280_20_OR_LATER(ah)
2474 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2475 REG_RMW(ah, addr, (type << gpio_shift),
2476 (0x1f << gpio_shift));
f078f209 2477 } else {
f1dc5600
S		 2478 tmp = REG_READ(ah, addr);
2479 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2480 tmp &= ~(0x1f << gpio_shift);
2481 tmp |= (type << gpio_shift);
2482 REG_WRITE(ah, addr, tmp);
f078f209 2483 }
f078f209
LR		 2484}
2485
cbe61d8a 2486void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2487{
f1dc5600 2488 u32 gpio_shift;
f078f209 2489
9680e8a3 2490 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2491
88c1f4f6
S		 2492 if (AR_DEVID_7010(ah)) {
2493 gpio_shift = gpio;
2494 REG_RMW(ah, AR7010_GPIO_OE,
2495 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2496 (AR7010_GPIO_OE_MASK << gpio_shift));
2497 return;
2498 }
f078f209 2499
88c1f4f6 2500 gpio_shift = gpio << 1;
f1dc5600
S		 2501 REG_RMW(ah,
2502 AR_GPIO_OE_OUT,
2503 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2504 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2505}
7322fd19 2506EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2507
cbe61d8a 2508u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2509{
cb33c412
SB		 2510#define MS_REG_READ(x, y) \
2511 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2512
2660b81a 2513 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2514 return 0xffffffff;
f078f209 2515
88c1f4f6
S		 2516 if (AR_DEVID_7010(ah)) {
2517 u32 val;
2518 val = REG_READ(ah, AR7010_GPIO_IN);
2519 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2520 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2521 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2522 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2523 else if (AR_SREV_9271(ah))
5b5fa355 2524 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2525 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2526 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2527 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2528 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2529 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2530 return MS_REG_READ(AR928X, gpio) != 0;
2531 else
2532 return MS_REG_READ(AR, gpio) != 0;
f078f209 2533}
7322fd19 2534EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2535
cbe61d8a 2536void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2537 u32 ah_signal_type)
f078f209 2538{
f1dc5600 2539 u32 gpio_shift;
f078f209 2540
88c1f4f6
S		 2541 if (AR_DEVID_7010(ah)) {
2542 gpio_shift = gpio;
2543 REG_RMW(ah, AR7010_GPIO_OE,
2544 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2545 (AR7010_GPIO_OE_MASK << gpio_shift));
2546 return;
2547 }
f078f209 2548
88c1f4f6 2549 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2550 gpio_shift = 2 * gpio;
f1dc5600
S		 2551 REG_RMW(ah,
2552 AR_GPIO_OE_OUT,
2553 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2554 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2555}
7322fd19 2556EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2557
cbe61d8a 2558void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2559{
88c1f4f6
S		 2560 if (AR_DEVID_7010(ah)) {
2561 val = val ? 0 : 1;
2562 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2563 AR_GPIO_BIT(gpio));
2564 return;
2565 }
2566
5b5fa355
S		 2567 if (AR_SREV_9271(ah))
2568 val = ~val;
2569
f1dc5600
S		 2570 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2571 AR_GPIO_BIT(gpio));
f078f209 2572}
7322fd19 2573EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2574
cbe61d8a 2575void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2576{
f1dc5600 2577 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2578}
7322fd19 2579EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2580
f1dc5600
S		 2581/*********************/
2582/* General Operation */
2583/*********************/
2584
cbe61d8a 2585u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2586{
f1dc5600
S		 2587 u32 bits = REG_READ(ah, AR_RX_FILTER);
2588 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2589
f1dc5600
S		 2590 if (phybits & AR_PHY_ERR_RADAR)
2591 bits |= ATH9K_RX_FILTER_PHYRADAR;
2592 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2593 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2594
f1dc5600 2595 return bits;
f078f209 2596}
7322fd19 2597EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2598
cbe61d8a 2599void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2600{
f1dc5600 2601 u32 phybits;
f078f209 2602
7d0d0df0
S		 2603 ENABLE_REGWRITE_BUFFER(ah);
2604
a4a2954f 2605 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2577c6e8
SB		 2606 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2607
7ea310be
S		 2608 REG_WRITE(ah, AR_RX_FILTER, bits);
2609
f1dc5600
S		 2610 phybits = 0;
2611 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2612 phybits |= AR_PHY_ERR_RADAR;
2613 if (bits & ATH9K_RX_FILTER_PHYERR)
2614 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2615 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2616
f1dc5600 2617 if (phybits)
ca7a4deb 2618 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2619 else
ca7a4deb 2620 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2621
2622 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2623}
7322fd19 2624EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2625
cbe61d8a 2626bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2627{
99922a45
RM		 2628 if (ath9k_hw_mci_is_enabled(ah))
2629 ar9003_mci_bt_gain_ctrl(ah);
2630
63a75b91
SB		 2631 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2632 return false;
2633
2634 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2635 ah->htc_reset_init = true;
63a75b91 2636 return true;
f1dc5600 2637}
7322fd19 2638EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2639
cbe61d8a 2640bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2641{
9ecdef4b 2642 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2643 return false;
f078f209 2644
63a75b91
SB		 2645 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2646 return false;
2647
2648 ath9k_hw_init_pll(ah, NULL);
2649 return true;
f078f209 2650}
7322fd19 2651EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2652
ca2c68cc
FF		 2653static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2654{
2655 enum eeprom_param gain_param;
2656
2657 if (IS_CHAN_2GHZ(chan))
2658 gain_param = EEP_ANTENNA_GAIN_2G;
2659 else
2660 gain_param = EEP_ANTENNA_GAIN_5G;
2661
2662 return ah->eep_ops->get_eeprom(ah, gain_param);
2663}
2664
64ea57d0
GJ		 2665void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2666 bool test)
ca2c68cc
FF		 2667{
2668 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2669 struct ieee80211_channel *channel;
2670 int chan_pwr, new_pwr, max_gain;
2671 int ant_gain, ant_reduction = 0;
2672
2673 if (!chan)
2674 return;
2675
2676 channel = chan->chan;
2677 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2678 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2679 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2680
2681 ant_gain = get_antenna_gain(ah, chan);
2682 if (ant_gain > max_gain)
2683 ant_reduction = ant_gain - max_gain;
2684
2685 ah->eep_ops->set_txpower(ah, chan,
2686 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2687 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2688}
2689
de40f316 2690void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2691{
ca2c68cc 2692 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2693 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2694 struct ieee80211_channel *channel = chan->chan;
9c204b46 2695
48ef5c42 2696 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2697 if (test)
ca2c68cc 2698 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2699
64ea57d0 2700 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2701
ca2c68cc
FF		 2702 if (test)
2703 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2704}
7322fd19 2705EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2706
cbe61d8a 2707void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2708{
2660b81a 2709 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2710}
7322fd19 2711EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2712
cbe61d8a 2713void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2714{
f1dc5600
S		 2715 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2716 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2717}
7322fd19 2718EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2719
f2b2143e 2720void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2721{
1510718d
LR		 2722 struct ath_common *common = ath9k_hw_common(ah);
2723
2724 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2725 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2726 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2727}
7322fd19 2728EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2729
1c0fc65e
BP		 2730#define ATH9K_MAX_TSF_READ 10
2731
cbe61d8a 2732u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2733{
1c0fc65e
BP		 2734 u32 tsf_lower, tsf_upper1, tsf_upper2;
2735 int i;
2736
2737 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2738 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2739 tsf_lower = REG_READ(ah, AR_TSF_L32);
2740 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2741 if (tsf_upper2 == tsf_upper1)
2742 break;
2743 tsf_upper1 = tsf_upper2;
2744 }
f078f209 2745
1c0fc65e 2746 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2747
1c0fc65e 2748 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2749}
7322fd19 2750EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2751
cbe61d8a 2752void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2753{
27abe060 2754 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2755 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2756}
7322fd19 2757EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2758
cbe61d8a 2759void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2760{
f9b604f6
GJ		 2761 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2762 AH_TSF_WRITE_TIMEOUT))
d2182b69 2763 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2764 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2765
f1dc5600
S		 2766 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2767}
7322fd19 2768EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2769
60ca9f87 2770void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 2771{
60ca9f87 2772 if (set)
2660b81a 2773 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2774 else
2660b81a 2775 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2776}
7322fd19 2777EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2778
e4744ec7 2779void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 2780{
2781 u32 macmode;
2782
e4744ec7 2783 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2784 macmode = AR_2040_JOINED_RX_CLEAR;
2785 else
2786 macmode = 0;
f078f209 2787
f1dc5600 2788 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2789}
ff155a45
VT		 2790
2791/* HW Generic timers configuration */
2792
2793static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2794{
2795 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2796 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2797 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2798 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2799 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2800 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2801 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2802 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2803 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2804 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2805 AR_NDP2_TIMER_MODE, 0x0002},
2806 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2807 AR_NDP2_TIMER_MODE, 0x0004},
2808 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2809 AR_NDP2_TIMER_MODE, 0x0008},
2810 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2811 AR_NDP2_TIMER_MODE, 0x0010},
2812 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2813 AR_NDP2_TIMER_MODE, 0x0020},
2814 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2815 AR_NDP2_TIMER_MODE, 0x0040},
2816 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2817 AR_NDP2_TIMER_MODE, 0x0080}
2818};
2819
2820/* HW generic timer primitives */
2821
dd347f2f 2822u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2823{
2824 return REG_READ(ah, AR_TSF_L32);
2825}
dd347f2f 2826EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2827
2828struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2829 void (*trigger)(void *),
2830 void (*overflow)(void *),
2831 void *arg,
2832 u8 timer_index)
2833{
2834 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2835 struct ath_gen_timer *timer;
2836
c67ce339
FF		 2837 if ((timer_index < AR_FIRST_NDP_TIMER) ||
2838 (timer_index >= ATH_MAX_GEN_TIMER))
2839 return NULL;
2840
ff155a45 2841 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 2842 if (timer == NULL)
ff155a45 2843 return NULL;
ff155a45
VT		 2844
2845 /* allocate a hardware generic timer slot */
2846 timer_table->timers[timer_index] = timer;
2847 timer->index = timer_index;
2848 timer->trigger = trigger;
2849 timer->overflow = overflow;
2850 timer->arg = arg;
2851
2852 return timer;
2853}
7322fd19 2854EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2855
cd9bf689
LR		 2856void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2857 struct ath_gen_timer *timer,
c67ce339 2858 u32 timer_next,
cd9bf689 2859 u32 timer_period)
ff155a45
VT		 2860{
2861 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 2862 u32 mask = 0;
788f6875 2863
c67ce339 2864 timer_table->timer_mask |= BIT(timer->index);
ff155a45 2865
ff155a45
VT		 2866 /*
2867 * Program generic timer registers
2868 */
2869 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2870 timer_next);
2871 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2872 timer_period);
2873 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2874 gen_tmr_configuration[timer->index].mode_mask);
2875
a4a2954f 2876 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 2877 /*
423e38e8 2878 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 2879 * to use. But we still follow the old rule, 0 - 7 use tsf and
2880 * 8 - 15 use tsf2.
2881 */
2882 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2883 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2884 (1 << timer->index));
2885 else
2886 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2887 (1 << timer->index));
2888 }
2889
c67ce339
FF		 2890 if (timer->trigger)
2891 mask |= SM(AR_GENTMR_BIT(timer->index),
2892 AR_IMR_S5_GENTIMER_TRIG);
2893 if (timer->overflow)
2894 mask |= SM(AR_GENTMR_BIT(timer->index),
2895 AR_IMR_S5_GENTIMER_THRESH);
2896
2897 REG_SET_BIT(ah, AR_IMR_S5, mask);
2898
2899 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
2900 ah->imask |= ATH9K_INT_GENTIMER;
2901 ath9k_hw_set_interrupts(ah);
2902 }
ff155a45 2903}
7322fd19 2904EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2905
cd9bf689 2906void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2907{
2908 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2909
ff155a45
VT		 2910 /* Clear generic timer enable bits. */
2911 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2912 gen_tmr_configuration[timer->index].mode_mask);
2913
b7f59766
SM		 2914 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2915 /*
2916 * Need to switch back to TSF if it was using TSF2.
2917 */
2918 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
2919 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2920 (1 << timer->index));
2921 }
2922 }
2923
ff155a45
VT		 2924 /* Disable both trigger and thresh interrupt masks */
2925 REG_CLR_BIT(ah, AR_IMR_S5,
2926 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2927 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2928
c67ce339
FF		 2929 timer_table->timer_mask &= ~BIT(timer->index);
2930
2931 if (timer_table->timer_mask == 0) {
2932 ah->imask &= ~ATH9K_INT_GENTIMER;
2933 ath9k_hw_set_interrupts(ah);
2934 }
ff155a45 2935}
7322fd19 2936EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2937
2938void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2939{
2940 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2941
2942 /* free the hardware generic timer slot */
2943 timer_table->timers[timer->index] = NULL;
2944 kfree(timer);
2945}
7322fd19 2946EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2947
2948/*
2949 * Generic Timer Interrupts handling
2950 */
2951void ath_gen_timer_isr(struct ath_hw *ah)
2952{
2953 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2954 struct ath_gen_timer *timer;
c67ce339
FF		 2955 unsigned long trigger_mask, thresh_mask;
2956 unsigned int index;
ff155a45
VT		 2957
2958 /* get hardware generic timer interrupt status */
2959 trigger_mask = ah->intr_gen_timer_trigger;
2960 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 2961 trigger_mask &= timer_table->timer_mask;
2962 thresh_mask &= timer_table->timer_mask;
ff155a45 2963
c67ce339 2964 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 2965 timer = timer_table->timers[index];
c67ce339
FF		 2966 if (!timer)
2967 continue;
2968 if (!timer->overflow)
2969 continue;
a6a172b2
FF		 2970
2971 trigger_mask &= ~BIT(index);
ff155a45
VT		 2972 timer->overflow(timer->arg);
2973 }
2974
c67ce339 2975 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 2976 timer = timer_table->timers[index];
c67ce339
FF		 2977 if (!timer)
2978 continue;
2979 if (!timer->trigger)
2980 continue;
ff155a45
VT		 2981 timer->trigger(timer->arg);
2982 }
2983}
7322fd19 2984EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2985
05020d23
S		 2986/********/
2987/* HTC */
2988/********/
2989
2da4f01a
LR		 2990static struct {
2991 u32 version;
2992 const char * name;
2993} ath_mac_bb_names[] = {
2994 /* Devices with external radios */
2995 { AR_SREV_VERSION_5416_PCI, "5416" },
2996 { AR_SREV_VERSION_5416_PCIE, "5418" },
2997 { AR_SREV_VERSION_9100, "9100" },
2998 { AR_SREV_VERSION_9160, "9160" },
2999 /* Single-chip solutions */
3000 { AR_SREV_VERSION_9280, "9280" },
3001 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3002 { AR_SREV_VERSION_9287, "9287" },
3003 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3004 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3005 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3006 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3007 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3008 { AR_SREV_VERSION_9462, "9462" },
485124cb 3009 { AR_SREV_VERSION_9550, "9550" },
77fac465 3010 { AR_SREV_VERSION_9565, "9565" },
2da4f01a
LR		 3011};
3012
3013/* For devices with external radios */
3014static struct {
3015 u16 version;
3016 const char * name;
3017} ath_rf_names[] = {
3018 { 0, "5133" },
3019 { AR_RAD5133_SREV_MAJOR, "5133" },
3020 { AR_RAD5122_SREV_MAJOR, "5122" },
3021 { AR_RAD2133_SREV_MAJOR, "2133" },
3022 { AR_RAD2122_SREV_MAJOR, "2122" }
3023};
3024
3025/*
3026 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3027 */
f934c4d9 3028static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3029{
3030 int i;
3031
3032 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3033 if (ath_mac_bb_names[i].version == mac_bb_version) {
3034 return ath_mac_bb_names[i].name;
3035 }
3036 }
3037
3038 return "????";
3039}
2da4f01a
LR		 3040
3041/*
3042 * Return the RF name. "????" is returned if the RF is unknown.
3043 * Used for devices with external radios.
3044 */
f934c4d9 3045static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3046{
3047 int i;
3048
3049 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3050 if (ath_rf_names[i].version == rf_version) {
3051 return ath_rf_names[i].name;
3052 }
3053 }
3054
3055 return "????";
3056}
f934c4d9
LR		 3057
3058void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3059{
3060 int used;
3061
3062 /* chipsets >= AR9280 are single-chip */
7a37081e 3063 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3064 used = scnprintf(hw_name, len,
3065 "Atheros AR%s Rev:%x",
3066 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3067 ah->hw_version.macRev);
f934c4d9
LR		 3068 }
3069 else {
5e88ba62
ZK		 3070 used = scnprintf(hw_name, len,
3071 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3072 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3073 ah->hw_version.macRev,
3074 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3075 & AR_RADIO_SREV_MAJOR)),
3076 ah->hw_version.phyRev);
f934c4d9
LR		 3077 }
3078
3079 hw_name[used] = '\0';
3080}
3081EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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