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ath9k_hw: remove ATH9K_CAP_TKIP_SPLIT
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
f078f209
LR		 19#include <asm/unaligned.h>
20
af03abec 21#include "hw.h"
d70357d5 22#include "hw-ops.h"
cfe8cba9 23#include "rc.h"
b622a720 24#include "ar9003_mac.h"
f078f209 25
cbe61d8a 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 27
7322fd19
LR		 28MODULE_AUTHOR("Atheros Communications");
29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31MODULE_LICENSE("Dual BSD/GPL");
32
33static int __init ath9k_init(void)
34{
35 return 0;
36}
37module_init(ath9k_init);
38
39static void __exit ath9k_exit(void)
40{
41 return;
42}
43module_exit(ath9k_exit);
44
d70357d5
LR		 45/* Private hardware callbacks */
46
47static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48{
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50}
51
52static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55}
56
57static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
58{
59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
60
61 return priv_ops->macversion_supported(ah->hw_version.macVersion);
62}
63
64773964
LR		 64static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
65 struct ath9k_channel *chan)
66{
67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
68}
69
991312d8
LR		 70static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
71{
72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
73 return;
74
75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
76}
77
e36b27af
LR		 78static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
79{
80 /* You will not have this callback if using the old ANI */
81 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
82 return;
83
84 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
85}
86
f1dc5600
S		 87/********************/
88/* Helper Functions */
89/********************/
f078f209 90
cbe61d8a 91static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 92{
b002a4a9 93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 94
2660b81a 95 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 96 return usecs *ATH9K_CLOCK_RATE_CCK;
97 if (conf->channel->band == IEEE80211_BAND_2GHZ)
98 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
e5553724
VT		 99
100 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
101 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
102 else
103 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 104}
105
cbe61d8a 106static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 107{
b002a4a9 108 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 109
4febf7b8 110 if (conf_is_ht40(conf))
f1dc5600
S		 111 return ath9k_hw_mac_clks(ah, usecs) * 2;
112 else
113 return ath9k_hw_mac_clks(ah, usecs);
114}
f078f209 115
0caa7b14 116bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 117{
118 int i;
119
0caa7b14
S		 120 BUG_ON(timeout < AH_TIME_QUANTUM);
121
122 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 123 if ((REG_READ(ah, reg) & mask) == val)
124 return true;
125
126 udelay(AH_TIME_QUANTUM);
127 }
04bd4638 128
c46917bb
LR		 129 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
131 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 132
f1dc5600 133 return false;
f078f209 134}
7322fd19 135EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 136
137u32 ath9k_hw_reverse_bits(u32 val, u32 n)
138{
139 u32 retval;
140 int i;
141
142 for (i = 0, retval = 0; i < n; i++) {
143 retval = (retval << 1) | (val & 1);
144 val >>= 1;
145 }
146 return retval;
147}
148
cbe61d8a 149bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 150 u16 flags, u16 *low,
151 u16 *high)
f078f209 152{
2660b81a 153 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 154
f1dc5600
S		 155 if (flags & CHANNEL_5GHZ) {
156 *low = pCap->low_5ghz_chan;
157 *high = pCap->high_5ghz_chan;
158 return true;
f078f209 159 }
f1dc5600
S		 160 if ((flags & CHANNEL_2GHZ)) {
161 *low = pCap->low_2ghz_chan;
162 *high = pCap->high_2ghz_chan;
163 return true;
164 }
165 return false;
f078f209
LR		 166}
167
cbe61d8a 168u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 169 u8 phy, int kbps,
f1dc5600
S		 170 u32 frameLen, u16 rateix,
171 bool shortPreamble)
f078f209 172{
f1dc5600 173 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 174
f1dc5600
S		 175 if (kbps == 0)
176 return 0;
f078f209 177
545750d3 178 switch (phy) {
46d14a58 179 case WLAN_RC_PHY_CCK:
f1dc5600 180 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 181 if (shortPreamble)
f1dc5600
S		 182 phyTime >>= 1;
183 numBits = frameLen << 3;
184 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
185 break;
46d14a58 186 case WLAN_RC_PHY_OFDM:
2660b81a 187 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 188 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
189 numBits = OFDM_PLCP_BITS + (frameLen << 3);
190 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
191 txTime = OFDM_SIFS_TIME_QUARTER
192 + OFDM_PREAMBLE_TIME_QUARTER
193 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 194 } else if (ah->curchan &&
195 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 196 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
197 numBits = OFDM_PLCP_BITS + (frameLen << 3);
198 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
199 txTime = OFDM_SIFS_TIME_HALF +
200 OFDM_PREAMBLE_TIME_HALF
201 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
202 } else {
203 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
204 numBits = OFDM_PLCP_BITS + (frameLen << 3);
205 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
206 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
207 + (numSymbols * OFDM_SYMBOL_TIME);
208 }
209 break;
210 default:
c46917bb 211 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 212 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 213 txTime = 0;
214 break;
215 }
f078f209 216
f1dc5600
S		 217 return txTime;
218}
7322fd19 219EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 220
cbe61d8a 221void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 222 struct ath9k_channel *chan,
223 struct chan_centers *centers)
f078f209 224{
f1dc5600 225 int8_t extoff;
f078f209 226
f1dc5600
S		 227 if (!IS_CHAN_HT40(chan)) {
228 centers->ctl_center = centers->ext_center =
229 centers->synth_center = chan->channel;
230 return;
f078f209 231 }
f078f209 232
f1dc5600
S		 233 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
234 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
235 centers->synth_center =
236 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
237 extoff = 1;
238 } else {
239 centers->synth_center =
240 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
241 extoff = -1;
242 }
f078f209 243
f1dc5600
S		 244 centers->ctl_center =
245 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 246 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 247 centers->ext_center =
6420014c 248 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 249}
250
f1dc5600
S		 251/******************/
252/* Chip Revisions */
253/******************/
254
cbe61d8a 255static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 256{
f1dc5600 257 u32 val;
f078f209 258
f1dc5600 259 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 260
f1dc5600
S		 261 if (val == 0xFF) {
262 val = REG_READ(ah, AR_SREV);
d535a42a
S		 263 ah->hw_version.macVersion =
264 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
265 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 266 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 267 } else {
268 if (!AR_SREV_9100(ah))
d535a42a 269 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 270
d535a42a 271 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 272
d535a42a 273 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 274 ah->is_pciexpress = true;
f1dc5600 275 }
f078f209
LR		 276}
277
f1dc5600
S		 278/************************************/
279/* HW Attach, Detach, Init Routines */
280/************************************/
281
cbe61d8a 282static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 283{
feed029c 284 if (AR_SREV_9100(ah))
f1dc5600 285 return;
f078f209 286
7d0d0df0
S		 287 ENABLE_REGWRITE_BUFFER(ah);
288
f1dc5600
S		 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 298
f1dc5600 299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
7d0d0df0
S		 300
301 REGWRITE_BUFFER_FLUSH(ah);
302 DISABLE_REGWRITE_BUFFER(ah);
f078f209
LR		 303}
304
1f3f0618 305/* This should work for all families including legacy */
cbe61d8a 306static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 307{
c46917bb 308 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 309 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600
S		 310 u32 regHold[2];
311 u32 patternData[4] = { 0x55555555,
312 0xaaaaaaaa,
313 0x66666666,
314 0x99999999 };
1f3f0618 315 int i, j, loop_max;
f078f209 316
1f3f0618
SB		 317 if (!AR_SREV_9300_20_OR_LATER(ah)) {
318 loop_max = 2;
319 regAddr[1] = AR_PHY_BASE + (8 << 2);
320 } else
321 loop_max = 1;
322
323 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 324 u32 addr = regAddr[i];
325 u32 wrData, rdData;
f078f209 326
f1dc5600
S		 327 regHold[i] = REG_READ(ah, addr);
328 for (j = 0; j < 0x100; j++) {
329 wrData = (j << 16) | j;
330 REG_WRITE(ah, addr, wrData);
331 rdData = REG_READ(ah, addr);
332 if (rdData != wrData) {
c46917bb
LR		 333 ath_print(common, ATH_DBG_FATAL,
334 "address test failed "
335 "addr: 0x%08x - wr:0x%08x != "
336 "rd:0x%08x\n",
337 addr, wrData, rdData);
f1dc5600
S		 338 return false;
339 }
340 }
341 for (j = 0; j < 4; j++) {
342 wrData = patternData[j];
343 REG_WRITE(ah, addr, wrData);
344 rdData = REG_READ(ah, addr);
345 if (wrData != rdData) {
c46917bb
LR		 346 ath_print(common, ATH_DBG_FATAL,
347 "address test failed "
348 "addr: 0x%08x - wr:0x%08x != "
349 "rd:0x%08x\n",
350 addr, wrData, rdData);
f1dc5600
S		 351 return false;
352 }
f078f209 353 }
f1dc5600 354 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 355 }
f1dc5600 356 udelay(100);
cbe61d8a 357
f078f209
LR		 358 return true;
359}
360
b8b0f377 361static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 362{
363 int i;
f078f209 364
2660b81a
S		 365 ah->config.dma_beacon_response_time = 2;
366 ah->config.sw_beacon_response_time = 10;
367 ah->config.additional_swba_backoff = 0;
368 ah->config.ack_6mb = 0x0;
369 ah->config.cwm_ignore_extcca = 0;
370 ah->config.pcie_powersave_enable = 0;
2660b81a 371 ah->config.pcie_clock_req = 0;
2660b81a
S		 372 ah->config.pcie_waen = 0;
373 ah->config.analog_shiftreg = 1;
2660b81a
S		 374 ah->config.ofdm_trig_low = 200;
375 ah->config.ofdm_trig_high = 500;
376 ah->config.cck_trig_high = 200;
377 ah->config.cck_trig_low = 100;
03c72518 378 ah->config.enable_ani = true;
f078f209 379
f1dc5600 380 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 381 ah->config.spurchans[i][0] = AR_NO_SPUR;
382 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 383 }
384
5ffaf8a3
LR		 385 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
386 ah->config.ht_enable = 1;
387 else
388 ah->config.ht_enable = 0;
389
0ce024cb 390 ah->config.rx_intr_mitigation = true;
6158425b
LR		 391
392 /*
393 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
394 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
395 * This means we use it for all AR5416 devices, and the few
396 * minor PCI AR9280 devices out there.
397 *
398 * Serialization is required because these devices do not handle
399 * well the case of two concurrent reads/writes due to the latency
400 * involved. During one read/write another read/write can be issued
401 * on another CPU while the previous read/write may still be working
402 * on our hardware, if we hit this case the hardware poops in a loop.
403 * We prevent this by serializing reads and writes.
404 *
405 * This issue is not present on PCI-Express devices or pre-AR5416
406 * devices (legacy, 802.11abg).
407 */
408 if (num_possible_cpus() > 1)
2d6a5e95 409 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 410}
411
50aca25b 412static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 413{
608b88cb
LR		 414 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
415
416 regulatory->country_code = CTRY_DEFAULT;
417 regulatory->power_limit = MAX_RATE_POWER;
418 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
419
d535a42a 420 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 421 ah->hw_version.subvendorid = 0;
f078f209
LR		 422
423 ah->ah_flags = 0;
f078f209
LR		 424 if (!AR_SREV_9100(ah))
425 ah->ah_flags = AH_USE_EEPROM;
426
2660b81a 427 ah->atim_window = 0;
2660b81a
S		 428 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
429 ah->beacon_interval = 100;
430 ah->enable_32kHz_clock = DONT_USE_32KHZ;
431 ah->slottime = (u32) -1;
2660b81a 432 ah->globaltxtimeout = (u32) -1;
cbdec975 433 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 434}
435
cbe61d8a 436static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 437{
1510718d 438 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 439 u32 sum;
440 int i;
441 u16 eeval;
49101676 442 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 443
444 sum = 0;
445 for (i = 0; i < 3; i++) {
49101676 446 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 447 sum += eeval;
1510718d
LR		 448 common->macaddr[2 * i] = eeval >> 8;
449 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 450 }
d8baa939 451 if (sum == 0 || sum == 0xffff * 3)
f078f209 452 return -EADDRNOTAVAIL;
f078f209
LR		 453
454 return 0;
455}
456
f637cfd6 457static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 458{
f1dc5600 459 int ecode;
f078f209 460
527d485f
S		 461 if (!AR_SREV_9271(ah)) {
462 if (!ath9k_hw_chip_test(ah))
463 return -ENODEV;
464 }
f078f209 465
ebd5a14a
LR		 466 if (!AR_SREV_9300_20_OR_LATER(ah)) {
467 ecode = ar9002_hw_rf_claim(ah);
468 if (ecode != 0)
469 return ecode;
470 }
f078f209 471
f637cfd6 472 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 473 if (ecode != 0)
474 return ecode;
7d01b221 475
c46917bb
LR		 476 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
477 "Eeprom VER: %d, REV: %d\n",
478 ah->eep_ops->get_eeprom_ver(ah),
479 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 480
8fe65368
LR		 481 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
482 if (ecode) {
483 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
484 "Failed allocating banks for "
485 "external radio\n");
486 return ecode;
574d6b12 487 }
f078f209 488
f1dc5600
S		 489 if (!AR_SREV_9100(ah)) {
490 ath9k_hw_ani_setup(ah);
f637cfd6 491 ath9k_hw_ani_init(ah);
f078f209
LR		 492 }
493
f078f209
LR		 494 return 0;
495}
496
8525f280 497static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 498{
8525f280
LR		 499 if (AR_SREV_9300_20_OR_LATER(ah))
500 ar9003_hw_attach_ops(ah);
501 else
502 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 503}
504
d70357d5
LR		 505/* Called for all hardware families */
506static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 507{
c46917bb 508 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 509 int r = 0;
aa4058ae 510
bab1f62e
LR		 511 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
512 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
aa4058ae
LR		 513
514 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 515 ath_print(common, ATH_DBG_FATAL,
516 "Couldn't reset chip\n");
95fafca2 517 return -EIO;
aa4058ae
LR		 518 }
519
bab1f62e
LR		 520 ath9k_hw_init_defaults(ah);
521 ath9k_hw_init_config(ah);
522
8525f280 523 ath9k_hw_attach_ops(ah);
d70357d5 524
9ecdef4b 525 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 526 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 527 return -EIO;
aa4058ae
LR		 528 }
529
530 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
531 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
532 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
533 ah->config.serialize_regmode =
534 SER_REG_MODE_ON;
535 } else {
536 ah->config.serialize_regmode =
537 SER_REG_MODE_OFF;
538 }
539 }
540
c46917bb 541 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 542 ah->config.serialize_regmode);
543
f4709fdf
LR		 544 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
545 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
546 else
547 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
548
d70357d5 549 if (!ath9k_hw_macversion_supported(ah)) {
c46917bb
LR		 550 ath_print(common, ATH_DBG_FATAL,
551 "Mac Chip Rev 0x%02x.%x is not supported by "
552 "this driver\n", ah->hw_version.macVersion,
553 ah->hw_version.macRev);
95fafca2 554 return -EOPNOTSUPP;
aa4058ae
LR		 555 }
556
0df13da4 557 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
d7e7d229
LR		 558 ah->is_pciexpress = false;
559
aa4058ae 560 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 561 ath9k_hw_init_cal_settings(ah);
562
563 ah->ani_function = ATH9K_ANI_ALL;
31a0bd3c 564 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 565 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 566 if (!AR_SREV_9300_20_OR_LATER(ah))
567 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae
LR		 568
569 ath9k_hw_init_mode_regs(ah);
570
5efa3a6b
LR		 571 /*
572 * Configire PCIE after Ini init. SERDES values now come from ini file
573 * This enables PCIe low power mode.
574 */
575 if (AR_SREV_9300_20_OR_LATER(ah)) {
576 u32 regval;
577 unsigned int i;
578
579 /* Set Bits 16 and 17 in the AR_WA register. */
580 regval = REG_READ(ah, AR_WA);
581 regval |= 0x00030000;
582 REG_WRITE(ah, AR_WA, regval);
583
584 for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
585 REG_WRITE(ah,
586 INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
587 INI_RA(&ah->iniPcieSerdesLowPower, i, 1));
588 }
589 }
590
aa4058ae 591 if (ah->is_pciexpress)
93b1b37f 592 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 593 else
594 ath9k_hw_disablepcie(ah);
595
d8f492b7
LR		 596 if (!AR_SREV_9300_20_OR_LATER(ah))
597 ar9002_hw_cck_chan14_spread(ah);
193cd458 598
f637cfd6 599 r = ath9k_hw_post_init(ah);
aa4058ae 600 if (r)
95fafca2 601 return r;
aa4058ae
LR		 602
603 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 604 r = ath9k_hw_fill_cap_info(ah);
605 if (r)
606 return r;
607
4f3acf81
LR		 608 r = ath9k_hw_init_macaddr(ah);
609 if (r) {
c46917bb
LR		 610 ath_print(common, ATH_DBG_FATAL,
611 "Failed to initialize MAC address\n");
95fafca2 612 return r;
f078f209
LR		 613 }
614
d7e7d229 615 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 616 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 617 else
2660b81a 618 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 619
641d9921
FF		 620 if (AR_SREV_9300_20_OR_LATER(ah))
621 ar9003_hw_set_nf_limits(ah);
622
f1dc5600 623 ath9k_init_nfcal_hist_buffer(ah);
aea702b7 624 ah->bb_watchdog_timeout_ms = 25;
f078f209 625
211f5859
LR		 626 common->state = ATH_HW_INITIALIZED;
627
4f3acf81 628 return 0;
f078f209
LR		 629}
630
d70357d5 631int ath9k_hw_init(struct ath_hw *ah)
f078f209 632{
d70357d5
LR		 633 int ret;
634 struct ath_common *common = ath9k_hw_common(ah);
f078f209 635
d70357d5
LR		 636 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
637 switch (ah->hw_version.devid) {
638 case AR5416_DEVID_PCI:
639 case AR5416_DEVID_PCIE:
640 case AR5416_AR9100_DEVID:
641 case AR9160_DEVID_PCI:
642 case AR9280_DEVID_PCI:
643 case AR9280_DEVID_PCIE:
644 case AR9285_DEVID_PCIE:
db3cc53a
SB		 645 case AR9287_DEVID_PCI:
646 case AR9287_DEVID_PCIE:
d70357d5 647 case AR2427_DEVID_PCIE:
db3cc53a 648 case AR9300_DEVID_PCIE:
d70357d5
LR		 649 break;
650 default:
651 if (common->bus_ops->ath_bus_type == ATH_USB)
652 break;
653 ath_print(common, ATH_DBG_FATAL,
654 "Hardware device ID 0x%04x not supported\n",
655 ah->hw_version.devid);
656 return -EOPNOTSUPP;
657 }
f078f209 658
d70357d5
LR		 659 ret = __ath9k_hw_init(ah);
660 if (ret) {
661 ath_print(common, ATH_DBG_FATAL,
662 "Unable to initialize hardware; "
663 "initialization status: %d\n", ret);
664 return ret;
665 }
f078f209 666
d70357d5 667 return 0;
f078f209 668}
d70357d5 669EXPORT_SYMBOL(ath9k_hw_init);
f078f209 670
cbe61d8a 671static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 672{
7d0d0df0
S		 673 ENABLE_REGWRITE_BUFFER(ah);
674
f1dc5600
S		 675 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
676 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 677
f1dc5600
S		 678 REG_WRITE(ah, AR_QOS_NO_ACK,
679 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
680 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
681 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
682
683 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
684 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
685 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
686 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
687 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 688
689 REGWRITE_BUFFER_FLUSH(ah);
690 DISABLE_REGWRITE_BUFFER(ah);
f078f209
LR		 691}
692
cbe61d8a 693static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 694 struct ath9k_channel *chan)
f078f209 695{
64773964 696 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 697
d03a66c1 698 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 699
c75724d1
LR		 700 /* Switch the core clock for ar9271 to 117Mhz */
701 if (AR_SREV_9271(ah)) {
25e2ab17
S		 702 udelay(500);
703 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 704 }
705
f1dc5600
S		 706 udelay(RTC_PLL_SETTLE_DELAY);
707
708 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 709}
710
cbe61d8a 711static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 712 enum nl80211_iftype opmode)
f078f209 713{
152d530d 714 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 715 AR_IMR_TXURN |
716 AR_IMR_RXERR |
717 AR_IMR_RXORN |
718 AR_IMR_BCNMISC;
f078f209 719
66860240
VT		 720 if (AR_SREV_9300_20_OR_LATER(ah)) {
721 imr_reg |= AR_IMR_RXOK_HP;
722 if (ah->config.rx_intr_mitigation)
723 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
724 else
725 imr_reg |= AR_IMR_RXOK_LP;
f078f209 726
66860240
VT		 727 } else {
728 if (ah->config.rx_intr_mitigation)
729 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
730 else
731 imr_reg |= AR_IMR_RXOK;
732 }
f078f209 733
66860240
VT		 734 if (ah->config.tx_intr_mitigation)
735 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
736 else
737 imr_reg |= AR_IMR_TXOK;
f078f209 738
d97809db 739 if (opmode == NL80211_IFTYPE_AP)
152d530d 740 imr_reg |= AR_IMR_MIB;
f078f209 741
7d0d0df0
S		 742 ENABLE_REGWRITE_BUFFER(ah);
743
152d530d 744 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 745 ah->imrs2_reg |= AR_IMR_S2_GTT;
746 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 747
f1dc5600
S		 748 if (!AR_SREV_9100(ah)) {
749 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
750 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
751 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
752 }
66860240 753
7d0d0df0
S		 754 REGWRITE_BUFFER_FLUSH(ah);
755 DISABLE_REGWRITE_BUFFER(ah);
756
66860240
VT		 757 if (AR_SREV_9300_20_OR_LATER(ah)) {
758 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
759 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
760 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
761 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
762 }
f078f209
LR		 763}
764
0005baf4 765static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 766{
0005baf4
FF		 767 u32 val = ath9k_hw_mac_to_clks(ah, us);
768 val = min(val, (u32) 0xFFFF);
769 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 770}
771
0005baf4 772static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 773{
0005baf4
FF		 774 u32 val = ath9k_hw_mac_to_clks(ah, us);
775 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
776 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
777}
778
779static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
780{
781 u32 val = ath9k_hw_mac_to_clks(ah, us);
782 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
783 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 784}
f1dc5600 785
cbe61d8a 786static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 787{
f078f209 788 if (tu > 0xFFFF) {
c46917bb
LR		 789 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
790 "bad global tx timeout %u\n", tu);
2660b81a 791 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 792 return false;
793 } else {
794 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 795 ah->globaltxtimeout = tu;
f078f209
LR		 796 return true;
797 }
798}
799
0005baf4 800void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 801{
0005baf4
FF		 802 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
803 int acktimeout;
e239d859 804 int slottime;
0005baf4
FF		 805 int sifstime;
806
c46917bb
LR		 807 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
808 ah->misc_mode);
f078f209 809
2660b81a 810 if (ah->misc_mode != 0)
f1dc5600 811 REG_WRITE(ah, AR_PCU_MISC,
2660b81a 812 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
0005baf4
FF		 813
814 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
815 sifstime = 16;
816 else
817 sifstime = 10;
818
e239d859
FF		 819 /* As defined by IEEE 802.11-2007 17.3.8.6 */
820 slottime = ah->slottime + 3 * ah->coverage_class;
821 acktimeout = slottime + sifstime;
42c4568a
FF		 822
823 /*
824 * Workaround for early ACK timeouts, add an offset to match the
825 * initval's 64us ack timeout value.
826 * This was initially only meant to work around an issue with delayed
827 * BA frames in some implementations, but it has been found to fix ACK
828 * timeout issues in other cases as well.
829 */
830 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
831 acktimeout += 64 - sifstime - ah->slottime;
832
e239d859 833 ath9k_hw_setslottime(ah, slottime);
0005baf4
FF		 834 ath9k_hw_set_ack_timeout(ah, acktimeout);
835 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 836 if (ah->globaltxtimeout != (u32) -1)
837 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 838}
0005baf4 839EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 840
285f2dda 841void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 842{
211f5859
LR		 843 struct ath_common *common = ath9k_hw_common(ah);
844
736b3a27 845 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 846 goto free_hw;
847
9ecdef4b 848 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 849
850free_hw:
8fe65368 851 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 852}
285f2dda 853EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 854
f1dc5600
S		 855/*******/
856/* INI */
857/*******/
858
8fe65368 859u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 860{
861 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
862
863 if (IS_CHAN_B(chan))
864 ctl |= CTL_11B;
865 else if (IS_CHAN_G(chan))
866 ctl |= CTL_11G;
867 else
868 ctl |= CTL_11A;
869
870 return ctl;
871}
872
f1dc5600
S		 873/****************************************/
874/* Reset and Channel Switching Routines */
875/****************************************/
f1dc5600 876
cbe61d8a 877static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 878{
57b32227 879 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 880 u32 regval;
881
7d0d0df0
S		 882 ENABLE_REGWRITE_BUFFER(ah);
883
d7e7d229
LR		 884 /*
885 * set AHB_MODE not to do cacheline prefetches
886 */
57b32227
FF		 887 if (!AR_SREV_9300_20_OR_LATER(ah)) {
888 regval = REG_READ(ah, AR_AHB_MODE);
889 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
890 }
f1dc5600 891
d7e7d229
LR		 892 /*
893 * let mac dma reads be in 128 byte chunks
894 */
f1dc5600
S		 895 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
896 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
897
7d0d0df0
S		 898 REGWRITE_BUFFER_FLUSH(ah);
899 DISABLE_REGWRITE_BUFFER(ah);
900
d7e7d229
LR		 901 /*
902 * Restore TX Trigger Level to its pre-reset value.
903 * The initial value depends on whether aggregation is enabled, and is
904 * adjusted whenever underruns are detected.
905 */
57b32227
FF		 906 if (!AR_SREV_9300_20_OR_LATER(ah))
907 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 908
7d0d0df0 909 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 910
d7e7d229
LR		 911 /*
912 * let mac dma writes be in 128 byte chunks
913 */
f1dc5600
S		 914 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
915 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
916
d7e7d229
LR		 917 /*
918 * Setup receive FIFO threshold to hold off TX activities
919 */
f1dc5600
S		 920 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
921
57b32227
FF		 922 if (AR_SREV_9300_20_OR_LATER(ah)) {
923 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
924 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
925
926 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
927 ah->caps.rx_status_len);
928 }
929
d7e7d229
LR		 930 /*
931 * reduce the number of usable entries in PCU TXBUF to avoid
932 * wrap around issues.
933 */
f1dc5600 934 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 935 /* For AR9285 the number of Fifos are reduced to half.
936 * So set the usable tx buf size also to half to
937 * avoid data/delimiter underruns
938 */
f1dc5600
S		 939 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
940 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 941 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 942 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
943 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
944 }
744d4025 945
7d0d0df0
S		 946 REGWRITE_BUFFER_FLUSH(ah);
947 DISABLE_REGWRITE_BUFFER(ah);
948
744d4025
VT		 949 if (AR_SREV_9300_20_OR_LATER(ah))
950 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 951}
952
cbe61d8a 953static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 954{
955 u32 val;
956
957 val = REG_READ(ah, AR_STA_ID1);
958 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
959 switch (opmode) {
d97809db 960 case NL80211_IFTYPE_AP:
f1dc5600
S		 961 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
962 | AR_STA_ID1_KSRCH_MODE);
963 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 964 break;
d97809db 965 case NL80211_IFTYPE_ADHOC:
9cb5412b 966 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 967 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
968 | AR_STA_ID1_KSRCH_MODE);
969 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 970 break;
d97809db
CM		 971 case NL80211_IFTYPE_STATION:
972 case NL80211_IFTYPE_MONITOR:
f1dc5600 973 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 974 break;
f1dc5600
S		 975 }
976}
977
8fe65368
LR		 978void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
979 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 980{
981 u32 coef_exp, coef_man;
982
983 for (coef_exp = 31; coef_exp > 0; coef_exp--)
984 if ((coef_scaled >> coef_exp) & 0x1)
985 break;
986
987 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
988
989 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
990
991 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
992 *coef_exponent = coef_exp - 16;
993}
994
cbe61d8a 995static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 996{
997 u32 rst_flags;
998 u32 tmpReg;
999
70768496
S		 1000 if (AR_SREV_9100(ah)) {
1001 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1002 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1003 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1004 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1005 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1006 }
1007
7d0d0df0
S		 1008 ENABLE_REGWRITE_BUFFER(ah);
1009
f1dc5600
S		 1010 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1011 AR_RTC_FORCE_WAKE_ON_INT);
1012
1013 if (AR_SREV_9100(ah)) {
1014 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1015 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1016 } else {
1017 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1018 if (tmpReg &
1019 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1020 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1021 u32 val;
f1dc5600 1022 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1023
1024 val = AR_RC_HOSTIF;
1025 if (!AR_SREV_9300_20_OR_LATER(ah))
1026 val |= AR_RC_AHB;
1027 REG_WRITE(ah, AR_RC, val);
1028
1029 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1030 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1031
1032 rst_flags = AR_RTC_RC_MAC_WARM;
1033 if (type == ATH9K_RESET_COLD)
1034 rst_flags |= AR_RTC_RC_MAC_COLD;
1035 }
1036
d03a66c1 1037 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1038
1039 REGWRITE_BUFFER_FLUSH(ah);
1040 DISABLE_REGWRITE_BUFFER(ah);
1041
f1dc5600
S		 1042 udelay(50);
1043
d03a66c1 1044 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1045 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1046 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1047 "RTC stuck in MAC reset\n");
f1dc5600
S		 1048 return false;
1049 }
1050
1051 if (!AR_SREV_9100(ah))
1052 REG_WRITE(ah, AR_RC, 0);
1053
f1dc5600
S		 1054 if (AR_SREV_9100(ah))
1055 udelay(50);
1056
1057 return true;
1058}
1059
cbe61d8a 1060static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1061{
7d0d0df0
S		 1062 ENABLE_REGWRITE_BUFFER(ah);
1063
f1dc5600
S		 1064 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1065 AR_RTC_FORCE_WAKE_ON_INT);
1066
42d5bc3f 1067 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1068 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1069
d03a66c1 1070 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1071
7d0d0df0
S		 1072 REGWRITE_BUFFER_FLUSH(ah);
1073 DISABLE_REGWRITE_BUFFER(ah);
1074
84e2169b
SB		 1075 if (!AR_SREV_9300_20_OR_LATER(ah))
1076 udelay(2);
1077
1078 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1079 REG_WRITE(ah, AR_RC, 0);
1080
d03a66c1 1081 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1082
1083 if (!ath9k_hw_wait(ah,
1084 AR_RTC_STATUS,
1085 AR_RTC_STATUS_M,
0caa7b14
S		 1086 AR_RTC_STATUS_ON,
1087 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1088 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1089 "RTC not waking up\n");
f1dc5600 1090 return false;
f078f209
LR		 1091 }
1092
f1dc5600
S		 1093 ath9k_hw_read_revisions(ah);
1094
1095 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1096}
1097
cbe61d8a 1098static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1099{
1100 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1101 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1102
1103 switch (type) {
1104 case ATH9K_RESET_POWER_ON:
1105 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1106 case ATH9K_RESET_WARM:
1107 case ATH9K_RESET_COLD:
1108 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1109 default:
1110 return false;
1111 }
f078f209
LR		 1112}
1113
cbe61d8a 1114static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1115 struct ath9k_channel *chan)
f078f209 1116{
42abfbee 1117 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1118 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1119 return false;
1120 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1121 return false;
f078f209 1122
9ecdef4b 1123 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1124 return false;
f078f209 1125
2660b81a 1126 ah->chip_fullsleep = false;
f1dc5600 1127 ath9k_hw_init_pll(ah, chan);
f1dc5600 1128 ath9k_hw_set_rfmode(ah, chan);
f078f209 1129
f1dc5600 1130 return true;
f078f209
LR		 1131}
1132
cbe61d8a 1133static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1134 struct ath9k_channel *chan)
f078f209 1135{
608b88cb 1136 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1137 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1138 struct ieee80211_channel *channel = chan->chan;
8fe65368 1139 u32 qnum;
0a3b7bac 1140 int r;
f078f209
LR		 1141
1142 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1143 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1144 ath_print(common, ATH_DBG_QUEUE,
1145 "Transmit frames pending on "
1146 "queue %d\n", qnum);
f078f209
LR		 1147 return false;
1148 }
1149 }
1150
8fe65368 1151 if (!ath9k_hw_rfbus_req(ah)) {
c46917bb
LR		 1152 ath_print(common, ATH_DBG_FATAL,
1153 "Could not kill baseband RX\n");
f078f209
LR		 1154 return false;
1155 }
1156
8fe65368 1157 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1158
8fe65368 1159 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1160 if (r) {
1161 ath_print(common, ATH_DBG_FATAL,
1162 "Failed to set channel\n");
1163 return false;
f078f209
LR		 1164 }
1165
8fbff4b8 1166 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1167 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1168 channel->max_antenna_gain * 2,
1169 channel->max_power * 2,
1170 min((u32) MAX_RATE_POWER,
608b88cb 1171 (u32) regulatory->power_limit));
f078f209 1172
8fe65368 1173 ath9k_hw_rfbus_done(ah);
f078f209 1174
f1dc5600
S		 1175 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1176 ath9k_hw_set_delta_slope(ah, chan);
1177
8fe65368 1178 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600
S		 1179
1180 if (!chan->oneTimeCalsDone)
1181 chan->oneTimeCalsDone = true;
1182
1183 return true;
1184}
1185
c9c99e5e 1186bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1187{
c9c99e5e
FF		 1188 int count = 50;
1189 u32 reg;
1190
1191 if (AR_SREV_9285_10_OR_LATER(ah))
1192 return true;
1193
1194 do {
1195 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1196
c9c99e5e
FF		 1197 if ((reg & 0x7E7FFFEF) == 0x00702400)
1198 continue;
1199
1200 switch (reg & 0x7E000B00) {
1201 case 0x1E000000:
1202 case 0x52000B00:
1203 case 0x18000B00:
1204 continue;
1205 default:
1206 return true;
1207 }
1208 } while (count-- > 0);
3b319aae 1209
c9c99e5e 1210 return false;
3b319aae 1211}
c9c99e5e 1212EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1213
cbe61d8a 1214int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 1215 bool bChannelChange)
f078f209 1216{
1510718d 1217 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1218 u32 saveLedState;
2660b81a 1219 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1220 u32 saveDefAntenna;
1221 u32 macStaId1;
46fe782c 1222 u64 tsf = 0;
8fe65368 1223 int i, r;
f078f209 1224
43c27613
LR		 1225 ah->txchainmask = common->tx_chainmask;
1226 ah->rxchainmask = common->rx_chainmask;
f078f209 1227
9b9cc61c
VT		 1228 if (!ah->chip_fullsleep) {
1229 ath9k_hw_abortpcurecv(ah);
1230 if (!ath9k_hw_stopdmarecv(ah))
1231 ath_print(common, ATH_DBG_XMIT,
1232 "Failed to stop receive dma\n");
1233 }
1234
9ecdef4b 1235 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1236 return -EIO;
f078f209 1237
9ebef799 1238 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1239 ath9k_hw_getnf(ah, curchan);
1240
1241 if (bChannelChange &&
2660b81a
S		 1242 (ah->chip_fullsleep != true) &&
1243 (ah->curchan != NULL) &&
1244 (chan->channel != ah->curchan->channel) &&
f078f209 1245 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1246 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
6b42e8d0 1247 !AR_SREV_9280(ah)) {
f078f209 1248
25c56eec 1249 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1250 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 1251 ath9k_hw_start_nfcal(ah);
ae8d2858 1252 return 0;
f078f209
LR		 1253 }
1254 }
1255
1256 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1257 if (saveDefAntenna == 0)
1258 saveDefAntenna = 1;
1259
1260 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1261
46fe782c
S		 1262 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1263 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1264 tsf = ath9k_hw_gettsf64(ah);
1265
f078f209
LR		 1266 saveLedState = REG_READ(ah, AR_CFG_LED) &
1267 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1268 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1269
1270 ath9k_hw_mark_phy_inactive(ah);
1271
05020d23 1272 /* Only required on the first reset */
d7e7d229
LR		 1273 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1274 REG_WRITE(ah,
1275 AR9271_RESET_POWER_DOWN_CONTROL,
1276 AR9271_RADIO_RF_RST);
1277 udelay(50);
1278 }
1279
f078f209 1280 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1281 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1282 return -EINVAL;
f078f209
LR		 1283 }
1284
05020d23 1285 /* Only required on the first reset */
d7e7d229
LR		 1286 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1287 ah->htc_reset_init = false;
1288 REG_WRITE(ah,
1289 AR9271_RESET_POWER_DOWN_CONTROL,
1290 AR9271_GATE_MAC_CTL);
1291 udelay(50);
1292 }
1293
46fe782c
S		 1294 /* Restore TSF */
1295 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1296 ath9k_hw_settsf64(ah, tsf);
1297
369391db
VT		 1298 if (AR_SREV_9280_10_OR_LATER(ah))
1299 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1300
e9141f71
S		 1301 if (!AR_SREV_9300_20_OR_LATER(ah))
1302 ar9002_hw_enable_async_fifo(ah);
1303
25c56eec 1304 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1305 if (r)
1306 return r;
f078f209 1307
0ced0e17
JM		 1308 /* Setup MFP options for CCMP */
1309 if (AR_SREV_9280_20_OR_LATER(ah)) {
1310 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1311 * frames when constructing CCMP AAD. */
1312 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1313 0xc7ff);
1314 ah->sw_mgmt_crypto = false;
1315 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1316 /* Disable hardware crypto for management frames */
1317 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1318 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1319 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1320 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1321 ah->sw_mgmt_crypto = true;
1322 } else
1323 ah->sw_mgmt_crypto = true;
1324
f078f209
LR		 1325 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1326 ath9k_hw_set_delta_slope(ah, chan);
1327
8fe65368 1328 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1329 ah->eep_ops->set_board_values(ah, chan);
a7765828 1330
6819d57f
S		 1331 ath9k_hw_set_operating_mode(ah, ah->opmode);
1332
7d0d0df0
S		 1333 ENABLE_REGWRITE_BUFFER(ah);
1334
1510718d
LR		 1335 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1336 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1337 | macStaId1
1338 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1339 | (ah->config.
60b67f51 1340 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1341 | ah->sta_id1_defaults);
13b81559 1342 ath_hw_setbssidmask(common);
f078f209 1343 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1344 ath9k_hw_write_associd(ah);
f078f209 1345 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1346 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1347
7d0d0df0
S		 1348 REGWRITE_BUFFER_FLUSH(ah);
1349 DISABLE_REGWRITE_BUFFER(ah);
1350
8fe65368 1351 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1352 if (r)
1353 return r;
f078f209 1354
7d0d0df0
S		 1355 ENABLE_REGWRITE_BUFFER(ah);
1356
f078f209
LR		 1357 for (i = 0; i < AR_NUM_DCU; i++)
1358 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1359
7d0d0df0
S		 1360 REGWRITE_BUFFER_FLUSH(ah);
1361 DISABLE_REGWRITE_BUFFER(ah);
1362
2660b81a
S		 1363 ah->intr_txqs = 0;
1364 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 1365 ath9k_hw_resettxqueue(ah, i);
1366
2660b81a 1367 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1368 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1369 ath9k_hw_init_qos(ah);
1370
2660b81a 1371 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 1372 ath9k_enable_rfkill(ah);
3b319aae 1373
0005baf4 1374 ath9k_hw_init_global_settings(ah);
f078f209 1375
6c94fdc9 1376 if (!AR_SREV_9300_20_OR_LATER(ah)) {
e9141f71 1377 ar9002_hw_update_async_fifo(ah);
6c94fdc9 1378 ar9002_hw_enable_wep_aggregation(ah);
ac88b6ec
VN		 1379 }
1380
f078f209
LR		 1381 REG_WRITE(ah, AR_STA_ID1,
1382 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1383
1384 ath9k_hw_set_dma(ah);
1385
1386 REG_WRITE(ah, AR_OBS, 8);
1387
0ce024cb 1388 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1389 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1390 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1391 }
1392
7f62a136
VT		 1393 if (ah->config.tx_intr_mitigation) {
1394 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1395 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1396 }
1397
f078f209
LR		 1398 ath9k_hw_init_bb(ah, chan);
1399
ae8d2858 1400 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1401 return -EIO;
f078f209 1402
7d0d0df0 1403 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1404
8fe65368 1405 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1406 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1407
7d0d0df0
S		 1408 REGWRITE_BUFFER_FLUSH(ah);
1409 DISABLE_REGWRITE_BUFFER(ah);
1410
d7e7d229
LR		 1411 /*
1412 * For big endian systems turn on swapping for descriptors
1413 */
f078f209
LR		 1414 if (AR_SREV_9100(ah)) {
1415 u32 mask;
1416 mask = REG_READ(ah, AR_CFG);
1417 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 1418 ath_print(common, ATH_DBG_RESET,
04bd4638 1419 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1420 } else {
1421 mask =
1422 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1423 REG_WRITE(ah, AR_CFG, mask);
c46917bb 1424 ath_print(common, ATH_DBG_RESET,
04bd4638 1425 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1426 }
1427 } else {
cbba8cd1
S		 1428 if (common->bus_ops->ath_bus_type == ATH_USB) {
1429 /* Configure AR9271 target WLAN */
1430 if (AR_SREV_9271(ah))
1431 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1432 else
1433 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1434 }
f078f209 1435#ifdef __BIG_ENDIAN
d7e7d229
LR		 1436 else
1437 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1438#endif
1439 }
1440
766ec4a9 1441 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1442 ath9k_hw_btcoex_enable(ah);
1443
d8903a53
VT		 1444 if (AR_SREV_9300_20_OR_LATER(ah)) {
1445 ath9k_hw_loadnf(ah, curchan);
1446 ath9k_hw_start_nfcal(ah);
aea702b7 1447 ar9003_hw_bb_watchdog_config(ah);
d8903a53
VT		 1448 }
1449
ae8d2858 1450 return 0;
f078f209 1451}
7322fd19 1452EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1453
f1dc5600
S		 1454/************************/
1455/* Key Cache Management */
1456/************************/
f078f209 1457
cbe61d8a 1458bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 1459{
f1dc5600 1460 u32 keyType;
f078f209 1461
2660b81a 1462 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1463 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1464 "keychache entry %u out of range\n", entry);
f078f209
LR		 1465 return false;
1466 }
1467
f1dc5600 1468 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 1469
f1dc5600
S		 1470 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1471 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1472 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1473 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1474 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1475 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1476 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1477 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 1478
f1dc5600
S		 1479 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1480 u16 micentry = entry + 64;
f078f209 1481
f1dc5600
S		 1482 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1483 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1484 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1485 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 1486
f078f209
LR		 1487 }
1488
f078f209
LR		 1489 return true;
1490}
7322fd19 1491EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 1492
cbe61d8a 1493bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 1494{
f1dc5600 1495 u32 macHi, macLo;
1d0bb42d 1496 u32 unicast_flag = AR_KEYTABLE_VALID;
f078f209 1497
2660b81a 1498 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1499 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1500 "keychache entry %u out of range\n", entry);
f1dc5600 1501 return false;
f078f209
LR		 1502 }
1503
f1dc5600 1504 if (mac != NULL) {
1d0bb42d
FF		 1505 /*
1506 * AR_KEYTABLE_VALID indicates that the address is a unicast
1507 * address, which must match the transmitter address for
1508 * decrypting frames.
1509 * Not setting this bit allows the hardware to use the key
1510 * for multicast frame decryption.
1511 */
1512 if (mac[0] & 0x01)
1513 unicast_flag = 0;
1514
f1dc5600
S		 1515 macHi = (mac[5] << 8) | mac[4];
1516 macLo = (mac[3] << 24) |
1517 (mac[2] << 16) |
1518 (mac[1] << 8) |
1519 mac[0];
1520 macLo >>= 1;
1521 macLo |= (macHi & 1) << 31;
1522 macHi >>= 1;
f078f209 1523 } else {
f1dc5600 1524 macLo = macHi = 0;
f078f209 1525 }
f1dc5600 1526 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1d0bb42d 1527 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
f078f209 1528
f1dc5600 1529 return true;
f078f209 1530}
7322fd19 1531EXPORT_SYMBOL(ath9k_hw_keysetmac);
f078f209 1532
cbe61d8a 1533bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 1534 const struct ath9k_keyval *k,
e0caf9ea 1535 const u8 *mac)
f078f209 1536{
2660b81a 1537 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1538 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 1539 u32 key0, key1, key2, key3, key4;
1540 u32 keyType;
f078f209 1541
f1dc5600 1542 if (entry >= pCap->keycache_size) {
c46917bb
LR		 1543 ath_print(common, ATH_DBG_FATAL,
1544 "keycache entry %u out of range\n", entry);
f1dc5600 1545 return false;
f078f209
LR		 1546 }
1547
f1dc5600
S		 1548 switch (k->kv_type) {
1549 case ATH9K_CIPHER_AES_OCB:
1550 keyType = AR_KEYTABLE_TYPE_AES;
1551 break;
1552 case ATH9K_CIPHER_AES_CCM:
1553 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 1554 ath_print(common, ATH_DBG_ANY,
1555 "AES-CCM not supported by mac rev 0x%x\n",
1556 ah->hw_version.macRev);
f1dc5600
S		 1557 return false;
1558 }
1559 keyType = AR_KEYTABLE_TYPE_CCM;
1560 break;
1561 case ATH9K_CIPHER_TKIP:
1562 keyType = AR_KEYTABLE_TYPE_TKIP;
1563 if (ATH9K_IS_MIC_ENABLED(ah)
1564 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 1565 ath_print(common, ATH_DBG_ANY,
1566 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 1567 return false;
1568 }
1569 break;
1570 case ATH9K_CIPHER_WEP:
e31a16d6 1571 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 1572 ath_print(common, ATH_DBG_ANY,
1573 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 1574 return false;
1575 }
e31a16d6 1576 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 1577 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 1578 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 1579 keyType = AR_KEYTABLE_TYPE_104;
1580 else
1581 keyType = AR_KEYTABLE_TYPE_128;
1582 break;
1583 case ATH9K_CIPHER_CLR:
1584 keyType = AR_KEYTABLE_TYPE_CLR;
1585 break;
1586 default:
c46917bb
LR		 1587 ath_print(common, ATH_DBG_FATAL,
1588 "cipher %u not supported\n", k->kv_type);
f1dc5600 1589 return false;
f078f209
LR		 1590 }
1591
e0caf9ea
JM		 1592 key0 = get_unaligned_le32(k->kv_val + 0);
1593 key1 = get_unaligned_le16(k->kv_val + 4);
1594 key2 = get_unaligned_le32(k->kv_val + 6);
1595 key3 = get_unaligned_le16(k->kv_val + 10);
1596 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 1597 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 1598 key4 &= 0xff;
f078f209 1599
672903b3
JM		 1600 /*
1601 * Note: Key cache registers access special memory area that requires
1602 * two 32-bit writes to actually update the values in the internal
1603 * memory. Consequently, the exact order and pairs used here must be
1604 * maintained.
1605 */
1606
f1dc5600
S		 1607 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1608 u16 micentry = entry + 64;
f078f209 1609
672903b3
JM		 1610 /*
1611 * Write inverted key[47:0] first to avoid Michael MIC errors
1612 * on frames that could be sent or received at the same time.
1613 * The correct key will be written in the end once everything
1614 * else is ready.
1615 */
f1dc5600
S		 1616 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1617 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 1618
1619 /* Write key[95:48] */
f1dc5600
S		 1620 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1621 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1622
1623 /* Write key[127:96] and key type */
f1dc5600
S		 1624 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1625 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 1626
1627 /* Write MAC address for the entry */
f1dc5600 1628 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 1629
2660b81a 1630 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 1631 /*
1632 * TKIP uses two key cache entries:
1633 * Michael MIC TX/RX keys in the same key cache entry
1634 * (idx = main index + 64):
1635 * key0 [31:0] = RX key [31:0]
1636 * key1 [15:0] = TX key [31:16]
1637 * key1 [31:16] = reserved
1638 * key2 [31:0] = RX key [63:32]
1639 * key3 [15:0] = TX key [15:0]
1640 * key3 [31:16] = reserved
1641 * key4 [31:0] = TX key [63:32]
1642 */
f1dc5600 1643 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 1644
f1dc5600
S		 1645 mic0 = get_unaligned_le32(k->kv_mic + 0);
1646 mic2 = get_unaligned_le32(k->kv_mic + 4);
1647 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1648 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1649 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 1650
1651 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 1652 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1653 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 1654
1655 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 1656 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1657 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 1658
1659 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1660 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1661 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1662 AR_KEYTABLE_TYPE_CLR);
f078f209 1663
f1dc5600 1664 } else {
672903b3
JM		 1665 /*
1666 * TKIP uses four key cache entries (two for group
1667 * keys):
1668 * Michael MIC TX/RX keys are in different key cache
1669 * entries (idx = main index + 64 for TX and
1670 * main index + 32 + 96 for RX):
1671 * key0 [31:0] = TX/RX MIC key [31:0]
1672 * key1 [31:0] = reserved
1673 * key2 [31:0] = TX/RX MIC key [63:32]
1674 * key3 [31:0] = reserved
1675 * key4 [31:0] = reserved
1676 *
1677 * Upper layer code will call this function separately
1678 * for TX and RX keys when these registers offsets are
1679 * used.
1680 */
f1dc5600 1681 u32 mic0, mic2;
f078f209 1682
f1dc5600
S		 1683 mic0 = get_unaligned_le32(k->kv_mic + 0);
1684 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 1685
1686 /* Write MIC key[31:0] */
f1dc5600
S		 1687 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1688 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 1689
1690 /* Write MIC key[63:32] */
f1dc5600
S		 1691 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1692 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 1693
1694 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1695 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1696 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1697 AR_KEYTABLE_TYPE_CLR);
1698 }
672903b3
JM		 1699
1700 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 1701 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1702 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 1703
1704 /*
1705 * Write the correct (un-inverted) key[47:0] last to enable
1706 * TKIP now that all other registers are set with correct
1707 * values.
1708 */
f1dc5600
S		 1709 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1710 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1711 } else {
672903b3 1712 /* Write key[47:0] */
f1dc5600
S		 1713 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1714 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 1715
1716 /* Write key[95:48] */
f1dc5600
S		 1717 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1718 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1719
1720 /* Write key[127:96] and key type */
f1dc5600
S		 1721 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1722 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 1723
672903b3 1724 /* Write MAC address for the entry */
f1dc5600
S		 1725 (void) ath9k_hw_keysetmac(ah, entry, mac);
1726 }
f078f209 1727
f078f209
LR		 1728 return true;
1729}
7322fd19 1730EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 1731
cbe61d8a 1732bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 1733{
2660b81a 1734 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 1735 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1736 if (val & AR_KEYTABLE_VALID)
1737 return true;
1738 }
1739 return false;
f078f209 1740}
7322fd19 1741EXPORT_SYMBOL(ath9k_hw_keyisvalid);
f078f209 1742
f1dc5600
S		 1743/******************************/
1744/* Power Management (Chipset) */
1745/******************************/
1746
42d5bc3f
LR		 1747/*
1748 * Notify Power Mgt is disabled in self-generated frames.
1749 * If requested, force chip to sleep.
1750 */
cbe61d8a 1751static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1752{
f1dc5600
S		 1753 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1754 if (setChip) {
42d5bc3f
LR		 1755 /*
1756 * Clear the RTC force wake bit to allow the
1757 * mac to go to sleep.
1758 */
f1dc5600
S		 1759 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1760 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1761 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1762 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1763
42d5bc3f 1764 /* Shutdown chip. Active low */
14b3af38 1765 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1766 REG_CLR_BIT(ah, (AR_RTC_RESET),
1767 AR_RTC_RESET_EN);
f1dc5600 1768 }
f078f209
LR		 1769}
1770
bbd79af5
LR		 1771/*
1772 * Notify Power Management is enabled in self-generating
1773 * frames. If request, set power mode of chip to
1774 * auto/normal. Duration in units of 128us (1/8 TU).
1775 */
cbe61d8a 1776static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1777{
f1dc5600
S		 1778 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1779 if (setChip) {
2660b81a 1780 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1781
f1dc5600 1782 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1783 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1784 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1785 AR_RTC_FORCE_WAKE_ON_INT);
1786 } else {
bbd79af5
LR		 1787 /*
1788 * Clear the RTC force wake bit to allow the
1789 * mac to go to sleep.
1790 */
f1dc5600
S		 1791 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1792 AR_RTC_FORCE_WAKE_EN);
f078f209 1793 }
f078f209 1794 }
f078f209
LR		 1795}
1796
cbe61d8a 1797static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1798{
f1dc5600
S		 1799 u32 val;
1800 int i;
f078f209 1801
f1dc5600
S		 1802 if (setChip) {
1803 if ((REG_READ(ah, AR_RTC_STATUS) &
1804 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1805 if (ath9k_hw_set_reset_reg(ah,
1806 ATH9K_RESET_POWER_ON) != true) {
1807 return false;
1808 }
e041228f
LR		 1809 if (!AR_SREV_9300_20_OR_LATER(ah))
1810 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1811 }
1812 if (AR_SREV_9100(ah))
1813 REG_SET_BIT(ah, AR_RTC_RESET,
1814 AR_RTC_RESET_EN);
f078f209 1815
f1dc5600
S		 1816 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1817 AR_RTC_FORCE_WAKE_EN);
1818 udelay(50);
f078f209 1819
f1dc5600
S		 1820 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1821 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1822 if (val == AR_RTC_STATUS_ON)
1823 break;
1824 udelay(50);
1825 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1826 AR_RTC_FORCE_WAKE_EN);
f078f209 1827 }
f1dc5600 1828 if (i == 0) {
c46917bb
LR		 1829 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1830 "Failed to wakeup in %uus\n",
1831 POWER_UP_TIME / 20);
f1dc5600 1832 return false;
f078f209 1833 }
f078f209
LR		 1834 }
1835
f1dc5600 1836 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1837
f1dc5600 1838 return true;
f078f209
LR		 1839}
1840
9ecdef4b 1841bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1842{
c46917bb 1843 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1844 int status = true, setChip = true;
f1dc5600
S		 1845 static const char *modes[] = {
1846 "AWAKE",
1847 "FULL-SLEEP",
1848 "NETWORK SLEEP",
1849 "UNDEFINED"
1850 };
f1dc5600 1851
cbdec975
GJ		 1852 if (ah->power_mode == mode)
1853 return status;
1854
c46917bb
LR		 1855 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1856 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1857
1858 switch (mode) {
1859 case ATH9K_PM_AWAKE:
1860 status = ath9k_hw_set_power_awake(ah, setChip);
1861 break;
1862 case ATH9K_PM_FULL_SLEEP:
1863 ath9k_set_power_sleep(ah, setChip);
2660b81a 1864 ah->chip_fullsleep = true;
f1dc5600
S		 1865 break;
1866 case ATH9K_PM_NETWORK_SLEEP:
1867 ath9k_set_power_network_sleep(ah, setChip);
1868 break;
f078f209 1869 default:
c46917bb
LR		 1870 ath_print(common, ATH_DBG_FATAL,
1871 "Unknown power mode %u\n", mode);
f078f209
LR		 1872 return false;
1873 }
2660b81a 1874 ah->power_mode = mode;
f1dc5600
S		 1875
1876 return status;
f078f209 1877}
7322fd19 1878EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1879
f1dc5600
S		 1880/*******************/
1881/* Beacon Handling */
1882/*******************/
1883
cbe61d8a 1884void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 1885{
f078f209
LR		 1886 int flags = 0;
1887
2660b81a 1888 ah->beacon_interval = beacon_period;
f078f209 1889
7d0d0df0
S		 1890 ENABLE_REGWRITE_BUFFER(ah);
1891
2660b81a 1892 switch (ah->opmode) {
d97809db
CM		 1893 case NL80211_IFTYPE_STATION:
1894 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 1895 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1896 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1897 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1898 flags |= AR_TBTT_TIMER_EN;
1899 break;
d97809db 1900 case NL80211_IFTYPE_ADHOC:
9cb5412b 1901 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 1902 REG_SET_BIT(ah, AR_TXCFG,
1903 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1904 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1905 TU_TO_USEC(next_beacon +
2660b81a
S		 1906 (ah->atim_window ? ah->
1907 atim_window : 1)));
f078f209 1908 flags |= AR_NDP_TIMER_EN;
d97809db 1909 case NL80211_IFTYPE_AP:
f078f209
LR		 1910 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1911 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1912 TU_TO_USEC(next_beacon -
2660b81a 1913 ah->config.
60b67f51 1914 dma_beacon_response_time));
f078f209
LR		 1915 REG_WRITE(ah, AR_NEXT_SWBA,
1916 TU_TO_USEC(next_beacon -
2660b81a 1917 ah->config.
60b67f51 1918 sw_beacon_response_time));
f078f209
LR		 1919 flags |=
1920 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1921 break;
d97809db 1922 default:
c46917bb
LR		 1923 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1924 "%s: unsupported opmode: %d\n",
1925 __func__, ah->opmode);
d97809db
CM		 1926 return;
1927 break;
f078f209
LR		 1928 }
1929
1930 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1931 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1932 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1933 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1934
7d0d0df0
S		 1935 REGWRITE_BUFFER_FLUSH(ah);
1936 DISABLE_REGWRITE_BUFFER(ah);
1937
f078f209
LR		 1938 beacon_period &= ~ATH9K_BEACON_ENA;
1939 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 1940 ath9k_hw_reset_tsf(ah);
1941 }
1942
1943 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1944}
7322fd19 1945EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 1946
cbe61d8a 1947void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 1948 const struct ath9k_beacon_state *bs)
f078f209
LR		 1949{
1950 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 1951 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1952 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1953
7d0d0df0
S		 1954 ENABLE_REGWRITE_BUFFER(ah);
1955
f078f209
LR		 1956 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1957
1958 REG_WRITE(ah, AR_BEACON_PERIOD,
1959 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1960 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1961 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1962
7d0d0df0
S		 1963 REGWRITE_BUFFER_FLUSH(ah);
1964 DISABLE_REGWRITE_BUFFER(ah);
1965
f078f209
LR		 1966 REG_RMW_FIELD(ah, AR_RSSI_THR,
1967 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1968
1969 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1970
1971 if (bs->bs_sleepduration > beaconintval)
1972 beaconintval = bs->bs_sleepduration;
1973
1974 dtimperiod = bs->bs_dtimperiod;
1975 if (bs->bs_sleepduration > dtimperiod)
1976 dtimperiod = bs->bs_sleepduration;
1977
1978 if (beaconintval == dtimperiod)
1979 nextTbtt = bs->bs_nextdtim;
1980 else
1981 nextTbtt = bs->bs_nexttbtt;
1982
c46917bb
LR		 1983 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1984 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1985 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1986 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 1987
7d0d0df0
S		 1988 ENABLE_REGWRITE_BUFFER(ah);
1989
f1dc5600
S		 1990 REG_WRITE(ah, AR_NEXT_DTIM,
1991 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1992 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 1993
f1dc5600
S		 1994 REG_WRITE(ah, AR_SLEEP1,
1995 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1996 | AR_SLEEP1_ASSUME_DTIM);
f078f209 1997
f1dc5600
S		 1998 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1999 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2000 else
2001 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2002
f1dc5600
S		 2003 REG_WRITE(ah, AR_SLEEP2,
2004 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2005
f1dc5600
S		 2006 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2007 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2008
7d0d0df0
S		 2009 REGWRITE_BUFFER_FLUSH(ah);
2010 DISABLE_REGWRITE_BUFFER(ah);
2011
f1dc5600
S		 2012 REG_SET_BIT(ah, AR_TIMER_MODE,
2013 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2014 AR_DTIM_TIMER_EN);
f078f209 2015
4af9cf4f
S		 2016 /* TSF Out of Range Threshold */
2017 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2018}
7322fd19 2019EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2020
f1dc5600
S		 2021/*******************/
2022/* HW Capabilities */
2023/*******************/
2024
a9a29ce6 2025int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2026{
2660b81a 2027 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2028 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2029 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 2030 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 2031
f1dc5600 2032 u16 capField = 0, eeval;
f078f209 2033
f74df6fb 2034 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2035 regulatory->current_rd = eeval;
f078f209 2036
f74df6fb 2037 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 2038 if (AR_SREV_9285_10_OR_LATER(ah))
2039 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 2040 regulatory->current_rd_ext = eeval;
f078f209 2041
f74df6fb 2042 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 2043
2660b81a 2044 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2045 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2046 if (regulatory->current_rd == 0x64 ||
2047 regulatory->current_rd == 0x65)
2048 regulatory->current_rd += 5;
2049 else if (regulatory->current_rd == 0x41)
2050 regulatory->current_rd = 0x43;
c46917bb
LR		 2051 ath_print(common, ATH_DBG_REGULATORY,
2052 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 2053 }
f078f209 2054
f74df6fb 2055 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6
GJ		 2056 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2057 ath_print(common, ATH_DBG_FATAL,
2058 "no band has been marked as supported in EEPROM.\n");
2059 return -EINVAL;
2060 }
2061
f1dc5600 2062 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 2063
f1dc5600
S		 2064 if (eeval & AR5416_OPFLAGS_11A) {
2065 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 2066 if (ah->config.ht_enable) {
f1dc5600
S		 2067 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2068 set_bit(ATH9K_MODE_11NA_HT20,
2069 pCap->wireless_modes);
2070 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2071 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2072 pCap->wireless_modes);
2073 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2074 pCap->wireless_modes);
2075 }
f078f209 2076 }
f078f209
LR		 2077 }
2078
f1dc5600 2079 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 2080 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 2081 if (ah->config.ht_enable) {
f1dc5600
S		 2082 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2083 set_bit(ATH9K_MODE_11NG_HT20,
2084 pCap->wireless_modes);
2085 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2086 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2087 pCap->wireless_modes);
2088 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2089 pCap->wireless_modes);
2090 }
2091 }
f078f209 2092 }
f1dc5600 2093
f74df6fb 2094 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2095 /*
2096 * For AR9271 we will temporarilly uses the rx chainmax as read from
2097 * the EEPROM.
2098 */
8147f5de 2099 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2100 !(eeval & AR5416_OPFLAGS_11A) &&
2101 !(AR_SREV_9271(ah)))
2102 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 2103 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2104 else
d7e7d229 2105 /* Use rx_chainmask from EEPROM. */
8147f5de 2106 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2107
d535a42a 2108 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 2109 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2110
f1dc5600
S		 2111 pCap->low_2ghz_chan = 2312;
2112 pCap->high_2ghz_chan = 2732;
f078f209 2113
f1dc5600
S		 2114 pCap->low_5ghz_chan = 4920;
2115 pCap->high_5ghz_chan = 6100;
f078f209 2116
f1dc5600
S		 2117 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2118 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2119 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 2120
f1dc5600
S		 2121 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2122 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2123 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 2124
2660b81a 2125 if (ah->config.ht_enable)
f1dc5600
S		 2126 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2127 else
2128 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2129
f1dc5600
S		 2130 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2131 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2132 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2133 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 2134
f1dc5600
S		 2135 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2136 pCap->total_queues =
2137 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2138 else
2139 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 2140
f1dc5600
S		 2141 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2142 pCap->keycache_size =
2143 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2144 else
2145 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 2146
f1dc5600 2147 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f4709fdf
LR		 2148
2149 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2150 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2151 else
2152 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 2153
5b5fa355
S		 2154 if (AR_SREV_9271(ah))
2155 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2156 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2157 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2158 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 2159 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2160 else
2161 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2162
f1dc5600
S		 2163 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2164 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2165 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2166 } else {
2167 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 2168 }
2169
f1dc5600
S		 2170 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2171
e97275cb 2172#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2173 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2174 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2175 ah->rfkill_gpio =
2176 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2177 ah->rfkill_polarity =
2178 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2179
2180 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2181 }
f1dc5600 2182#endif
d5d1154f 2183 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2184 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2185 else
2186 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2187
e7594072 2188 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2189 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2190 else
2191 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2192
608b88cb 2193 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 2194 pCap->reg_cap =
2195 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2196 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2197 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2198 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 2199 } else {
f1dc5600
S		 2200 pCap->reg_cap =
2201 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2202 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 2203 }
f078f209 2204
ebb90cfc
SB		 2205 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2206 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2207 AR_SREV_5416(ah))
2208 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 2209
2210 pCap->num_antcfg_5ghz =
f74df6fb 2211 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 2212 pCap->num_antcfg_2ghz =
f74df6fb 2213 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 2214
fe12946e 2215 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 2216 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 2217 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2218 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 2219
8c8f9ba7 2220 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 2221 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2222 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 2223 } else {
766ec4a9 2224 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 2225 }
22f25d0d 2226 } else {
766ec4a9 2227 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 2228 }
a9a29ce6 2229
ceb26445 2230 if (AR_SREV_9300_20_OR_LATER(ah)) {
e5553724
VT		 2231 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2232 ATH9K_HW_CAP_FASTCLOCK;
ceb26445
VT		 2233 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2234 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2235 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2236 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2237 pCap->txs_len = sizeof(struct ar9003_txs);
4935250a
FF		 2238 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2239 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 2240 } else {
2241 pCap->tx_desc_len = sizeof(struct ath_desc);
6b42e8d0
FF		 2242 if (AR_SREV_9280_20(ah) &&
2243 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2244 AR5416_EEP_MINOR_VER_16) ||
2245 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2246 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2247 }
1adf02ff 2248
6c84ce08
VT		 2249 if (AR_SREV_9300_20_OR_LATER(ah))
2250 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2251
b4dec5e8 2252 if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2253 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2254
a9a29ce6 2255 return 0;
f078f209
LR		 2256}
2257
cbe61d8a 2258bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2259 u32 capability, u32 *result)
f078f209 2260{
f1dc5600 2261 switch (type) {
f1dc5600
S		 2262 case ATH9K_CAP_MCAST_KEYSRCH:
2263 switch (capability) {
2264 case 0:
2265 return true;
2266 case 1:
2267 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2268 return false;
2269 } else {
2660b81a 2270 return (ah->sta_id1_defaults &
f1dc5600
S		 2271 AR_STA_ID1_MCAST_KSRCH) ? true :
2272 false;
2273 }
2274 }
2275 return false;
8bd1d07f
SB		 2276 case ATH9K_CAP_DS:
2277 return (AR_SREV_9280_20_OR_LATER(ah) &&
2278 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2279 ? false : true;
f1dc5600
S		 2280 default:
2281 return false;
f078f209 2282 }
f078f209 2283}
7322fd19 2284EXPORT_SYMBOL(ath9k_hw_getcapability);
f078f209 2285
cbe61d8a 2286bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2287 u32 capability, u32 setting, int *status)
f078f209 2288{
f1dc5600 2289 switch (type) {
f1dc5600
S		 2290 case ATH9K_CAP_MCAST_KEYSRCH:
2291 if (setting)
2660b81a 2292 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2293 else
2660b81a 2294 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2295 return true;
f1dc5600
S		 2296 default:
2297 return false;
f078f209
LR		 2298 }
2299}
7322fd19 2300EXPORT_SYMBOL(ath9k_hw_setcapability);
f078f209 2301
f1dc5600
S		 2302/****************************/
2303/* GPIO / RFKILL / Antennae */
2304/****************************/
f078f209 2305
cbe61d8a 2306static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2307 u32 gpio, u32 type)
2308{
2309 int addr;
2310 u32 gpio_shift, tmp;
f078f209 2311
f1dc5600
S		 2312 if (gpio > 11)
2313 addr = AR_GPIO_OUTPUT_MUX3;
2314 else if (gpio > 5)
2315 addr = AR_GPIO_OUTPUT_MUX2;
2316 else
2317 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2318
f1dc5600 2319 gpio_shift = (gpio % 6) * 5;
f078f209 2320
f1dc5600
S		 2321 if (AR_SREV_9280_20_OR_LATER(ah)
2322 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2323 REG_RMW(ah, addr, (type << gpio_shift),
2324 (0x1f << gpio_shift));
f078f209 2325 } else {
f1dc5600
S		 2326 tmp = REG_READ(ah, addr);
2327 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2328 tmp &= ~(0x1f << gpio_shift);
2329 tmp |= (type << gpio_shift);
2330 REG_WRITE(ah, addr, tmp);
f078f209 2331 }
f078f209
LR		 2332}
2333
cbe61d8a 2334void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2335{
f1dc5600 2336 u32 gpio_shift;
f078f209 2337
9680e8a3 2338 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2339
f1dc5600 2340 gpio_shift = gpio << 1;
f078f209 2341
f1dc5600
S		 2342 REG_RMW(ah,
2343 AR_GPIO_OE_OUT,
2344 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2345 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2346}
7322fd19 2347EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2348
cbe61d8a 2349u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2350{
cb33c412
SB		 2351#define MS_REG_READ(x, y) \
2352 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2353
2660b81a 2354 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2355 return 0xffffffff;
f078f209 2356
783dfca1
FF		 2357 if (AR_SREV_9300_20_OR_LATER(ah))
2358 return MS_REG_READ(AR9300, gpio) != 0;
2359 else if (AR_SREV_9271(ah))
5b5fa355
S		 2360 return MS_REG_READ(AR9271, gpio) != 0;
2361 else if (AR_SREV_9287_10_OR_LATER(ah))
ac88b6ec
VN		 2362 return MS_REG_READ(AR9287, gpio) != 0;
2363 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2364 return MS_REG_READ(AR9285, gpio) != 0;
2365 else if (AR_SREV_9280_10_OR_LATER(ah))
2366 return MS_REG_READ(AR928X, gpio) != 0;
2367 else
2368 return MS_REG_READ(AR, gpio) != 0;
f078f209 2369}
7322fd19 2370EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2371
cbe61d8a 2372void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2373 u32 ah_signal_type)
f078f209 2374{
f1dc5600 2375 u32 gpio_shift;
f078f209 2376
f1dc5600 2377 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 2378
f1dc5600 2379 gpio_shift = 2 * gpio;
f078f209 2380
f1dc5600
S		 2381 REG_RMW(ah,
2382 AR_GPIO_OE_OUT,
2383 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2384 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2385}
7322fd19 2386EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2387
cbe61d8a 2388void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2389{
5b5fa355
S		 2390 if (AR_SREV_9271(ah))
2391 val = ~val;
2392
f1dc5600
S		 2393 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2394 AR_GPIO_BIT(gpio));
f078f209 2395}
7322fd19 2396EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2397
cbe61d8a 2398u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2399{
f1dc5600 2400 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2401}
7322fd19 2402EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2403
cbe61d8a 2404void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2405{
f1dc5600 2406 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2407}
7322fd19 2408EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2409
f1dc5600
S		 2410/*********************/
2411/* General Operation */
2412/*********************/
2413
cbe61d8a 2414u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2415{
f1dc5600
S		 2416 u32 bits = REG_READ(ah, AR_RX_FILTER);
2417 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2418
f1dc5600
S		 2419 if (phybits & AR_PHY_ERR_RADAR)
2420 bits |= ATH9K_RX_FILTER_PHYRADAR;
2421 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2422 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2423
f1dc5600 2424 return bits;
f078f209 2425}
7322fd19 2426EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2427
cbe61d8a 2428void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2429{
f1dc5600 2430 u32 phybits;
f078f209 2431
7d0d0df0
S		 2432 ENABLE_REGWRITE_BUFFER(ah);
2433
7ea310be
S		 2434 REG_WRITE(ah, AR_RX_FILTER, bits);
2435
f1dc5600
S		 2436 phybits = 0;
2437 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2438 phybits |= AR_PHY_ERR_RADAR;
2439 if (bits & ATH9K_RX_FILTER_PHYERR)
2440 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2441 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2442
f1dc5600
S		 2443 if (phybits)
2444 REG_WRITE(ah, AR_RXCFG,
2445 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2446 else
2447 REG_WRITE(ah, AR_RXCFG,
2448 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2449
2450 REGWRITE_BUFFER_FLUSH(ah);
2451 DISABLE_REGWRITE_BUFFER(ah);
f1dc5600 2452}
7322fd19 2453EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2454
cbe61d8a 2455bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2456{
63a75b91
SB		 2457 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2458 return false;
2459
2460 ath9k_hw_init_pll(ah, NULL);
2461 return true;
f1dc5600 2462}
7322fd19 2463EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2464
cbe61d8a 2465bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2466{
9ecdef4b 2467 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2468 return false;
f078f209 2469
63a75b91
SB		 2470 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2471 return false;
2472
2473 ath9k_hw_init_pll(ah, NULL);
2474 return true;
f078f209 2475}
7322fd19 2476EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2477
8fbff4b8 2478void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 2479{
608b88cb 2480 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2481 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2482 struct ieee80211_channel *channel = chan->chan;
f078f209 2483
608b88cb 2484 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2485
8fbff4b8 2486 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2487 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2488 channel->max_antenna_gain * 2,
2489 channel->max_power * 2,
2490 min((u32) MAX_RATE_POWER,
608b88cb 2491 (u32) regulatory->power_limit));
6f255425 2492}
7322fd19 2493EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2494
cbe61d8a 2495void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2496{
2660b81a 2497 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2498}
7322fd19 2499EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2500
cbe61d8a 2501void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2502{
f1dc5600
S		 2503 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2504 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2505}
7322fd19 2506EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2507
f2b2143e 2508void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2509{
1510718d
LR		 2510 struct ath_common *common = ath9k_hw_common(ah);
2511
2512 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2513 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2514 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2515}
7322fd19 2516EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2517
1c0fc65e
BP		 2518#define ATH9K_MAX_TSF_READ 10
2519
cbe61d8a 2520u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2521{
1c0fc65e
BP		 2522 u32 tsf_lower, tsf_upper1, tsf_upper2;
2523 int i;
2524
2525 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2526 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2527 tsf_lower = REG_READ(ah, AR_TSF_L32);
2528 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2529 if (tsf_upper2 == tsf_upper1)
2530 break;
2531 tsf_upper1 = tsf_upper2;
2532 }
f078f209 2533
1c0fc65e 2534 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2535
1c0fc65e 2536 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2537}
7322fd19 2538EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2539
cbe61d8a 2540void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2541{
27abe060 2542 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2543 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2544}
7322fd19 2545EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2546
cbe61d8a 2547void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2548{
f9b604f6
GJ		 2549 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2550 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 2551 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2552 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2553
f1dc5600
S		 2554 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2555}
7322fd19 2556EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2557
54e4cec6 2558void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2559{
f1dc5600 2560 if (setting)
2660b81a 2561 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2562 else
2660b81a 2563 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2564}
7322fd19 2565EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2566
25c56eec 2567void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2568{
25c56eec 2569 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2570 u32 macmode;
2571
25c56eec 2572 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2573 macmode = AR_2040_JOINED_RX_CLEAR;
2574 else
2575 macmode = 0;
f078f209 2576
f1dc5600 2577 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2578}
ff155a45
VT		 2579
2580/* HW Generic timers configuration */
2581
2582static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2583{
2584 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2585 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2586 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2587 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2588 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2589 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2590 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2591 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2592 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2593 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2594 AR_NDP2_TIMER_MODE, 0x0002},
2595 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2596 AR_NDP2_TIMER_MODE, 0x0004},
2597 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2598 AR_NDP2_TIMER_MODE, 0x0008},
2599 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2600 AR_NDP2_TIMER_MODE, 0x0010},
2601 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2602 AR_NDP2_TIMER_MODE, 0x0020},
2603 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2604 AR_NDP2_TIMER_MODE, 0x0040},
2605 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2606 AR_NDP2_TIMER_MODE, 0x0080}
2607};
2608
2609/* HW generic timer primitives */
2610
2611/* compute and clear index of rightmost 1 */
2612static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2613{
2614 u32 b;
2615
2616 b = *mask;
2617 b &= (0-b);
2618 *mask &= ~b;
2619 b *= debruijn32;
2620 b >>= 27;
2621
2622 return timer_table->gen_timer_index[b];
2623}
2624
1773912b 2625u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2626{
2627 return REG_READ(ah, AR_TSF_L32);
2628}
7322fd19 2629EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2630
2631struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2632 void (*trigger)(void *),
2633 void (*overflow)(void *),
2634 void *arg,
2635 u8 timer_index)
2636{
2637 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2638 struct ath_gen_timer *timer;
2639
2640 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2641
2642 if (timer == NULL) {
c46917bb
LR		 2643 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2644 "Failed to allocate memory"
2645 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 2646 return NULL;
2647 }
2648
2649 /* allocate a hardware generic timer slot */
2650 timer_table->timers[timer_index] = timer;
2651 timer->index = timer_index;
2652 timer->trigger = trigger;
2653 timer->overflow = overflow;
2654 timer->arg = arg;
2655
2656 return timer;
2657}
7322fd19 2658EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2659
cd9bf689
LR		 2660void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2661 struct ath_gen_timer *timer,
2662 u32 timer_next,
2663 u32 timer_period)
ff155a45
VT		 2664{
2665 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2666 u32 tsf;
2667
2668 BUG_ON(!timer_period);
2669
2670 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2671
2672 tsf = ath9k_hw_gettsf32(ah);
2673
c46917bb
LR		 2674 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2675 "curent tsf %x period %x"
2676 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 2677
2678 /*
2679 * Pull timer_next forward if the current TSF already passed it
2680 * because of software latency
2681 */
2682 if (timer_next < tsf)
2683 timer_next = tsf + timer_period;
2684
2685 /*
2686 * Program generic timer registers
2687 */
2688 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2689 timer_next);
2690 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2691 timer_period);
2692 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2693 gen_tmr_configuration[timer->index].mode_mask);
2694
2695 /* Enable both trigger and thresh interrupt masks */
2696 REG_SET_BIT(ah, AR_IMR_S5,
2697 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2698 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2699}
7322fd19 2700EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2701
cd9bf689 2702void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2703{
2704 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2705
2706 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2707 (timer->index >= ATH_MAX_GEN_TIMER)) {
2708 return;
2709 }
2710
2711 /* Clear generic timer enable bits. */
2712 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2713 gen_tmr_configuration[timer->index].mode_mask);
2714
2715 /* Disable both trigger and thresh interrupt masks */
2716 REG_CLR_BIT(ah, AR_IMR_S5,
2717 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2718 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2719
2720 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 2721}
7322fd19 2722EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2723
2724void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2725{
2726 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2727
2728 /* free the hardware generic timer slot */
2729 timer_table->timers[timer->index] = NULL;
2730 kfree(timer);
2731}
7322fd19 2732EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2733
2734/*
2735 * Generic Timer Interrupts handling
2736 */
2737void ath_gen_timer_isr(struct ath_hw *ah)
2738{
2739 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2740 struct ath_gen_timer *timer;
c46917bb 2741 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 2742 u32 trigger_mask, thresh_mask, index;
2743
2744 /* get hardware generic timer interrupt status */
2745 trigger_mask = ah->intr_gen_timer_trigger;
2746 thresh_mask = ah->intr_gen_timer_thresh;
2747 trigger_mask &= timer_table->timer_mask.val;
2748 thresh_mask &= timer_table->timer_mask.val;
2749
2750 trigger_mask &= ~thresh_mask;
2751
2752 while (thresh_mask) {
2753 index = rightmost_index(timer_table, &thresh_mask);
2754 timer = timer_table->timers[index];
2755 BUG_ON(!timer);
c46917bb
LR		 2756 ath_print(common, ATH_DBG_HWTIMER,
2757 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 2758 timer->overflow(timer->arg);
2759 }
2760
2761 while (trigger_mask) {
2762 index = rightmost_index(timer_table, &trigger_mask);
2763 timer = timer_table->timers[index];
2764 BUG_ON(!timer);
c46917bb
LR		 2765 ath_print(common, ATH_DBG_HWTIMER,
2766 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 2767 timer->trigger(timer->arg);
2768 }
2769}
7322fd19 2770EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2771
05020d23
S		 2772/********/
2773/* HTC */
2774/********/
2775
2776void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2777{
2778 ah->htc_reset_init = true;
2779}
2780EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2781
2da4f01a
LR		 2782static struct {
2783 u32 version;
2784 const char * name;
2785} ath_mac_bb_names[] = {
2786 /* Devices with external radios */
2787 { AR_SREV_VERSION_5416_PCI, "5416" },
2788 { AR_SREV_VERSION_5416_PCIE, "5418" },
2789 { AR_SREV_VERSION_9100, "9100" },
2790 { AR_SREV_VERSION_9160, "9160" },
2791 /* Single-chip solutions */
2792 { AR_SREV_VERSION_9280, "9280" },
2793 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 2794 { AR_SREV_VERSION_9287, "9287" },
2795 { AR_SREV_VERSION_9271, "9271" },
ec83903e 2796 { AR_SREV_VERSION_9300, "9300" },
2da4f01a
LR		 2797};
2798
2799/* For devices with external radios */
2800static struct {
2801 u16 version;
2802 const char * name;
2803} ath_rf_names[] = {
2804 { 0, "5133" },
2805 { AR_RAD5133_SREV_MAJOR, "5133" },
2806 { AR_RAD5122_SREV_MAJOR, "5122" },
2807 { AR_RAD2133_SREV_MAJOR, "2133" },
2808 { AR_RAD2122_SREV_MAJOR, "2122" }
2809};
2810
2811/*
2812 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2813 */
f934c4d9 2814static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 2815{
2816 int i;
2817
2818 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2819 if (ath_mac_bb_names[i].version == mac_bb_version) {
2820 return ath_mac_bb_names[i].name;
2821 }
2822 }
2823
2824 return "????";
2825}
2da4f01a
LR		 2826
2827/*
2828 * Return the RF name. "????" is returned if the RF is unknown.
2829 * Used for devices with external radios.
2830 */
f934c4d9 2831static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 2832{
2833 int i;
2834
2835 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2836 if (ath_rf_names[i].version == rf_version) {
2837 return ath_rf_names[i].name;
2838 }
2839 }
2840
2841 return "????";
2842}
f934c4d9
LR		 2843
2844void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2845{
2846 int used;
2847
2848 /* chipsets >= AR9280 are single-chip */
2849 if (AR_SREV_9280_10_OR_LATER(ah)) {
2850 used = snprintf(hw_name, len,
2851 "Atheros AR%s Rev:%x",
2852 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2853 ah->hw_version.macRev);
2854 }
2855 else {
2856 used = snprintf(hw_name, len,
2857 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2858 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2859 ah->hw_version.macRev,
2860 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2861 AR_RADIO_SREV_MAJOR)),
2862 ah->hw_version.phyRev);
2863 }
2864
2865 hw_name[used] = '\0';
2866}
2867EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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