Commit | Line | Data |
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f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef HW_H | |
18 | #define HW_H | |
19 | ||
20 | #include <linux/if_ether.h> | |
21 | #include <linux/delay.h> | |
394cf0a1 | 22 | #include <linux/io.h> |
ab5c4f71 | 23 | #include <linux/firmware.h> |
394cf0a1 S |
24 | |
25 | #include "mac.h" | |
26 | #include "ani.h" | |
27 | #include "eeprom.h" | |
28 | #include "calib.h" | |
394cf0a1 S |
29 | #include "reg.h" |
30 | #include "phy.h" | |
af03abec | 31 | #include "btcoex.h" |
394cf0a1 | 32 | |
203c4805 | 33 | #include "../regd.h" |
3a702e49 | 34 | |
394cf0a1 | 35 | #define ATHEROS_VENDOR_ID 0x168c |
7976b426 | 36 | |
394cf0a1 S |
37 | #define AR5416_DEVID_PCI 0x0023 |
38 | #define AR5416_DEVID_PCIE 0x0024 | |
39 | #define AR9160_DEVID_PCI 0x0027 | |
40 | #define AR9280_DEVID_PCI 0x0029 | |
41 | #define AR9280_DEVID_PCIE 0x002a | |
42 | #define AR9285_DEVID_PCIE 0x002b | |
5ffaf8a3 | 43 | #define AR2427_DEVID_PCIE 0x002c |
db3cc53a SB |
44 | #define AR9287_DEVID_PCI 0x002d |
45 | #define AR9287_DEVID_PCIE 0x002e | |
46 | #define AR9300_DEVID_PCIE 0x0030 | |
b99a7be4 | 47 | #define AR9300_DEVID_AR9340 0x0031 |
3050c914 | 48 | #define AR9300_DEVID_AR9485_PCIE 0x0032 |
5a63ef0f | 49 | #define AR9300_DEVID_AR9580 0x0033 |
423e38e8 | 50 | #define AR9300_DEVID_AR9462 0x0034 |
03689301 | 51 | #define AR9300_DEVID_AR9330 0x0035 |
b1233779 | 52 | #define AR9300_DEVID_QCA955X 0x0038 |
d4e5979c | 53 | #define AR9485_DEVID_AR1111 0x0037 |
77fac465 | 54 | #define AR9300_DEVID_AR9565 0x0036 |
7976b426 | 55 | |
394cf0a1 | 56 | #define AR5416_AR9100_DEVID 0x000b |
7976b426 | 57 | |
394cf0a1 S |
58 | #define AR_SUBVENDOR_ID_NOG 0x0e11 |
59 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | |
60 | #define AR5416_MAGIC 0x19641014 | |
61 | ||
fe12946e VT |
62 | #define AR9280_COEX2WIRE_SUBSYSID 0x309b |
63 | #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa | |
64 | #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab | |
65 | ||
e3d01bfc LR |
66 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) |
67 | ||
cfe8cba9 LR |
68 | #define ATH_DEFAULT_NOISE_FLOOR -95 |
69 | ||
04658fba | 70 | #define ATH9K_RSSI_BAD -128 |
990b70ab | 71 | |
cac4220b FF |
72 | #define ATH9K_NUM_CHANNELS 38 |
73 | ||
394cf0a1 | 74 | /* Register read/write primitives */ |
9e4bffd2 | 75 | #define REG_WRITE(_ah, _reg, _val) \ |
f9f84e96 | 76 | (_ah)->reg_ops.write((_ah), (_val), (_reg)) |
9e4bffd2 LR |
77 | |
78 | #define REG_READ(_ah, _reg) \ | |
f9f84e96 | 79 | (_ah)->reg_ops.read((_ah), (_reg)) |
394cf0a1 | 80 | |
09a525d3 | 81 | #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ |
f9f84e96 | 82 | (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) |
09a525d3 | 83 | |
845e03c9 FF |
84 | #define REG_RMW(_ah, _reg, _set, _clr) \ |
85 | (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) | |
86 | ||
20b3efd9 S |
87 | #define ENABLE_REGWRITE_BUFFER(_ah) \ |
88 | do { \ | |
f9f84e96 FF |
89 | if ((_ah)->reg_ops.enable_write_buffer) \ |
90 | (_ah)->reg_ops.enable_write_buffer((_ah)); \ | |
20b3efd9 S |
91 | } while (0) |
92 | ||
20b3efd9 S |
93 | #define REGWRITE_BUFFER_FLUSH(_ah) \ |
94 | do { \ | |
f9f84e96 FF |
95 | if ((_ah)->reg_ops.write_flush) \ |
96 | (_ah)->reg_ops.write_flush((_ah)); \ | |
20b3efd9 S |
97 | } while (0) |
98 | ||
26526202 RM |
99 | #define PR_EEP(_s, _val) \ |
100 | do { \ | |
5e88ba62 ZK |
101 | len += scnprintf(buf + len, size - len, "%20s : %10d\n",\ |
102 | _s, (_val)); \ | |
26526202 RM |
103 | } while (0) |
104 | ||
394cf0a1 S |
105 | #define SM(_v, _f) (((_v) << _f##_S) & _f) |
106 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | |
394cf0a1 | 107 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ |
845e03c9 | 108 | REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) |
1547da37 LR |
109 | #define REG_READ_FIELD(_a, _r, _f) \ |
110 | (((REG_READ(_a, _r) & _f) >> _f##_S)) | |
394cf0a1 | 111 | #define REG_SET_BIT(_a, _r, _f) \ |
845e03c9 | 112 | REG_RMW(_a, _r, (_f), 0) |
394cf0a1 | 113 | #define REG_CLR_BIT(_a, _r, _f) \ |
845e03c9 | 114 | REG_RMW(_a, _r, 0, (_f)) |
f078f209 | 115 | |
e7fc6338 RM |
116 | #define DO_DELAY(x) do { \ |
117 | if (((++(x) % 64) == 0) && \ | |
118 | (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ | |
119 | != ATH_USB)) \ | |
120 | udelay(1); \ | |
394cf0a1 | 121 | } while (0) |
f078f209 | 122 | |
a9b6b256 FF |
123 | #define REG_WRITE_ARRAY(iniarray, column, regWr) \ |
124 | ath9k_hw_write_array(ah, iniarray, column, &(regWr)) | |
f078f209 | 125 | |
394cf0a1 S |
126 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
127 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | |
128 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | |
129 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 | |
1773912b | 130 | #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 |
394cf0a1 S |
131 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
132 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | |
93d36e99 MSS |
133 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 |
134 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 | |
135 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 | |
136 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 | |
137 | #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 | |
138 | #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 | |
139 | #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 | |
140 | #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 | |
141 | #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d | |
142 | #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e | |
f078f209 | 143 | |
394cf0a1 S |
144 | #define AR_GPIOD_MASK 0x00001FFF |
145 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) | |
f078f209 | 146 | |
394cf0a1 | 147 | #define BASE_ACTIVATE_DELAY 100 |
0b488ac6 | 148 | #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) |
394cf0a1 S |
149 | #define COEF_SCALE_S 24 |
150 | #define HT40_CHANNEL_CENTER_SHIFT 10 | |
f078f209 | 151 | |
394cf0a1 S |
152 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 |
153 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 | |
154 | ||
155 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 | |
156 | #define ATH9K_NUM_QUEUES 10 | |
157 | ||
158 | #define MAX_RATE_POWER 63 | |
0caa7b14 | 159 | #define AH_WAIT_TIMEOUT 100000 /* (us) */ |
f9b604f6 | 160 | #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ |
394cf0a1 S |
161 | #define AH_TIME_QUANTUM 10 |
162 | #define AR_KEYTABLE_SIZE 128 | |
d8caa839 | 163 | #define POWER_UP_TIME 10000 |
394cf0a1 | 164 | #define SPUR_RSSI_THRESH 40 |
331c5ea2 MSS |
165 | #define UPPER_5G_SUB_BAND_START 5700 |
166 | #define MID_5G_SUB_BAND_START 5400 | |
394cf0a1 S |
167 | |
168 | #define CAB_TIMEOUT_VAL 10 | |
169 | #define BEACON_TIMEOUT_VAL 10 | |
170 | #define MIN_BEACON_TIMEOUT_VAL 1 | |
171 | #define SLEEP_SLOP 3 | |
172 | ||
173 | #define INIT_CONFIG_STATUS 0x00000000 | |
174 | #define INIT_RSSI_THR 0x00000700 | |
175 | #define INIT_BCON_CNTRL_REG 0x00000000 | |
176 | ||
177 | #define TU_TO_USEC(_tu) ((_tu) << 10) | |
178 | ||
ceb26445 VT |
179 | #define ATH9K_HW_RX_HP_QDEPTH 16 |
180 | #define ATH9K_HW_RX_LP_QDEPTH 128 | |
181 | ||
0e44d48c MSS |
182 | #define PAPRD_GAIN_TABLE_ENTRIES 32 |
183 | #define PAPRD_TABLE_SZ 24 | |
184 | #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 | |
717f6bed | 185 | |
01c78533 MSS |
186 | /* |
187 | * Wake on Wireless | |
188 | */ | |
189 | ||
190 | /* Keep Alive Frame */ | |
191 | #define KAL_FRAME_LEN 28 | |
192 | #define KAL_FRAME_TYPE 0x2 /* data frame */ | |
193 | #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */ | |
194 | #define KAL_DURATION_ID 0x3d | |
195 | #define KAL_NUM_DATA_WORDS 6 | |
196 | #define KAL_NUM_DESC_WORDS 12 | |
197 | #define KAL_ANTENNA_MODE 1 | |
198 | #define KAL_TO_DS 1 | |
199 | #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */ | |
200 | #define KAL_TIMEOUT 900 | |
201 | ||
202 | #define MAX_PATTERN_SIZE 256 | |
203 | #define MAX_PATTERN_MASK_SIZE 32 | |
204 | #define MAX_NUM_PATTERN 8 | |
205 | #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and | |
206 | deauthenticate packets */ | |
207 | ||
208 | /* | |
209 | * WoW trigger mapping to hardware code | |
210 | */ | |
211 | ||
212 | #define AH_WOW_USER_PATTERN_EN BIT(0) | |
213 | #define AH_WOW_MAGIC_PATTERN_EN BIT(1) | |
214 | #define AH_WOW_LINK_CHANGE BIT(2) | |
215 | #define AH_WOW_BEACON_MISS BIT(3) | |
216 | ||
066dae93 FF |
217 | enum ath_hw_txq_subtype { |
218 | ATH_TXQ_AC_BE = 0, | |
219 | ATH_TXQ_AC_BK = 1, | |
220 | ATH_TXQ_AC_VI = 2, | |
221 | ATH_TXQ_AC_VO = 3, | |
222 | }; | |
223 | ||
13ce3e99 LR |
224 | enum ath_ini_subsys { |
225 | ATH_INI_PRE = 0, | |
226 | ATH_INI_CORE, | |
227 | ATH_INI_POST, | |
228 | ATH_INI_NUM_SPLIT, | |
229 | }; | |
230 | ||
394cf0a1 | 231 | enum ath9k_hw_caps { |
364734fa FF |
232 | ATH9K_HW_CAP_HT = BIT(0), |
233 | ATH9K_HW_CAP_RFSILENT = BIT(1), | |
1b2538b2 MSS |
234 | ATH9K_HW_CAP_AUTOSLEEP = BIT(2), |
235 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), | |
236 | ATH9K_HW_CAP_EDMA = BIT(4), | |
237 | ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), | |
238 | ATH9K_HW_CAP_LDPC = BIT(6), | |
239 | ATH9K_HW_CAP_FASTCLOCK = BIT(7), | |
240 | ATH9K_HW_CAP_SGI_20 = BIT(8), | |
1b2538b2 MSS |
241 | ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), |
242 | ATH9K_HW_CAP_2GHZ = BIT(11), | |
243 | ATH9K_HW_CAP_5GHZ = BIT(12), | |
244 | ATH9K_HW_CAP_APM = BIT(13), | |
245 | ATH9K_HW_CAP_RTT = BIT(14), | |
246 | ATH9K_HW_CAP_MCI = BIT(15), | |
247 | ATH9K_HW_CAP_DFS = BIT(16), | |
8e981389 | 248 | ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(17), |
846e438f | 249 | ATH9K_HW_CAP_PAPRD = BIT(18), |
81dc75b5 | 250 | ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(19), |
3f2da955 | 251 | ATH9K_HW_CAP_BT_ANT_DIV = BIT(20), |
394cf0a1 | 252 | }; |
f078f209 | 253 | |
8e981389 MSS |
254 | /* |
255 | * WoW device capabilities | |
256 | * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW. | |
257 | * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching | |
258 | * an exact user defined pattern or de-authentication/disassoc pattern. | |
259 | * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four | |
260 | * bytes of the pattern for user defined pattern, de-authentication and | |
261 | * disassociation patterns for all types of possible frames recieved | |
262 | * of those types. | |
263 | */ | |
264 | ||
394cf0a1 S |
265 | struct ath9k_hw_capabilities { |
266 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ | |
394cf0a1 S |
267 | u16 rts_aggr_limit; |
268 | u8 tx_chainmask; | |
269 | u8 rx_chainmask; | |
47c80de6 VT |
270 | u8 max_txchains; |
271 | u8 max_rxchains; | |
394cf0a1 | 272 | u8 num_gpio_pins; |
ceb26445 VT |
273 | u8 rx_hp_qdepth; |
274 | u8 rx_lp_qdepth; | |
275 | u8 rx_status_len; | |
162c3be3 | 276 | u8 tx_desc_len; |
5088c2f1 | 277 | u8 txs_len; |
394cf0a1 | 278 | }; |
f078f209 | 279 | |
394cf0a1 S |
280 | struct ath9k_ops_config { |
281 | int dma_beacon_response_time; | |
282 | int sw_beacon_response_time; | |
283 | int additional_swba_backoff; | |
284 | int ack_6mb; | |
41f3e54d | 285 | u32 cwm_ignore_extcca; |
6a0ec30a | 286 | bool pcieSerDesWrite; |
394cf0a1 S |
287 | u8 pcie_clock_req; |
288 | u32 pcie_waen; | |
394cf0a1 | 289 | u8 analog_shiftreg; |
394cf0a1 S |
290 | u32 ofdm_trig_low; |
291 | u32 ofdm_trig_high; | |
292 | u32 cck_trig_high; | |
293 | u32 cck_trig_low; | |
74673db9 | 294 | u32 enable_paprd; |
394cf0a1 | 295 | int serialize_regmode; |
0ce024cb | 296 | bool rx_intr_mitigation; |
55e82df4 | 297 | bool tx_intr_mitigation; |
394cf0a1 S |
298 | #define SPUR_DISABLE 0 |
299 | #define SPUR_ENABLE_IOCTL 1 | |
300 | #define SPUR_ENABLE_EEPROM 2 | |
394cf0a1 S |
301 | #define AR_SPUR_5413_1 1640 |
302 | #define AR_SPUR_5413_2 1200 | |
303 | #define AR_NO_SPUR 0x8000 | |
304 | #define AR_BASE_FREQ_2GHZ 2300 | |
305 | #define AR_BASE_FREQ_5GHZ 4900 | |
306 | #define AR_SPUR_FEEQ_BOUND_HT40 19 | |
307 | #define AR_SPUR_FEEQ_BOUND_HT20 10 | |
308 | int spurmode; | |
309 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; | |
f4709fdf | 310 | u8 max_txtrig_level; |
e36b27af | 311 | u16 ani_poll_interval; /* ANI poll interval in ms */ |
9b60b64b SM |
312 | |
313 | /* Platform specific config */ | |
b380a43b | 314 | u32 aspm_l1_fix; |
9b60b64b | 315 | u32 xlna_gpio; |
31fd216d | 316 | u32 ant_ctrl_comm2g_switch_enable; |
9b60b64b | 317 | bool xatten_margin_cfg; |
e083a42e | 318 | bool alt_mingainidx; |
2d22c7dd | 319 | bool no_pll_pwrsave; |
394cf0a1 | 320 | }; |
f078f209 | 321 | |
394cf0a1 S |
322 | enum ath9k_int { |
323 | ATH9K_INT_RX = 0x00000001, | |
324 | ATH9K_INT_RXDESC = 0x00000002, | |
b5c80475 FF |
325 | ATH9K_INT_RXHP = 0x00000001, |
326 | ATH9K_INT_RXLP = 0x00000002, | |
394cf0a1 S |
327 | ATH9K_INT_RXNOFRM = 0x00000008, |
328 | ATH9K_INT_RXEOL = 0x00000010, | |
329 | ATH9K_INT_RXORN = 0x00000020, | |
330 | ATH9K_INT_TX = 0x00000040, | |
331 | ATH9K_INT_TXDESC = 0x00000080, | |
332 | ATH9K_INT_TIM_TIMER = 0x00000100, | |
2ee4bd1e | 333 | ATH9K_INT_MCI = 0x00000200, |
aea702b7 | 334 | ATH9K_INT_BB_WATCHDOG = 0x00000400, |
394cf0a1 S |
335 | ATH9K_INT_TXURN = 0x00000800, |
336 | ATH9K_INT_MIB = 0x00001000, | |
337 | ATH9K_INT_RXPHY = 0x00004000, | |
338 | ATH9K_INT_RXKCM = 0x00008000, | |
339 | ATH9K_INT_SWBA = 0x00010000, | |
340 | ATH9K_INT_BMISS = 0x00040000, | |
341 | ATH9K_INT_BNR = 0x00100000, | |
342 | ATH9K_INT_TIM = 0x00200000, | |
343 | ATH9K_INT_DTIM = 0x00400000, | |
344 | ATH9K_INT_DTIMSYNC = 0x00800000, | |
345 | ATH9K_INT_GPIO = 0x01000000, | |
346 | ATH9K_INT_CABEND = 0x02000000, | |
4af9cf4f | 347 | ATH9K_INT_TSFOOR = 0x04000000, |
ff155a45 | 348 | ATH9K_INT_GENTIMER = 0x08000000, |
394cf0a1 S |
349 | ATH9K_INT_CST = 0x10000000, |
350 | ATH9K_INT_GTT = 0x20000000, | |
351 | ATH9K_INT_FATAL = 0x40000000, | |
352 | ATH9K_INT_GLOBAL = 0x80000000, | |
353 | ATH9K_INT_BMISC = ATH9K_INT_TIM | | |
354 | ATH9K_INT_DTIM | | |
355 | ATH9K_INT_DTIMSYNC | | |
4af9cf4f | 356 | ATH9K_INT_TSFOOR | |
394cf0a1 S |
357 | ATH9K_INT_CABEND, |
358 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | | |
359 | ATH9K_INT_RXDESC | | |
360 | ATH9K_INT_RXEOL | | |
361 | ATH9K_INT_RXORN | | |
362 | ATH9K_INT_TXURN | | |
363 | ATH9K_INT_TXDESC | | |
364 | ATH9K_INT_MIB | | |
365 | ATH9K_INT_RXPHY | | |
366 | ATH9K_INT_RXKCM | | |
367 | ATH9K_INT_SWBA | | |
368 | ATH9K_INT_BMISS | | |
369 | ATH9K_INT_GPIO, | |
370 | ATH9K_INT_NOCARD = 0xffffffff | |
371 | }; | |
f078f209 | 372 | |
324c74ad | 373 | #define MAX_RTT_TABLE_ENTRY 6 |
5f0c04ea | 374 | #define MAX_IQCAL_MEASUREMENT 8 |
77a5a664 | 375 | #define MAX_CL_TAB_ENTRY 16 |
96da6fdd | 376 | #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j)) |
5f0c04ea | 377 | |
4b9b42bf SM |
378 | enum ath9k_cal_flags { |
379 | RTT_DONE, | |
380 | PAPRD_PACKET_SENT, | |
381 | PAPRD_DONE, | |
382 | NFCAL_PENDING, | |
383 | NFCAL_INTF, | |
384 | TXIQCAL_DONE, | |
385 | TXCLCAL_DONE, | |
3001f0d0 | 386 | SW_PKDET_DONE, |
4b9b42bf SM |
387 | }; |
388 | ||
20bd2a09 | 389 | struct ath9k_hw_cal_data { |
394cf0a1 | 390 | u16 channel; |
6b21fd20 | 391 | u16 channelFlags; |
4b9b42bf | 392 | unsigned long cal_flags; |
394cf0a1 | 393 | int32_t CalValid; |
394cf0a1 S |
394 | int8_t iCoff; |
395 | int8_t qCoff; | |
3001f0d0 | 396 | u8 caldac[2]; |
717f6bed FF |
397 | u16 small_signal_gain[AR9300_MAX_CHAINS]; |
398 | u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; | |
5f0c04ea RM |
399 | u32 num_measures[AR9300_MAX_CHAINS]; |
400 | int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; | |
77a5a664 | 401 | u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; |
8a90555f | 402 | u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY]; |
20bd2a09 FF |
403 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
404 | }; | |
405 | ||
406 | struct ath9k_channel { | |
407 | struct ieee80211_channel *chan; | |
408 | u16 channel; | |
6b21fd20 | 409 | u16 channelFlags; |
d9891c78 | 410 | s16 noisefloor; |
394cf0a1 | 411 | }; |
f078f209 | 412 | |
6b21fd20 FF |
413 | #define CHANNEL_5GHZ BIT(0) |
414 | #define CHANNEL_HALF BIT(1) | |
415 | #define CHANNEL_QUARTER BIT(2) | |
416 | #define CHANNEL_HT BIT(3) | |
417 | #define CHANNEL_HT40PLUS BIT(4) | |
418 | #define CHANNEL_HT40MINUS BIT(5) | |
419 | ||
420 | #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ)) | |
421 | #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) | |
422 | ||
423 | #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF)) | |
424 | #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER)) | |
6b42e8d0 | 425 | #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ |
6b21fd20 FF |
426 | (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) |
427 | ||
428 | #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT) | |
429 | ||
430 | #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c)) | |
431 | ||
432 | #define IS_CHAN_HT40(_c) \ | |
433 | (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS))) | |
434 | ||
435 | #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS) | |
436 | #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS) | |
394cf0a1 S |
437 | |
438 | enum ath9k_power_mode { | |
439 | ATH9K_PM_AWAKE = 0, | |
440 | ATH9K_PM_FULL_SLEEP, | |
441 | ATH9K_PM_NETWORK_SLEEP, | |
442 | ATH9K_PM_UNDEFINED | |
443 | }; | |
f078f209 | 444 | |
394cf0a1 S |
445 | enum ser_reg_mode { |
446 | SER_REG_MODE_OFF = 0, | |
447 | SER_REG_MODE_ON = 1, | |
448 | SER_REG_MODE_AUTO = 2, | |
449 | }; | |
f078f209 | 450 | |
ad7b8060 VT |
451 | enum ath9k_rx_qtype { |
452 | ATH9K_RX_QUEUE_HP, | |
453 | ATH9K_RX_QUEUE_LP, | |
454 | ATH9K_RX_QUEUE_MAX, | |
455 | }; | |
456 | ||
394cf0a1 S |
457 | struct ath9k_beacon_state { |
458 | u32 bs_nexttbtt; | |
459 | u32 bs_nextdtim; | |
460 | u32 bs_intval; | |
4af9cf4f | 461 | #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
394cf0a1 S |
462 | u32 bs_dtimperiod; |
463 | u16 bs_cfpperiod; | |
464 | u16 bs_cfpmaxduration; | |
465 | u32 bs_cfpnext; | |
466 | u16 bs_timoffset; | |
467 | u16 bs_bmissthreshold; | |
468 | u32 bs_sleepduration; | |
4af9cf4f | 469 | u32 bs_tsfoor_threshold; |
394cf0a1 | 470 | }; |
f078f209 | 471 | |
394cf0a1 S |
472 | struct chan_centers { |
473 | u16 synth_center; | |
474 | u16 ctl_center; | |
475 | u16 ext_center; | |
476 | }; | |
f078f209 | 477 | |
394cf0a1 S |
478 | enum { |
479 | ATH9K_RESET_POWER_ON, | |
480 | ATH9K_RESET_WARM, | |
481 | ATH9K_RESET_COLD, | |
482 | }; | |
f078f209 | 483 | |
d535a42a S |
484 | struct ath9k_hw_version { |
485 | u32 magic; | |
486 | u16 devid; | |
487 | u16 subvendorid; | |
488 | u32 macVersion; | |
489 | u16 macRev; | |
490 | u16 phyRev; | |
491 | u16 analog5GhzRev; | |
492 | u16 analog2GhzRev; | |
0b5ead91 | 493 | enum ath_usb_dev usbdev; |
d535a42a | 494 | }; |
394cf0a1 | 495 | |
ff155a45 VT |
496 | /* Generic TSF timer definitions */ |
497 | ||
498 | #define ATH_MAX_GEN_TIMER 16 | |
499 | ||
500 | #define AR_GENTMR_BIT(_index) (1 << (_index)) | |
501 | ||
502 | /* | |
77c2061d | 503 | * Using de Bruijin sequence to look up 1's index in a 32 bit number |
ff155a45 VT |
504 | * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 |
505 | */ | |
c90017dd | 506 | #define debruijn32 0x077CB531U |
ff155a45 VT |
507 | |
508 | struct ath_gen_timer_configuration { | |
509 | u32 next_addr; | |
510 | u32 period_addr; | |
511 | u32 mode_addr; | |
512 | u32 mode_mask; | |
513 | }; | |
514 | ||
515 | struct ath_gen_timer { | |
516 | void (*trigger)(void *arg); | |
517 | void (*overflow)(void *arg); | |
518 | void *arg; | |
519 | u8 index; | |
520 | }; | |
521 | ||
522 | struct ath_gen_timer_table { | |
523 | u32 gen_timer_index[32]; | |
524 | struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; | |
525 | union { | |
526 | unsigned long timer_bits; | |
527 | u16 val; | |
528 | } timer_mask; | |
529 | }; | |
530 | ||
21cc630f VT |
531 | struct ath_hw_antcomb_conf { |
532 | u8 main_lna_conf; | |
533 | u8 alt_lna_conf; | |
534 | u8 fast_div_bias; | |
c6ba9feb MSS |
535 | u8 main_gaintb; |
536 | u8 alt_gaintb; | |
537 | int lna1_lna2_delta; | |
f96bd2ad | 538 | int lna1_lna2_switch_delta; |
8afbcc8b | 539 | u8 div_group; |
21cc630f VT |
540 | }; |
541 | ||
4e8c14e9 FF |
542 | /** |
543 | * struct ath_hw_radar_conf - radar detection initialization parameters | |
544 | * | |
545 | * @pulse_inband: threshold for checking the ratio of in-band power | |
546 | * to total power for short radar pulses (half dB steps) | |
547 | * @pulse_inband_step: threshold for checking an in-band power to total | |
548 | * power ratio increase for short radar pulses (half dB steps) | |
549 | * @pulse_height: threshold for detecting the beginning of a short | |
550 | * radar pulse (dB step) | |
551 | * @pulse_rssi: threshold for detecting if a short radar pulse is | |
552 | * gone (dB step) | |
553 | * @pulse_maxlen: maximum pulse length (0.8 us steps) | |
554 | * | |
555 | * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) | |
556 | * @radar_inband: threshold for checking the ratio of in-band power | |
557 | * to total power for long radar pulses (half dB steps) | |
558 | * @fir_power: threshold for detecting the end of a long radar pulse (dB) | |
559 | * | |
560 | * @ext_channel: enable extension channel radar detection | |
561 | */ | |
562 | struct ath_hw_radar_conf { | |
563 | unsigned int pulse_inband; | |
564 | unsigned int pulse_inband_step; | |
565 | unsigned int pulse_height; | |
566 | unsigned int pulse_rssi; | |
567 | unsigned int pulse_maxlen; | |
568 | ||
569 | unsigned int radar_rssi; | |
570 | unsigned int radar_inband; | |
571 | int fir_power; | |
572 | ||
573 | bool ext_channel; | |
574 | }; | |
575 | ||
d70357d5 LR |
576 | /** |
577 | * struct ath_hw_private_ops - callbacks used internally by hardware code | |
578 | * | |
579 | * This structure contains private callbacks designed to only be used internally | |
580 | * by the hardware core. | |
581 | * | |
795f5e2c LR |
582 | * @init_cal_settings: setup types of calibrations supported |
583 | * @init_cal: starts actual calibration | |
584 | * | |
991312d8 | 585 | * @init_mode_gain_regs: Initialize TX/RX gain registers |
8fe65368 LR |
586 | * |
587 | * @rf_set_freq: change frequency | |
588 | * @spur_mitigate_freq: spur mitigation | |
8fe65368 | 589 | * @set_rf_regs: |
64773964 LR |
590 | * @compute_pll_control: compute the PLL control value to use for |
591 | * AR_RTC_PLL_CONTROL for a given channel | |
795f5e2c LR |
592 | * @setup_calibration: set up calibration |
593 | * @iscal_supported: used to query if a type of calibration is supported | |
ac0bb767 | 594 | * |
e36b27af LR |
595 | * @ani_cache_ini_regs: cache the values for ANI from the initial |
596 | * register settings through the register initialization. | |
d70357d5 LR |
597 | */ |
598 | struct ath_hw_private_ops { | |
795f5e2c | 599 | /* Calibration ops */ |
d70357d5 | 600 | void (*init_cal_settings)(struct ath_hw *ah); |
795f5e2c LR |
601 | bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); |
602 | ||
991312d8 | 603 | void (*init_mode_gain_regs)(struct ath_hw *ah); |
795f5e2c LR |
604 | void (*setup_calibration)(struct ath_hw *ah, |
605 | struct ath9k_cal_list *currCal); | |
8fe65368 LR |
606 | |
607 | /* PHY ops */ | |
608 | int (*rf_set_freq)(struct ath_hw *ah, | |
609 | struct ath9k_channel *chan); | |
610 | void (*spur_mitigate_freq)(struct ath_hw *ah, | |
611 | struct ath9k_channel *chan); | |
8fe65368 LR |
612 | bool (*set_rf_regs)(struct ath_hw *ah, |
613 | struct ath9k_channel *chan, | |
614 | u16 modesIndex); | |
615 | void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); | |
616 | void (*init_bb)(struct ath_hw *ah, | |
617 | struct ath9k_channel *chan); | |
618 | int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); | |
619 | void (*olc_init)(struct ath_hw *ah); | |
620 | void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); | |
621 | void (*mark_phy_inactive)(struct ath_hw *ah); | |
622 | void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); | |
623 | bool (*rfbus_req)(struct ath_hw *ah); | |
624 | void (*rfbus_done)(struct ath_hw *ah); | |
8fe65368 | 625 | void (*restore_chainmask)(struct ath_hw *ah); |
64773964 LR |
626 | u32 (*compute_pll_control)(struct ath_hw *ah, |
627 | struct ath9k_channel *chan); | |
c16fcb49 FF |
628 | bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, |
629 | int param); | |
641d9921 | 630 | void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); |
4e8c14e9 FF |
631 | void (*set_radar_params)(struct ath_hw *ah, |
632 | struct ath_hw_radar_conf *conf); | |
5f0c04ea RM |
633 | int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, |
634 | u8 *ini_reloaded); | |
ac0bb767 LR |
635 | |
636 | /* ANI */ | |
e36b27af | 637 | void (*ani_cache_ini_regs)(struct ath_hw *ah); |
d70357d5 LR |
638 | }; |
639 | ||
e93d083f SW |
640 | /** |
641 | * struct ath_spec_scan - parameters for Atheros spectral scan | |
642 | * | |
643 | * @enabled: enable/disable spectral scan | |
644 | * @short_repeat: controls whether the chip is in spectral scan mode | |
645 | * for 4 usec (enabled) or 204 usec (disabled) | |
646 | * @count: number of scan results requested. There are special meanings | |
647 | * in some chip revisions: | |
648 | * AR92xx: highest bit set (>=128) for endless mode | |
649 | * (spectral scan won't stopped until explicitly disabled) | |
650 | * AR9300 and newer: 0 for endless mode | |
651 | * @endless: true if endless mode is intended. Otherwise, count value is | |
652 | * corrected to the next possible value. | |
653 | * @period: time duration between successive spectral scan entry points | |
654 | * (period*256*Tclk). Tclk = ath_common->clockrate | |
655 | * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS | |
656 | * | |
657 | * Note: Tclk = 40MHz or 44MHz depending upon operating mode. | |
658 | * Typically it's 44MHz in 2/5GHz on later chips, but there's | |
659 | * a "fast clock" check for this in 5GHz. | |
660 | * | |
661 | */ | |
662 | struct ath_spec_scan { | |
663 | bool enabled; | |
664 | bool short_repeat; | |
665 | bool endless; | |
666 | u8 count; | |
667 | u8 period; | |
668 | u8 fft_period; | |
669 | }; | |
670 | ||
d70357d5 LR |
671 | /** |
672 | * struct ath_hw_ops - callbacks used by hardware code and driver code | |
673 | * | |
674 | * This structure contains callbacks designed to to be used internally by | |
675 | * hardware code and also by the lower level driver. | |
676 | * | |
677 | * @config_pci_powersave: | |
795f5e2c | 678 | * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC |
e93d083f SW |
679 | * |
680 | * @spectral_scan_config: set parameters for spectral scan and enable/disable it | |
681 | * @spectral_scan_trigger: trigger a spectral scan run | |
682 | * @spectral_scan_wait: wait for a spectral scan run to finish | |
d70357d5 LR |
683 | */ |
684 | struct ath_hw_ops { | |
685 | void (*config_pci_powersave)(struct ath_hw *ah, | |
84c87dc8 | 686 | bool power_off); |
cee1f625 | 687 | void (*rx_enable)(struct ath_hw *ah); |
87d5efbb | 688 | void (*set_desc_link)(void *ds, u32 link); |
795f5e2c LR |
689 | bool (*calibrate)(struct ath_hw *ah, |
690 | struct ath9k_channel *chan, | |
691 | u8 rxchainmask, | |
692 | bool longcal); | |
55e82df4 | 693 | bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); |
2b63a41d FF |
694 | void (*set_txdesc)(struct ath_hw *ah, void *ds, |
695 | struct ath_tx_info *i); | |
cc610ac0 VT |
696 | int (*proc_txdesc)(struct ath_hw *ah, void *ds, |
697 | struct ath_tx_status *ts); | |
69de3721 MSS |
698 | void (*antdiv_comb_conf_get)(struct ath_hw *ah, |
699 | struct ath_hw_antcomb_conf *antconf); | |
700 | void (*antdiv_comb_conf_set)(struct ath_hw *ah, | |
701 | struct ath_hw_antcomb_conf *antconf); | |
e93d083f SW |
702 | void (*spectral_scan_config)(struct ath_hw *ah, |
703 | struct ath_spec_scan *param); | |
704 | void (*spectral_scan_trigger)(struct ath_hw *ah); | |
705 | void (*spectral_scan_wait)(struct ath_hw *ah); | |
36e8825e | 706 | |
89f927af LR |
707 | void (*tx99_start)(struct ath_hw *ah, u32 qnum); |
708 | void (*tx99_stop)(struct ath_hw *ah); | |
709 | void (*tx99_set_txpower)(struct ath_hw *ah, u8 power); | |
710 | ||
36e8825e SM |
711 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
712 | void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable); | |
713 | #endif | |
d70357d5 LR |
714 | }; |
715 | ||
f2552e28 FF |
716 | struct ath_nf_limits { |
717 | s16 max; | |
718 | s16 min; | |
719 | s16 nominal; | |
720 | }; | |
721 | ||
8ad74c4d RM |
722 | enum ath_cal_list { |
723 | TX_IQ_CAL = BIT(0), | |
724 | TX_IQ_ON_AGC_CAL = BIT(1), | |
725 | TX_CL_CAL = BIT(2), | |
726 | }; | |
727 | ||
97dcec57 SM |
728 | /* ah_flags */ |
729 | #define AH_USE_EEPROM 0x1 | |
730 | #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ | |
a126ff51 | 731 | #define AH_FASTCC 0x4 |
97dcec57 | 732 | |
cbe61d8a | 733 | struct ath_hw { |
f9f84e96 FF |
734 | struct ath_ops reg_ops; |
735 | ||
c1b976d2 | 736 | struct device *dev; |
b002a4a9 | 737 | struct ieee80211_hw *hw; |
27c51f1a | 738 | struct ath_common common; |
cbe61d8a | 739 | struct ath9k_hw_version hw_version; |
2660b81a S |
740 | struct ath9k_ops_config config; |
741 | struct ath9k_hw_capabilities caps; | |
cac4220b | 742 | struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; |
2660b81a | 743 | struct ath9k_channel *curchan; |
394cf0a1 | 744 | |
cbe61d8a S |
745 | union { |
746 | struct ar5416_eeprom_def def; | |
747 | struct ar5416_eeprom_4k map4k; | |
475f5989 | 748 | struct ar9287_eeprom map9287; |
15c9ee7a | 749 | struct ar9300_eeprom ar9300_eep; |
2660b81a | 750 | } eeprom; |
f74df6fb | 751 | const struct eeprom_ops *eep_ops; |
cbe61d8a S |
752 | |
753 | bool sw_mgmt_crypto; | |
2660b81a | 754 | bool is_pciexpress; |
d4930086 | 755 | bool aspm_enabled; |
5f841b41 | 756 | bool is_monitoring; |
2eb46d9b | 757 | bool need_an_top2_fixup; |
2660b81a | 758 | u16 tx_trig_level; |
f2552e28 | 759 | |
bbacee13 | 760 | u32 nf_regs[6]; |
f2552e28 FF |
761 | struct ath_nf_limits nf_2g; |
762 | struct ath_nf_limits nf_5g; | |
2660b81a S |
763 | u16 rfsilent; |
764 | u32 rfkill_gpio; | |
765 | u32 rfkill_polarity; | |
cbe61d8a | 766 | u32 ah_flags; |
394cf0a1 | 767 | |
ceb26a60 | 768 | bool reset_power_on; |
d7e7d229 LR |
769 | bool htc_reset_init; |
770 | ||
2660b81a S |
771 | enum nl80211_iftype opmode; |
772 | enum ath9k_power_mode power_mode; | |
f078f209 | 773 | |
f23fba49 | 774 | s8 noise; |
20bd2a09 | 775 | struct ath9k_hw_cal_data *caldata; |
a13883b0 | 776 | struct ath9k_pacal_info pacal_info; |
2660b81a S |
777 | struct ar5416Stats stats; |
778 | struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; | |
779 | ||
3069168c | 780 | enum ath9k_int imask; |
74bad5cb | 781 | u32 imrs2_reg; |
2660b81a S |
782 | u32 txok_interrupt_mask; |
783 | u32 txerr_interrupt_mask; | |
784 | u32 txdesc_interrupt_mask; | |
785 | u32 txeol_interrupt_mask; | |
786 | u32 txurn_interrupt_mask; | |
e8fe7336 | 787 | atomic_t intr_ref_cnt; |
2660b81a S |
788 | bool chip_fullsleep; |
789 | u32 atim_window; | |
5f0c04ea | 790 | u32 modes_index; |
6a2b9e8c S |
791 | |
792 | /* Calibration */ | |
6497827f | 793 | u32 supp_cals; |
cbfe9468 S |
794 | struct ath9k_cal_list iq_caldata; |
795 | struct ath9k_cal_list adcgain_caldata; | |
cbfe9468 S |
796 | struct ath9k_cal_list adcdc_caldata; |
797 | struct ath9k_cal_list *cal_list; | |
798 | struct ath9k_cal_list *cal_list_last; | |
799 | struct ath9k_cal_list *cal_list_curr; | |
2660b81a S |
800 | #define totalPowerMeasI meas0.unsign |
801 | #define totalPowerMeasQ meas1.unsign | |
802 | #define totalIqCorrMeas meas2.sign | |
803 | #define totalAdcIOddPhase meas0.unsign | |
804 | #define totalAdcIEvenPhase meas1.unsign | |
805 | #define totalAdcQOddPhase meas2.unsign | |
806 | #define totalAdcQEvenPhase meas3.unsign | |
807 | #define totalAdcDcOffsetIOddPhase meas0.sign | |
808 | #define totalAdcDcOffsetIEvenPhase meas1.sign | |
809 | #define totalAdcDcOffsetQOddPhase meas2.sign | |
810 | #define totalAdcDcOffsetQEvenPhase meas3.sign | |
f078f209 LR |
811 | union { |
812 | u32 unsign[AR5416_MAX_CHAINS]; | |
813 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 814 | } meas0; |
f078f209 LR |
815 | union { |
816 | u32 unsign[AR5416_MAX_CHAINS]; | |
817 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 818 | } meas1; |
f078f209 LR |
819 | union { |
820 | u32 unsign[AR5416_MAX_CHAINS]; | |
821 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 822 | } meas2; |
f078f209 LR |
823 | union { |
824 | u32 unsign[AR5416_MAX_CHAINS]; | |
825 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a S |
826 | } meas3; |
827 | u16 cal_samples; | |
8ad74c4d | 828 | u8 enabled_cals; |
6a2b9e8c | 829 | |
2660b81a S |
830 | u32 sta_id1_defaults; |
831 | u32 misc_mode; | |
6a2b9e8c | 832 | |
d70357d5 LR |
833 | /* Private to hardware code */ |
834 | struct ath_hw_private_ops private_ops; | |
835 | /* Accessed by the lower level driver */ | |
836 | struct ath_hw_ops ops; | |
837 | ||
e68a060b | 838 | /* Used to program the radio on non single-chip devices */ |
2660b81a | 839 | u32 *analogBank6Data; |
2660b81a | 840 | |
e239d859 | 841 | int coverage_class; |
2660b81a | 842 | u32 slottime; |
2660b81a | 843 | u32 globaltxtimeout; |
6a2b9e8c S |
844 | |
845 | /* ANI */ | |
2660b81a | 846 | u32 aniperiod; |
2660b81a | 847 | enum ath9k_ani_cmd ani_function; |
424749c7 | 848 | u32 ani_skip_count; |
c24bd362 | 849 | struct ar5416AniState ani; |
2660b81a | 850 | |
dbccdd1d | 851 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
766ec4a9 | 852 | struct ath_btcoex_hw btcoex_hw; |
dbccdd1d | 853 | #endif |
af03abec | 854 | |
2660b81a | 855 | u32 intr_txqs; |
2660b81a S |
856 | u8 txchainmask; |
857 | u8 rxchainmask; | |
858 | ||
c5d0855a FF |
859 | struct ath_hw_radar_conf radar_conf; |
860 | ||
8bd1d07f SB |
861 | u32 originalGain[22]; |
862 | int initPDADC; | |
863 | int PDADCdelta; | |
6de66dd9 | 864 | int led_pin; |
691680b8 FF |
865 | u32 gpio_mask; |
866 | u32 gpio_val; | |
8bd1d07f | 867 | |
2660b81a S |
868 | struct ar5416IniArray iniModes; |
869 | struct ar5416IniArray iniCommon; | |
2660b81a | 870 | struct ar5416IniArray iniBB_RfGain; |
2660b81a | 871 | struct ar5416IniArray iniBank6; |
2660b81a S |
872 | struct ar5416IniArray iniAddac; |
873 | struct ar5416IniArray iniPcieSerdes; | |
13ce3e99 | 874 | struct ar5416IniArray iniPcieSerdesLowPower; |
c7d36f9f FF |
875 | struct ar5416IniArray iniModesFastClock; |
876 | struct ar5416IniArray iniAdditional; | |
2660b81a | 877 | struct ar5416IniArray iniModesRxGain; |
8bc45c6b | 878 | struct ar5416IniArray ini_modes_rx_gain_bounds; |
2660b81a | 879 | struct ar5416IniArray iniModesTxGain; |
193cd458 S |
880 | struct ar5416IniArray iniCckfirNormal; |
881 | struct ar5416IniArray iniCckfirJapan2484; | |
70807e99 | 882 | struct ar5416IniArray iniModes_9271_ANI_reg; |
ce407afc | 883 | struct ar5416IniArray ini_radio_post_sys2ant; |
51dbd0a8 | 884 | struct ar5416IniArray ini_modes_rxgain_5g_xlna; |
c177fabe SM |
885 | struct ar5416IniArray ini_modes_rxgain_bb_core; |
886 | struct ar5416IniArray ini_modes_rxgain_bb_postamble; | |
ff155a45 | 887 | |
13ce3e99 LR |
888 | struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; |
889 | struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; | |
890 | struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; | |
891 | struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; | |
892 | ||
ff155a45 VT |
893 | u32 intr_gen_timer_trigger; |
894 | u32 intr_gen_timer_thresh; | |
895 | struct ath_gen_timer_table hw_gen_timers; | |
744d4025 VT |
896 | |
897 | struct ar9003_txs *ts_ring; | |
744d4025 VT |
898 | u32 ts_paddr_start; |
899 | u32 ts_paddr_end; | |
900 | u16 ts_tail; | |
016c2177 | 901 | u16 ts_size; |
aea702b7 LR |
902 | |
903 | u32 bb_watchdog_last_status; | |
904 | u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ | |
51ac8cbb | 905 | u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ |
717f6bed | 906 | |
1bf38661 FF |
907 | unsigned int paprd_target_power; |
908 | unsigned int paprd_training_power; | |
7072bf62 | 909 | unsigned int paprd_ratemask; |
f1a8abb0 | 910 | unsigned int paprd_ratemask_ht40; |
45ef6a0b | 911 | bool paprd_table_write_done; |
717f6bed FF |
912 | u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; |
913 | u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; | |
9a658d2b LR |
914 | /* |
915 | * Store the permanent value of Reg 0x4004in WARegVal | |
916 | * so we dont have to R/M/W. We should not be reading | |
917 | * this register when in sleep states. | |
918 | */ | |
919 | u32 WARegVal; | |
6ee63f55 SB |
920 | |
921 | /* Enterprise mode cap */ | |
922 | u32 ent_mode; | |
f2f5f2a1 | 923 | |
01c78533 MSS |
924 | #ifdef CONFIG_PM_SLEEP |
925 | u32 wow_event_mask; | |
926 | #endif | |
f2f5f2a1 | 927 | bool is_clk_25mhz; |
3762561a | 928 | int (*get_mac_revision)(void); |
7d95847c | 929 | int (*external_reset)(void); |
ab5c4f71 GJ |
930 | |
931 | const struct firmware *eeprom_blob; | |
f078f209 | 932 | }; |
f078f209 | 933 | |
0cb9e06b FF |
934 | struct ath_bus_ops { |
935 | enum ath_bus_type ath_bus_type; | |
936 | void (*read_cachesize)(struct ath_common *common, int *csz); | |
937 | bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); | |
938 | void (*bt_coex_prep)(struct ath_common *common); | |
d4930086 | 939 | void (*aspm_init)(struct ath_common *common); |
0cb9e06b FF |
940 | }; |
941 | ||
9e4bffd2 LR |
942 | static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) |
943 | { | |
944 | return &ah->common; | |
945 | } | |
946 | ||
947 | static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) | |
948 | { | |
949 | return &(ath9k_hw_common(ah)->regulatory); | |
950 | } | |
951 | ||
d70357d5 LR |
952 | static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) |
953 | { | |
954 | return &ah->private_ops; | |
955 | } | |
956 | ||
957 | static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) | |
958 | { | |
959 | return &ah->ops; | |
960 | } | |
961 | ||
895ad7eb VT |
962 | static inline u8 get_streams(int mask) |
963 | { | |
964 | return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); | |
965 | } | |
966 | ||
f637cfd6 | 967 | /* Initialization, Detach, Reset */ |
285f2dda | 968 | void ath9k_hw_deinit(struct ath_hw *ah); |
f637cfd6 | 969 | int ath9k_hw_init(struct ath_hw *ah); |
cbe61d8a | 970 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
caed6579 | 971 | struct ath9k_hw_cal_data *caldata, bool fastcc); |
a9a29ce6 | 972 | int ath9k_hw_fill_cap_info(struct ath_hw *ah); |
8fe65368 | 973 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); |
394cf0a1 | 974 | |
394cf0a1 | 975 | /* GPIO / RFKILL / Antennae */ |
cbe61d8a S |
976 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); |
977 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); | |
978 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, | |
394cf0a1 | 979 | u32 ah_signal_type); |
cbe61d8a | 980 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); |
cbe61d8a | 981 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); |
394cf0a1 S |
982 | |
983 | /* General Operation */ | |
7c5adc8d FF |
984 | void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, |
985 | int hw_delay); | |
0caa7b14 | 986 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); |
0166b4be | 987 | void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, |
a9b6b256 | 988 | int column, unsigned int *writecnt); |
394cf0a1 | 989 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
4f0fc7c3 | 990 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 991 | u8 phy, int kbps, |
394cf0a1 | 992 | u32 frameLen, u16 rateix, bool shortPreamble); |
cbe61d8a | 993 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
394cf0a1 S |
994 | struct ath9k_channel *chan, |
995 | struct chan_centers *centers); | |
cbe61d8a S |
996 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah); |
997 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); | |
998 | bool ath9k_hw_phy_disable(struct ath_hw *ah); | |
999 | bool ath9k_hw_disable(struct ath_hw *ah); | |
de40f316 | 1000 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); |
cbe61d8a S |
1001 | void ath9k_hw_setopmode(struct ath_hw *ah); |
1002 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); | |
f2b2143e | 1003 | void ath9k_hw_write_associd(struct ath_hw *ah); |
dd347f2f | 1004 | u32 ath9k_hw_gettsf32(struct ath_hw *ah); |
cbe61d8a S |
1005 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
1006 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); | |
1007 | void ath9k_hw_reset_tsf(struct ath_hw *ah); | |
60ca9f87 | 1008 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set); |
0005baf4 | 1009 | void ath9k_hw_init_global_settings(struct ath_hw *ah); |
b84628eb | 1010 | u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); |
e4744ec7 | 1011 | void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan); |
cbe61d8a S |
1012 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); |
1013 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |
394cf0a1 | 1014 | const struct ath9k_beacon_state *bs); |
1e516ca7 | 1015 | void ath9k_hw_check_nav(struct ath_hw *ah); |
c9c99e5e | 1016 | bool ath9k_hw_check_alive(struct ath_hw *ah); |
a91d75ae | 1017 | |
9ecdef4b | 1018 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); |
a91d75ae | 1019 | |
462e58f2 BG |
1020 | #ifdef CONFIG_ATH9K_DEBUGFS |
1021 | void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause); | |
1022 | #else | |
990e08a0 BG |
1023 | static inline void ath9k_debug_sync_cause(struct ath_common *common, |
1024 | u32 sync_cause) {} | |
462e58f2 BG |
1025 | #endif |
1026 | ||
ff155a45 VT |
1027 | /* Generic hw timer primitives */ |
1028 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
1029 | void (*trigger)(void *), | |
1030 | void (*overflow)(void *), | |
1031 | void *arg, | |
1032 | u8 timer_index); | |
cd9bf689 LR |
1033 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
1034 | struct ath_gen_timer *timer, | |
1035 | u32 timer_next, | |
1036 | u32 timer_period); | |
1037 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); | |
1038 | ||
ff155a45 VT |
1039 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); |
1040 | void ath_gen_timer_isr(struct ath_hw *hw); | |
1041 | ||
f934c4d9 | 1042 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); |
2da4f01a | 1043 | |
8fe65368 LR |
1044 | /* PHY */ |
1045 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, | |
1046 | u32 *coef_mantissa, u32 *coef_exponent); | |
64ea57d0 GJ |
1047 | void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, |
1048 | bool test); | |
8fe65368 | 1049 | |
ebd5a14a LR |
1050 | /* |
1051 | * Code Specific to AR5008, AR9001 or AR9002, | |
1052 | * we stuff these here to avoid callbacks for AR9003. | |
1053 | */ | |
ebd5a14a | 1054 | int ar9002_hw_rf_claim(struct ath_hw *ah); |
78ec2677 | 1055 | void ar9002_hw_enable_async_fifo(struct ath_hw *ah); |
d8f492b7 | 1056 | |
641d9921 | 1057 | /* |
aea702b7 | 1058 | * Code specific to AR9003, we stuff these here to avoid callbacks |
641d9921 FF |
1059 | * for older families |
1060 | */ | |
aea702b7 LR |
1061 | void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); |
1062 | void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); | |
1063 | void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); | |
51ac8cbb | 1064 | void ar9003_hw_disable_phy_restart(struct ath_hw *ah); |
717f6bed FF |
1065 | void ar9003_paprd_enable(struct ath_hw *ah, bool val); |
1066 | void ar9003_paprd_populate_single_table(struct ath_hw *ah, | |
20bd2a09 FF |
1067 | struct ath9k_hw_cal_data *caldata, |
1068 | int chain); | |
1069 | int ar9003_paprd_create_curve(struct ath_hw *ah, | |
1070 | struct ath9k_hw_cal_data *caldata, int chain); | |
36d2943b | 1071 | void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); |
717f6bed FF |
1072 | int ar9003_paprd_init_table(struct ath_hw *ah); |
1073 | bool ar9003_paprd_is_done(struct ath_hw *ah); | |
0f21ee8d | 1074 | bool ar9003_is_paprd_enabled(struct ath_hw *ah); |
4a8f1995 | 1075 | void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); |
641d9921 FF |
1076 | |
1077 | /* Hardware family op attach helpers */ | |
c1b976d2 | 1078 | int ar5008_hw_attach_phy_ops(struct ath_hw *ah); |
8525f280 LR |
1079 | void ar9002_hw_attach_phy_ops(struct ath_hw *ah); |
1080 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah); | |
8fe65368 | 1081 | |
795f5e2c LR |
1082 | void ar9002_hw_attach_calib_ops(struct ath_hw *ah); |
1083 | void ar9003_hw_attach_calib_ops(struct ath_hw *ah); | |
1084 | ||
c1b976d2 | 1085 | int ar9002_hw_attach_ops(struct ath_hw *ah); |
b3950e6a LR |
1086 | void ar9003_hw_attach_ops(struct ath_hw *ah); |
1087 | ||
c2ba3342 | 1088 | void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); |
6790ae7a | 1089 | |
8eb4980c | 1090 | void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); |
95792178 | 1091 | void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); |
ac0bb767 | 1092 | |
8a309305 | 1093 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
dbccdd1d SM |
1094 | static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) |
1095 | { | |
1096 | return ah->btcoex_hw.enabled; | |
1097 | } | |
5955b2b0 SM |
1098 | static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) |
1099 | { | |
e1ecad78 RM |
1100 | return ah->common.btcoex_enabled && |
1101 | (ah->caps.hw_caps & ATH9K_HW_CAP_MCI); | |
5955b2b0 SM |
1102 | |
1103 | } | |
dbccdd1d | 1104 | void ath9k_hw_btcoex_enable(struct ath_hw *ah); |
8a309305 FF |
1105 | static inline enum ath_btcoex_scheme |
1106 | ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) | |
1107 | { | |
1108 | return ah->btcoex_hw.scheme; | |
1109 | } | |
1110 | #else | |
dbccdd1d SM |
1111 | static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) |
1112 | { | |
1113 | return false; | |
1114 | } | |
5955b2b0 SM |
1115 | static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) |
1116 | { | |
1117 | return false; | |
1118 | } | |
dbccdd1d SM |
1119 | static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) |
1120 | { | |
1121 | } | |
1122 | static inline enum ath_btcoex_scheme | |
1123 | ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) | |
1124 | { | |
1125 | return ATH_BTCOEX_CFG_NONE; | |
1126 | } | |
64ab38df | 1127 | #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ |
8a309305 | 1128 | |
64875c63 MSS |
1129 | |
1130 | #ifdef CONFIG_PM_SLEEP | |
1131 | const char *ath9k_hw_wow_event_to_string(u32 wow_event); | |
1132 | void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, | |
1133 | u8 *user_mask, int pattern_count, | |
1134 | int pattern_len); | |
1135 | u32 ath9k_hw_wow_wakeup(struct ath_hw *ah); | |
1136 | void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable); | |
1137 | #else | |
1138 | static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event) | |
1139 | { | |
1140 | return NULL; | |
1141 | } | |
1142 | static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, | |
1143 | u8 *user_pattern, | |
1144 | u8 *user_mask, | |
1145 | int pattern_count, | |
1146 | int pattern_len) | |
1147 | { | |
1148 | } | |
1149 | static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) | |
1150 | { | |
1151 | return 0; | |
1152 | } | |
1153 | static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) | |
1154 | { | |
1155 | } | |
1156 | #endif | |
1157 | ||
73377256 LR |
1158 | #define ATH9K_CLOCK_RATE_CCK 22 |
1159 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 | |
1160 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 | |
1161 | #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 | |
1162 | ||
f078f209 | 1163 | #endif |