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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.h
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
3a702e49 33
394cf0a1 34#define ATHEROS_VENDOR_ID 0x168c
7976b426 35
394cf0a1
S		 36#define AR5416_DEVID_PCI 0x0023
37#define AR5416_DEVID_PCIE 0x0024
38#define AR9160_DEVID_PCI 0x0027
39#define AR9280_DEVID_PCI 0x0029
40#define AR9280_DEVID_PCIE 0x002a
41#define AR9285_DEVID_PCIE 0x002b
5ffaf8a3 42#define AR2427_DEVID_PCIE 0x002c
db3cc53a
SB		 43#define AR9287_DEVID_PCI 0x002d
44#define AR9287_DEVID_PCIE 0x002e
45#define AR9300_DEVID_PCIE 0x0030
b99a7be4 46#define AR9300_DEVID_AR9340 0x0031
3050c914 47#define AR9300_DEVID_AR9485_PCIE 0x0032
5a63ef0f 48#define AR9300_DEVID_AR9580 0x0033
423e38e8 49#define AR9300_DEVID_AR9462 0x0034
03689301 50#define AR9300_DEVID_AR9330 0x0035
7976b426 51
394cf0a1 52#define AR5416_AR9100_DEVID 0x000b
7976b426 53
394cf0a1
S		 54#define AR_SUBVENDOR_ID_NOG 0x0e11
55#define AR_SUBVENDOR_ID_NEW_A 0x7065
56#define AR5416_MAGIC 0x19641014
57
fe12946e
VT		 58#define AR9280_COEX2WIRE_SUBSYSID 0x309b
59#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
60#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
61
e3d01bfc
LR		 62#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
63
cfe8cba9
LR		 64#define ATH_DEFAULT_NOISE_FLOOR -95
65
04658fba 66#define ATH9K_RSSI_BAD -128
990b70ab 67
cac4220b
FF		 68#define ATH9K_NUM_CHANNELS 38
69
394cf0a1 70/* Register read/write primitives */
9e4bffd2 71#define REG_WRITE(_ah, _reg, _val) \
f9f84e96 72 (_ah)->reg_ops.write((_ah), (_val), (_reg))
9e4bffd2
LR		 73
74#define REG_READ(_ah, _reg) \
f9f84e96 75 (_ah)->reg_ops.read((_ah), (_reg))
394cf0a1 76
09a525d3 77#define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
f9f84e96 78 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
09a525d3 79
845e03c9
FF		 80#define REG_RMW(_ah, _reg, _set, _clr) \
81 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
82
20b3efd9
S		 83#define ENABLE_REGWRITE_BUFFER(_ah) \
84 do { \
f9f84e96
FF		 85 if ((_ah)->reg_ops.enable_write_buffer) \
86 (_ah)->reg_ops.enable_write_buffer((_ah)); \
20b3efd9
S		 87 } while (0)
88
20b3efd9
S		 89#define REGWRITE_BUFFER_FLUSH(_ah) \
90 do { \
f9f84e96
FF		 91 if ((_ah)->reg_ops.write_flush) \
92 (_ah)->reg_ops.write_flush((_ah)); \
20b3efd9
S		 93 } while (0)
94
26526202
RM		 95#define PR_EEP(_s, _val) \
96 do { \
97 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
98 _s, (_val)); \
99 } while (0)
100
394cf0a1
S		 101#define SM(_v, _f) (((_v) << _f##_S) & _f)
102#define MS(_v, _f) (((_v) & _f) >> _f##_S)
394cf0a1 103#define REG_RMW_FIELD(_a, _r, _f, _v) \
845e03c9 104 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
1547da37
LR		 105#define REG_READ_FIELD(_a, _r, _f) \
106 (((REG_READ(_a, _r) & _f) >> _f##_S))
394cf0a1 107#define REG_SET_BIT(_a, _r, _f) \
845e03c9 108 REG_RMW(_a, _r, (_f), 0)
394cf0a1 109#define REG_CLR_BIT(_a, _r, _f) \
845e03c9 110 REG_RMW(_a, _r, 0, (_f))
f078f209 111
e7fc6338
RM		 112#define DO_DELAY(x) do { \
113 if (((++(x) % 64) == 0) && \
114 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
115 != ATH_USB)) \
116 udelay(1); \
394cf0a1 117 } while (0)
f078f209 118
a9b6b256
FF		 119#define REG_WRITE_ARRAY(iniarray, column, regWr) \
120 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
f078f209 121
394cf0a1
S		 122#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
123#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
124#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
125#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 126#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 127#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
128#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
93d36e99
MSS		 129#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
130#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
131#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
132#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
133#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
134#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
135#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
136#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
137#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
138#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
f078f209 139
394cf0a1
S		 140#define AR_GPIOD_MASK 0x00001FFF
141#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 142
394cf0a1 143#define BASE_ACTIVATE_DELAY 100
0b488ac6 144#define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
394cf0a1
S		 145#define COEF_SCALE_S 24
146#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 147
394cf0a1
S		 148#define ATH9K_ANTENNA0_CHAINMASK 0x1
149#define ATH9K_ANTENNA1_CHAINMASK 0x2
150
151#define ATH9K_NUM_DMA_DEBUG_REGS 8
152#define ATH9K_NUM_QUEUES 10
153
154#define MAX_RATE_POWER 63
0caa7b14 155#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 156#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 157#define AH_TIME_QUANTUM 10
158#define AR_KEYTABLE_SIZE 128
d8caa839 159#define POWER_UP_TIME 10000
394cf0a1 160#define SPUR_RSSI_THRESH 40
331c5ea2
MSS		 161#define UPPER_5G_SUB_BAND_START 5700
162#define MID_5G_SUB_BAND_START 5400
394cf0a1
S		 163
164#define CAB_TIMEOUT_VAL 10
165#define BEACON_TIMEOUT_VAL 10
166#define MIN_BEACON_TIMEOUT_VAL 1
167#define SLEEP_SLOP 3
168
169#define INIT_CONFIG_STATUS 0x00000000
170#define INIT_RSSI_THR 0x00000700
171#define INIT_BCON_CNTRL_REG 0x00000000
172
173#define TU_TO_USEC(_tu) ((_tu) << 10)
174
ceb26445
VT		 175#define ATH9K_HW_RX_HP_QDEPTH 16
176#define ATH9K_HW_RX_LP_QDEPTH 128
177
0e44d48c
MSS		 178#define PAPRD_GAIN_TABLE_ENTRIES 32
179#define PAPRD_TABLE_SZ 24
180#define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
717f6bed 181
066dae93
FF		 182enum ath_hw_txq_subtype {
183 ATH_TXQ_AC_BE = 0,
184 ATH_TXQ_AC_BK = 1,
185 ATH_TXQ_AC_VI = 2,
186 ATH_TXQ_AC_VO = 3,
187};
188
13ce3e99
LR		 189enum ath_ini_subsys {
190 ATH_INI_PRE = 0,
191 ATH_INI_CORE,
192 ATH_INI_POST,
193 ATH_INI_NUM_SPLIT,
194};
195
394cf0a1 196enum ath9k_hw_caps {
364734fa
FF		 197 ATH9K_HW_CAP_HT = BIT(0),
198 ATH9K_HW_CAP_RFSILENT = BIT(1),
1b2538b2
MSS		 199 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
200 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
201 ATH9K_HW_CAP_EDMA = BIT(4),
202 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
203 ATH9K_HW_CAP_LDPC = BIT(6),
204 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
205 ATH9K_HW_CAP_SGI_20 = BIT(8),
206 ATH9K_HW_CAP_PAPRD = BIT(9),
207 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
208 ATH9K_HW_CAP_2GHZ = BIT(11),
209 ATH9K_HW_CAP_5GHZ = BIT(12),
210 ATH9K_HW_CAP_APM = BIT(13),
211 ATH9K_HW_CAP_RTT = BIT(14),
212 ATH9K_HW_CAP_MCI = BIT(15),
213 ATH9K_HW_CAP_DFS = BIT(16),
394cf0a1 214};
f078f209 215
394cf0a1
S		 216struct ath9k_hw_capabilities {
217 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
394cf0a1
S		 218 u16 rts_aggr_limit;
219 u8 tx_chainmask;
220 u8 rx_chainmask;
47c80de6
VT		 221 u8 max_txchains;
222 u8 max_rxchains;
394cf0a1 223 u8 num_gpio_pins;
ceb26445
VT		 224 u8 rx_hp_qdepth;
225 u8 rx_lp_qdepth;
226 u8 rx_status_len;
162c3be3 227 u8 tx_desc_len;
5088c2f1 228 u8 txs_len;
8060e169
VT		 229 u16 pcie_lcr_offset;
230 bool pcie_lcr_extsync_en;
394cf0a1 231};
f078f209 232
394cf0a1
S		 233struct ath9k_ops_config {
234 int dma_beacon_response_time;
235 int sw_beacon_response_time;
236 int additional_swba_backoff;
237 int ack_6mb;
41f3e54d 238 u32 cwm_ignore_extcca;
6a0ec30a 239 bool pcieSerDesWrite;
394cf0a1
S		 240 u8 pcie_clock_req;
241 u32 pcie_waen;
394cf0a1 242 u8 analog_shiftreg;
6f481010 243 u8 paprd_disable;
394cf0a1
S		 244 u32 ofdm_trig_low;
245 u32 ofdm_trig_high;
246 u32 cck_trig_high;
247 u32 cck_trig_low;
248 u32 enable_ani;
394cf0a1 249 int serialize_regmode;
0ce024cb 250 bool rx_intr_mitigation;
55e82df4 251 bool tx_intr_mitigation;
394cf0a1
S		 252#define SPUR_DISABLE 0
253#define SPUR_ENABLE_IOCTL 1
254#define SPUR_ENABLE_EEPROM 2
394cf0a1
S		 255#define AR_SPUR_5413_1 1640
256#define AR_SPUR_5413_2 1200
257#define AR_NO_SPUR 0x8000
258#define AR_BASE_FREQ_2GHZ 2300
259#define AR_BASE_FREQ_5GHZ 4900
260#define AR_SPUR_FEEQ_BOUND_HT40 19
261#define AR_SPUR_FEEQ_BOUND_HT20 10
262 int spurmode;
263 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
f4709fdf 264 u8 max_txtrig_level;
e36b27af 265 u16 ani_poll_interval; /* ANI poll interval in ms */
394cf0a1 266};
f078f209 267
394cf0a1
S		 268enum ath9k_int {
269 ATH9K_INT_RX = 0x00000001,
270 ATH9K_INT_RXDESC = 0x00000002,
b5c80475
FF		 271 ATH9K_INT_RXHP = 0x00000001,
272 ATH9K_INT_RXLP = 0x00000002,
394cf0a1
S		 273 ATH9K_INT_RXNOFRM = 0x00000008,
274 ATH9K_INT_RXEOL = 0x00000010,
275 ATH9K_INT_RXORN = 0x00000020,
276 ATH9K_INT_TX = 0x00000040,
277 ATH9K_INT_TXDESC = 0x00000080,
278 ATH9K_INT_TIM_TIMER = 0x00000100,
2ee4bd1e 279 ATH9K_INT_MCI = 0x00000200,
aea702b7 280 ATH9K_INT_BB_WATCHDOG = 0x00000400,
394cf0a1
S		 281 ATH9K_INT_TXURN = 0x00000800,
282 ATH9K_INT_MIB = 0x00001000,
283 ATH9K_INT_RXPHY = 0x00004000,
284 ATH9K_INT_RXKCM = 0x00008000,
285 ATH9K_INT_SWBA = 0x00010000,
286 ATH9K_INT_BMISS = 0x00040000,
287 ATH9K_INT_BNR = 0x00100000,
288 ATH9K_INT_TIM = 0x00200000,
289 ATH9K_INT_DTIM = 0x00400000,
290 ATH9K_INT_DTIMSYNC = 0x00800000,
291 ATH9K_INT_GPIO = 0x01000000,
292 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 293 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 294 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 295 ATH9K_INT_CST = 0x10000000,
296 ATH9K_INT_GTT = 0x20000000,
297 ATH9K_INT_FATAL = 0x40000000,
298 ATH9K_INT_GLOBAL = 0x80000000,
299 ATH9K_INT_BMISC = ATH9K_INT_TIM |
300 ATH9K_INT_DTIM |
301 ATH9K_INT_DTIMSYNC |
4af9cf4f 302 ATH9K_INT_TSFOOR |
394cf0a1
S		 303 ATH9K_INT_CABEND,
304 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
305 ATH9K_INT_RXDESC |
306 ATH9K_INT_RXEOL |
307 ATH9K_INT_RXORN |
308 ATH9K_INT_TXURN |
309 ATH9K_INT_TXDESC |
310 ATH9K_INT_MIB |
311 ATH9K_INT_RXPHY |
312 ATH9K_INT_RXKCM |
313 ATH9K_INT_SWBA |
314 ATH9K_INT_BMISS |
315 ATH9K_INT_GPIO,
316 ATH9K_INT_NOCARD = 0xffffffff
317};
f078f209 318
394cf0a1
S		 319#define CHANNEL_CW_INT 0x00002
320#define CHANNEL_CCK 0x00020
321#define CHANNEL_OFDM 0x00040
322#define CHANNEL_2GHZ 0x00080
323#define CHANNEL_5GHZ 0x00100
324#define CHANNEL_PASSIVE 0x00200
325#define CHANNEL_DYN 0x00400
326#define CHANNEL_HALF 0x04000
327#define CHANNEL_QUARTER 0x08000
328#define CHANNEL_HT20 0x10000
329#define CHANNEL_HT40PLUS 0x20000
330#define CHANNEL_HT40MINUS 0x40000
331
394cf0a1
S		 332#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
333#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
334#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
335#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
336#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
337#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
338#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
339#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
340#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
341#define CHANNEL_ALL \
342 (CHANNEL_OFDM| \
343 CHANNEL_CCK| \
344 CHANNEL_2GHZ | \
345 CHANNEL_5GHZ | \
346 CHANNEL_HT20 | \
347 CHANNEL_HT40PLUS | \
348 CHANNEL_HT40MINUS)
349
324c74ad
RM		 350#define MAX_RTT_TABLE_ENTRY 6
351#define RTT_HIST_MAX 3
352struct ath9k_rtt_hist {
353 u32 table[AR9300_MAX_CHAINS][RTT_HIST_MAX][MAX_RTT_TABLE_ENTRY];
354 u8 num_readings;
355};
356
5f0c04ea 357#define MAX_IQCAL_MEASUREMENT 8
77a5a664 358#define MAX_CL_TAB_ENTRY 16
5f0c04ea 359
20bd2a09 360struct ath9k_hw_cal_data {
394cf0a1
S		 361 u16 channel;
362 u32 channelFlags;
394cf0a1 363 int32_t CalValid;
394cf0a1
S		 364 int8_t iCoff;
365 int8_t qCoff;
717f6bed 366 bool paprd_done;
4254bc1c 367 bool nfcal_pending;
70cf1533 368 bool nfcal_interference;
5f0c04ea 369 bool done_txiqcal_once;
77a5a664 370 bool done_txclcal_once;
717f6bed
FF		 371 u16 small_signal_gain[AR9300_MAX_CHAINS];
372 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
5f0c04ea
RM		 373 u32 num_measures[AR9300_MAX_CHAINS];
374 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
77a5a664 375 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
20bd2a09 376 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
324c74ad 377 struct ath9k_rtt_hist rtt_hist;
20bd2a09
FF		 378};
379
380struct ath9k_channel {
381 struct ieee80211_channel *chan;
093115b7 382 struct ar5416AniState ani;
20bd2a09
FF		 383 u16 channel;
384 u32 channelFlags;
385 u32 chanmode;
d9891c78 386 s16 noisefloor;
394cf0a1 387};
f078f209 388
394cf0a1
S		 389#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
390 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
391 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
392 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
393#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
394#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
395#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 396#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
397#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
6b42e8d0 398#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
394cf0a1 399 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
6b42e8d0 400 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
394cf0a1
S		 401
402/* These macros check chanmode and not channelFlags */
403#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
404#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
405 ((_c)->chanmode == CHANNEL_G_HT20))
406#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
407 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
408 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
409 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
410#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
411
412enum ath9k_power_mode {
413 ATH9K_PM_AWAKE = 0,
414 ATH9K_PM_FULL_SLEEP,
415 ATH9K_PM_NETWORK_SLEEP,
416 ATH9K_PM_UNDEFINED
417};
f078f209 418
394cf0a1
S		 419enum ser_reg_mode {
420 SER_REG_MODE_OFF = 0,
421 SER_REG_MODE_ON = 1,
422 SER_REG_MODE_AUTO = 2,
423};
f078f209 424
ad7b8060
VT		 425enum ath9k_rx_qtype {
426 ATH9K_RX_QUEUE_HP,
427 ATH9K_RX_QUEUE_LP,
428 ATH9K_RX_QUEUE_MAX,
429};
430
394cf0a1
S		 431struct ath9k_beacon_state {
432 u32 bs_nexttbtt;
433 u32 bs_nextdtim;
434 u32 bs_intval;
4af9cf4f 435#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 436 u32 bs_dtimperiod;
437 u16 bs_cfpperiod;
438 u16 bs_cfpmaxduration;
439 u32 bs_cfpnext;
440 u16 bs_timoffset;
441 u16 bs_bmissthreshold;
442 u32 bs_sleepduration;
4af9cf4f 443 u32 bs_tsfoor_threshold;
394cf0a1 444};
f078f209 445
394cf0a1
S		 446struct chan_centers {
447 u16 synth_center;
448 u16 ctl_center;
449 u16 ext_center;
450};
f078f209 451
394cf0a1
S		 452enum {
453 ATH9K_RESET_POWER_ON,
454 ATH9K_RESET_WARM,
455 ATH9K_RESET_COLD,
456};
f078f209 457
d535a42a
S		 458struct ath9k_hw_version {
459 u32 magic;
460 u16 devid;
461 u16 subvendorid;
462 u32 macVersion;
463 u16 macRev;
464 u16 phyRev;
465 u16 analog5GhzRev;
466 u16 analog2GhzRev;
0b5ead91 467 enum ath_usb_dev usbdev;
d535a42a 468};
394cf0a1 469
ff155a45
VT		 470/* Generic TSF timer definitions */
471
472#define ATH_MAX_GEN_TIMER 16
473
474#define AR_GENTMR_BIT(_index) (1 << (_index))
475
476/*
77c2061d 477 * Using de Bruijin sequence to look up 1's index in a 32 bit number
ff155a45
VT		 478 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
479 */
c90017dd 480#define debruijn32 0x077CB531U
ff155a45
VT		 481
482struct ath_gen_timer_configuration {
483 u32 next_addr;
484 u32 period_addr;
485 u32 mode_addr;
486 u32 mode_mask;
487};
488
489struct ath_gen_timer {
490 void (*trigger)(void *arg);
491 void (*overflow)(void *arg);
492 void *arg;
493 u8 index;
494};
495
496struct ath_gen_timer_table {
497 u32 gen_timer_index[32];
498 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
499 union {
500 unsigned long timer_bits;
501 u16 val;
502 } timer_mask;
503};
504
21cc630f
VT		 505struct ath_hw_antcomb_conf {
506 u8 main_lna_conf;
507 u8 alt_lna_conf;
508 u8 fast_div_bias;
c6ba9feb
MSS		 509 u8 main_gaintb;
510 u8 alt_gaintb;
511 int lna1_lna2_delta;
8afbcc8b 512 u8 div_group;
21cc630f
VT		 513};
514
4e8c14e9
FF		 515/**
516 * struct ath_hw_radar_conf - radar detection initialization parameters
517 *
518 * @pulse_inband: threshold for checking the ratio of in-band power
519 * to total power for short radar pulses (half dB steps)
520 * @pulse_inband_step: threshold for checking an in-band power to total
521 * power ratio increase for short radar pulses (half dB steps)
522 * @pulse_height: threshold for detecting the beginning of a short
523 * radar pulse (dB step)
524 * @pulse_rssi: threshold for detecting if a short radar pulse is
525 * gone (dB step)
526 * @pulse_maxlen: maximum pulse length (0.8 us steps)
527 *
528 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
529 * @radar_inband: threshold for checking the ratio of in-band power
530 * to total power for long radar pulses (half dB steps)
531 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
532 *
533 * @ext_channel: enable extension channel radar detection
534 */
535struct ath_hw_radar_conf {
536 unsigned int pulse_inband;
537 unsigned int pulse_inband_step;
538 unsigned int pulse_height;
539 unsigned int pulse_rssi;
540 unsigned int pulse_maxlen;
541
542 unsigned int radar_rssi;
543 unsigned int radar_inband;
544 int fir_power;
545
546 bool ext_channel;
547};
548
d70357d5
LR		 549/**
550 * struct ath_hw_private_ops - callbacks used internally by hardware code
551 *
552 * This structure contains private callbacks designed to only be used internally
553 * by the hardware core.
554 *
795f5e2c
LR		 555 * @init_cal_settings: setup types of calibrations supported
556 * @init_cal: starts actual calibration
557 *
d70357d5 558 * @init_mode_regs: Initializes mode registers
991312d8 559 * @init_mode_gain_regs: Initialize TX/RX gain registers
8fe65368
LR		 560 *
561 * @rf_set_freq: change frequency
562 * @spur_mitigate_freq: spur mitigation
563 * @rf_alloc_ext_banks:
564 * @rf_free_ext_banks:
565 * @set_rf_regs:
64773964
LR		 566 * @compute_pll_control: compute the PLL control value to use for
567 * AR_RTC_PLL_CONTROL for a given channel
795f5e2c
LR		 568 * @setup_calibration: set up calibration
569 * @iscal_supported: used to query if a type of calibration is supported
ac0bb767 570 *
e36b27af
LR		 571 * @ani_cache_ini_regs: cache the values for ANI from the initial
572 * register settings through the register initialization.
d70357d5
LR		 573 */
574struct ath_hw_private_ops {
795f5e2c 575 /* Calibration ops */
d70357d5 576 void (*init_cal_settings)(struct ath_hw *ah);
795f5e2c
LR		 577 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
578
d70357d5 579 void (*init_mode_regs)(struct ath_hw *ah);
991312d8 580 void (*init_mode_gain_regs)(struct ath_hw *ah);
795f5e2c
LR		 581 void (*setup_calibration)(struct ath_hw *ah,
582 struct ath9k_cal_list *currCal);
8fe65368
LR		 583
584 /* PHY ops */
585 int (*rf_set_freq)(struct ath_hw *ah,
586 struct ath9k_channel *chan);
587 void (*spur_mitigate_freq)(struct ath_hw *ah,
588 struct ath9k_channel *chan);
589 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
590 void (*rf_free_ext_banks)(struct ath_hw *ah);
591 bool (*set_rf_regs)(struct ath_hw *ah,
592 struct ath9k_channel *chan,
593 u16 modesIndex);
594 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
595 void (*init_bb)(struct ath_hw *ah,
596 struct ath9k_channel *chan);
597 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
598 void (*olc_init)(struct ath_hw *ah);
599 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
600 void (*mark_phy_inactive)(struct ath_hw *ah);
601 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
602 bool (*rfbus_req)(struct ath_hw *ah);
603 void (*rfbus_done)(struct ath_hw *ah);
8fe65368 604 void (*restore_chainmask)(struct ath_hw *ah);
64773964
LR		 605 u32 (*compute_pll_control)(struct ath_hw *ah,
606 struct ath9k_channel *chan);
c16fcb49
FF		 607 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
608 int param);
641d9921 609 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
4e8c14e9
FF		 610 void (*set_radar_params)(struct ath_hw *ah,
611 struct ath_hw_radar_conf *conf);
5f0c04ea
RM		 612 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
613 u8 *ini_reloaded);
ac0bb767
LR		 614
615 /* ANI */
e36b27af 616 void (*ani_cache_ini_regs)(struct ath_hw *ah);
d70357d5
LR		 617};
618
619/**
620 * struct ath_hw_ops - callbacks used by hardware code and driver code
621 *
622 * This structure contains callbacks designed to to be used internally by
623 * hardware code and also by the lower level driver.
624 *
625 * @config_pci_powersave:
795f5e2c 626 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
d70357d5
LR		 627 */
628struct ath_hw_ops {
629 void (*config_pci_powersave)(struct ath_hw *ah,
84c87dc8 630 bool power_off);
cee1f625 631 void (*rx_enable)(struct ath_hw *ah);
87d5efbb 632 void (*set_desc_link)(void *ds, u32 link);
795f5e2c
LR		 633 bool (*calibrate)(struct ath_hw *ah,
634 struct ath9k_channel *chan,
635 u8 rxchainmask,
636 bool longcal);
55e82df4 637 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
2b63a41d
FF		 638 void (*set_txdesc)(struct ath_hw *ah, void *ds,
639 struct ath_tx_info *i);
cc610ac0
VT		 640 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
641 struct ath_tx_status *ts);
69de3721
MSS		 642 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
643 struct ath_hw_antcomb_conf *antconf);
644 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
645 struct ath_hw_antcomb_conf *antconf);
646
d70357d5
LR		 647};
648
f2552e28
FF		 649struct ath_nf_limits {
650 s16 max;
651 s16 min;
652 s16 nominal;
653};
654
8ad74c4d
RM		 655enum ath_cal_list {
656 TX_IQ_CAL = BIT(0),
657 TX_IQ_ON_AGC_CAL = BIT(1),
658 TX_CL_CAL = BIT(2),
659};
660
97dcec57
SM		 661/* ah_flags */
662#define AH_USE_EEPROM 0x1
663#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
a126ff51 664#define AH_FASTCC 0x4
97dcec57 665
cbe61d8a 666struct ath_hw {
f9f84e96
FF		 667 struct ath_ops reg_ops;
668
b002a4a9 669 struct ieee80211_hw *hw;
27c51f1a 670 struct ath_common common;
cbe61d8a 671 struct ath9k_hw_version hw_version;
2660b81a
S		 672 struct ath9k_ops_config config;
673 struct ath9k_hw_capabilities caps;
cac4220b 674 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
2660b81a 675 struct ath9k_channel *curchan;
394cf0a1 676
cbe61d8a
S		 677 union {
678 struct ar5416_eeprom_def def;
679 struct ar5416_eeprom_4k map4k;
475f5989 680 struct ar9287_eeprom map9287;
15c9ee7a 681 struct ar9300_eeprom ar9300_eep;
2660b81a 682 } eeprom;
f74df6fb 683 const struct eeprom_ops *eep_ops;
cbe61d8a
S		 684
685 bool sw_mgmt_crypto;
2660b81a 686 bool is_pciexpress;
d4930086 687 bool aspm_enabled;
5f841b41 688 bool is_monitoring;
2eb46d9b 689 bool need_an_top2_fixup;
2660b81a 690 u16 tx_trig_level;
f2552e28 691
bbacee13 692 u32 nf_regs[6];
f2552e28
FF		 693 struct ath_nf_limits nf_2g;
694 struct ath_nf_limits nf_5g;
2660b81a
S		 695 u16 rfsilent;
696 u32 rfkill_gpio;
697 u32 rfkill_polarity;
cbe61d8a 698 u32 ah_flags;
394cf0a1 699
d7e7d229
LR		 700 bool htc_reset_init;
701
2660b81a
S		 702 enum nl80211_iftype opmode;
703 enum ath9k_power_mode power_mode;
f078f209 704
f23fba49 705 s8 noise;
20bd2a09 706 struct ath9k_hw_cal_data *caldata;
a13883b0 707 struct ath9k_pacal_info pacal_info;
2660b81a
S		 708 struct ar5416Stats stats;
709 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
710
3069168c 711 enum ath9k_int imask;
74bad5cb 712 u32 imrs2_reg;
2660b81a
S		 713 u32 txok_interrupt_mask;
714 u32 txerr_interrupt_mask;
715 u32 txdesc_interrupt_mask;
716 u32 txeol_interrupt_mask;
717 u32 txurn_interrupt_mask;
e8fe7336 718 atomic_t intr_ref_cnt;
2660b81a
S		 719 bool chip_fullsleep;
720 u32 atim_window;
5f0c04ea 721 u32 modes_index;
6a2b9e8c
S		 722
723 /* Calibration */
6497827f 724 u32 supp_cals;
cbfe9468
S		 725 struct ath9k_cal_list iq_caldata;
726 struct ath9k_cal_list adcgain_caldata;
cbfe9468 727 struct ath9k_cal_list adcdc_caldata;
df23acaa 728 struct ath9k_cal_list tempCompCalData;
cbfe9468
S		 729 struct ath9k_cal_list *cal_list;
730 struct ath9k_cal_list *cal_list_last;
731 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 732#define totalPowerMeasI meas0.unsign
733#define totalPowerMeasQ meas1.unsign
734#define totalIqCorrMeas meas2.sign
735#define totalAdcIOddPhase meas0.unsign
736#define totalAdcIEvenPhase meas1.unsign
737#define totalAdcQOddPhase meas2.unsign
738#define totalAdcQEvenPhase meas3.unsign
739#define totalAdcDcOffsetIOddPhase meas0.sign
740#define totalAdcDcOffsetIEvenPhase meas1.sign
741#define totalAdcDcOffsetQOddPhase meas2.sign
742#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 743 union {
744 u32 unsign[AR5416_MAX_CHAINS];
745 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 746 } meas0;
f078f209
LR		 747 union {
748 u32 unsign[AR5416_MAX_CHAINS];
749 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 750 } meas1;
f078f209
LR		 751 union {
752 u32 unsign[AR5416_MAX_CHAINS];
753 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 754 } meas2;
f078f209
LR		 755 union {
756 u32 unsign[AR5416_MAX_CHAINS];
757 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 758 } meas3;
759 u16 cal_samples;
8ad74c4d 760 u8 enabled_cals;
6a2b9e8c 761
2660b81a
S		 762 u32 sta_id1_defaults;
763 u32 misc_mode;
6a2b9e8c 764
d70357d5
LR		 765 /* Private to hardware code */
766 struct ath_hw_private_ops private_ops;
767 /* Accessed by the lower level driver */
768 struct ath_hw_ops ops;
769
e68a060b 770 /* Used to program the radio on non single-chip devices */
2660b81a
S		 771 u32 *analogBank0Data;
772 u32 *analogBank1Data;
773 u32 *analogBank2Data;
774 u32 *analogBank3Data;
775 u32 *analogBank6Data;
776 u32 *analogBank6TPCData;
777 u32 *analogBank7Data;
2660b81a
S		 778 u32 *bank6Temp;
779
e239d859 780 int coverage_class;
2660b81a 781 u32 slottime;
2660b81a 782 u32 globaltxtimeout;
6a2b9e8c
S		 783
784 /* ANI */
2660b81a 785 u32 proc_phyerr;
2660b81a 786 u32 aniperiod;
2660b81a
S		 787 int totalSizeDesired[5];
788 int coarse_high[5];
789 int coarse_low[5];
790 int firpwr[5];
791 enum ath9k_ani_cmd ani_function;
792
dbccdd1d 793#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
766ec4a9 794 struct ath_btcoex_hw btcoex_hw;
dbccdd1d 795#endif
af03abec 796
2660b81a 797 u32 intr_txqs;
2660b81a
S		 798 u8 txchainmask;
799 u8 rxchainmask;
800
c5d0855a
FF		 801 struct ath_hw_radar_conf radar_conf;
802
8bd1d07f
SB		 803 u32 originalGain[22];
804 int initPDADC;
805 int PDADCdelta;
6de66dd9 806 int led_pin;
691680b8
FF		 807 u32 gpio_mask;
808 u32 gpio_val;
8bd1d07f 809
2660b81a
S		 810 struct ar5416IniArray iniModes;
811 struct ar5416IniArray iniCommon;
812 struct ar5416IniArray iniBank0;
813 struct ar5416IniArray iniBB_RfGain;
814 struct ar5416IniArray iniBank1;
815 struct ar5416IniArray iniBank2;
816 struct ar5416IniArray iniBank3;
817 struct ar5416IniArray iniBank6;
818 struct ar5416IniArray iniBank6TPC;
819 struct ar5416IniArray iniBank7;
820 struct ar5416IniArray iniAddac;
821 struct ar5416IniArray iniPcieSerdes;
13ce3e99 822 struct ar5416IniArray iniPcieSerdesLowPower;
c7d36f9f
FF		 823 struct ar5416IniArray iniModesFastClock;
824 struct ar5416IniArray iniAdditional;
2660b81a
S		 825 struct ar5416IniArray iniModesRxGain;
826 struct ar5416IniArray iniModesTxGain;
193cd458
S		 827 struct ar5416IniArray iniCckfirNormal;
828 struct ar5416IniArray iniCckfirJapan2484;
ce407afc 829 struct ar5416IniArray ini_japan2484;
70807e99 830 struct ar5416IniArray iniModes_9271_ANI_reg;
ce407afc
SB		 831 struct ar5416IniArray ini_radio_post_sys2ant;
832 struct ar5416IniArray ini_BTCOEX_MAX_TXPWR;
ff155a45 833
13ce3e99
LR		 834 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
835 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
836 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
837 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
838
ff155a45
VT		 839 u32 intr_gen_timer_trigger;
840 u32 intr_gen_timer_thresh;
841 struct ath_gen_timer_table hw_gen_timers;
744d4025
VT		 842
843 struct ar9003_txs *ts_ring;
744d4025
VT		 844 u32 ts_paddr_start;
845 u32 ts_paddr_end;
846 u16 ts_tail;
016c2177 847 u16 ts_size;
aea702b7
LR		 848
849 u32 bb_watchdog_last_status;
850 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
51ac8cbb 851 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
717f6bed 852
1bf38661
FF		 853 unsigned int paprd_target_power;
854 unsigned int paprd_training_power;
7072bf62 855 unsigned int paprd_ratemask;
f1a8abb0 856 unsigned int paprd_ratemask_ht40;
45ef6a0b 857 bool paprd_table_write_done;
717f6bed
FF		 858 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
859 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
9a658d2b
LR		 860 /*
861 * Store the permanent value of Reg 0x4004in WARegVal
862 * so we dont have to R/M/W. We should not be reading
863 * this register when in sleep states.
864 */
865 u32 WARegVal;
6ee63f55
SB		 866
867 /* Enterprise mode cap */
868 u32 ent_mode;
f2f5f2a1
VT		 869
870 bool is_clk_25mhz;
3762561a 871 int (*get_mac_revision)(void);
7d95847c 872 int (*external_reset)(void);
f078f209 873};
f078f209 874
0cb9e06b
FF		 875struct ath_bus_ops {
876 enum ath_bus_type ath_bus_type;
877 void (*read_cachesize)(struct ath_common *common, int *csz);
878 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
879 void (*bt_coex_prep)(struct ath_common *common);
880 void (*extn_synch_en)(struct ath_common *common);
d4930086 881 void (*aspm_init)(struct ath_common *common);
0cb9e06b
FF		 882};
883
9e4bffd2
LR		 884static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
885{
886 return &ah->common;
887}
888
889static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
890{
891 return &(ath9k_hw_common(ah)->regulatory);
892}
893
d70357d5
LR		 894static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
895{
896 return &ah->private_ops;
897}
898
899static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
900{
901 return &ah->ops;
902}
903
895ad7eb
VT		 904static inline u8 get_streams(int mask)
905{
906 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
907}
908
f637cfd6 909/* Initialization, Detach, Reset */
285f2dda 910void ath9k_hw_deinit(struct ath_hw *ah);
f637cfd6 911int ath9k_hw_init(struct ath_hw *ah);
cbe61d8a 912int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 913 struct ath9k_hw_cal_data *caldata, bool fastcc);
a9a29ce6 914int ath9k_hw_fill_cap_info(struct ath_hw *ah);
8fe65368 915u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
394cf0a1 916
394cf0a1 917/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 918void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
919u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
920void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 921 u32 ah_signal_type);
cbe61d8a 922void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a 923void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
394cf0a1
S		 924
925/* General Operation */
0caa7b14 926bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
a9b6b256
FF		 927void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
928 int column, unsigned int *writecnt);
394cf0a1 929u32 ath9k_hw_reverse_bits(u32 val, u32 n);
4f0fc7c3 930u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 931 u8 phy, int kbps,
394cf0a1 932 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 933void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 934 struct ath9k_channel *chan,
935 struct chan_centers *centers);
cbe61d8a
S		 936u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
937void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
938bool ath9k_hw_phy_disable(struct ath_hw *ah);
939bool ath9k_hw_disable(struct ath_hw *ah);
de40f316 940void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
cbe61d8a
S		 941void ath9k_hw_setopmode(struct ath_hw *ah);
942void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e 943void ath9k_hw_write_associd(struct ath_hw *ah);
dd347f2f 944u32 ath9k_hw_gettsf32(struct ath_hw *ah);
cbe61d8a
S		 945u64 ath9k_hw_gettsf64(struct ath_hw *ah);
946void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
947void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 948void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
0005baf4 949void ath9k_hw_init_global_settings(struct ath_hw *ah);
b84628eb 950u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
25c56eec 951void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 952void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
953void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 954 const struct ath9k_beacon_state *bs);
c9c99e5e 955bool ath9k_hw_check_alive(struct ath_hw *ah);
a91d75ae 956
9ecdef4b 957bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 958
462e58f2
BG		 959#ifdef CONFIG_ATH9K_DEBUGFS
960void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause);
961#else
962static void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause) {}
963#endif
964
ff155a45
VT		 965/* Generic hw timer primitives */
966struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
967 void (*trigger)(void *),
968 void (*overflow)(void *),
969 void *arg,
970 u8 timer_index);
cd9bf689
LR		 971void ath9k_hw_gen_timer_start(struct ath_hw *ah,
972 struct ath_gen_timer *timer,
973 u32 timer_next,
974 u32 timer_period);
975void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
976
ff155a45
VT		 977void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
978void ath_gen_timer_isr(struct ath_hw *hw);
979
f934c4d9 980void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
2da4f01a 981
8fe65368
LR		 982/* PHY */
983void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
984 u32 *coef_mantissa, u32 *coef_exponent);
ca2c68cc 985void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan);
8fe65368 986
ebd5a14a
LR		 987/*
988 * Code Specific to AR5008, AR9001 or AR9002,
989 * we stuff these here to avoid callbacks for AR9003.
990 */
ebd5a14a 991int ar9002_hw_rf_claim(struct ath_hw *ah);
78ec2677 992void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
d8f492b7 993
641d9921 994/*
aea702b7 995 * Code specific to AR9003, we stuff these here to avoid callbacks
641d9921
FF		 996 * for older families
997 */
aea702b7
LR		 998void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
999void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1000void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
51ac8cbb 1001void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
717f6bed
FF		 1002void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1003void ar9003_paprd_populate_single_table(struct ath_hw *ah,
20bd2a09
FF		 1004 struct ath9k_hw_cal_data *caldata,
1005 int chain);
1006int ar9003_paprd_create_curve(struct ath_hw *ah,
1007 struct ath9k_hw_cal_data *caldata, int chain);
717f6bed
FF		 1008int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1009int ar9003_paprd_init_table(struct ath_hw *ah);
1010bool ar9003_paprd_is_done(struct ath_hw *ah);
641d9921
FF		 1011
1012/* Hardware family op attach helpers */
8fe65368 1013void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
8525f280
LR		 1014void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1015void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
8fe65368 1016
795f5e2c
LR		 1017void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1018void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1019
b3950e6a
LR		 1020void ar9002_hw_attach_ops(struct ath_hw *ah);
1021void ar9003_hw_attach_ops(struct ath_hw *ah);
1022
c2ba3342 1023void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767
LR		 1024/*
1025 * ANI work can be shared between all families but a next
1026 * generation implementation of ANI will be used only for AR9003 only
1027 * for now as the other families still need to be tested with the same
e36b27af
LR		 1028 * next generation ANI. Feel free to start testing it though for the
1029 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
ac0bb767 1030 */
e36b27af 1031extern int modparam_force_new_ani;
8eb4980c 1032void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
bfc472bb 1033void ath9k_hw_proc_mib_event(struct ath_hw *ah);
95792178 1034void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767 1035
8a309305 1036#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
dbccdd1d
SM		 1037static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1038{
1039 return ah->btcoex_hw.enabled;
1040}
1041void ath9k_hw_btcoex_enable(struct ath_hw *ah);
8a309305
FF		 1042static inline enum ath_btcoex_scheme
1043ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1044{
1045 return ah->btcoex_hw.scheme;
1046}
1047#else
dbccdd1d
SM		 1048static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1049{
1050 return false;
1051}
1052static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1053{
1054}
1055static inline enum ath_btcoex_scheme
1056ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1057{
1058 return ATH_BTCOEX_CFG_NONE;
1059}
64ab38df 1060#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
8a309305 1061
73377256
LR		 1062#define ATH9K_CLOCK_RATE_CCK 22
1063#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1064#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1065#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1066
f078f209 1067#endif
Linux kernel - Deliverables
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