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ath9k: Add support for AR9287 based chipsets.
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.h
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
30
203c4805 31#include "../regd.h"
3a702e49 32
394cf0a1
S		 33#define ATHEROS_VENDOR_ID 0x168c
34#define AR5416_DEVID_PCI 0x0023
35#define AR5416_DEVID_PCIE 0x0024
36#define AR9160_DEVID_PCI 0x0027
37#define AR9280_DEVID_PCI 0x0029
38#define AR9280_DEVID_PCIE 0x002a
39#define AR9285_DEVID_PCIE 0x002b
40#define AR5416_AR9100_DEVID 0x000b
41#define AR_SUBVENDOR_ID_NOG 0x0e11
42#define AR_SUBVENDOR_ID_NEW_A 0x7065
43#define AR5416_MAGIC 0x19641014
44
ac88b6ec
VN		 45#define AR5416_DEVID_AR9287_PCI 0x002D
46#define AR5416_DEVID_AR9287_PCIE 0x002E
47
394cf0a1 48/* Register read/write primitives */
2d6a5e95
DM		 49#define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val))
50#define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg))
394cf0a1
S		 51
52#define SM(_v, _f) (((_v) << _f##_S) & _f)
53#define MS(_v, _f) (((_v) & _f) >> _f##_S)
54#define REG_RMW(_a, _r, _set, _clr) \
55 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
56#define REG_RMW_FIELD(_a, _r, _f, _v) \
57 REG_WRITE(_a, _r, \
58 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
59#define REG_SET_BIT(_a, _r, _f) \
60 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
61#define REG_CLR_BIT(_a, _r, _f) \
62 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 63
394cf0a1
S		 64#define DO_DELAY(x) do { \
65 if ((++(x) % 64) == 0) \
66 udelay(1); \
67 } while (0)
f078f209 68
394cf0a1
S		 69#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
70 int r; \
71 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
72 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
73 INI_RA((iniarray), r, (column))); \
74 DO_DELAY(regWr); \
75 } \
76 } while (0)
f078f209 77
394cf0a1
S		 78#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
79#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
80#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
81#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
82#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
83#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 84
394cf0a1
S		 85#define AR_GPIOD_MASK 0x00001FFF
86#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 87
394cf0a1
S		 88#define BASE_ACTIVATE_DELAY 100
89#define RTC_PLL_SETTLE_DELAY 1000
90#define COEF_SCALE_S 24
91#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 92
394cf0a1
S		 93#define ATH9K_ANTENNA0_CHAINMASK 0x1
94#define ATH9K_ANTENNA1_CHAINMASK 0x2
95
96#define ATH9K_NUM_DMA_DEBUG_REGS 8
97#define ATH9K_NUM_QUEUES 10
98
99#define MAX_RATE_POWER 63
0caa7b14 100#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 101#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 102#define AH_TIME_QUANTUM 10
103#define AR_KEYTABLE_SIZE 128
104#define POWER_UP_TIME 200000
105#define SPUR_RSSI_THRESH 40
106
107#define CAB_TIMEOUT_VAL 10
108#define BEACON_TIMEOUT_VAL 10
109#define MIN_BEACON_TIMEOUT_VAL 1
110#define SLEEP_SLOP 3
111
112#define INIT_CONFIG_STATUS 0x00000000
113#define INIT_RSSI_THR 0x00000700
114#define INIT_BCON_CNTRL_REG 0x00000000
115
116#define TU_TO_USEC(_tu) ((_tu) << 10)
117
118enum wireless_mode {
119 ATH9K_MODE_11A = 0,
b9b6e15a
LR		 120 ATH9K_MODE_11G,
121 ATH9K_MODE_11NA_HT20,
122 ATH9K_MODE_11NG_HT20,
123 ATH9K_MODE_11NA_HT40PLUS,
124 ATH9K_MODE_11NA_HT40MINUS,
125 ATH9K_MODE_11NG_HT40PLUS,
126 ATH9K_MODE_11NG_HT40MINUS,
127 ATH9K_MODE_MAX,
394cf0a1 128};
f078f209 129
394cf0a1 130enum ath9k_hw_caps {
bdbdf46d
S		 131 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
132 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
133 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
134 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
135 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
136 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
137 ATH9K_HW_CAP_VEOL = BIT(6),
138 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
139 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
140 ATH9K_HW_CAP_HT = BIT(9),
141 ATH9K_HW_CAP_GTT = BIT(10),
142 ATH9K_HW_CAP_FASTCC = BIT(11),
143 ATH9K_HW_CAP_RFSILENT = BIT(12),
144 ATH9K_HW_CAP_CST = BIT(13),
145 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
146 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
147 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
148 ATH9K_HW_CAP_BT_COEX = BIT(17)
394cf0a1 149};
f078f209 150
394cf0a1
S		 151enum ath9k_capability_type {
152 ATH9K_CAP_CIPHER = 0,
153 ATH9K_CAP_TKIP_MIC,
154 ATH9K_CAP_TKIP_SPLIT,
394cf0a1
S		 155 ATH9K_CAP_DIVERSITY,
156 ATH9K_CAP_TXPOW,
394cf0a1 157 ATH9K_CAP_MCAST_KEYSRCH,
8bd1d07f 158 ATH9K_CAP_DS
394cf0a1 159};
f078f209 160
394cf0a1
S		 161struct ath9k_hw_capabilities {
162 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
163 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
164 u16 total_queues;
165 u16 keycache_size;
166 u16 low_5ghz_chan, high_5ghz_chan;
167 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 168 u16 rts_aggr_limit;
169 u8 tx_chainmask;
170 u8 rx_chainmask;
171 u16 tx_triglevel_max;
172 u16 reg_cap;
173 u8 num_gpio_pins;
174 u8 num_antcfg_2ghz;
175 u8 num_antcfg_5ghz;
176};
f078f209 177
394cf0a1
S		 178struct ath9k_ops_config {
179 int dma_beacon_response_time;
180 int sw_beacon_response_time;
181 int additional_swba_backoff;
182 int ack_6mb;
183 int cwm_ignore_extcca;
184 u8 pcie_powersave_enable;
394cf0a1
S		 185 u8 pcie_clock_req;
186 u32 pcie_waen;
394cf0a1
S		 187 u8 analog_shiftreg;
188 u8 ht_enable;
189 u32 ofdm_trig_low;
190 u32 ofdm_trig_high;
191 u32 cck_trig_high;
192 u32 cck_trig_low;
193 u32 enable_ani;
394cf0a1
S		 194 u16 diversity_control;
195 u16 antenna_switch_swap;
196 int serialize_regmode;
0ef1f168 197 bool intr_mitigation;
394cf0a1
S		 198#define SPUR_DISABLE 0
199#define SPUR_ENABLE_IOCTL 1
200#define SPUR_ENABLE_EEPROM 2
201#define AR_EEPROM_MODAL_SPURS 5
202#define AR_SPUR_5413_1 1640
203#define AR_SPUR_5413_2 1200
204#define AR_NO_SPUR 0x8000
205#define AR_BASE_FREQ_2GHZ 2300
206#define AR_BASE_FREQ_5GHZ 4900
207#define AR_SPUR_FEEQ_BOUND_HT40 19
208#define AR_SPUR_FEEQ_BOUND_HT20 10
209 int spurmode;
210 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
211};
f078f209 212
394cf0a1
S		 213enum ath9k_int {
214 ATH9K_INT_RX = 0x00000001,
215 ATH9K_INT_RXDESC = 0x00000002,
216 ATH9K_INT_RXNOFRM = 0x00000008,
217 ATH9K_INT_RXEOL = 0x00000010,
218 ATH9K_INT_RXORN = 0x00000020,
219 ATH9K_INT_TX = 0x00000040,
220 ATH9K_INT_TXDESC = 0x00000080,
221 ATH9K_INT_TIM_TIMER = 0x00000100,
222 ATH9K_INT_TXURN = 0x00000800,
223 ATH9K_INT_MIB = 0x00001000,
224 ATH9K_INT_RXPHY = 0x00004000,
225 ATH9K_INT_RXKCM = 0x00008000,
226 ATH9K_INT_SWBA = 0x00010000,
227 ATH9K_INT_BMISS = 0x00040000,
228 ATH9K_INT_BNR = 0x00100000,
229 ATH9K_INT_TIM = 0x00200000,
230 ATH9K_INT_DTIM = 0x00400000,
231 ATH9K_INT_DTIMSYNC = 0x00800000,
232 ATH9K_INT_GPIO = 0x01000000,
233 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 234 ATH9K_INT_TSFOOR = 0x04000000,
394cf0a1
S		 235 ATH9K_INT_CST = 0x10000000,
236 ATH9K_INT_GTT = 0x20000000,
237 ATH9K_INT_FATAL = 0x40000000,
238 ATH9K_INT_GLOBAL = 0x80000000,
239 ATH9K_INT_BMISC = ATH9K_INT_TIM |
240 ATH9K_INT_DTIM |
241 ATH9K_INT_DTIMSYNC |
4af9cf4f 242 ATH9K_INT_TSFOOR |
394cf0a1
S		 243 ATH9K_INT_CABEND,
244 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
245 ATH9K_INT_RXDESC |
246 ATH9K_INT_RXEOL |
247 ATH9K_INT_RXORN |
248 ATH9K_INT_TXURN |
249 ATH9K_INT_TXDESC |
250 ATH9K_INT_MIB |
251 ATH9K_INT_RXPHY |
252 ATH9K_INT_RXKCM |
253 ATH9K_INT_SWBA |
254 ATH9K_INT_BMISS |
255 ATH9K_INT_GPIO,
256 ATH9K_INT_NOCARD = 0xffffffff
257};
f078f209 258
394cf0a1
S		 259#define CHANNEL_CW_INT 0x00002
260#define CHANNEL_CCK 0x00020
261#define CHANNEL_OFDM 0x00040
262#define CHANNEL_2GHZ 0x00080
263#define CHANNEL_5GHZ 0x00100
264#define CHANNEL_PASSIVE 0x00200
265#define CHANNEL_DYN 0x00400
266#define CHANNEL_HALF 0x04000
267#define CHANNEL_QUARTER 0x08000
268#define CHANNEL_HT20 0x10000
269#define CHANNEL_HT40PLUS 0x20000
270#define CHANNEL_HT40MINUS 0x40000
271
394cf0a1
S		 272#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
273#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
274#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
275#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
276#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
277#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
278#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
279#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
280#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
281#define CHANNEL_ALL \
282 (CHANNEL_OFDM| \
283 CHANNEL_CCK| \
284 CHANNEL_2GHZ | \
285 CHANNEL_5GHZ | \
286 CHANNEL_HT20 | \
287 CHANNEL_HT40PLUS | \
288 CHANNEL_HT40MINUS)
289
290struct ath9k_channel {
291 struct ieee80211_channel *chan;
292 u16 channel;
293 u32 channelFlags;
294 u32 chanmode;
295 int32_t CalValid;
296 bool oneTimeCalsDone;
297 int8_t iCoff;
298 int8_t qCoff;
299 int16_t rawNoiseFloor;
300};
f078f209 301
394cf0a1
S		 302#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
303 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
304 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
305 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
306#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
307#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
308#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 309#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
310#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
311#define IS_CHAN_A_5MHZ_SPACED(_c) \
312 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
313 (((_c)->channel % 20) != 0) && \
314 (((_c)->channel % 10) != 0))
315
316/* These macros check chanmode and not channelFlags */
317#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
318#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
319 ((_c)->chanmode == CHANNEL_G_HT20))
320#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
321 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
322 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
323 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
324#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
325
326enum ath9k_power_mode {
327 ATH9K_PM_AWAKE = 0,
328 ATH9K_PM_FULL_SLEEP,
329 ATH9K_PM_NETWORK_SLEEP,
330 ATH9K_PM_UNDEFINED
331};
f078f209 332
394cf0a1
S		 333enum ath9k_ant_setting {
334 ATH9K_ANT_VARIABLE = 0,
335 ATH9K_ANT_FIXED_A,
336 ATH9K_ANT_FIXED_B
337};
f078f209 338
394cf0a1
S		 339enum ath9k_tp_scale {
340 ATH9K_TP_SCALE_MAX = 0,
341 ATH9K_TP_SCALE_50,
342 ATH9K_TP_SCALE_25,
343 ATH9K_TP_SCALE_12,
344 ATH9K_TP_SCALE_MIN
345};
f078f209 346
394cf0a1
S		 347enum ser_reg_mode {
348 SER_REG_MODE_OFF = 0,
349 SER_REG_MODE_ON = 1,
350 SER_REG_MODE_AUTO = 2,
351};
f078f209 352
394cf0a1
S		 353struct ath9k_beacon_state {
354 u32 bs_nexttbtt;
355 u32 bs_nextdtim;
356 u32 bs_intval;
357#define ATH9K_BEACON_PERIOD 0x0000ffff
358#define ATH9K_BEACON_ENA 0x00800000
359#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 360#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 361 u32 bs_dtimperiod;
362 u16 bs_cfpperiod;
363 u16 bs_cfpmaxduration;
364 u32 bs_cfpnext;
365 u16 bs_timoffset;
366 u16 bs_bmissthreshold;
367 u32 bs_sleepduration;
4af9cf4f 368 u32 bs_tsfoor_threshold;
394cf0a1 369};
f078f209 370
394cf0a1
S		 371struct chan_centers {
372 u16 synth_center;
373 u16 ctl_center;
374 u16 ext_center;
375};
f078f209 376
394cf0a1
S		 377enum {
378 ATH9K_RESET_POWER_ON,
379 ATH9K_RESET_WARM,
380 ATH9K_RESET_COLD,
381};
f078f209 382
d535a42a
S		 383struct ath9k_hw_version {
384 u32 magic;
385 u16 devid;
386 u16 subvendorid;
387 u32 macVersion;
388 u16 macRev;
389 u16 phyRev;
390 u16 analog5GhzRev;
391 u16 analog2GhzRev;
392};
394cf0a1 393
cbe61d8a 394struct ath_hw {
394cf0a1 395 struct ath_softc *ah_sc;
cbe61d8a 396 struct ath9k_hw_version hw_version;
2660b81a
S		 397 struct ath9k_ops_config config;
398 struct ath9k_hw_capabilities caps;
3a702e49 399 struct ath_regulatory regulatory;
2660b81a
S		 400 struct ath9k_channel channels[38];
401 struct ath9k_channel *curchan;
394cf0a1 402
cbe61d8a
S		 403 union {
404 struct ar5416_eeprom_def def;
405 struct ar5416_eeprom_4k map4k;
ac88b6ec 406 struct ar9287_eeprom_t map9287;
2660b81a 407 } eeprom;
f74df6fb 408 const struct eeprom_ops *eep_ops;
2660b81a 409 enum ath9k_eep_map eep_map;
cbe61d8a
S		 410
411 bool sw_mgmt_crypto;
2660b81a 412 bool is_pciexpress;
cbe61d8a 413 u8 macaddr[ETH_ALEN];
2660b81a
S		 414 u16 tx_trig_level;
415 u16 rfsilent;
416 u32 rfkill_gpio;
417 u32 rfkill_polarity;
418 u32 btactive_gpio;
419 u32 wlanactive_gpio;
cbe61d8a 420 u32 ah_flags;
394cf0a1 421
2660b81a
S		 422 enum nl80211_iftype opmode;
423 enum ath9k_power_mode power_mode;
424 enum ath9k_power_mode restore_mode;
f078f209 425
cbe61d8a 426 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
2660b81a
S		 427 struct ar5416Stats stats;
428 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
429
430 int16_t curchan_rad_index;
431 u32 mask_reg;
432 u32 txok_interrupt_mask;
433 u32 txerr_interrupt_mask;
434 u32 txdesc_interrupt_mask;
435 u32 txeol_interrupt_mask;
436 u32 txurn_interrupt_mask;
437 bool chip_fullsleep;
438 u32 atim_window;
439 u16 antenna_switch_swap;
440 enum ath9k_ant_setting diversity_control;
6a2b9e8c
S		 441
442 /* Calibration */
cbfe9468
S		 443 enum ath9k_cal_types supp_cals;
444 struct ath9k_cal_list iq_caldata;
445 struct ath9k_cal_list adcgain_caldata;
446 struct ath9k_cal_list adcdc_calinitdata;
447 struct ath9k_cal_list adcdc_caldata;
448 struct ath9k_cal_list *cal_list;
449 struct ath9k_cal_list *cal_list_last;
450 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 451#define totalPowerMeasI meas0.unsign
452#define totalPowerMeasQ meas1.unsign
453#define totalIqCorrMeas meas2.sign
454#define totalAdcIOddPhase meas0.unsign
455#define totalAdcIEvenPhase meas1.unsign
456#define totalAdcQOddPhase meas2.unsign
457#define totalAdcQEvenPhase meas3.unsign
458#define totalAdcDcOffsetIOddPhase meas0.sign
459#define totalAdcDcOffsetIEvenPhase meas1.sign
460#define totalAdcDcOffsetQOddPhase meas2.sign
461#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 462 union {
463 u32 unsign[AR5416_MAX_CHAINS];
464 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 465 } meas0;
f078f209
LR		 466 union {
467 u32 unsign[AR5416_MAX_CHAINS];
468 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 469 } meas1;
f078f209
LR		 470 union {
471 u32 unsign[AR5416_MAX_CHAINS];
472 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 473 } meas2;
f078f209
LR		 474 union {
475 u32 unsign[AR5416_MAX_CHAINS];
476 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 477 } meas3;
478 u16 cal_samples;
6a2b9e8c 479
2660b81a
S		 480 u32 sta_id1_defaults;
481 u32 misc_mode;
f078f209
LR		 482 enum {
483 AUTO_32KHZ,
484 USE_32KHZ,
485 DONT_USE_32KHZ,
2660b81a 486 } enable_32kHz_clock;
6a2b9e8c
S		 487
488 /* RF */
2660b81a
S		 489 u32 *analogBank0Data;
490 u32 *analogBank1Data;
491 u32 *analogBank2Data;
492 u32 *analogBank3Data;
493 u32 *analogBank6Data;
494 u32 *analogBank6TPCData;
495 u32 *analogBank7Data;
496 u32 *addac5416_21;
497 u32 *bank6Temp;
498
499 int16_t txpower_indexoffset;
500 u32 beacon_interval;
501 u32 slottime;
502 u32 acktimeout;
503 u32 ctstimeout;
504 u32 globaltxtimeout;
505 u8 gbeacon_rate;
6a2b9e8c
S		 506
507 /* ANI */
2660b81a
S		 508 u32 proc_phyerr;
509 bool has_hw_phycounters;
510 u32 aniperiod;
511 struct ar5416AniState *curani;
512 struct ar5416AniState ani[255];
513 int totalSizeDesired[5];
514 int coarse_high[5];
515 int coarse_low[5];
516 int firpwr[5];
517 enum ath9k_ani_cmd ani_function;
518
519 u32 intr_txqs;
2660b81a
S		 520 enum ath9k_ht_extprotspacing extprotspacing;
521 u8 txchainmask;
522 u8 rxchainmask;
523
8bd1d07f
SB		 524 u32 originalGain[22];
525 int initPDADC;
526 int PDADCdelta;
527
2660b81a
S		 528 struct ar5416IniArray iniModes;
529 struct ar5416IniArray iniCommon;
530 struct ar5416IniArray iniBank0;
531 struct ar5416IniArray iniBB_RfGain;
532 struct ar5416IniArray iniBank1;
533 struct ar5416IniArray iniBank2;
534 struct ar5416IniArray iniBank3;
535 struct ar5416IniArray iniBank6;
536 struct ar5416IniArray iniBank6TPC;
537 struct ar5416IniArray iniBank7;
538 struct ar5416IniArray iniAddac;
539 struct ar5416IniArray iniPcieSerdes;
540 struct ar5416IniArray iniModesAdditional;
541 struct ar5416IniArray iniModesRxGain;
542 struct ar5416IniArray iniModesTxGain;
f078f209 543};
f078f209 544
394cf0a1
S		 545/* Attach, Detach, Reset */
546const char *ath9k_hw_probe(u16 vendorid, u16 devid);
cbe61d8a
S		 547void ath9k_hw_detach(struct ath_hw *ah);
548struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error);
549void ath9k_hw_rfdetach(struct ath_hw *ah);
550int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
394cf0a1 551 bool bChannelChange);
eef7a574 552void ath9k_hw_fill_cap_info(struct ath_hw *ah);
cbe61d8a 553bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1 554 u32 capability, u32 *result);
cbe61d8a 555bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1
S		 556 u32 capability, u32 setting, int *status);
557
558/* Key Cache Management */
cbe61d8a
S		 559bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
560bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
561bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
394cf0a1 562 const struct ath9k_keyval *k,
e0caf9ea 563 const u8 *mac);
cbe61d8a 564bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
394cf0a1
S		 565
566/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 567void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
568u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
569void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 570 u32 ah_signal_type);
cbe61d8a 571void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 572u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
573void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
574bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
394cf0a1
S		 575 enum ath9k_ant_setting settings,
576 struct ath9k_channel *chan,
577 u8 *tx_chainmask, u8 *rx_chainmask,
578 u8 *antenna_cfgd);
579
580/* General Operation */
0caa7b14 581bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 582u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a 583bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
4f0fc7c3
LR		 584u16 ath9k_hw_computetxtime(struct ath_hw *ah,
585 const struct ath_rate_table *rates,
394cf0a1 586 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 587void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 588 struct ath9k_channel *chan,
589 struct chan_centers *centers);
cbe61d8a
S		 590u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
591void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
592bool ath9k_hw_phy_disable(struct ath_hw *ah);
593bool ath9k_hw_disable(struct ath_hw *ah);
8fbff4b8 594void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
cbe61d8a
S		 595void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
596void ath9k_hw_setopmode(struct ath_hw *ah);
597void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
ba52da58
S		 598void ath9k_hw_setbssidmask(struct ath_softc *sc);
599void ath9k_hw_write_associd(struct ath_softc *sc);
cbe61d8a
S		 600u64 ath9k_hw_gettsf64(struct ath_hw *ah);
601void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
602void ath9k_hw_reset_tsf(struct ath_hw *ah);
603bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
604bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
605void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
606void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
607void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 608 const struct ath9k_beacon_state *bs);
cbe61d8a 609bool ath9k_hw_setpower(struct ath_hw *ah,
394cf0a1 610 enum ath9k_power_mode mode);
cbe61d8a 611void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore);
394cf0a1
S		 612
613/* Interrupt Handling */
cbe61d8a
S		 614bool ath9k_hw_intrpend(struct ath_hw *ah);
615bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
616enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah);
617enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
394cf0a1 618
cbe61d8a 619void ath9k_hw_btcoex_enable(struct ath_hw *ah);
f078f209
LR		 620
621#endif
Linux kernel - Deliverables
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