Commit | Line | Data |
---|---|---|
55624204 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
55624204 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
516304b0 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
b7f080cf | 19 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
6fb1b1e1 | 21 | #include <linux/ath9k_platform.h> |
9d9779e7 | 22 | #include <linux/module.h> |
e93d083f | 23 | #include <linux/relay.h> |
b0a1ae97 | 24 | #include <net/ieee80211_radiotap.h> |
5a0e3ad6 | 25 | |
55624204 S |
26 | #include "ath9k.h" |
27 | ||
ab5c4f71 GJ |
28 | struct ath9k_eeprom_ctx { |
29 | struct completion complete; | |
30 | struct ath_hw *ah; | |
31 | }; | |
32 | ||
55624204 S |
33 | static char *dev_info = "ath9k"; |
34 | ||
35 | MODULE_AUTHOR("Atheros Communications"); | |
36 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
37 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
38 | MODULE_LICENSE("Dual BSD/GPL"); | |
39 | ||
40 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
41 | module_param_named(debug, ath9k_debug, uint, 0); | |
42 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
43 | ||
3e6109c5 JL |
44 | int ath9k_modparam_nohwcrypt; |
45 | module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); | |
55624204 S |
46 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); |
47 | ||
93dbbcc4 | 48 | int led_blink; |
9a75c2ff VN |
49 | module_param_named(blink, led_blink, int, 0444); |
50 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); | |
51 | ||
8f5dcb1c VT |
52 | static int ath9k_btcoex_enable; |
53 | module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); | |
54 | MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); | |
55 | ||
63081305 SM |
56 | static int ath9k_bt_ant_diversity; |
57 | module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); | |
58 | MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); | |
e09f2dc7 | 59 | |
d584747b | 60 | bool is_ath9k_unloaded; |
55624204 S |
61 | /* We use the hw_value as an index into our private channel structure */ |
62 | ||
63 | #define CHAN2G(_freq, _idx) { \ | |
b1c1d000 | 64 | .band = IEEE80211_BAND_2GHZ, \ |
55624204 S |
65 | .center_freq = (_freq), \ |
66 | .hw_value = (_idx), \ | |
67 | .max_power = 20, \ | |
68 | } | |
69 | ||
70 | #define CHAN5G(_freq, _idx) { \ | |
71 | .band = IEEE80211_BAND_5GHZ, \ | |
72 | .center_freq = (_freq), \ | |
73 | .hw_value = (_idx), \ | |
74 | .max_power = 20, \ | |
75 | } | |
76 | ||
77 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
78 | * on 5 MHz steps, we support the channels which we know | |
79 | * we have calibration data for all cards though to make | |
80 | * this static */ | |
f209f529 | 81 | static const struct ieee80211_channel ath9k_2ghz_chantable[] = { |
55624204 S |
82 | CHAN2G(2412, 0), /* Channel 1 */ |
83 | CHAN2G(2417, 1), /* Channel 2 */ | |
84 | CHAN2G(2422, 2), /* Channel 3 */ | |
85 | CHAN2G(2427, 3), /* Channel 4 */ | |
86 | CHAN2G(2432, 4), /* Channel 5 */ | |
87 | CHAN2G(2437, 5), /* Channel 6 */ | |
88 | CHAN2G(2442, 6), /* Channel 7 */ | |
89 | CHAN2G(2447, 7), /* Channel 8 */ | |
90 | CHAN2G(2452, 8), /* Channel 9 */ | |
91 | CHAN2G(2457, 9), /* Channel 10 */ | |
92 | CHAN2G(2462, 10), /* Channel 11 */ | |
93 | CHAN2G(2467, 11), /* Channel 12 */ | |
94 | CHAN2G(2472, 12), /* Channel 13 */ | |
95 | CHAN2G(2484, 13), /* Channel 14 */ | |
96 | }; | |
97 | ||
98 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
99 | * on 5 MHz steps, we support the channels which we know | |
100 | * we have calibration data for all cards though to make | |
101 | * this static */ | |
f209f529 | 102 | static const struct ieee80211_channel ath9k_5ghz_chantable[] = { |
55624204 S |
103 | /* _We_ call this UNII 1 */ |
104 | CHAN5G(5180, 14), /* Channel 36 */ | |
105 | CHAN5G(5200, 15), /* Channel 40 */ | |
106 | CHAN5G(5220, 16), /* Channel 44 */ | |
107 | CHAN5G(5240, 17), /* Channel 48 */ | |
108 | /* _We_ call this UNII 2 */ | |
109 | CHAN5G(5260, 18), /* Channel 52 */ | |
110 | CHAN5G(5280, 19), /* Channel 56 */ | |
111 | CHAN5G(5300, 20), /* Channel 60 */ | |
112 | CHAN5G(5320, 21), /* Channel 64 */ | |
113 | /* _We_ call this "Middle band" */ | |
114 | CHAN5G(5500, 22), /* Channel 100 */ | |
115 | CHAN5G(5520, 23), /* Channel 104 */ | |
116 | CHAN5G(5540, 24), /* Channel 108 */ | |
117 | CHAN5G(5560, 25), /* Channel 112 */ | |
118 | CHAN5G(5580, 26), /* Channel 116 */ | |
119 | CHAN5G(5600, 27), /* Channel 120 */ | |
120 | CHAN5G(5620, 28), /* Channel 124 */ | |
121 | CHAN5G(5640, 29), /* Channel 128 */ | |
122 | CHAN5G(5660, 30), /* Channel 132 */ | |
123 | CHAN5G(5680, 31), /* Channel 136 */ | |
124 | CHAN5G(5700, 32), /* Channel 140 */ | |
125 | /* _We_ call this UNII 3 */ | |
126 | CHAN5G(5745, 33), /* Channel 149 */ | |
127 | CHAN5G(5765, 34), /* Channel 153 */ | |
128 | CHAN5G(5785, 35), /* Channel 157 */ | |
129 | CHAN5G(5805, 36), /* Channel 161 */ | |
130 | CHAN5G(5825, 37), /* Channel 165 */ | |
131 | }; | |
132 | ||
133 | /* Atheros hardware rate code addition for short premble */ | |
134 | #define SHPCHECK(__hw_rate, __flags) \ | |
135 | ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) | |
136 | ||
137 | #define RATE(_bitrate, _hw_rate, _flags) { \ | |
138 | .bitrate = (_bitrate), \ | |
139 | .flags = (_flags), \ | |
140 | .hw_value = (_hw_rate), \ | |
141 | .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ | |
142 | } | |
143 | ||
144 | static struct ieee80211_rate ath9k_legacy_rates[] = { | |
145 | RATE(10, 0x1b, 0), | |
146 | RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), | |
147 | RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), | |
148 | RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), | |
67a55330 SW |
149 | RATE(60, 0x0b, (IEEE80211_RATE_SUPPORTS_5MHZ | |
150 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
151 | RATE(90, 0x0f, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
152 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
153 | RATE(120, 0x0a, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
154 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
155 | RATE(180, 0x0e, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
156 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
157 | RATE(240, 0x09, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
158 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
159 | RATE(360, 0x0d, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
160 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
161 | RATE(480, 0x08, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
162 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
163 | RATE(540, 0x0c, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
164 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
55624204 S |
165 | }; |
166 | ||
0cf55c21 FF |
167 | #ifdef CONFIG_MAC80211_LEDS |
168 | static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { | |
169 | { .throughput = 0 * 1024, .blink_time = 334 }, | |
170 | { .throughput = 1 * 1024, .blink_time = 260 }, | |
171 | { .throughput = 5 * 1024, .blink_time = 220 }, | |
172 | { .throughput = 10 * 1024, .blink_time = 190 }, | |
173 | { .throughput = 20 * 1024, .blink_time = 170 }, | |
174 | { .throughput = 50 * 1024, .blink_time = 150 }, | |
175 | { .throughput = 70 * 1024, .blink_time = 130 }, | |
176 | { .throughput = 100 * 1024, .blink_time = 110 }, | |
177 | { .throughput = 200 * 1024, .blink_time = 80 }, | |
178 | { .throughput = 300 * 1024, .blink_time = 50 }, | |
179 | }; | |
180 | #endif | |
181 | ||
285f2dda | 182 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 S |
183 | |
184 | /* | |
185 | * Read and write, they both share the same lock. We do this to serialize | |
186 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
187 | * as the FIFO on these devices can only accept sanely 2 requests. | |
188 | */ | |
189 | ||
190 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
191 | { | |
192 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
193 | struct ath_common *common = ath9k_hw_common(ah); | |
194 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
195 | ||
f3eef645 | 196 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
197 | unsigned long flags; |
198 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
199 | iowrite32(val, sc->mem + reg_offset); | |
200 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
201 | } else | |
202 | iowrite32(val, sc->mem + reg_offset); | |
203 | } | |
204 | ||
205 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
206 | { | |
207 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
208 | struct ath_common *common = ath9k_hw_common(ah); | |
209 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
210 | u32 val; | |
211 | ||
f3eef645 | 212 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
213 | unsigned long flags; |
214 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
215 | val = ioread32(sc->mem + reg_offset); | |
216 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
217 | } else | |
218 | val = ioread32(sc->mem + reg_offset); | |
219 | return val; | |
220 | } | |
221 | ||
5479de6e RM |
222 | static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, |
223 | u32 set, u32 clr) | |
224 | { | |
225 | u32 val; | |
226 | ||
227 | val = ioread32(sc->mem + reg_offset); | |
228 | val &= ~clr; | |
229 | val |= set; | |
230 | iowrite32(val, sc->mem + reg_offset); | |
231 | ||
232 | return val; | |
233 | } | |
234 | ||
845e03c9 FF |
235 | static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) |
236 | { | |
237 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
238 | struct ath_common *common = ath9k_hw_common(ah); | |
239 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
240 | unsigned long uninitialized_var(flags); | |
241 | u32 val; | |
242 | ||
f3eef645 | 243 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
845e03c9 | 244 | spin_lock_irqsave(&sc->sc_serial_rw, flags); |
5479de6e | 245 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); |
845e03c9 | 246 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); |
5479de6e RM |
247 | } else |
248 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); | |
845e03c9 FF |
249 | |
250 | return val; | |
251 | } | |
252 | ||
55624204 S |
253 | /**************************/ |
254 | /* Initialization */ | |
255 | /**************************/ | |
256 | ||
257 | static void setup_ht_cap(struct ath_softc *sc, | |
258 | struct ieee80211_sta_ht_cap *ht_info) | |
259 | { | |
3bb065a7 FF |
260 | struct ath_hw *ah = sc->sc_ah; |
261 | struct ath_common *common = ath9k_hw_common(ah); | |
55624204 | 262 | u8 tx_streams, rx_streams; |
3bb065a7 | 263 | int i, max_streams; |
55624204 S |
264 | |
265 | ht_info->ht_supported = true; | |
266 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
267 | IEEE80211_HT_CAP_SM_PS | | |
268 | IEEE80211_HT_CAP_SGI_40 | | |
269 | IEEE80211_HT_CAP_DSSSCCK40; | |
270 | ||
b0a33448 LR |
271 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) |
272 | ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; | |
273 | ||
6473d24d VT |
274 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) |
275 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
276 | ||
55624204 S |
277 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
278 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
279 | ||
e41db61d | 280 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) |
7f1c7a6a | 281 | max_streams = 1; |
e7104195 MSS |
282 | else if (AR_SREV_9462(ah)) |
283 | max_streams = 2; | |
7f1c7a6a | 284 | else if (AR_SREV_9300_20_OR_LATER(ah)) |
3bb065a7 FF |
285 | max_streams = 3; |
286 | else | |
287 | max_streams = 2; | |
288 | ||
7a37081e | 289 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
074a8c0d FF |
290 | if (max_streams >= 2) |
291 | ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; | |
292 | ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); | |
293 | } | |
294 | ||
55624204 S |
295 | /* set up supported mcs set */ |
296 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
82b2d334 FF |
297 | tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); |
298 | rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); | |
3bb065a7 | 299 | |
d2182b69 | 300 | ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n", |
226afe68 | 301 | tx_streams, rx_streams); |
55624204 S |
302 | |
303 | if (tx_streams != rx_streams) { | |
55624204 S |
304 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
305 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
306 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
307 | } | |
308 | ||
3bb065a7 FF |
309 | for (i = 0; i < rx_streams; i++) |
310 | ht_info->mcs.rx_mask[i] = 0xff; | |
55624204 S |
311 | |
312 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; | |
313 | } | |
314 | ||
0c0280bd LR |
315 | static void ath9k_reg_notifier(struct wiphy *wiphy, |
316 | struct regulatory_request *request) | |
55624204 S |
317 | { |
318 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
9ac58615 | 319 | struct ath_softc *sc = hw->priv; |
687f545e RM |
320 | struct ath_hw *ah = sc->sc_ah; |
321 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
687f545e | 322 | |
0c0280bd | 323 | ath_reg_notifier_apply(wiphy, request, reg); |
687f545e RM |
324 | |
325 | /* Set tx power */ | |
326 | if (ah->curchan) { | |
327 | sc->config.txpowlimit = 2 * ah->curchan->chan->max_power; | |
328 | ath9k_ps_wakeup(sc); | |
329 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); | |
330 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; | |
73e4937d ZK |
331 | /* synchronize DFS detector if regulatory domain changed */ |
332 | if (sc->dfs_detector != NULL) | |
333 | sc->dfs_detector->set_dfs_domain(sc->dfs_detector, | |
334 | request->dfs_region); | |
687f545e RM |
335 | ath9k_ps_restore(sc); |
336 | } | |
55624204 S |
337 | } |
338 | ||
339 | /* | |
340 | * This function will allocate both the DMA descriptor structure, and the | |
341 | * buffers it contains. These are used to contain the descriptors used | |
342 | * by the system. | |
343 | */ | |
344 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
345 | struct list_head *head, const char *name, | |
4adfcded | 346 | int nbuf, int ndesc, bool is_tx) |
55624204 | 347 | { |
55624204 | 348 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4adfcded | 349 | u8 *ds; |
55624204 | 350 | struct ath_buf *bf; |
b81950b1 | 351 | int i, bsize, desc_len; |
55624204 | 352 | |
d2182b69 | 353 | ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
226afe68 | 354 | name, nbuf, ndesc); |
55624204 S |
355 | |
356 | INIT_LIST_HEAD(head); | |
4adfcded VT |
357 | |
358 | if (is_tx) | |
359 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
360 | else | |
361 | desc_len = sizeof(struct ath_desc); | |
362 | ||
55624204 | 363 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 364 | if ((desc_len % 4) != 0) { |
3800276a | 365 | ath_err(common, "ath_desc not DWORD aligned\n"); |
4adfcded | 366 | BUG_ON((desc_len % 4) != 0); |
b81950b1 | 367 | return -ENOMEM; |
55624204 S |
368 | } |
369 | ||
4adfcded | 370 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
371 | |
372 | /* | |
373 | * Need additional DMA memory because we can't use | |
374 | * descriptors that cross the 4K page boundary. Assume | |
375 | * one skipped descriptor per 4K page. | |
376 | */ | |
377 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
378 | u32 ndesc_skipped = | |
379 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
380 | u32 dma_len; | |
381 | ||
382 | while (ndesc_skipped) { | |
4adfcded | 383 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
384 | dd->dd_desc_len += dma_len; |
385 | ||
386 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 387 | } |
55624204 S |
388 | } |
389 | ||
390 | /* allocate descriptors */ | |
b81950b1 FF |
391 | dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, |
392 | &dd->dd_desc_paddr, GFP_KERNEL); | |
393 | if (!dd->dd_desc) | |
394 | return -ENOMEM; | |
395 | ||
4adfcded | 396 | ds = (u8 *) dd->dd_desc; |
d2182b69 | 397 | ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
226afe68 JP |
398 | name, ds, (u32) dd->dd_desc_len, |
399 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
55624204 S |
400 | |
401 | /* allocate buffers */ | |
402 | bsize = sizeof(struct ath_buf) * nbuf; | |
b81950b1 FF |
403 | bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); |
404 | if (!bf) | |
405 | return -ENOMEM; | |
55624204 | 406 | |
4adfcded | 407 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { |
55624204 S |
408 | bf->bf_desc = ds; |
409 | bf->bf_daddr = DS2PHYS(dd, ds); | |
410 | ||
411 | if (!(sc->sc_ah->caps.hw_caps & | |
412 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
413 | /* | |
414 | * Skip descriptor addresses which can cause 4KB | |
415 | * boundary crossing (addr + length) with a 32 dword | |
416 | * descriptor fetch. | |
417 | */ | |
418 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
419 | BUG_ON((caddr_t) bf->bf_desc >= | |
420 | ((caddr_t) dd->dd_desc + | |
421 | dd->dd_desc_len)); | |
422 | ||
4adfcded | 423 | ds += (desc_len * ndesc); |
55624204 S |
424 | bf->bf_desc = ds; |
425 | bf->bf_daddr = DS2PHYS(dd, ds); | |
426 | } | |
427 | } | |
428 | list_add_tail(&bf->list, head); | |
429 | } | |
430 | return 0; | |
55624204 S |
431 | } |
432 | ||
285f2dda S |
433 | static int ath9k_init_queues(struct ath_softc *sc) |
434 | { | |
285f2dda S |
435 | int i = 0; |
436 | ||
285f2dda | 437 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 438 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
439 | |
440 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; | |
441 | ath_cabq_update(sc); | |
442 | ||
f2c7a793 FF |
443 | sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); |
444 | ||
bea843c7 | 445 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
066dae93 | 446 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); |
60f2d1d5 | 447 | sc->tx.txq_map[i]->mac80211_qnum = i; |
7702e788 | 448 | sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; |
60f2d1d5 | 449 | } |
285f2dda | 450 | return 0; |
285f2dda S |
451 | } |
452 | ||
f209f529 | 453 | static int ath9k_init_channels_rates(struct ath_softc *sc) |
285f2dda | 454 | { |
f209f529 FF |
455 | void *channels; |
456 | ||
cac4220b FF |
457 | BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + |
458 | ARRAY_SIZE(ath9k_5ghz_chantable) != | |
459 | ATH9K_NUM_CHANNELS); | |
460 | ||
d4659912 | 461 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { |
b81950b1 | 462 | channels = devm_kzalloc(sc->dev, |
f209f529 FF |
463 | sizeof(ath9k_2ghz_chantable), GFP_KERNEL); |
464 | if (!channels) | |
465 | return -ENOMEM; | |
466 | ||
b81950b1 FF |
467 | memcpy(channels, ath9k_2ghz_chantable, |
468 | sizeof(ath9k_2ghz_chantable)); | |
f209f529 | 469 | sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; |
285f2dda S |
470 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; |
471 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = | |
472 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
473 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; | |
474 | sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = | |
475 | ARRAY_SIZE(ath9k_legacy_rates); | |
55624204 S |
476 | } |
477 | ||
d4659912 | 478 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { |
b81950b1 | 479 | channels = devm_kzalloc(sc->dev, |
f209f529 | 480 | sizeof(ath9k_5ghz_chantable), GFP_KERNEL); |
b81950b1 | 481 | if (!channels) |
f209f529 | 482 | return -ENOMEM; |
f209f529 | 483 | |
b81950b1 FF |
484 | memcpy(channels, ath9k_5ghz_chantable, |
485 | sizeof(ath9k_5ghz_chantable)); | |
f209f529 | 486 | sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; |
285f2dda S |
487 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; |
488 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = | |
489 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
490 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
491 | ath9k_legacy_rates + 4; | |
492 | sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = | |
493 | ARRAY_SIZE(ath9k_legacy_rates) - 4; | |
494 | } | |
f209f529 | 495 | return 0; |
285f2dda | 496 | } |
55624204 | 497 | |
285f2dda S |
498 | static void ath9k_init_misc(struct ath_softc *sc) |
499 | { | |
500 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
501 | int i = 0; | |
3d4e20f2 | 502 | |
285f2dda | 503 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); |
55624204 | 504 | |
aaa1ec46 | 505 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
55624204 | 506 | sc->config.txpowlimit = ATH_TXPOWER_MAX; |
364734fa | 507 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
285f2dda | 508 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 509 | |
7545daf4 | 510 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) |
55624204 | 511 | sc->beacon.bslot[i] = NULL; |
102885a5 VT |
512 | |
513 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
514 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
04ccd4a1 SW |
515 | |
516 | sc->spec_config.enabled = 0; | |
517 | sc->spec_config.short_repeat = true; | |
518 | sc->spec_config.count = 8; | |
519 | sc->spec_config.endless = false; | |
520 | sc->spec_config.period = 0xFF; | |
521 | sc->spec_config.fft_period = 0xF; | |
285f2dda | 522 | } |
55624204 | 523 | |
9b60b64b SM |
524 | static void ath9k_init_platform(struct ath_softc *sc) |
525 | { | |
526 | struct ath_hw *ah = sc->sc_ah; | |
3f2da955 | 527 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
9b60b64b SM |
528 | struct ath_common *common = ath9k_hw_common(ah); |
529 | ||
530 | if (common->bus_ops->ath_bus_type != ATH_PCI) | |
531 | return; | |
532 | ||
e861ef52 SM |
533 | if (sc->driver_data & (ATH9K_PCI_CUS198 | |
534 | ATH9K_PCI_CUS230)) { | |
9b60b64b SM |
535 | ah->config.xlna_gpio = 9; |
536 | ah->config.xatten_margin_cfg = true; | |
e083a42e | 537 | ah->config.alt_mingainidx = true; |
31fd216d | 538 | ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; |
3afa6b4f SM |
539 | sc->ant_comb.low_rssi_thresh = 20; |
540 | sc->ant_comb.fast_div_bias = 3; | |
9b60b64b | 541 | |
e861ef52 SM |
542 | ath_info(common, "Set parameters for %s\n", |
543 | (sc->driver_data & ATH9K_PCI_CUS198) ? | |
544 | "CUS198" : "CUS230"); | |
3f2da955 SM |
545 | } |
546 | ||
547 | if (sc->driver_data & ATH9K_PCI_CUS217) | |
12eea640 | 548 | ath_info(common, "CUS217 card detected\n"); |
3f2da955 | 549 | |
10631336 SM |
550 | if (sc->driver_data & ATH9K_PCI_CUS252) |
551 | ath_info(common, "CUS252 card detected\n"); | |
552 | ||
3f2da955 SM |
553 | if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { |
554 | pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; | |
555 | ath_info(common, "Set BT/WLAN RX diversity capability\n"); | |
9b60b64b | 556 | } |
d1ae25a0 SM |
557 | |
558 | if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { | |
559 | ah->config.pcie_waen = 0x0040473b; | |
560 | ath_info(common, "Enable WAR for ASPM D3/L1\n"); | |
561 | } | |
9b60b64b SM |
562 | } |
563 | ||
ab5c4f71 GJ |
564 | static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, |
565 | void *ctx) | |
566 | { | |
567 | struct ath9k_eeprom_ctx *ec = ctx; | |
568 | ||
569 | if (eeprom_blob) | |
570 | ec->ah->eeprom_blob = eeprom_blob; | |
571 | ||
572 | complete(&ec->complete); | |
573 | } | |
574 | ||
575 | static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) | |
576 | { | |
577 | struct ath9k_eeprom_ctx ec; | |
578 | struct ath_hw *ah = ah = sc->sc_ah; | |
579 | int err; | |
580 | ||
581 | /* try to load the EEPROM content asynchronously */ | |
582 | init_completion(&ec.complete); | |
583 | ec.ah = sc->sc_ah; | |
584 | ||
585 | err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, | |
586 | &ec, ath9k_eeprom_request_cb); | |
587 | if (err < 0) { | |
588 | ath_err(ath9k_hw_common(ah), | |
589 | "EEPROM request failed\n"); | |
590 | return err; | |
591 | } | |
592 | ||
593 | wait_for_completion(&ec.complete); | |
594 | ||
595 | if (!ah->eeprom_blob) { | |
596 | ath_err(ath9k_hw_common(ah), | |
597 | "Unable to load EEPROM file %s\n", name); | |
598 | return -EINVAL; | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | static void ath9k_eeprom_release(struct ath_softc *sc) | |
605 | { | |
606 | release_firmware(sc->sc_ah->eeprom_blob); | |
607 | } | |
608 | ||
eb93e891 | 609 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, |
285f2dda S |
610 | const struct ath_bus_ops *bus_ops) |
611 | { | |
6fb1b1e1 | 612 | struct ath9k_platform_data *pdata = sc->dev->platform_data; |
285f2dda | 613 | struct ath_hw *ah = NULL; |
3f2da955 | 614 | struct ath9k_hw_capabilities *pCap; |
285f2dda S |
615 | struct ath_common *common; |
616 | int ret = 0, i; | |
617 | int csz = 0; | |
55624204 | 618 | |
b81950b1 | 619 | ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); |
285f2dda S |
620 | if (!ah) |
621 | return -ENOMEM; | |
622 | ||
c1b976d2 | 623 | ah->dev = sc->dev; |
233536e1 | 624 | ah->hw = sc->hw; |
285f2dda | 625 | ah->hw_version.devid = devid; |
f9f84e96 FF |
626 | ah->reg_ops.read = ath9k_ioread32; |
627 | ah->reg_ops.write = ath9k_iowrite32; | |
845e03c9 | 628 | ah->reg_ops.rmw = ath9k_reg_rmw; |
e8fe7336 | 629 | atomic_set(&ah->intr_ref_cnt, -1); |
285f2dda | 630 | sc->sc_ah = ah; |
3f2da955 | 631 | pCap = &ah->caps; |
285f2dda | 632 | |
ca21cfde | 633 | sc->dfs_detector = dfs_pattern_detector_init(ah, NL80211_DFS_UNSET); |
8e92d3f2 | 634 | |
6de66dd9 | 635 | if (!pdata) { |
a05b5d45 | 636 | ah->ah_flags |= AH_USE_EEPROM; |
6de66dd9 FF |
637 | sc->sc_ah->led_pin = -1; |
638 | } else { | |
639 | sc->sc_ah->gpio_mask = pdata->gpio_mask; | |
640 | sc->sc_ah->gpio_val = pdata->gpio_val; | |
641 | sc->sc_ah->led_pin = pdata->led_pin; | |
f2f5f2a1 | 642 | ah->is_clk_25mhz = pdata->is_clk_25mhz; |
3762561a | 643 | ah->get_mac_revision = pdata->get_mac_revision; |
7d95847c | 644 | ah->external_reset = pdata->external_reset; |
6de66dd9 | 645 | } |
a05b5d45 | 646 | |
285f2dda | 647 | common = ath9k_hw_common(ah); |
f9f84e96 | 648 | common->ops = &ah->reg_ops; |
285f2dda S |
649 | common->bus_ops = bus_ops; |
650 | common->ah = ah; | |
651 | common->hw = sc->hw; | |
652 | common->priv = sc; | |
653 | common->debug_mask = ath9k_debug; | |
8f5dcb1c | 654 | common->btcoex_enabled = ath9k_btcoex_enable == 1; |
05c0be2f | 655 | common->disable_ani = false; |
e09f2dc7 | 656 | |
9b60b64b SM |
657 | /* |
658 | * Platform quirks. | |
659 | */ | |
660 | ath9k_init_platform(sc); | |
661 | ||
e09f2dc7 | 662 | /* |
3f2da955 SM |
663 | * Enable WLAN/BT RX Antenna diversity only when: |
664 | * | |
7d845871 | 665 | * - BTCOEX is disabled. |
3f2da955 SM |
666 | * - the user manually requests the feature. |
667 | * - the HW cap is set using the platform data. | |
e09f2dc7 | 668 | */ |
7d845871 | 669 | if (!common->btcoex_enabled && ath9k_bt_ant_diversity && |
3f2da955 | 670 | (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) |
63081305 | 671 | common->bt_ant_diversity = 1; |
e09f2dc7 | 672 | |
20b25744 | 673 | spin_lock_init(&common->cc_lock); |
285f2dda | 674 | |
285f2dda S |
675 | spin_lock_init(&sc->sc_serial_rw); |
676 | spin_lock_init(&sc->sc_pm_lock); | |
677 | mutex_init(&sc->mutex); | |
678 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); | |
fb6e252f | 679 | tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, |
285f2dda S |
680 | (unsigned long)sc); |
681 | ||
aaa1ec46 SM |
682 | INIT_WORK(&sc->hw_reset_work, ath_reset_work); |
683 | INIT_WORK(&sc->hw_check_work, ath_hw_check); | |
684 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); | |
685 | INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); | |
686 | setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc); | |
687 | ||
285f2dda S |
688 | /* |
689 | * Cache line size is used to size and align various | |
690 | * structures used to communicate with the hardware. | |
691 | */ | |
692 | ath_read_cachesize(common, &csz); | |
693 | common->cachelsz = csz << 2; /* convert to bytes */ | |
694 | ||
36b07d15 | 695 | if (pdata && pdata->eeprom_name) { |
ab5c4f71 GJ |
696 | ret = ath9k_eeprom_request(sc, pdata->eeprom_name); |
697 | if (ret) | |
b81950b1 | 698 | return ret; |
ab5c4f71 GJ |
699 | } |
700 | ||
d70357d5 | 701 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 702 | ret = ath9k_hw_init(ah); |
d70357d5 | 703 | if (ret) |
285f2dda | 704 | goto err_hw; |
55624204 | 705 | |
6fb1b1e1 FF |
706 | if (pdata && pdata->macaddr) |
707 | memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); | |
708 | ||
285f2dda S |
709 | ret = ath9k_init_queues(sc); |
710 | if (ret) | |
711 | goto err_queues; | |
712 | ||
713 | ret = ath9k_init_btcoex(sc); | |
714 | if (ret) | |
715 | goto err_btcoex; | |
716 | ||
f209f529 FF |
717 | ret = ath9k_init_channels_rates(sc); |
718 | if (ret) | |
719 | goto err_btcoex; | |
720 | ||
f82b4bde | 721 | ath9k_cmn_init_crypto(sc->sc_ah); |
285f2dda | 722 | ath9k_init_misc(sc); |
8f176a3a | 723 | ath_fill_led_pin(sc); |
285f2dda | 724 | |
d09f5f4c SM |
725 | if (common->bus_ops->aspm_init) |
726 | common->bus_ops->aspm_init(common); | |
727 | ||
55624204 | 728 | return 0; |
285f2dda S |
729 | |
730 | err_btcoex: | |
55624204 S |
731 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
732 | if (ATH_TXQ_SETUP(sc, i)) | |
733 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda | 734 | err_queues: |
285f2dda S |
735 | ath9k_hw_deinit(ah); |
736 | err_hw: | |
ab5c4f71 | 737 | ath9k_eeprom_release(sc); |
285f2dda | 738 | return ret; |
55624204 S |
739 | } |
740 | ||
babcbc29 FF |
741 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
742 | { | |
743 | struct ieee80211_supported_band *sband; | |
744 | struct ieee80211_channel *chan; | |
745 | struct ath_hw *ah = sc->sc_ah; | |
0671894f | 746 | struct cfg80211_chan_def chandef; |
babcbc29 FF |
747 | int i; |
748 | ||
749 | sband = &sc->sbands[band]; | |
750 | for (i = 0; i < sband->n_channels; i++) { | |
751 | chan = &sband->channels[i]; | |
752 | ah->curchan = &ah->channels[chan->hw_value]; | |
0671894f SW |
753 | cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); |
754 | ath9k_cmn_update_ichannel(ah->curchan, &chandef); | |
babcbc29 | 755 | ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); |
babcbc29 FF |
756 | } |
757 | } | |
758 | ||
759 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
760 | { | |
761 | struct ath_hw *ah = sc->sc_ah; | |
762 | struct ath9k_channel *curchan = ah->curchan; | |
763 | ||
764 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
765 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); | |
766 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
767 | ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); | |
768 | ||
769 | ah->curchan = curchan; | |
770 | } | |
771 | ||
43c35284 FF |
772 | void ath9k_reload_chainmask_settings(struct ath_softc *sc) |
773 | { | |
774 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)) | |
775 | return; | |
776 | ||
777 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
778 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); | |
779 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
780 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); | |
781 | } | |
782 | ||
20c8e8dc FF |
783 | static const struct ieee80211_iface_limit if_limits[] = { |
784 | { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) | | |
785 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
786 | BIT(NL80211_IFTYPE_WDS) }, | |
787 | { .max = 8, .types = | |
788 | #ifdef CONFIG_MAC80211_MESH | |
789 | BIT(NL80211_IFTYPE_MESH_POINT) | | |
790 | #endif | |
791 | BIT(NL80211_IFTYPE_AP) | | |
792 | BIT(NL80211_IFTYPE_P2P_GO) }, | |
793 | }; | |
794 | ||
e9cdedf6 ZK |
795 | |
796 | static const struct ieee80211_iface_limit if_dfs_limits[] = { | |
797 | { .max = 1, .types = BIT(NL80211_IFTYPE_AP) }, | |
798 | }; | |
799 | ||
800 | static const struct ieee80211_iface_combination if_comb[] = { | |
801 | { | |
802 | .limits = if_limits, | |
803 | .n_limits = ARRAY_SIZE(if_limits), | |
804 | .max_interfaces = 2048, | |
805 | .num_different_channels = 1, | |
806 | .beacon_int_infra_match = true, | |
807 | }, | |
808 | { | |
809 | .limits = if_dfs_limits, | |
810 | .n_limits = ARRAY_SIZE(if_dfs_limits), | |
811 | .max_interfaces = 1, | |
812 | .num_different_channels = 1, | |
813 | .beacon_int_infra_match = true, | |
814 | .radar_detect_widths = BIT(NL80211_CHAN_NO_HT) | | |
815 | BIT(NL80211_CHAN_HT20), | |
816 | } | |
20c8e8dc | 817 | }; |
43c35284 | 818 | |
964dc9e2 JB |
819 | #ifdef CONFIG_PM |
820 | static const struct wiphy_wowlan_support ath9k_wowlan_support = { | |
821 | .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, | |
822 | .n_patterns = MAX_NUM_USER_PATTERN, | |
823 | .pattern_min_len = 1, | |
824 | .pattern_max_len = MAX_PATTERN_SIZE, | |
825 | }; | |
826 | #endif | |
827 | ||
285f2dda | 828 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 829 | { |
43c35284 FF |
830 | struct ath_hw *ah = sc->sc_ah; |
831 | struct ath_common *common = ath9k_hw_common(ah); | |
285f2dda | 832 | |
55624204 S |
833 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
834 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
835 | IEEE80211_HW_SIGNAL_DBM | | |
55624204 S |
836 | IEEE80211_HW_SUPPORTS_PS | |
837 | IEEE80211_HW_PS_NULLFUNC_STACK | | |
05df4986 | 838 | IEEE80211_HW_SPECTRUM_MGMT | |
79acac07 | 839 | IEEE80211_HW_REPORTS_TX_ACK_STATUS | |
2dfca312 FF |
840 | IEEE80211_HW_SUPPORTS_RC_TABLE | |
841 | IEEE80211_HW_SUPPORTS_HT_CCK_RATES; | |
55624204 | 842 | |
b0a1ae97 OR |
843 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
844 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
845 | ||
846 | if (AR_SREV_9280_20_OR_LATER(ah)) | |
847 | hw->radiotap_mcs_details |= | |
848 | IEEE80211_RADIOTAP_MCS_HAVE_STBC; | |
849 | } | |
5ffaf8a3 | 850 | |
3e6109c5 | 851 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) |
55624204 S |
852 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; |
853 | ||
ec26bcc0 FF |
854 | hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR; |
855 | ||
55624204 | 856 | hw->wiphy->interface_modes = |
c426ee24 JB |
857 | BIT(NL80211_IFTYPE_P2P_GO) | |
858 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
55624204 | 859 | BIT(NL80211_IFTYPE_AP) | |
e51f3eff | 860 | BIT(NL80211_IFTYPE_WDS) | |
55624204 S |
861 | BIT(NL80211_IFTYPE_STATION) | |
862 | BIT(NL80211_IFTYPE_ADHOC) | | |
863 | BIT(NL80211_IFTYPE_MESH_POINT); | |
864 | ||
e9cdedf6 ZK |
865 | hw->wiphy->iface_combinations = if_comb; |
866 | hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); | |
20c8e8dc | 867 | |
531671cb | 868 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
55624204 | 869 | |
cfdc9a8b | 870 | hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; |
fd656234 | 871 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; |
81ddbb5c | 872 | hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; |
6fac8bbc | 873 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; |
d074e8d5 | 874 | hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; |
cfdc9a8b | 875 | |
9f11e16e | 876 | #ifdef CONFIG_PM_SLEEP |
9f11e16e | 877 | if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) && |
fca3c21d | 878 | (sc->driver_data & ATH9K_PCI_WOW) && |
964dc9e2 JB |
879 | device_can_wakeup(sc->dev)) |
880 | hw->wiphy->wowlan = &ath9k_wowlan_support; | |
9f11e16e MSS |
881 | |
882 | atomic_set(&sc->wow_sleep_proc_intr, -1); | |
883 | atomic_set(&sc->wow_got_bmiss_intr, -1); | |
9f11e16e MSS |
884 | #endif |
885 | ||
55624204 S |
886 | hw->queues = 4; |
887 | hw->max_rates = 4; | |
888 | hw->channel_change_time = 5000; | |
195ca3b1 | 889 | hw->max_listen_interval = 1; |
65896510 | 890 | hw->max_rate_tries = 10; |
55624204 S |
891 | hw->sta_data_size = sizeof(struct ath_node); |
892 | hw->vif_data_size = sizeof(struct ath_vif); | |
893 | ||
43c35284 FF |
894 | hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; |
895 | hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; | |
896 | ||
897 | /* single chain devices with rx diversity */ | |
898 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
899 | hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); | |
900 | ||
901 | sc->ant_rx = hw->wiphy->available_antennas_rx; | |
902 | sc->ant_tx = hw->wiphy->available_antennas_tx; | |
903 | ||
d4659912 | 904 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
55624204 S |
905 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
906 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
d4659912 | 907 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
55624204 S |
908 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
909 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
285f2dda | 910 | |
43c35284 | 911 | ath9k_reload_chainmask_settings(sc); |
285f2dda S |
912 | |
913 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
914 | } |
915 | ||
eb93e891 | 916 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
55624204 S |
917 | const struct ath_bus_ops *bus_ops) |
918 | { | |
919 | struct ieee80211_hw *hw = sc->hw; | |
920 | struct ath_common *common; | |
921 | struct ath_hw *ah; | |
285f2dda | 922 | int error = 0; |
55624204 S |
923 | struct ath_regulatory *reg; |
924 | ||
285f2dda | 925 | /* Bring up device */ |
eb93e891 | 926 | error = ath9k_init_softc(devid, sc, bus_ops); |
b81950b1 FF |
927 | if (error) |
928 | return error; | |
55624204 S |
929 | |
930 | ah = sc->sc_ah; | |
931 | common = ath9k_hw_common(ah); | |
285f2dda | 932 | ath9k_set_hw_capab(sc, hw); |
55624204 | 933 | |
285f2dda | 934 | /* Initialize regulatory */ |
55624204 S |
935 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
936 | ath9k_reg_notifier); | |
937 | if (error) | |
b81950b1 | 938 | goto deinit; |
55624204 S |
939 | |
940 | reg = &common->regulatory; | |
941 | ||
285f2dda | 942 | /* Setup TX DMA */ |
55624204 S |
943 | error = ath_tx_init(sc, ATH_TXBUF); |
944 | if (error != 0) | |
b81950b1 | 945 | goto deinit; |
55624204 | 946 | |
285f2dda | 947 | /* Setup RX DMA */ |
55624204 S |
948 | error = ath_rx_init(sc, ATH_RXBUF); |
949 | if (error != 0) | |
b81950b1 | 950 | goto deinit; |
55624204 | 951 | |
babcbc29 FF |
952 | ath9k_init_txpower_limits(sc); |
953 | ||
0cf55c21 FF |
954 | #ifdef CONFIG_MAC80211_LEDS |
955 | /* must be initialized before ieee80211_register_hw */ | |
956 | sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, | |
957 | IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, | |
958 | ARRAY_SIZE(ath9k_tpt_blink)); | |
959 | #endif | |
960 | ||
285f2dda | 961 | /* Register with mac80211 */ |
55624204 | 962 | error = ieee80211_register_hw(hw); |
285f2dda | 963 | if (error) |
b81950b1 | 964 | goto rx_cleanup; |
55624204 | 965 | |
eb272441 BG |
966 | error = ath9k_init_debug(ah); |
967 | if (error) { | |
3800276a | 968 | ath_err(common, "Unable to create debugfs files\n"); |
b81950b1 | 969 | goto unregister; |
eb272441 BG |
970 | } |
971 | ||
285f2dda | 972 | /* Handle world regulatory */ |
55624204 S |
973 | if (!ath_is_world_regd(reg)) { |
974 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
975 | if (error) | |
af690092 | 976 | goto debug_cleanup; |
55624204 S |
977 | } |
978 | ||
285f2dda | 979 | ath_init_leds(sc); |
55624204 S |
980 | ath_start_rfkill_poll(sc); |
981 | ||
982 | return 0; | |
983 | ||
af690092 SM |
984 | debug_cleanup: |
985 | ath9k_deinit_debug(sc); | |
b81950b1 | 986 | unregister: |
285f2dda | 987 | ieee80211_unregister_hw(hw); |
b81950b1 | 988 | rx_cleanup: |
285f2dda | 989 | ath_rx_cleanup(sc); |
b81950b1 | 990 | deinit: |
285f2dda | 991 | ath9k_deinit_softc(sc); |
55624204 S |
992 | return error; |
993 | } | |
994 | ||
995 | /*****************************/ | |
996 | /* De-Initialization */ | |
997 | /*****************************/ | |
998 | ||
285f2dda | 999 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 1000 | { |
285f2dda | 1001 | int i = 0; |
55624204 | 1002 | |
5908120f | 1003 | ath9k_deinit_btcoex(sc); |
19686ddf | 1004 | |
285f2dda S |
1005 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
1006 | if (ATH_TXQ_SETUP(sc, i)) | |
1007 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
1008 | ||
285f2dda | 1009 | ath9k_hw_deinit(sc->sc_ah); |
8e92d3f2 ZK |
1010 | if (sc->dfs_detector != NULL) |
1011 | sc->dfs_detector->exit(sc->dfs_detector); | |
285f2dda | 1012 | |
ab5c4f71 | 1013 | ath9k_eeprom_release(sc); |
55624204 S |
1014 | } |
1015 | ||
285f2dda | 1016 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
1017 | { |
1018 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
1019 | |
1020 | ath9k_ps_wakeup(sc); | |
1021 | ||
55624204 | 1022 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 1023 | ath_deinit_leds(sc); |
55624204 | 1024 | |
c7c18060 RM |
1025 | ath9k_ps_restore(sc); |
1026 | ||
af690092 | 1027 | ath9k_deinit_debug(sc); |
55624204 S |
1028 | ieee80211_unregister_hw(hw); |
1029 | ath_rx_cleanup(sc); | |
285f2dda | 1030 | ath9k_deinit_softc(sc); |
55624204 S |
1031 | } |
1032 | ||
55624204 S |
1033 | /************************/ |
1034 | /* Module Hooks */ | |
1035 | /************************/ | |
1036 | ||
1037 | static int __init ath9k_init(void) | |
1038 | { | |
1039 | int error; | |
1040 | ||
1041 | /* Register rate control algorithm */ | |
1042 | error = ath_rate_control_register(); | |
1043 | if (error != 0) { | |
516304b0 JP |
1044 | pr_err("Unable to register rate control algorithm: %d\n", |
1045 | error); | |
55624204 S |
1046 | goto err_out; |
1047 | } | |
1048 | ||
55624204 S |
1049 | error = ath_pci_init(); |
1050 | if (error < 0) { | |
516304b0 | 1051 | pr_err("No PCI devices found, driver not installed\n"); |
55624204 | 1052 | error = -ENODEV; |
eb272441 | 1053 | goto err_rate_unregister; |
55624204 S |
1054 | } |
1055 | ||
1056 | error = ath_ahb_init(); | |
1057 | if (error < 0) { | |
1058 | error = -ENODEV; | |
1059 | goto err_pci_exit; | |
1060 | } | |
1061 | ||
1062 | return 0; | |
1063 | ||
1064 | err_pci_exit: | |
1065 | ath_pci_exit(); | |
1066 | ||
55624204 S |
1067 | err_rate_unregister: |
1068 | ath_rate_control_unregister(); | |
1069 | err_out: | |
1070 | return error; | |
1071 | } | |
1072 | module_init(ath9k_init); | |
1073 | ||
1074 | static void __exit ath9k_exit(void) | |
1075 | { | |
d584747b | 1076 | is_ath9k_unloaded = true; |
55624204 S |
1077 | ath_ahb_exit(); |
1078 | ath_pci_exit(); | |
55624204 | 1079 | ath_rate_control_unregister(); |
516304b0 | 1080 | pr_info("%s: Driver unloaded\n", dev_info); |
55624204 S |
1081 | } |
1082 | module_exit(ath9k_exit); |