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mac80211: Retry null data frame for power save.
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / init.c
CommitLineData
55624204
S		 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "ath9k.h"
18
19static char *dev_info = "ath9k";
20
21MODULE_AUTHOR("Atheros Communications");
22MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
23MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
24MODULE_LICENSE("Dual BSD/GPL");
25
26static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
27module_param_named(debug, ath9k_debug, uint, 0);
28MODULE_PARM_DESC(debug, "Debugging mask");
29
30int modparam_nohwcrypt;
31module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
32MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
33
34/* We use the hw_value as an index into our private channel structure */
35
36#define CHAN2G(_freq, _idx) { \
37 .center_freq = (_freq), \
38 .hw_value = (_idx), \
39 .max_power = 20, \
40}
41
42#define CHAN5G(_freq, _idx) { \
43 .band = IEEE80211_BAND_5GHZ, \
44 .center_freq = (_freq), \
45 .hw_value = (_idx), \
46 .max_power = 20, \
47}
48
49/* Some 2 GHz radios are actually tunable on 2312-2732
50 * on 5 MHz steps, we support the channels which we know
51 * we have calibration data for all cards though to make
52 * this static */
53static struct ieee80211_channel ath9k_2ghz_chantable[] = {
54 CHAN2G(2412, 0), /* Channel 1 */
55 CHAN2G(2417, 1), /* Channel 2 */
56 CHAN2G(2422, 2), /* Channel 3 */
57 CHAN2G(2427, 3), /* Channel 4 */
58 CHAN2G(2432, 4), /* Channel 5 */
59 CHAN2G(2437, 5), /* Channel 6 */
60 CHAN2G(2442, 6), /* Channel 7 */
61 CHAN2G(2447, 7), /* Channel 8 */
62 CHAN2G(2452, 8), /* Channel 9 */
63 CHAN2G(2457, 9), /* Channel 10 */
64 CHAN2G(2462, 10), /* Channel 11 */
65 CHAN2G(2467, 11), /* Channel 12 */
66 CHAN2G(2472, 12), /* Channel 13 */
67 CHAN2G(2484, 13), /* Channel 14 */
68};
69
70/* Some 5 GHz radios are actually tunable on XXXX-YYYY
71 * on 5 MHz steps, we support the channels which we know
72 * we have calibration data for all cards though to make
73 * this static */
74static struct ieee80211_channel ath9k_5ghz_chantable[] = {
75 /* _We_ call this UNII 1 */
76 CHAN5G(5180, 14), /* Channel 36 */
77 CHAN5G(5200, 15), /* Channel 40 */
78 CHAN5G(5220, 16), /* Channel 44 */
79 CHAN5G(5240, 17), /* Channel 48 */
80 /* _We_ call this UNII 2 */
81 CHAN5G(5260, 18), /* Channel 52 */
82 CHAN5G(5280, 19), /* Channel 56 */
83 CHAN5G(5300, 20), /* Channel 60 */
84 CHAN5G(5320, 21), /* Channel 64 */
85 /* _We_ call this "Middle band" */
86 CHAN5G(5500, 22), /* Channel 100 */
87 CHAN5G(5520, 23), /* Channel 104 */
88 CHAN5G(5540, 24), /* Channel 108 */
89 CHAN5G(5560, 25), /* Channel 112 */
90 CHAN5G(5580, 26), /* Channel 116 */
91 CHAN5G(5600, 27), /* Channel 120 */
92 CHAN5G(5620, 28), /* Channel 124 */
93 CHAN5G(5640, 29), /* Channel 128 */
94 CHAN5G(5660, 30), /* Channel 132 */
95 CHAN5G(5680, 31), /* Channel 136 */
96 CHAN5G(5700, 32), /* Channel 140 */
97 /* _We_ call this UNII 3 */
98 CHAN5G(5745, 33), /* Channel 149 */
99 CHAN5G(5765, 34), /* Channel 153 */
100 CHAN5G(5785, 35), /* Channel 157 */
101 CHAN5G(5805, 36), /* Channel 161 */
102 CHAN5G(5825, 37), /* Channel 165 */
103};
104
105/* Atheros hardware rate code addition for short premble */
106#define SHPCHECK(__hw_rate, __flags) \
107 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
108
109#define RATE(_bitrate, _hw_rate, _flags) { \
110 .bitrate = (_bitrate), \
111 .flags = (_flags), \
112 .hw_value = (_hw_rate), \
113 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
114}
115
116static struct ieee80211_rate ath9k_legacy_rates[] = {
117 RATE(10, 0x1b, 0),
118 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
119 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
120 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
121 RATE(60, 0x0b, 0),
122 RATE(90, 0x0f, 0),
123 RATE(120, 0x0a, 0),
124 RATE(180, 0x0e, 0),
125 RATE(240, 0x09, 0),
126 RATE(360, 0x0d, 0),
127 RATE(480, 0x08, 0),
128 RATE(540, 0x0c, 0),
129};
130
285f2dda 131static void ath9k_deinit_softc(struct ath_softc *sc);
55624204
S		 132
133/*
134 * Read and write, they both share the same lock. We do this to serialize
135 * reads and writes on Atheros 802.11n PCI devices only. This is required
136 * as the FIFO on these devices can only accept sanely 2 requests.
137 */
138
139static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
140{
141 struct ath_hw *ah = (struct ath_hw *) hw_priv;
142 struct ath_common *common = ath9k_hw_common(ah);
143 struct ath_softc *sc = (struct ath_softc *) common->priv;
144
145 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
146 unsigned long flags;
147 spin_lock_irqsave(&sc->sc_serial_rw, flags);
148 iowrite32(val, sc->mem + reg_offset);
149 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
150 } else
151 iowrite32(val, sc->mem + reg_offset);
152}
153
154static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
155{
156 struct ath_hw *ah = (struct ath_hw *) hw_priv;
157 struct ath_common *common = ath9k_hw_common(ah);
158 struct ath_softc *sc = (struct ath_softc *) common->priv;
159 u32 val;
160
161 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
162 unsigned long flags;
163 spin_lock_irqsave(&sc->sc_serial_rw, flags);
164 val = ioread32(sc->mem + reg_offset);
165 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
166 } else
167 val = ioread32(sc->mem + reg_offset);
168 return val;
169}
170
171static const struct ath_ops ath9k_common_ops = {
172 .read = ath9k_ioread32,
173 .write = ath9k_iowrite32,
174};
175
176/**************************/
177/* Initialization */
178/**************************/
179
180static void setup_ht_cap(struct ath_softc *sc,
181 struct ieee80211_sta_ht_cap *ht_info)
182{
183 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
184 u8 tx_streams, rx_streams;
185
186 ht_info->ht_supported = true;
187 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
188 IEEE80211_HT_CAP_SM_PS |
189 IEEE80211_HT_CAP_SGI_40 |
190 IEEE80211_HT_CAP_DSSSCCK40;
191
192 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
193 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
194
195 /* set up supported mcs set */
196 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
197 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
198 1 : 2;
199 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
200 1 : 2;
201
202 if (tx_streams != rx_streams) {
203 ath_print(common, ATH_DBG_CONFIG,
204 "TX streams %d, RX streams: %d\n",
205 tx_streams, rx_streams);
206 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
207 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
208 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
209 }
210
211 ht_info->mcs.rx_mask[0] = 0xff;
212 if (rx_streams >= 2)
213 ht_info->mcs.rx_mask[1] = 0xff;
214
215 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
216}
217
218static int ath9k_reg_notifier(struct wiphy *wiphy,
219 struct regulatory_request *request)
220{
221 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
222 struct ath_wiphy *aphy = hw->priv;
223 struct ath_softc *sc = aphy->sc;
224 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
225
226 return ath_reg_notifier_apply(wiphy, request, reg);
227}
228
229/*
230 * This function will allocate both the DMA descriptor structure, and the
231 * buffers it contains. These are used to contain the descriptors used
232 * by the system.
233*/
234int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
235 struct list_head *head, const char *name,
236 int nbuf, int ndesc)
237{
238#define DS2PHYS(_dd, _ds) \
239 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
240#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
241#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
242 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
243 struct ath_desc *ds;
244 struct ath_buf *bf;
245 int i, bsize, error;
246
247 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
248 name, nbuf, ndesc);
249
250 INIT_LIST_HEAD(head);
251 /* ath_desc must be a multiple of DWORDs */
252 if ((sizeof(struct ath_desc) % 4) != 0) {
253 ath_print(common, ATH_DBG_FATAL,
254 "ath_desc not DWORD aligned\n");
255 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
256 error = -ENOMEM;
257 goto fail;
258 }
259
260 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
261
262 /*
263 * Need additional DMA memory because we can't use
264 * descriptors that cross the 4K page boundary. Assume
265 * one skipped descriptor per 4K page.
266 */
267 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
268 u32 ndesc_skipped =
269 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
270 u32 dma_len;
271
272 while (ndesc_skipped) {
273 dma_len = ndesc_skipped * sizeof(struct ath_desc);
274 dd->dd_desc_len += dma_len;
275
276 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
277 };
278 }
279
280 /* allocate descriptors */
281 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
282 &dd->dd_desc_paddr, GFP_KERNEL);
283 if (dd->dd_desc == NULL) {
284 error = -ENOMEM;
285 goto fail;
286 }
287 ds = dd->dd_desc;
288 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
289 name, ds, (u32) dd->dd_desc_len,
290 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
291
292 /* allocate buffers */
293 bsize = sizeof(struct ath_buf) * nbuf;
294 bf = kzalloc(bsize, GFP_KERNEL);
295 if (bf == NULL) {
296 error = -ENOMEM;
297 goto fail2;
298 }
299 dd->dd_bufptr = bf;
300
301 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
302 bf->bf_desc = ds;
303 bf->bf_daddr = DS2PHYS(dd, ds);
304
305 if (!(sc->sc_ah->caps.hw_caps &
306 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
307 /*
308 * Skip descriptor addresses which can cause 4KB
309 * boundary crossing (addr + length) with a 32 dword
310 * descriptor fetch.
311 */
312 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
313 BUG_ON((caddr_t) bf->bf_desc >=
314 ((caddr_t) dd->dd_desc +
315 dd->dd_desc_len));
316
317 ds += ndesc;
318 bf->bf_desc = ds;
319 bf->bf_daddr = DS2PHYS(dd, ds);
320 }
321 }
322 list_add_tail(&bf->list, head);
323 }
324 return 0;
325fail2:
326 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
327 dd->dd_desc_paddr);
328fail:
329 memset(dd, 0, sizeof(*dd));
330 return error;
331#undef ATH_DESC_4KB_BOUND_CHECK
332#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
333#undef DS2PHYS
334}
335
285f2dda 336static void ath9k_init_crypto(struct ath_softc *sc)
55624204 337{
285f2dda
S		 338 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
339 int i = 0;
55624204
S		 340
341 /* Get the hardware key cache size. */
285f2dda 342 common->keymax = sc->sc_ah->caps.keycache_size;
55624204
S		 343 if (common->keymax > ATH_KEYMAX) {
344 ath_print(common, ATH_DBG_ANY,
345 "Warning, using only %u entries in %u key cache\n",
346 ATH_KEYMAX, common->keymax);
347 common->keymax = ATH_KEYMAX;
348 }
349
350 /*
351 * Reset the key cache since some parts do not
352 * reset the contents on initial power up.
353 */
354 for (i = 0; i < common->keymax; i++)
285f2dda 355 ath9k_hw_keyreset(sc->sc_ah, (u16) i);
55624204 356
285f2dda
S		 357 if (ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER,
358 ATH9K_CIPHER_TKIP, NULL)) {
359 /*
360 * Whether we should enable h/w TKIP MIC.
361 * XXX: if we don't support WME TKIP MIC, then we wouldn't
362 * report WMM capable, so it's always safe to turn on
363 * TKIP MIC in this case.
364 */
365 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC, 0, 1, NULL);
366 }
55624204
S		 367
368 /*
285f2dda
S		 369 * Check whether the separate key cache entries
370 * are required to handle both tx+rx MIC keys.
371 * With split mic keys the number of stations is limited
372 * to 27 otherwise 59.
55624204 373 */
285f2dda
S		 374 if (ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER,
375 ATH9K_CIPHER_TKIP, NULL)
376 && ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER,
377 ATH9K_CIPHER_MIC, NULL)
378 && ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_TKIP_SPLIT,
379 0, NULL))
380 common->splitmic = 1;
381
382 /* turn on mcast key search if possible */
383 if (!ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
384 (void)ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH,
385 1, 1, NULL);
386
387}
388
389static int ath9k_init_btcoex(struct ath_softc *sc)
390{
391 int r, qnum;
392
393 switch (sc->sc_ah->btcoex_hw.scheme) {
394 case ATH_BTCOEX_CFG_NONE:
395 break;
396 case ATH_BTCOEX_CFG_2WIRE:
397 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
398 break;
399 case ATH_BTCOEX_CFG_3WIRE:
400 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
401 r = ath_init_btcoex_timer(sc);
402 if (r)
403 return -1;
404 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
405 ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
406 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
407 break;
408 default:
409 WARN_ON(1);
410 break;
411 }
412
413 return 0;
414}
415
416static int ath9k_init_queues(struct ath_softc *sc)
417{
418 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
419 int i = 0;
420
421 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
422 sc->tx.hwq_map[i] = -1;
423
424 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
55624204
S		 425 if (sc->beacon.beaconq == -1) {
426 ath_print(common, ATH_DBG_FATAL,
427 "Unable to setup a beacon xmit queue\n");
285f2dda 428 goto err;
55624204 429 }
285f2dda 430
55624204
S		 431 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
432 if (sc->beacon.cabq == NULL) {
433 ath_print(common, ATH_DBG_FATAL,
434 "Unable to setup CAB xmit queue\n");
285f2dda 435 goto err;
55624204
S		 436 }
437
438 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
439 ath_cabq_update(sc);
440
55624204
S		 441 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
442 ath_print(common, ATH_DBG_FATAL,
443 "Unable to setup xmit queue for BK traffic\n");
285f2dda 444 goto err;
55624204
S		 445 }
446
447 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
448 ath_print(common, ATH_DBG_FATAL,
449 "Unable to setup xmit queue for BE traffic\n");
285f2dda 450 goto err;
55624204
S		 451 }
452 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
453 ath_print(common, ATH_DBG_FATAL,
454 "Unable to setup xmit queue for VI traffic\n");
285f2dda 455 goto err;
55624204
S		 456 }
457 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
458 ath_print(common, ATH_DBG_FATAL,
459 "Unable to setup xmit queue for VO traffic\n");
285f2dda 460 goto err;
55624204
S		 461 }
462
285f2dda 463 return 0;
55624204 464
285f2dda
S		 465err:
466 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
467 if (ATH_TXQ_SETUP(sc, i))
468 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
55624204 469
285f2dda
S		 470 return -EIO;
471}
472
473static void ath9k_init_channels_rates(struct ath_softc *sc)
474{
475 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
476 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
477 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
478 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
479 ARRAY_SIZE(ath9k_2ghz_chantable);
480 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
481 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
482 ARRAY_SIZE(ath9k_legacy_rates);
55624204
S		 483 }
484
285f2dda
S		 485 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
486 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
487 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
488 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
489 ARRAY_SIZE(ath9k_5ghz_chantable);
490 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
491 ath9k_legacy_rates + 4;
492 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
493 ARRAY_SIZE(ath9k_legacy_rates) - 4;
494 }
495}
55624204 496
285f2dda
S		 497static void ath9k_init_misc(struct ath_softc *sc)
498{
499 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
500 int i = 0;
501
502 common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
503 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
55624204
S		 504
505 sc->config.txpowlimit = ATH_TXPOWER_MAX;
506
285f2dda 507 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
55624204
S		 508 sc->sc_flags |= SC_OP_TXAGGR;
509 sc->sc_flags |= SC_OP_RXAGGR;
510 }
511
285f2dda
S		 512 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
513 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
55624204 514
285f2dda
S		 515 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
516 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
55624204 517
285f2dda 518 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
55624204
S		 519 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
520
285f2dda 521 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
55624204 522
55624204
S		 523 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
524 sc->beacon.bslot[i] = NULL;
525 sc->beacon.bslot_aphy[i] = NULL;
526 }
285f2dda 527}
55624204 528
285f2dda
S		 529static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
530 const struct ath_bus_ops *bus_ops)
531{
532 struct ath_hw *ah = NULL;
533 struct ath_common *common;
534 int ret = 0, i;
535 int csz = 0;
55624204 536
285f2dda
S		 537 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
538 if (!ah)
539 return -ENOMEM;
540
541 ah->hw_version.devid = devid;
542 ah->hw_version.subsysid = subsysid;
543 sc->sc_ah = ah;
544
545 common = ath9k_hw_common(ah);
546 common->ops = &ath9k_common_ops;
547 common->bus_ops = bus_ops;
548 common->ah = ah;
549 common->hw = sc->hw;
550 common->priv = sc;
551 common->debug_mask = ath9k_debug;
552
553 spin_lock_init(&sc->wiphy_lock);
554 spin_lock_init(&sc->sc_resetlock);
555 spin_lock_init(&sc->sc_serial_rw);
556 spin_lock_init(&sc->sc_pm_lock);
557 mutex_init(&sc->mutex);
558 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
559 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
560 (unsigned long)sc);
561
562 /*
563 * Cache line size is used to size and align various
564 * structures used to communicate with the hardware.
565 */
566 ath_read_cachesize(common, &csz);
567 common->cachelsz = csz << 2; /* convert to bytes */
568
569 ret = ath9k_hw_init(ah);
570 if (ret) {
571 ath_print(common, ATH_DBG_FATAL,
572 "Unable to initialize hardware; "
573 "initialization status: %d\n", ret);
574 goto err_hw;
55624204
S		 575 }
576
285f2dda
S		 577 ret = ath9k_init_debug(ah);
578 if (ret) {
579 ath_print(common, ATH_DBG_FATAL,
580 "Unable to create debugfs files\n");
581 goto err_debug;
55624204
S		 582 }
583
285f2dda
S		 584 ret = ath9k_init_queues(sc);
585 if (ret)
586 goto err_queues;
587
588 ret = ath9k_init_btcoex(sc);
589 if (ret)
590 goto err_btcoex;
591
592 ath9k_init_crypto(sc);
593 ath9k_init_channels_rates(sc);
594 ath9k_init_misc(sc);
595
55624204 596 return 0;
285f2dda
S		 597
598err_btcoex:
55624204
S		 599 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
600 if (ATH_TXQ_SETUP(sc, i))
601 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
285f2dda
S		 602err_queues:
603 ath9k_exit_debug(ah);
604err_debug:
605 ath9k_hw_deinit(ah);
606err_hw:
607 tasklet_kill(&sc->intr_tq);
608 tasklet_kill(&sc->bcon_tasklet);
55624204 609
285f2dda
S		 610 kfree(ah);
611 sc->sc_ah = NULL;
612
613 return ret;
55624204
S		 614}
615
285f2dda 616void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
55624204 617{
285f2dda
S		 618 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
619
55624204
S		 620 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
621 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
622 IEEE80211_HW_SIGNAL_DBM |
55624204
S		 623 IEEE80211_HW_SUPPORTS_PS |
624 IEEE80211_HW_PS_NULLFUNC_STACK |
625 IEEE80211_HW_SPECTRUM_MGMT;
626
5ffaf8a3
LR		 627 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
628 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
629
55624204
S		 630 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
631 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
632
633 hw->wiphy->interface_modes =
634 BIT(NL80211_IFTYPE_AP) |
635 BIT(NL80211_IFTYPE_STATION) |
636 BIT(NL80211_IFTYPE_ADHOC) |
637 BIT(NL80211_IFTYPE_MESH_POINT);
638
639 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
640
641 hw->queues = 4;
642 hw->max_rates = 4;
643 hw->channel_change_time = 5000;
644 hw->max_listen_interval = 10;
65896510 645 hw->max_rate_tries = 10;
55624204
S		 646 hw->sta_data_size = sizeof(struct ath_node);
647 hw->vif_data_size = sizeof(struct ath_vif);
648
649 hw->rate_control_algorithm = "ath9k_rate_control";
650
651 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
652 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
653 &sc->sbands[IEEE80211_BAND_2GHZ];
654 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
655 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
656 &sc->sbands[IEEE80211_BAND_5GHZ];
285f2dda
S		 657
658 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
659 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
660 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
661 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
662 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
663 }
664
665 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
55624204
S		 666}
667
285f2dda 668int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
55624204
S		 669 const struct ath_bus_ops *bus_ops)
670{
671 struct ieee80211_hw *hw = sc->hw;
672 struct ath_common *common;
673 struct ath_hw *ah;
285f2dda 674 int error = 0;
55624204
S		 675 struct ath_regulatory *reg;
676
285f2dda
S		 677 /* Bring up device */
678 error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
55624204 679 if (error != 0)
285f2dda 680 goto error_init;
55624204
S		 681
682 ah = sc->sc_ah;
683 common = ath9k_hw_common(ah);
285f2dda 684 ath9k_set_hw_capab(sc, hw);
55624204 685
285f2dda 686 /* Initialize regulatory */
55624204
S		 687 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
688 ath9k_reg_notifier);
689 if (error)
285f2dda 690 goto error_regd;
55624204
S		 691
692 reg = &common->regulatory;
693
285f2dda 694 /* Setup TX DMA */
55624204
S		 695 error = ath_tx_init(sc, ATH_TXBUF);
696 if (error != 0)
285f2dda 697 goto error_tx;
55624204 698
285f2dda 699 /* Setup RX DMA */
55624204
S		 700 error = ath_rx_init(sc, ATH_RXBUF);
701 if (error != 0)
285f2dda 702 goto error_rx;
55624204 703
285f2dda 704 /* Register with mac80211 */
55624204 705 error = ieee80211_register_hw(hw);
285f2dda
S		 706 if (error)
707 goto error_register;
55624204 708
285f2dda 709 /* Handle world regulatory */
55624204
S		 710 if (!ath_is_world_regd(reg)) {
711 error = regulatory_hint(hw->wiphy, reg->alpha2);
712 if (error)
285f2dda 713 goto error_world;
55624204
S		 714 }
715
285f2dda
S		 716 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
717 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
718 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
55624204 719
285f2dda 720 ath_init_leds(sc);
55624204
S		 721 ath_start_rfkill_poll(sc);
722
723 return 0;
724
285f2dda
S		 725error_world:
726 ieee80211_unregister_hw(hw);
727error_register:
728 ath_rx_cleanup(sc);
729error_rx:
730 ath_tx_cleanup(sc);
731error_tx:
732 /* Nothing */
733error_regd:
734 ath9k_deinit_softc(sc);
735error_init:
55624204
S		 736 return error;
737}
738
739/*****************************/
740/* De-Initialization */
741/*****************************/
742
285f2dda 743static void ath9k_deinit_softc(struct ath_softc *sc)
55624204 744{
285f2dda 745 int i = 0;
55624204 746
285f2dda
S		 747 if ((sc->btcoex.no_stomp_timer) &&
748 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
749 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
55624204 750
285f2dda
S		 751 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
752 if (ATH_TXQ_SETUP(sc, i))
753 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
754
755 ath9k_exit_debug(sc->sc_ah);
756 ath9k_hw_deinit(sc->sc_ah);
757
758 tasklet_kill(&sc->intr_tq);
759 tasklet_kill(&sc->bcon_tasklet);
55624204
S		 760}
761
285f2dda 762void ath9k_deinit_device(struct ath_softc *sc)
55624204
S		 763{
764 struct ieee80211_hw *hw = sc->hw;
55624204
S		 765 int i = 0;
766
767 ath9k_ps_wakeup(sc);
768
55624204 769 wiphy_rfkill_stop_polling(sc->hw->wiphy);
285f2dda 770 ath_deinit_leds(sc);
55624204
S		 771
772 for (i = 0; i < sc->num_sec_wiphy; i++) {
773 struct ath_wiphy *aphy = sc->sec_wiphy[i];
774 if (aphy == NULL)
775 continue;
776 sc->sec_wiphy[i] = NULL;
777 ieee80211_unregister_hw(aphy->hw);
778 ieee80211_free_hw(aphy->hw);
779 }
285f2dda
S		 780 kfree(sc->sec_wiphy);
781
55624204
S		 782 ieee80211_unregister_hw(hw);
783 ath_rx_cleanup(sc);
784 ath_tx_cleanup(sc);
285f2dda 785 ath9k_deinit_softc(sc);
55624204
S		 786}
787
788void ath_descdma_cleanup(struct ath_softc *sc,
789 struct ath_descdma *dd,
790 struct list_head *head)
791{
792 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
793 dd->dd_desc_paddr);
794
795 INIT_LIST_HEAD(head);
796 kfree(dd->dd_bufptr);
797 memset(dd, 0, sizeof(*dd));
798}
799
55624204
S		 800/************************/
801/* Module Hooks */
802/************************/
803
804static int __init ath9k_init(void)
805{
806 int error;
807
808 /* Register rate control algorithm */
809 error = ath_rate_control_register();
810 if (error != 0) {
811 printk(KERN_ERR
812 "ath9k: Unable to register rate control "
813 "algorithm: %d\n",
814 error);
815 goto err_out;
816 }
817
818 error = ath9k_debug_create_root();
819 if (error) {
820 printk(KERN_ERR
821 "ath9k: Unable to create debugfs root: %d\n",
822 error);
823 goto err_rate_unregister;
824 }
825
826 error = ath_pci_init();
827 if (error < 0) {
828 printk(KERN_ERR
829 "ath9k: No PCI devices found, driver not installed.\n");
830 error = -ENODEV;
831 goto err_remove_root;
832 }
833
834 error = ath_ahb_init();
835 if (error < 0) {
836 error = -ENODEV;
837 goto err_pci_exit;
838 }
839
840 return 0;
841
842 err_pci_exit:
843 ath_pci_exit();
844
845 err_remove_root:
846 ath9k_debug_remove_root();
847 err_rate_unregister:
848 ath_rate_control_unregister();
849 err_out:
850 return error;
851}
852module_init(ath9k_init);
853
854static void __exit ath9k_exit(void)
855{
856 ath_ahb_exit();
857 ath_pci_exit();
858 ath9k_debug_remove_root();
859 ath_rate_control_unregister();
860 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
861}
862module_exit(ath9k_exit);
Linux kernel - Deliverables
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