Commit | Line | Data |
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55624204 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
55624204 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
516304b0 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
b7f080cf | 19 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
6fb1b1e1 | 21 | #include <linux/ath9k_platform.h> |
9d9779e7 | 22 | #include <linux/module.h> |
e93d083f | 23 | #include <linux/relay.h> |
b0a1ae97 | 24 | #include <net/ieee80211_radiotap.h> |
5a0e3ad6 | 25 | |
55624204 S |
26 | #include "ath9k.h" |
27 | ||
ab5c4f71 GJ |
28 | struct ath9k_eeprom_ctx { |
29 | struct completion complete; | |
30 | struct ath_hw *ah; | |
31 | }; | |
32 | ||
55624204 S |
33 | static char *dev_info = "ath9k"; |
34 | ||
35 | MODULE_AUTHOR("Atheros Communications"); | |
36 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
37 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
38 | MODULE_LICENSE("Dual BSD/GPL"); | |
39 | ||
40 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
41 | module_param_named(debug, ath9k_debug, uint, 0); | |
42 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
43 | ||
3e6109c5 JL |
44 | int ath9k_modparam_nohwcrypt; |
45 | module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); | |
55624204 S |
46 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); |
47 | ||
93dbbcc4 | 48 | int led_blink; |
9a75c2ff VN |
49 | module_param_named(blink, led_blink, int, 0444); |
50 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); | |
51 | ||
8f5dcb1c VT |
52 | static int ath9k_btcoex_enable; |
53 | module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); | |
54 | MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); | |
55 | ||
63081305 SM |
56 | static int ath9k_bt_ant_diversity; |
57 | module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); | |
58 | MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); | |
e09f2dc7 | 59 | |
8298383c SM |
60 | static int ath9k_ps_enable; |
61 | module_param_named(ps_enable, ath9k_ps_enable, int, 0444); | |
62 | MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave"); | |
63 | ||
d584747b | 64 | bool is_ath9k_unloaded; |
55624204 S |
65 | /* We use the hw_value as an index into our private channel structure */ |
66 | ||
67 | #define CHAN2G(_freq, _idx) { \ | |
b1c1d000 | 68 | .band = IEEE80211_BAND_2GHZ, \ |
55624204 S |
69 | .center_freq = (_freq), \ |
70 | .hw_value = (_idx), \ | |
71 | .max_power = 20, \ | |
72 | } | |
73 | ||
74 | #define CHAN5G(_freq, _idx) { \ | |
75 | .band = IEEE80211_BAND_5GHZ, \ | |
76 | .center_freq = (_freq), \ | |
77 | .hw_value = (_idx), \ | |
78 | .max_power = 20, \ | |
79 | } | |
80 | ||
81 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
82 | * on 5 MHz steps, we support the channels which we know | |
83 | * we have calibration data for all cards though to make | |
84 | * this static */ | |
f209f529 | 85 | static const struct ieee80211_channel ath9k_2ghz_chantable[] = { |
55624204 S |
86 | CHAN2G(2412, 0), /* Channel 1 */ |
87 | CHAN2G(2417, 1), /* Channel 2 */ | |
88 | CHAN2G(2422, 2), /* Channel 3 */ | |
89 | CHAN2G(2427, 3), /* Channel 4 */ | |
90 | CHAN2G(2432, 4), /* Channel 5 */ | |
91 | CHAN2G(2437, 5), /* Channel 6 */ | |
92 | CHAN2G(2442, 6), /* Channel 7 */ | |
93 | CHAN2G(2447, 7), /* Channel 8 */ | |
94 | CHAN2G(2452, 8), /* Channel 9 */ | |
95 | CHAN2G(2457, 9), /* Channel 10 */ | |
96 | CHAN2G(2462, 10), /* Channel 11 */ | |
97 | CHAN2G(2467, 11), /* Channel 12 */ | |
98 | CHAN2G(2472, 12), /* Channel 13 */ | |
99 | CHAN2G(2484, 13), /* Channel 14 */ | |
100 | }; | |
101 | ||
102 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
103 | * on 5 MHz steps, we support the channels which we know | |
104 | * we have calibration data for all cards though to make | |
105 | * this static */ | |
f209f529 | 106 | static const struct ieee80211_channel ath9k_5ghz_chantable[] = { |
55624204 S |
107 | /* _We_ call this UNII 1 */ |
108 | CHAN5G(5180, 14), /* Channel 36 */ | |
109 | CHAN5G(5200, 15), /* Channel 40 */ | |
110 | CHAN5G(5220, 16), /* Channel 44 */ | |
111 | CHAN5G(5240, 17), /* Channel 48 */ | |
112 | /* _We_ call this UNII 2 */ | |
113 | CHAN5G(5260, 18), /* Channel 52 */ | |
114 | CHAN5G(5280, 19), /* Channel 56 */ | |
115 | CHAN5G(5300, 20), /* Channel 60 */ | |
116 | CHAN5G(5320, 21), /* Channel 64 */ | |
117 | /* _We_ call this "Middle band" */ | |
118 | CHAN5G(5500, 22), /* Channel 100 */ | |
119 | CHAN5G(5520, 23), /* Channel 104 */ | |
120 | CHAN5G(5540, 24), /* Channel 108 */ | |
121 | CHAN5G(5560, 25), /* Channel 112 */ | |
122 | CHAN5G(5580, 26), /* Channel 116 */ | |
123 | CHAN5G(5600, 27), /* Channel 120 */ | |
124 | CHAN5G(5620, 28), /* Channel 124 */ | |
125 | CHAN5G(5640, 29), /* Channel 128 */ | |
126 | CHAN5G(5660, 30), /* Channel 132 */ | |
127 | CHAN5G(5680, 31), /* Channel 136 */ | |
128 | CHAN5G(5700, 32), /* Channel 140 */ | |
129 | /* _We_ call this UNII 3 */ | |
130 | CHAN5G(5745, 33), /* Channel 149 */ | |
131 | CHAN5G(5765, 34), /* Channel 153 */ | |
132 | CHAN5G(5785, 35), /* Channel 157 */ | |
133 | CHAN5G(5805, 36), /* Channel 161 */ | |
134 | CHAN5G(5825, 37), /* Channel 165 */ | |
135 | }; | |
136 | ||
137 | /* Atheros hardware rate code addition for short premble */ | |
138 | #define SHPCHECK(__hw_rate, __flags) \ | |
139 | ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) | |
140 | ||
141 | #define RATE(_bitrate, _hw_rate, _flags) { \ | |
142 | .bitrate = (_bitrate), \ | |
143 | .flags = (_flags), \ | |
144 | .hw_value = (_hw_rate), \ | |
145 | .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ | |
146 | } | |
147 | ||
148 | static struct ieee80211_rate ath9k_legacy_rates[] = { | |
149 | RATE(10, 0x1b, 0), | |
150 | RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), | |
151 | RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), | |
152 | RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), | |
67a55330 SW |
153 | RATE(60, 0x0b, (IEEE80211_RATE_SUPPORTS_5MHZ | |
154 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
155 | RATE(90, 0x0f, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
156 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
157 | RATE(120, 0x0a, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
158 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
159 | RATE(180, 0x0e, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
160 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
161 | RATE(240, 0x09, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
162 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
163 | RATE(360, 0x0d, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
164 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
165 | RATE(480, 0x08, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
166 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
167 | RATE(540, 0x0c, (IEEE80211_RATE_SUPPORTS_5MHZ | | |
168 | IEEE80211_RATE_SUPPORTS_10MHZ)), | |
55624204 S |
169 | }; |
170 | ||
0cf55c21 FF |
171 | #ifdef CONFIG_MAC80211_LEDS |
172 | static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { | |
173 | { .throughput = 0 * 1024, .blink_time = 334 }, | |
174 | { .throughput = 1 * 1024, .blink_time = 260 }, | |
175 | { .throughput = 5 * 1024, .blink_time = 220 }, | |
176 | { .throughput = 10 * 1024, .blink_time = 190 }, | |
177 | { .throughput = 20 * 1024, .blink_time = 170 }, | |
178 | { .throughput = 50 * 1024, .blink_time = 150 }, | |
179 | { .throughput = 70 * 1024, .blink_time = 130 }, | |
180 | { .throughput = 100 * 1024, .blink_time = 110 }, | |
181 | { .throughput = 200 * 1024, .blink_time = 80 }, | |
182 | { .throughput = 300 * 1024, .blink_time = 50 }, | |
183 | }; | |
184 | #endif | |
185 | ||
285f2dda | 186 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 S |
187 | |
188 | /* | |
189 | * Read and write, they both share the same lock. We do this to serialize | |
190 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
191 | * as the FIFO on these devices can only accept sanely 2 requests. | |
192 | */ | |
193 | ||
194 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
195 | { | |
196 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
197 | struct ath_common *common = ath9k_hw_common(ah); | |
198 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
199 | ||
f3eef645 | 200 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
201 | unsigned long flags; |
202 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
203 | iowrite32(val, sc->mem + reg_offset); | |
204 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
205 | } else | |
206 | iowrite32(val, sc->mem + reg_offset); | |
207 | } | |
208 | ||
209 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
210 | { | |
211 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
212 | struct ath_common *common = ath9k_hw_common(ah); | |
213 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
214 | u32 val; | |
215 | ||
f3eef645 | 216 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
217 | unsigned long flags; |
218 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
219 | val = ioread32(sc->mem + reg_offset); | |
220 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
221 | } else | |
222 | val = ioread32(sc->mem + reg_offset); | |
223 | return val; | |
224 | } | |
225 | ||
5479de6e RM |
226 | static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, |
227 | u32 set, u32 clr) | |
228 | { | |
229 | u32 val; | |
230 | ||
231 | val = ioread32(sc->mem + reg_offset); | |
232 | val &= ~clr; | |
233 | val |= set; | |
234 | iowrite32(val, sc->mem + reg_offset); | |
235 | ||
236 | return val; | |
237 | } | |
238 | ||
845e03c9 FF |
239 | static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) |
240 | { | |
241 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
242 | struct ath_common *common = ath9k_hw_common(ah); | |
243 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
244 | unsigned long uninitialized_var(flags); | |
245 | u32 val; | |
246 | ||
f3eef645 | 247 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
845e03c9 | 248 | spin_lock_irqsave(&sc->sc_serial_rw, flags); |
5479de6e | 249 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); |
845e03c9 | 250 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); |
5479de6e RM |
251 | } else |
252 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); | |
845e03c9 FF |
253 | |
254 | return val; | |
255 | } | |
256 | ||
55624204 S |
257 | /**************************/ |
258 | /* Initialization */ | |
259 | /**************************/ | |
260 | ||
261 | static void setup_ht_cap(struct ath_softc *sc, | |
262 | struct ieee80211_sta_ht_cap *ht_info) | |
263 | { | |
3bb065a7 FF |
264 | struct ath_hw *ah = sc->sc_ah; |
265 | struct ath_common *common = ath9k_hw_common(ah); | |
55624204 | 266 | u8 tx_streams, rx_streams; |
3bb065a7 | 267 | int i, max_streams; |
55624204 S |
268 | |
269 | ht_info->ht_supported = true; | |
270 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
271 | IEEE80211_HT_CAP_SM_PS | | |
272 | IEEE80211_HT_CAP_SGI_40 | | |
273 | IEEE80211_HT_CAP_DSSSCCK40; | |
274 | ||
b0a33448 LR |
275 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) |
276 | ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; | |
277 | ||
6473d24d VT |
278 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) |
279 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
280 | ||
55624204 S |
281 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
282 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
283 | ||
e41db61d | 284 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) |
7f1c7a6a | 285 | max_streams = 1; |
e7104195 MSS |
286 | else if (AR_SREV_9462(ah)) |
287 | max_streams = 2; | |
7f1c7a6a | 288 | else if (AR_SREV_9300_20_OR_LATER(ah)) |
3bb065a7 FF |
289 | max_streams = 3; |
290 | else | |
291 | max_streams = 2; | |
292 | ||
7a37081e | 293 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
074a8c0d FF |
294 | if (max_streams >= 2) |
295 | ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; | |
296 | ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); | |
297 | } | |
298 | ||
55624204 S |
299 | /* set up supported mcs set */ |
300 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
82b2d334 FF |
301 | tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); |
302 | rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); | |
3bb065a7 | 303 | |
d2182b69 | 304 | ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n", |
226afe68 | 305 | tx_streams, rx_streams); |
55624204 S |
306 | |
307 | if (tx_streams != rx_streams) { | |
55624204 S |
308 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
309 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
310 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
311 | } | |
312 | ||
3bb065a7 FF |
313 | for (i = 0; i < rx_streams; i++) |
314 | ht_info->mcs.rx_mask[i] = 0xff; | |
55624204 S |
315 | |
316 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; | |
317 | } | |
318 | ||
0c0280bd LR |
319 | static void ath9k_reg_notifier(struct wiphy *wiphy, |
320 | struct regulatory_request *request) | |
55624204 S |
321 | { |
322 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
9ac58615 | 323 | struct ath_softc *sc = hw->priv; |
687f545e RM |
324 | struct ath_hw *ah = sc->sc_ah; |
325 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
687f545e | 326 | |
0c0280bd | 327 | ath_reg_notifier_apply(wiphy, request, reg); |
687f545e RM |
328 | |
329 | /* Set tx power */ | |
330 | if (ah->curchan) { | |
331 | sc->config.txpowlimit = 2 * ah->curchan->chan->max_power; | |
332 | ath9k_ps_wakeup(sc); | |
333 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); | |
334 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; | |
73e4937d ZK |
335 | /* synchronize DFS detector if regulatory domain changed */ |
336 | if (sc->dfs_detector != NULL) | |
337 | sc->dfs_detector->set_dfs_domain(sc->dfs_detector, | |
338 | request->dfs_region); | |
687f545e RM |
339 | ath9k_ps_restore(sc); |
340 | } | |
55624204 S |
341 | } |
342 | ||
343 | /* | |
344 | * This function will allocate both the DMA descriptor structure, and the | |
345 | * buffers it contains. These are used to contain the descriptors used | |
346 | * by the system. | |
347 | */ | |
348 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
349 | struct list_head *head, const char *name, | |
4adfcded | 350 | int nbuf, int ndesc, bool is_tx) |
55624204 | 351 | { |
55624204 | 352 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4adfcded | 353 | u8 *ds; |
b81950b1 | 354 | int i, bsize, desc_len; |
55624204 | 355 | |
d2182b69 | 356 | ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
226afe68 | 357 | name, nbuf, ndesc); |
55624204 S |
358 | |
359 | INIT_LIST_HEAD(head); | |
4adfcded VT |
360 | |
361 | if (is_tx) | |
362 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
363 | else | |
364 | desc_len = sizeof(struct ath_desc); | |
365 | ||
55624204 | 366 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 367 | if ((desc_len % 4) != 0) { |
3800276a | 368 | ath_err(common, "ath_desc not DWORD aligned\n"); |
4adfcded | 369 | BUG_ON((desc_len % 4) != 0); |
b81950b1 | 370 | return -ENOMEM; |
55624204 S |
371 | } |
372 | ||
4adfcded | 373 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
374 | |
375 | /* | |
376 | * Need additional DMA memory because we can't use | |
377 | * descriptors that cross the 4K page boundary. Assume | |
378 | * one skipped descriptor per 4K page. | |
379 | */ | |
380 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
381 | u32 ndesc_skipped = | |
382 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
383 | u32 dma_len; | |
384 | ||
385 | while (ndesc_skipped) { | |
4adfcded | 386 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
387 | dd->dd_desc_len += dma_len; |
388 | ||
389 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 390 | } |
55624204 S |
391 | } |
392 | ||
393 | /* allocate descriptors */ | |
b81950b1 FF |
394 | dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, |
395 | &dd->dd_desc_paddr, GFP_KERNEL); | |
396 | if (!dd->dd_desc) | |
397 | return -ENOMEM; | |
398 | ||
4adfcded | 399 | ds = (u8 *) dd->dd_desc; |
d2182b69 | 400 | ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
226afe68 JP |
401 | name, ds, (u32) dd->dd_desc_len, |
402 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
55624204 S |
403 | |
404 | /* allocate buffers */ | |
1a04d59d FF |
405 | if (is_tx) { |
406 | struct ath_buf *bf; | |
407 | ||
408 | bsize = sizeof(struct ath_buf) * nbuf; | |
409 | bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); | |
410 | if (!bf) | |
411 | return -ENOMEM; | |
412 | ||
413 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { | |
414 | bf->bf_desc = ds; | |
415 | bf->bf_daddr = DS2PHYS(dd, ds); | |
416 | ||
417 | if (!(sc->sc_ah->caps.hw_caps & | |
418 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
419 | /* | |
420 | * Skip descriptor addresses which can cause 4KB | |
421 | * boundary crossing (addr + length) with a 32 dword | |
422 | * descriptor fetch. | |
423 | */ | |
424 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
425 | BUG_ON((caddr_t) bf->bf_desc >= | |
426 | ((caddr_t) dd->dd_desc + | |
427 | dd->dd_desc_len)); | |
428 | ||
429 | ds += (desc_len * ndesc); | |
430 | bf->bf_desc = ds; | |
431 | bf->bf_daddr = DS2PHYS(dd, ds); | |
432 | } | |
433 | } | |
434 | list_add_tail(&bf->list, head); | |
435 | } | |
436 | } else { | |
437 | struct ath_rxbuf *bf; | |
438 | ||
439 | bsize = sizeof(struct ath_rxbuf) * nbuf; | |
440 | bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); | |
441 | if (!bf) | |
442 | return -ENOMEM; | |
443 | ||
444 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { | |
445 | bf->bf_desc = ds; | |
446 | bf->bf_daddr = DS2PHYS(dd, ds); | |
447 | ||
448 | if (!(sc->sc_ah->caps.hw_caps & | |
449 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
450 | /* | |
451 | * Skip descriptor addresses which can cause 4KB | |
452 | * boundary crossing (addr + length) with a 32 dword | |
453 | * descriptor fetch. | |
454 | */ | |
455 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
456 | BUG_ON((caddr_t) bf->bf_desc >= | |
457 | ((caddr_t) dd->dd_desc + | |
458 | dd->dd_desc_len)); | |
459 | ||
460 | ds += (desc_len * ndesc); | |
461 | bf->bf_desc = ds; | |
462 | bf->bf_daddr = DS2PHYS(dd, ds); | |
463 | } | |
55624204 | 464 | } |
1a04d59d | 465 | list_add_tail(&bf->list, head); |
55624204 | 466 | } |
55624204 S |
467 | } |
468 | return 0; | |
55624204 S |
469 | } |
470 | ||
285f2dda S |
471 | static int ath9k_init_queues(struct ath_softc *sc) |
472 | { | |
285f2dda S |
473 | int i = 0; |
474 | ||
285f2dda | 475 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 476 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
477 | ath_cabq_update(sc); |
478 | ||
f2c7a793 FF |
479 | sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); |
480 | ||
bea843c7 | 481 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
066dae93 | 482 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); |
60f2d1d5 | 483 | sc->tx.txq_map[i]->mac80211_qnum = i; |
7702e788 | 484 | sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; |
60f2d1d5 | 485 | } |
285f2dda | 486 | return 0; |
285f2dda S |
487 | } |
488 | ||
f209f529 | 489 | static int ath9k_init_channels_rates(struct ath_softc *sc) |
285f2dda | 490 | { |
f209f529 FF |
491 | void *channels; |
492 | ||
cac4220b FF |
493 | BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + |
494 | ARRAY_SIZE(ath9k_5ghz_chantable) != | |
495 | ATH9K_NUM_CHANNELS); | |
496 | ||
d4659912 | 497 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { |
b81950b1 | 498 | channels = devm_kzalloc(sc->dev, |
f209f529 FF |
499 | sizeof(ath9k_2ghz_chantable), GFP_KERNEL); |
500 | if (!channels) | |
501 | return -ENOMEM; | |
502 | ||
b81950b1 FF |
503 | memcpy(channels, ath9k_2ghz_chantable, |
504 | sizeof(ath9k_2ghz_chantable)); | |
f209f529 | 505 | sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; |
285f2dda S |
506 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; |
507 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = | |
508 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
509 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; | |
510 | sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = | |
511 | ARRAY_SIZE(ath9k_legacy_rates); | |
55624204 S |
512 | } |
513 | ||
d4659912 | 514 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { |
b81950b1 | 515 | channels = devm_kzalloc(sc->dev, |
f209f529 | 516 | sizeof(ath9k_5ghz_chantable), GFP_KERNEL); |
b81950b1 | 517 | if (!channels) |
f209f529 | 518 | return -ENOMEM; |
f209f529 | 519 | |
b81950b1 FF |
520 | memcpy(channels, ath9k_5ghz_chantable, |
521 | sizeof(ath9k_5ghz_chantable)); | |
f209f529 | 522 | sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; |
285f2dda S |
523 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; |
524 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = | |
525 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
526 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
527 | ath9k_legacy_rates + 4; | |
528 | sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = | |
529 | ARRAY_SIZE(ath9k_legacy_rates) - 4; | |
530 | } | |
f209f529 | 531 | return 0; |
285f2dda | 532 | } |
55624204 | 533 | |
285f2dda S |
534 | static void ath9k_init_misc(struct ath_softc *sc) |
535 | { | |
536 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
537 | int i = 0; | |
3d4e20f2 | 538 | |
285f2dda | 539 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); |
55624204 | 540 | |
aaa1ec46 | 541 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
55624204 | 542 | sc->config.txpowlimit = ATH_TXPOWER_MAX; |
364734fa | 543 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
285f2dda | 544 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 545 | |
7545daf4 | 546 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) |
55624204 | 547 | sc->beacon.bslot[i] = NULL; |
102885a5 VT |
548 | |
549 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
550 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
04ccd4a1 SW |
551 | |
552 | sc->spec_config.enabled = 0; | |
553 | sc->spec_config.short_repeat = true; | |
554 | sc->spec_config.count = 8; | |
555 | sc->spec_config.endless = false; | |
556 | sc->spec_config.period = 0xFF; | |
557 | sc->spec_config.fft_period = 0xF; | |
285f2dda | 558 | } |
55624204 | 559 | |
0f978bfa | 560 | static void ath9k_init_pcoem_platform(struct ath_softc *sc) |
9b60b64b SM |
561 | { |
562 | struct ath_hw *ah = sc->sc_ah; | |
3f2da955 | 563 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
9b60b64b SM |
564 | struct ath_common *common = ath9k_hw_common(ah); |
565 | ||
566 | if (common->bus_ops->ath_bus_type != ATH_PCI) | |
567 | return; | |
568 | ||
e861ef52 SM |
569 | if (sc->driver_data & (ATH9K_PCI_CUS198 | |
570 | ATH9K_PCI_CUS230)) { | |
9b60b64b SM |
571 | ah->config.xlna_gpio = 9; |
572 | ah->config.xatten_margin_cfg = true; | |
e083a42e | 573 | ah->config.alt_mingainidx = true; |
31fd216d | 574 | ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; |
3afa6b4f SM |
575 | sc->ant_comb.low_rssi_thresh = 20; |
576 | sc->ant_comb.fast_div_bias = 3; | |
9b60b64b | 577 | |
e861ef52 SM |
578 | ath_info(common, "Set parameters for %s\n", |
579 | (sc->driver_data & ATH9K_PCI_CUS198) ? | |
580 | "CUS198" : "CUS230"); | |
3f2da955 SM |
581 | } |
582 | ||
583 | if (sc->driver_data & ATH9K_PCI_CUS217) | |
12eea640 | 584 | ath_info(common, "CUS217 card detected\n"); |
3f2da955 | 585 | |
10631336 SM |
586 | if (sc->driver_data & ATH9K_PCI_CUS252) |
587 | ath_info(common, "CUS252 card detected\n"); | |
588 | ||
3fcdd0a1 SM |
589 | if (sc->driver_data & ATH9K_PCI_AR9565_1ANT) |
590 | ath_info(common, "WB335 1-ANT card detected\n"); | |
591 | ||
592 | if (sc->driver_data & ATH9K_PCI_AR9565_2ANT) | |
593 | ath_info(common, "WB335 2-ANT card detected\n"); | |
594 | ||
4dd35640 SM |
595 | if (sc->driver_data & ATH9K_PCI_KILLER) |
596 | ath_info(common, "Killer Wireless card detected\n"); | |
597 | ||
3fcdd0a1 SM |
598 | /* |
599 | * Some WB335 cards do not support antenna diversity. Since | |
600 | * we use a hardcoded value for AR9565 instead of using the | |
601 | * EEPROM/OTP data, remove the combining feature from | |
602 | * the HW capabilities bitmap. | |
603 | */ | |
604 | if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { | |
605 | if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV)) | |
606 | pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; | |
607 | } | |
608 | ||
3f2da955 SM |
609 | if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { |
610 | pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; | |
611 | ath_info(common, "Set BT/WLAN RX diversity capability\n"); | |
9b60b64b | 612 | } |
d1ae25a0 SM |
613 | |
614 | if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { | |
615 | ah->config.pcie_waen = 0x0040473b; | |
616 | ath_info(common, "Enable WAR for ASPM D3/L1\n"); | |
617 | } | |
2d22c7dd SM |
618 | |
619 | if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { | |
620 | ah->config.no_pll_pwrsave = true; | |
621 | ath_info(common, "Disable PLL PowerSave\n"); | |
622 | } | |
9b60b64b SM |
623 | } |
624 | ||
ab5c4f71 GJ |
625 | static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, |
626 | void *ctx) | |
627 | { | |
628 | struct ath9k_eeprom_ctx *ec = ctx; | |
629 | ||
630 | if (eeprom_blob) | |
631 | ec->ah->eeprom_blob = eeprom_blob; | |
632 | ||
633 | complete(&ec->complete); | |
634 | } | |
635 | ||
636 | static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) | |
637 | { | |
638 | struct ath9k_eeprom_ctx ec; | |
639 | struct ath_hw *ah = ah = sc->sc_ah; | |
640 | int err; | |
641 | ||
642 | /* try to load the EEPROM content asynchronously */ | |
643 | init_completion(&ec.complete); | |
644 | ec.ah = sc->sc_ah; | |
645 | ||
646 | err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, | |
647 | &ec, ath9k_eeprom_request_cb); | |
648 | if (err < 0) { | |
649 | ath_err(ath9k_hw_common(ah), | |
650 | "EEPROM request failed\n"); | |
651 | return err; | |
652 | } | |
653 | ||
654 | wait_for_completion(&ec.complete); | |
655 | ||
656 | if (!ah->eeprom_blob) { | |
657 | ath_err(ath9k_hw_common(ah), | |
658 | "Unable to load EEPROM file %s\n", name); | |
659 | return -EINVAL; | |
660 | } | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
665 | static void ath9k_eeprom_release(struct ath_softc *sc) | |
666 | { | |
667 | release_firmware(sc->sc_ah->eeprom_blob); | |
668 | } | |
669 | ||
0f978bfa SM |
670 | static int ath9k_init_soc_platform(struct ath_softc *sc) |
671 | { | |
672 | struct ath9k_platform_data *pdata = sc->dev->platform_data; | |
673 | struct ath_hw *ah = sc->sc_ah; | |
674 | int ret = 0; | |
675 | ||
676 | if (!pdata) | |
677 | return 0; | |
678 | ||
679 | if (pdata->eeprom_name) { | |
680 | ret = ath9k_eeprom_request(sc, pdata->eeprom_name); | |
681 | if (ret) | |
682 | return ret; | |
683 | } | |
684 | ||
685 | if (pdata->tx_gain_buffalo) | |
686 | ah->config.tx_gain_buffalo = true; | |
687 | ||
688 | return ret; | |
689 | } | |
690 | ||
eb93e891 | 691 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, |
285f2dda S |
692 | const struct ath_bus_ops *bus_ops) |
693 | { | |
6fb1b1e1 | 694 | struct ath9k_platform_data *pdata = sc->dev->platform_data; |
285f2dda | 695 | struct ath_hw *ah = NULL; |
3f2da955 | 696 | struct ath9k_hw_capabilities *pCap; |
285f2dda S |
697 | struct ath_common *common; |
698 | int ret = 0, i; | |
699 | int csz = 0; | |
55624204 | 700 | |
b81950b1 | 701 | ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); |
285f2dda S |
702 | if (!ah) |
703 | return -ENOMEM; | |
704 | ||
c1b976d2 | 705 | ah->dev = sc->dev; |
233536e1 | 706 | ah->hw = sc->hw; |
285f2dda | 707 | ah->hw_version.devid = devid; |
f9f84e96 FF |
708 | ah->reg_ops.read = ath9k_ioread32; |
709 | ah->reg_ops.write = ath9k_iowrite32; | |
845e03c9 | 710 | ah->reg_ops.rmw = ath9k_reg_rmw; |
285f2dda | 711 | sc->sc_ah = ah; |
3f2da955 | 712 | pCap = &ah->caps; |
285f2dda | 713 | |
95a5992e JD |
714 | common = ath9k_hw_common(ah); |
715 | sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); | |
89f927af | 716 | sc->tx99_power = MAX_RATE_POWER + 1; |
10e23181 | 717 | init_waitqueue_head(&sc->tx_wait); |
8e92d3f2 | 718 | |
6de66dd9 | 719 | if (!pdata) { |
a05b5d45 | 720 | ah->ah_flags |= AH_USE_EEPROM; |
6de66dd9 FF |
721 | sc->sc_ah->led_pin = -1; |
722 | } else { | |
723 | sc->sc_ah->gpio_mask = pdata->gpio_mask; | |
724 | sc->sc_ah->gpio_val = pdata->gpio_val; | |
725 | sc->sc_ah->led_pin = pdata->led_pin; | |
f2f5f2a1 | 726 | ah->is_clk_25mhz = pdata->is_clk_25mhz; |
3762561a | 727 | ah->get_mac_revision = pdata->get_mac_revision; |
7d95847c | 728 | ah->external_reset = pdata->external_reset; |
6de66dd9 | 729 | } |
a05b5d45 | 730 | |
f9f84e96 | 731 | common->ops = &ah->reg_ops; |
285f2dda S |
732 | common->bus_ops = bus_ops; |
733 | common->ah = ah; | |
734 | common->hw = sc->hw; | |
735 | common->priv = sc; | |
736 | common->debug_mask = ath9k_debug; | |
8f5dcb1c | 737 | common->btcoex_enabled = ath9k_btcoex_enable == 1; |
05c0be2f | 738 | common->disable_ani = false; |
e09f2dc7 | 739 | |
9b60b64b SM |
740 | /* |
741 | * Platform quirks. | |
742 | */ | |
0f978bfa SM |
743 | ath9k_init_pcoem_platform(sc); |
744 | ||
745 | ret = ath9k_init_soc_platform(sc); | |
746 | if (ret) | |
747 | return ret; | |
9b60b64b | 748 | |
e09f2dc7 | 749 | /* |
3f2da955 SM |
750 | * Enable WLAN/BT RX Antenna diversity only when: |
751 | * | |
7d845871 | 752 | * - BTCOEX is disabled. |
3f2da955 SM |
753 | * - the user manually requests the feature. |
754 | * - the HW cap is set using the platform data. | |
e09f2dc7 | 755 | */ |
7d845871 | 756 | if (!common->btcoex_enabled && ath9k_bt_ant_diversity && |
3f2da955 | 757 | (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) |
63081305 | 758 | common->bt_ant_diversity = 1; |
e09f2dc7 | 759 | |
20b25744 | 760 | spin_lock_init(&common->cc_lock); |
285f2dda S |
761 | spin_lock_init(&sc->sc_serial_rw); |
762 | spin_lock_init(&sc->sc_pm_lock); | |
763 | mutex_init(&sc->mutex); | |
764 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); | |
fb6e252f | 765 | tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, |
285f2dda S |
766 | (unsigned long)sc); |
767 | ||
bf3dac5a | 768 | setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc); |
aaa1ec46 | 769 | INIT_WORK(&sc->hw_reset_work, ath_reset_work); |
aaa1ec46 SM |
770 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); |
771 | INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); | |
aaa1ec46 | 772 | |
285f2dda S |
773 | /* |
774 | * Cache line size is used to size and align various | |
775 | * structures used to communicate with the hardware. | |
776 | */ | |
777 | ath_read_cachesize(common, &csz); | |
778 | common->cachelsz = csz << 2; /* convert to bytes */ | |
779 | ||
d70357d5 | 780 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 781 | ret = ath9k_hw_init(ah); |
d70357d5 | 782 | if (ret) |
285f2dda | 783 | goto err_hw; |
55624204 | 784 | |
6fb1b1e1 FF |
785 | if (pdata && pdata->macaddr) |
786 | memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); | |
787 | ||
285f2dda S |
788 | ret = ath9k_init_queues(sc); |
789 | if (ret) | |
790 | goto err_queues; | |
791 | ||
792 | ret = ath9k_init_btcoex(sc); | |
793 | if (ret) | |
794 | goto err_btcoex; | |
795 | ||
f209f529 FF |
796 | ret = ath9k_init_channels_rates(sc); |
797 | if (ret) | |
798 | goto err_btcoex; | |
799 | ||
f82b4bde | 800 | ath9k_cmn_init_crypto(sc->sc_ah); |
285f2dda | 801 | ath9k_init_misc(sc); |
8f176a3a | 802 | ath_fill_led_pin(sc); |
285f2dda | 803 | |
d09f5f4c SM |
804 | if (common->bus_ops->aspm_init) |
805 | common->bus_ops->aspm_init(common); | |
806 | ||
55624204 | 807 | return 0; |
285f2dda S |
808 | |
809 | err_btcoex: | |
55624204 S |
810 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
811 | if (ATH_TXQ_SETUP(sc, i)) | |
812 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda | 813 | err_queues: |
285f2dda S |
814 | ath9k_hw_deinit(ah); |
815 | err_hw: | |
ab5c4f71 | 816 | ath9k_eeprom_release(sc); |
89f927af | 817 | dev_kfree_skb_any(sc->tx99_skb); |
285f2dda | 818 | return ret; |
55624204 S |
819 | } |
820 | ||
babcbc29 FF |
821 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
822 | { | |
823 | struct ieee80211_supported_band *sband; | |
824 | struct ieee80211_channel *chan; | |
825 | struct ath_hw *ah = sc->sc_ah; | |
0671894f | 826 | struct cfg80211_chan_def chandef; |
babcbc29 FF |
827 | int i; |
828 | ||
829 | sband = &sc->sbands[band]; | |
830 | for (i = 0; i < sband->n_channels; i++) { | |
831 | chan = &sband->channels[i]; | |
832 | ah->curchan = &ah->channels[chan->hw_value]; | |
0671894f | 833 | cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); |
2297f1c7 | 834 | ath9k_cmn_get_channel(sc->hw, ah, &chandef); |
babcbc29 | 835 | ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); |
babcbc29 FF |
836 | } |
837 | } | |
838 | ||
839 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
840 | { | |
841 | struct ath_hw *ah = sc->sc_ah; | |
842 | struct ath9k_channel *curchan = ah->curchan; | |
843 | ||
844 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
845 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); | |
846 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
847 | ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); | |
848 | ||
849 | ah->curchan = curchan; | |
850 | } | |
851 | ||
43c35284 FF |
852 | void ath9k_reload_chainmask_settings(struct ath_softc *sc) |
853 | { | |
854 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)) | |
855 | return; | |
856 | ||
857 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
858 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); | |
859 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
860 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); | |
861 | } | |
862 | ||
20c8e8dc FF |
863 | static const struct ieee80211_iface_limit if_limits[] = { |
864 | { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) | | |
865 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
866 | BIT(NL80211_IFTYPE_WDS) }, | |
867 | { .max = 8, .types = | |
868 | #ifdef CONFIG_MAC80211_MESH | |
869 | BIT(NL80211_IFTYPE_MESH_POINT) | | |
870 | #endif | |
871 | BIT(NL80211_IFTYPE_AP) | | |
872 | BIT(NL80211_IFTYPE_P2P_GO) }, | |
873 | }; | |
874 | ||
e9cdedf6 | 875 | static const struct ieee80211_iface_limit if_dfs_limits[] = { |
3c57e865 | 876 | { .max = 1, .types = BIT(NL80211_IFTYPE_AP) | |
997b179b CYY |
877 | #ifdef CONFIG_MAC80211_MESH |
878 | BIT(NL80211_IFTYPE_MESH_POINT) | | |
879 | #endif | |
3c57e865 | 880 | BIT(NL80211_IFTYPE_ADHOC) }, |
e9cdedf6 ZK |
881 | }; |
882 | ||
883 | static const struct ieee80211_iface_combination if_comb[] = { | |
884 | { | |
885 | .limits = if_limits, | |
886 | .n_limits = ARRAY_SIZE(if_limits), | |
887 | .max_interfaces = 2048, | |
888 | .num_different_channels = 1, | |
889 | .beacon_int_infra_match = true, | |
890 | }, | |
891 | { | |
892 | .limits = if_dfs_limits, | |
893 | .n_limits = ARRAY_SIZE(if_dfs_limits), | |
894 | .max_interfaces = 1, | |
895 | .num_different_channels = 1, | |
896 | .beacon_int_infra_match = true, | |
87eb0167 JD |
897 | .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | |
898 | BIT(NL80211_CHAN_WIDTH_20), | |
e9cdedf6 | 899 | } |
20c8e8dc | 900 | }; |
43c35284 | 901 | |
7b6ef998 | 902 | static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 903 | { |
43c35284 FF |
904 | struct ath_hw *ah = sc->sc_ah; |
905 | struct ath_common *common = ath9k_hw_common(ah); | |
285f2dda | 906 | |
55624204 S |
907 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
908 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
909 | IEEE80211_HW_SIGNAL_DBM | | |
55624204 | 910 | IEEE80211_HW_PS_NULLFUNC_STACK | |
05df4986 | 911 | IEEE80211_HW_SPECTRUM_MGMT | |
79acac07 | 912 | IEEE80211_HW_REPORTS_TX_ACK_STATUS | |
2dfca312 FF |
913 | IEEE80211_HW_SUPPORTS_RC_TABLE | |
914 | IEEE80211_HW_SUPPORTS_HT_CCK_RATES; | |
55624204 | 915 | |
8298383c SM |
916 | if (ath9k_ps_enable) |
917 | hw->flags |= IEEE80211_HW_SUPPORTS_PS; | |
918 | ||
b0a1ae97 OR |
919 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
920 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
921 | ||
922 | if (AR_SREV_9280_20_OR_LATER(ah)) | |
923 | hw->radiotap_mcs_details |= | |
924 | IEEE80211_RADIOTAP_MCS_HAVE_STBC; | |
925 | } | |
5ffaf8a3 | 926 | |
3e6109c5 | 927 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) |
55624204 S |
928 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; |
929 | ||
ec26bcc0 FF |
930 | hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR; |
931 | ||
89f927af LR |
932 | if (!config_enabled(CONFIG_ATH9K_TX99)) { |
933 | hw->wiphy->interface_modes = | |
934 | BIT(NL80211_IFTYPE_P2P_GO) | | |
935 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
936 | BIT(NL80211_IFTYPE_AP) | | |
937 | BIT(NL80211_IFTYPE_WDS) | | |
938 | BIT(NL80211_IFTYPE_STATION) | | |
939 | BIT(NL80211_IFTYPE_ADHOC) | | |
940 | BIT(NL80211_IFTYPE_MESH_POINT); | |
941 | hw->wiphy->iface_combinations = if_comb; | |
942 | hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); | |
943 | } | |
20c8e8dc | 944 | |
531671cb | 945 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
55624204 | 946 | |
cfdc9a8b | 947 | hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; |
fd656234 | 948 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; |
81ddbb5c | 949 | hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; |
6fac8bbc | 950 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; |
d074e8d5 | 951 | hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; |
cfdc9a8b | 952 | |
55624204 S |
953 | hw->queues = 4; |
954 | hw->max_rates = 4; | |
195ca3b1 | 955 | hw->max_listen_interval = 1; |
65896510 | 956 | hw->max_rate_tries = 10; |
55624204 S |
957 | hw->sta_data_size = sizeof(struct ath_node); |
958 | hw->vif_data_size = sizeof(struct ath_vif); | |
959 | ||
43c35284 FF |
960 | hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; |
961 | hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; | |
962 | ||
963 | /* single chain devices with rx diversity */ | |
964 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
965 | hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); | |
966 | ||
967 | sc->ant_rx = hw->wiphy->available_antennas_rx; | |
968 | sc->ant_tx = hw->wiphy->available_antennas_tx; | |
969 | ||
d4659912 | 970 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
55624204 S |
971 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
972 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
d4659912 | 973 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
55624204 S |
974 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
975 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
285f2dda | 976 | |
babaa80a | 977 | ath9k_init_wow(hw); |
43c35284 | 978 | ath9k_reload_chainmask_settings(sc); |
285f2dda S |
979 | |
980 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
981 | } |
982 | ||
eb93e891 | 983 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
55624204 S |
984 | const struct ath_bus_ops *bus_ops) |
985 | { | |
986 | struct ieee80211_hw *hw = sc->hw; | |
987 | struct ath_common *common; | |
988 | struct ath_hw *ah; | |
285f2dda | 989 | int error = 0; |
55624204 S |
990 | struct ath_regulatory *reg; |
991 | ||
285f2dda | 992 | /* Bring up device */ |
eb93e891 | 993 | error = ath9k_init_softc(devid, sc, bus_ops); |
b81950b1 FF |
994 | if (error) |
995 | return error; | |
55624204 S |
996 | |
997 | ah = sc->sc_ah; | |
998 | common = ath9k_hw_common(ah); | |
285f2dda | 999 | ath9k_set_hw_capab(sc, hw); |
55624204 | 1000 | |
285f2dda | 1001 | /* Initialize regulatory */ |
55624204 S |
1002 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
1003 | ath9k_reg_notifier); | |
1004 | if (error) | |
b81950b1 | 1005 | goto deinit; |
55624204 S |
1006 | |
1007 | reg = &common->regulatory; | |
1008 | ||
285f2dda | 1009 | /* Setup TX DMA */ |
55624204 S |
1010 | error = ath_tx_init(sc, ATH_TXBUF); |
1011 | if (error != 0) | |
b81950b1 | 1012 | goto deinit; |
55624204 | 1013 | |
285f2dda | 1014 | /* Setup RX DMA */ |
55624204 S |
1015 | error = ath_rx_init(sc, ATH_RXBUF); |
1016 | if (error != 0) | |
b81950b1 | 1017 | goto deinit; |
55624204 | 1018 | |
babcbc29 FF |
1019 | ath9k_init_txpower_limits(sc); |
1020 | ||
0cf55c21 FF |
1021 | #ifdef CONFIG_MAC80211_LEDS |
1022 | /* must be initialized before ieee80211_register_hw */ | |
1023 | sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, | |
1024 | IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, | |
1025 | ARRAY_SIZE(ath9k_tpt_blink)); | |
1026 | #endif | |
1027 | ||
285f2dda | 1028 | /* Register with mac80211 */ |
55624204 | 1029 | error = ieee80211_register_hw(hw); |
285f2dda | 1030 | if (error) |
b81950b1 | 1031 | goto rx_cleanup; |
55624204 | 1032 | |
eb272441 BG |
1033 | error = ath9k_init_debug(ah); |
1034 | if (error) { | |
3800276a | 1035 | ath_err(common, "Unable to create debugfs files\n"); |
b81950b1 | 1036 | goto unregister; |
eb272441 BG |
1037 | } |
1038 | ||
285f2dda | 1039 | /* Handle world regulatory */ |
55624204 S |
1040 | if (!ath_is_world_regd(reg)) { |
1041 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
1042 | if (error) | |
af690092 | 1043 | goto debug_cleanup; |
55624204 S |
1044 | } |
1045 | ||
285f2dda | 1046 | ath_init_leds(sc); |
55624204 S |
1047 | ath_start_rfkill_poll(sc); |
1048 | ||
1049 | return 0; | |
1050 | ||
af690092 SM |
1051 | debug_cleanup: |
1052 | ath9k_deinit_debug(sc); | |
b81950b1 | 1053 | unregister: |
285f2dda | 1054 | ieee80211_unregister_hw(hw); |
b81950b1 | 1055 | rx_cleanup: |
285f2dda | 1056 | ath_rx_cleanup(sc); |
b81950b1 | 1057 | deinit: |
285f2dda | 1058 | ath9k_deinit_softc(sc); |
55624204 S |
1059 | return error; |
1060 | } | |
1061 | ||
1062 | /*****************************/ | |
1063 | /* De-Initialization */ | |
1064 | /*****************************/ | |
1065 | ||
285f2dda | 1066 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 1067 | { |
285f2dda | 1068 | int i = 0; |
55624204 | 1069 | |
5908120f | 1070 | ath9k_deinit_btcoex(sc); |
19686ddf | 1071 | |
285f2dda S |
1072 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
1073 | if (ATH_TXQ_SETUP(sc, i)) | |
1074 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
1075 | ||
bf3dac5a | 1076 | del_timer_sync(&sc->sleep_timer); |
285f2dda | 1077 | ath9k_hw_deinit(sc->sc_ah); |
8e92d3f2 ZK |
1078 | if (sc->dfs_detector != NULL) |
1079 | sc->dfs_detector->exit(sc->dfs_detector); | |
285f2dda | 1080 | |
ab5c4f71 | 1081 | ath9k_eeprom_release(sc); |
55624204 S |
1082 | } |
1083 | ||
285f2dda | 1084 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
1085 | { |
1086 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
1087 | |
1088 | ath9k_ps_wakeup(sc); | |
1089 | ||
55624204 | 1090 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 1091 | ath_deinit_leds(sc); |
55624204 | 1092 | |
c7c18060 RM |
1093 | ath9k_ps_restore(sc); |
1094 | ||
af690092 | 1095 | ath9k_deinit_debug(sc); |
55624204 S |
1096 | ieee80211_unregister_hw(hw); |
1097 | ath_rx_cleanup(sc); | |
285f2dda | 1098 | ath9k_deinit_softc(sc); |
55624204 S |
1099 | } |
1100 | ||
55624204 S |
1101 | /************************/ |
1102 | /* Module Hooks */ | |
1103 | /************************/ | |
1104 | ||
1105 | static int __init ath9k_init(void) | |
1106 | { | |
1107 | int error; | |
1108 | ||
1109 | /* Register rate control algorithm */ | |
1110 | error = ath_rate_control_register(); | |
1111 | if (error != 0) { | |
516304b0 JP |
1112 | pr_err("Unable to register rate control algorithm: %d\n", |
1113 | error); | |
55624204 S |
1114 | goto err_out; |
1115 | } | |
1116 | ||
55624204 S |
1117 | error = ath_pci_init(); |
1118 | if (error < 0) { | |
516304b0 | 1119 | pr_err("No PCI devices found, driver not installed\n"); |
55624204 | 1120 | error = -ENODEV; |
eb272441 | 1121 | goto err_rate_unregister; |
55624204 S |
1122 | } |
1123 | ||
1124 | error = ath_ahb_init(); | |
1125 | if (error < 0) { | |
1126 | error = -ENODEV; | |
1127 | goto err_pci_exit; | |
1128 | } | |
1129 | ||
1130 | return 0; | |
1131 | ||
1132 | err_pci_exit: | |
1133 | ath_pci_exit(); | |
1134 | ||
55624204 S |
1135 | err_rate_unregister: |
1136 | ath_rate_control_unregister(); | |
1137 | err_out: | |
1138 | return error; | |
1139 | } | |
1140 | module_init(ath9k_init); | |
1141 | ||
1142 | static void __exit ath9k_exit(void) | |
1143 | { | |
d584747b | 1144 | is_ath9k_unloaded = true; |
55624204 S |
1145 | ath_ahb_exit(); |
1146 | ath_pci_exit(); | |
55624204 | 1147 | ath_rate_control_unregister(); |
516304b0 | 1148 | pr_info("%s: Driver unloaded\n", dev_info); |
55624204 S |
1149 | } |
1150 | module_exit(ath9k_exit); |