Commit | Line | Data |
---|---|---|
55624204 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
55624204 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
5a0e3ad6 | 17 | #include <linux/slab.h> |
6fb1b1e1 | 18 | #include <linux/ath9k_platform.h> |
5a0e3ad6 | 19 | |
55624204 S |
20 | #include "ath9k.h" |
21 | ||
22 | static char *dev_info = "ath9k"; | |
23 | ||
24 | MODULE_AUTHOR("Atheros Communications"); | |
25 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
26 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
27 | MODULE_LICENSE("Dual BSD/GPL"); | |
28 | ||
29 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
30 | module_param_named(debug, ath9k_debug, uint, 0); | |
31 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
32 | ||
3e6109c5 JL |
33 | int ath9k_modparam_nohwcrypt; |
34 | module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); | |
55624204 S |
35 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); |
36 | ||
93dbbcc4 | 37 | int led_blink; |
9a75c2ff VN |
38 | module_param_named(blink, led_blink, int, 0444); |
39 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); | |
40 | ||
8f5dcb1c VT |
41 | static int ath9k_btcoex_enable; |
42 | module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); | |
43 | MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); | |
44 | ||
d584747b | 45 | bool is_ath9k_unloaded; |
55624204 S |
46 | /* We use the hw_value as an index into our private channel structure */ |
47 | ||
48 | #define CHAN2G(_freq, _idx) { \ | |
b1c1d000 | 49 | .band = IEEE80211_BAND_2GHZ, \ |
55624204 S |
50 | .center_freq = (_freq), \ |
51 | .hw_value = (_idx), \ | |
52 | .max_power = 20, \ | |
53 | } | |
54 | ||
55 | #define CHAN5G(_freq, _idx) { \ | |
56 | .band = IEEE80211_BAND_5GHZ, \ | |
57 | .center_freq = (_freq), \ | |
58 | .hw_value = (_idx), \ | |
59 | .max_power = 20, \ | |
60 | } | |
61 | ||
62 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
63 | * on 5 MHz steps, we support the channels which we know | |
64 | * we have calibration data for all cards though to make | |
65 | * this static */ | |
f209f529 | 66 | static const struct ieee80211_channel ath9k_2ghz_chantable[] = { |
55624204 S |
67 | CHAN2G(2412, 0), /* Channel 1 */ |
68 | CHAN2G(2417, 1), /* Channel 2 */ | |
69 | CHAN2G(2422, 2), /* Channel 3 */ | |
70 | CHAN2G(2427, 3), /* Channel 4 */ | |
71 | CHAN2G(2432, 4), /* Channel 5 */ | |
72 | CHAN2G(2437, 5), /* Channel 6 */ | |
73 | CHAN2G(2442, 6), /* Channel 7 */ | |
74 | CHAN2G(2447, 7), /* Channel 8 */ | |
75 | CHAN2G(2452, 8), /* Channel 9 */ | |
76 | CHAN2G(2457, 9), /* Channel 10 */ | |
77 | CHAN2G(2462, 10), /* Channel 11 */ | |
78 | CHAN2G(2467, 11), /* Channel 12 */ | |
79 | CHAN2G(2472, 12), /* Channel 13 */ | |
80 | CHAN2G(2484, 13), /* Channel 14 */ | |
81 | }; | |
82 | ||
83 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
84 | * on 5 MHz steps, we support the channels which we know | |
85 | * we have calibration data for all cards though to make | |
86 | * this static */ | |
f209f529 | 87 | static const struct ieee80211_channel ath9k_5ghz_chantable[] = { |
55624204 S |
88 | /* _We_ call this UNII 1 */ |
89 | CHAN5G(5180, 14), /* Channel 36 */ | |
90 | CHAN5G(5200, 15), /* Channel 40 */ | |
91 | CHAN5G(5220, 16), /* Channel 44 */ | |
92 | CHAN5G(5240, 17), /* Channel 48 */ | |
93 | /* _We_ call this UNII 2 */ | |
94 | CHAN5G(5260, 18), /* Channel 52 */ | |
95 | CHAN5G(5280, 19), /* Channel 56 */ | |
96 | CHAN5G(5300, 20), /* Channel 60 */ | |
97 | CHAN5G(5320, 21), /* Channel 64 */ | |
98 | /* _We_ call this "Middle band" */ | |
99 | CHAN5G(5500, 22), /* Channel 100 */ | |
100 | CHAN5G(5520, 23), /* Channel 104 */ | |
101 | CHAN5G(5540, 24), /* Channel 108 */ | |
102 | CHAN5G(5560, 25), /* Channel 112 */ | |
103 | CHAN5G(5580, 26), /* Channel 116 */ | |
104 | CHAN5G(5600, 27), /* Channel 120 */ | |
105 | CHAN5G(5620, 28), /* Channel 124 */ | |
106 | CHAN5G(5640, 29), /* Channel 128 */ | |
107 | CHAN5G(5660, 30), /* Channel 132 */ | |
108 | CHAN5G(5680, 31), /* Channel 136 */ | |
109 | CHAN5G(5700, 32), /* Channel 140 */ | |
110 | /* _We_ call this UNII 3 */ | |
111 | CHAN5G(5745, 33), /* Channel 149 */ | |
112 | CHAN5G(5765, 34), /* Channel 153 */ | |
113 | CHAN5G(5785, 35), /* Channel 157 */ | |
114 | CHAN5G(5805, 36), /* Channel 161 */ | |
115 | CHAN5G(5825, 37), /* Channel 165 */ | |
116 | }; | |
117 | ||
118 | /* Atheros hardware rate code addition for short premble */ | |
119 | #define SHPCHECK(__hw_rate, __flags) \ | |
120 | ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) | |
121 | ||
122 | #define RATE(_bitrate, _hw_rate, _flags) { \ | |
123 | .bitrate = (_bitrate), \ | |
124 | .flags = (_flags), \ | |
125 | .hw_value = (_hw_rate), \ | |
126 | .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ | |
127 | } | |
128 | ||
129 | static struct ieee80211_rate ath9k_legacy_rates[] = { | |
130 | RATE(10, 0x1b, 0), | |
131 | RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), | |
132 | RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), | |
133 | RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), | |
134 | RATE(60, 0x0b, 0), | |
135 | RATE(90, 0x0f, 0), | |
136 | RATE(120, 0x0a, 0), | |
137 | RATE(180, 0x0e, 0), | |
138 | RATE(240, 0x09, 0), | |
139 | RATE(360, 0x0d, 0), | |
140 | RATE(480, 0x08, 0), | |
141 | RATE(540, 0x0c, 0), | |
142 | }; | |
143 | ||
0cf55c21 FF |
144 | #ifdef CONFIG_MAC80211_LEDS |
145 | static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { | |
146 | { .throughput = 0 * 1024, .blink_time = 334 }, | |
147 | { .throughput = 1 * 1024, .blink_time = 260 }, | |
148 | { .throughput = 5 * 1024, .blink_time = 220 }, | |
149 | { .throughput = 10 * 1024, .blink_time = 190 }, | |
150 | { .throughput = 20 * 1024, .blink_time = 170 }, | |
151 | { .throughput = 50 * 1024, .blink_time = 150 }, | |
152 | { .throughput = 70 * 1024, .blink_time = 130 }, | |
153 | { .throughput = 100 * 1024, .blink_time = 110 }, | |
154 | { .throughput = 200 * 1024, .blink_time = 80 }, | |
155 | { .throughput = 300 * 1024, .blink_time = 50 }, | |
156 | }; | |
157 | #endif | |
158 | ||
285f2dda | 159 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 S |
160 | |
161 | /* | |
162 | * Read and write, they both share the same lock. We do this to serialize | |
163 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
164 | * as the FIFO on these devices can only accept sanely 2 requests. | |
165 | */ | |
166 | ||
167 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
168 | { | |
169 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
170 | struct ath_common *common = ath9k_hw_common(ah); | |
171 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
172 | ||
173 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
174 | unsigned long flags; | |
175 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
176 | iowrite32(val, sc->mem + reg_offset); | |
177 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
178 | } else | |
179 | iowrite32(val, sc->mem + reg_offset); | |
180 | } | |
181 | ||
182 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
183 | { | |
184 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
185 | struct ath_common *common = ath9k_hw_common(ah); | |
186 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
187 | u32 val; | |
188 | ||
189 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
190 | unsigned long flags; | |
191 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
192 | val = ioread32(sc->mem + reg_offset); | |
193 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
194 | } else | |
195 | val = ioread32(sc->mem + reg_offset); | |
196 | return val; | |
197 | } | |
198 | ||
5479de6e RM |
199 | static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, |
200 | u32 set, u32 clr) | |
201 | { | |
202 | u32 val; | |
203 | ||
204 | val = ioread32(sc->mem + reg_offset); | |
205 | val &= ~clr; | |
206 | val |= set; | |
207 | iowrite32(val, sc->mem + reg_offset); | |
208 | ||
209 | return val; | |
210 | } | |
211 | ||
845e03c9 FF |
212 | static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) |
213 | { | |
214 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
215 | struct ath_common *common = ath9k_hw_common(ah); | |
216 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
217 | unsigned long uninitialized_var(flags); | |
218 | u32 val; | |
219 | ||
5479de6e | 220 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { |
845e03c9 | 221 | spin_lock_irqsave(&sc->sc_serial_rw, flags); |
5479de6e | 222 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); |
845e03c9 | 223 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); |
5479de6e RM |
224 | } else |
225 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); | |
845e03c9 FF |
226 | |
227 | return val; | |
228 | } | |
229 | ||
55624204 S |
230 | /**************************/ |
231 | /* Initialization */ | |
232 | /**************************/ | |
233 | ||
234 | static void setup_ht_cap(struct ath_softc *sc, | |
235 | struct ieee80211_sta_ht_cap *ht_info) | |
236 | { | |
3bb065a7 FF |
237 | struct ath_hw *ah = sc->sc_ah; |
238 | struct ath_common *common = ath9k_hw_common(ah); | |
55624204 | 239 | u8 tx_streams, rx_streams; |
3bb065a7 | 240 | int i, max_streams; |
55624204 S |
241 | |
242 | ht_info->ht_supported = true; | |
243 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
244 | IEEE80211_HT_CAP_SM_PS | | |
245 | IEEE80211_HT_CAP_SGI_40 | | |
246 | IEEE80211_HT_CAP_DSSSCCK40; | |
247 | ||
b0a33448 LR |
248 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) |
249 | ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; | |
250 | ||
6473d24d VT |
251 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) |
252 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
253 | ||
55624204 S |
254 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
255 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
256 | ||
7216198d | 257 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) |
7f1c7a6a VT |
258 | max_streams = 1; |
259 | else if (AR_SREV_9300_20_OR_LATER(ah)) | |
3bb065a7 FF |
260 | max_streams = 3; |
261 | else | |
262 | max_streams = 2; | |
263 | ||
7a37081e | 264 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
074a8c0d FF |
265 | if (max_streams >= 2) |
266 | ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; | |
267 | ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); | |
268 | } | |
269 | ||
55624204 S |
270 | /* set up supported mcs set */ |
271 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
61389f3e S |
272 | tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams); |
273 | rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams); | |
3bb065a7 | 274 | |
226afe68 JP |
275 | ath_dbg(common, ATH_DBG_CONFIG, |
276 | "TX streams %d, RX streams: %d\n", | |
277 | tx_streams, rx_streams); | |
55624204 S |
278 | |
279 | if (tx_streams != rx_streams) { | |
55624204 S |
280 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
281 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
282 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
283 | } | |
284 | ||
3bb065a7 FF |
285 | for (i = 0; i < rx_streams; i++) |
286 | ht_info->mcs.rx_mask[i] = 0xff; | |
55624204 S |
287 | |
288 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; | |
289 | } | |
290 | ||
291 | static int ath9k_reg_notifier(struct wiphy *wiphy, | |
292 | struct regulatory_request *request) | |
293 | { | |
294 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
9ac58615 | 295 | struct ath_softc *sc = hw->priv; |
55624204 S |
296 | struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah); |
297 | ||
298 | return ath_reg_notifier_apply(wiphy, request, reg); | |
299 | } | |
300 | ||
301 | /* | |
302 | * This function will allocate both the DMA descriptor structure, and the | |
303 | * buffers it contains. These are used to contain the descriptors used | |
304 | * by the system. | |
305 | */ | |
306 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
307 | struct list_head *head, const char *name, | |
4adfcded | 308 | int nbuf, int ndesc, bool is_tx) |
55624204 | 309 | { |
55624204 | 310 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4adfcded | 311 | u8 *ds; |
55624204 | 312 | struct ath_buf *bf; |
4adfcded | 313 | int i, bsize, error, desc_len; |
55624204 | 314 | |
226afe68 JP |
315 | ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
316 | name, nbuf, ndesc); | |
55624204 S |
317 | |
318 | INIT_LIST_HEAD(head); | |
4adfcded VT |
319 | |
320 | if (is_tx) | |
321 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
322 | else | |
323 | desc_len = sizeof(struct ath_desc); | |
324 | ||
55624204 | 325 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 326 | if ((desc_len % 4) != 0) { |
3800276a | 327 | ath_err(common, "ath_desc not DWORD aligned\n"); |
4adfcded | 328 | BUG_ON((desc_len % 4) != 0); |
55624204 S |
329 | error = -ENOMEM; |
330 | goto fail; | |
331 | } | |
332 | ||
4adfcded | 333 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
334 | |
335 | /* | |
336 | * Need additional DMA memory because we can't use | |
337 | * descriptors that cross the 4K page boundary. Assume | |
338 | * one skipped descriptor per 4K page. | |
339 | */ | |
340 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
341 | u32 ndesc_skipped = | |
342 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
343 | u32 dma_len; | |
344 | ||
345 | while (ndesc_skipped) { | |
4adfcded | 346 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
347 | dd->dd_desc_len += dma_len; |
348 | ||
349 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 350 | } |
55624204 S |
351 | } |
352 | ||
353 | /* allocate descriptors */ | |
354 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, | |
355 | &dd->dd_desc_paddr, GFP_KERNEL); | |
356 | if (dd->dd_desc == NULL) { | |
357 | error = -ENOMEM; | |
358 | goto fail; | |
359 | } | |
4adfcded | 360 | ds = (u8 *) dd->dd_desc; |
226afe68 JP |
361 | ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
362 | name, ds, (u32) dd->dd_desc_len, | |
363 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
55624204 S |
364 | |
365 | /* allocate buffers */ | |
366 | bsize = sizeof(struct ath_buf) * nbuf; | |
367 | bf = kzalloc(bsize, GFP_KERNEL); | |
368 | if (bf == NULL) { | |
369 | error = -ENOMEM; | |
370 | goto fail2; | |
371 | } | |
372 | dd->dd_bufptr = bf; | |
373 | ||
4adfcded | 374 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { |
55624204 S |
375 | bf->bf_desc = ds; |
376 | bf->bf_daddr = DS2PHYS(dd, ds); | |
377 | ||
378 | if (!(sc->sc_ah->caps.hw_caps & | |
379 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
380 | /* | |
381 | * Skip descriptor addresses which can cause 4KB | |
382 | * boundary crossing (addr + length) with a 32 dword | |
383 | * descriptor fetch. | |
384 | */ | |
385 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
386 | BUG_ON((caddr_t) bf->bf_desc >= | |
387 | ((caddr_t) dd->dd_desc + | |
388 | dd->dd_desc_len)); | |
389 | ||
4adfcded | 390 | ds += (desc_len * ndesc); |
55624204 S |
391 | bf->bf_desc = ds; |
392 | bf->bf_daddr = DS2PHYS(dd, ds); | |
393 | } | |
394 | } | |
395 | list_add_tail(&bf->list, head); | |
396 | } | |
397 | return 0; | |
398 | fail2: | |
399 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
400 | dd->dd_desc_paddr); | |
401 | fail: | |
402 | memset(dd, 0, sizeof(*dd)); | |
403 | return error; | |
55624204 S |
404 | } |
405 | ||
db7ec38d | 406 | void ath9k_init_crypto(struct ath_softc *sc) |
55624204 | 407 | { |
285f2dda S |
408 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
409 | int i = 0; | |
55624204 S |
410 | |
411 | /* Get the hardware key cache size. */ | |
6de12a1b | 412 | common->keymax = AR_KEYTABLE_SIZE; |
55624204 S |
413 | |
414 | /* | |
415 | * Reset the key cache since some parts do not | |
416 | * reset the contents on initial power up. | |
417 | */ | |
418 | for (i = 0; i < common->keymax; i++) | |
040e539e | 419 | ath_hw_keyreset(common, (u16) i); |
55624204 | 420 | |
55624204 | 421 | /* |
285f2dda S |
422 | * Check whether the separate key cache entries |
423 | * are required to handle both tx+rx MIC keys. | |
424 | * With split mic keys the number of stations is limited | |
425 | * to 27 otherwise 59. | |
55624204 | 426 | */ |
117675d0 BR |
427 | if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) |
428 | common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED; | |
285f2dda S |
429 | } |
430 | ||
431 | static int ath9k_init_btcoex(struct ath_softc *sc) | |
432 | { | |
066dae93 FF |
433 | struct ath_txq *txq; |
434 | int r; | |
285f2dda S |
435 | |
436 | switch (sc->sc_ah->btcoex_hw.scheme) { | |
437 | case ATH_BTCOEX_CFG_NONE: | |
438 | break; | |
439 | case ATH_BTCOEX_CFG_2WIRE: | |
440 | ath9k_hw_btcoex_init_2wire(sc->sc_ah); | |
441 | break; | |
442 | case ATH_BTCOEX_CFG_3WIRE: | |
443 | ath9k_hw_btcoex_init_3wire(sc->sc_ah); | |
444 | r = ath_init_btcoex_timer(sc); | |
445 | if (r) | |
446 | return -1; | |
066dae93 FF |
447 | txq = sc->tx.txq_map[WME_AC_BE]; |
448 | ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum); | |
285f2dda S |
449 | sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; |
450 | break; | |
451 | default: | |
452 | WARN_ON(1); | |
453 | break; | |
454 | } | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
459 | static int ath9k_init_queues(struct ath_softc *sc) | |
460 | { | |
285f2dda S |
461 | int i = 0; |
462 | ||
285f2dda | 463 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 464 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
465 | |
466 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; | |
467 | ath_cabq_update(sc); | |
468 | ||
60f2d1d5 | 469 | for (i = 0; i < WME_NUM_AC; i++) { |
066dae93 | 470 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); |
60f2d1d5 BG |
471 | sc->tx.txq_map[i]->mac80211_qnum = i; |
472 | } | |
285f2dda | 473 | return 0; |
285f2dda S |
474 | } |
475 | ||
f209f529 | 476 | static int ath9k_init_channels_rates(struct ath_softc *sc) |
285f2dda | 477 | { |
f209f529 FF |
478 | void *channels; |
479 | ||
cac4220b FF |
480 | BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + |
481 | ARRAY_SIZE(ath9k_5ghz_chantable) != | |
482 | ATH9K_NUM_CHANNELS); | |
483 | ||
d4659912 | 484 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { |
f209f529 FF |
485 | channels = kmemdup(ath9k_2ghz_chantable, |
486 | sizeof(ath9k_2ghz_chantable), GFP_KERNEL); | |
487 | if (!channels) | |
488 | return -ENOMEM; | |
489 | ||
490 | sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; | |
285f2dda S |
491 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; |
492 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = | |
493 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
494 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; | |
495 | sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = | |
496 | ARRAY_SIZE(ath9k_legacy_rates); | |
55624204 S |
497 | } |
498 | ||
d4659912 | 499 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { |
f209f529 FF |
500 | channels = kmemdup(ath9k_5ghz_chantable, |
501 | sizeof(ath9k_5ghz_chantable), GFP_KERNEL); | |
502 | if (!channels) { | |
503 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) | |
504 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
505 | return -ENOMEM; | |
506 | } | |
507 | ||
508 | sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; | |
285f2dda S |
509 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; |
510 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = | |
511 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
512 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
513 | ath9k_legacy_rates + 4; | |
514 | sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = | |
515 | ARRAY_SIZE(ath9k_legacy_rates) - 4; | |
516 | } | |
f209f529 | 517 | return 0; |
285f2dda | 518 | } |
55624204 | 519 | |
285f2dda S |
520 | static void ath9k_init_misc(struct ath_softc *sc) |
521 | { | |
522 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
523 | int i = 0; | |
285f2dda | 524 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); |
55624204 S |
525 | |
526 | sc->config.txpowlimit = ATH_TXPOWER_MAX; | |
527 | ||
285f2dda | 528 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
55624204 S |
529 | sc->sc_flags |= SC_OP_TXAGGR; |
530 | sc->sc_flags |= SC_OP_RXAGGR; | |
531 | } | |
532 | ||
285f2dda S |
533 | common->tx_chainmask = sc->sc_ah->caps.tx_chainmask; |
534 | common->rx_chainmask = sc->sc_ah->caps.rx_chainmask; | |
55624204 | 535 | |
8fe65368 | 536 | ath9k_hw_set_diversity(sc->sc_ah, true); |
285f2dda | 537 | sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah); |
55624204 | 538 | |
364734fa | 539 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
55624204 | 540 | |
285f2dda | 541 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 542 | |
7545daf4 | 543 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) |
55624204 | 544 | sc->beacon.bslot[i] = NULL; |
102885a5 VT |
545 | |
546 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
547 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
285f2dda | 548 | } |
55624204 | 549 | |
285f2dda S |
550 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid, |
551 | const struct ath_bus_ops *bus_ops) | |
552 | { | |
6fb1b1e1 | 553 | struct ath9k_platform_data *pdata = sc->dev->platform_data; |
285f2dda S |
554 | struct ath_hw *ah = NULL; |
555 | struct ath_common *common; | |
556 | int ret = 0, i; | |
557 | int csz = 0; | |
55624204 | 558 | |
285f2dda S |
559 | ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); |
560 | if (!ah) | |
561 | return -ENOMEM; | |
562 | ||
233536e1 | 563 | ah->hw = sc->hw; |
285f2dda S |
564 | ah->hw_version.devid = devid; |
565 | ah->hw_version.subsysid = subsysid; | |
f9f84e96 FF |
566 | ah->reg_ops.read = ath9k_ioread32; |
567 | ah->reg_ops.write = ath9k_iowrite32; | |
845e03c9 | 568 | ah->reg_ops.rmw = ath9k_reg_rmw; |
285f2dda S |
569 | sc->sc_ah = ah; |
570 | ||
6de66dd9 | 571 | if (!pdata) { |
a05b5d45 | 572 | ah->ah_flags |= AH_USE_EEPROM; |
6de66dd9 FF |
573 | sc->sc_ah->led_pin = -1; |
574 | } else { | |
575 | sc->sc_ah->gpio_mask = pdata->gpio_mask; | |
576 | sc->sc_ah->gpio_val = pdata->gpio_val; | |
577 | sc->sc_ah->led_pin = pdata->led_pin; | |
f2f5f2a1 | 578 | ah->is_clk_25mhz = pdata->is_clk_25mhz; |
3762561a | 579 | ah->get_mac_revision = pdata->get_mac_revision; |
7d95847c | 580 | ah->external_reset = pdata->external_reset; |
6de66dd9 | 581 | } |
a05b5d45 | 582 | |
285f2dda | 583 | common = ath9k_hw_common(ah); |
f9f84e96 | 584 | common->ops = &ah->reg_ops; |
285f2dda S |
585 | common->bus_ops = bus_ops; |
586 | common->ah = ah; | |
587 | common->hw = sc->hw; | |
588 | common->priv = sc; | |
589 | common->debug_mask = ath9k_debug; | |
8f5dcb1c | 590 | common->btcoex_enabled = ath9k_btcoex_enable == 1; |
05c0be2f | 591 | common->disable_ani = false; |
20b25744 | 592 | spin_lock_init(&common->cc_lock); |
285f2dda | 593 | |
285f2dda S |
594 | spin_lock_init(&sc->sc_serial_rw); |
595 | spin_lock_init(&sc->sc_pm_lock); | |
596 | mutex_init(&sc->mutex); | |
7f010c93 BG |
597 | #ifdef CONFIG_ATH9K_DEBUGFS |
598 | spin_lock_init(&sc->nodes_lock); | |
599 | INIT_LIST_HEAD(&sc->nodes); | |
600 | #endif | |
285f2dda S |
601 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); |
602 | tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, | |
603 | (unsigned long)sc); | |
604 | ||
605 | /* | |
606 | * Cache line size is used to size and align various | |
607 | * structures used to communicate with the hardware. | |
608 | */ | |
609 | ath_read_cachesize(common, &csz); | |
610 | common->cachelsz = csz << 2; /* convert to bytes */ | |
611 | ||
d70357d5 | 612 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 613 | ret = ath9k_hw_init(ah); |
d70357d5 | 614 | if (ret) |
285f2dda | 615 | goto err_hw; |
55624204 | 616 | |
6fb1b1e1 FF |
617 | if (pdata && pdata->macaddr) |
618 | memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); | |
619 | ||
285f2dda S |
620 | ret = ath9k_init_queues(sc); |
621 | if (ret) | |
622 | goto err_queues; | |
623 | ||
624 | ret = ath9k_init_btcoex(sc); | |
625 | if (ret) | |
626 | goto err_btcoex; | |
627 | ||
f209f529 FF |
628 | ret = ath9k_init_channels_rates(sc); |
629 | if (ret) | |
630 | goto err_btcoex; | |
631 | ||
285f2dda | 632 | ath9k_init_crypto(sc); |
285f2dda S |
633 | ath9k_init_misc(sc); |
634 | ||
55624204 | 635 | return 0; |
285f2dda S |
636 | |
637 | err_btcoex: | |
55624204 S |
638 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
639 | if (ATH_TXQ_SETUP(sc, i)) | |
640 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda | 641 | err_queues: |
285f2dda S |
642 | ath9k_hw_deinit(ah); |
643 | err_hw: | |
55624204 | 644 | |
285f2dda S |
645 | kfree(ah); |
646 | sc->sc_ah = NULL; | |
647 | ||
648 | return ret; | |
55624204 S |
649 | } |
650 | ||
babcbc29 FF |
651 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
652 | { | |
653 | struct ieee80211_supported_band *sband; | |
654 | struct ieee80211_channel *chan; | |
655 | struct ath_hw *ah = sc->sc_ah; | |
656 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
657 | int i; | |
658 | ||
659 | sband = &sc->sbands[band]; | |
660 | for (i = 0; i < sband->n_channels; i++) { | |
661 | chan = &sband->channels[i]; | |
662 | ah->curchan = &ah->channels[chan->hw_value]; | |
663 | ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20); | |
664 | ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); | |
665 | chan->max_power = reg->max_power_level / 2; | |
666 | } | |
667 | } | |
668 | ||
669 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
670 | { | |
671 | struct ath_hw *ah = sc->sc_ah; | |
672 | struct ath9k_channel *curchan = ah->curchan; | |
673 | ||
674 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
675 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); | |
676 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
677 | ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); | |
678 | ||
679 | ah->curchan = curchan; | |
680 | } | |
681 | ||
285f2dda | 682 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 683 | { |
285f2dda S |
684 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
685 | ||
55624204 S |
686 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
687 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
688 | IEEE80211_HW_SIGNAL_DBM | | |
55624204 S |
689 | IEEE80211_HW_SUPPORTS_PS | |
690 | IEEE80211_HW_PS_NULLFUNC_STACK | | |
05df4986 | 691 | IEEE80211_HW_SPECTRUM_MGMT | |
bd8027a7 | 692 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; |
55624204 | 693 | |
5ffaf8a3 LR |
694 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
695 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
696 | ||
3e6109c5 | 697 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) |
55624204 S |
698 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; |
699 | ||
700 | hw->wiphy->interface_modes = | |
c426ee24 JB |
701 | BIT(NL80211_IFTYPE_P2P_GO) | |
702 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
55624204 | 703 | BIT(NL80211_IFTYPE_AP) | |
e51f3eff | 704 | BIT(NL80211_IFTYPE_WDS) | |
55624204 S |
705 | BIT(NL80211_IFTYPE_STATION) | |
706 | BIT(NL80211_IFTYPE_ADHOC) | | |
707 | BIT(NL80211_IFTYPE_MESH_POINT); | |
708 | ||
008443de LR |
709 | if (AR_SREV_5416(sc->sc_ah)) |
710 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
55624204 | 711 | |
cfdc9a8b JM |
712 | hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; |
713 | ||
55624204 S |
714 | hw->queues = 4; |
715 | hw->max_rates = 4; | |
716 | hw->channel_change_time = 5000; | |
717 | hw->max_listen_interval = 10; | |
65896510 | 718 | hw->max_rate_tries = 10; |
55624204 S |
719 | hw->sta_data_size = sizeof(struct ath_node); |
720 | hw->vif_data_size = sizeof(struct ath_vif); | |
721 | ||
6e5c2b4e | 722 | #ifdef CONFIG_ATH9K_RATE_CONTROL |
55624204 | 723 | hw->rate_control_algorithm = "ath9k_rate_control"; |
6e5c2b4e | 724 | #endif |
55624204 | 725 | |
d4659912 | 726 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
55624204 S |
727 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
728 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
d4659912 | 729 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
55624204 S |
730 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
731 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
285f2dda S |
732 | |
733 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { | |
d4659912 | 734 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
285f2dda | 735 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); |
d4659912 | 736 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
285f2dda S |
737 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); |
738 | } | |
739 | ||
740 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
741 | } |
742 | ||
285f2dda | 743 | int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, |
55624204 S |
744 | const struct ath_bus_ops *bus_ops) |
745 | { | |
746 | struct ieee80211_hw *hw = sc->hw; | |
747 | struct ath_common *common; | |
748 | struct ath_hw *ah; | |
285f2dda | 749 | int error = 0; |
55624204 S |
750 | struct ath_regulatory *reg; |
751 | ||
285f2dda S |
752 | /* Bring up device */ |
753 | error = ath9k_init_softc(devid, sc, subsysid, bus_ops); | |
55624204 | 754 | if (error != 0) |
285f2dda | 755 | goto error_init; |
55624204 S |
756 | |
757 | ah = sc->sc_ah; | |
758 | common = ath9k_hw_common(ah); | |
285f2dda | 759 | ath9k_set_hw_capab(sc, hw); |
55624204 | 760 | |
285f2dda | 761 | /* Initialize regulatory */ |
55624204 S |
762 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
763 | ath9k_reg_notifier); | |
764 | if (error) | |
285f2dda | 765 | goto error_regd; |
55624204 S |
766 | |
767 | reg = &common->regulatory; | |
768 | ||
285f2dda | 769 | /* Setup TX DMA */ |
55624204 S |
770 | error = ath_tx_init(sc, ATH_TXBUF); |
771 | if (error != 0) | |
285f2dda | 772 | goto error_tx; |
55624204 | 773 | |
285f2dda | 774 | /* Setup RX DMA */ |
55624204 S |
775 | error = ath_rx_init(sc, ATH_RXBUF); |
776 | if (error != 0) | |
285f2dda | 777 | goto error_rx; |
55624204 | 778 | |
babcbc29 FF |
779 | ath9k_init_txpower_limits(sc); |
780 | ||
0cf55c21 FF |
781 | #ifdef CONFIG_MAC80211_LEDS |
782 | /* must be initialized before ieee80211_register_hw */ | |
783 | sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, | |
784 | IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, | |
785 | ARRAY_SIZE(ath9k_tpt_blink)); | |
786 | #endif | |
787 | ||
285f2dda | 788 | /* Register with mac80211 */ |
55624204 | 789 | error = ieee80211_register_hw(hw); |
285f2dda S |
790 | if (error) |
791 | goto error_register; | |
55624204 | 792 | |
eb272441 BG |
793 | error = ath9k_init_debug(ah); |
794 | if (error) { | |
3800276a | 795 | ath_err(common, "Unable to create debugfs files\n"); |
eb272441 BG |
796 | goto error_world; |
797 | } | |
798 | ||
285f2dda | 799 | /* Handle world regulatory */ |
55624204 S |
800 | if (!ath_is_world_regd(reg)) { |
801 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
802 | if (error) | |
285f2dda | 803 | goto error_world; |
55624204 S |
804 | } |
805 | ||
347809fc | 806 | INIT_WORK(&sc->hw_check_work, ath_hw_check); |
9f42c2b6 | 807 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); |
9eab61c2 | 808 | INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); |
9ac58615 | 809 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
55624204 | 810 | |
285f2dda | 811 | ath_init_leds(sc); |
55624204 S |
812 | ath_start_rfkill_poll(sc); |
813 | ||
814 | return 0; | |
815 | ||
285f2dda S |
816 | error_world: |
817 | ieee80211_unregister_hw(hw); | |
818 | error_register: | |
819 | ath_rx_cleanup(sc); | |
820 | error_rx: | |
821 | ath_tx_cleanup(sc); | |
822 | error_tx: | |
823 | /* Nothing */ | |
824 | error_regd: | |
825 | ath9k_deinit_softc(sc); | |
826 | error_init: | |
55624204 S |
827 | return error; |
828 | } | |
829 | ||
830 | /*****************************/ | |
831 | /* De-Initialization */ | |
832 | /*****************************/ | |
833 | ||
285f2dda | 834 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 835 | { |
285f2dda | 836 | int i = 0; |
55624204 | 837 | |
f209f529 FF |
838 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) |
839 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
840 | ||
841 | if (sc->sbands[IEEE80211_BAND_5GHZ].channels) | |
842 | kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels); | |
843 | ||
285f2dda S |
844 | if ((sc->btcoex.no_stomp_timer) && |
845 | sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) | |
846 | ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer); | |
55624204 | 847 | |
285f2dda S |
848 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
849 | if (ATH_TXQ_SETUP(sc, i)) | |
850 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
851 | ||
285f2dda S |
852 | ath9k_hw_deinit(sc->sc_ah); |
853 | ||
736b3a27 S |
854 | kfree(sc->sc_ah); |
855 | sc->sc_ah = NULL; | |
55624204 S |
856 | } |
857 | ||
285f2dda | 858 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
859 | { |
860 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
861 | |
862 | ath9k_ps_wakeup(sc); | |
863 | ||
55624204 | 864 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 865 | ath_deinit_leds(sc); |
55624204 | 866 | |
c7c18060 RM |
867 | ath9k_ps_restore(sc); |
868 | ||
55624204 S |
869 | ieee80211_unregister_hw(hw); |
870 | ath_rx_cleanup(sc); | |
871 | ath_tx_cleanup(sc); | |
285f2dda | 872 | ath9k_deinit_softc(sc); |
55624204 S |
873 | } |
874 | ||
875 | void ath_descdma_cleanup(struct ath_softc *sc, | |
876 | struct ath_descdma *dd, | |
877 | struct list_head *head) | |
878 | { | |
879 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
880 | dd->dd_desc_paddr); | |
881 | ||
882 | INIT_LIST_HEAD(head); | |
883 | kfree(dd->dd_bufptr); | |
884 | memset(dd, 0, sizeof(*dd)); | |
885 | } | |
886 | ||
55624204 S |
887 | /************************/ |
888 | /* Module Hooks */ | |
889 | /************************/ | |
890 | ||
891 | static int __init ath9k_init(void) | |
892 | { | |
893 | int error; | |
894 | ||
895 | /* Register rate control algorithm */ | |
896 | error = ath_rate_control_register(); | |
897 | if (error != 0) { | |
898 | printk(KERN_ERR | |
899 | "ath9k: Unable to register rate control " | |
900 | "algorithm: %d\n", | |
901 | error); | |
902 | goto err_out; | |
903 | } | |
904 | ||
55624204 S |
905 | error = ath_pci_init(); |
906 | if (error < 0) { | |
907 | printk(KERN_ERR | |
908 | "ath9k: No PCI devices found, driver not installed.\n"); | |
909 | error = -ENODEV; | |
eb272441 | 910 | goto err_rate_unregister; |
55624204 S |
911 | } |
912 | ||
913 | error = ath_ahb_init(); | |
914 | if (error < 0) { | |
915 | error = -ENODEV; | |
916 | goto err_pci_exit; | |
917 | } | |
918 | ||
919 | return 0; | |
920 | ||
921 | err_pci_exit: | |
922 | ath_pci_exit(); | |
923 | ||
55624204 S |
924 | err_rate_unregister: |
925 | ath_rate_control_unregister(); | |
926 | err_out: | |
927 | return error; | |
928 | } | |
929 | module_init(ath9k_init); | |
930 | ||
931 | static void __exit ath9k_exit(void) | |
932 | { | |
d584747b | 933 | is_ath9k_unloaded = true; |
55624204 S |
934 | ath_ahb_exit(); |
935 | ath_pci_exit(); | |
55624204 S |
936 | ath_rate_control_unregister(); |
937 | printk(KERN_INFO "%s: Driver unloaded\n", dev_info); | |
938 | } | |
939 | module_exit(ath9k_exit); |