Commit | Line | Data |
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55624204 S |
1 | /* |
2 | * Copyright (c) 2008-2009 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
5a0e3ad6 TH |
17 | #include <linux/slab.h> |
18 | ||
55624204 S |
19 | #include "ath9k.h" |
20 | ||
21 | static char *dev_info = "ath9k"; | |
22 | ||
23 | MODULE_AUTHOR("Atheros Communications"); | |
24 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
25 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
26 | MODULE_LICENSE("Dual BSD/GPL"); | |
27 | ||
28 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
29 | module_param_named(debug, ath9k_debug, uint, 0); | |
30 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
31 | ||
32 | int modparam_nohwcrypt; | |
33 | module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); | |
34 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); | |
35 | ||
93dbbcc4 | 36 | int led_blink; |
9a75c2ff VN |
37 | module_param_named(blink, led_blink, int, 0444); |
38 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); | |
39 | ||
8f5dcb1c VT |
40 | static int ath9k_btcoex_enable; |
41 | module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); | |
42 | MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); | |
43 | ||
4dc3530d MSS |
44 | int ath9k_pm_qos_value = ATH9K_PM_QOS_DEFAULT_VALUE; |
45 | module_param_named(pmqos, ath9k_pm_qos_value, int, S_IRUSR | S_IRGRP | S_IROTH); | |
46 | MODULE_PARM_DESC(pmqos, "User specified PM-QOS value"); | |
47 | ||
55624204 S |
48 | /* We use the hw_value as an index into our private channel structure */ |
49 | ||
50 | #define CHAN2G(_freq, _idx) { \ | |
b1c1d000 | 51 | .band = IEEE80211_BAND_2GHZ, \ |
55624204 S |
52 | .center_freq = (_freq), \ |
53 | .hw_value = (_idx), \ | |
54 | .max_power = 20, \ | |
55 | } | |
56 | ||
57 | #define CHAN5G(_freq, _idx) { \ | |
58 | .band = IEEE80211_BAND_5GHZ, \ | |
59 | .center_freq = (_freq), \ | |
60 | .hw_value = (_idx), \ | |
61 | .max_power = 20, \ | |
62 | } | |
63 | ||
64 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
65 | * on 5 MHz steps, we support the channels which we know | |
66 | * we have calibration data for all cards though to make | |
67 | * this static */ | |
f209f529 | 68 | static const struct ieee80211_channel ath9k_2ghz_chantable[] = { |
55624204 S |
69 | CHAN2G(2412, 0), /* Channel 1 */ |
70 | CHAN2G(2417, 1), /* Channel 2 */ | |
71 | CHAN2G(2422, 2), /* Channel 3 */ | |
72 | CHAN2G(2427, 3), /* Channel 4 */ | |
73 | CHAN2G(2432, 4), /* Channel 5 */ | |
74 | CHAN2G(2437, 5), /* Channel 6 */ | |
75 | CHAN2G(2442, 6), /* Channel 7 */ | |
76 | CHAN2G(2447, 7), /* Channel 8 */ | |
77 | CHAN2G(2452, 8), /* Channel 9 */ | |
78 | CHAN2G(2457, 9), /* Channel 10 */ | |
79 | CHAN2G(2462, 10), /* Channel 11 */ | |
80 | CHAN2G(2467, 11), /* Channel 12 */ | |
81 | CHAN2G(2472, 12), /* Channel 13 */ | |
82 | CHAN2G(2484, 13), /* Channel 14 */ | |
83 | }; | |
84 | ||
85 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
86 | * on 5 MHz steps, we support the channels which we know | |
87 | * we have calibration data for all cards though to make | |
88 | * this static */ | |
f209f529 | 89 | static const struct ieee80211_channel ath9k_5ghz_chantable[] = { |
55624204 S |
90 | /* _We_ call this UNII 1 */ |
91 | CHAN5G(5180, 14), /* Channel 36 */ | |
92 | CHAN5G(5200, 15), /* Channel 40 */ | |
93 | CHAN5G(5220, 16), /* Channel 44 */ | |
94 | CHAN5G(5240, 17), /* Channel 48 */ | |
95 | /* _We_ call this UNII 2 */ | |
96 | CHAN5G(5260, 18), /* Channel 52 */ | |
97 | CHAN5G(5280, 19), /* Channel 56 */ | |
98 | CHAN5G(5300, 20), /* Channel 60 */ | |
99 | CHAN5G(5320, 21), /* Channel 64 */ | |
100 | /* _We_ call this "Middle band" */ | |
101 | CHAN5G(5500, 22), /* Channel 100 */ | |
102 | CHAN5G(5520, 23), /* Channel 104 */ | |
103 | CHAN5G(5540, 24), /* Channel 108 */ | |
104 | CHAN5G(5560, 25), /* Channel 112 */ | |
105 | CHAN5G(5580, 26), /* Channel 116 */ | |
106 | CHAN5G(5600, 27), /* Channel 120 */ | |
107 | CHAN5G(5620, 28), /* Channel 124 */ | |
108 | CHAN5G(5640, 29), /* Channel 128 */ | |
109 | CHAN5G(5660, 30), /* Channel 132 */ | |
110 | CHAN5G(5680, 31), /* Channel 136 */ | |
111 | CHAN5G(5700, 32), /* Channel 140 */ | |
112 | /* _We_ call this UNII 3 */ | |
113 | CHAN5G(5745, 33), /* Channel 149 */ | |
114 | CHAN5G(5765, 34), /* Channel 153 */ | |
115 | CHAN5G(5785, 35), /* Channel 157 */ | |
116 | CHAN5G(5805, 36), /* Channel 161 */ | |
117 | CHAN5G(5825, 37), /* Channel 165 */ | |
118 | }; | |
119 | ||
120 | /* Atheros hardware rate code addition for short premble */ | |
121 | #define SHPCHECK(__hw_rate, __flags) \ | |
122 | ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) | |
123 | ||
124 | #define RATE(_bitrate, _hw_rate, _flags) { \ | |
125 | .bitrate = (_bitrate), \ | |
126 | .flags = (_flags), \ | |
127 | .hw_value = (_hw_rate), \ | |
128 | .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ | |
129 | } | |
130 | ||
131 | static struct ieee80211_rate ath9k_legacy_rates[] = { | |
132 | RATE(10, 0x1b, 0), | |
133 | RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), | |
134 | RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), | |
135 | RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), | |
136 | RATE(60, 0x0b, 0), | |
137 | RATE(90, 0x0f, 0), | |
138 | RATE(120, 0x0a, 0), | |
139 | RATE(180, 0x0e, 0), | |
140 | RATE(240, 0x09, 0), | |
141 | RATE(360, 0x0d, 0), | |
142 | RATE(480, 0x08, 0), | |
143 | RATE(540, 0x0c, 0), | |
144 | }; | |
145 | ||
285f2dda | 146 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 S |
147 | |
148 | /* | |
149 | * Read and write, they both share the same lock. We do this to serialize | |
150 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
151 | * as the FIFO on these devices can only accept sanely 2 requests. | |
152 | */ | |
153 | ||
154 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
155 | { | |
156 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
157 | struct ath_common *common = ath9k_hw_common(ah); | |
158 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
159 | ||
160 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
161 | unsigned long flags; | |
162 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
163 | iowrite32(val, sc->mem + reg_offset); | |
164 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
165 | } else | |
166 | iowrite32(val, sc->mem + reg_offset); | |
167 | } | |
168 | ||
169 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
170 | { | |
171 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
172 | struct ath_common *common = ath9k_hw_common(ah); | |
173 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
174 | u32 val; | |
175 | ||
176 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
177 | unsigned long flags; | |
178 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
179 | val = ioread32(sc->mem + reg_offset); | |
180 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
181 | } else | |
182 | val = ioread32(sc->mem + reg_offset); | |
183 | return val; | |
184 | } | |
185 | ||
186 | static const struct ath_ops ath9k_common_ops = { | |
187 | .read = ath9k_ioread32, | |
188 | .write = ath9k_iowrite32, | |
189 | }; | |
190 | ||
191 | /**************************/ | |
192 | /* Initialization */ | |
193 | /**************************/ | |
194 | ||
195 | static void setup_ht_cap(struct ath_softc *sc, | |
196 | struct ieee80211_sta_ht_cap *ht_info) | |
197 | { | |
3bb065a7 FF |
198 | struct ath_hw *ah = sc->sc_ah; |
199 | struct ath_common *common = ath9k_hw_common(ah); | |
55624204 | 200 | u8 tx_streams, rx_streams; |
3bb065a7 | 201 | int i, max_streams; |
55624204 S |
202 | |
203 | ht_info->ht_supported = true; | |
204 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
205 | IEEE80211_HT_CAP_SM_PS | | |
206 | IEEE80211_HT_CAP_SGI_40 | | |
207 | IEEE80211_HT_CAP_DSSSCCK40; | |
208 | ||
b0a33448 LR |
209 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) |
210 | ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; | |
211 | ||
6473d24d VT |
212 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) |
213 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
214 | ||
55624204 S |
215 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
216 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
217 | ||
7f1c7a6a VT |
218 | if (AR_SREV_9485(ah)) |
219 | max_streams = 1; | |
220 | else if (AR_SREV_9300_20_OR_LATER(ah)) | |
3bb065a7 FF |
221 | max_streams = 3; |
222 | else | |
223 | max_streams = 2; | |
224 | ||
7a37081e | 225 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
074a8c0d FF |
226 | if (max_streams >= 2) |
227 | ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; | |
228 | ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); | |
229 | } | |
230 | ||
55624204 S |
231 | /* set up supported mcs set */ |
232 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
61389f3e S |
233 | tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams); |
234 | rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams); | |
3bb065a7 | 235 | |
226afe68 JP |
236 | ath_dbg(common, ATH_DBG_CONFIG, |
237 | "TX streams %d, RX streams: %d\n", | |
238 | tx_streams, rx_streams); | |
55624204 S |
239 | |
240 | if (tx_streams != rx_streams) { | |
55624204 S |
241 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
242 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
243 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
244 | } | |
245 | ||
3bb065a7 FF |
246 | for (i = 0; i < rx_streams; i++) |
247 | ht_info->mcs.rx_mask[i] = 0xff; | |
55624204 S |
248 | |
249 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; | |
250 | } | |
251 | ||
252 | static int ath9k_reg_notifier(struct wiphy *wiphy, | |
253 | struct regulatory_request *request) | |
254 | { | |
255 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
256 | struct ath_wiphy *aphy = hw->priv; | |
257 | struct ath_softc *sc = aphy->sc; | |
258 | struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah); | |
259 | ||
260 | return ath_reg_notifier_apply(wiphy, request, reg); | |
261 | } | |
262 | ||
263 | /* | |
264 | * This function will allocate both the DMA descriptor structure, and the | |
265 | * buffers it contains. These are used to contain the descriptors used | |
266 | * by the system. | |
267 | */ | |
268 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
269 | struct list_head *head, const char *name, | |
4adfcded | 270 | int nbuf, int ndesc, bool is_tx) |
55624204 S |
271 | { |
272 | #define DS2PHYS(_dd, _ds) \ | |
273 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
274 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
275 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
276 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
4adfcded | 277 | u8 *ds; |
55624204 | 278 | struct ath_buf *bf; |
4adfcded | 279 | int i, bsize, error, desc_len; |
55624204 | 280 | |
226afe68 JP |
281 | ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
282 | name, nbuf, ndesc); | |
55624204 S |
283 | |
284 | INIT_LIST_HEAD(head); | |
4adfcded VT |
285 | |
286 | if (is_tx) | |
287 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
288 | else | |
289 | desc_len = sizeof(struct ath_desc); | |
290 | ||
55624204 | 291 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 292 | if ((desc_len % 4) != 0) { |
3800276a | 293 | ath_err(common, "ath_desc not DWORD aligned\n"); |
4adfcded | 294 | BUG_ON((desc_len % 4) != 0); |
55624204 S |
295 | error = -ENOMEM; |
296 | goto fail; | |
297 | } | |
298 | ||
4adfcded | 299 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
300 | |
301 | /* | |
302 | * Need additional DMA memory because we can't use | |
303 | * descriptors that cross the 4K page boundary. Assume | |
304 | * one skipped descriptor per 4K page. | |
305 | */ | |
306 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
307 | u32 ndesc_skipped = | |
308 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
309 | u32 dma_len; | |
310 | ||
311 | while (ndesc_skipped) { | |
4adfcded | 312 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
313 | dd->dd_desc_len += dma_len; |
314 | ||
315 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 316 | } |
55624204 S |
317 | } |
318 | ||
319 | /* allocate descriptors */ | |
320 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, | |
321 | &dd->dd_desc_paddr, GFP_KERNEL); | |
322 | if (dd->dd_desc == NULL) { | |
323 | error = -ENOMEM; | |
324 | goto fail; | |
325 | } | |
4adfcded | 326 | ds = (u8 *) dd->dd_desc; |
226afe68 JP |
327 | ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
328 | name, ds, (u32) dd->dd_desc_len, | |
329 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
55624204 S |
330 | |
331 | /* allocate buffers */ | |
332 | bsize = sizeof(struct ath_buf) * nbuf; | |
333 | bf = kzalloc(bsize, GFP_KERNEL); | |
334 | if (bf == NULL) { | |
335 | error = -ENOMEM; | |
336 | goto fail2; | |
337 | } | |
338 | dd->dd_bufptr = bf; | |
339 | ||
4adfcded | 340 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { |
55624204 S |
341 | bf->bf_desc = ds; |
342 | bf->bf_daddr = DS2PHYS(dd, ds); | |
343 | ||
344 | if (!(sc->sc_ah->caps.hw_caps & | |
345 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
346 | /* | |
347 | * Skip descriptor addresses which can cause 4KB | |
348 | * boundary crossing (addr + length) with a 32 dword | |
349 | * descriptor fetch. | |
350 | */ | |
351 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
352 | BUG_ON((caddr_t) bf->bf_desc >= | |
353 | ((caddr_t) dd->dd_desc + | |
354 | dd->dd_desc_len)); | |
355 | ||
4adfcded | 356 | ds += (desc_len * ndesc); |
55624204 S |
357 | bf->bf_desc = ds; |
358 | bf->bf_daddr = DS2PHYS(dd, ds); | |
359 | } | |
360 | } | |
361 | list_add_tail(&bf->list, head); | |
362 | } | |
363 | return 0; | |
364 | fail2: | |
365 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
366 | dd->dd_desc_paddr); | |
367 | fail: | |
368 | memset(dd, 0, sizeof(*dd)); | |
369 | return error; | |
370 | #undef ATH_DESC_4KB_BOUND_CHECK | |
371 | #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED | |
372 | #undef DS2PHYS | |
373 | } | |
374 | ||
285f2dda | 375 | static void ath9k_init_crypto(struct ath_softc *sc) |
55624204 | 376 | { |
285f2dda S |
377 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
378 | int i = 0; | |
55624204 S |
379 | |
380 | /* Get the hardware key cache size. */ | |
285f2dda | 381 | common->keymax = sc->sc_ah->caps.keycache_size; |
55624204 | 382 | if (common->keymax > ATH_KEYMAX) { |
226afe68 JP |
383 | ath_dbg(common, ATH_DBG_ANY, |
384 | "Warning, using only %u entries in %u key cache\n", | |
385 | ATH_KEYMAX, common->keymax); | |
55624204 S |
386 | common->keymax = ATH_KEYMAX; |
387 | } | |
388 | ||
389 | /* | |
390 | * Reset the key cache since some parts do not | |
391 | * reset the contents on initial power up. | |
392 | */ | |
393 | for (i = 0; i < common->keymax; i++) | |
040e539e | 394 | ath_hw_keyreset(common, (u16) i); |
55624204 | 395 | |
55624204 | 396 | /* |
285f2dda S |
397 | * Check whether the separate key cache entries |
398 | * are required to handle both tx+rx MIC keys. | |
399 | * With split mic keys the number of stations is limited | |
400 | * to 27 otherwise 59. | |
55624204 | 401 | */ |
117675d0 BR |
402 | if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) |
403 | common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED; | |
285f2dda S |
404 | } |
405 | ||
406 | static int ath9k_init_btcoex(struct ath_softc *sc) | |
407 | { | |
066dae93 FF |
408 | struct ath_txq *txq; |
409 | int r; | |
285f2dda S |
410 | |
411 | switch (sc->sc_ah->btcoex_hw.scheme) { | |
412 | case ATH_BTCOEX_CFG_NONE: | |
413 | break; | |
414 | case ATH_BTCOEX_CFG_2WIRE: | |
415 | ath9k_hw_btcoex_init_2wire(sc->sc_ah); | |
416 | break; | |
417 | case ATH_BTCOEX_CFG_3WIRE: | |
418 | ath9k_hw_btcoex_init_3wire(sc->sc_ah); | |
419 | r = ath_init_btcoex_timer(sc); | |
420 | if (r) | |
421 | return -1; | |
066dae93 FF |
422 | txq = sc->tx.txq_map[WME_AC_BE]; |
423 | ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum); | |
285f2dda S |
424 | sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; |
425 | break; | |
426 | default: | |
427 | WARN_ON(1); | |
428 | break; | |
429 | } | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
434 | static int ath9k_init_queues(struct ath_softc *sc) | |
435 | { | |
285f2dda S |
436 | int i = 0; |
437 | ||
285f2dda | 438 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 439 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
440 | |
441 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; | |
442 | ath_cabq_update(sc); | |
443 | ||
066dae93 FF |
444 | for (i = 0; i < WME_NUM_AC; i++) |
445 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); | |
55624204 | 446 | |
285f2dda | 447 | return 0; |
285f2dda S |
448 | } |
449 | ||
f209f529 | 450 | static int ath9k_init_channels_rates(struct ath_softc *sc) |
285f2dda | 451 | { |
f209f529 FF |
452 | void *channels; |
453 | ||
cac4220b FF |
454 | BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + |
455 | ARRAY_SIZE(ath9k_5ghz_chantable) != | |
456 | ATH9K_NUM_CHANNELS); | |
457 | ||
d4659912 | 458 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { |
f209f529 FF |
459 | channels = kmemdup(ath9k_2ghz_chantable, |
460 | sizeof(ath9k_2ghz_chantable), GFP_KERNEL); | |
461 | if (!channels) | |
462 | return -ENOMEM; | |
463 | ||
464 | sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; | |
285f2dda S |
465 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; |
466 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = | |
467 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
468 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; | |
469 | sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = | |
470 | ARRAY_SIZE(ath9k_legacy_rates); | |
55624204 S |
471 | } |
472 | ||
d4659912 | 473 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { |
f209f529 FF |
474 | channels = kmemdup(ath9k_5ghz_chantable, |
475 | sizeof(ath9k_5ghz_chantable), GFP_KERNEL); | |
476 | if (!channels) { | |
477 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) | |
478 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
479 | return -ENOMEM; | |
480 | } | |
481 | ||
482 | sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; | |
285f2dda S |
483 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; |
484 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = | |
485 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
486 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
487 | ath9k_legacy_rates + 4; | |
488 | sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = | |
489 | ARRAY_SIZE(ath9k_legacy_rates) - 4; | |
490 | } | |
f209f529 | 491 | return 0; |
285f2dda | 492 | } |
55624204 | 493 | |
285f2dda S |
494 | static void ath9k_init_misc(struct ath_softc *sc) |
495 | { | |
496 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
497 | int i = 0; | |
498 | ||
285f2dda | 499 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); |
55624204 S |
500 | |
501 | sc->config.txpowlimit = ATH_TXPOWER_MAX; | |
502 | ||
285f2dda | 503 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
55624204 S |
504 | sc->sc_flags |= SC_OP_TXAGGR; |
505 | sc->sc_flags |= SC_OP_RXAGGR; | |
506 | } | |
507 | ||
285f2dda S |
508 | common->tx_chainmask = sc->sc_ah->caps.tx_chainmask; |
509 | common->rx_chainmask = sc->sc_ah->caps.rx_chainmask; | |
55624204 | 510 | |
8fe65368 | 511 | ath9k_hw_set_diversity(sc->sc_ah, true); |
285f2dda | 512 | sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah); |
55624204 | 513 | |
364734fa | 514 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
55624204 | 515 | |
285f2dda | 516 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 517 | |
55624204 S |
518 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
519 | sc->beacon.bslot[i] = NULL; | |
520 | sc->beacon.bslot_aphy[i] = NULL; | |
521 | } | |
102885a5 VT |
522 | |
523 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
524 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
285f2dda | 525 | } |
55624204 | 526 | |
285f2dda S |
527 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid, |
528 | const struct ath_bus_ops *bus_ops) | |
529 | { | |
530 | struct ath_hw *ah = NULL; | |
531 | struct ath_common *common; | |
532 | int ret = 0, i; | |
533 | int csz = 0; | |
55624204 | 534 | |
285f2dda S |
535 | ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); |
536 | if (!ah) | |
537 | return -ENOMEM; | |
538 | ||
539 | ah->hw_version.devid = devid; | |
540 | ah->hw_version.subsysid = subsysid; | |
541 | sc->sc_ah = ah; | |
542 | ||
a05b5d45 FF |
543 | if (!sc->dev->platform_data) |
544 | ah->ah_flags |= AH_USE_EEPROM; | |
545 | ||
285f2dda S |
546 | common = ath9k_hw_common(ah); |
547 | common->ops = &ath9k_common_ops; | |
548 | common->bus_ops = bus_ops; | |
549 | common->ah = ah; | |
550 | common->hw = sc->hw; | |
551 | common->priv = sc; | |
552 | common->debug_mask = ath9k_debug; | |
8f5dcb1c | 553 | common->btcoex_enabled = ath9k_btcoex_enable == 1; |
20b25744 | 554 | spin_lock_init(&common->cc_lock); |
285f2dda S |
555 | |
556 | spin_lock_init(&sc->wiphy_lock); | |
285f2dda S |
557 | spin_lock_init(&sc->sc_serial_rw); |
558 | spin_lock_init(&sc->sc_pm_lock); | |
559 | mutex_init(&sc->mutex); | |
560 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); | |
561 | tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, | |
562 | (unsigned long)sc); | |
563 | ||
564 | /* | |
565 | * Cache line size is used to size and align various | |
566 | * structures used to communicate with the hardware. | |
567 | */ | |
568 | ath_read_cachesize(common, &csz); | |
569 | common->cachelsz = csz << 2; /* convert to bytes */ | |
570 | ||
d70357d5 | 571 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 572 | ret = ath9k_hw_init(ah); |
d70357d5 | 573 | if (ret) |
285f2dda | 574 | goto err_hw; |
55624204 | 575 | |
285f2dda S |
576 | ret = ath9k_init_queues(sc); |
577 | if (ret) | |
578 | goto err_queues; | |
579 | ||
580 | ret = ath9k_init_btcoex(sc); | |
581 | if (ret) | |
582 | goto err_btcoex; | |
583 | ||
f209f529 FF |
584 | ret = ath9k_init_channels_rates(sc); |
585 | if (ret) | |
586 | goto err_btcoex; | |
587 | ||
285f2dda | 588 | ath9k_init_crypto(sc); |
285f2dda S |
589 | ath9k_init_misc(sc); |
590 | ||
55624204 | 591 | return 0; |
285f2dda S |
592 | |
593 | err_btcoex: | |
55624204 S |
594 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
595 | if (ATH_TXQ_SETUP(sc, i)) | |
596 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda | 597 | err_queues: |
285f2dda S |
598 | ath9k_hw_deinit(ah); |
599 | err_hw: | |
600 | tasklet_kill(&sc->intr_tq); | |
601 | tasklet_kill(&sc->bcon_tasklet); | |
55624204 | 602 | |
285f2dda S |
603 | kfree(ah); |
604 | sc->sc_ah = NULL; | |
605 | ||
606 | return ret; | |
55624204 S |
607 | } |
608 | ||
babcbc29 FF |
609 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
610 | { | |
611 | struct ieee80211_supported_band *sband; | |
612 | struct ieee80211_channel *chan; | |
613 | struct ath_hw *ah = sc->sc_ah; | |
614 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
615 | int i; | |
616 | ||
617 | sband = &sc->sbands[band]; | |
618 | for (i = 0; i < sband->n_channels; i++) { | |
619 | chan = &sband->channels[i]; | |
620 | ah->curchan = &ah->channels[chan->hw_value]; | |
621 | ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20); | |
622 | ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); | |
623 | chan->max_power = reg->max_power_level / 2; | |
624 | } | |
625 | } | |
626 | ||
627 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
628 | { | |
629 | struct ath_hw *ah = sc->sc_ah; | |
630 | struct ath9k_channel *curchan = ah->curchan; | |
631 | ||
632 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
633 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); | |
634 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
635 | ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); | |
636 | ||
637 | ah->curchan = curchan; | |
638 | } | |
639 | ||
285f2dda | 640 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 641 | { |
285f2dda S |
642 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
643 | ||
55624204 S |
644 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
645 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
646 | IEEE80211_HW_SIGNAL_DBM | | |
55624204 S |
647 | IEEE80211_HW_SUPPORTS_PS | |
648 | IEEE80211_HW_PS_NULLFUNC_STACK | | |
05df4986 | 649 | IEEE80211_HW_SPECTRUM_MGMT | |
0ce3bcfc MSS |
650 | IEEE80211_HW_REPORTS_TX_ACK_STATUS | |
651 | IEEE80211_HW_NEED_DTIM_PERIOD; | |
55624204 | 652 | |
5ffaf8a3 LR |
653 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
654 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
655 | ||
55624204 S |
656 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt) |
657 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; | |
658 | ||
659 | hw->wiphy->interface_modes = | |
c426ee24 JB |
660 | BIT(NL80211_IFTYPE_P2P_GO) | |
661 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
55624204 | 662 | BIT(NL80211_IFTYPE_AP) | |
e51f3eff | 663 | BIT(NL80211_IFTYPE_WDS) | |
55624204 S |
664 | BIT(NL80211_IFTYPE_STATION) | |
665 | BIT(NL80211_IFTYPE_ADHOC) | | |
666 | BIT(NL80211_IFTYPE_MESH_POINT); | |
667 | ||
008443de LR |
668 | if (AR_SREV_5416(sc->sc_ah)) |
669 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
55624204 S |
670 | |
671 | hw->queues = 4; | |
672 | hw->max_rates = 4; | |
673 | hw->channel_change_time = 5000; | |
674 | hw->max_listen_interval = 10; | |
65896510 | 675 | hw->max_rate_tries = 10; |
55624204 S |
676 | hw->sta_data_size = sizeof(struct ath_node); |
677 | hw->vif_data_size = sizeof(struct ath_vif); | |
678 | ||
6e5c2b4e | 679 | #ifdef CONFIG_ATH9K_RATE_CONTROL |
55624204 | 680 | hw->rate_control_algorithm = "ath9k_rate_control"; |
6e5c2b4e | 681 | #endif |
55624204 | 682 | |
d4659912 | 683 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
55624204 S |
684 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
685 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
d4659912 | 686 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
55624204 S |
687 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
688 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
285f2dda S |
689 | |
690 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { | |
d4659912 | 691 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
285f2dda | 692 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); |
d4659912 | 693 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
285f2dda S |
694 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); |
695 | } | |
696 | ||
697 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
698 | } |
699 | ||
285f2dda | 700 | int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, |
55624204 S |
701 | const struct ath_bus_ops *bus_ops) |
702 | { | |
703 | struct ieee80211_hw *hw = sc->hw; | |
9fa23e17 | 704 | struct ath_wiphy *aphy = hw->priv; |
55624204 S |
705 | struct ath_common *common; |
706 | struct ath_hw *ah; | |
285f2dda | 707 | int error = 0; |
55624204 S |
708 | struct ath_regulatory *reg; |
709 | ||
285f2dda S |
710 | /* Bring up device */ |
711 | error = ath9k_init_softc(devid, sc, subsysid, bus_ops); | |
55624204 | 712 | if (error != 0) |
285f2dda | 713 | goto error_init; |
55624204 S |
714 | |
715 | ah = sc->sc_ah; | |
716 | common = ath9k_hw_common(ah); | |
285f2dda | 717 | ath9k_set_hw_capab(sc, hw); |
55624204 | 718 | |
285f2dda | 719 | /* Initialize regulatory */ |
55624204 S |
720 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
721 | ath9k_reg_notifier); | |
722 | if (error) | |
285f2dda | 723 | goto error_regd; |
55624204 S |
724 | |
725 | reg = &common->regulatory; | |
726 | ||
285f2dda | 727 | /* Setup TX DMA */ |
55624204 S |
728 | error = ath_tx_init(sc, ATH_TXBUF); |
729 | if (error != 0) | |
285f2dda | 730 | goto error_tx; |
55624204 | 731 | |
285f2dda | 732 | /* Setup RX DMA */ |
55624204 S |
733 | error = ath_rx_init(sc, ATH_RXBUF); |
734 | if (error != 0) | |
285f2dda | 735 | goto error_rx; |
55624204 | 736 | |
babcbc29 FF |
737 | ath9k_init_txpower_limits(sc); |
738 | ||
285f2dda | 739 | /* Register with mac80211 */ |
55624204 | 740 | error = ieee80211_register_hw(hw); |
285f2dda S |
741 | if (error) |
742 | goto error_register; | |
55624204 | 743 | |
eb272441 BG |
744 | error = ath9k_init_debug(ah); |
745 | if (error) { | |
3800276a | 746 | ath_err(common, "Unable to create debugfs files\n"); |
eb272441 BG |
747 | goto error_world; |
748 | } | |
749 | ||
285f2dda | 750 | /* Handle world regulatory */ |
55624204 S |
751 | if (!ath_is_world_regd(reg)) { |
752 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
753 | if (error) | |
285f2dda | 754 | goto error_world; |
55624204 S |
755 | } |
756 | ||
347809fc | 757 | INIT_WORK(&sc->hw_check_work, ath_hw_check); |
9f42c2b6 | 758 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); |
285f2dda S |
759 | INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work); |
760 | INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work); | |
761 | sc->wiphy_scheduler_int = msecs_to_jiffies(500); | |
9fa23e17 | 762 | aphy->last_rssi = ATH_RSSI_DUMMY_MARKER; |
55624204 | 763 | |
285f2dda | 764 | ath_init_leds(sc); |
55624204 S |
765 | ath_start_rfkill_poll(sc); |
766 | ||
98c316e3 | 767 | pm_qos_add_request(&sc->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, |
10598c12 VN |
768 | PM_QOS_DEFAULT_VALUE); |
769 | ||
55624204 S |
770 | return 0; |
771 | ||
285f2dda S |
772 | error_world: |
773 | ieee80211_unregister_hw(hw); | |
774 | error_register: | |
775 | ath_rx_cleanup(sc); | |
776 | error_rx: | |
777 | ath_tx_cleanup(sc); | |
778 | error_tx: | |
779 | /* Nothing */ | |
780 | error_regd: | |
781 | ath9k_deinit_softc(sc); | |
782 | error_init: | |
55624204 S |
783 | return error; |
784 | } | |
785 | ||
786 | /*****************************/ | |
787 | /* De-Initialization */ | |
788 | /*****************************/ | |
789 | ||
285f2dda | 790 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 791 | { |
285f2dda | 792 | int i = 0; |
55624204 | 793 | |
f209f529 FF |
794 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) |
795 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
796 | ||
797 | if (sc->sbands[IEEE80211_BAND_5GHZ].channels) | |
798 | kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels); | |
799 | ||
285f2dda S |
800 | if ((sc->btcoex.no_stomp_timer) && |
801 | sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) | |
802 | ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer); | |
55624204 | 803 | |
285f2dda S |
804 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
805 | if (ATH_TXQ_SETUP(sc, i)) | |
806 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
807 | ||
285f2dda S |
808 | ath9k_hw_deinit(sc->sc_ah); |
809 | ||
810 | tasklet_kill(&sc->intr_tq); | |
811 | tasklet_kill(&sc->bcon_tasklet); | |
736b3a27 S |
812 | |
813 | kfree(sc->sc_ah); | |
814 | sc->sc_ah = NULL; | |
55624204 S |
815 | } |
816 | ||
285f2dda | 817 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
818 | { |
819 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
820 | int i = 0; |
821 | ||
822 | ath9k_ps_wakeup(sc); | |
823 | ||
55624204 | 824 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 825 | ath_deinit_leds(sc); |
55624204 S |
826 | |
827 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
828 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
829 | if (aphy == NULL) | |
830 | continue; | |
831 | sc->sec_wiphy[i] = NULL; | |
832 | ieee80211_unregister_hw(aphy->hw); | |
833 | ieee80211_free_hw(aphy->hw); | |
834 | } | |
285f2dda | 835 | |
55624204 | 836 | ieee80211_unregister_hw(hw); |
98c316e3 | 837 | pm_qos_remove_request(&sc->pm_qos_req); |
55624204 S |
838 | ath_rx_cleanup(sc); |
839 | ath_tx_cleanup(sc); | |
285f2dda | 840 | ath9k_deinit_softc(sc); |
447a42c2 | 841 | kfree(sc->sec_wiphy); |
55624204 S |
842 | } |
843 | ||
844 | void ath_descdma_cleanup(struct ath_softc *sc, | |
845 | struct ath_descdma *dd, | |
846 | struct list_head *head) | |
847 | { | |
848 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
849 | dd->dd_desc_paddr); | |
850 | ||
851 | INIT_LIST_HEAD(head); | |
852 | kfree(dd->dd_bufptr); | |
853 | memset(dd, 0, sizeof(*dd)); | |
854 | } | |
855 | ||
55624204 S |
856 | /************************/ |
857 | /* Module Hooks */ | |
858 | /************************/ | |
859 | ||
860 | static int __init ath9k_init(void) | |
861 | { | |
862 | int error; | |
863 | ||
864 | /* Register rate control algorithm */ | |
865 | error = ath_rate_control_register(); | |
866 | if (error != 0) { | |
867 | printk(KERN_ERR | |
868 | "ath9k: Unable to register rate control " | |
869 | "algorithm: %d\n", | |
870 | error); | |
871 | goto err_out; | |
872 | } | |
873 | ||
55624204 S |
874 | error = ath_pci_init(); |
875 | if (error < 0) { | |
876 | printk(KERN_ERR | |
877 | "ath9k: No PCI devices found, driver not installed.\n"); | |
878 | error = -ENODEV; | |
eb272441 | 879 | goto err_rate_unregister; |
55624204 S |
880 | } |
881 | ||
882 | error = ath_ahb_init(); | |
883 | if (error < 0) { | |
884 | error = -ENODEV; | |
885 | goto err_pci_exit; | |
886 | } | |
887 | ||
888 | return 0; | |
889 | ||
890 | err_pci_exit: | |
891 | ath_pci_exit(); | |
892 | ||
55624204 S |
893 | err_rate_unregister: |
894 | ath_rate_control_unregister(); | |
895 | err_out: | |
896 | return error; | |
897 | } | |
898 | module_init(ath9k_init); | |
899 | ||
900 | static void __exit ath9k_exit(void) | |
901 | { | |
902 | ath_ahb_exit(); | |
903 | ath_pci_exit(); | |
55624204 S |
904 | ath_rate_control_unregister(); |
905 | printk(KERN_INFO "%s: Driver unloaded\n", dev_info); | |
906 | } | |
907 | module_exit(ath9k_exit); |