Commit | Line | Data |
---|---|---|
55624204 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
55624204 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
b7f080cf | 17 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
6fb1b1e1 | 19 | #include <linux/ath9k_platform.h> |
5a0e3ad6 | 20 | |
55624204 S |
21 | #include "ath9k.h" |
22 | ||
23 | static char *dev_info = "ath9k"; | |
24 | ||
25 | MODULE_AUTHOR("Atheros Communications"); | |
26 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
27 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
28 | MODULE_LICENSE("Dual BSD/GPL"); | |
29 | ||
30 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
31 | module_param_named(debug, ath9k_debug, uint, 0); | |
32 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
33 | ||
3e6109c5 JL |
34 | int ath9k_modparam_nohwcrypt; |
35 | module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); | |
55624204 S |
36 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); |
37 | ||
93dbbcc4 | 38 | int led_blink; |
9a75c2ff VN |
39 | module_param_named(blink, led_blink, int, 0444); |
40 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); | |
41 | ||
8f5dcb1c VT |
42 | static int ath9k_btcoex_enable; |
43 | module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); | |
44 | MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); | |
45 | ||
d584747b | 46 | bool is_ath9k_unloaded; |
55624204 S |
47 | /* We use the hw_value as an index into our private channel structure */ |
48 | ||
49 | #define CHAN2G(_freq, _idx) { \ | |
b1c1d000 | 50 | .band = IEEE80211_BAND_2GHZ, \ |
55624204 S |
51 | .center_freq = (_freq), \ |
52 | .hw_value = (_idx), \ | |
53 | .max_power = 20, \ | |
54 | } | |
55 | ||
56 | #define CHAN5G(_freq, _idx) { \ | |
57 | .band = IEEE80211_BAND_5GHZ, \ | |
58 | .center_freq = (_freq), \ | |
59 | .hw_value = (_idx), \ | |
60 | .max_power = 20, \ | |
61 | } | |
62 | ||
63 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
64 | * on 5 MHz steps, we support the channels which we know | |
65 | * we have calibration data for all cards though to make | |
66 | * this static */ | |
f209f529 | 67 | static const struct ieee80211_channel ath9k_2ghz_chantable[] = { |
55624204 S |
68 | CHAN2G(2412, 0), /* Channel 1 */ |
69 | CHAN2G(2417, 1), /* Channel 2 */ | |
70 | CHAN2G(2422, 2), /* Channel 3 */ | |
71 | CHAN2G(2427, 3), /* Channel 4 */ | |
72 | CHAN2G(2432, 4), /* Channel 5 */ | |
73 | CHAN2G(2437, 5), /* Channel 6 */ | |
74 | CHAN2G(2442, 6), /* Channel 7 */ | |
75 | CHAN2G(2447, 7), /* Channel 8 */ | |
76 | CHAN2G(2452, 8), /* Channel 9 */ | |
77 | CHAN2G(2457, 9), /* Channel 10 */ | |
78 | CHAN2G(2462, 10), /* Channel 11 */ | |
79 | CHAN2G(2467, 11), /* Channel 12 */ | |
80 | CHAN2G(2472, 12), /* Channel 13 */ | |
81 | CHAN2G(2484, 13), /* Channel 14 */ | |
82 | }; | |
83 | ||
84 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
85 | * on 5 MHz steps, we support the channels which we know | |
86 | * we have calibration data for all cards though to make | |
87 | * this static */ | |
f209f529 | 88 | static const struct ieee80211_channel ath9k_5ghz_chantable[] = { |
55624204 S |
89 | /* _We_ call this UNII 1 */ |
90 | CHAN5G(5180, 14), /* Channel 36 */ | |
91 | CHAN5G(5200, 15), /* Channel 40 */ | |
92 | CHAN5G(5220, 16), /* Channel 44 */ | |
93 | CHAN5G(5240, 17), /* Channel 48 */ | |
94 | /* _We_ call this UNII 2 */ | |
95 | CHAN5G(5260, 18), /* Channel 52 */ | |
96 | CHAN5G(5280, 19), /* Channel 56 */ | |
97 | CHAN5G(5300, 20), /* Channel 60 */ | |
98 | CHAN5G(5320, 21), /* Channel 64 */ | |
99 | /* _We_ call this "Middle band" */ | |
100 | CHAN5G(5500, 22), /* Channel 100 */ | |
101 | CHAN5G(5520, 23), /* Channel 104 */ | |
102 | CHAN5G(5540, 24), /* Channel 108 */ | |
103 | CHAN5G(5560, 25), /* Channel 112 */ | |
104 | CHAN5G(5580, 26), /* Channel 116 */ | |
105 | CHAN5G(5600, 27), /* Channel 120 */ | |
106 | CHAN5G(5620, 28), /* Channel 124 */ | |
107 | CHAN5G(5640, 29), /* Channel 128 */ | |
108 | CHAN5G(5660, 30), /* Channel 132 */ | |
109 | CHAN5G(5680, 31), /* Channel 136 */ | |
110 | CHAN5G(5700, 32), /* Channel 140 */ | |
111 | /* _We_ call this UNII 3 */ | |
112 | CHAN5G(5745, 33), /* Channel 149 */ | |
113 | CHAN5G(5765, 34), /* Channel 153 */ | |
114 | CHAN5G(5785, 35), /* Channel 157 */ | |
115 | CHAN5G(5805, 36), /* Channel 161 */ | |
116 | CHAN5G(5825, 37), /* Channel 165 */ | |
117 | }; | |
118 | ||
119 | /* Atheros hardware rate code addition for short premble */ | |
120 | #define SHPCHECK(__hw_rate, __flags) \ | |
121 | ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) | |
122 | ||
123 | #define RATE(_bitrate, _hw_rate, _flags) { \ | |
124 | .bitrate = (_bitrate), \ | |
125 | .flags = (_flags), \ | |
126 | .hw_value = (_hw_rate), \ | |
127 | .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ | |
128 | } | |
129 | ||
130 | static struct ieee80211_rate ath9k_legacy_rates[] = { | |
131 | RATE(10, 0x1b, 0), | |
132 | RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), | |
133 | RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), | |
134 | RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), | |
135 | RATE(60, 0x0b, 0), | |
136 | RATE(90, 0x0f, 0), | |
137 | RATE(120, 0x0a, 0), | |
138 | RATE(180, 0x0e, 0), | |
139 | RATE(240, 0x09, 0), | |
140 | RATE(360, 0x0d, 0), | |
141 | RATE(480, 0x08, 0), | |
142 | RATE(540, 0x0c, 0), | |
143 | }; | |
144 | ||
0cf55c21 FF |
145 | #ifdef CONFIG_MAC80211_LEDS |
146 | static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { | |
147 | { .throughput = 0 * 1024, .blink_time = 334 }, | |
148 | { .throughput = 1 * 1024, .blink_time = 260 }, | |
149 | { .throughput = 5 * 1024, .blink_time = 220 }, | |
150 | { .throughput = 10 * 1024, .blink_time = 190 }, | |
151 | { .throughput = 20 * 1024, .blink_time = 170 }, | |
152 | { .throughput = 50 * 1024, .blink_time = 150 }, | |
153 | { .throughput = 70 * 1024, .blink_time = 130 }, | |
154 | { .throughput = 100 * 1024, .blink_time = 110 }, | |
155 | { .throughput = 200 * 1024, .blink_time = 80 }, | |
156 | { .throughput = 300 * 1024, .blink_time = 50 }, | |
157 | }; | |
158 | #endif | |
159 | ||
285f2dda | 160 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 S |
161 | |
162 | /* | |
163 | * Read and write, they both share the same lock. We do this to serialize | |
164 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
165 | * as the FIFO on these devices can only accept sanely 2 requests. | |
166 | */ | |
167 | ||
168 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
169 | { | |
170 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
171 | struct ath_common *common = ath9k_hw_common(ah); | |
172 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
173 | ||
174 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
175 | unsigned long flags; | |
176 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
177 | iowrite32(val, sc->mem + reg_offset); | |
178 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
179 | } else | |
180 | iowrite32(val, sc->mem + reg_offset); | |
181 | } | |
182 | ||
183 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
184 | { | |
185 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
186 | struct ath_common *common = ath9k_hw_common(ah); | |
187 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
188 | u32 val; | |
189 | ||
190 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
191 | unsigned long flags; | |
192 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
193 | val = ioread32(sc->mem + reg_offset); | |
194 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
195 | } else | |
196 | val = ioread32(sc->mem + reg_offset); | |
197 | return val; | |
198 | } | |
199 | ||
5479de6e RM |
200 | static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, |
201 | u32 set, u32 clr) | |
202 | { | |
203 | u32 val; | |
204 | ||
205 | val = ioread32(sc->mem + reg_offset); | |
206 | val &= ~clr; | |
207 | val |= set; | |
208 | iowrite32(val, sc->mem + reg_offset); | |
209 | ||
210 | return val; | |
211 | } | |
212 | ||
845e03c9 FF |
213 | static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) |
214 | { | |
215 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
216 | struct ath_common *common = ath9k_hw_common(ah); | |
217 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
218 | unsigned long uninitialized_var(flags); | |
219 | u32 val; | |
220 | ||
5479de6e | 221 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { |
845e03c9 | 222 | spin_lock_irqsave(&sc->sc_serial_rw, flags); |
5479de6e | 223 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); |
845e03c9 | 224 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); |
5479de6e RM |
225 | } else |
226 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); | |
845e03c9 FF |
227 | |
228 | return val; | |
229 | } | |
230 | ||
55624204 S |
231 | /**************************/ |
232 | /* Initialization */ | |
233 | /**************************/ | |
234 | ||
235 | static void setup_ht_cap(struct ath_softc *sc, | |
236 | struct ieee80211_sta_ht_cap *ht_info) | |
237 | { | |
3bb065a7 FF |
238 | struct ath_hw *ah = sc->sc_ah; |
239 | struct ath_common *common = ath9k_hw_common(ah); | |
55624204 | 240 | u8 tx_streams, rx_streams; |
3bb065a7 | 241 | int i, max_streams; |
55624204 S |
242 | |
243 | ht_info->ht_supported = true; | |
244 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
245 | IEEE80211_HT_CAP_SM_PS | | |
246 | IEEE80211_HT_CAP_SGI_40 | | |
247 | IEEE80211_HT_CAP_DSSSCCK40; | |
248 | ||
b0a33448 LR |
249 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) |
250 | ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; | |
251 | ||
6473d24d VT |
252 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) |
253 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
254 | ||
55624204 S |
255 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
256 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
257 | ||
7216198d | 258 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) |
7f1c7a6a VT |
259 | max_streams = 1; |
260 | else if (AR_SREV_9300_20_OR_LATER(ah)) | |
3bb065a7 FF |
261 | max_streams = 3; |
262 | else | |
263 | max_streams = 2; | |
264 | ||
7a37081e | 265 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
074a8c0d FF |
266 | if (max_streams >= 2) |
267 | ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; | |
268 | ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); | |
269 | } | |
270 | ||
55624204 S |
271 | /* set up supported mcs set */ |
272 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
82b2d334 FF |
273 | tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); |
274 | rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); | |
3bb065a7 | 275 | |
226afe68 JP |
276 | ath_dbg(common, ATH_DBG_CONFIG, |
277 | "TX streams %d, RX streams: %d\n", | |
278 | tx_streams, rx_streams); | |
55624204 S |
279 | |
280 | if (tx_streams != rx_streams) { | |
55624204 S |
281 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
282 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
283 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
284 | } | |
285 | ||
3bb065a7 FF |
286 | for (i = 0; i < rx_streams; i++) |
287 | ht_info->mcs.rx_mask[i] = 0xff; | |
55624204 S |
288 | |
289 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; | |
290 | } | |
291 | ||
292 | static int ath9k_reg_notifier(struct wiphy *wiphy, | |
293 | struct regulatory_request *request) | |
294 | { | |
295 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
9ac58615 | 296 | struct ath_softc *sc = hw->priv; |
55624204 S |
297 | struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah); |
298 | ||
299 | return ath_reg_notifier_apply(wiphy, request, reg); | |
300 | } | |
301 | ||
302 | /* | |
303 | * This function will allocate both the DMA descriptor structure, and the | |
304 | * buffers it contains. These are used to contain the descriptors used | |
305 | * by the system. | |
306 | */ | |
307 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
308 | struct list_head *head, const char *name, | |
4adfcded | 309 | int nbuf, int ndesc, bool is_tx) |
55624204 | 310 | { |
55624204 | 311 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4adfcded | 312 | u8 *ds; |
55624204 | 313 | struct ath_buf *bf; |
4adfcded | 314 | int i, bsize, error, desc_len; |
55624204 | 315 | |
226afe68 JP |
316 | ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
317 | name, nbuf, ndesc); | |
55624204 S |
318 | |
319 | INIT_LIST_HEAD(head); | |
4adfcded VT |
320 | |
321 | if (is_tx) | |
322 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
323 | else | |
324 | desc_len = sizeof(struct ath_desc); | |
325 | ||
55624204 | 326 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 327 | if ((desc_len % 4) != 0) { |
3800276a | 328 | ath_err(common, "ath_desc not DWORD aligned\n"); |
4adfcded | 329 | BUG_ON((desc_len % 4) != 0); |
55624204 S |
330 | error = -ENOMEM; |
331 | goto fail; | |
332 | } | |
333 | ||
4adfcded | 334 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
335 | |
336 | /* | |
337 | * Need additional DMA memory because we can't use | |
338 | * descriptors that cross the 4K page boundary. Assume | |
339 | * one skipped descriptor per 4K page. | |
340 | */ | |
341 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
342 | u32 ndesc_skipped = | |
343 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
344 | u32 dma_len; | |
345 | ||
346 | while (ndesc_skipped) { | |
4adfcded | 347 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
348 | dd->dd_desc_len += dma_len; |
349 | ||
350 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 351 | } |
55624204 S |
352 | } |
353 | ||
354 | /* allocate descriptors */ | |
355 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, | |
356 | &dd->dd_desc_paddr, GFP_KERNEL); | |
357 | if (dd->dd_desc == NULL) { | |
358 | error = -ENOMEM; | |
359 | goto fail; | |
360 | } | |
4adfcded | 361 | ds = (u8 *) dd->dd_desc; |
226afe68 JP |
362 | ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
363 | name, ds, (u32) dd->dd_desc_len, | |
364 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
55624204 S |
365 | |
366 | /* allocate buffers */ | |
367 | bsize = sizeof(struct ath_buf) * nbuf; | |
368 | bf = kzalloc(bsize, GFP_KERNEL); | |
369 | if (bf == NULL) { | |
370 | error = -ENOMEM; | |
371 | goto fail2; | |
372 | } | |
373 | dd->dd_bufptr = bf; | |
374 | ||
4adfcded | 375 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { |
55624204 S |
376 | bf->bf_desc = ds; |
377 | bf->bf_daddr = DS2PHYS(dd, ds); | |
378 | ||
379 | if (!(sc->sc_ah->caps.hw_caps & | |
380 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
381 | /* | |
382 | * Skip descriptor addresses which can cause 4KB | |
383 | * boundary crossing (addr + length) with a 32 dword | |
384 | * descriptor fetch. | |
385 | */ | |
386 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
387 | BUG_ON((caddr_t) bf->bf_desc >= | |
388 | ((caddr_t) dd->dd_desc + | |
389 | dd->dd_desc_len)); | |
390 | ||
4adfcded | 391 | ds += (desc_len * ndesc); |
55624204 S |
392 | bf->bf_desc = ds; |
393 | bf->bf_daddr = DS2PHYS(dd, ds); | |
394 | } | |
395 | } | |
396 | list_add_tail(&bf->list, head); | |
397 | } | |
398 | return 0; | |
399 | fail2: | |
400 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
401 | dd->dd_desc_paddr); | |
402 | fail: | |
403 | memset(dd, 0, sizeof(*dd)); | |
404 | return error; | |
55624204 S |
405 | } |
406 | ||
285f2dda S |
407 | static int ath9k_init_btcoex(struct ath_softc *sc) |
408 | { | |
066dae93 FF |
409 | struct ath_txq *txq; |
410 | int r; | |
285f2dda S |
411 | |
412 | switch (sc->sc_ah->btcoex_hw.scheme) { | |
413 | case ATH_BTCOEX_CFG_NONE: | |
414 | break; | |
415 | case ATH_BTCOEX_CFG_2WIRE: | |
416 | ath9k_hw_btcoex_init_2wire(sc->sc_ah); | |
417 | break; | |
418 | case ATH_BTCOEX_CFG_3WIRE: | |
419 | ath9k_hw_btcoex_init_3wire(sc->sc_ah); | |
420 | r = ath_init_btcoex_timer(sc); | |
421 | if (r) | |
422 | return -1; | |
066dae93 FF |
423 | txq = sc->tx.txq_map[WME_AC_BE]; |
424 | ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum); | |
285f2dda S |
425 | sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; |
426 | break; | |
427 | default: | |
428 | WARN_ON(1); | |
429 | break; | |
430 | } | |
431 | ||
432 | return 0; | |
433 | } | |
434 | ||
435 | static int ath9k_init_queues(struct ath_softc *sc) | |
436 | { | |
285f2dda S |
437 | int i = 0; |
438 | ||
285f2dda | 439 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 440 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
441 | |
442 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; | |
443 | ath_cabq_update(sc); | |
444 | ||
60f2d1d5 | 445 | for (i = 0; i < WME_NUM_AC; i++) { |
066dae93 | 446 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); |
60f2d1d5 BG |
447 | sc->tx.txq_map[i]->mac80211_qnum = i; |
448 | } | |
285f2dda | 449 | return 0; |
285f2dda S |
450 | } |
451 | ||
f209f529 | 452 | static int ath9k_init_channels_rates(struct ath_softc *sc) |
285f2dda | 453 | { |
f209f529 FF |
454 | void *channels; |
455 | ||
cac4220b FF |
456 | BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + |
457 | ARRAY_SIZE(ath9k_5ghz_chantable) != | |
458 | ATH9K_NUM_CHANNELS); | |
459 | ||
d4659912 | 460 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { |
f209f529 FF |
461 | channels = kmemdup(ath9k_2ghz_chantable, |
462 | sizeof(ath9k_2ghz_chantable), GFP_KERNEL); | |
463 | if (!channels) | |
464 | return -ENOMEM; | |
465 | ||
466 | sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; | |
285f2dda S |
467 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; |
468 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = | |
469 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
470 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; | |
471 | sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = | |
472 | ARRAY_SIZE(ath9k_legacy_rates); | |
55624204 S |
473 | } |
474 | ||
d4659912 | 475 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { |
f209f529 FF |
476 | channels = kmemdup(ath9k_5ghz_chantable, |
477 | sizeof(ath9k_5ghz_chantable), GFP_KERNEL); | |
478 | if (!channels) { | |
479 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) | |
480 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
481 | return -ENOMEM; | |
482 | } | |
483 | ||
484 | sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; | |
285f2dda S |
485 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; |
486 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = | |
487 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
488 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
489 | ath9k_legacy_rates + 4; | |
490 | sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = | |
491 | ARRAY_SIZE(ath9k_legacy_rates) - 4; | |
492 | } | |
f209f529 | 493 | return 0; |
285f2dda | 494 | } |
55624204 | 495 | |
285f2dda S |
496 | static void ath9k_init_misc(struct ath_softc *sc) |
497 | { | |
498 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
499 | int i = 0; | |
285f2dda | 500 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); |
55624204 S |
501 | |
502 | sc->config.txpowlimit = ATH_TXPOWER_MAX; | |
503 | ||
285f2dda | 504 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
55624204 S |
505 | sc->sc_flags |= SC_OP_TXAGGR; |
506 | sc->sc_flags |= SC_OP_RXAGGR; | |
507 | } | |
508 | ||
8fe65368 | 509 | ath9k_hw_set_diversity(sc->sc_ah, true); |
285f2dda | 510 | sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah); |
55624204 | 511 | |
364734fa | 512 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
55624204 | 513 | |
285f2dda | 514 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 515 | |
7545daf4 | 516 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) |
55624204 | 517 | sc->beacon.bslot[i] = NULL; |
102885a5 VT |
518 | |
519 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
520 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
285f2dda | 521 | } |
55624204 | 522 | |
eb93e891 | 523 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, |
285f2dda S |
524 | const struct ath_bus_ops *bus_ops) |
525 | { | |
6fb1b1e1 | 526 | struct ath9k_platform_data *pdata = sc->dev->platform_data; |
285f2dda S |
527 | struct ath_hw *ah = NULL; |
528 | struct ath_common *common; | |
529 | int ret = 0, i; | |
530 | int csz = 0; | |
55624204 | 531 | |
285f2dda S |
532 | ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); |
533 | if (!ah) | |
534 | return -ENOMEM; | |
535 | ||
233536e1 | 536 | ah->hw = sc->hw; |
285f2dda | 537 | ah->hw_version.devid = devid; |
f9f84e96 FF |
538 | ah->reg_ops.read = ath9k_ioread32; |
539 | ah->reg_ops.write = ath9k_iowrite32; | |
845e03c9 | 540 | ah->reg_ops.rmw = ath9k_reg_rmw; |
e8fe7336 | 541 | atomic_set(&ah->intr_ref_cnt, -1); |
285f2dda S |
542 | sc->sc_ah = ah; |
543 | ||
6de66dd9 | 544 | if (!pdata) { |
a05b5d45 | 545 | ah->ah_flags |= AH_USE_EEPROM; |
6de66dd9 FF |
546 | sc->sc_ah->led_pin = -1; |
547 | } else { | |
548 | sc->sc_ah->gpio_mask = pdata->gpio_mask; | |
549 | sc->sc_ah->gpio_val = pdata->gpio_val; | |
550 | sc->sc_ah->led_pin = pdata->led_pin; | |
f2f5f2a1 | 551 | ah->is_clk_25mhz = pdata->is_clk_25mhz; |
3762561a | 552 | ah->get_mac_revision = pdata->get_mac_revision; |
7d95847c | 553 | ah->external_reset = pdata->external_reset; |
6de66dd9 | 554 | } |
a05b5d45 | 555 | |
285f2dda | 556 | common = ath9k_hw_common(ah); |
f9f84e96 | 557 | common->ops = &ah->reg_ops; |
285f2dda S |
558 | common->bus_ops = bus_ops; |
559 | common->ah = ah; | |
560 | common->hw = sc->hw; | |
561 | common->priv = sc; | |
562 | common->debug_mask = ath9k_debug; | |
8f5dcb1c | 563 | common->btcoex_enabled = ath9k_btcoex_enable == 1; |
05c0be2f | 564 | common->disable_ani = false; |
20b25744 | 565 | spin_lock_init(&common->cc_lock); |
285f2dda | 566 | |
285f2dda S |
567 | spin_lock_init(&sc->sc_serial_rw); |
568 | spin_lock_init(&sc->sc_pm_lock); | |
569 | mutex_init(&sc->mutex); | |
7f010c93 BG |
570 | #ifdef CONFIG_ATH9K_DEBUGFS |
571 | spin_lock_init(&sc->nodes_lock); | |
cf3af748 | 572 | spin_lock_init(&sc->debug.samp_lock); |
7f010c93 BG |
573 | INIT_LIST_HEAD(&sc->nodes); |
574 | #endif | |
285f2dda S |
575 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); |
576 | tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, | |
577 | (unsigned long)sc); | |
578 | ||
579 | /* | |
580 | * Cache line size is used to size and align various | |
581 | * structures used to communicate with the hardware. | |
582 | */ | |
583 | ath_read_cachesize(common, &csz); | |
584 | common->cachelsz = csz << 2; /* convert to bytes */ | |
585 | ||
d70357d5 | 586 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 587 | ret = ath9k_hw_init(ah); |
d70357d5 | 588 | if (ret) |
285f2dda | 589 | goto err_hw; |
55624204 | 590 | |
6fb1b1e1 FF |
591 | if (pdata && pdata->macaddr) |
592 | memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); | |
593 | ||
285f2dda S |
594 | ret = ath9k_init_queues(sc); |
595 | if (ret) | |
596 | goto err_queues; | |
597 | ||
598 | ret = ath9k_init_btcoex(sc); | |
599 | if (ret) | |
600 | goto err_btcoex; | |
601 | ||
f209f529 FF |
602 | ret = ath9k_init_channels_rates(sc); |
603 | if (ret) | |
604 | goto err_btcoex; | |
605 | ||
f82b4bde | 606 | ath9k_cmn_init_crypto(sc->sc_ah); |
285f2dda S |
607 | ath9k_init_misc(sc); |
608 | ||
55624204 | 609 | return 0; |
285f2dda S |
610 | |
611 | err_btcoex: | |
55624204 S |
612 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
613 | if (ATH_TXQ_SETUP(sc, i)) | |
614 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda | 615 | err_queues: |
285f2dda S |
616 | ath9k_hw_deinit(ah); |
617 | err_hw: | |
55624204 | 618 | |
285f2dda S |
619 | kfree(ah); |
620 | sc->sc_ah = NULL; | |
621 | ||
622 | return ret; | |
55624204 S |
623 | } |
624 | ||
babcbc29 FF |
625 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
626 | { | |
627 | struct ieee80211_supported_band *sband; | |
628 | struct ieee80211_channel *chan; | |
629 | struct ath_hw *ah = sc->sc_ah; | |
630 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
631 | int i; | |
632 | ||
633 | sband = &sc->sbands[band]; | |
634 | for (i = 0; i < sband->n_channels; i++) { | |
635 | chan = &sband->channels[i]; | |
636 | ah->curchan = &ah->channels[chan->hw_value]; | |
637 | ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20); | |
638 | ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); | |
639 | chan->max_power = reg->max_power_level / 2; | |
640 | } | |
641 | } | |
642 | ||
643 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
644 | { | |
645 | struct ath_hw *ah = sc->sc_ah; | |
646 | struct ath9k_channel *curchan = ah->curchan; | |
647 | ||
648 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
649 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); | |
650 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
651 | ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); | |
652 | ||
653 | ah->curchan = curchan; | |
654 | } | |
655 | ||
285f2dda | 656 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 657 | { |
285f2dda S |
658 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
659 | ||
55624204 S |
660 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
661 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
662 | IEEE80211_HW_SIGNAL_DBM | | |
55624204 S |
663 | IEEE80211_HW_SUPPORTS_PS | |
664 | IEEE80211_HW_PS_NULLFUNC_STACK | | |
05df4986 | 665 | IEEE80211_HW_SPECTRUM_MGMT | |
bd8027a7 | 666 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; |
55624204 | 667 | |
5ffaf8a3 LR |
668 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
669 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
670 | ||
3e6109c5 | 671 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) |
55624204 S |
672 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; |
673 | ||
674 | hw->wiphy->interface_modes = | |
c426ee24 JB |
675 | BIT(NL80211_IFTYPE_P2P_GO) | |
676 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
55624204 | 677 | BIT(NL80211_IFTYPE_AP) | |
e51f3eff | 678 | BIT(NL80211_IFTYPE_WDS) | |
55624204 S |
679 | BIT(NL80211_IFTYPE_STATION) | |
680 | BIT(NL80211_IFTYPE_ADHOC) | | |
681 | BIT(NL80211_IFTYPE_MESH_POINT); | |
682 | ||
008443de LR |
683 | if (AR_SREV_5416(sc->sc_ah)) |
684 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
55624204 | 685 | |
cfdc9a8b JM |
686 | hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; |
687 | ||
55624204 S |
688 | hw->queues = 4; |
689 | hw->max_rates = 4; | |
690 | hw->channel_change_time = 5000; | |
691 | hw->max_listen_interval = 10; | |
65896510 | 692 | hw->max_rate_tries = 10; |
55624204 S |
693 | hw->sta_data_size = sizeof(struct ath_node); |
694 | hw->vif_data_size = sizeof(struct ath_vif); | |
695 | ||
6e5c2b4e | 696 | #ifdef CONFIG_ATH9K_RATE_CONTROL |
55624204 | 697 | hw->rate_control_algorithm = "ath9k_rate_control"; |
6e5c2b4e | 698 | #endif |
55624204 | 699 | |
d4659912 | 700 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
55624204 S |
701 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
702 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
d4659912 | 703 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
55624204 S |
704 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
705 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
285f2dda S |
706 | |
707 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { | |
d4659912 | 708 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
285f2dda | 709 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); |
d4659912 | 710 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
285f2dda S |
711 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); |
712 | } | |
713 | ||
714 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
715 | } |
716 | ||
eb93e891 | 717 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
55624204 S |
718 | const struct ath_bus_ops *bus_ops) |
719 | { | |
720 | struct ieee80211_hw *hw = sc->hw; | |
721 | struct ath_common *common; | |
722 | struct ath_hw *ah; | |
285f2dda | 723 | int error = 0; |
55624204 S |
724 | struct ath_regulatory *reg; |
725 | ||
285f2dda | 726 | /* Bring up device */ |
eb93e891 | 727 | error = ath9k_init_softc(devid, sc, bus_ops); |
55624204 | 728 | if (error != 0) |
285f2dda | 729 | goto error_init; |
55624204 S |
730 | |
731 | ah = sc->sc_ah; | |
732 | common = ath9k_hw_common(ah); | |
285f2dda | 733 | ath9k_set_hw_capab(sc, hw); |
55624204 | 734 | |
285f2dda | 735 | /* Initialize regulatory */ |
55624204 S |
736 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
737 | ath9k_reg_notifier); | |
738 | if (error) | |
285f2dda | 739 | goto error_regd; |
55624204 S |
740 | |
741 | reg = &common->regulatory; | |
742 | ||
285f2dda | 743 | /* Setup TX DMA */ |
55624204 S |
744 | error = ath_tx_init(sc, ATH_TXBUF); |
745 | if (error != 0) | |
285f2dda | 746 | goto error_tx; |
55624204 | 747 | |
285f2dda | 748 | /* Setup RX DMA */ |
55624204 S |
749 | error = ath_rx_init(sc, ATH_RXBUF); |
750 | if (error != 0) | |
285f2dda | 751 | goto error_rx; |
55624204 | 752 | |
babcbc29 FF |
753 | ath9k_init_txpower_limits(sc); |
754 | ||
0cf55c21 FF |
755 | #ifdef CONFIG_MAC80211_LEDS |
756 | /* must be initialized before ieee80211_register_hw */ | |
757 | sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, | |
758 | IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, | |
759 | ARRAY_SIZE(ath9k_tpt_blink)); | |
760 | #endif | |
761 | ||
285f2dda | 762 | /* Register with mac80211 */ |
55624204 | 763 | error = ieee80211_register_hw(hw); |
285f2dda S |
764 | if (error) |
765 | goto error_register; | |
55624204 | 766 | |
eb272441 BG |
767 | error = ath9k_init_debug(ah); |
768 | if (error) { | |
3800276a | 769 | ath_err(common, "Unable to create debugfs files\n"); |
eb272441 BG |
770 | goto error_world; |
771 | } | |
772 | ||
285f2dda | 773 | /* Handle world regulatory */ |
55624204 S |
774 | if (!ath_is_world_regd(reg)) { |
775 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
776 | if (error) | |
285f2dda | 777 | goto error_world; |
55624204 S |
778 | } |
779 | ||
236de514 | 780 | INIT_WORK(&sc->hw_reset_work, ath_reset_work); |
347809fc | 781 | INIT_WORK(&sc->hw_check_work, ath_hw_check); |
9f42c2b6 | 782 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); |
9eab61c2 | 783 | INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); |
9ac58615 | 784 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
55624204 | 785 | |
285f2dda | 786 | ath_init_leds(sc); |
55624204 S |
787 | ath_start_rfkill_poll(sc); |
788 | ||
789 | return 0; | |
790 | ||
285f2dda S |
791 | error_world: |
792 | ieee80211_unregister_hw(hw); | |
793 | error_register: | |
794 | ath_rx_cleanup(sc); | |
795 | error_rx: | |
796 | ath_tx_cleanup(sc); | |
797 | error_tx: | |
798 | /* Nothing */ | |
799 | error_regd: | |
800 | ath9k_deinit_softc(sc); | |
801 | error_init: | |
55624204 S |
802 | return error; |
803 | } | |
804 | ||
805 | /*****************************/ | |
806 | /* De-Initialization */ | |
807 | /*****************************/ | |
808 | ||
285f2dda | 809 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 810 | { |
285f2dda | 811 | int i = 0; |
55624204 | 812 | |
f209f529 FF |
813 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) |
814 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
815 | ||
816 | if (sc->sbands[IEEE80211_BAND_5GHZ].channels) | |
817 | kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels); | |
818 | ||
285f2dda S |
819 | if ((sc->btcoex.no_stomp_timer) && |
820 | sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) | |
821 | ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer); | |
55624204 | 822 | |
285f2dda S |
823 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
824 | if (ATH_TXQ_SETUP(sc, i)) | |
825 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
826 | ||
285f2dda S |
827 | ath9k_hw_deinit(sc->sc_ah); |
828 | ||
736b3a27 S |
829 | kfree(sc->sc_ah); |
830 | sc->sc_ah = NULL; | |
55624204 S |
831 | } |
832 | ||
285f2dda | 833 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
834 | { |
835 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
836 | |
837 | ath9k_ps_wakeup(sc); | |
838 | ||
55624204 | 839 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 840 | ath_deinit_leds(sc); |
55624204 | 841 | |
c7c18060 RM |
842 | ath9k_ps_restore(sc); |
843 | ||
55624204 S |
844 | ieee80211_unregister_hw(hw); |
845 | ath_rx_cleanup(sc); | |
846 | ath_tx_cleanup(sc); | |
285f2dda | 847 | ath9k_deinit_softc(sc); |
55624204 S |
848 | } |
849 | ||
850 | void ath_descdma_cleanup(struct ath_softc *sc, | |
851 | struct ath_descdma *dd, | |
852 | struct list_head *head) | |
853 | { | |
854 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
855 | dd->dd_desc_paddr); | |
856 | ||
857 | INIT_LIST_HEAD(head); | |
858 | kfree(dd->dd_bufptr); | |
859 | memset(dd, 0, sizeof(*dd)); | |
860 | } | |
861 | ||
55624204 S |
862 | /************************/ |
863 | /* Module Hooks */ | |
864 | /************************/ | |
865 | ||
866 | static int __init ath9k_init(void) | |
867 | { | |
868 | int error; | |
869 | ||
870 | /* Register rate control algorithm */ | |
871 | error = ath_rate_control_register(); | |
872 | if (error != 0) { | |
873 | printk(KERN_ERR | |
874 | "ath9k: Unable to register rate control " | |
875 | "algorithm: %d\n", | |
876 | error); | |
877 | goto err_out; | |
878 | } | |
879 | ||
55624204 S |
880 | error = ath_pci_init(); |
881 | if (error < 0) { | |
882 | printk(KERN_ERR | |
883 | "ath9k: No PCI devices found, driver not installed.\n"); | |
884 | error = -ENODEV; | |
eb272441 | 885 | goto err_rate_unregister; |
55624204 S |
886 | } |
887 | ||
888 | error = ath_ahb_init(); | |
889 | if (error < 0) { | |
890 | error = -ENODEV; | |
891 | goto err_pci_exit; | |
892 | } | |
893 | ||
894 | return 0; | |
895 | ||
896 | err_pci_exit: | |
897 | ath_pci_exit(); | |
898 | ||
55624204 S |
899 | err_rate_unregister: |
900 | ath_rate_control_unregister(); | |
901 | err_out: | |
902 | return error; | |
903 | } | |
904 | module_init(ath9k_init); | |
905 | ||
906 | static void __exit ath9k_exit(void) | |
907 | { | |
d584747b | 908 | is_ath9k_unloaded = true; |
55624204 S |
909 | ath_ahb_exit(); |
910 | ath_pci_exit(); | |
55624204 S |
911 | ath_rate_control_unregister(); |
912 | printk(KERN_INFO "%s: Driver unloaded\n", dev_info); | |
913 | } | |
914 | module_exit(ath9k_exit); |