Commit | Line | Data |
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55624204 S |
1 | /* |
2 | * Copyright (c) 2008-2009 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include "ath9k.h" | |
18 | ||
19 | static char *dev_info = "ath9k"; | |
20 | ||
21 | MODULE_AUTHOR("Atheros Communications"); | |
22 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
23 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
24 | MODULE_LICENSE("Dual BSD/GPL"); | |
25 | ||
26 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
27 | module_param_named(debug, ath9k_debug, uint, 0); | |
28 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
29 | ||
30 | int modparam_nohwcrypt; | |
31 | module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); | |
32 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); | |
33 | ||
34 | /* We use the hw_value as an index into our private channel structure */ | |
35 | ||
36 | #define CHAN2G(_freq, _idx) { \ | |
37 | .center_freq = (_freq), \ | |
38 | .hw_value = (_idx), \ | |
39 | .max_power = 20, \ | |
40 | } | |
41 | ||
42 | #define CHAN5G(_freq, _idx) { \ | |
43 | .band = IEEE80211_BAND_5GHZ, \ | |
44 | .center_freq = (_freq), \ | |
45 | .hw_value = (_idx), \ | |
46 | .max_power = 20, \ | |
47 | } | |
48 | ||
49 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
50 | * on 5 MHz steps, we support the channels which we know | |
51 | * we have calibration data for all cards though to make | |
52 | * this static */ | |
53 | static struct ieee80211_channel ath9k_2ghz_chantable[] = { | |
54 | CHAN2G(2412, 0), /* Channel 1 */ | |
55 | CHAN2G(2417, 1), /* Channel 2 */ | |
56 | CHAN2G(2422, 2), /* Channel 3 */ | |
57 | CHAN2G(2427, 3), /* Channel 4 */ | |
58 | CHAN2G(2432, 4), /* Channel 5 */ | |
59 | CHAN2G(2437, 5), /* Channel 6 */ | |
60 | CHAN2G(2442, 6), /* Channel 7 */ | |
61 | CHAN2G(2447, 7), /* Channel 8 */ | |
62 | CHAN2G(2452, 8), /* Channel 9 */ | |
63 | CHAN2G(2457, 9), /* Channel 10 */ | |
64 | CHAN2G(2462, 10), /* Channel 11 */ | |
65 | CHAN2G(2467, 11), /* Channel 12 */ | |
66 | CHAN2G(2472, 12), /* Channel 13 */ | |
67 | CHAN2G(2484, 13), /* Channel 14 */ | |
68 | }; | |
69 | ||
70 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
71 | * on 5 MHz steps, we support the channels which we know | |
72 | * we have calibration data for all cards though to make | |
73 | * this static */ | |
74 | static struct ieee80211_channel ath9k_5ghz_chantable[] = { | |
75 | /* _We_ call this UNII 1 */ | |
76 | CHAN5G(5180, 14), /* Channel 36 */ | |
77 | CHAN5G(5200, 15), /* Channel 40 */ | |
78 | CHAN5G(5220, 16), /* Channel 44 */ | |
79 | CHAN5G(5240, 17), /* Channel 48 */ | |
80 | /* _We_ call this UNII 2 */ | |
81 | CHAN5G(5260, 18), /* Channel 52 */ | |
82 | CHAN5G(5280, 19), /* Channel 56 */ | |
83 | CHAN5G(5300, 20), /* Channel 60 */ | |
84 | CHAN5G(5320, 21), /* Channel 64 */ | |
85 | /* _We_ call this "Middle band" */ | |
86 | CHAN5G(5500, 22), /* Channel 100 */ | |
87 | CHAN5G(5520, 23), /* Channel 104 */ | |
88 | CHAN5G(5540, 24), /* Channel 108 */ | |
89 | CHAN5G(5560, 25), /* Channel 112 */ | |
90 | CHAN5G(5580, 26), /* Channel 116 */ | |
91 | CHAN5G(5600, 27), /* Channel 120 */ | |
92 | CHAN5G(5620, 28), /* Channel 124 */ | |
93 | CHAN5G(5640, 29), /* Channel 128 */ | |
94 | CHAN5G(5660, 30), /* Channel 132 */ | |
95 | CHAN5G(5680, 31), /* Channel 136 */ | |
96 | CHAN5G(5700, 32), /* Channel 140 */ | |
97 | /* _We_ call this UNII 3 */ | |
98 | CHAN5G(5745, 33), /* Channel 149 */ | |
99 | CHAN5G(5765, 34), /* Channel 153 */ | |
100 | CHAN5G(5785, 35), /* Channel 157 */ | |
101 | CHAN5G(5805, 36), /* Channel 161 */ | |
102 | CHAN5G(5825, 37), /* Channel 165 */ | |
103 | }; | |
104 | ||
105 | /* Atheros hardware rate code addition for short premble */ | |
106 | #define SHPCHECK(__hw_rate, __flags) \ | |
107 | ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) | |
108 | ||
109 | #define RATE(_bitrate, _hw_rate, _flags) { \ | |
110 | .bitrate = (_bitrate), \ | |
111 | .flags = (_flags), \ | |
112 | .hw_value = (_hw_rate), \ | |
113 | .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ | |
114 | } | |
115 | ||
116 | static struct ieee80211_rate ath9k_legacy_rates[] = { | |
117 | RATE(10, 0x1b, 0), | |
118 | RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), | |
119 | RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), | |
120 | RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), | |
121 | RATE(60, 0x0b, 0), | |
122 | RATE(90, 0x0f, 0), | |
123 | RATE(120, 0x0a, 0), | |
124 | RATE(180, 0x0e, 0), | |
125 | RATE(240, 0x09, 0), | |
126 | RATE(360, 0x0d, 0), | |
127 | RATE(480, 0x08, 0), | |
128 | RATE(540, 0x0c, 0), | |
129 | }; | |
130 | ||
285f2dda | 131 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 S |
132 | |
133 | /* | |
134 | * Read and write, they both share the same lock. We do this to serialize | |
135 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
136 | * as the FIFO on these devices can only accept sanely 2 requests. | |
137 | */ | |
138 | ||
139 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
140 | { | |
141 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
142 | struct ath_common *common = ath9k_hw_common(ah); | |
143 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
144 | ||
145 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
146 | unsigned long flags; | |
147 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
148 | iowrite32(val, sc->mem + reg_offset); | |
149 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
150 | } else | |
151 | iowrite32(val, sc->mem + reg_offset); | |
152 | } | |
153 | ||
154 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
155 | { | |
156 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
157 | struct ath_common *common = ath9k_hw_common(ah); | |
158 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
159 | u32 val; | |
160 | ||
161 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
162 | unsigned long flags; | |
163 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
164 | val = ioread32(sc->mem + reg_offset); | |
165 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
166 | } else | |
167 | val = ioread32(sc->mem + reg_offset); | |
168 | return val; | |
169 | } | |
170 | ||
171 | static const struct ath_ops ath9k_common_ops = { | |
172 | .read = ath9k_ioread32, | |
173 | .write = ath9k_iowrite32, | |
174 | }; | |
175 | ||
176 | /**************************/ | |
177 | /* Initialization */ | |
178 | /**************************/ | |
179 | ||
180 | static void setup_ht_cap(struct ath_softc *sc, | |
181 | struct ieee80211_sta_ht_cap *ht_info) | |
182 | { | |
183 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
184 | u8 tx_streams, rx_streams; | |
185 | ||
186 | ht_info->ht_supported = true; | |
187 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
188 | IEEE80211_HT_CAP_SM_PS | | |
189 | IEEE80211_HT_CAP_SGI_40 | | |
190 | IEEE80211_HT_CAP_DSSSCCK40; | |
191 | ||
192 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; | |
193 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
194 | ||
195 | /* set up supported mcs set */ | |
196 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
197 | tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ? | |
198 | 1 : 2; | |
199 | rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ? | |
200 | 1 : 2; | |
201 | ||
202 | if (tx_streams != rx_streams) { | |
203 | ath_print(common, ATH_DBG_CONFIG, | |
204 | "TX streams %d, RX streams: %d\n", | |
205 | tx_streams, rx_streams); | |
206 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; | |
207 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
208 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
209 | } | |
210 | ||
211 | ht_info->mcs.rx_mask[0] = 0xff; | |
212 | if (rx_streams >= 2) | |
213 | ht_info->mcs.rx_mask[1] = 0xff; | |
214 | ||
215 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; | |
216 | } | |
217 | ||
218 | static int ath9k_reg_notifier(struct wiphy *wiphy, | |
219 | struct regulatory_request *request) | |
220 | { | |
221 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
222 | struct ath_wiphy *aphy = hw->priv; | |
223 | struct ath_softc *sc = aphy->sc; | |
224 | struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah); | |
225 | ||
226 | return ath_reg_notifier_apply(wiphy, request, reg); | |
227 | } | |
228 | ||
229 | /* | |
230 | * This function will allocate both the DMA descriptor structure, and the | |
231 | * buffers it contains. These are used to contain the descriptors used | |
232 | * by the system. | |
233 | */ | |
234 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
235 | struct list_head *head, const char *name, | |
4adfcded | 236 | int nbuf, int ndesc, bool is_tx) |
55624204 S |
237 | { |
238 | #define DS2PHYS(_dd, _ds) \ | |
239 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
240 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
241 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
242 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
4adfcded | 243 | u8 *ds; |
55624204 | 244 | struct ath_buf *bf; |
4adfcded | 245 | int i, bsize, error, desc_len; |
55624204 S |
246 | |
247 | ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", | |
248 | name, nbuf, ndesc); | |
249 | ||
250 | INIT_LIST_HEAD(head); | |
4adfcded VT |
251 | |
252 | if (is_tx) | |
253 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
254 | else | |
255 | desc_len = sizeof(struct ath_desc); | |
256 | ||
55624204 | 257 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 258 | if ((desc_len % 4) != 0) { |
55624204 S |
259 | ath_print(common, ATH_DBG_FATAL, |
260 | "ath_desc not DWORD aligned\n"); | |
4adfcded | 261 | BUG_ON((desc_len % 4) != 0); |
55624204 S |
262 | error = -ENOMEM; |
263 | goto fail; | |
264 | } | |
265 | ||
4adfcded | 266 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
267 | |
268 | /* | |
269 | * Need additional DMA memory because we can't use | |
270 | * descriptors that cross the 4K page boundary. Assume | |
271 | * one skipped descriptor per 4K page. | |
272 | */ | |
273 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
274 | u32 ndesc_skipped = | |
275 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
276 | u32 dma_len; | |
277 | ||
278 | while (ndesc_skipped) { | |
4adfcded | 279 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
280 | dd->dd_desc_len += dma_len; |
281 | ||
282 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
283 | }; | |
284 | } | |
285 | ||
286 | /* allocate descriptors */ | |
287 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, | |
288 | &dd->dd_desc_paddr, GFP_KERNEL); | |
289 | if (dd->dd_desc == NULL) { | |
290 | error = -ENOMEM; | |
291 | goto fail; | |
292 | } | |
4adfcded | 293 | ds = (u8 *) dd->dd_desc; |
55624204 S |
294 | ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
295 | name, ds, (u32) dd->dd_desc_len, | |
296 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
297 | ||
298 | /* allocate buffers */ | |
299 | bsize = sizeof(struct ath_buf) * nbuf; | |
300 | bf = kzalloc(bsize, GFP_KERNEL); | |
301 | if (bf == NULL) { | |
302 | error = -ENOMEM; | |
303 | goto fail2; | |
304 | } | |
305 | dd->dd_bufptr = bf; | |
306 | ||
4adfcded | 307 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { |
55624204 S |
308 | bf->bf_desc = ds; |
309 | bf->bf_daddr = DS2PHYS(dd, ds); | |
310 | ||
311 | if (!(sc->sc_ah->caps.hw_caps & | |
312 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
313 | /* | |
314 | * Skip descriptor addresses which can cause 4KB | |
315 | * boundary crossing (addr + length) with a 32 dword | |
316 | * descriptor fetch. | |
317 | */ | |
318 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
319 | BUG_ON((caddr_t) bf->bf_desc >= | |
320 | ((caddr_t) dd->dd_desc + | |
321 | dd->dd_desc_len)); | |
322 | ||
4adfcded | 323 | ds += (desc_len * ndesc); |
55624204 S |
324 | bf->bf_desc = ds; |
325 | bf->bf_daddr = DS2PHYS(dd, ds); | |
326 | } | |
327 | } | |
328 | list_add_tail(&bf->list, head); | |
329 | } | |
330 | return 0; | |
331 | fail2: | |
332 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
333 | dd->dd_desc_paddr); | |
334 | fail: | |
335 | memset(dd, 0, sizeof(*dd)); | |
336 | return error; | |
337 | #undef ATH_DESC_4KB_BOUND_CHECK | |
338 | #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED | |
339 | #undef DS2PHYS | |
340 | } | |
341 | ||
285f2dda | 342 | static void ath9k_init_crypto(struct ath_softc *sc) |
55624204 | 343 | { |
285f2dda S |
344 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
345 | int i = 0; | |
55624204 S |
346 | |
347 | /* Get the hardware key cache size. */ | |
285f2dda | 348 | common->keymax = sc->sc_ah->caps.keycache_size; |
55624204 S |
349 | if (common->keymax > ATH_KEYMAX) { |
350 | ath_print(common, ATH_DBG_ANY, | |
351 | "Warning, using only %u entries in %u key cache\n", | |
352 | ATH_KEYMAX, common->keymax); | |
353 | common->keymax = ATH_KEYMAX; | |
354 | } | |
355 | ||
356 | /* | |
357 | * Reset the key cache since some parts do not | |
358 | * reset the contents on initial power up. | |
359 | */ | |
360 | for (i = 0; i < common->keymax; i++) | |
285f2dda | 361 | ath9k_hw_keyreset(sc->sc_ah, (u16) i); |
55624204 | 362 | |
285f2dda S |
363 | if (ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER, |
364 | ATH9K_CIPHER_TKIP, NULL)) { | |
365 | /* | |
366 | * Whether we should enable h/w TKIP MIC. | |
367 | * XXX: if we don't support WME TKIP MIC, then we wouldn't | |
368 | * report WMM capable, so it's always safe to turn on | |
369 | * TKIP MIC in this case. | |
370 | */ | |
371 | ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC, 0, 1, NULL); | |
372 | } | |
55624204 S |
373 | |
374 | /* | |
285f2dda S |
375 | * Check whether the separate key cache entries |
376 | * are required to handle both tx+rx MIC keys. | |
377 | * With split mic keys the number of stations is limited | |
378 | * to 27 otherwise 59. | |
55624204 | 379 | */ |
285f2dda S |
380 | if (ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER, |
381 | ATH9K_CIPHER_TKIP, NULL) | |
382 | && ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER, | |
383 | ATH9K_CIPHER_MIC, NULL) | |
384 | && ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_TKIP_SPLIT, | |
385 | 0, NULL)) | |
386 | common->splitmic = 1; | |
387 | ||
388 | /* turn on mcast key search if possible */ | |
389 | if (!ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL)) | |
390 | (void)ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH, | |
391 | 1, 1, NULL); | |
392 | ||
393 | } | |
394 | ||
395 | static int ath9k_init_btcoex(struct ath_softc *sc) | |
396 | { | |
397 | int r, qnum; | |
398 | ||
399 | switch (sc->sc_ah->btcoex_hw.scheme) { | |
400 | case ATH_BTCOEX_CFG_NONE: | |
401 | break; | |
402 | case ATH_BTCOEX_CFG_2WIRE: | |
403 | ath9k_hw_btcoex_init_2wire(sc->sc_ah); | |
404 | break; | |
405 | case ATH_BTCOEX_CFG_3WIRE: | |
406 | ath9k_hw_btcoex_init_3wire(sc->sc_ah); | |
407 | r = ath_init_btcoex_timer(sc); | |
408 | if (r) | |
409 | return -1; | |
410 | qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
411 | ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum); | |
412 | sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; | |
413 | break; | |
414 | default: | |
415 | WARN_ON(1); | |
416 | break; | |
417 | } | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
422 | static int ath9k_init_queues(struct ath_softc *sc) | |
423 | { | |
424 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
425 | int i = 0; | |
426 | ||
427 | for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++) | |
428 | sc->tx.hwq_map[i] = -1; | |
429 | ||
430 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); | |
55624204 S |
431 | if (sc->beacon.beaconq == -1) { |
432 | ath_print(common, ATH_DBG_FATAL, | |
433 | "Unable to setup a beacon xmit queue\n"); | |
285f2dda | 434 | goto err; |
55624204 | 435 | } |
285f2dda | 436 | |
55624204 S |
437 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
438 | if (sc->beacon.cabq == NULL) { | |
439 | ath_print(common, ATH_DBG_FATAL, | |
440 | "Unable to setup CAB xmit queue\n"); | |
285f2dda | 441 | goto err; |
55624204 S |
442 | } |
443 | ||
444 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; | |
445 | ath_cabq_update(sc); | |
446 | ||
55624204 S |
447 | if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) { |
448 | ath_print(common, ATH_DBG_FATAL, | |
449 | "Unable to setup xmit queue for BK traffic\n"); | |
285f2dda | 450 | goto err; |
55624204 S |
451 | } |
452 | ||
453 | if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) { | |
454 | ath_print(common, ATH_DBG_FATAL, | |
455 | "Unable to setup xmit queue for BE traffic\n"); | |
285f2dda | 456 | goto err; |
55624204 S |
457 | } |
458 | if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) { | |
459 | ath_print(common, ATH_DBG_FATAL, | |
460 | "Unable to setup xmit queue for VI traffic\n"); | |
285f2dda | 461 | goto err; |
55624204 S |
462 | } |
463 | if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) { | |
464 | ath_print(common, ATH_DBG_FATAL, | |
465 | "Unable to setup xmit queue for VO traffic\n"); | |
285f2dda | 466 | goto err; |
55624204 S |
467 | } |
468 | ||
285f2dda | 469 | return 0; |
55624204 | 470 | |
285f2dda S |
471 | err: |
472 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
473 | if (ATH_TXQ_SETUP(sc, i)) | |
474 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
55624204 | 475 | |
285f2dda S |
476 | return -EIO; |
477 | } | |
478 | ||
479 | static void ath9k_init_channels_rates(struct ath_softc *sc) | |
480 | { | |
481 | if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) { | |
482 | sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable; | |
483 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; | |
484 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = | |
485 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
486 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; | |
487 | sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = | |
488 | ARRAY_SIZE(ath9k_legacy_rates); | |
55624204 S |
489 | } |
490 | ||
285f2dda S |
491 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) { |
492 | sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable; | |
493 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; | |
494 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = | |
495 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
496 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
497 | ath9k_legacy_rates + 4; | |
498 | sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = | |
499 | ARRAY_SIZE(ath9k_legacy_rates) - 4; | |
500 | } | |
501 | } | |
55624204 | 502 | |
285f2dda S |
503 | static void ath9k_init_misc(struct ath_softc *sc) |
504 | { | |
505 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
506 | int i = 0; | |
507 | ||
508 | common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR; | |
509 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); | |
55624204 S |
510 | |
511 | sc->config.txpowlimit = ATH_TXPOWER_MAX; | |
512 | ||
285f2dda | 513 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
55624204 S |
514 | sc->sc_flags |= SC_OP_TXAGGR; |
515 | sc->sc_flags |= SC_OP_RXAGGR; | |
516 | } | |
517 | ||
285f2dda S |
518 | common->tx_chainmask = sc->sc_ah->caps.tx_chainmask; |
519 | common->rx_chainmask = sc->sc_ah->caps.rx_chainmask; | |
55624204 | 520 | |
8fe65368 | 521 | ath9k_hw_set_diversity(sc->sc_ah, true); |
285f2dda | 522 | sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah); |
55624204 | 523 | |
285f2dda | 524 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
55624204 S |
525 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
526 | ||
285f2dda | 527 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 528 | |
55624204 S |
529 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
530 | sc->beacon.bslot[i] = NULL; | |
531 | sc->beacon.bslot_aphy[i] = NULL; | |
532 | } | |
285f2dda | 533 | } |
55624204 | 534 | |
285f2dda S |
535 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid, |
536 | const struct ath_bus_ops *bus_ops) | |
537 | { | |
538 | struct ath_hw *ah = NULL; | |
539 | struct ath_common *common; | |
540 | int ret = 0, i; | |
541 | int csz = 0; | |
55624204 | 542 | |
285f2dda S |
543 | ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); |
544 | if (!ah) | |
545 | return -ENOMEM; | |
546 | ||
547 | ah->hw_version.devid = devid; | |
548 | ah->hw_version.subsysid = subsysid; | |
549 | sc->sc_ah = ah; | |
550 | ||
551 | common = ath9k_hw_common(ah); | |
552 | common->ops = &ath9k_common_ops; | |
553 | common->bus_ops = bus_ops; | |
554 | common->ah = ah; | |
555 | common->hw = sc->hw; | |
556 | common->priv = sc; | |
557 | common->debug_mask = ath9k_debug; | |
558 | ||
559 | spin_lock_init(&sc->wiphy_lock); | |
560 | spin_lock_init(&sc->sc_resetlock); | |
561 | spin_lock_init(&sc->sc_serial_rw); | |
562 | spin_lock_init(&sc->sc_pm_lock); | |
563 | mutex_init(&sc->mutex); | |
564 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); | |
565 | tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, | |
566 | (unsigned long)sc); | |
567 | ||
568 | /* | |
569 | * Cache line size is used to size and align various | |
570 | * structures used to communicate with the hardware. | |
571 | */ | |
572 | ath_read_cachesize(common, &csz); | |
573 | common->cachelsz = csz << 2; /* convert to bytes */ | |
574 | ||
d70357d5 | 575 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 576 | ret = ath9k_hw_init(ah); |
d70357d5 | 577 | if (ret) |
285f2dda | 578 | goto err_hw; |
55624204 | 579 | |
285f2dda S |
580 | ret = ath9k_init_debug(ah); |
581 | if (ret) { | |
582 | ath_print(common, ATH_DBG_FATAL, | |
583 | "Unable to create debugfs files\n"); | |
584 | goto err_debug; | |
55624204 S |
585 | } |
586 | ||
285f2dda S |
587 | ret = ath9k_init_queues(sc); |
588 | if (ret) | |
589 | goto err_queues; | |
590 | ||
591 | ret = ath9k_init_btcoex(sc); | |
592 | if (ret) | |
593 | goto err_btcoex; | |
594 | ||
595 | ath9k_init_crypto(sc); | |
596 | ath9k_init_channels_rates(sc); | |
597 | ath9k_init_misc(sc); | |
598 | ||
55624204 | 599 | return 0; |
285f2dda S |
600 | |
601 | err_btcoex: | |
55624204 S |
602 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
603 | if (ATH_TXQ_SETUP(sc, i)) | |
604 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda S |
605 | err_queues: |
606 | ath9k_exit_debug(ah); | |
607 | err_debug: | |
608 | ath9k_hw_deinit(ah); | |
609 | err_hw: | |
610 | tasklet_kill(&sc->intr_tq); | |
611 | tasklet_kill(&sc->bcon_tasklet); | |
55624204 | 612 | |
285f2dda S |
613 | kfree(ah); |
614 | sc->sc_ah = NULL; | |
615 | ||
616 | return ret; | |
55624204 S |
617 | } |
618 | ||
285f2dda | 619 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 620 | { |
285f2dda S |
621 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
622 | ||
55624204 S |
623 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
624 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
625 | IEEE80211_HW_SIGNAL_DBM | | |
55624204 S |
626 | IEEE80211_HW_SUPPORTS_PS | |
627 | IEEE80211_HW_PS_NULLFUNC_STACK | | |
05df4986 VN |
628 | IEEE80211_HW_SPECTRUM_MGMT | |
629 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; | |
55624204 | 630 | |
5ffaf8a3 LR |
631 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
632 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
633 | ||
55624204 S |
634 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt) |
635 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; | |
636 | ||
637 | hw->wiphy->interface_modes = | |
638 | BIT(NL80211_IFTYPE_AP) | | |
639 | BIT(NL80211_IFTYPE_STATION) | | |
640 | BIT(NL80211_IFTYPE_ADHOC) | | |
641 | BIT(NL80211_IFTYPE_MESH_POINT); | |
642 | ||
643 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
644 | ||
645 | hw->queues = 4; | |
646 | hw->max_rates = 4; | |
647 | hw->channel_change_time = 5000; | |
648 | hw->max_listen_interval = 10; | |
65896510 | 649 | hw->max_rate_tries = 10; |
55624204 S |
650 | hw->sta_data_size = sizeof(struct ath_node); |
651 | hw->vif_data_size = sizeof(struct ath_vif); | |
652 | ||
653 | hw->rate_control_algorithm = "ath9k_rate_control"; | |
654 | ||
655 | if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) | |
656 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
657 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
658 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) | |
659 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
660 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
285f2dda S |
661 | |
662 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { | |
663 | if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) | |
664 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); | |
665 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) | |
666 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); | |
667 | } | |
668 | ||
669 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
670 | } |
671 | ||
285f2dda | 672 | int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, |
55624204 S |
673 | const struct ath_bus_ops *bus_ops) |
674 | { | |
675 | struct ieee80211_hw *hw = sc->hw; | |
676 | struct ath_common *common; | |
677 | struct ath_hw *ah; | |
285f2dda | 678 | int error = 0; |
55624204 S |
679 | struct ath_regulatory *reg; |
680 | ||
285f2dda S |
681 | /* Bring up device */ |
682 | error = ath9k_init_softc(devid, sc, subsysid, bus_ops); | |
55624204 | 683 | if (error != 0) |
285f2dda | 684 | goto error_init; |
55624204 S |
685 | |
686 | ah = sc->sc_ah; | |
687 | common = ath9k_hw_common(ah); | |
285f2dda | 688 | ath9k_set_hw_capab(sc, hw); |
55624204 | 689 | |
285f2dda | 690 | /* Initialize regulatory */ |
55624204 S |
691 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
692 | ath9k_reg_notifier); | |
693 | if (error) | |
285f2dda | 694 | goto error_regd; |
55624204 S |
695 | |
696 | reg = &common->regulatory; | |
697 | ||
285f2dda | 698 | /* Setup TX DMA */ |
55624204 S |
699 | error = ath_tx_init(sc, ATH_TXBUF); |
700 | if (error != 0) | |
285f2dda | 701 | goto error_tx; |
55624204 | 702 | |
285f2dda | 703 | /* Setup RX DMA */ |
55624204 S |
704 | error = ath_rx_init(sc, ATH_RXBUF); |
705 | if (error != 0) | |
285f2dda | 706 | goto error_rx; |
55624204 | 707 | |
285f2dda | 708 | /* Register with mac80211 */ |
55624204 | 709 | error = ieee80211_register_hw(hw); |
285f2dda S |
710 | if (error) |
711 | goto error_register; | |
55624204 | 712 | |
285f2dda | 713 | /* Handle world regulatory */ |
55624204 S |
714 | if (!ath_is_world_regd(reg)) { |
715 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
716 | if (error) | |
285f2dda | 717 | goto error_world; |
55624204 S |
718 | } |
719 | ||
285f2dda S |
720 | INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work); |
721 | INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work); | |
722 | sc->wiphy_scheduler_int = msecs_to_jiffies(500); | |
55624204 | 723 | |
285f2dda | 724 | ath_init_leds(sc); |
55624204 S |
725 | ath_start_rfkill_poll(sc); |
726 | ||
727 | return 0; | |
728 | ||
285f2dda S |
729 | error_world: |
730 | ieee80211_unregister_hw(hw); | |
731 | error_register: | |
732 | ath_rx_cleanup(sc); | |
733 | error_rx: | |
734 | ath_tx_cleanup(sc); | |
735 | error_tx: | |
736 | /* Nothing */ | |
737 | error_regd: | |
738 | ath9k_deinit_softc(sc); | |
739 | error_init: | |
55624204 S |
740 | return error; |
741 | } | |
742 | ||
743 | /*****************************/ | |
744 | /* De-Initialization */ | |
745 | /*****************************/ | |
746 | ||
285f2dda | 747 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 748 | { |
285f2dda | 749 | int i = 0; |
55624204 | 750 | |
285f2dda S |
751 | if ((sc->btcoex.no_stomp_timer) && |
752 | sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) | |
753 | ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer); | |
55624204 | 754 | |
285f2dda S |
755 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
756 | if (ATH_TXQ_SETUP(sc, i)) | |
757 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
758 | ||
759 | ath9k_exit_debug(sc->sc_ah); | |
760 | ath9k_hw_deinit(sc->sc_ah); | |
761 | ||
762 | tasklet_kill(&sc->intr_tq); | |
763 | tasklet_kill(&sc->bcon_tasklet); | |
736b3a27 S |
764 | |
765 | kfree(sc->sc_ah); | |
766 | sc->sc_ah = NULL; | |
55624204 S |
767 | } |
768 | ||
285f2dda | 769 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
770 | { |
771 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
772 | int i = 0; |
773 | ||
774 | ath9k_ps_wakeup(sc); | |
775 | ||
55624204 | 776 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 777 | ath_deinit_leds(sc); |
55624204 S |
778 | |
779 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
780 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
781 | if (aphy == NULL) | |
782 | continue; | |
783 | sc->sec_wiphy[i] = NULL; | |
784 | ieee80211_unregister_hw(aphy->hw); | |
785 | ieee80211_free_hw(aphy->hw); | |
786 | } | |
285f2dda S |
787 | kfree(sc->sec_wiphy); |
788 | ||
55624204 S |
789 | ieee80211_unregister_hw(hw); |
790 | ath_rx_cleanup(sc); | |
791 | ath_tx_cleanup(sc); | |
285f2dda | 792 | ath9k_deinit_softc(sc); |
55624204 S |
793 | } |
794 | ||
795 | void ath_descdma_cleanup(struct ath_softc *sc, | |
796 | struct ath_descdma *dd, | |
797 | struct list_head *head) | |
798 | { | |
799 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
800 | dd->dd_desc_paddr); | |
801 | ||
802 | INIT_LIST_HEAD(head); | |
803 | kfree(dd->dd_bufptr); | |
804 | memset(dd, 0, sizeof(*dd)); | |
805 | } | |
806 | ||
55624204 S |
807 | /************************/ |
808 | /* Module Hooks */ | |
809 | /************************/ | |
810 | ||
811 | static int __init ath9k_init(void) | |
812 | { | |
813 | int error; | |
814 | ||
815 | /* Register rate control algorithm */ | |
816 | error = ath_rate_control_register(); | |
817 | if (error != 0) { | |
818 | printk(KERN_ERR | |
819 | "ath9k: Unable to register rate control " | |
820 | "algorithm: %d\n", | |
821 | error); | |
822 | goto err_out; | |
823 | } | |
824 | ||
825 | error = ath9k_debug_create_root(); | |
826 | if (error) { | |
827 | printk(KERN_ERR | |
828 | "ath9k: Unable to create debugfs root: %d\n", | |
829 | error); | |
830 | goto err_rate_unregister; | |
831 | } | |
832 | ||
833 | error = ath_pci_init(); | |
834 | if (error < 0) { | |
835 | printk(KERN_ERR | |
836 | "ath9k: No PCI devices found, driver not installed.\n"); | |
837 | error = -ENODEV; | |
838 | goto err_remove_root; | |
839 | } | |
840 | ||
841 | error = ath_ahb_init(); | |
842 | if (error < 0) { | |
843 | error = -ENODEV; | |
844 | goto err_pci_exit; | |
845 | } | |
846 | ||
847 | return 0; | |
848 | ||
849 | err_pci_exit: | |
850 | ath_pci_exit(); | |
851 | ||
852 | err_remove_root: | |
853 | ath9k_debug_remove_root(); | |
854 | err_rate_unregister: | |
855 | ath_rate_control_unregister(); | |
856 | err_out: | |
857 | return error; | |
858 | } | |
859 | module_init(ath9k_init); | |
860 | ||
861 | static void __exit ath9k_exit(void) | |
862 | { | |
863 | ath_ahb_exit(); | |
864 | ath_pci_exit(); | |
865 | ath9k_debug_remove_root(); | |
866 | ath_rate_control_unregister(); | |
867 | printk(KERN_INFO "%s: Driver unloaded\n", dev_info); | |
868 | } | |
869 | module_exit(ath9k_exit); |