Commit | Line | Data |
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55624204 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
55624204 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
516304b0 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
b7f080cf | 19 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
6fb1b1e1 | 21 | #include <linux/ath9k_platform.h> |
9d9779e7 | 22 | #include <linux/module.h> |
e93d083f | 23 | #include <linux/relay.h> |
b0a1ae97 | 24 | #include <net/ieee80211_radiotap.h> |
5a0e3ad6 | 25 | |
55624204 S |
26 | #include "ath9k.h" |
27 | ||
ab5c4f71 GJ |
28 | struct ath9k_eeprom_ctx { |
29 | struct completion complete; | |
30 | struct ath_hw *ah; | |
31 | }; | |
32 | ||
55624204 S |
33 | static char *dev_info = "ath9k"; |
34 | ||
35 | MODULE_AUTHOR("Atheros Communications"); | |
36 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
37 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
38 | MODULE_LICENSE("Dual BSD/GPL"); | |
39 | ||
40 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
41 | module_param_named(debug, ath9k_debug, uint, 0); | |
42 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
43 | ||
3e6109c5 JL |
44 | int ath9k_modparam_nohwcrypt; |
45 | module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); | |
55624204 S |
46 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); |
47 | ||
93dbbcc4 | 48 | int led_blink; |
9a75c2ff VN |
49 | module_param_named(blink, led_blink, int, 0444); |
50 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); | |
51 | ||
8f5dcb1c VT |
52 | static int ath9k_btcoex_enable; |
53 | module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); | |
54 | MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); | |
55 | ||
e09f2dc7 SM |
56 | static int ath9k_enable_diversity; |
57 | module_param_named(enable_diversity, ath9k_enable_diversity, int, 0444); | |
58 | MODULE_PARM_DESC(enable_diversity, "Enable Antenna diversity for AR9565"); | |
59 | ||
d584747b | 60 | bool is_ath9k_unloaded; |
55624204 S |
61 | /* We use the hw_value as an index into our private channel structure */ |
62 | ||
63 | #define CHAN2G(_freq, _idx) { \ | |
b1c1d000 | 64 | .band = IEEE80211_BAND_2GHZ, \ |
55624204 S |
65 | .center_freq = (_freq), \ |
66 | .hw_value = (_idx), \ | |
67 | .max_power = 20, \ | |
68 | } | |
69 | ||
70 | #define CHAN5G(_freq, _idx) { \ | |
71 | .band = IEEE80211_BAND_5GHZ, \ | |
72 | .center_freq = (_freq), \ | |
73 | .hw_value = (_idx), \ | |
74 | .max_power = 20, \ | |
75 | } | |
76 | ||
77 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
78 | * on 5 MHz steps, we support the channels which we know | |
79 | * we have calibration data for all cards though to make | |
80 | * this static */ | |
f209f529 | 81 | static const struct ieee80211_channel ath9k_2ghz_chantable[] = { |
55624204 S |
82 | CHAN2G(2412, 0), /* Channel 1 */ |
83 | CHAN2G(2417, 1), /* Channel 2 */ | |
84 | CHAN2G(2422, 2), /* Channel 3 */ | |
85 | CHAN2G(2427, 3), /* Channel 4 */ | |
86 | CHAN2G(2432, 4), /* Channel 5 */ | |
87 | CHAN2G(2437, 5), /* Channel 6 */ | |
88 | CHAN2G(2442, 6), /* Channel 7 */ | |
89 | CHAN2G(2447, 7), /* Channel 8 */ | |
90 | CHAN2G(2452, 8), /* Channel 9 */ | |
91 | CHAN2G(2457, 9), /* Channel 10 */ | |
92 | CHAN2G(2462, 10), /* Channel 11 */ | |
93 | CHAN2G(2467, 11), /* Channel 12 */ | |
94 | CHAN2G(2472, 12), /* Channel 13 */ | |
95 | CHAN2G(2484, 13), /* Channel 14 */ | |
96 | }; | |
97 | ||
98 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
99 | * on 5 MHz steps, we support the channels which we know | |
100 | * we have calibration data for all cards though to make | |
101 | * this static */ | |
f209f529 | 102 | static const struct ieee80211_channel ath9k_5ghz_chantable[] = { |
55624204 S |
103 | /* _We_ call this UNII 1 */ |
104 | CHAN5G(5180, 14), /* Channel 36 */ | |
105 | CHAN5G(5200, 15), /* Channel 40 */ | |
106 | CHAN5G(5220, 16), /* Channel 44 */ | |
107 | CHAN5G(5240, 17), /* Channel 48 */ | |
108 | /* _We_ call this UNII 2 */ | |
109 | CHAN5G(5260, 18), /* Channel 52 */ | |
110 | CHAN5G(5280, 19), /* Channel 56 */ | |
111 | CHAN5G(5300, 20), /* Channel 60 */ | |
112 | CHAN5G(5320, 21), /* Channel 64 */ | |
113 | /* _We_ call this "Middle band" */ | |
114 | CHAN5G(5500, 22), /* Channel 100 */ | |
115 | CHAN5G(5520, 23), /* Channel 104 */ | |
116 | CHAN5G(5540, 24), /* Channel 108 */ | |
117 | CHAN5G(5560, 25), /* Channel 112 */ | |
118 | CHAN5G(5580, 26), /* Channel 116 */ | |
119 | CHAN5G(5600, 27), /* Channel 120 */ | |
120 | CHAN5G(5620, 28), /* Channel 124 */ | |
121 | CHAN5G(5640, 29), /* Channel 128 */ | |
122 | CHAN5G(5660, 30), /* Channel 132 */ | |
123 | CHAN5G(5680, 31), /* Channel 136 */ | |
124 | CHAN5G(5700, 32), /* Channel 140 */ | |
125 | /* _We_ call this UNII 3 */ | |
126 | CHAN5G(5745, 33), /* Channel 149 */ | |
127 | CHAN5G(5765, 34), /* Channel 153 */ | |
128 | CHAN5G(5785, 35), /* Channel 157 */ | |
129 | CHAN5G(5805, 36), /* Channel 161 */ | |
130 | CHAN5G(5825, 37), /* Channel 165 */ | |
131 | }; | |
132 | ||
133 | /* Atheros hardware rate code addition for short premble */ | |
134 | #define SHPCHECK(__hw_rate, __flags) \ | |
135 | ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) | |
136 | ||
137 | #define RATE(_bitrate, _hw_rate, _flags) { \ | |
138 | .bitrate = (_bitrate), \ | |
139 | .flags = (_flags), \ | |
140 | .hw_value = (_hw_rate), \ | |
141 | .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ | |
142 | } | |
143 | ||
144 | static struct ieee80211_rate ath9k_legacy_rates[] = { | |
145 | RATE(10, 0x1b, 0), | |
146 | RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), | |
147 | RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), | |
148 | RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), | |
149 | RATE(60, 0x0b, 0), | |
150 | RATE(90, 0x0f, 0), | |
151 | RATE(120, 0x0a, 0), | |
152 | RATE(180, 0x0e, 0), | |
153 | RATE(240, 0x09, 0), | |
154 | RATE(360, 0x0d, 0), | |
155 | RATE(480, 0x08, 0), | |
156 | RATE(540, 0x0c, 0), | |
157 | }; | |
158 | ||
0cf55c21 FF |
159 | #ifdef CONFIG_MAC80211_LEDS |
160 | static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { | |
161 | { .throughput = 0 * 1024, .blink_time = 334 }, | |
162 | { .throughput = 1 * 1024, .blink_time = 260 }, | |
163 | { .throughput = 5 * 1024, .blink_time = 220 }, | |
164 | { .throughput = 10 * 1024, .blink_time = 190 }, | |
165 | { .throughput = 20 * 1024, .blink_time = 170 }, | |
166 | { .throughput = 50 * 1024, .blink_time = 150 }, | |
167 | { .throughput = 70 * 1024, .blink_time = 130 }, | |
168 | { .throughput = 100 * 1024, .blink_time = 110 }, | |
169 | { .throughput = 200 * 1024, .blink_time = 80 }, | |
170 | { .throughput = 300 * 1024, .blink_time = 50 }, | |
171 | }; | |
172 | #endif | |
173 | ||
285f2dda | 174 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 S |
175 | |
176 | /* | |
177 | * Read and write, they both share the same lock. We do this to serialize | |
178 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
179 | * as the FIFO on these devices can only accept sanely 2 requests. | |
180 | */ | |
181 | ||
182 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
183 | { | |
184 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
185 | struct ath_common *common = ath9k_hw_common(ah); | |
186 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
187 | ||
f3eef645 | 188 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
189 | unsigned long flags; |
190 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
191 | iowrite32(val, sc->mem + reg_offset); | |
192 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
193 | } else | |
194 | iowrite32(val, sc->mem + reg_offset); | |
195 | } | |
196 | ||
197 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
198 | { | |
199 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
200 | struct ath_common *common = ath9k_hw_common(ah); | |
201 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
202 | u32 val; | |
203 | ||
f3eef645 | 204 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
205 | unsigned long flags; |
206 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
207 | val = ioread32(sc->mem + reg_offset); | |
208 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
209 | } else | |
210 | val = ioread32(sc->mem + reg_offset); | |
211 | return val; | |
212 | } | |
213 | ||
5479de6e RM |
214 | static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, |
215 | u32 set, u32 clr) | |
216 | { | |
217 | u32 val; | |
218 | ||
219 | val = ioread32(sc->mem + reg_offset); | |
220 | val &= ~clr; | |
221 | val |= set; | |
222 | iowrite32(val, sc->mem + reg_offset); | |
223 | ||
224 | return val; | |
225 | } | |
226 | ||
845e03c9 FF |
227 | static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) |
228 | { | |
229 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
230 | struct ath_common *common = ath9k_hw_common(ah); | |
231 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
232 | unsigned long uninitialized_var(flags); | |
233 | u32 val; | |
234 | ||
f3eef645 | 235 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
845e03c9 | 236 | spin_lock_irqsave(&sc->sc_serial_rw, flags); |
5479de6e | 237 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); |
845e03c9 | 238 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); |
5479de6e RM |
239 | } else |
240 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); | |
845e03c9 FF |
241 | |
242 | return val; | |
243 | } | |
244 | ||
55624204 S |
245 | /**************************/ |
246 | /* Initialization */ | |
247 | /**************************/ | |
248 | ||
249 | static void setup_ht_cap(struct ath_softc *sc, | |
250 | struct ieee80211_sta_ht_cap *ht_info) | |
251 | { | |
3bb065a7 FF |
252 | struct ath_hw *ah = sc->sc_ah; |
253 | struct ath_common *common = ath9k_hw_common(ah); | |
55624204 | 254 | u8 tx_streams, rx_streams; |
3bb065a7 | 255 | int i, max_streams; |
55624204 S |
256 | |
257 | ht_info->ht_supported = true; | |
258 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
259 | IEEE80211_HT_CAP_SM_PS | | |
260 | IEEE80211_HT_CAP_SGI_40 | | |
261 | IEEE80211_HT_CAP_DSSSCCK40; | |
262 | ||
b0a33448 LR |
263 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) |
264 | ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; | |
265 | ||
6473d24d VT |
266 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) |
267 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
268 | ||
55624204 S |
269 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
270 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
271 | ||
e41db61d | 272 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) |
7f1c7a6a | 273 | max_streams = 1; |
e7104195 MSS |
274 | else if (AR_SREV_9462(ah)) |
275 | max_streams = 2; | |
7f1c7a6a | 276 | else if (AR_SREV_9300_20_OR_LATER(ah)) |
3bb065a7 FF |
277 | max_streams = 3; |
278 | else | |
279 | max_streams = 2; | |
280 | ||
7a37081e | 281 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
074a8c0d FF |
282 | if (max_streams >= 2) |
283 | ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; | |
284 | ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); | |
285 | } | |
286 | ||
55624204 S |
287 | /* set up supported mcs set */ |
288 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
82b2d334 FF |
289 | tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); |
290 | rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); | |
3bb065a7 | 291 | |
d2182b69 | 292 | ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n", |
226afe68 | 293 | tx_streams, rx_streams); |
55624204 S |
294 | |
295 | if (tx_streams != rx_streams) { | |
55624204 S |
296 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
297 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
298 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
299 | } | |
300 | ||
3bb065a7 FF |
301 | for (i = 0; i < rx_streams; i++) |
302 | ht_info->mcs.rx_mask[i] = 0xff; | |
55624204 S |
303 | |
304 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; | |
305 | } | |
306 | ||
0c0280bd LR |
307 | static void ath9k_reg_notifier(struct wiphy *wiphy, |
308 | struct regulatory_request *request) | |
55624204 S |
309 | { |
310 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
9ac58615 | 311 | struct ath_softc *sc = hw->priv; |
687f545e RM |
312 | struct ath_hw *ah = sc->sc_ah; |
313 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
687f545e | 314 | |
0c0280bd | 315 | ath_reg_notifier_apply(wiphy, request, reg); |
687f545e RM |
316 | |
317 | /* Set tx power */ | |
318 | if (ah->curchan) { | |
319 | sc->config.txpowlimit = 2 * ah->curchan->chan->max_power; | |
320 | ath9k_ps_wakeup(sc); | |
321 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); | |
322 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; | |
73e4937d ZK |
323 | /* synchronize DFS detector if regulatory domain changed */ |
324 | if (sc->dfs_detector != NULL) | |
325 | sc->dfs_detector->set_dfs_domain(sc->dfs_detector, | |
326 | request->dfs_region); | |
687f545e RM |
327 | ath9k_ps_restore(sc); |
328 | } | |
55624204 S |
329 | } |
330 | ||
331 | /* | |
332 | * This function will allocate both the DMA descriptor structure, and the | |
333 | * buffers it contains. These are used to contain the descriptors used | |
334 | * by the system. | |
335 | */ | |
336 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
337 | struct list_head *head, const char *name, | |
4adfcded | 338 | int nbuf, int ndesc, bool is_tx) |
55624204 | 339 | { |
55624204 | 340 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4adfcded | 341 | u8 *ds; |
55624204 | 342 | struct ath_buf *bf; |
b81950b1 | 343 | int i, bsize, desc_len; |
55624204 | 344 | |
d2182b69 | 345 | ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
226afe68 | 346 | name, nbuf, ndesc); |
55624204 S |
347 | |
348 | INIT_LIST_HEAD(head); | |
4adfcded VT |
349 | |
350 | if (is_tx) | |
351 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
352 | else | |
353 | desc_len = sizeof(struct ath_desc); | |
354 | ||
55624204 | 355 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 356 | if ((desc_len % 4) != 0) { |
3800276a | 357 | ath_err(common, "ath_desc not DWORD aligned\n"); |
4adfcded | 358 | BUG_ON((desc_len % 4) != 0); |
b81950b1 | 359 | return -ENOMEM; |
55624204 S |
360 | } |
361 | ||
4adfcded | 362 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
363 | |
364 | /* | |
365 | * Need additional DMA memory because we can't use | |
366 | * descriptors that cross the 4K page boundary. Assume | |
367 | * one skipped descriptor per 4K page. | |
368 | */ | |
369 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
370 | u32 ndesc_skipped = | |
371 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
372 | u32 dma_len; | |
373 | ||
374 | while (ndesc_skipped) { | |
4adfcded | 375 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
376 | dd->dd_desc_len += dma_len; |
377 | ||
378 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 379 | } |
55624204 S |
380 | } |
381 | ||
382 | /* allocate descriptors */ | |
b81950b1 FF |
383 | dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, |
384 | &dd->dd_desc_paddr, GFP_KERNEL); | |
385 | if (!dd->dd_desc) | |
386 | return -ENOMEM; | |
387 | ||
4adfcded | 388 | ds = (u8 *) dd->dd_desc; |
d2182b69 | 389 | ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
226afe68 JP |
390 | name, ds, (u32) dd->dd_desc_len, |
391 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
55624204 S |
392 | |
393 | /* allocate buffers */ | |
394 | bsize = sizeof(struct ath_buf) * nbuf; | |
b81950b1 FF |
395 | bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); |
396 | if (!bf) | |
397 | return -ENOMEM; | |
55624204 | 398 | |
4adfcded | 399 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { |
55624204 S |
400 | bf->bf_desc = ds; |
401 | bf->bf_daddr = DS2PHYS(dd, ds); | |
402 | ||
403 | if (!(sc->sc_ah->caps.hw_caps & | |
404 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
405 | /* | |
406 | * Skip descriptor addresses which can cause 4KB | |
407 | * boundary crossing (addr + length) with a 32 dword | |
408 | * descriptor fetch. | |
409 | */ | |
410 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
411 | BUG_ON((caddr_t) bf->bf_desc >= | |
412 | ((caddr_t) dd->dd_desc + | |
413 | dd->dd_desc_len)); | |
414 | ||
4adfcded | 415 | ds += (desc_len * ndesc); |
55624204 S |
416 | bf->bf_desc = ds; |
417 | bf->bf_daddr = DS2PHYS(dd, ds); | |
418 | } | |
419 | } | |
420 | list_add_tail(&bf->list, head); | |
421 | } | |
422 | return 0; | |
55624204 S |
423 | } |
424 | ||
285f2dda S |
425 | static int ath9k_init_queues(struct ath_softc *sc) |
426 | { | |
285f2dda S |
427 | int i = 0; |
428 | ||
285f2dda | 429 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 430 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
431 | |
432 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; | |
433 | ath_cabq_update(sc); | |
434 | ||
f2c7a793 FF |
435 | sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); |
436 | ||
bea843c7 | 437 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
066dae93 | 438 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); |
60f2d1d5 | 439 | sc->tx.txq_map[i]->mac80211_qnum = i; |
7702e788 | 440 | sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; |
60f2d1d5 | 441 | } |
285f2dda | 442 | return 0; |
285f2dda S |
443 | } |
444 | ||
f209f529 | 445 | static int ath9k_init_channels_rates(struct ath_softc *sc) |
285f2dda | 446 | { |
f209f529 FF |
447 | void *channels; |
448 | ||
cac4220b FF |
449 | BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + |
450 | ARRAY_SIZE(ath9k_5ghz_chantable) != | |
451 | ATH9K_NUM_CHANNELS); | |
452 | ||
d4659912 | 453 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { |
b81950b1 | 454 | channels = devm_kzalloc(sc->dev, |
f209f529 FF |
455 | sizeof(ath9k_2ghz_chantable), GFP_KERNEL); |
456 | if (!channels) | |
457 | return -ENOMEM; | |
458 | ||
b81950b1 FF |
459 | memcpy(channels, ath9k_2ghz_chantable, |
460 | sizeof(ath9k_2ghz_chantable)); | |
f209f529 | 461 | sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; |
285f2dda S |
462 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; |
463 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = | |
464 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
465 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; | |
466 | sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = | |
467 | ARRAY_SIZE(ath9k_legacy_rates); | |
55624204 S |
468 | } |
469 | ||
d4659912 | 470 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { |
b81950b1 | 471 | channels = devm_kzalloc(sc->dev, |
f209f529 | 472 | sizeof(ath9k_5ghz_chantable), GFP_KERNEL); |
b81950b1 | 473 | if (!channels) |
f209f529 | 474 | return -ENOMEM; |
f209f529 | 475 | |
b81950b1 FF |
476 | memcpy(channels, ath9k_5ghz_chantable, |
477 | sizeof(ath9k_5ghz_chantable)); | |
f209f529 | 478 | sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; |
285f2dda S |
479 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; |
480 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = | |
481 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
482 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
483 | ath9k_legacy_rates + 4; | |
484 | sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = | |
485 | ARRAY_SIZE(ath9k_legacy_rates) - 4; | |
486 | } | |
f209f529 | 487 | return 0; |
285f2dda | 488 | } |
55624204 | 489 | |
285f2dda S |
490 | static void ath9k_init_misc(struct ath_softc *sc) |
491 | { | |
492 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
493 | int i = 0; | |
3d4e20f2 | 494 | |
285f2dda | 495 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); |
55624204 | 496 | |
aaa1ec46 | 497 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
55624204 | 498 | sc->config.txpowlimit = ATH_TXPOWER_MAX; |
364734fa | 499 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
285f2dda | 500 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 501 | |
7545daf4 | 502 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) |
55624204 | 503 | sc->beacon.bslot[i] = NULL; |
102885a5 VT |
504 | |
505 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
506 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
04ccd4a1 SW |
507 | |
508 | sc->spec_config.enabled = 0; | |
509 | sc->spec_config.short_repeat = true; | |
510 | sc->spec_config.count = 8; | |
511 | sc->spec_config.endless = false; | |
512 | sc->spec_config.period = 0xFF; | |
513 | sc->spec_config.fft_period = 0xF; | |
285f2dda | 514 | } |
55624204 | 515 | |
9b60b64b SM |
516 | static void ath9k_init_platform(struct ath_softc *sc) |
517 | { | |
518 | struct ath_hw *ah = sc->sc_ah; | |
519 | struct ath_common *common = ath9k_hw_common(ah); | |
520 | ||
521 | if (common->bus_ops->ath_bus_type != ATH_PCI) | |
522 | return; | |
523 | ||
e861ef52 SM |
524 | if (sc->driver_data & (ATH9K_PCI_CUS198 | |
525 | ATH9K_PCI_CUS230)) { | |
9b60b64b SM |
526 | ah->config.xlna_gpio = 9; |
527 | ah->config.xatten_margin_cfg = true; | |
528 | ||
e861ef52 SM |
529 | ath_info(common, "Set parameters for %s\n", |
530 | (sc->driver_data & ATH9K_PCI_CUS198) ? | |
531 | "CUS198" : "CUS230"); | |
9b60b64b SM |
532 | } |
533 | } | |
534 | ||
ab5c4f71 GJ |
535 | static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, |
536 | void *ctx) | |
537 | { | |
538 | struct ath9k_eeprom_ctx *ec = ctx; | |
539 | ||
540 | if (eeprom_blob) | |
541 | ec->ah->eeprom_blob = eeprom_blob; | |
542 | ||
543 | complete(&ec->complete); | |
544 | } | |
545 | ||
546 | static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) | |
547 | { | |
548 | struct ath9k_eeprom_ctx ec; | |
549 | struct ath_hw *ah = ah = sc->sc_ah; | |
550 | int err; | |
551 | ||
552 | /* try to load the EEPROM content asynchronously */ | |
553 | init_completion(&ec.complete); | |
554 | ec.ah = sc->sc_ah; | |
555 | ||
556 | err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, | |
557 | &ec, ath9k_eeprom_request_cb); | |
558 | if (err < 0) { | |
559 | ath_err(ath9k_hw_common(ah), | |
560 | "EEPROM request failed\n"); | |
561 | return err; | |
562 | } | |
563 | ||
564 | wait_for_completion(&ec.complete); | |
565 | ||
566 | if (!ah->eeprom_blob) { | |
567 | ath_err(ath9k_hw_common(ah), | |
568 | "Unable to load EEPROM file %s\n", name); | |
569 | return -EINVAL; | |
570 | } | |
571 | ||
572 | return 0; | |
573 | } | |
574 | ||
575 | static void ath9k_eeprom_release(struct ath_softc *sc) | |
576 | { | |
577 | release_firmware(sc->sc_ah->eeprom_blob); | |
578 | } | |
579 | ||
eb93e891 | 580 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, |
285f2dda S |
581 | const struct ath_bus_ops *bus_ops) |
582 | { | |
6fb1b1e1 | 583 | struct ath9k_platform_data *pdata = sc->dev->platform_data; |
285f2dda S |
584 | struct ath_hw *ah = NULL; |
585 | struct ath_common *common; | |
586 | int ret = 0, i; | |
587 | int csz = 0; | |
55624204 | 588 | |
b81950b1 | 589 | ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); |
285f2dda S |
590 | if (!ah) |
591 | return -ENOMEM; | |
592 | ||
c1b976d2 | 593 | ah->dev = sc->dev; |
233536e1 | 594 | ah->hw = sc->hw; |
285f2dda | 595 | ah->hw_version.devid = devid; |
f9f84e96 FF |
596 | ah->reg_ops.read = ath9k_ioread32; |
597 | ah->reg_ops.write = ath9k_iowrite32; | |
845e03c9 | 598 | ah->reg_ops.rmw = ath9k_reg_rmw; |
e8fe7336 | 599 | atomic_set(&ah->intr_ref_cnt, -1); |
285f2dda S |
600 | sc->sc_ah = ah; |
601 | ||
ca21cfde | 602 | sc->dfs_detector = dfs_pattern_detector_init(ah, NL80211_DFS_UNSET); |
8e92d3f2 | 603 | |
6de66dd9 | 604 | if (!pdata) { |
a05b5d45 | 605 | ah->ah_flags |= AH_USE_EEPROM; |
6de66dd9 FF |
606 | sc->sc_ah->led_pin = -1; |
607 | } else { | |
608 | sc->sc_ah->gpio_mask = pdata->gpio_mask; | |
609 | sc->sc_ah->gpio_val = pdata->gpio_val; | |
610 | sc->sc_ah->led_pin = pdata->led_pin; | |
f2f5f2a1 | 611 | ah->is_clk_25mhz = pdata->is_clk_25mhz; |
3762561a | 612 | ah->get_mac_revision = pdata->get_mac_revision; |
7d95847c | 613 | ah->external_reset = pdata->external_reset; |
6de66dd9 | 614 | } |
a05b5d45 | 615 | |
285f2dda | 616 | common = ath9k_hw_common(ah); |
f9f84e96 | 617 | common->ops = &ah->reg_ops; |
285f2dda S |
618 | common->bus_ops = bus_ops; |
619 | common->ah = ah; | |
620 | common->hw = sc->hw; | |
621 | common->priv = sc; | |
622 | common->debug_mask = ath9k_debug; | |
8f5dcb1c | 623 | common->btcoex_enabled = ath9k_btcoex_enable == 1; |
05c0be2f | 624 | common->disable_ani = false; |
e09f2dc7 | 625 | |
9b60b64b SM |
626 | /* |
627 | * Platform quirks. | |
628 | */ | |
629 | ath9k_init_platform(sc); | |
630 | ||
e09f2dc7 SM |
631 | /* |
632 | * Enable Antenna diversity only when BTCOEX is disabled | |
633 | * and the user manually requests the feature. | |
634 | */ | |
635 | if (!common->btcoex_enabled && ath9k_enable_diversity) | |
636 | common->antenna_diversity = 1; | |
637 | ||
20b25744 | 638 | spin_lock_init(&common->cc_lock); |
285f2dda | 639 | |
285f2dda S |
640 | spin_lock_init(&sc->sc_serial_rw); |
641 | spin_lock_init(&sc->sc_pm_lock); | |
642 | mutex_init(&sc->mutex); | |
643 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); | |
fb6e252f | 644 | tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, |
285f2dda S |
645 | (unsigned long)sc); |
646 | ||
aaa1ec46 SM |
647 | INIT_WORK(&sc->hw_reset_work, ath_reset_work); |
648 | INIT_WORK(&sc->hw_check_work, ath_hw_check); | |
649 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); | |
650 | INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); | |
651 | setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc); | |
652 | ||
285f2dda S |
653 | /* |
654 | * Cache line size is used to size and align various | |
655 | * structures used to communicate with the hardware. | |
656 | */ | |
657 | ath_read_cachesize(common, &csz); | |
658 | common->cachelsz = csz << 2; /* convert to bytes */ | |
659 | ||
36b07d15 | 660 | if (pdata && pdata->eeprom_name) { |
ab5c4f71 GJ |
661 | ret = ath9k_eeprom_request(sc, pdata->eeprom_name); |
662 | if (ret) | |
b81950b1 | 663 | return ret; |
ab5c4f71 GJ |
664 | } |
665 | ||
d70357d5 | 666 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 667 | ret = ath9k_hw_init(ah); |
d70357d5 | 668 | if (ret) |
285f2dda | 669 | goto err_hw; |
55624204 | 670 | |
6fb1b1e1 FF |
671 | if (pdata && pdata->macaddr) |
672 | memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); | |
673 | ||
285f2dda S |
674 | ret = ath9k_init_queues(sc); |
675 | if (ret) | |
676 | goto err_queues; | |
677 | ||
678 | ret = ath9k_init_btcoex(sc); | |
679 | if (ret) | |
680 | goto err_btcoex; | |
681 | ||
f209f529 FF |
682 | ret = ath9k_init_channels_rates(sc); |
683 | if (ret) | |
684 | goto err_btcoex; | |
685 | ||
f82b4bde | 686 | ath9k_cmn_init_crypto(sc->sc_ah); |
285f2dda | 687 | ath9k_init_misc(sc); |
8f176a3a | 688 | ath_fill_led_pin(sc); |
285f2dda | 689 | |
d09f5f4c SM |
690 | if (common->bus_ops->aspm_init) |
691 | common->bus_ops->aspm_init(common); | |
692 | ||
55624204 | 693 | return 0; |
285f2dda S |
694 | |
695 | err_btcoex: | |
55624204 S |
696 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
697 | if (ATH_TXQ_SETUP(sc, i)) | |
698 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda | 699 | err_queues: |
285f2dda S |
700 | ath9k_hw_deinit(ah); |
701 | err_hw: | |
ab5c4f71 | 702 | ath9k_eeprom_release(sc); |
285f2dda | 703 | return ret; |
55624204 S |
704 | } |
705 | ||
babcbc29 FF |
706 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
707 | { | |
708 | struct ieee80211_supported_band *sband; | |
709 | struct ieee80211_channel *chan; | |
710 | struct ath_hw *ah = sc->sc_ah; | |
babcbc29 FF |
711 | int i; |
712 | ||
713 | sband = &sc->sbands[band]; | |
714 | for (i = 0; i < sband->n_channels; i++) { | |
715 | chan = &sband->channels[i]; | |
716 | ah->curchan = &ah->channels[chan->hw_value]; | |
717 | ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20); | |
718 | ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); | |
babcbc29 FF |
719 | } |
720 | } | |
721 | ||
722 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
723 | { | |
724 | struct ath_hw *ah = sc->sc_ah; | |
725 | struct ath9k_channel *curchan = ah->curchan; | |
726 | ||
727 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
728 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); | |
729 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
730 | ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); | |
731 | ||
732 | ah->curchan = curchan; | |
733 | } | |
734 | ||
43c35284 FF |
735 | void ath9k_reload_chainmask_settings(struct ath_softc *sc) |
736 | { | |
737 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)) | |
738 | return; | |
739 | ||
740 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
741 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); | |
742 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
743 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); | |
744 | } | |
745 | ||
20c8e8dc FF |
746 | static const struct ieee80211_iface_limit if_limits[] = { |
747 | { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) | | |
748 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
749 | BIT(NL80211_IFTYPE_WDS) }, | |
750 | { .max = 8, .types = | |
751 | #ifdef CONFIG_MAC80211_MESH | |
752 | BIT(NL80211_IFTYPE_MESH_POINT) | | |
753 | #endif | |
754 | BIT(NL80211_IFTYPE_AP) | | |
755 | BIT(NL80211_IFTYPE_P2P_GO) }, | |
756 | }; | |
757 | ||
e9cdedf6 ZK |
758 | |
759 | static const struct ieee80211_iface_limit if_dfs_limits[] = { | |
760 | { .max = 1, .types = BIT(NL80211_IFTYPE_AP) }, | |
761 | }; | |
762 | ||
763 | static const struct ieee80211_iface_combination if_comb[] = { | |
764 | { | |
765 | .limits = if_limits, | |
766 | .n_limits = ARRAY_SIZE(if_limits), | |
767 | .max_interfaces = 2048, | |
768 | .num_different_channels = 1, | |
769 | .beacon_int_infra_match = true, | |
770 | }, | |
771 | { | |
772 | .limits = if_dfs_limits, | |
773 | .n_limits = ARRAY_SIZE(if_dfs_limits), | |
774 | .max_interfaces = 1, | |
775 | .num_different_channels = 1, | |
776 | .beacon_int_infra_match = true, | |
777 | .radar_detect_widths = BIT(NL80211_CHAN_NO_HT) | | |
778 | BIT(NL80211_CHAN_HT20), | |
779 | } | |
20c8e8dc | 780 | }; |
43c35284 | 781 | |
964dc9e2 JB |
782 | #ifdef CONFIG_PM |
783 | static const struct wiphy_wowlan_support ath9k_wowlan_support = { | |
784 | .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, | |
785 | .n_patterns = MAX_NUM_USER_PATTERN, | |
786 | .pattern_min_len = 1, | |
787 | .pattern_max_len = MAX_PATTERN_SIZE, | |
788 | }; | |
789 | #endif | |
790 | ||
285f2dda | 791 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 792 | { |
43c35284 FF |
793 | struct ath_hw *ah = sc->sc_ah; |
794 | struct ath_common *common = ath9k_hw_common(ah); | |
285f2dda | 795 | |
55624204 S |
796 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
797 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
798 | IEEE80211_HW_SIGNAL_DBM | | |
55624204 S |
799 | IEEE80211_HW_SUPPORTS_PS | |
800 | IEEE80211_HW_PS_NULLFUNC_STACK | | |
05df4986 | 801 | IEEE80211_HW_SPECTRUM_MGMT | |
79acac07 FF |
802 | IEEE80211_HW_REPORTS_TX_ACK_STATUS | |
803 | IEEE80211_HW_SUPPORTS_RC_TABLE; | |
55624204 | 804 | |
b0a1ae97 OR |
805 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
806 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
807 | ||
808 | if (AR_SREV_9280_20_OR_LATER(ah)) | |
809 | hw->radiotap_mcs_details |= | |
810 | IEEE80211_RADIOTAP_MCS_HAVE_STBC; | |
811 | } | |
5ffaf8a3 | 812 | |
3e6109c5 | 813 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) |
55624204 S |
814 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; |
815 | ||
ec26bcc0 FF |
816 | hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR; |
817 | ||
55624204 | 818 | hw->wiphy->interface_modes = |
c426ee24 JB |
819 | BIT(NL80211_IFTYPE_P2P_GO) | |
820 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
55624204 | 821 | BIT(NL80211_IFTYPE_AP) | |
e51f3eff | 822 | BIT(NL80211_IFTYPE_WDS) | |
55624204 S |
823 | BIT(NL80211_IFTYPE_STATION) | |
824 | BIT(NL80211_IFTYPE_ADHOC) | | |
825 | BIT(NL80211_IFTYPE_MESH_POINT); | |
826 | ||
e9cdedf6 ZK |
827 | hw->wiphy->iface_combinations = if_comb; |
828 | hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); | |
20c8e8dc | 829 | |
531671cb | 830 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
55624204 | 831 | |
cfdc9a8b | 832 | hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; |
fd656234 | 833 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; |
81ddbb5c | 834 | hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; |
cfdc9a8b | 835 | |
9f11e16e | 836 | #ifdef CONFIG_PM_SLEEP |
9f11e16e | 837 | if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) && |
964dc9e2 JB |
838 | device_can_wakeup(sc->dev)) |
839 | hw->wiphy->wowlan = &ath9k_wowlan_support; | |
9f11e16e MSS |
840 | |
841 | atomic_set(&sc->wow_sleep_proc_intr, -1); | |
842 | atomic_set(&sc->wow_got_bmiss_intr, -1); | |
9f11e16e MSS |
843 | #endif |
844 | ||
55624204 S |
845 | hw->queues = 4; |
846 | hw->max_rates = 4; | |
847 | hw->channel_change_time = 5000; | |
195ca3b1 | 848 | hw->max_listen_interval = 1; |
65896510 | 849 | hw->max_rate_tries = 10; |
55624204 S |
850 | hw->sta_data_size = sizeof(struct ath_node); |
851 | hw->vif_data_size = sizeof(struct ath_vif); | |
852 | ||
43c35284 FF |
853 | hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; |
854 | hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; | |
855 | ||
856 | /* single chain devices with rx diversity */ | |
857 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
858 | hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); | |
859 | ||
860 | sc->ant_rx = hw->wiphy->available_antennas_rx; | |
861 | sc->ant_tx = hw->wiphy->available_antennas_tx; | |
862 | ||
d4659912 | 863 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
55624204 S |
864 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
865 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
d4659912 | 866 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
55624204 S |
867 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
868 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
285f2dda | 869 | |
43c35284 | 870 | ath9k_reload_chainmask_settings(sc); |
285f2dda S |
871 | |
872 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
873 | } |
874 | ||
eb93e891 | 875 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
55624204 S |
876 | const struct ath_bus_ops *bus_ops) |
877 | { | |
878 | struct ieee80211_hw *hw = sc->hw; | |
879 | struct ath_common *common; | |
880 | struct ath_hw *ah; | |
285f2dda | 881 | int error = 0; |
55624204 S |
882 | struct ath_regulatory *reg; |
883 | ||
285f2dda | 884 | /* Bring up device */ |
eb93e891 | 885 | error = ath9k_init_softc(devid, sc, bus_ops); |
b81950b1 FF |
886 | if (error) |
887 | return error; | |
55624204 S |
888 | |
889 | ah = sc->sc_ah; | |
890 | common = ath9k_hw_common(ah); | |
285f2dda | 891 | ath9k_set_hw_capab(sc, hw); |
55624204 | 892 | |
285f2dda | 893 | /* Initialize regulatory */ |
55624204 S |
894 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
895 | ath9k_reg_notifier); | |
896 | if (error) | |
b81950b1 | 897 | goto deinit; |
55624204 S |
898 | |
899 | reg = &common->regulatory; | |
900 | ||
285f2dda | 901 | /* Setup TX DMA */ |
55624204 S |
902 | error = ath_tx_init(sc, ATH_TXBUF); |
903 | if (error != 0) | |
b81950b1 | 904 | goto deinit; |
55624204 | 905 | |
285f2dda | 906 | /* Setup RX DMA */ |
55624204 S |
907 | error = ath_rx_init(sc, ATH_RXBUF); |
908 | if (error != 0) | |
b81950b1 | 909 | goto deinit; |
55624204 | 910 | |
babcbc29 FF |
911 | ath9k_init_txpower_limits(sc); |
912 | ||
0cf55c21 FF |
913 | #ifdef CONFIG_MAC80211_LEDS |
914 | /* must be initialized before ieee80211_register_hw */ | |
915 | sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, | |
916 | IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, | |
917 | ARRAY_SIZE(ath9k_tpt_blink)); | |
918 | #endif | |
919 | ||
285f2dda | 920 | /* Register with mac80211 */ |
55624204 | 921 | error = ieee80211_register_hw(hw); |
285f2dda | 922 | if (error) |
b81950b1 | 923 | goto rx_cleanup; |
55624204 | 924 | |
eb272441 BG |
925 | error = ath9k_init_debug(ah); |
926 | if (error) { | |
3800276a | 927 | ath_err(common, "Unable to create debugfs files\n"); |
b81950b1 | 928 | goto unregister; |
eb272441 BG |
929 | } |
930 | ||
285f2dda | 931 | /* Handle world regulatory */ |
55624204 S |
932 | if (!ath_is_world_regd(reg)) { |
933 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
934 | if (error) | |
af690092 | 935 | goto debug_cleanup; |
55624204 S |
936 | } |
937 | ||
285f2dda | 938 | ath_init_leds(sc); |
55624204 S |
939 | ath_start_rfkill_poll(sc); |
940 | ||
941 | return 0; | |
942 | ||
af690092 SM |
943 | debug_cleanup: |
944 | ath9k_deinit_debug(sc); | |
b81950b1 | 945 | unregister: |
285f2dda | 946 | ieee80211_unregister_hw(hw); |
b81950b1 | 947 | rx_cleanup: |
285f2dda | 948 | ath_rx_cleanup(sc); |
b81950b1 | 949 | deinit: |
285f2dda | 950 | ath9k_deinit_softc(sc); |
55624204 S |
951 | return error; |
952 | } | |
953 | ||
954 | /*****************************/ | |
955 | /* De-Initialization */ | |
956 | /*****************************/ | |
957 | ||
285f2dda | 958 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 959 | { |
285f2dda | 960 | int i = 0; |
55624204 | 961 | |
5908120f | 962 | ath9k_deinit_btcoex(sc); |
19686ddf | 963 | |
285f2dda S |
964 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
965 | if (ATH_TXQ_SETUP(sc, i)) | |
966 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
967 | ||
285f2dda | 968 | ath9k_hw_deinit(sc->sc_ah); |
8e92d3f2 ZK |
969 | if (sc->dfs_detector != NULL) |
970 | sc->dfs_detector->exit(sc->dfs_detector); | |
285f2dda | 971 | |
ab5c4f71 | 972 | ath9k_eeprom_release(sc); |
55624204 S |
973 | } |
974 | ||
285f2dda | 975 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
976 | { |
977 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
978 | |
979 | ath9k_ps_wakeup(sc); | |
980 | ||
55624204 | 981 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 982 | ath_deinit_leds(sc); |
55624204 | 983 | |
c7c18060 RM |
984 | ath9k_ps_restore(sc); |
985 | ||
af690092 | 986 | ath9k_deinit_debug(sc); |
55624204 S |
987 | ieee80211_unregister_hw(hw); |
988 | ath_rx_cleanup(sc); | |
285f2dda | 989 | ath9k_deinit_softc(sc); |
55624204 S |
990 | } |
991 | ||
55624204 S |
992 | /************************/ |
993 | /* Module Hooks */ | |
994 | /************************/ | |
995 | ||
996 | static int __init ath9k_init(void) | |
997 | { | |
998 | int error; | |
999 | ||
1000 | /* Register rate control algorithm */ | |
1001 | error = ath_rate_control_register(); | |
1002 | if (error != 0) { | |
516304b0 JP |
1003 | pr_err("Unable to register rate control algorithm: %d\n", |
1004 | error); | |
55624204 S |
1005 | goto err_out; |
1006 | } | |
1007 | ||
55624204 S |
1008 | error = ath_pci_init(); |
1009 | if (error < 0) { | |
516304b0 | 1010 | pr_err("No PCI devices found, driver not installed\n"); |
55624204 | 1011 | error = -ENODEV; |
eb272441 | 1012 | goto err_rate_unregister; |
55624204 S |
1013 | } |
1014 | ||
1015 | error = ath_ahb_init(); | |
1016 | if (error < 0) { | |
1017 | error = -ENODEV; | |
1018 | goto err_pci_exit; | |
1019 | } | |
1020 | ||
1021 | return 0; | |
1022 | ||
1023 | err_pci_exit: | |
1024 | ath_pci_exit(); | |
1025 | ||
55624204 S |
1026 | err_rate_unregister: |
1027 | ath_rate_control_unregister(); | |
1028 | err_out: | |
1029 | return error; | |
1030 | } | |
1031 | module_init(ath9k_init); | |
1032 | ||
1033 | static void __exit ath9k_exit(void) | |
1034 | { | |
d584747b | 1035 | is_ath9k_unloaded = true; |
55624204 S |
1036 | ath_ahb_exit(); |
1037 | ath_pci_exit(); | |
55624204 | 1038 | ath_rate_control_unregister(); |
516304b0 | 1039 | pr_info("%s: Driver unloaded\n", dev_info); |
55624204 S |
1040 | } |
1041 | module_exit(ath9k_exit); |