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mac80211: add flags for STBC (Space-Time Block Coding)
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / init.c
CommitLineData
55624204
S		 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "ath9k.h"
18
19static char *dev_info = "ath9k";
20
21MODULE_AUTHOR("Atheros Communications");
22MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
23MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
24MODULE_LICENSE("Dual BSD/GPL");
25
26static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
27module_param_named(debug, ath9k_debug, uint, 0);
28MODULE_PARM_DESC(debug, "Debugging mask");
29
30int modparam_nohwcrypt;
31module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
32MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
33
34/* We use the hw_value as an index into our private channel structure */
35
36#define CHAN2G(_freq, _idx) { \
37 .center_freq = (_freq), \
38 .hw_value = (_idx), \
39 .max_power = 20, \
40}
41
42#define CHAN5G(_freq, _idx) { \
43 .band = IEEE80211_BAND_5GHZ, \
44 .center_freq = (_freq), \
45 .hw_value = (_idx), \
46 .max_power = 20, \
47}
48
49/* Some 2 GHz radios are actually tunable on 2312-2732
50 * on 5 MHz steps, we support the channels which we know
51 * we have calibration data for all cards though to make
52 * this static */
53static struct ieee80211_channel ath9k_2ghz_chantable[] = {
54 CHAN2G(2412, 0), /* Channel 1 */
55 CHAN2G(2417, 1), /* Channel 2 */
56 CHAN2G(2422, 2), /* Channel 3 */
57 CHAN2G(2427, 3), /* Channel 4 */
58 CHAN2G(2432, 4), /* Channel 5 */
59 CHAN2G(2437, 5), /* Channel 6 */
60 CHAN2G(2442, 6), /* Channel 7 */
61 CHAN2G(2447, 7), /* Channel 8 */
62 CHAN2G(2452, 8), /* Channel 9 */
63 CHAN2G(2457, 9), /* Channel 10 */
64 CHAN2G(2462, 10), /* Channel 11 */
65 CHAN2G(2467, 11), /* Channel 12 */
66 CHAN2G(2472, 12), /* Channel 13 */
67 CHAN2G(2484, 13), /* Channel 14 */
68};
69
70/* Some 5 GHz radios are actually tunable on XXXX-YYYY
71 * on 5 MHz steps, we support the channels which we know
72 * we have calibration data for all cards though to make
73 * this static */
74static struct ieee80211_channel ath9k_5ghz_chantable[] = {
75 /* _We_ call this UNII 1 */
76 CHAN5G(5180, 14), /* Channel 36 */
77 CHAN5G(5200, 15), /* Channel 40 */
78 CHAN5G(5220, 16), /* Channel 44 */
79 CHAN5G(5240, 17), /* Channel 48 */
80 /* _We_ call this UNII 2 */
81 CHAN5G(5260, 18), /* Channel 52 */
82 CHAN5G(5280, 19), /* Channel 56 */
83 CHAN5G(5300, 20), /* Channel 60 */
84 CHAN5G(5320, 21), /* Channel 64 */
85 /* _We_ call this "Middle band" */
86 CHAN5G(5500, 22), /* Channel 100 */
87 CHAN5G(5520, 23), /* Channel 104 */
88 CHAN5G(5540, 24), /* Channel 108 */
89 CHAN5G(5560, 25), /* Channel 112 */
90 CHAN5G(5580, 26), /* Channel 116 */
91 CHAN5G(5600, 27), /* Channel 120 */
92 CHAN5G(5620, 28), /* Channel 124 */
93 CHAN5G(5640, 29), /* Channel 128 */
94 CHAN5G(5660, 30), /* Channel 132 */
95 CHAN5G(5680, 31), /* Channel 136 */
96 CHAN5G(5700, 32), /* Channel 140 */
97 /* _We_ call this UNII 3 */
98 CHAN5G(5745, 33), /* Channel 149 */
99 CHAN5G(5765, 34), /* Channel 153 */
100 CHAN5G(5785, 35), /* Channel 157 */
101 CHAN5G(5805, 36), /* Channel 161 */
102 CHAN5G(5825, 37), /* Channel 165 */
103};
104
105/* Atheros hardware rate code addition for short premble */
106#define SHPCHECK(__hw_rate, __flags) \
107 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
108
109#define RATE(_bitrate, _hw_rate, _flags) { \
110 .bitrate = (_bitrate), \
111 .flags = (_flags), \
112 .hw_value = (_hw_rate), \
113 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
114}
115
116static struct ieee80211_rate ath9k_legacy_rates[] = {
117 RATE(10, 0x1b, 0),
118 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
119 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
120 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
121 RATE(60, 0x0b, 0),
122 RATE(90, 0x0f, 0),
123 RATE(120, 0x0a, 0),
124 RATE(180, 0x0e, 0),
125 RATE(240, 0x09, 0),
126 RATE(360, 0x0d, 0),
127 RATE(480, 0x08, 0),
128 RATE(540, 0x0c, 0),
129};
130
285f2dda 131static void ath9k_deinit_softc(struct ath_softc *sc);
55624204
S		 132
133/*
134 * Read and write, they both share the same lock. We do this to serialize
135 * reads and writes on Atheros 802.11n PCI devices only. This is required
136 * as the FIFO on these devices can only accept sanely 2 requests.
137 */
138
139static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
140{
141 struct ath_hw *ah = (struct ath_hw *) hw_priv;
142 struct ath_common *common = ath9k_hw_common(ah);
143 struct ath_softc *sc = (struct ath_softc *) common->priv;
144
145 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
146 unsigned long flags;
147 spin_lock_irqsave(&sc->sc_serial_rw, flags);
148 iowrite32(val, sc->mem + reg_offset);
149 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
150 } else
151 iowrite32(val, sc->mem + reg_offset);
152}
153
154static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
155{
156 struct ath_hw *ah = (struct ath_hw *) hw_priv;
157 struct ath_common *common = ath9k_hw_common(ah);
158 struct ath_softc *sc = (struct ath_softc *) common->priv;
159 u32 val;
160
161 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
162 unsigned long flags;
163 spin_lock_irqsave(&sc->sc_serial_rw, flags);
164 val = ioread32(sc->mem + reg_offset);
165 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
166 } else
167 val = ioread32(sc->mem + reg_offset);
168 return val;
169}
170
171static const struct ath_ops ath9k_common_ops = {
172 .read = ath9k_ioread32,
173 .write = ath9k_iowrite32,
174};
175
3bb065a7
FF		 176static int count_streams(unsigned int chainmask, int max)
177{
178 int streams = 0;
179
180 do {
181 if (++streams == max)
182 break;
183 } while ((chainmask = chainmask & (chainmask - 1)));
184
185 return streams;
186}
187
55624204
S		 188/**************************/
189/* Initialization */
190/**************************/
191
192static void setup_ht_cap(struct ath_softc *sc,
193 struct ieee80211_sta_ht_cap *ht_info)
194{
3bb065a7
FF		 195 struct ath_hw *ah = sc->sc_ah;
196 struct ath_common *common = ath9k_hw_common(ah);
55624204 197 u8 tx_streams, rx_streams;
3bb065a7 198 int i, max_streams;
55624204
S		 199
200 ht_info->ht_supported = true;
201 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
202 IEEE80211_HT_CAP_SM_PS |
203 IEEE80211_HT_CAP_SGI_40 |
204 IEEE80211_HT_CAP_DSSSCCK40;
205
b0a33448
LR		 206 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
207 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
208
55624204
S		 209 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
210 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
211
3bb065a7
FF		 212 if (AR_SREV_9300_20_OR_LATER(ah))
213 max_streams = 3;
214 else
215 max_streams = 2;
216
55624204
S		 217 /* set up supported mcs set */
218 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
3bb065a7
FF		 219 tx_streams = count_streams(common->tx_chainmask, max_streams);
220 rx_streams = count_streams(common->rx_chainmask, max_streams);
221
222 ath_print(common, ATH_DBG_CONFIG,
223 "TX streams %d, RX streams: %d\n",
224 tx_streams, rx_streams);
55624204
S		 225
226 if (tx_streams != rx_streams) {
55624204
S		 227 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
228 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
229 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
230 }
231
3bb065a7
FF		 232 for (i = 0; i < rx_streams; i++)
233 ht_info->mcs.rx_mask[i] = 0xff;
55624204
S		 234
235 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
236}
237
238static int ath9k_reg_notifier(struct wiphy *wiphy,
239 struct regulatory_request *request)
240{
241 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
242 struct ath_wiphy *aphy = hw->priv;
243 struct ath_softc *sc = aphy->sc;
244 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
245
246 return ath_reg_notifier_apply(wiphy, request, reg);
247}
248
249/*
250 * This function will allocate both the DMA descriptor structure, and the
251 * buffers it contains. These are used to contain the descriptors used
252 * by the system.
253*/
254int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
255 struct list_head *head, const char *name,
4adfcded 256 int nbuf, int ndesc, bool is_tx)
55624204
S		 257{
258#define DS2PHYS(_dd, _ds) \
259 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
260#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
261#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
262 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4adfcded 263 u8 *ds;
55624204 264 struct ath_buf *bf;
4adfcded 265 int i, bsize, error, desc_len;
55624204
S		 266
267 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
268 name, nbuf, ndesc);
269
270 INIT_LIST_HEAD(head);
4adfcded
VT		 271
272 if (is_tx)
273 desc_len = sc->sc_ah->caps.tx_desc_len;
274 else
275 desc_len = sizeof(struct ath_desc);
276
55624204 277 /* ath_desc must be a multiple of DWORDs */
4adfcded 278 if ((desc_len % 4) != 0) {
55624204
S		 279 ath_print(common, ATH_DBG_FATAL,
280 "ath_desc not DWORD aligned\n");
4adfcded 281 BUG_ON((desc_len % 4) != 0);
55624204
S		 282 error = -ENOMEM;
283 goto fail;
284 }
285
4adfcded 286 dd->dd_desc_len = desc_len * nbuf * ndesc;
55624204
S		 287
288 /*
289 * Need additional DMA memory because we can't use
290 * descriptors that cross the 4K page boundary. Assume
291 * one skipped descriptor per 4K page.
292 */
293 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
294 u32 ndesc_skipped =
295 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
296 u32 dma_len;
297
298 while (ndesc_skipped) {
4adfcded 299 dma_len = ndesc_skipped * desc_len;
55624204
S		 300 dd->dd_desc_len += dma_len;
301
302 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
303 };
304 }
305
306 /* allocate descriptors */
307 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
308 &dd->dd_desc_paddr, GFP_KERNEL);
309 if (dd->dd_desc == NULL) {
310 error = -ENOMEM;
311 goto fail;
312 }
4adfcded 313 ds = (u8 *) dd->dd_desc;
55624204
S		 314 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
315 name, ds, (u32) dd->dd_desc_len,
316 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
317
318 /* allocate buffers */
319 bsize = sizeof(struct ath_buf) * nbuf;
320 bf = kzalloc(bsize, GFP_KERNEL);
321 if (bf == NULL) {
322 error = -ENOMEM;
323 goto fail2;
324 }
325 dd->dd_bufptr = bf;
326
4adfcded 327 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
55624204
S		 328 bf->bf_desc = ds;
329 bf->bf_daddr = DS2PHYS(dd, ds);
330
331 if (!(sc->sc_ah->caps.hw_caps &
332 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
333 /*
334 * Skip descriptor addresses which can cause 4KB
335 * boundary crossing (addr + length) with a 32 dword
336 * descriptor fetch.
337 */
338 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
339 BUG_ON((caddr_t) bf->bf_desc >=
340 ((caddr_t) dd->dd_desc +
341 dd->dd_desc_len));
342
4adfcded 343 ds += (desc_len * ndesc);
55624204
S		 344 bf->bf_desc = ds;
345 bf->bf_daddr = DS2PHYS(dd, ds);
346 }
347 }
348 list_add_tail(&bf->list, head);
349 }
350 return 0;
351fail2:
352 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
353 dd->dd_desc_paddr);
354fail:
355 memset(dd, 0, sizeof(*dd));
356 return error;
357#undef ATH_DESC_4KB_BOUND_CHECK
358#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
359#undef DS2PHYS
360}
361
285f2dda 362static void ath9k_init_crypto(struct ath_softc *sc)
55624204 363{
285f2dda
S		 364 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
365 int i = 0;
55624204
S		 366
367 /* Get the hardware key cache size. */
285f2dda 368 common->keymax = sc->sc_ah->caps.keycache_size;
55624204
S		 369 if (common->keymax > ATH_KEYMAX) {
370 ath_print(common, ATH_DBG_ANY,
371 "Warning, using only %u entries in %u key cache\n",
372 ATH_KEYMAX, common->keymax);
373 common->keymax = ATH_KEYMAX;
374 }
375
376 /*
377 * Reset the key cache since some parts do not
378 * reset the contents on initial power up.
379 */
380 for (i = 0; i < common->keymax; i++)
285f2dda 381 ath9k_hw_keyreset(sc->sc_ah, (u16) i);
55624204 382
285f2dda
S		 383 if (ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER,
384 ATH9K_CIPHER_TKIP, NULL)) {
385 /*
386 * Whether we should enable h/w TKIP MIC.
387 * XXX: if we don't support WME TKIP MIC, then we wouldn't
388 * report WMM capable, so it's always safe to turn on
389 * TKIP MIC in this case.
390 */
391 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC, 0, 1, NULL);
392 }
55624204
S		 393
394 /*
285f2dda
S		 395 * Check whether the separate key cache entries
396 * are required to handle both tx+rx MIC keys.
397 * With split mic keys the number of stations is limited
398 * to 27 otherwise 59.
55624204 399 */
285f2dda
S		 400 if (ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER,
401 ATH9K_CIPHER_TKIP, NULL)
402 && ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER,
403 ATH9K_CIPHER_MIC, NULL)
404 && ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_TKIP_SPLIT,
405 0, NULL))
406 common->splitmic = 1;
407
408 /* turn on mcast key search if possible */
409 if (!ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
410 (void)ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH,
411 1, 1, NULL);
412
413}
414
415static int ath9k_init_btcoex(struct ath_softc *sc)
416{
417 int r, qnum;
418
419 switch (sc->sc_ah->btcoex_hw.scheme) {
420 case ATH_BTCOEX_CFG_NONE:
421 break;
422 case ATH_BTCOEX_CFG_2WIRE:
423 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
424 break;
425 case ATH_BTCOEX_CFG_3WIRE:
426 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
427 r = ath_init_btcoex_timer(sc);
428 if (r)
429 return -1;
430 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
431 ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
432 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
433 break;
434 default:
435 WARN_ON(1);
436 break;
437 }
438
439 return 0;
440}
441
442static int ath9k_init_queues(struct ath_softc *sc)
443{
444 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
445 int i = 0;
446
447 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
448 sc->tx.hwq_map[i] = -1;
449
450 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
55624204
S		 451 if (sc->beacon.beaconq == -1) {
452 ath_print(common, ATH_DBG_FATAL,
453 "Unable to setup a beacon xmit queue\n");
285f2dda 454 goto err;
55624204 455 }
285f2dda 456
55624204
S		 457 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
458 if (sc->beacon.cabq == NULL) {
459 ath_print(common, ATH_DBG_FATAL,
460 "Unable to setup CAB xmit queue\n");
285f2dda 461 goto err;
55624204
S		 462 }
463
464 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
465 ath_cabq_update(sc);
466
55624204
S		 467 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
468 ath_print(common, ATH_DBG_FATAL,
469 "Unable to setup xmit queue for BK traffic\n");
285f2dda 470 goto err;
55624204
S		 471 }
472
473 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
474 ath_print(common, ATH_DBG_FATAL,
475 "Unable to setup xmit queue for BE traffic\n");
285f2dda 476 goto err;
55624204
S		 477 }
478 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
479 ath_print(common, ATH_DBG_FATAL,
480 "Unable to setup xmit queue for VI traffic\n");
285f2dda 481 goto err;
55624204
S		 482 }
483 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
484 ath_print(common, ATH_DBG_FATAL,
485 "Unable to setup xmit queue for VO traffic\n");
285f2dda 486 goto err;
55624204
S		 487 }
488
285f2dda 489 return 0;
55624204 490
285f2dda
S		 491err:
492 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
493 if (ATH_TXQ_SETUP(sc, i))
494 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
55624204 495
285f2dda
S		 496 return -EIO;
497}
498
499static void ath9k_init_channels_rates(struct ath_softc *sc)
500{
501 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
502 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
503 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
504 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
505 ARRAY_SIZE(ath9k_2ghz_chantable);
506 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
507 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
508 ARRAY_SIZE(ath9k_legacy_rates);
55624204
S		 509 }
510
285f2dda
S		 511 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
512 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
513 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
514 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
515 ARRAY_SIZE(ath9k_5ghz_chantable);
516 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
517 ath9k_legacy_rates + 4;
518 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
519 ARRAY_SIZE(ath9k_legacy_rates) - 4;
520 }
521}
55624204 522
285f2dda
S		 523static void ath9k_init_misc(struct ath_softc *sc)
524{
525 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
526 int i = 0;
527
528 common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
529 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
55624204
S		 530
531 sc->config.txpowlimit = ATH_TXPOWER_MAX;
532
285f2dda 533 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
55624204
S		 534 sc->sc_flags |= SC_OP_TXAGGR;
535 sc->sc_flags |= SC_OP_RXAGGR;
536 }
537
285f2dda
S		 538 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
539 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
55624204 540
8fe65368 541 ath9k_hw_set_diversity(sc->sc_ah, true);
285f2dda 542 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
55624204 543
285f2dda 544 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
55624204
S		 545 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
546
285f2dda 547 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
55624204 548
55624204
S		 549 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
550 sc->beacon.bslot[i] = NULL;
551 sc->beacon.bslot_aphy[i] = NULL;
552 }
285f2dda 553}
55624204 554
285f2dda
S		 555static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
556 const struct ath_bus_ops *bus_ops)
557{
558 struct ath_hw *ah = NULL;
559 struct ath_common *common;
560 int ret = 0, i;
561 int csz = 0;
55624204 562
285f2dda
S		 563 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
564 if (!ah)
565 return -ENOMEM;
566
567 ah->hw_version.devid = devid;
568 ah->hw_version.subsysid = subsysid;
569 sc->sc_ah = ah;
570
571 common = ath9k_hw_common(ah);
572 common->ops = &ath9k_common_ops;
573 common->bus_ops = bus_ops;
574 common->ah = ah;
575 common->hw = sc->hw;
576 common->priv = sc;
577 common->debug_mask = ath9k_debug;
578
579 spin_lock_init(&sc->wiphy_lock);
580 spin_lock_init(&sc->sc_resetlock);
581 spin_lock_init(&sc->sc_serial_rw);
582 spin_lock_init(&sc->sc_pm_lock);
583 mutex_init(&sc->mutex);
584 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
585 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
586 (unsigned long)sc);
587
588 /*
589 * Cache line size is used to size and align various
590 * structures used to communicate with the hardware.
591 */
592 ath_read_cachesize(common, &csz);
593 common->cachelsz = csz << 2; /* convert to bytes */
594
d70357d5 595 /* Initializes the hardware for all supported chipsets */
285f2dda 596 ret = ath9k_hw_init(ah);
d70357d5 597 if (ret)
285f2dda 598 goto err_hw;
55624204 599
285f2dda
S		 600 ret = ath9k_init_debug(ah);
601 if (ret) {
602 ath_print(common, ATH_DBG_FATAL,
603 "Unable to create debugfs files\n");
604 goto err_debug;
55624204
S		 605 }
606
285f2dda
S		 607 ret = ath9k_init_queues(sc);
608 if (ret)
609 goto err_queues;
610
611 ret = ath9k_init_btcoex(sc);
612 if (ret)
613 goto err_btcoex;
614
615 ath9k_init_crypto(sc);
616 ath9k_init_channels_rates(sc);
617 ath9k_init_misc(sc);
618
55624204 619 return 0;
285f2dda
S		 620
621err_btcoex:
55624204
S		 622 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
623 if (ATH_TXQ_SETUP(sc, i))
624 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
285f2dda
S		 625err_queues:
626 ath9k_exit_debug(ah);
627err_debug:
628 ath9k_hw_deinit(ah);
629err_hw:
630 tasklet_kill(&sc->intr_tq);
631 tasklet_kill(&sc->bcon_tasklet);
55624204 632
285f2dda
S		 633 kfree(ah);
634 sc->sc_ah = NULL;
635
636 return ret;
55624204
S		 637}
638
285f2dda 639void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
55624204 640{
285f2dda
S		 641 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
642
55624204
S		 643 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
644 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
645 IEEE80211_HW_SIGNAL_DBM |
55624204
S		 646 IEEE80211_HW_SUPPORTS_PS |
647 IEEE80211_HW_PS_NULLFUNC_STACK |
05df4986
VN		 648 IEEE80211_HW_SPECTRUM_MGMT |
649 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
55624204 650
5ffaf8a3
LR		 651 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
652 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
653
55624204
S		 654 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
655 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
656
657 hw->wiphy->interface_modes =
658 BIT(NL80211_IFTYPE_AP) |
659 BIT(NL80211_IFTYPE_STATION) |
660 BIT(NL80211_IFTYPE_ADHOC) |
661 BIT(NL80211_IFTYPE_MESH_POINT);
662
663 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
664
665 hw->queues = 4;
666 hw->max_rates = 4;
667 hw->channel_change_time = 5000;
668 hw->max_listen_interval = 10;
65896510 669 hw->max_rate_tries = 10;
55624204
S		 670 hw->sta_data_size = sizeof(struct ath_node);
671 hw->vif_data_size = sizeof(struct ath_vif);
672
673 hw->rate_control_algorithm = "ath9k_rate_control";
674
675 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
676 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
677 &sc->sbands[IEEE80211_BAND_2GHZ];
678 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
679 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
680 &sc->sbands[IEEE80211_BAND_5GHZ];
285f2dda
S		 681
682 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
683 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
684 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
685 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
686 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
687 }
688
689 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
55624204
S		 690}
691
285f2dda 692int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
55624204
S		 693 const struct ath_bus_ops *bus_ops)
694{
695 struct ieee80211_hw *hw = sc->hw;
696 struct ath_common *common;
697 struct ath_hw *ah;
285f2dda 698 int error = 0;
55624204
S		 699 struct ath_regulatory *reg;
700
285f2dda
S		 701 /* Bring up device */
702 error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
55624204 703 if (error != 0)
285f2dda 704 goto error_init;
55624204
S		 705
706 ah = sc->sc_ah;
707 common = ath9k_hw_common(ah);
285f2dda 708 ath9k_set_hw_capab(sc, hw);
55624204 709
285f2dda 710 /* Initialize regulatory */
55624204
S		 711 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
712 ath9k_reg_notifier);
713 if (error)
285f2dda 714 goto error_regd;
55624204
S		 715
716 reg = &common->regulatory;
717
285f2dda 718 /* Setup TX DMA */
55624204
S		 719 error = ath_tx_init(sc, ATH_TXBUF);
720 if (error != 0)
285f2dda 721 goto error_tx;
55624204 722
285f2dda 723 /* Setup RX DMA */
55624204
S		 724 error = ath_rx_init(sc, ATH_RXBUF);
725 if (error != 0)
285f2dda 726 goto error_rx;
55624204 727
285f2dda 728 /* Register with mac80211 */
55624204 729 error = ieee80211_register_hw(hw);
285f2dda
S		 730 if (error)
731 goto error_register;
55624204 732
285f2dda 733 /* Handle world regulatory */
55624204
S		 734 if (!ath_is_world_regd(reg)) {
735 error = regulatory_hint(hw->wiphy, reg->alpha2);
736 if (error)
285f2dda 737 goto error_world;
55624204
S		 738 }
739
285f2dda
S		 740 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
741 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
742 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
55624204 743
285f2dda 744 ath_init_leds(sc);
55624204
S		 745 ath_start_rfkill_poll(sc);
746
747 return 0;
748
285f2dda
S		 749error_world:
750 ieee80211_unregister_hw(hw);
751error_register:
752 ath_rx_cleanup(sc);
753error_rx:
754 ath_tx_cleanup(sc);
755error_tx:
756 /* Nothing */
757error_regd:
758 ath9k_deinit_softc(sc);
759error_init:
55624204
S		 760 return error;
761}
762
763/*****************************/
764/* De-Initialization */
765/*****************************/
766
285f2dda 767static void ath9k_deinit_softc(struct ath_softc *sc)
55624204 768{
285f2dda 769 int i = 0;
55624204 770
285f2dda
S		 771 if ((sc->btcoex.no_stomp_timer) &&
772 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
773 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
55624204 774
285f2dda
S		 775 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
776 if (ATH_TXQ_SETUP(sc, i))
777 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
778
779 ath9k_exit_debug(sc->sc_ah);
780 ath9k_hw_deinit(sc->sc_ah);
781
782 tasklet_kill(&sc->intr_tq);
783 tasklet_kill(&sc->bcon_tasklet);
736b3a27
S		 784
785 kfree(sc->sc_ah);
786 sc->sc_ah = NULL;
55624204
S		 787}
788
285f2dda 789void ath9k_deinit_device(struct ath_softc *sc)
55624204
S		 790{
791 struct ieee80211_hw *hw = sc->hw;
55624204
S		 792 int i = 0;
793
794 ath9k_ps_wakeup(sc);
795
55624204 796 wiphy_rfkill_stop_polling(sc->hw->wiphy);
285f2dda 797 ath_deinit_leds(sc);
55624204
S		 798
799 for (i = 0; i < sc->num_sec_wiphy; i++) {
800 struct ath_wiphy *aphy = sc->sec_wiphy[i];
801 if (aphy == NULL)
802 continue;
803 sc->sec_wiphy[i] = NULL;
804 ieee80211_unregister_hw(aphy->hw);
805 ieee80211_free_hw(aphy->hw);
806 }
285f2dda
S		 807 kfree(sc->sec_wiphy);
808
55624204
S		 809 ieee80211_unregister_hw(hw);
810 ath_rx_cleanup(sc);
811 ath_tx_cleanup(sc);
285f2dda 812 ath9k_deinit_softc(sc);
55624204
S		 813}
814
815void ath_descdma_cleanup(struct ath_softc *sc,
816 struct ath_descdma *dd,
817 struct list_head *head)
818{
819 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
820 dd->dd_desc_paddr);
821
822 INIT_LIST_HEAD(head);
823 kfree(dd->dd_bufptr);
824 memset(dd, 0, sizeof(*dd));
825}
826
55624204
S		 827/************************/
828/* Module Hooks */
829/************************/
830
831static int __init ath9k_init(void)
832{
833 int error;
834
835 /* Register rate control algorithm */
836 error = ath_rate_control_register();
837 if (error != 0) {
838 printk(KERN_ERR
839 "ath9k: Unable to register rate control "
840 "algorithm: %d\n",
841 error);
842 goto err_out;
843 }
844
845 error = ath9k_debug_create_root();
846 if (error) {
847 printk(KERN_ERR
848 "ath9k: Unable to create debugfs root: %d\n",
849 error);
850 goto err_rate_unregister;
851 }
852
853 error = ath_pci_init();
854 if (error < 0) {
855 printk(KERN_ERR
856 "ath9k: No PCI devices found, driver not installed.\n");
857 error = -ENODEV;
858 goto err_remove_root;
859 }
860
861 error = ath_ahb_init();
862 if (error < 0) {
863 error = -ENODEV;
864 goto err_pci_exit;
865 }
866
867 return 0;
868
869 err_pci_exit:
870 ath_pci_exit();
871
872 err_remove_root:
873 ath9k_debug_remove_root();
874 err_rate_unregister:
875 ath_rate_control_unregister();
876 err_out:
877 return error;
878}
879module_init(ath9k_init);
880
881static void __exit ath9k_exit(void)
882{
883 ath_ahb_exit();
884 ath_pci_exit();
885 ath9k_debug_remove_root();
886 ath_rate_control_unregister();
887 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
888}
889module_exit(ath9k_exit);
Linux kernel - Deliverables
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