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Merge tag 'efi-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/mfleming...
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / mac.c
CommitLineData
f1dc5600 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f1dc5600
S		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
990b70ab 17#include "hw.h"
ac0bb767 18#include "hw-ops.h"
ee40fa06 19#include <linux/export.h>
f1dc5600 20
cc610ac0
VT		 21static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
22 struct ath9k_tx_queue_info *qi)
23{
d2182b69 24 ath_dbg(ath9k_hw_common(ah), INTERRUPT,
226afe68
JP		 25 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
28 ah->txurn_interrupt_mask);
cc610ac0 29
7d0d0df0
S		 30 ENABLE_REGWRITE_BUFFER(ah);
31
cc610ac0
VT		 32 REG_WRITE(ah, AR_IMR_S0,
33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
35 REG_WRITE(ah, AR_IMR_S1,
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
38
39 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
40 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
7d0d0df0
S		 42
43 REGWRITE_BUFFER_FLUSH(ah);
cc610ac0
VT		 44}
45
46u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
47{
48 return REG_READ(ah, AR_QTXDP(q));
49}
50EXPORT_SYMBOL(ath9k_hw_gettxbuf);
51
52void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
53{
54 REG_WRITE(ah, AR_QTXDP(q), txdp);
55}
56EXPORT_SYMBOL(ath9k_hw_puttxbuf);
57
58void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
59{
d2182b69 60 ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q);
cc610ac0
VT		 61 REG_WRITE(ah, AR_Q_TXE, 1 << q);
62}
63EXPORT_SYMBOL(ath9k_hw_txstart);
64
cc610ac0
VT		 65u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
66{
67 u32 npend;
68
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
70 if (npend == 0) {
71
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
73 npend = 1;
74 }
75
76 return npend;
77}
78EXPORT_SYMBOL(ath9k_hw_numtxpending);
79
80/**
81 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
82 *
83 * @ah: atheros hardware struct
84 * @bIncTrigLevel: whether or not the frame trigger level should be updated
85 *
86 * The frame trigger level specifies the minimum number of bytes,
87 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
88 * before the PCU will initiate sending the frame on the air. This can
89 * mean we initiate transmit before a full frame is on the PCU TX FIFO.
90 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
91 * first)
92 *
93 * Caution must be taken to ensure to set the frame trigger level based
94 * on the DMA request size. For example if the DMA request size is set to
95 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
96 * there need to be enough space in the tx FIFO for the requested transfer
97 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
98 * the threshold to a value beyond 6, then the transmit will hang.
99 *
100 * Current dual stream devices have a PCU TX FIFO size of 8 KB.
101 * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
102 * there is a hardware issue which forces us to use 2 KB instead so the
103 * frame trigger level must not exceed 2 KB for these chipsets.
104 */
105bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
106{
107 u32 txcfg, curLevel, newLevel;
cc610ac0
VT		 108
109 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
110 return false;
111
4df3071e 112 ath9k_hw_disable_interrupts(ah);
cc610ac0
VT		 113
114 txcfg = REG_READ(ah, AR_TXCFG);
115 curLevel = MS(txcfg, AR_FTRIG);
116 newLevel = curLevel;
117 if (bIncTrigLevel) {
118 if (curLevel < ah->config.max_txtrig_level)
119 newLevel++;
120 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
121 newLevel--;
122 if (newLevel != curLevel)
123 REG_WRITE(ah, AR_TXCFG,
124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
125
4df3071e 126 ath9k_hw_enable_interrupts(ah);
cc610ac0
VT		 127
128 ah->tx_trig_level = newLevel;
129
130 return newLevel != curLevel;
131}
132EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
133
0d51cccc 134void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
cc610ac0 135{
8d1bd2af 136 int maxdelay = 1000;
0d51cccc 137 int i, q;
cc610ac0 138
8d1bd2af
FF		 139 if (ah->curchan) {
140 if (IS_CHAN_HALF_RATE(ah->curchan))
141 maxdelay *= 2;
142 else if (IS_CHAN_QUARTER_RATE(ah->curchan))
143 maxdelay *= 4;
144 }
145
0d51cccc 146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
cc610ac0 147
0d51cccc
FF		 148 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
149 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
150 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
cc610ac0 151
0d51cccc 152 for (q = 0; q < AR_NUM_QCU; q++) {
8d1bd2af 153 for (i = 0; i < maxdelay; i++) {
0d51cccc
FF		 154 if (i)
155 udelay(5);
cc610ac0 156
0d51cccc 157 if (!ath9k_hw_numtxpending(ah, q))
cc610ac0 158 break;
cc610ac0 159 }
0d51cccc 160 }
cc610ac0 161
0d51cccc
FF		 162 REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
163 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
164 REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
cc610ac0 165
0d51cccc
FF		 166 REG_WRITE(ah, AR_Q_TXD, 0);
167}
168EXPORT_SYMBOL(ath9k_hw_abort_tx_dma);
cc610ac0 169
efff395e 170bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
cc610ac0 171{
efff395e 172#define ATH9K_TX_STOP_DMA_TIMEOUT 1000 /* usec */
cc610ac0 173#define ATH9K_TIME_QUANTUM 100 /* usec */
efff395e
FF		 174 int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
175 int wait;
cc610ac0
VT		 176
177 REG_WRITE(ah, AR_Q_TXD, 1 << q);
178
179 for (wait = wait_time; wait != 0; wait--) {
efff395e 180 if (wait != wait_time)
cc610ac0 181 udelay(ATH9K_TIME_QUANTUM);
cc610ac0 182
efff395e
FF		 183 if (ath9k_hw_numtxpending(ah, q) == 0)
184 break;
cc610ac0
VT		 185 }
186
187 REG_WRITE(ah, AR_Q_TXD, 0);
efff395e 188
cc610ac0
VT		 189 return wait != 0;
190
191#undef ATH9K_TX_STOP_DMA_TIMEOUT
192#undef ATH9K_TIME_QUANTUM
193}
efff395e 194EXPORT_SYMBOL(ath9k_hw_stop_dma_queue);
cc610ac0 195
cbe61d8a 196bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
f1dc5600
S		 197 const struct ath9k_tx_queue_info *qinfo)
198{
199 u32 cw;
c46917bb 200 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 201 struct ath9k_tx_queue_info *qi;
202
2660b81a 203 qi = &ah->txq[q];
f1dc5600 204 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
d2182b69 205 ath_dbg(common, QUEUE,
226afe68 206 "Set TXQ properties, inactive queue: %u\n", q);
f1dc5600
S		 207 return false;
208 }
209
d2182b69 210 ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q);
f1dc5600
S		 211
212 qi->tqi_ver = qinfo->tqi_ver;
213 qi->tqi_subtype = qinfo->tqi_subtype;
214 qi->tqi_qflags = qinfo->tqi_qflags;
215 qi->tqi_priority = qinfo->tqi_priority;
216 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
217 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
218 else
219 qi->tqi_aifs = INIT_AIFS;
220 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
221 cw = min(qinfo->tqi_cwmin, 1024U);
222 qi->tqi_cwmin = 1;
223 while (qi->tqi_cwmin < cw)
224 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
225 } else
226 qi->tqi_cwmin = qinfo->tqi_cwmin;
227 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
228 cw = min(qinfo->tqi_cwmax, 1024U);
229 qi->tqi_cwmax = 1;
230 while (qi->tqi_cwmax < cw)
231 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
232 } else
233 qi->tqi_cwmax = INIT_CWMAX;
234
235 if (qinfo->tqi_shretry != 0)
236 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
237 else
238 qi->tqi_shretry = INIT_SH_RETRY;
239 if (qinfo->tqi_lgretry != 0)
240 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
241 else
242 qi->tqi_lgretry = INIT_LG_RETRY;
243 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
244 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
245 qi->tqi_burstTime = qinfo->tqi_burstTime;
246 qi->tqi_readyTime = qinfo->tqi_readyTime;
247
248 switch (qinfo->tqi_subtype) {
249 case ATH9K_WME_UPSD:
250 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
251 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
252 break;
253 default:
254 break;
255 }
256
257 return true;
258}
7322fd19 259EXPORT_SYMBOL(ath9k_hw_set_txq_props);
f1dc5600 260
cbe61d8a 261bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
f1dc5600
S		 262 struct ath9k_tx_queue_info *qinfo)
263{
c46917bb 264 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 265 struct ath9k_tx_queue_info *qi;
266
2660b81a 267 qi = &ah->txq[q];
f1dc5600 268 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
d2182b69 269 ath_dbg(common, QUEUE,
226afe68 270 "Get TXQ properties, inactive queue: %u\n", q);
f1dc5600
S		 271 return false;
272 }
273
274 qinfo->tqi_qflags = qi->tqi_qflags;
275 qinfo->tqi_ver = qi->tqi_ver;
276 qinfo->tqi_subtype = qi->tqi_subtype;
277 qinfo->tqi_qflags = qi->tqi_qflags;
278 qinfo->tqi_priority = qi->tqi_priority;
279 qinfo->tqi_aifs = qi->tqi_aifs;
280 qinfo->tqi_cwmin = qi->tqi_cwmin;
281 qinfo->tqi_cwmax = qi->tqi_cwmax;
282 qinfo->tqi_shretry = qi->tqi_shretry;
283 qinfo->tqi_lgretry = qi->tqi_lgretry;
284 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
285 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
286 qinfo->tqi_burstTime = qi->tqi_burstTime;
287 qinfo->tqi_readyTime = qi->tqi_readyTime;
288
289 return true;
290}
7322fd19 291EXPORT_SYMBOL(ath9k_hw_get_txq_props);
f1dc5600 292
cbe61d8a 293int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
f1dc5600
S		 294 const struct ath9k_tx_queue_info *qinfo)
295{
c46917bb 296 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 297 struct ath9k_tx_queue_info *qi;
f1dc5600
S		 298 int q;
299
300 switch (type) {
301 case ATH9K_TX_QUEUE_BEACON:
f4c607dc 302 q = ATH9K_NUM_TX_QUEUES - 1;
f1dc5600
S		 303 break;
304 case ATH9K_TX_QUEUE_CAB:
f4c607dc 305 q = ATH9K_NUM_TX_QUEUES - 2;
f1dc5600
S		 306 break;
307 case ATH9K_TX_QUEUE_PSPOLL:
308 q = 1;
309 break;
310 case ATH9K_TX_QUEUE_UAPSD:
f4c607dc 311 q = ATH9K_NUM_TX_QUEUES - 3;
f1dc5600
S		 312 break;
313 case ATH9K_TX_QUEUE_DATA:
ad8fdccf 314 q = qinfo->tqi_subtype;
f1dc5600
S		 315 break;
316 default:
3800276a 317 ath_err(common, "Invalid TX queue type: %u\n", type);
f1dc5600
S		 318 return -1;
319 }
320
d2182b69 321 ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q);
f1dc5600 322
2660b81a 323 qi = &ah->txq[q];
f1dc5600 324 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
3800276a 325 ath_err(common, "TX queue: %u already active\n", q);
f1dc5600
S		 326 return -1;
327 }
328 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
329 qi->tqi_type = type;
479c6892
RM		 330 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
331 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
f1dc5600
S		 332
333 return q;
334}
7322fd19 335EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
f1dc5600 336
7e03072e
FF		 337static void ath9k_hw_clear_queue_interrupts(struct ath_hw *ah, u32 q)
338{
339 ah->txok_interrupt_mask &= ~(1 << q);
340 ah->txerr_interrupt_mask &= ~(1 << q);
341 ah->txdesc_interrupt_mask &= ~(1 << q);
342 ah->txeol_interrupt_mask &= ~(1 << q);
343 ah->txurn_interrupt_mask &= ~(1 << q);
344}
345
cbe61d8a 346bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
f1dc5600 347{
c46917bb 348 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 349 struct ath9k_tx_queue_info *qi;
350
2660b81a 351 qi = &ah->txq[q];
f1dc5600 352 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
d2182b69 353 ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q);
f1dc5600
S		 354 return false;
355 }
356
d2182b69 357 ath_dbg(common, QUEUE, "Release TX queue: %u\n", q);
f1dc5600
S		 358
359 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
7e03072e 360 ath9k_hw_clear_queue_interrupts(ah, q);
f1dc5600
S		 361 ath9k_hw_set_txq_interrupts(ah, qi);
362
363 return true;
364}
7322fd19 365EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
f1dc5600 366
cbe61d8a 367bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
f1dc5600 368{
c46917bb 369 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 370 struct ath9k_tx_queue_info *qi;
371 u32 cwMin, chanCwMin, value;
372
2660b81a 373 qi = &ah->txq[q];
f1dc5600 374 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
d2182b69 375 ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q);
f1dc5600
S		 376 return true;
377 }
378
d2182b69 379 ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q);
f1dc5600
S		 380
381 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
1a5e6326 382 chanCwMin = INIT_CWMIN;
f1dc5600
S		 383
384 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
385 } else
386 cwMin = qi->tqi_cwmin;
387
7d0d0df0
S		 388 ENABLE_REGWRITE_BUFFER(ah);
389
f1dc5600
S		 390 REG_WRITE(ah, AR_DLCL_IFS(q),
391 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
392 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
393 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
394
395 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
396 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
397 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
398 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
399
400 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
94333f59 401
86c157b3 402 if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah))
94333f59
RM		 403 REG_WRITE(ah, AR_DMISC(q),
404 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
405 else
406 REG_WRITE(ah, AR_DMISC(q),
407 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
f1dc5600
S		 408
409 if (qi->tqi_cbrPeriod) {
410 REG_WRITE(ah, AR_QCBRCFG(q),
411 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
412 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
ca7a4deb
FF		 413 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
414 (qi->tqi_cbrOverflowLimit ?
415 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
f1dc5600
S		 416 }
417 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
418 REG_WRITE(ah, AR_QRDYTIMECFG(q),
419 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
420 AR_Q_RDYTIMECFG_EN);
421 }
422
423 REG_WRITE(ah, AR_DCHNTIME(q),
424 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
425 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
426
427 if (qi->tqi_burstTime
ca7a4deb
FF		 428 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
429 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
f1dc5600 430
ca7a4deb
FF		 431 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
432 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
7d0d0df0
S		 433
434 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 435
ca7a4deb
FF		 436 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
437 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
438
f1dc5600
S		 439 switch (qi->tqi_type) {
440 case ATH9K_TX_QUEUE_BEACON:
7d0d0df0
S		 441 ENABLE_REGWRITE_BUFFER(ah);
442
ca7a4deb
FF		 443 REG_SET_BIT(ah, AR_QMISC(q),
444 AR_Q_MISC_FSP_DBA_GATED
445 | AR_Q_MISC_BEACON_USE
446 | AR_Q_MISC_CBR_INCR_DIS1);
f1dc5600 447
ca7a4deb
FF		 448 REG_SET_BIT(ah, AR_DMISC(q),
449 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
f1dc5600 450 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
ca7a4deb
FF		 451 | AR_D_MISC_BEACON_USE
452 | AR_D_MISC_POST_FR_BKOFF_DIS);
7d0d0df0
S		 453
454 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 455
9a2af889
LR		 456 /*
457 * cwmin and cwmax should be 0 for beacon queue
458 * but not for IBSS as we would create an imbalance
459 * on beaconing fairness for participating nodes.
460 */
461 if (AR_SREV_9300_20_OR_LATER(ah) &&
462 ah->opmode != NL80211_IFTYPE_ADHOC) {
3deb4da5
LR		 463 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
464 | SM(0, AR_D_LCL_IFS_CWMAX)
465 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
466 }
f1dc5600
S		 467 break;
468 case ATH9K_TX_QUEUE_CAB:
7d0d0df0
S		 469 ENABLE_REGWRITE_BUFFER(ah);
470
ca7a4deb
FF		 471 REG_SET_BIT(ah, AR_QMISC(q),
472 AR_Q_MISC_FSP_DBA_GATED
473 | AR_Q_MISC_CBR_INCR_DIS1
474 | AR_Q_MISC_CBR_INCR_DIS0);
f1dc5600 475 value = (qi->tqi_readyTime -
2660b81a 476 (ah->config.sw_beacon_response_time -
49685634 477 ah->config.dma_beacon_response_time)) * 1024;
f1dc5600
S		 478 REG_WRITE(ah, AR_QRDYTIMECFG(q),
479 value | AR_Q_RDYTIMECFG_EN);
ca7a4deb
FF		 480 REG_SET_BIT(ah, AR_DMISC(q),
481 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
f1dc5600 482 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
7d0d0df0
S		 483
484 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 485
f1dc5600
S		 486 break;
487 case ATH9K_TX_QUEUE_PSPOLL:
ca7a4deb 488 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
f1dc5600
S		 489 break;
490 case ATH9K_TX_QUEUE_UAPSD:
ca7a4deb 491 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
f1dc5600
S		 492 break;
493 default:
494 break;
495 }
496
497 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
ca7a4deb
FF		 498 REG_SET_BIT(ah, AR_DMISC(q),
499 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
500 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
501 AR_D_MISC_POST_FR_BKOFF_DIS);
f1dc5600
S		 502 }
503
79de2375
LR		 504 if (AR_SREV_9300_20_OR_LATER(ah))
505 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
506
7e03072e 507 ath9k_hw_clear_queue_interrupts(ah, q);
ce8fdf6e 508 if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) {
2660b81a 509 ah->txok_interrupt_mask |= 1 << q;
2660b81a 510 ah->txerr_interrupt_mask |= 1 << q;
ce8fdf6e 511 }
f1dc5600 512 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
2660b81a 513 ah->txdesc_interrupt_mask |= 1 << q;
f1dc5600 514 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
2660b81a 515 ah->txeol_interrupt_mask |= 1 << q;
f1dc5600 516 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
2660b81a 517 ah->txurn_interrupt_mask |= 1 << q;
f1dc5600
S		 518 ath9k_hw_set_txq_interrupts(ah, qi);
519
520 return true;
521}
7322fd19 522EXPORT_SYMBOL(ath9k_hw_resettxqueue);
f1dc5600 523
cbe61d8a 524int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
3de21116 525 struct ath_rx_status *rs)
f1dc5600
S		 526{
527 struct ar5416_desc ads;
528 struct ar5416_desc *adsp = AR5416DESC(ds);
529 u32 phyerr;
530
531 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
532 return -EINPROGRESS;
533
534 ads.u.rx = adsp->u.rx;
535
8e6f5aa2
FF		 536 rs->rs_status = 0;
537 rs->rs_flags = 0;
ab276103 538 rs->flag = 0;
f1dc5600 539
8e6f5aa2
FF		 540 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
541 rs->rs_tstamp = ads.AR_RcvTimestamp;
f1dc5600 542
dd8b15b0 543 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
8e6f5aa2 544 rs->rs_rssi = ATH9K_RSSI_BAD;
e45e91d8
FF		 545 rs->rs_rssi_ctl[0] = ATH9K_RSSI_BAD;
546 rs->rs_rssi_ctl[1] = ATH9K_RSSI_BAD;
547 rs->rs_rssi_ctl[2] = ATH9K_RSSI_BAD;
548 rs->rs_rssi_ext[0] = ATH9K_RSSI_BAD;
549 rs->rs_rssi_ext[1] = ATH9K_RSSI_BAD;
550 rs->rs_rssi_ext[2] = ATH9K_RSSI_BAD;
dd8b15b0 551 } else {
8e6f5aa2 552 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
e45e91d8 553 rs->rs_rssi_ctl[0] = MS(ads.ds_rxstatus0,
dd8b15b0 554 AR_RxRSSIAnt00);
e45e91d8 555 rs->rs_rssi_ctl[1] = MS(ads.ds_rxstatus0,
dd8b15b0 556 AR_RxRSSIAnt01);
e45e91d8 557 rs->rs_rssi_ctl[2] = MS(ads.ds_rxstatus0,
dd8b15b0 558 AR_RxRSSIAnt02);
e45e91d8 559 rs->rs_rssi_ext[0] = MS(ads.ds_rxstatus4,
dd8b15b0 560 AR_RxRSSIAnt10);
e45e91d8 561 rs->rs_rssi_ext[1] = MS(ads.ds_rxstatus4,
dd8b15b0 562 AR_RxRSSIAnt11);
e45e91d8 563 rs->rs_rssi_ext[2] = MS(ads.ds_rxstatus4,
dd8b15b0
SB		 564 AR_RxRSSIAnt12);
565 }
f1dc5600 566 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
8e6f5aa2 567 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
f1dc5600 568 else
8e6f5aa2 569 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
f1dc5600 570
1b8714f7 571 rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate);
8e6f5aa2 572 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
f1dc5600 573
009af8fb 574 rs->rs_firstaggr = (ads.ds_rxstatus8 & AR_RxFirstAggr) ? 1 : 0;
8e6f5aa2 575 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
009af8fb 576 rs->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
8e6f5aa2 577 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
ab276103
OR		 578
579 /* directly mapped flags for ieee80211_rx_status */
580 rs->flag |=
581 (ads.ds_rxstatus3 & AR_GI) ? RX_FLAG_SHORT_GI : 0;
582 rs->flag |=
583 (ads.ds_rxstatus3 & AR_2040) ? RX_FLAG_40MHZ : 0;
b0a1ae97
OR		 584 if (AR_SREV_9280_20_OR_LATER(ah))
585 rs->flag |=
586 (ads.ds_rxstatus3 & AR_STBC) ?
587 /* we can only Nss=1 STBC */
588 (1 << RX_FLAG_STBC_SHIFT) : 0;
f1dc5600
S		 589
590 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
8e6f5aa2 591 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
f1dc5600 592 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
8e6f5aa2 593 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
f1dc5600 594 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
8e6f5aa2 595 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
f1dc5600
S		 596
597 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
115dad7a
FF		 598 /*
599 * Treat these errors as mutually exclusive to avoid spurious
600 * extra error reports from the hardware. If a CRC error is
601 * reported, then decryption and MIC errors are irrelevant,
602 * the frame is going to be dropped either way
603 */
3a325565 604 if (ads.ds_rxstatus8 & AR_PHYErr) {
8e6f5aa2 605 rs->rs_status |= ATH9K_RXERR_PHY;
f1dc5600 606 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
8e6f5aa2 607 rs->rs_phyerr = phyerr;
3a325565
SW		 608 } else if (ads.ds_rxstatus8 & AR_CRCErr)
609 rs->rs_status |= ATH9K_RXERR_CRC;
610 else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
8e6f5aa2 611 rs->rs_status |= ATH9K_RXERR_DECRYPT;
115dad7a 612 else if (ads.ds_rxstatus8 & AR_MichaelErr)
8e6f5aa2 613 rs->rs_status |= ATH9K_RXERR_MIC;
3747c3ee
FF		 614 } else {
615 if (ads.ds_rxstatus8 &
616 (AR_CRCErr | AR_PHYErr | AR_DecryptCRCErr | AR_MichaelErr))
617 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC;
618
619 /* Only up to MCS16 supported, everything above is invalid */
620 if (rs->rs_rate >= 0x90)
621 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC;
f1dc5600
S		 622 }
623
7a532fe7
FF		 624 if (ads.ds_rxstatus8 & AR_KeyMiss)
625 rs->rs_status |= ATH9K_RXERR_KEYMISS;
626
f1dc5600
S		 627 return 0;
628}
7322fd19 629EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
f1dc5600 630
e7824a50
LR		 631/*
632 * This can stop or re-enables RX.
633 *
634 * If bool is set this will kill any frame which is currently being
635 * transferred between the MAC and baseband and also prevent any new
636 * frames from getting started.
637 */
cbe61d8a 638bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
f1dc5600
S		 639{
640 u32 reg;
641
642 if (set) {
643 REG_SET_BIT(ah, AR_DIAG_SW,
644 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
645
0caa7b14
S		 646 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
647 0, AH_WAIT_TIMEOUT)) {
f1dc5600
S		 648 REG_CLR_BIT(ah, AR_DIAG_SW,
649 (AR_DIAG_RX_DIS |
650 AR_DIAG_RX_ABORT));
651
652 reg = REG_READ(ah, AR_OBS_BUS_1);
3800276a
JP		 653 ath_err(ath9k_hw_common(ah),
654 "RX failed to go idle in 10 ms RXSM=0x%x\n",
655 reg);
f1dc5600
S		 656
657 return false;
658 }
659 } else {
660 REG_CLR_BIT(ah, AR_DIAG_SW,
661 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
662 }
663
664 return true;
665}
7322fd19 666EXPORT_SYMBOL(ath9k_hw_setrxabort);
f1dc5600 667
cbe61d8a 668void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
f1dc5600
S		 669{
670 REG_WRITE(ah, AR_RXDP, rxdp);
671}
7322fd19 672EXPORT_SYMBOL(ath9k_hw_putrxbuf);
f1dc5600 673
40346b66 674void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
f1dc5600 675{
f1dc5600
S		 676 ath9k_enable_mib_counters(ah);
677
40346b66 678 ath9k_ani_reset(ah, is_scanning);
e7594072 679
8aa15e15 680 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
f1dc5600 681}
7322fd19 682EXPORT_SYMBOL(ath9k_hw_startpcureceive);
f1dc5600 683
9b9cc61c
VT		 684void ath9k_hw_abortpcurecv(struct ath_hw *ah)
685{
686 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
687
688 ath9k_hw_disable_mib_counters(ah);
689}
690EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
691
5882da02 692bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset)
f1dc5600 693{
0caa7b14 694#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
c46917bb 695 struct ath_common *common = ath9k_hw_common(ah);
5882da02 696 u32 mac_status, last_mac_status = 0;
0caa7b14
S		 697 int i;
698
5882da02
FF		 699 /* Enable access to the DMA observation bus */
700 REG_WRITE(ah, AR_MACMISC,
701 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
702 (AR_MACMISC_MISC_OBS_BUS_1 <<
703 AR_MACMISC_MISC_OBS_BUS_MSB_S)));
704
f1dc5600
S		 705 REG_WRITE(ah, AR_CR, AR_CR_RXD);
706
0caa7b14
S		 707 /* Wait for rx enable bit to go low */
708 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
709 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
710 break;
5882da02
FF		 711
712 if (!AR_SREV_9300_20_OR_LATER(ah)) {
713 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
714 if (mac_status == 0x1c0 && mac_status == last_mac_status) {
715 *reset = true;
716 break;
717 }
718
719 last_mac_status = mac_status;
720 }
721
0caa7b14
S		 722 udelay(AH_TIME_QUANTUM);
723 }
724
725 if (i == 0) {
3800276a 726 ath_err(common,
5882da02 727 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
3800276a
JP		 728 AH_RX_STOP_DMA_TIMEOUT / 1000,
729 REG_READ(ah, AR_CR),
5882da02
FF		 730 REG_READ(ah, AR_DIAG_SW),
731 REG_READ(ah, AR_DMADBG_7));
f1dc5600
S		 732 return false;
733 } else {
734 return true;
735 }
0caa7b14 736
0caa7b14 737#undef AH_RX_STOP_DMA_TIMEOUT
f1dc5600 738}
7322fd19 739EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
536b3a7a
LR		 740
741int ath9k_hw_beaconq_setup(struct ath_hw *ah)
742{
743 struct ath9k_tx_queue_info qi;
744
745 memset(&qi, 0, sizeof(qi));
746 qi.tqi_aifs = 1;
747 qi.tqi_cwmin = 0;
748 qi.tqi_cwmax = 0;
627e67a6
FF		 749
750 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
ce8fdf6e 751 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
627e67a6 752
536b3a7a
LR		 753 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
754}
755EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
55e82df4
VT		 756
757bool ath9k_hw_intrpend(struct ath_hw *ah)
758{
759 u32 host_isr;
760
761 if (AR_SREV_9100(ah))
762 return true;
763
764 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
e3584813
MSS		 765
766 if (((host_isr & AR_INTR_MAC_IRQ) ||
767 (host_isr & AR_INTR_ASYNC_MASK_MCI)) &&
768 (host_isr != AR_INTR_SPURIOUS))
55e82df4
VT		 769 return true;
770
771 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
772 if ((host_isr & AR_INTR_SYNC_DEFAULT)
773 && (host_isr != AR_INTR_SPURIOUS))
774 return true;
775
776 return false;
777}
778EXPORT_SYMBOL(ath9k_hw_intrpend);
779
f41a9b3b 780void ath9k_hw_kill_interrupts(struct ath_hw *ah)
4df3071e
FF		 781{
782 struct ath_common *common = ath9k_hw_common(ah);
783
d2182b69 784 ath_dbg(common, INTERRUPT, "disable IER\n");
4df3071e
FF		 785 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
786 (void) REG_READ(ah, AR_IER);
787 if (!AR_SREV_9100(ah)) {
788 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
789 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
790
791 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
792 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
793 }
794}
f41a9b3b
FF		 795EXPORT_SYMBOL(ath9k_hw_kill_interrupts);
796
797void ath9k_hw_disable_interrupts(struct ath_hw *ah)
798{
799 if (!(ah->imask & ATH9K_INT_GLOBAL))
800 atomic_set(&ah->intr_ref_cnt, -1);
801 else
802 atomic_dec(&ah->intr_ref_cnt);
803
804 ath9k_hw_kill_interrupts(ah);
805}
4df3071e
FF		 806EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
807
808void ath9k_hw_enable_interrupts(struct ath_hw *ah)
809{
810 struct ath_common *common = ath9k_hw_common(ah);
79d1d2b8 811 u32 sync_default = AR_INTR_SYNC_DEFAULT;
f229f815 812 u32 async_mask;
4df3071e
FF		 813
814 if (!(ah->imask & ATH9K_INT_GLOBAL))
815 return;
816
e8fe7336 817 if (!atomic_inc_and_test(&ah->intr_ref_cnt)) {
d2182b69 818 ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n",
e8fe7336
RM		 819 atomic_read(&ah->intr_ref_cnt));
820 return;
821 }
822
ede6a5e7
MP		 823 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
824 AR_SREV_9561(ah))
79d1d2b8
VT		 825 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
826
f229f815
MSS		 827 async_mask = AR_INTR_MAC_IRQ;
828
829 if (ah->imask & ATH9K_INT_MCI)
830 async_mask |= AR_INTR_ASYNC_MASK_MCI;
831
d2182b69 832 ath_dbg(common, INTERRUPT, "enable IER\n");
4df3071e
FF		 833 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
834 if (!AR_SREV_9100(ah)) {
f229f815
MSS		 835 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask);
836 REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask);
4df3071e 837
79d1d2b8
VT		 838 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
839 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
4df3071e 840 }
d2182b69 841 ath_dbg(common, INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
226afe68 842 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
4df3071e
FF		 843}
844EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
845
72d874c6 846void ath9k_hw_set_interrupts(struct ath_hw *ah)
55e82df4 847{
72d874c6 848 enum ath9k_int ints = ah->imask;
55e82df4
VT		 849 u32 mask, mask2;
850 struct ath9k_hw_capabilities *pCap = &ah->caps;
851 struct ath_common *common = ath9k_hw_common(ah);
852
4df3071e 853 if (!(ints & ATH9K_INT_GLOBAL))
385918cc 854 ath9k_hw_disable_interrupts(ah);
55e82df4 855
d2182b69 856 ath_dbg(common, INTERRUPT, "New interrupt mask 0x%x\n", ints);
55e82df4 857
55e82df4
VT		 858 mask = ints & ATH9K_INT_COMMON;
859 mask2 = 0;
860
861 if (ints & ATH9K_INT_TX) {
862 if (ah->config.tx_intr_mitigation)
863 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
5bea4006
LR		 864 else {
865 if (ah->txok_interrupt_mask)
866 mask |= AR_IMR_TXOK;
867 if (ah->txdesc_interrupt_mask)
868 mask |= AR_IMR_TXDESC;
869 }
55e82df4
VT		 870 if (ah->txerr_interrupt_mask)
871 mask |= AR_IMR_TXERR;
872 if (ah->txeol_interrupt_mask)
873 mask |= AR_IMR_TXEOL;
874 }
875 if (ints & ATH9K_INT_RX) {
876 if (AR_SREV_9300_20_OR_LATER(ah)) {
877 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
878 if (ah->config.rx_intr_mitigation) {
879 mask &= ~AR_IMR_RXOK_LP;
880 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
881 } else {
882 mask |= AR_IMR_RXOK_LP;
883 }
884 } else {
885 if (ah->config.rx_intr_mitigation)
886 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
887 else
888 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
889 }
890 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
891 mask |= AR_IMR_GENTMR;
892 }
893
f78eb657
VN		 894 if (ints & ATH9K_INT_GENTIMER)
895 mask |= AR_IMR_GENTMR;
896
55e82df4
VT		 897 if (ints & (ATH9K_INT_BMISC)) {
898 mask |= AR_IMR_BCNMISC;
899 if (ints & ATH9K_INT_TIM)
900 mask2 |= AR_IMR_S2_TIM;
901 if (ints & ATH9K_INT_DTIM)
902 mask2 |= AR_IMR_S2_DTIM;
903 if (ints & ATH9K_INT_DTIMSYNC)
904 mask2 |= AR_IMR_S2_DTIMSYNC;
905 if (ints & ATH9K_INT_CABEND)
906 mask2 |= AR_IMR_S2_CABEND;
907 if (ints & ATH9K_INT_TSFOOR)
908 mask2 |= AR_IMR_S2_TSFOOR;
909 }
910
911 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
912 mask |= AR_IMR_BCNMISC;
913 if (ints & ATH9K_INT_GTT)
914 mask2 |= AR_IMR_S2_GTT;
915 if (ints & ATH9K_INT_CST)
916 mask2 |= AR_IMR_S2_CST;
917 }
918
a6bb860b
SM		 919 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) {
920 if (ints & ATH9K_INT_BB_WATCHDOG) {
921 mask |= AR_IMR_BCNMISC;
922 mask2 |= AR_IMR_S2_BB_WATCHDOG;
923 }
924 }
925
d2182b69 926 ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask);
55e82df4 927 REG_WRITE(ah, AR_IMR, mask);
a6bb860b
SM		 928 ah->imrs2_reg &= ~(AR_IMR_S2_TIM |
929 AR_IMR_S2_DTIM |
930 AR_IMR_S2_DTIMSYNC |
931 AR_IMR_S2_CABEND |
932 AR_IMR_S2_CABTO |
933 AR_IMR_S2_TSFOOR |
934 AR_IMR_S2_GTT |
935 AR_IMR_S2_CST);
936
937 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) {
938 if (ints & ATH9K_INT_BB_WATCHDOG)
939 ah->imrs2_reg &= ~AR_IMR_S2_BB_WATCHDOG;
940 }
941
55e82df4
VT		 942 ah->imrs2_reg |= mask2;
943 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
944
945 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
946 if (ints & ATH9K_INT_TIM_TIMER)
947 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
948 else
949 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
950 }
951
4df3071e 952 return;
55e82df4
VT		 953}
954EXPORT_SYMBOL(ath9k_hw_set_interrupts);
08232bf9
RM		 955
956#define ATH9K_HW_MAX_DCU 10
957#define ATH9K_HW_SLICE_PER_DCU 16
958#define ATH9K_HW_BIT_IN_SLICE 16
959void ath9k_hw_set_tx_filter(struct ath_hw *ah, u8 destidx, bool set)
960{
961 int dcu_idx;
962 u32 filter;
963
964 for (dcu_idx = 0; dcu_idx < 10; dcu_idx++) {
965 filter = SM(set, AR_D_TXBLK_WRITE_COMMAND);
966 filter |= SM(dcu_idx, AR_D_TXBLK_WRITE_DCU);
967 filter |= SM((destidx / ATH9K_HW_SLICE_PER_DCU),
968 AR_D_TXBLK_WRITE_SLICE);
969 filter |= BIT(destidx % ATH9K_HW_BIT_IN_SLICE);
970 ath_dbg(ath9k_hw_common(ah), PS,
971 "DCU%d staid %d set %d txfilter %08x\n",
972 dcu_idx, destidx, set, filter);
973 REG_WRITE(ah, AR_D_TXBLK_BASE, filter);
974 }
975}
976EXPORT_SYMBOL(ath9k_hw_set_tx_filter);
Linux kernel - Deliverables
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