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ath9k: Add more information to debugfs xmit file.
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / mac.c
CommitLineData
f1dc5600 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f1dc5600
S		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
990b70ab 17#include "hw.h"
ac0bb767 18#include "hw-ops.h"
2dac4fb9
BG		 19#include "debug.h"
20#include "ath9k.h"
f1dc5600 21
cc610ac0
VT		 22static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
23 struct ath9k_tx_queue_info *qi)
24{
226afe68
JP		 25 ath_dbg(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
26 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
27 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
28 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
29 ah->txurn_interrupt_mask);
cc610ac0 30
7d0d0df0
S		 31 ENABLE_REGWRITE_BUFFER(ah);
32
cc610ac0
VT		 33 REG_WRITE(ah, AR_IMR_S0,
34 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
35 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
36 REG_WRITE(ah, AR_IMR_S1,
37 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
38 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
39
40 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
41 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
42 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
7d0d0df0
S		 43
44 REGWRITE_BUFFER_FLUSH(ah);
cc610ac0
VT		 45}
46
47u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
48{
49 return REG_READ(ah, AR_QTXDP(q));
50}
51EXPORT_SYMBOL(ath9k_hw_gettxbuf);
52
53void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
54{
2dac4fb9
BG		 55 struct ath_wiphy *aphy = ah->hw->priv;
56 struct ath_softc *sc = aphy->sc;
57 TX_STAT_INC(q, puttxbuf);
cc610ac0
VT		 58 REG_WRITE(ah, AR_QTXDP(q), txdp);
59}
60EXPORT_SYMBOL(ath9k_hw_puttxbuf);
61
62void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
63{
2dac4fb9
BG		 64 struct ath_wiphy *aphy = ah->hw->priv;
65 struct ath_softc *sc = aphy->sc;
66 TX_STAT_INC(q, txstart);
226afe68
JP		 67 ath_dbg(ath9k_hw_common(ah), ATH_DBG_QUEUE,
68 "Enable TXE on queue: %u\n", q);
cc610ac0
VT		 69 REG_WRITE(ah, AR_Q_TXE, 1 << q);
70}
71EXPORT_SYMBOL(ath9k_hw_txstart);
72
73void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
74{
75 struct ar5416_desc *ads = AR5416DESC(ds);
76
77 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
78 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
79 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
80 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
81 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
82}
83EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
84
85u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
86{
87 u32 npend;
88
89 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
90 if (npend == 0) {
91
92 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
93 npend = 1;
94 }
95
96 return npend;
97}
98EXPORT_SYMBOL(ath9k_hw_numtxpending);
99
100/**
101 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
102 *
103 * @ah: atheros hardware struct
104 * @bIncTrigLevel: whether or not the frame trigger level should be updated
105 *
106 * The frame trigger level specifies the minimum number of bytes,
107 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
108 * before the PCU will initiate sending the frame on the air. This can
109 * mean we initiate transmit before a full frame is on the PCU TX FIFO.
110 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
111 * first)
112 *
113 * Caution must be taken to ensure to set the frame trigger level based
114 * on the DMA request size. For example if the DMA request size is set to
115 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
116 * there need to be enough space in the tx FIFO for the requested transfer
117 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
118 * the threshold to a value beyond 6, then the transmit will hang.
119 *
120 * Current dual stream devices have a PCU TX FIFO size of 8 KB.
121 * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
122 * there is a hardware issue which forces us to use 2 KB instead so the
123 * frame trigger level must not exceed 2 KB for these chipsets.
124 */
125bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
126{
127 u32 txcfg, curLevel, newLevel;
cc610ac0
VT		 128
129 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
130 return false;
131
4df3071e 132 ath9k_hw_disable_interrupts(ah);
cc610ac0
VT		 133
134 txcfg = REG_READ(ah, AR_TXCFG);
135 curLevel = MS(txcfg, AR_FTRIG);
136 newLevel = curLevel;
137 if (bIncTrigLevel) {
138 if (curLevel < ah->config.max_txtrig_level)
139 newLevel++;
140 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
141 newLevel--;
142 if (newLevel != curLevel)
143 REG_WRITE(ah, AR_TXCFG,
144 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
145
4df3071e 146 ath9k_hw_enable_interrupts(ah);
cc610ac0
VT		 147
148 ah->tx_trig_level = newLevel;
149
150 return newLevel != curLevel;
151}
152EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
153
154bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
155{
156#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
157#define ATH9K_TIME_QUANTUM 100 /* usec */
158 struct ath_common *common = ath9k_hw_common(ah);
159 struct ath9k_hw_capabilities *pCap = &ah->caps;
160 struct ath9k_tx_queue_info *qi;
161 u32 tsfLow, j, wait;
162 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
163
164 if (q >= pCap->total_queues) {
226afe68
JP		 165 ath_dbg(common, ATH_DBG_QUEUE,
166 "Stopping TX DMA, invalid queue: %u\n", q);
cc610ac0
VT		 167 return false;
168 }
169
170 qi = &ah->txq[q];
171 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
226afe68
JP		 172 ath_dbg(common, ATH_DBG_QUEUE,
173 "Stopping TX DMA, inactive queue: %u\n", q);
cc610ac0
VT		 174 return false;
175 }
176
177 REG_WRITE(ah, AR_Q_TXD, 1 << q);
178
179 for (wait = wait_time; wait != 0; wait--) {
180 if (ath9k_hw_numtxpending(ah, q) == 0)
181 break;
182 udelay(ATH9K_TIME_QUANTUM);
183 }
184
185 if (ath9k_hw_numtxpending(ah, q)) {
226afe68
JP		 186 ath_dbg(common, ATH_DBG_QUEUE,
187 "%s: Num of pending TX Frames %d on Q %d\n",
188 __func__, ath9k_hw_numtxpending(ah, q), q);
cc610ac0
VT		 189
190 for (j = 0; j < 2; j++) {
191 tsfLow = REG_READ(ah, AR_TSF_L32);
192 REG_WRITE(ah, AR_QUIET2,
193 SM(10, AR_QUIET2_QUIET_DUR));
194 REG_WRITE(ah, AR_QUIET_PERIOD, 100);
195 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
196 REG_SET_BIT(ah, AR_TIMER_MODE,
197 AR_QUIET_TIMER_EN);
198
199 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
200 break;
201
226afe68
JP		 202 ath_dbg(common, ATH_DBG_QUEUE,
203 "TSF has moved while trying to set quiet time TSF: 0x%08x\n",
204 tsfLow);
cc610ac0
VT		 205 }
206
207 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
208
209 udelay(200);
210 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
211
212 wait = wait_time;
213 while (ath9k_hw_numtxpending(ah, q)) {
214 if ((--wait) == 0) {
3800276a
JP		 215 ath_err(common,
216 "Failed to stop TX DMA in 100 msec after killing last frame\n");
cc610ac0
VT		 217 break;
218 }
219 udelay(ATH9K_TIME_QUANTUM);
220 }
221
222 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
223 }
224
225 REG_WRITE(ah, AR_Q_TXD, 0);
226 return wait != 0;
227
228#undef ATH9K_TX_STOP_DMA_TIMEOUT
229#undef ATH9K_TIME_QUANTUM
230}
231EXPORT_SYMBOL(ath9k_hw_stoptxdma);
232
cbe61d8a 233void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
f1dc5600 234{
2660b81a
S		 235 *txqs &= ah->intr_txqs;
236 ah->intr_txqs &= ~(*txqs);
f1dc5600 237}
7322fd19 238EXPORT_SYMBOL(ath9k_hw_gettxintrtxqs);
f1dc5600 239
cbe61d8a 240bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
f1dc5600
S		 241 const struct ath9k_tx_queue_info *qinfo)
242{
243 u32 cw;
c46917bb 244 struct ath_common *common = ath9k_hw_common(ah);
2660b81a 245 struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600
S		 246 struct ath9k_tx_queue_info *qi;
247
248 if (q >= pCap->total_queues) {
226afe68
JP		 249 ath_dbg(common, ATH_DBG_QUEUE,
250 "Set TXQ properties, invalid queue: %u\n", q);
f1dc5600
S		 251 return false;
252 }
253
2660b81a 254 qi = &ah->txq[q];
f1dc5600 255 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
226afe68
JP		 256 ath_dbg(common, ATH_DBG_QUEUE,
257 "Set TXQ properties, inactive queue: %u\n", q);
f1dc5600
S		 258 return false;
259 }
260
226afe68 261 ath_dbg(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
f1dc5600
S		 262
263 qi->tqi_ver = qinfo->tqi_ver;
264 qi->tqi_subtype = qinfo->tqi_subtype;
265 qi->tqi_qflags = qinfo->tqi_qflags;
266 qi->tqi_priority = qinfo->tqi_priority;
267 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
268 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
269 else
270 qi->tqi_aifs = INIT_AIFS;
271 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
272 cw = min(qinfo->tqi_cwmin, 1024U);
273 qi->tqi_cwmin = 1;
274 while (qi->tqi_cwmin < cw)
275 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
276 } else
277 qi->tqi_cwmin = qinfo->tqi_cwmin;
278 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
279 cw = min(qinfo->tqi_cwmax, 1024U);
280 qi->tqi_cwmax = 1;
281 while (qi->tqi_cwmax < cw)
282 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
283 } else
284 qi->tqi_cwmax = INIT_CWMAX;
285
286 if (qinfo->tqi_shretry != 0)
287 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
288 else
289 qi->tqi_shretry = INIT_SH_RETRY;
290 if (qinfo->tqi_lgretry != 0)
291 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
292 else
293 qi->tqi_lgretry = INIT_LG_RETRY;
294 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
295 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
296 qi->tqi_burstTime = qinfo->tqi_burstTime;
297 qi->tqi_readyTime = qinfo->tqi_readyTime;
298
299 switch (qinfo->tqi_subtype) {
300 case ATH9K_WME_UPSD:
301 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
302 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
303 break;
304 default:
305 break;
306 }
307
308 return true;
309}
7322fd19 310EXPORT_SYMBOL(ath9k_hw_set_txq_props);
f1dc5600 311
cbe61d8a 312bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
f1dc5600
S		 313 struct ath9k_tx_queue_info *qinfo)
314{
c46917bb 315 struct ath_common *common = ath9k_hw_common(ah);
2660b81a 316 struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600
S		 317 struct ath9k_tx_queue_info *qi;
318
319 if (q >= pCap->total_queues) {
226afe68
JP		 320 ath_dbg(common, ATH_DBG_QUEUE,
321 "Get TXQ properties, invalid queue: %u\n", q);
f1dc5600
S		 322 return false;
323 }
324
2660b81a 325 qi = &ah->txq[q];
f1dc5600 326 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
226afe68
JP		 327 ath_dbg(common, ATH_DBG_QUEUE,
328 "Get TXQ properties, inactive queue: %u\n", q);
f1dc5600
S		 329 return false;
330 }
331
332 qinfo->tqi_qflags = qi->tqi_qflags;
333 qinfo->tqi_ver = qi->tqi_ver;
334 qinfo->tqi_subtype = qi->tqi_subtype;
335 qinfo->tqi_qflags = qi->tqi_qflags;
336 qinfo->tqi_priority = qi->tqi_priority;
337 qinfo->tqi_aifs = qi->tqi_aifs;
338 qinfo->tqi_cwmin = qi->tqi_cwmin;
339 qinfo->tqi_cwmax = qi->tqi_cwmax;
340 qinfo->tqi_shretry = qi->tqi_shretry;
341 qinfo->tqi_lgretry = qi->tqi_lgretry;
342 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
343 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
344 qinfo->tqi_burstTime = qi->tqi_burstTime;
345 qinfo->tqi_readyTime = qi->tqi_readyTime;
346
347 return true;
348}
7322fd19 349EXPORT_SYMBOL(ath9k_hw_get_txq_props);
f1dc5600 350
cbe61d8a 351int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
f1dc5600
S		 352 const struct ath9k_tx_queue_info *qinfo)
353{
c46917bb 354 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 355 struct ath9k_tx_queue_info *qi;
2660b81a 356 struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600
S		 357 int q;
358
359 switch (type) {
360 case ATH9K_TX_QUEUE_BEACON:
361 q = pCap->total_queues - 1;
362 break;
363 case ATH9K_TX_QUEUE_CAB:
364 q = pCap->total_queues - 2;
365 break;
366 case ATH9K_TX_QUEUE_PSPOLL:
367 q = 1;
368 break;
369 case ATH9K_TX_QUEUE_UAPSD:
370 q = pCap->total_queues - 3;
371 break;
372 case ATH9K_TX_QUEUE_DATA:
373 for (q = 0; q < pCap->total_queues; q++)
2660b81a 374 if (ah->txq[q].tqi_type ==
f1dc5600
S		 375 ATH9K_TX_QUEUE_INACTIVE)
376 break;
377 if (q == pCap->total_queues) {
3800276a 378 ath_err(common, "No available TX queue\n");
f1dc5600
S		 379 return -1;
380 }
381 break;
382 default:
3800276a 383 ath_err(common, "Invalid TX queue type: %u\n", type);
f1dc5600
S		 384 return -1;
385 }
386
226afe68 387 ath_dbg(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
f1dc5600 388
2660b81a 389 qi = &ah->txq[q];
f1dc5600 390 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
3800276a 391 ath_err(common, "TX queue: %u already active\n", q);
f1dc5600
S		 392 return -1;
393 }
394 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
395 qi->tqi_type = type;
396 if (qinfo == NULL) {
397 qi->tqi_qflags =
398 TXQ_FLAG_TXOKINT_ENABLE
399 | TXQ_FLAG_TXERRINT_ENABLE
400 | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
401 qi->tqi_aifs = INIT_AIFS;
402 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
403 qi->tqi_cwmax = INIT_CWMAX;
404 qi->tqi_shretry = INIT_SH_RETRY;
405 qi->tqi_lgretry = INIT_LG_RETRY;
406 qi->tqi_physCompBuf = 0;
407 } else {
408 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
409 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
410 }
411
412 return q;
413}
7322fd19 414EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
f1dc5600 415
cbe61d8a 416bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
f1dc5600 417{
2660b81a 418 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 419 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 420 struct ath9k_tx_queue_info *qi;
421
422 if (q >= pCap->total_queues) {
226afe68
JP		 423 ath_dbg(common, ATH_DBG_QUEUE,
424 "Release TXQ, invalid queue: %u\n", q);
f1dc5600
S		 425 return false;
426 }
2660b81a 427 qi = &ah->txq[q];
f1dc5600 428 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
226afe68
JP		 429 ath_dbg(common, ATH_DBG_QUEUE,
430 "Release TXQ, inactive queue: %u\n", q);
f1dc5600
S		 431 return false;
432 }
433
226afe68 434 ath_dbg(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
f1dc5600
S		 435
436 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
2660b81a
S		 437 ah->txok_interrupt_mask &= ~(1 << q);
438 ah->txerr_interrupt_mask &= ~(1 << q);
439 ah->txdesc_interrupt_mask &= ~(1 << q);
440 ah->txeol_interrupt_mask &= ~(1 << q);
441 ah->txurn_interrupt_mask &= ~(1 << q);
f1dc5600
S		 442 ath9k_hw_set_txq_interrupts(ah, qi);
443
444 return true;
445}
7322fd19 446EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
f1dc5600 447
cbe61d8a 448bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
f1dc5600 449{
2660b81a 450 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 451 struct ath_common *common = ath9k_hw_common(ah);
2660b81a 452 struct ath9k_channel *chan = ah->curchan;
f1dc5600
S		 453 struct ath9k_tx_queue_info *qi;
454 u32 cwMin, chanCwMin, value;
455
456 if (q >= pCap->total_queues) {
226afe68
JP		 457 ath_dbg(common, ATH_DBG_QUEUE,
458 "Reset TXQ, invalid queue: %u\n", q);
f1dc5600
S		 459 return false;
460 }
461
2660b81a 462 qi = &ah->txq[q];
f1dc5600 463 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
226afe68
JP		 464 ath_dbg(common, ATH_DBG_QUEUE,
465 "Reset TXQ, inactive queue: %u\n", q);
f1dc5600
S		 466 return true;
467 }
468
226afe68 469 ath_dbg(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
f1dc5600
S		 470
471 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
472 if (chan && IS_CHAN_B(chan))
473 chanCwMin = INIT_CWMIN_11B;
474 else
475 chanCwMin = INIT_CWMIN;
476
477 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
478 } else
479 cwMin = qi->tqi_cwmin;
480
7d0d0df0
S		 481 ENABLE_REGWRITE_BUFFER(ah);
482
f1dc5600
S		 483 REG_WRITE(ah, AR_DLCL_IFS(q),
484 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
485 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
486 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
487
488 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
489 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
490 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
491 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
492
493 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
494 REG_WRITE(ah, AR_DMISC(q),
495 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
496
497 if (qi->tqi_cbrPeriod) {
498 REG_WRITE(ah, AR_QCBRCFG(q),
499 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
500 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
501 REG_WRITE(ah, AR_QMISC(q),
502 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
503 (qi->tqi_cbrOverflowLimit ?
504 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
505 }
506 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
507 REG_WRITE(ah, AR_QRDYTIMECFG(q),
508 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
509 AR_Q_RDYTIMECFG_EN);
510 }
511
512 REG_WRITE(ah, AR_DCHNTIME(q),
513 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
514 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
515
516 if (qi->tqi_burstTime
517 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
518 REG_WRITE(ah, AR_QMISC(q),
519 REG_READ(ah, AR_QMISC(q)) |
520 AR_Q_MISC_RDYTIME_EXP_POLICY);
521
522 }
523
524 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
525 REG_WRITE(ah, AR_DMISC(q),
526 REG_READ(ah, AR_DMISC(q)) |
527 AR_D_MISC_POST_FR_BKOFF_DIS);
528 }
7d0d0df0
S		 529
530 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 531
f1dc5600
S		 532 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
533 REG_WRITE(ah, AR_DMISC(q),
534 REG_READ(ah, AR_DMISC(q)) |
535 AR_D_MISC_FRAG_BKOFF_EN);
536 }
537 switch (qi->tqi_type) {
538 case ATH9K_TX_QUEUE_BEACON:
7d0d0df0
S		 539 ENABLE_REGWRITE_BUFFER(ah);
540
f1dc5600
S		 541 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
542 | AR_Q_MISC_FSP_DBA_GATED
543 | AR_Q_MISC_BEACON_USE
544 | AR_Q_MISC_CBR_INCR_DIS1);
545
546 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
547 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
548 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
549 | AR_D_MISC_BEACON_USE
550 | AR_D_MISC_POST_FR_BKOFF_DIS);
7d0d0df0
S		 551
552 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 553
9a2af889
LR		 554 /*
555 * cwmin and cwmax should be 0 for beacon queue
556 * but not for IBSS as we would create an imbalance
557 * on beaconing fairness for participating nodes.
558 */
559 if (AR_SREV_9300_20_OR_LATER(ah) &&
560 ah->opmode != NL80211_IFTYPE_ADHOC) {
3deb4da5
LR		 561 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
562 | SM(0, AR_D_LCL_IFS_CWMAX)
563 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
564 }
f1dc5600
S		 565 break;
566 case ATH9K_TX_QUEUE_CAB:
7d0d0df0
S		 567 ENABLE_REGWRITE_BUFFER(ah);
568
f1dc5600
S		 569 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
570 | AR_Q_MISC_FSP_DBA_GATED
571 | AR_Q_MISC_CBR_INCR_DIS1
572 | AR_Q_MISC_CBR_INCR_DIS0);
573 value = (qi->tqi_readyTime -
2660b81a
S		 574 (ah->config.sw_beacon_response_time -
575 ah->config.dma_beacon_response_time) -
576 ah->config.additional_swba_backoff) * 1024;
f1dc5600
S		 577 REG_WRITE(ah, AR_QRDYTIMECFG(q),
578 value | AR_Q_RDYTIMECFG_EN);
579 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
580 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
581 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
7d0d0df0
S		 582
583 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 584
f1dc5600
S		 585 break;
586 case ATH9K_TX_QUEUE_PSPOLL:
587 REG_WRITE(ah, AR_QMISC(q),
588 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
589 break;
590 case ATH9K_TX_QUEUE_UAPSD:
591 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
592 AR_D_MISC_POST_FR_BKOFF_DIS);
593 break;
594 default:
595 break;
596 }
597
598 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
599 REG_WRITE(ah, AR_DMISC(q),
600 REG_READ(ah, AR_DMISC(q)) |
601 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
602 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
603 AR_D_MISC_POST_FR_BKOFF_DIS);
604 }
605
79de2375
LR		 606 if (AR_SREV_9300_20_OR_LATER(ah))
607 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
608
f1dc5600 609 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
2660b81a 610 ah->txok_interrupt_mask |= 1 << q;
f1dc5600 611 else
2660b81a 612 ah->txok_interrupt_mask &= ~(1 << q);
f1dc5600 613 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
2660b81a 614 ah->txerr_interrupt_mask |= 1 << q;
f1dc5600 615 else
2660b81a 616 ah->txerr_interrupt_mask &= ~(1 << q);
f1dc5600 617 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
2660b81a 618 ah->txdesc_interrupt_mask |= 1 << q;
f1dc5600 619 else
2660b81a 620 ah->txdesc_interrupt_mask &= ~(1 << q);
f1dc5600 621 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
2660b81a 622 ah->txeol_interrupt_mask |= 1 << q;
f1dc5600 623 else
2660b81a 624 ah->txeol_interrupt_mask &= ~(1 << q);
f1dc5600 625 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
2660b81a 626 ah->txurn_interrupt_mask |= 1 << q;
f1dc5600 627 else
2660b81a 628 ah->txurn_interrupt_mask &= ~(1 << q);
f1dc5600
S		 629 ath9k_hw_set_txq_interrupts(ah, qi);
630
631 return true;
632}
7322fd19 633EXPORT_SYMBOL(ath9k_hw_resettxqueue);
f1dc5600 634
cbe61d8a 635int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
8e6f5aa2 636 struct ath_rx_status *rs, u64 tsf)
f1dc5600
S		 637{
638 struct ar5416_desc ads;
639 struct ar5416_desc *adsp = AR5416DESC(ds);
640 u32 phyerr;
641
642 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
643 return -EINPROGRESS;
644
645 ads.u.rx = adsp->u.rx;
646
8e6f5aa2
FF		 647 rs->rs_status = 0;
648 rs->rs_flags = 0;
f1dc5600 649
8e6f5aa2
FF		 650 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
651 rs->rs_tstamp = ads.AR_RcvTimestamp;
f1dc5600 652
dd8b15b0 653 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
8e6f5aa2
FF		 654 rs->rs_rssi = ATH9K_RSSI_BAD;
655 rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
656 rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
657 rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
658 rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
659 rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
660 rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
dd8b15b0 661 } else {
8e6f5aa2
FF		 662 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
663 rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
dd8b15b0 664 AR_RxRSSIAnt00);
8e6f5aa2 665 rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
dd8b15b0 666 AR_RxRSSIAnt01);
8e6f5aa2 667 rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
dd8b15b0 668 AR_RxRSSIAnt02);
8e6f5aa2 669 rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
dd8b15b0 670 AR_RxRSSIAnt10);
8e6f5aa2 671 rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
dd8b15b0 672 AR_RxRSSIAnt11);
8e6f5aa2 673 rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
dd8b15b0
SB		 674 AR_RxRSSIAnt12);
675 }
f1dc5600 676 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
8e6f5aa2 677 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
f1dc5600 678 else
8e6f5aa2 679 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
f1dc5600 680
8e6f5aa2
FF		 681 rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
682 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
f1dc5600 683
8e6f5aa2
FF		 684 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
685 rs->rs_moreaggr =
f1dc5600 686 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
8e6f5aa2
FF		 687 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
688 rs->rs_flags =
f1dc5600 689 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
8e6f5aa2 690 rs->rs_flags |=
f1dc5600
S		 691 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
692
693 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
8e6f5aa2 694 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
f1dc5600 695 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
8e6f5aa2 696 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
f1dc5600 697 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
8e6f5aa2 698 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
f1dc5600
S		 699
700 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
115dad7a
FF		 701 /*
702 * Treat these errors as mutually exclusive to avoid spurious
703 * extra error reports from the hardware. If a CRC error is
704 * reported, then decryption and MIC errors are irrelevant,
705 * the frame is going to be dropped either way
706 */
f1dc5600 707 if (ads.ds_rxstatus8 & AR_CRCErr)
8e6f5aa2 708 rs->rs_status |= ATH9K_RXERR_CRC;
115dad7a 709 else if (ads.ds_rxstatus8 & AR_PHYErr) {
8e6f5aa2 710 rs->rs_status |= ATH9K_RXERR_PHY;
f1dc5600 711 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
8e6f5aa2 712 rs->rs_phyerr = phyerr;
115dad7a 713 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
8e6f5aa2 714 rs->rs_status |= ATH9K_RXERR_DECRYPT;
115dad7a 715 else if (ads.ds_rxstatus8 & AR_MichaelErr)
8e6f5aa2 716 rs->rs_status |= ATH9K_RXERR_MIC;
115dad7a 717
1c30cc19 718 if (ads.ds_rxstatus8 & AR_KeyMiss)
3ae74c33 719 rs->rs_status |= ATH9K_RXERR_DECRYPT;
f1dc5600
S		 720 }
721
722 return 0;
723}
7322fd19 724EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
f1dc5600 725
e7824a50
LR		 726/*
727 * This can stop or re-enables RX.
728 *
729 * If bool is set this will kill any frame which is currently being
730 * transferred between the MAC and baseband and also prevent any new
731 * frames from getting started.
732 */
cbe61d8a 733bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
f1dc5600
S		 734{
735 u32 reg;
736
737 if (set) {
738 REG_SET_BIT(ah, AR_DIAG_SW,
739 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
740
0caa7b14
S		 741 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
742 0, AH_WAIT_TIMEOUT)) {
f1dc5600
S		 743 REG_CLR_BIT(ah, AR_DIAG_SW,
744 (AR_DIAG_RX_DIS |
745 AR_DIAG_RX_ABORT));
746
747 reg = REG_READ(ah, AR_OBS_BUS_1);
3800276a
JP		 748 ath_err(ath9k_hw_common(ah),
749 "RX failed to go idle in 10 ms RXSM=0x%x\n",
750 reg);
f1dc5600
S		 751
752 return false;
753 }
754 } else {
755 REG_CLR_BIT(ah, AR_DIAG_SW,
756 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
757 }
758
759 return true;
760}
7322fd19 761EXPORT_SYMBOL(ath9k_hw_setrxabort);
f1dc5600 762
cbe61d8a 763void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
f1dc5600
S		 764{
765 REG_WRITE(ah, AR_RXDP, rxdp);
766}
7322fd19 767EXPORT_SYMBOL(ath9k_hw_putrxbuf);
f1dc5600 768
40346b66 769void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
f1dc5600 770{
f1dc5600
S		 771 ath9k_enable_mib_counters(ah);
772
40346b66 773 ath9k_ani_reset(ah, is_scanning);
e7594072 774
8aa15e15 775 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
f1dc5600 776}
7322fd19 777EXPORT_SYMBOL(ath9k_hw_startpcureceive);
f1dc5600 778
9b9cc61c
VT		 779void ath9k_hw_abortpcurecv(struct ath_hw *ah)
780{
781 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
782
783 ath9k_hw_disable_mib_counters(ah);
784}
785EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
786
cbe61d8a 787bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
f1dc5600 788{
0caa7b14
S		 789#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
790#define AH_RX_TIME_QUANTUM 100 /* usec */
c46917bb 791 struct ath_common *common = ath9k_hw_common(ah);
0caa7b14
S		 792 int i;
793
f1dc5600
S		 794 REG_WRITE(ah, AR_CR, AR_CR_RXD);
795
0caa7b14
S		 796 /* Wait for rx enable bit to go low */
797 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
798 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
799 break;
800 udelay(AH_TIME_QUANTUM);
801 }
802
803 if (i == 0) {
3800276a
JP		 804 ath_err(common,
805 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
806 AH_RX_STOP_DMA_TIMEOUT / 1000,
807 REG_READ(ah, AR_CR),
808 REG_READ(ah, AR_DIAG_SW));
f1dc5600
S		 809 return false;
810 } else {
811 return true;
812 }
0caa7b14
S		 813
814#undef AH_RX_TIME_QUANTUM
815#undef AH_RX_STOP_DMA_TIMEOUT
f1dc5600 816}
7322fd19 817EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
536b3a7a
LR		 818
819int ath9k_hw_beaconq_setup(struct ath_hw *ah)
820{
821 struct ath9k_tx_queue_info qi;
822
823 memset(&qi, 0, sizeof(qi));
824 qi.tqi_aifs = 1;
825 qi.tqi_cwmin = 0;
826 qi.tqi_cwmax = 0;
827 /* NB: don't enable any interrupts */
828 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
829}
830EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
55e82df4
VT		 831
832bool ath9k_hw_intrpend(struct ath_hw *ah)
833{
834 u32 host_isr;
835
836 if (AR_SREV_9100(ah))
837 return true;
838
839 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
840 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
841 return true;
842
843 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
844 if ((host_isr & AR_INTR_SYNC_DEFAULT)
845 && (host_isr != AR_INTR_SPURIOUS))
846 return true;
847
848 return false;
849}
850EXPORT_SYMBOL(ath9k_hw_intrpend);
851
4df3071e
FF		 852void ath9k_hw_disable_interrupts(struct ath_hw *ah)
853{
854 struct ath_common *common = ath9k_hw_common(ah);
855
226afe68 856 ath_dbg(common, ATH_DBG_INTERRUPT, "disable IER\n");
4df3071e
FF		 857 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
858 (void) REG_READ(ah, AR_IER);
859 if (!AR_SREV_9100(ah)) {
860 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
861 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
862
863 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
864 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
865 }
866}
867EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
868
869void ath9k_hw_enable_interrupts(struct ath_hw *ah)
870{
871 struct ath_common *common = ath9k_hw_common(ah);
872
873 if (!(ah->imask & ATH9K_INT_GLOBAL))
874 return;
875
226afe68 876 ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
4df3071e
FF		 877 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
878 if (!AR_SREV_9100(ah)) {
879 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
880 AR_INTR_MAC_IRQ);
881 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
882
883
884 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
885 AR_INTR_SYNC_DEFAULT);
886 REG_WRITE(ah, AR_INTR_SYNC_MASK,
887 AR_INTR_SYNC_DEFAULT);
888 }
226afe68
JP		 889 ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
890 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
4df3071e
FF		 891}
892EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
893
894void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
55e82df4
VT		 895{
896 enum ath9k_int omask = ah->imask;
897 u32 mask, mask2;
898 struct ath9k_hw_capabilities *pCap = &ah->caps;
899 struct ath_common *common = ath9k_hw_common(ah);
900
4df3071e
FF		 901 if (!(ints & ATH9K_INT_GLOBAL))
902 ath9k_hw_enable_interrupts(ah);
55e82df4 903
226afe68 904 ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
55e82df4
VT		 905
906 /* TODO: global int Ref count */
907 mask = ints & ATH9K_INT_COMMON;
908 mask2 = 0;
909
910 if (ints & ATH9K_INT_TX) {
911 if (ah->config.tx_intr_mitigation)
912 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
5bea4006
LR		 913 else {
914 if (ah->txok_interrupt_mask)
915 mask |= AR_IMR_TXOK;
916 if (ah->txdesc_interrupt_mask)
917 mask |= AR_IMR_TXDESC;
918 }
55e82df4
VT		 919 if (ah->txerr_interrupt_mask)
920 mask |= AR_IMR_TXERR;
921 if (ah->txeol_interrupt_mask)
922 mask |= AR_IMR_TXEOL;
923 }
924 if (ints & ATH9K_INT_RX) {
925 if (AR_SREV_9300_20_OR_LATER(ah)) {
926 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
927 if (ah->config.rx_intr_mitigation) {
928 mask &= ~AR_IMR_RXOK_LP;
929 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
930 } else {
931 mask |= AR_IMR_RXOK_LP;
932 }
933 } else {
934 if (ah->config.rx_intr_mitigation)
935 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
936 else
937 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
938 }
939 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
940 mask |= AR_IMR_GENTMR;
941 }
942
943 if (ints & (ATH9K_INT_BMISC)) {
944 mask |= AR_IMR_BCNMISC;
945 if (ints & ATH9K_INT_TIM)
946 mask2 |= AR_IMR_S2_TIM;
947 if (ints & ATH9K_INT_DTIM)
948 mask2 |= AR_IMR_S2_DTIM;
949 if (ints & ATH9K_INT_DTIMSYNC)
950 mask2 |= AR_IMR_S2_DTIMSYNC;
951 if (ints & ATH9K_INT_CABEND)
952 mask2 |= AR_IMR_S2_CABEND;
953 if (ints & ATH9K_INT_TSFOOR)
954 mask2 |= AR_IMR_S2_TSFOOR;
955 }
956
957 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
958 mask |= AR_IMR_BCNMISC;
959 if (ints & ATH9K_INT_GTT)
960 mask2 |= AR_IMR_S2_GTT;
961 if (ints & ATH9K_INT_CST)
962 mask2 |= AR_IMR_S2_CST;
963 }
964
226afe68 965 ath_dbg(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
55e82df4
VT		 966 REG_WRITE(ah, AR_IMR, mask);
967 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
968 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
969 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
970 ah->imrs2_reg |= mask2;
971 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
972
973 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
974 if (ints & ATH9K_INT_TIM_TIMER)
975 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
976 else
977 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
978 }
979
4df3071e 980 ath9k_hw_enable_interrupts(ah);
55e82df4 981
4df3071e 982 return;
55e82df4
VT		 983}
984EXPORT_SYMBOL(ath9k_hw_set_interrupts);
Linux kernel - Deliverables
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