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Merge branch 'for-linus' into for-next
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
6dcc3444
SM		 22static void ath9k_set_assoc_state(struct ath_softc *sc,
23 struct ieee80211_vif *vif);
24
313eb87f 25u8 ath9k_parse_mpdudensity(u8 mpdudensity)
ff37e337
S		 26{
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58}
59
69081624
VT		 60static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61{
62 bool pending = false;
63
64 spin_lock_bh(&txq->axq_lock);
65
66 if (txq->axq_depth || !list_empty(&txq->axq_acq))
67 pending = true;
69081624
VT		 68
69 spin_unlock_bh(&txq->axq_lock);
70 return pending;
71}
72
6d79cb4c 73static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 74{
75 unsigned long flags;
76 bool ret;
77
9ecdef4b
LR		 78 spin_lock_irqsave(&sc->sc_pm_lock, flags);
79 ret = ath9k_hw_setpower(sc->sc_ah, mode);
80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 81
82 return ret;
83}
84
a91d75ae
LR		 85void ath9k_ps_wakeup(struct ath_softc *sc)
86{
898c914a 87 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 88 unsigned long flags;
fbb078fc 89 enum ath9k_power_mode power_mode;
a91d75ae
LR		 90
91 spin_lock_irqsave(&sc->sc_pm_lock, flags);
92 if (++sc->ps_usecount != 1)
93 goto unlock;
94
fbb078fc 95 power_mode = sc->sc_ah->power_mode;
9ecdef4b 96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 97
898c914a
FF		 98 /*
99 * While the hardware is asleep, the cycle counters contain no
100 * useful data. Better clear them now so that they don't mess up
101 * survey data results.
102 */
fbb078fc
FF		 103 if (power_mode != ATH9K_PM_AWAKE) {
104 spin_lock(&common->cc_lock);
105 ath_hw_cycle_counters_update(common);
106 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
c9ae6ab4 107 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
fbb078fc
FF		 108 spin_unlock(&common->cc_lock);
109 }
898c914a 110
a91d75ae
LR		 111 unlock:
112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
113}
114
115void ath9k_ps_restore(struct ath_softc *sc)
116{
898c914a 117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 118 enum ath9k_power_mode mode;
a91d75ae 119 unsigned long flags;
ad128860 120 bool reset;
a91d75ae
LR		 121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (--sc->ps_usecount != 0)
124 goto unlock;
125
ad128860
SM		 126 if (sc->ps_idle) {
127 ath9k_hw_setrxabort(sc->sc_ah, 1);
128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
c6c539f0 129 mode = ATH9K_PM_FULL_SLEEP;
ad128860
SM		 130 } else if (sc->ps_enabled &&
131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
132 PS_WAIT_FOR_CAB |
133 PS_WAIT_FOR_PSPOLL_DATA |
134 PS_WAIT_FOR_TX_ACK))) {
c6c539f0 135 mode = ATH9K_PM_NETWORK_SLEEP;
08d4df41
RM		 136 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
137 ath9k_btcoex_stop_gen_timer(sc);
ad128860 138 } else {
c6c539f0 139 goto unlock;
ad128860 140 }
c6c539f0
FF		 141
142 spin_lock(&common->cc_lock);
143 ath_hw_cycle_counters_update(common);
144 spin_unlock(&common->cc_lock);
145
1a8f0d39 146 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR		 147
148 unlock:
149 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
150}
151
9adcf440 152static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 153{
5ee08656
FF		 154 cancel_work_sync(&sc->paprd_work);
155 cancel_work_sync(&sc->hw_check_work);
156 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 157 cancel_delayed_work_sync(&sc->hw_pll_work);
fad29cd2 158
bf52592f 159#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
fad29cd2
SM		 160 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
161 cancel_work_sync(&sc->mci_work);
bf52592f 162#endif
9adcf440 163}
5ee08656 164
9adcf440
FF		 165static void ath_cancel_work(struct ath_softc *sc)
166{
167 __ath_cancel_work(sc);
168 cancel_work_sync(&sc->hw_reset_work);
169}
3cbb5dd7 170
af68abad
SM		 171static void ath_restart_work(struct ath_softc *sc)
172{
af68abad
SM		 173 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
174
c12b6021
GJ		 175 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
176 AR_SREV_9550(sc->sc_ah))
af68abad
SM		 177 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
178 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
179
180 ath_start_rx_poll(sc, 3);
da0d45f7 181 ath_start_ani(sc);
af68abad
SM		 182}
183
9adcf440
FF		 184static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
185{
186 struct ath_hw *ah = sc->sc_ah;
ceea2a51 187 bool ret = true;
6a6733f2 188
9adcf440 189 ieee80211_stop_queues(sc->hw);
5e848f78 190
9adcf440 191 sc->hw_busy_count = 0;
da0d45f7 192 ath_stop_ani(sc);
01e18918 193 del_timer_sync(&sc->rx_poll_timer);
ff37e337 194
9adcf440
FF		 195 ath9k_debug_samp_bb_mac(sc);
196 ath9k_hw_disable_interrupts(ah);
8b3f4616 197
9adcf440
FF		 198 if (!ath_stoprecv(sc))
199 ret = false;
c0d7c7af 200
ceea2a51
FF		 201 if (!ath_drain_all_txq(sc, retry_tx))
202 ret = false;
203
9adcf440
FF		 204 if (!flush) {
205 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
3483288c
FF		 206 ath_rx_tasklet(sc, 1, true);
207 ath_rx_tasklet(sc, 1, false);
9adcf440
FF		 208 } else {
209 ath_flushrecv(sc);
210 }
20bd2a09 211
9adcf440
FF		 212 return ret;
213}
ff37e337 214
9adcf440
FF		 215static bool ath_complete_reset(struct ath_softc *sc, bool start)
216{
217 struct ath_hw *ah = sc->sc_ah;
218 struct ath_common *common = ath9k_hw_common(ah);
196fb860 219 unsigned long flags;
c0d7c7af 220
c0d7c7af 221 if (ath_startrecv(sc) != 0) {
3800276a 222 ath_err(common, "Unable to restart recv logic\n");
9adcf440 223 return false;
c0d7c7af
LR		 224 }
225
5048e8c3
RM		 226 ath9k_cmn_update_txpow(ah, sc->curtxpow,
227 sc->config.txpowlimit, &sc->curtxpow);
b74713d0
SM		 228
229 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
72d874c6 230 ath9k_hw_set_interrupts(ah);
b037b693 231 ath9k_hw_enable_interrupts(ah);
3989279c 232
4cb54fa3 233 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
196fb860
SM		 234 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
235 goto work;
236
ef4ad633 237 ath9k_set_beacon(sc);
196fb860
SM		 238
239 if (ah->opmode == NL80211_IFTYPE_STATION &&
240 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
241 spin_lock_irqsave(&sc->sc_pm_lock, flags);
242 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
243 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
244 }
245 work:
af68abad 246 ath_restart_work(sc);
5ee08656
FF		 247 }
248
8da07830
SM		 249 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
250 ath_ant_comb_update(sc);
43c35284 251
9adcf440
FF		 252 ieee80211_wake_queues(sc->hw);
253
254 return true;
255}
256
257static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
258 bool retry_tx)
259{
260 struct ath_hw *ah = sc->sc_ah;
261 struct ath_common *common = ath9k_hw_common(ah);
262 struct ath9k_hw_cal_data *caldata = NULL;
263 bool fastcc = true;
264 bool flush = false;
265 int r;
266
267 __ath_cancel_work(sc);
268
269 spin_lock_bh(&sc->sc_pcu_lock);
92460412 270
4cb54fa3 271 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
9adcf440
FF		 272 fastcc = false;
273 caldata = &sc->caldata;
274 }
275
276 if (!hchan) {
277 fastcc = false;
278 flush = true;
279 hchan = ah->curchan;
280 }
281
9adcf440
FF		 282 if (!ath_prepare_reset(sc, retry_tx, flush))
283 fastcc = false;
284
d2182b69 285 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 286 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF		 287
288 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
289 if (r) {
290 ath_err(common,
291 "Unable to reset channel, reset status %d\n", r);
292 goto out;
293 }
294
295 if (!ath_complete_reset(sc, true))
296 r = -EIO;
297
298out:
6a6733f2 299 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440
FF		 300 return r;
301}
302
303
304/*
305 * Set/change channels. If the channel is really being changed, it's done
306 * by reseting the chip. To accomplish this we must first cleanup any pending
307 * DMA, then restart stuff.
308*/
309static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
310 struct ath9k_channel *hchan)
311{
312 int r;
313
781b14a3 314 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
9adcf440
FF		 315 return -EIO;
316
9adcf440 317 r = ath_reset_internal(sc, hchan, false);
6a6733f2 318
3989279c 319 return r;
ff37e337
S		 320}
321
7e1e3864
BG		 322static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
323 struct ieee80211_vif *vif)
ff37e337
S		 324{
325 struct ath_node *an;
313eb87f 326 u8 density;
ff37e337
S		 327 an = (struct ath_node *)sta->drv_priv;
328
7f010c93
BG		 329#ifdef CONFIG_ATH9K_DEBUGFS
330 spin_lock(&sc->nodes_lock);
331 list_add(&an->list, &sc->nodes);
332 spin_unlock(&sc->nodes_lock);
156369fa 333#endif
7f010c93 334 an->sta = sta;
7e1e3864 335 an->vif = vif;
3d4e20f2 336
a4d6367f 337 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337 338 ath_tx_node_init(sc, an);
9e98ac65 339 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc 340 sta->ht_cap.ampdu_factor);
313eb87f
SE		 341 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
342 an->mpdudensity = density;
87792efc 343 }
ff37e337
S		 344}
345
346static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
347{
348 struct ath_node *an = (struct ath_node *)sta->drv_priv;
349
7f010c93
BG		 350#ifdef CONFIG_ATH9K_DEBUGFS
351 spin_lock(&sc->nodes_lock);
352 list_del(&an->list);
353 spin_unlock(&sc->nodes_lock);
354 an->sta = NULL;
355#endif
356
a4d6367f 357 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
ff37e337
S		 358 ath_tx_node_cleanup(sc, an);
359}
360
55624204 361void ath9k_tasklet(unsigned long data)
ff37e337
S		 362{
363 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 364 struct ath_hw *ah = sc->sc_ah;
c46917bb 365 struct ath_common *common = ath9k_hw_common(ah);
124b979b 366 enum ath_reset_type type;
07c15a3f 367 unsigned long flags;
17d7904d 368 u32 status = sc->intrstatus;
b5c80475 369 u32 rxmask;
ff37e337 370
e3927007
FF		 371 ath9k_ps_wakeup(sc);
372 spin_lock(&sc->sc_pcu_lock);
373
a4d86d95
RM		 374 if ((status & ATH9K_INT_FATAL) ||
375 (status & ATH9K_INT_BB_WATCHDOG)) {
030d6294
FF		 376
377 if (status & ATH9K_INT_FATAL)
378 type = RESET_TYPE_FATAL_INT;
379 else
380 type = RESET_TYPE_BB_WATCHDOG;
381
124b979b 382 ath9k_queue_reset(sc, type);
e3927007 383 goto out;
063d8be3 384 }
ff37e337 385
07c15a3f 386 spin_lock_irqsave(&sc->sc_pm_lock, flags);
4105f807
RM		 387 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
388 /*
389 * TSF sync does not look correct; remain awake to sync with
390 * the next Beacon.
391 */
d2182b69 392 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 393 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807 394 }
07c15a3f 395 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
4105f807 396
b5c80475
FF		 397 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
398 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
399 ATH9K_INT_RXORN);
400 else
401 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
402
403 if (status & rxmask) {
b5c80475
FF		 404 /* Check for high priority Rx first */
405 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
406 (status & ATH9K_INT_RXHP))
407 ath_rx_tasklet(sc, 0, true);
408
409 ath_rx_tasklet(sc, 0, false);
ff37e337
S		 410 }
411
e5003249
VT		 412 if (status & ATH9K_INT_TX) {
413 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
414 ath_tx_edma_tasklet(sc);
415 else
416 ath_tx_tasklet(sc);
417 }
063d8be3 418
56ca0dba 419 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 420
e3927007 421out:
ff37e337 422 /* re-enable hardware interrupt */
4df3071e 423 ath9k_hw_enable_interrupts(ah);
6a6733f2 424
52671e43 425 spin_unlock(&sc->sc_pcu_lock);
153e080d 426 ath9k_ps_restore(sc);
ff37e337
S		 427}
428
6baff7f9 429irqreturn_t ath_isr(int irq, void *dev)
ff37e337 430{
063d8be3
S		 431#define SCHED_INTR ( \
432 ATH9K_INT_FATAL | \
a4d86d95 433 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S		 434 ATH9K_INT_RXORN | \
435 ATH9K_INT_RXEOL | \
436 ATH9K_INT_RX | \
b5c80475
FF		 437 ATH9K_INT_RXLP | \
438 ATH9K_INT_RXHP | \
063d8be3
S		 439 ATH9K_INT_TX | \
440 ATH9K_INT_BMISS | \
441 ATH9K_INT_CST | \
ebb8e1d7 442 ATH9K_INT_TSFOOR | \
40dc5392
MSS		 443 ATH9K_INT_GENTIMER | \
444 ATH9K_INT_MCI)
063d8be3 445
ff37e337 446 struct ath_softc *sc = dev;
cbe61d8a 447 struct ath_hw *ah = sc->sc_ah;
b5bfc568 448 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 449 enum ath9k_int status;
450 bool sched = false;
451
063d8be3
S		 452 /*
453 * The hardware is not ready/present, don't
454 * touch anything. Note this can happen early
455 * on if the IRQ is shared.
456 */
781b14a3 457 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
063d8be3 458 return IRQ_NONE;
ff37e337 459
063d8be3
S		 460 /* shared irq, not for us */
461
153e080d 462 if (!ath9k_hw_intrpend(ah))
063d8be3 463 return IRQ_NONE;
063d8be3 464
f41a9b3b
FF		 465 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
466 ath9k_hw_kill_interrupts(ah);
b74713d0 467 return IRQ_HANDLED;
f41a9b3b 468 }
b74713d0 469
063d8be3
S		 470 /*
471 * Figure out the reason(s) for the interrupt. Note
472 * that the hal returns a pseudo-ISR that may include
473 * bits we haven't explicitly enabled so we mask the
474 * value to insure we only process bits we requested.
475 */
476 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 477 status &= ah->imask; /* discard unasked-for bits */
ff37e337 478
063d8be3
S		 479 /*
480 * If there are no status bits set, then this interrupt was not
481 * for me (should have been caught above).
482 */
153e080d 483 if (!status)
063d8be3 484 return IRQ_NONE;
ff37e337 485
063d8be3
S		 486 /* Cache the status */
487 sc->intrstatus = status;
488
489 if (status & SCHED_INTR)
490 sched = true;
491
b11e640a
MSS		 492#ifdef CONFIG_PM_SLEEP
493 if (status & ATH9K_INT_BMISS) {
494 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
495 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
496 atomic_inc(&sc->wow_got_bmiss_intr);
497 atomic_dec(&sc->wow_sleep_proc_intr);
498 }
499 ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
500 }
501#endif
502
063d8be3
S		 503 /*
504 * If a FATAL or RXORN interrupt is received, we have to reset the
505 * chip immediately.
506 */
b5c80475
FF		 507 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
508 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S		 509 goto chip_reset;
510
08578b8f
LR		 511 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
512 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF		 513
514 spin_lock(&common->cc_lock);
515 ath_hw_cycle_counters_update(common);
08578b8f 516 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF		 517 spin_unlock(&common->cc_lock);
518
08578b8f
LR		 519 goto chip_reset;
520 }
521
063d8be3
S		 522 if (status & ATH9K_INT_SWBA)
523 tasklet_schedule(&sc->bcon_tasklet);
524
525 if (status & ATH9K_INT_TXURN)
526 ath9k_hw_updatetxtriglevel(ah, true);
527
0682c9b5
RM		 528 if (status & ATH9K_INT_RXEOL) {
529 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 530 ath9k_hw_set_interrupts(ah);
b5c80475
FF		 531 }
532
153e080d
VT		 533 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
534 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR		 535 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
536 goto chip_reset;
063d8be3
S		 537 /* Clear RxAbort bit so that we can
538 * receive frames */
9ecdef4b 539 ath9k_setpower(sc, ATH9K_PM_AWAKE);
07c15a3f 540 spin_lock(&sc->sc_pm_lock);
153e080d 541 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 542 sc->ps_flags |= PS_WAIT_FOR_BEACON;
07c15a3f 543 spin_unlock(&sc->sc_pm_lock);
ff37e337 544 }
063d8be3
S		 545
546chip_reset:
ff37e337 547
817e11de
S		 548 ath_debug_stat_interrupt(sc, status);
549
ff37e337 550 if (sched) {
4df3071e
FF		 551 /* turn off every interrupt */
552 ath9k_hw_disable_interrupts(ah);
ff37e337
S		 553 tasklet_schedule(&sc->intr_tq);
554 }
555
556 return IRQ_HANDLED;
063d8be3
S		 557
558#undef SCHED_INTR
ff37e337
S		 559}
560
236de514 561static int ath_reset(struct ath_softc *sc, bool retry_tx)
ff37e337 562{
ae8d2858 563 int r;
ff37e337 564
783cd01e 565 ath9k_ps_wakeup(sc);
6a6733f2 566
9adcf440 567 r = ath_reset_internal(sc, NULL, retry_tx);
ff37e337
S		 568
569 if (retry_tx) {
570 int i;
571 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
572 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 573 spin_lock_bh(&sc->tx.txq[i].axq_lock);
574 ath_txq_schedule(sc, &sc->tx.txq[i]);
575 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 576 }
577 }
578 }
579
783cd01e 580 ath9k_ps_restore(sc);
2ab81d4a 581
ae8d2858 582 return r;
ff37e337
S		 583}
584
124b979b
RM		 585void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
586{
587#ifdef CONFIG_ATH9K_DEBUGFS
588 RESET_STAT_INC(sc, type);
589#endif
590 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
591 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
592}
593
236de514
FF		 594void ath_reset_work(struct work_struct *work)
595{
596 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
597
236de514 598 ath_reset(sc, true);
236de514
FF		 599}
600
ff37e337
S		 601/**********************/
602/* mac80211 callbacks */
603/**********************/
604
8feceb67 605static int ath9k_start(struct ieee80211_hw *hw)
f078f209 606{
9ac58615 607 struct ath_softc *sc = hw->priv;
af03abec 608 struct ath_hw *ah = sc->sc_ah;
c46917bb 609 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 610 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 611 struct ath9k_channel *init_channel;
82880a7c 612 int r;
f078f209 613
d2182b69 614 ath_dbg(common, CONFIG,
226afe68
JP		 615 "Starting driver with initial channel: %d MHz\n",
616 curchan->center_freq);
f078f209 617
f62d816f 618 ath9k_ps_wakeup(sc);
141b38b6
S		 619 mutex_lock(&sc->mutex);
620
c344c9cb 621 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S		 622
623 /* Reset SERDES registers */
84c87dc8 624 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S		 625
626 /*
627 * The basic interface to setting the hardware in a good
628 * state is ``reset''. On return the hardware is known to
629 * be powered up and with interrupts disabled. This must
630 * be followed by initialization of the appropriate bits
631 * and then setup of the interrupt mask.
632 */
4bdd1e97 633 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF		 634
635 atomic_set(&ah->intr_ref_cnt, -1);
636
20bd2a09 637 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 638 if (r) {
3800276a
JP		 639 ath_err(common,
640 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
641 r, curchan->center_freq);
4bdd1e97 642 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 643 goto mutex_unlock;
ff37e337 644 }
ff37e337 645
ff37e337 646 /* Setup our intr mask. */
b5c80475
FF		 647 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
648 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
649 ATH9K_INT_GLOBAL;
650
651 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR		 652 ah->imask |= ATH9K_INT_RXHP |
653 ATH9K_INT_RXLP |
654 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF		 655 else
656 ah->imask |= ATH9K_INT_RX;
ff37e337 657
364734fa 658 ah->imask |= ATH9K_INT_GTT;
ff37e337 659
af03abec 660 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 661 ah->imask |= ATH9K_INT_CST;
ff37e337 662
e270e776 663 ath_mci_enable(sc);
40dc5392 664
781b14a3 665 clear_bit(SC_OP_INVALID, &sc->sc_flags);
5f841b41 666 sc->sc_ah->is_monitoring = false;
ff37e337 667
9adcf440
FF		 668 if (!ath_complete_reset(sc, false)) {
669 r = -EIO;
670 spin_unlock_bh(&sc->sc_pcu_lock);
671 goto mutex_unlock;
672 }
ff37e337 673
c0c11741
FF		 674 if (ah->led_pin >= 0) {
675 ath9k_hw_cfg_output(ah, ah->led_pin,
676 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
677 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
678 }
679
680 /*
681 * Reset key cache to sane defaults (all entries cleared) instead of
682 * semi-random values after suspend/resume.
683 */
684 ath9k_cmn_init_crypto(sc->sc_ah);
685
9adcf440 686 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 687
8060e169
VT		 688 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
689 common->bus_ops->extn_synch_en(common);
690
141b38b6
S		 691mutex_unlock:
692 mutex_unlock(&sc->mutex);
693
f62d816f
FF		 694 ath9k_ps_restore(sc);
695
ae8d2858 696 return r;
f078f209
LR		 697}
698
7bb45683 699static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 700{
9ac58615 701 struct ath_softc *sc = hw->priv;
c46917bb 702 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 703 struct ath_tx_control txctl;
1bc14880 704 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
07c15a3f 705 unsigned long flags;
528f0c6b 706
96148326 707 if (sc->ps_enabled) {
dc8c4585
JM		 708 /*
709 * mac80211 does not set PM field for normal data frames, so we
710 * need to update that based on the current PS mode.
711 */
712 if (ieee80211_is_data(hdr->frame_control) &&
713 !ieee80211_is_nullfunc(hdr->frame_control) &&
714 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 715 ath_dbg(common, PS,
226afe68 716 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM		 717 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
718 }
719 }
720
ad128860 721 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
9a23f9ca
JM		 722 /*
723 * We are using PS-Poll and mac80211 can request TX while in
724 * power save mode. Need to wake up hardware for the TX to be
725 * completed and if needed, also for RX of buffered frames.
726 */
9a23f9ca 727 ath9k_ps_wakeup(sc);
07c15a3f 728 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fdf76622
VT		 729 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
730 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 731 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 732 ath_dbg(common, PS,
226afe68 733 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 734 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 735 } else {
d2182b69 736 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 737 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM		 738 }
739 /*
740 * The actual restore operation will happen only after
ad128860 741 * the ps_flags bit is cleared. We are just dropping
9a23f9ca
JM		 742 * the ps_usecount here.
743 */
07c15a3f 744 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca
JM		 745 ath9k_ps_restore(sc);
746 }
747
ad128860
SM		 748 /*
749 * Cannot tx while the hardware is in full sleep, it first needs a full
750 * chip reset to recover from that
751 */
752 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
753 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
754 goto exit;
755 }
756
528f0c6b 757 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 758 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 759
d2182b69 760 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 761
c52f33d0 762 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 763 ath_dbg(common, XMIT, "TX failed\n");
a5a0bca1 764 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
528f0c6b 765 goto exit;
8feceb67
VT		 766 }
767
7bb45683 768 return;
528f0c6b
S		 769exit:
770 dev_kfree_skb_any(skb);
f078f209
LR		 771}
772
8feceb67 773static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 774{
9ac58615 775 struct ath_softc *sc = hw->priv;
af03abec 776 struct ath_hw *ah = sc->sc_ah;
c46917bb 777 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 778 bool prev_idle;
f078f209 779
4c483817
S		 780 mutex_lock(&sc->mutex);
781
9adcf440 782 ath_cancel_work(sc);
01e18918 783 del_timer_sync(&sc->rx_poll_timer);
c94dbff7 784
781b14a3 785 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
d2182b69 786 ath_dbg(common, ANY, "Device not present\n");
4c483817 787 mutex_unlock(&sc->mutex);
9c84b797
S		 788 return;
789 }
8feceb67 790
3867cf6a
S		 791 /* Ensure HW is awake when we try to shut it down. */
792 ath9k_ps_wakeup(sc);
793
6a6733f2
LR		 794 spin_lock_bh(&sc->sc_pcu_lock);
795
203043f5
SG		 796 /* prevent tasklets to enable interrupts once we disable them */
797 ah->imask &= ~ATH9K_INT_GLOBAL;
798
ff37e337
S		 799 /* make sure h/w will not generate any interrupt
800 * before setting the invalid flag. */
4df3071e 801 ath9k_hw_disable_interrupts(ah);
ff37e337 802
c0c11741
FF		 803 spin_unlock_bh(&sc->sc_pcu_lock);
804
805 /* we can now sync irq and kill any running tasklets, since we already
806 * disabled interrupts and not holding a spin lock */
807 synchronize_irq(sc->irq);
808 tasklet_kill(&sc->intr_tq);
809 tasklet_kill(&sc->bcon_tasklet);
810
811 prev_idle = sc->ps_idle;
812 sc->ps_idle = true;
813
814 spin_lock_bh(&sc->sc_pcu_lock);
815
816 if (ah->led_pin >= 0) {
817 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
818 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
819 }
820
821 ath_prepare_reset(sc, false, true);
ff37e337 822
0d95521e
FF		 823 if (sc->rx.frag) {
824 dev_kfree_skb_any(sc->rx.frag);
825 sc->rx.frag = NULL;
826 }
827
c0c11741
FF		 828 if (!ah->curchan)
829 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
6a6733f2 830
c0c11741
FF		 831 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
832 ath9k_hw_phy_disable(ah);
6a6733f2 833
c0c11741 834 ath9k_hw_configpcipowersave(ah, true);
203043f5 835
c0c11741 836 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 837
c0c11741 838 ath9k_ps_restore(sc);
ff37e337 839
781b14a3 840 set_bit(SC_OP_INVALID, &sc->sc_flags);
c0c11741 841 sc->ps_idle = prev_idle;
500c064d 842
141b38b6
S		 843 mutex_unlock(&sc->mutex);
844
d2182b69 845 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR		 846}
847
4801416c
BG		 848bool ath9k_uses_beacons(int type)
849{
850 switch (type) {
851 case NL80211_IFTYPE_AP:
852 case NL80211_IFTYPE_ADHOC:
853 case NL80211_IFTYPE_MESH_POINT:
854 return true;
855 default:
856 return false;
857 }
858}
859
4801416c
BG		 860static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
861{
862 struct ath9k_vif_iter_data *iter_data = data;
863 int i;
864
865 if (iter_data->hw_macaddr)
866 for (i = 0; i < ETH_ALEN; i++)
867 iter_data->mask[i] &=
868 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 869
1ed32e4f 870 switch (vif->type) {
4801416c
BG		 871 case NL80211_IFTYPE_AP:
872 iter_data->naps++;
f078f209 873 break;
4801416c
BG		 874 case NL80211_IFTYPE_STATION:
875 iter_data->nstations++;
e51f3eff 876 break;
05c914fe 877 case NL80211_IFTYPE_ADHOC:
4801416c
BG		 878 iter_data->nadhocs++;
879 break;
9cb5412b 880 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG		 881 iter_data->nmeshes++;
882 break;
883 case NL80211_IFTYPE_WDS:
884 iter_data->nwds++;
f078f209
LR		 885 break;
886 default:
4801416c 887 break;
f078f209 888 }
4801416c 889}
f078f209 890
6dcc3444
SM		 891static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
892{
893 struct ath_softc *sc = data;
894 struct ath_vif *avp = (void *)vif->drv_priv;
895
896 if (vif->type != NL80211_IFTYPE_STATION)
897 return;
898
899 if (avp->primary_sta_vif)
900 ath9k_set_assoc_state(sc, vif);
901}
902
4801416c
BG		 903/* Called with sc->mutex held. */
904void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
905 struct ieee80211_vif *vif,
906 struct ath9k_vif_iter_data *iter_data)
907{
9ac58615 908 struct ath_softc *sc = hw->priv;
4801416c
BG		 909 struct ath_hw *ah = sc->sc_ah;
910 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 911
4801416c
BG		 912 /*
913 * Use the hardware MAC address as reference, the hardware uses it
914 * together with the BSSID mask when matching addresses.
915 */
916 memset(iter_data, 0, sizeof(*iter_data));
917 iter_data->hw_macaddr = common->macaddr;
918 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 919
4801416c
BG		 920 if (vif)
921 ath9k_vif_iter(iter_data, vif->addr, vif);
922
923 /* Get list of all active MAC addresses */
4801416c
BG		 924 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
925 iter_data);
4801416c 926}
8ca21f01 927
4801416c
BG		 928/* Called with sc->mutex held. */
929static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
930 struct ieee80211_vif *vif)
931{
9ac58615 932 struct ath_softc *sc = hw->priv;
4801416c
BG		 933 struct ath_hw *ah = sc->sc_ah;
934 struct ath_common *common = ath9k_hw_common(ah);
935 struct ath9k_vif_iter_data iter_data;
6dcc3444 936 enum nl80211_iftype old_opmode = ah->opmode;
8ca21f01 937
4801416c 938 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 939
4801416c
BG		 940 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
941 ath_hw_setbssidmask(common);
942
4801416c 943 if (iter_data.naps > 0) {
60ca9f87 944 ath9k_hw_set_tsfadjust(ah, true);
4801416c
BG		 945 ah->opmode = NL80211_IFTYPE_AP;
946 } else {
60ca9f87 947 ath9k_hw_set_tsfadjust(ah, false);
5640b08e 948
fd5999cf
JC		 949 if (iter_data.nmeshes)
950 ah->opmode = NL80211_IFTYPE_MESH_POINT;
951 else if (iter_data.nwds)
4801416c
BG		 952 ah->opmode = NL80211_IFTYPE_AP;
953 else if (iter_data.nadhocs)
954 ah->opmode = NL80211_IFTYPE_ADHOC;
955 else
956 ah->opmode = NL80211_IFTYPE_STATION;
957 }
5640b08e 958
df35d29e
SM		 959 ath9k_hw_setopmode(ah);
960
198823fd 961 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
3069168c 962 ah->imask |= ATH9K_INT_TSFOOR;
198823fd 963 else
4801416c 964 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f 965
72d874c6 966 ath9k_hw_set_interrupts(ah);
6dcc3444
SM		 967
968 /*
969 * If we are changing the opmode to STATION,
970 * a beacon sync needs to be done.
971 */
972 if (ah->opmode == NL80211_IFTYPE_STATION &&
973 old_opmode == NL80211_IFTYPE_AP &&
974 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
975 ieee80211_iterate_active_interfaces_atomic(sc->hw,
976 ath9k_sta_vif_iter, sc);
977 }
4801416c 978}
6f255425 979
4801416c
BG		 980static int ath9k_add_interface(struct ieee80211_hw *hw,
981 struct ieee80211_vif *vif)
6b3b991d 982{
9ac58615 983 struct ath_softc *sc = hw->priv;
4801416c
BG		 984 struct ath_hw *ah = sc->sc_ah;
985 struct ath_common *common = ath9k_hw_common(ah);
4801416c 986 int ret = 0;
6b3b991d 987
96f372c9 988 ath9k_ps_wakeup(sc);
4801416c 989 mutex_lock(&sc->mutex);
6b3b991d 990
4801416c
BG		 991 switch (vif->type) {
992 case NL80211_IFTYPE_STATION:
993 case NL80211_IFTYPE_WDS:
994 case NL80211_IFTYPE_ADHOC:
995 case NL80211_IFTYPE_AP:
996 case NL80211_IFTYPE_MESH_POINT:
997 break;
998 default:
999 ath_err(common, "Interface type %d not yet supported\n",
1000 vif->type);
1001 ret = -EOPNOTSUPP;
1002 goto out;
1003 }
6b3b991d 1004
4801416c
BG		 1005 if (ath9k_uses_beacons(vif->type)) {
1006 if (sc->nbcnvifs >= ATH_BCBUF) {
1007 ath_err(common, "Not enough beacon buffers when adding"
1008 " new interface of type: %i\n",
1009 vif->type);
1010 ret = -ENOBUFS;
1011 goto out;
1012 }
1013 }
1014
d2182b69 1015 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
4801416c 1016
4801416c
BG		 1017 sc->nvifs++;
1018
130ef6e9
SM		 1019 ath9k_calculate_summary_state(hw, vif);
1020 if (ath9k_uses_beacons(vif->type))
1021 ath9k_beacon_assign_slot(sc, vif);
1022
4801416c
BG		 1023out:
1024 mutex_unlock(&sc->mutex);
96f372c9 1025 ath9k_ps_restore(sc);
4801416c 1026 return ret;
6b3b991d
RM		 1027}
1028
1029static int ath9k_change_interface(struct ieee80211_hw *hw,
1030 struct ieee80211_vif *vif,
1031 enum nl80211_iftype new_type,
1032 bool p2p)
1033{
9ac58615 1034 struct ath_softc *sc = hw->priv;
6b3b991d 1035 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1036 int ret = 0;
6b3b991d 1037
d2182b69 1038 ath_dbg(common, CONFIG, "Change Interface\n");
130ef6e9 1039
6b3b991d 1040 mutex_lock(&sc->mutex);
96f372c9 1041 ath9k_ps_wakeup(sc);
6b3b991d 1042
4801416c
BG		 1043 if (ath9k_uses_beacons(new_type) &&
1044 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM		 1045 if (sc->nbcnvifs >= ATH_BCBUF) {
1046 ath_err(common, "No beacon slot available\n");
6dab55bf
DC		 1047 ret = -ENOBUFS;
1048 goto out;
6b3b991d 1049 }
6b3b991d 1050 }
4801416c 1051
4801416c 1052 if (ath9k_uses_beacons(vif->type))
130ef6e9 1053 ath9k_beacon_remove_slot(sc, vif);
4801416c 1054
6b3b991d
RM		 1055 vif->type = new_type;
1056 vif->p2p = p2p;
1057
130ef6e9
SM		 1058 ath9k_calculate_summary_state(hw, vif);
1059 if (ath9k_uses_beacons(vif->type))
1060 ath9k_beacon_assign_slot(sc, vif);
1061
6dab55bf 1062out:
96f372c9 1063 ath9k_ps_restore(sc);
6b3b991d 1064 mutex_unlock(&sc->mutex);
6dab55bf 1065 return ret;
6b3b991d
RM		 1066}
1067
8feceb67 1068static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1069 struct ieee80211_vif *vif)
f078f209 1070{
9ac58615 1071 struct ath_softc *sc = hw->priv;
c46917bb 1072 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1073
d2182b69 1074 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1075
96f372c9 1076 ath9k_ps_wakeup(sc);
141b38b6
S		 1077 mutex_lock(&sc->mutex);
1078
4801416c 1079 sc->nvifs--;
580f0b8a 1080
4801416c 1081 if (ath9k_uses_beacons(vif->type))
130ef6e9 1082 ath9k_beacon_remove_slot(sc, vif);
2c3db3d5 1083
4801416c 1084 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S		 1085
1086 mutex_unlock(&sc->mutex);
96f372c9 1087 ath9k_ps_restore(sc);
f078f209
LR		 1088}
1089
fbab7390 1090static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1091{
3069168c 1092 struct ath_hw *ah = sc->sc_ah;
ad128860 1093 struct ath_common *common = ath9k_hw_common(ah);
3069168c 1094
3f7c5c10 1095 sc->ps_enabled = true;
3069168c
PR		 1096 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1097 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1098 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1099 ath9k_hw_set_interrupts(ah);
3f7c5c10 1100 }
fdf76622 1101 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1102 }
ad128860 1103 ath_dbg(common, PS, "PowerSave enabled\n");
3f7c5c10
SB		 1104}
1105
845d708e
SB		 1106static void ath9k_disable_ps(struct ath_softc *sc)
1107{
1108 struct ath_hw *ah = sc->sc_ah;
ad128860 1109 struct ath_common *common = ath9k_hw_common(ah);
845d708e
SB		 1110
1111 sc->ps_enabled = false;
1112 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1113 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1114 ath9k_hw_setrxabort(ah, 0);
1115 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1116 PS_WAIT_FOR_CAB |
1117 PS_WAIT_FOR_PSPOLL_DATA |
1118 PS_WAIT_FOR_TX_ACK);
1119 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1120 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1121 ath9k_hw_set_interrupts(ah);
845d708e
SB		 1122 }
1123 }
ad128860 1124 ath_dbg(common, PS, "PowerSave disabled\n");
845d708e
SB		 1125}
1126
e8975581 1127static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1128{
9ac58615 1129 struct ath_softc *sc = hw->priv;
3430098a
FF		 1130 struct ath_hw *ah = sc->sc_ah;
1131 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1132 struct ieee80211_conf *conf = &hw->conf;
75600abf 1133 bool reset_channel = false;
f078f209 1134
c0c11741 1135 ath9k_ps_wakeup(sc);
aa33de09 1136 mutex_lock(&sc->mutex);
141b38b6 1137
daa1b6ee 1138 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1139 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
b73f3e78 1140 if (sc->ps_idle) {
daa1b6ee 1141 ath_cancel_work(sc);
b73f3e78
RM		 1142 ath9k_stop_btcoex(sc);
1143 } else {
1144 ath9k_start_btcoex(sc);
75600abf
FF		 1145 /*
1146 * The chip needs a reset to properly wake up from
1147 * full sleep
1148 */
1149 reset_channel = ah->chip_fullsleep;
b73f3e78 1150 }
daa1b6ee 1151 }
64839170 1152
e7824a50
LR		 1153 /*
1154 * We just prepare to enable PS. We have to wait until our AP has
1155 * ACK'd our null data frame to disable RX otherwise we'll ignore
1156 * those ACKs and end up retransmitting the same null data frames.
1157 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1158 */
3cbb5dd7 1159 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR		 1160 unsigned long flags;
1161 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB		 1162 if (conf->flags & IEEE80211_CONF_PS)
1163 ath9k_enable_ps(sc);
845d708e
SB		 1164 else
1165 ath9k_disable_ps(sc);
8ab2cd09 1166 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN		 1167 }
1168
199afd9d
S		 1169 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1170 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1171 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM		 1172 sc->sc_ah->is_monitoring = true;
1173 } else {
d2182b69 1174 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1175 sc->sc_ah->is_monitoring = false;
199afd9d
S		 1176 }
1177 }
1178
75600abf 1179 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
99405f93 1180 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1181 int pos = curchan->hw_value;
3430098a
FF		 1182 int old_pos = -1;
1183 unsigned long flags;
1184
1185 if (ah->curchan)
1186 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1187
d2182b69 1188 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
8c79a610 1189 curchan->center_freq, conf->channel_type);
f078f209 1190
3430098a
FF		 1191 /* update survey stats for the old channel before switching */
1192 spin_lock_irqsave(&common->cc_lock, flags);
1193 ath_update_survey_stats(sc);
1194 spin_unlock_irqrestore(&common->cc_lock, flags);
1195
e338a85e
RM		 1196 /*
1197 * Preserve the current channel values, before updating
1198 * the same channel
1199 */
1a19f77f
RM		 1200 if (ah->curchan && (old_pos == pos))
1201 ath9k_hw_getnf(ah, ah->curchan);
e338a85e
RM		 1202
1203 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1204 curchan, conf->channel_type);
1205
3430098a
FF		 1206 /*
1207 * If the operating channel changes, change the survey in-use flags
1208 * along with it.
1209 * Reset the survey data for the new channel, unless we're switching
1210 * back to the operating channel from an off-channel operation.
1211 */
1212 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1213 sc->cur_survey != &sc->survey[pos]) {
1214
1215 if (sc->cur_survey)
1216 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1217
1218 sc->cur_survey = &sc->survey[pos];
1219
1220 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1221 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1222 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1223 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1224 }
1225
0e2dedf9 1226 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1227 ath_err(common, "Unable to set channel\n");
aa33de09 1228 mutex_unlock(&sc->mutex);
8389fb3f 1229 ath9k_ps_restore(sc);
e11602b7
S		 1230 return -EINVAL;
1231 }
3430098a
FF		 1232
1233 /*
1234 * The most recent snapshot of channel->noisefloor for the old
1235 * channel is only available after the hardware reset. Copy it to
1236 * the survey stats now.
1237 */
1238 if (old_pos >= 0)
1239 ath_update_survey_nf(sc, old_pos);
094d05dc 1240 }
f078f209 1241
c9f6a656 1242 if (changed & IEEE80211_CONF_CHANGE_POWER) {
d2182b69 1243 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
17d7904d 1244 sc->config.txpowlimit = 2 * conf->power_level;
5048e8c3
RM		 1245 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1246 sc->config.txpowlimit, &sc->curtxpow);
64839170
LR		 1247 }
1248
aa33de09 1249 mutex_unlock(&sc->mutex);
c0c11741 1250 ath9k_ps_restore(sc);
141b38b6 1251
f078f209
LR		 1252 return 0;
1253}
1254
8feceb67
VT		 1255#define SUPPORTED_FILTERS \
1256 (FIF_PROMISC_IN_BSS | \
1257 FIF_ALLMULTI | \
1258 FIF_CONTROL | \
af6a3fc7 1259 FIF_PSPOLL | \
8feceb67
VT		 1260 FIF_OTHER_BSS | \
1261 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1262 FIF_PROBE_REQ | \
8feceb67 1263 FIF_FCSFAIL)
c83be688 1264
8feceb67
VT		 1265/* FIXME: sc->sc_full_reset ? */
1266static void ath9k_configure_filter(struct ieee80211_hw *hw,
1267 unsigned int changed_flags,
1268 unsigned int *total_flags,
3ac64bee 1269 u64 multicast)
8feceb67 1270{
9ac58615 1271 struct ath_softc *sc = hw->priv;
8feceb67 1272 u32 rfilt;
f078f209 1273
8feceb67
VT		 1274 changed_flags &= SUPPORTED_FILTERS;
1275 *total_flags &= SUPPORTED_FILTERS;
f078f209 1276
b77f483f 1277 sc->rx.rxfilter = *total_flags;
aa68aeaa 1278 ath9k_ps_wakeup(sc);
8feceb67
VT		 1279 rfilt = ath_calcrxfilter(sc);
1280 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1281 ath9k_ps_restore(sc);
f078f209 1282
d2182b69
JP		 1283 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1284 rfilt);
8feceb67 1285}
f078f209 1286
4ca77860
JB		 1287static int ath9k_sta_add(struct ieee80211_hw *hw,
1288 struct ieee80211_vif *vif,
1289 struct ieee80211_sta *sta)
8feceb67 1290{
9ac58615 1291 struct ath_softc *sc = hw->priv;
93ae2dd2
FF		 1292 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1293 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1294 struct ieee80211_key_conf ps_key = { };
f078f209 1295
7e1e3864 1296 ath_node_attach(sc, sta, vif);
f59a59fe
FF		 1297
1298 if (vif->type != NL80211_IFTYPE_AP &&
1299 vif->type != NL80211_IFTYPE_AP_VLAN)
1300 return 0;
1301
93ae2dd2 1302 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB		 1303
1304 return 0;
1305}
1306
93ae2dd2
FF		 1307static void ath9k_del_ps_key(struct ath_softc *sc,
1308 struct ieee80211_vif *vif,
1309 struct ieee80211_sta *sta)
1310{
1311 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1312 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1313 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1314
1315 if (!an->ps_key)
1316 return;
1317
1318 ath_key_delete(common, &ps_key);
1319}
1320
4ca77860
JB		 1321static int ath9k_sta_remove(struct ieee80211_hw *hw,
1322 struct ieee80211_vif *vif,
1323 struct ieee80211_sta *sta)
1324{
9ac58615 1325 struct ath_softc *sc = hw->priv;
4ca77860 1326
93ae2dd2 1327 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB		 1328 ath_node_detach(sc, sta);
1329
1330 return 0;
f078f209
LR		 1331}
1332
5519541d
FF		 1333static void ath9k_sta_notify(struct ieee80211_hw *hw,
1334 struct ieee80211_vif *vif,
1335 enum sta_notify_cmd cmd,
1336 struct ieee80211_sta *sta)
1337{
1338 struct ath_softc *sc = hw->priv;
1339 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1340
3d4e20f2 1341 if (!sta->ht_cap.ht_supported)
b25bfda3
MSS		 1342 return;
1343
5519541d
FF		 1344 switch (cmd) {
1345 case STA_NOTIFY_SLEEP:
1346 an->sleeping = true;
042ec453 1347 ath_tx_aggr_sleep(sta, sc, an);
5519541d
FF		 1348 break;
1349 case STA_NOTIFY_AWAKE:
1350 an->sleeping = false;
1351 ath_tx_aggr_wakeup(sc, an);
1352 break;
1353 }
1354}
1355
8a3a3c85
EP		 1356static int ath9k_conf_tx(struct ieee80211_hw *hw,
1357 struct ieee80211_vif *vif, u16 queue,
8feceb67 1358 const struct ieee80211_tx_queue_params *params)
f078f209 1359{
9ac58615 1360 struct ath_softc *sc = hw->priv;
c46917bb 1361 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1362 struct ath_txq *txq;
8feceb67 1363 struct ath9k_tx_queue_info qi;
066dae93 1364 int ret = 0;
f078f209 1365
8feceb67
VT		 1366 if (queue >= WME_NUM_AC)
1367 return 0;
f078f209 1368
066dae93
FF		 1369 txq = sc->tx.txq_map[queue];
1370
96f372c9 1371 ath9k_ps_wakeup(sc);
141b38b6
S		 1372 mutex_lock(&sc->mutex);
1373
1ffb0610
S		 1374 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1375
8feceb67
VT		 1376 qi.tqi_aifs = params->aifs;
1377 qi.tqi_cwmin = params->cw_min;
1378 qi.tqi_cwmax = params->cw_max;
531bd079 1379 qi.tqi_burstTime = params->txop * 32;
f078f209 1380
d2182b69 1381 ath_dbg(common, CONFIG,
226afe68
JP		 1382 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1383 queue, txq->axq_qnum, params->aifs, params->cw_min,
1384 params->cw_max, params->txop);
f078f209 1385
aa5955c3 1386 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
066dae93 1387 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1388 if (ret)
3800276a 1389 ath_err(common, "TXQ Update failed\n");
f078f209 1390
141b38b6 1391 mutex_unlock(&sc->mutex);
96f372c9 1392 ath9k_ps_restore(sc);
141b38b6 1393
8feceb67
VT		 1394 return ret;
1395}
f078f209 1396
8feceb67
VT		 1397static int ath9k_set_key(struct ieee80211_hw *hw,
1398 enum set_key_cmd cmd,
dc822b5d
JB		 1399 struct ieee80211_vif *vif,
1400 struct ieee80211_sta *sta,
8feceb67
VT		 1401 struct ieee80211_key_conf *key)
1402{
9ac58615 1403 struct ath_softc *sc = hw->priv;
c46917bb 1404 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1405 int ret = 0;
f078f209 1406
3e6109c5 1407 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM		 1408 return -ENOSPC;
1409
5bd5e9a6
CYY		 1410 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1411 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM		 1412 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1413 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1414 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1415 /*
1416 * For now, disable hw crypto for the RSN IBSS group keys. This
1417 * could be optimized in the future to use a modified key cache
1418 * design to support per-STA RX GTK, but until that gets
1419 * implemented, use of software crypto for group addressed
1420 * frames is a acceptable to allow RSN IBSS to be used.
1421 */
1422 return -EOPNOTSUPP;
1423 }
1424
141b38b6 1425 mutex_lock(&sc->mutex);
3cbb5dd7 1426 ath9k_ps_wakeup(sc);
d2182b69 1427 ath_dbg(common, CONFIG, "Set HW Key\n");
f078f209 1428
8feceb67
VT		 1429 switch (cmd) {
1430 case SET_KEY:
93ae2dd2
FF		 1431 if (sta)
1432 ath9k_del_ps_key(sc, vif, sta);
1433
040e539e 1434 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM		 1435 if (ret >= 0) {
1436 key->hw_key_idx = ret;
8feceb67
VT		 1437 /* push IV and Michael MIC generation to stack */
1438 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1439 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1440 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB		 1441 if (sc->sc_ah->sw_mgmt_crypto &&
1442 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1443 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1444 ret = 0;
8feceb67
VT		 1445 }
1446 break;
1447 case DISABLE_KEY:
040e539e 1448 ath_key_delete(common, key);
8feceb67
VT		 1449 break;
1450 default:
1451 ret = -EINVAL;
1452 }
f078f209 1453
3cbb5dd7 1454 ath9k_ps_restore(sc);
141b38b6
S		 1455 mutex_unlock(&sc->mutex);
1456
8feceb67
VT		 1457 return ret;
1458}
6c43c090
SM		 1459
1460static void ath9k_set_assoc_state(struct ath_softc *sc,
1461 struct ieee80211_vif *vif)
4f5ef75b 1462{
4f5ef75b 1463 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4f5ef75b 1464 struct ath_vif *avp = (void *)vif->drv_priv;
6c43c090 1465 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
07c15a3f 1466 unsigned long flags;
6c43c090
SM		 1467
1468 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1469 avp->primary_sta_vif = true;
1470
2e5ef459 1471 /*
6c43c090
SM		 1472 * Set the AID, BSSID and do beacon-sync only when
1473 * the HW opmode is STATION.
1474 *
1475 * But the primary bit is set above in any case.
2e5ef459 1476 */
6c43c090 1477 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
2e5ef459
RM		 1478 return;
1479
6c43c090
SM		 1480 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1481 common->curaid = bss_conf->aid;
1482 ath9k_hw_write_associd(sc->sc_ah);
07c15a3f 1483
6c43c090
SM		 1484 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1485 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1486
6c43c090
SM		 1487 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1488 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1489 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
05c0be2f 1490
6c43c090
SM		 1491 ath_dbg(common, CONFIG,
1492 "Primary Station interface: %pM, BSSID: %pM\n",
1493 vif->addr, common->curbssid);
4f5ef75b
RM		 1494}
1495
6c43c090 1496static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
4f5ef75b 1497{
6c43c090 1498 struct ath_softc *sc = data;
4f5ef75b 1499 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
4f5ef75b 1500
6c43c090 1501 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
2e5ef459
RM		 1502 return;
1503
6c43c090
SM		 1504 if (bss_conf->assoc)
1505 ath9k_set_assoc_state(sc, vif);
4f5ef75b 1506}
f078f209 1507
8feceb67
VT		 1508static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1509 struct ieee80211_vif *vif,
1510 struct ieee80211_bss_conf *bss_conf,
1511 u32 changed)
1512{
da0d45f7
SM		 1513#define CHECK_ANI \
1514 (BSS_CHANGED_ASSOC | \
1515 BSS_CHANGED_IBSS | \
1516 BSS_CHANGED_BEACON_ENABLED)
1517
9ac58615 1518 struct ath_softc *sc = hw->priv;
2d0ddec5 1519 struct ath_hw *ah = sc->sc_ah;
1510718d 1520 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1521 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1522 int slottime;
f078f209 1523
96f372c9 1524 ath9k_ps_wakeup(sc);
141b38b6
S		 1525 mutex_lock(&sc->mutex);
1526
9f61903c 1527 if (changed & BSS_CHANGED_ASSOC) {
6c43c090
SM		 1528 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1529 bss_conf->bssid, bss_conf->assoc);
1530
1531 if (avp->primary_sta_vif && !bss_conf->assoc) {
1532 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1533 avp->primary_sta_vif = false;
1534
1535 if (ah->opmode == NL80211_IFTYPE_STATION)
1536 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1537 }
1538
1539 ieee80211_iterate_active_interfaces_atomic(sc->hw,
1540 ath9k_bss_assoc_iter, sc);
2d0ddec5 1541
6c43c090
SM		 1542 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
1543 ah->opmode == NL80211_IFTYPE_STATION) {
1544 memset(common->curbssid, 0, ETH_ALEN);
1545 common->curaid = 0;
1546 ath9k_hw_write_associd(sc->sc_ah);
1547 }
c6089ccc 1548 }
2d0ddec5 1549
2e5ef459 1550 if (changed & BSS_CHANGED_IBSS) {
2e5ef459
RM		 1551 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1552 common->curaid = bss_conf->aid;
1553 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459
RM		 1554 }
1555
ef4ad633
SM		 1556 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1557 (changed & BSS_CHANGED_BEACON_INT)) {
2f8e82e8
SM		 1558 if (ah->opmode == NL80211_IFTYPE_AP &&
1559 bss_conf->enable_beacon)
1560 ath9k_set_tsfadjust(sc, vif);
ef4ad633
SM		 1561 if (ath9k_allow_beacon_config(sc, vif))
1562 ath9k_beacon_config(sc, vif, changed);
0005baf4
FF		 1563 }
1564
1565 if (changed & BSS_CHANGED_ERP_SLOT) {
1566 if (bss_conf->use_short_slot)
1567 slottime = 9;
1568 else
1569 slottime = 20;
1570 if (vif->type == NL80211_IFTYPE_AP) {
1571 /*
1572 * Defer update, so that connected stations can adjust
1573 * their settings at the same time.
1574 * See beacon.c for more details
1575 */
1576 sc->beacon.slottime = slottime;
1577 sc->beacon.updateslot = UPDATE;
1578 } else {
1579 ah->slottime = slottime;
1580 ath9k_hw_init_global_settings(ah);
1581 }
2d0ddec5
JB		 1582 }
1583
da0d45f7
SM		 1584 if (changed & CHECK_ANI)
1585 ath_check_ani(sc);
1586
141b38b6 1587 mutex_unlock(&sc->mutex);
96f372c9 1588 ath9k_ps_restore(sc);
da0d45f7
SM		 1589
1590#undef CHECK_ANI
8feceb67 1591}
f078f209 1592
37a41b4a 1593static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1594{
9ac58615 1595 struct ath_softc *sc = hw->priv;
8feceb67 1596 u64 tsf;
f078f209 1597
141b38b6 1598 mutex_lock(&sc->mutex);
9abbfb27 1599 ath9k_ps_wakeup(sc);
141b38b6 1600 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 1601 ath9k_ps_restore(sc);
141b38b6 1602 mutex_unlock(&sc->mutex);
f078f209 1603
8feceb67
VT		 1604 return tsf;
1605}
f078f209 1606
37a41b4a
EP		 1607static void ath9k_set_tsf(struct ieee80211_hw *hw,
1608 struct ieee80211_vif *vif,
1609 u64 tsf)
3b5d665b 1610{
9ac58615 1611 struct ath_softc *sc = hw->priv;
3b5d665b 1612
141b38b6 1613 mutex_lock(&sc->mutex);
9abbfb27 1614 ath9k_ps_wakeup(sc);
141b38b6 1615 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 1616 ath9k_ps_restore(sc);
141b38b6 1617 mutex_unlock(&sc->mutex);
3b5d665b
AF		 1618}
1619
37a41b4a 1620static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1621{
9ac58615 1622 struct ath_softc *sc = hw->priv;
c83be688 1623
141b38b6 1624 mutex_lock(&sc->mutex);
21526d57
LR		 1625
1626 ath9k_ps_wakeup(sc);
141b38b6 1627 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 1628 ath9k_ps_restore(sc);
1629
141b38b6 1630 mutex_unlock(&sc->mutex);
8feceb67 1631}
f078f209 1632
8feceb67 1633static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1634 struct ieee80211_vif *vif,
141b38b6
S		 1635 enum ieee80211_ampdu_mlme_action action,
1636 struct ieee80211_sta *sta,
0b01f030 1637 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 1638{
9ac58615 1639 struct ath_softc *sc = hw->priv;
8feceb67 1640 int ret = 0;
f078f209 1641
85ad181e
JB		 1642 local_bh_disable();
1643
8feceb67
VT		 1644 switch (action) {
1645 case IEEE80211_AMPDU_RX_START:
8feceb67
VT		 1646 break;
1647 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 1648 break;
1649 case IEEE80211_AMPDU_TX_START:
8b685ba9 1650 ath9k_ps_wakeup(sc);
231c3a1f
FF		 1651 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1652 if (!ret)
1653 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1654 ath9k_ps_restore(sc);
8feceb67
VT		 1655 break;
1656 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 1657 ath9k_ps_wakeup(sc);
f83da965 1658 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 1659 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1660 ath9k_ps_restore(sc);
8feceb67 1661 break;
b1720231 1662 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1663 ath9k_ps_wakeup(sc);
8469cdef 1664 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1665 ath9k_ps_restore(sc);
8469cdef 1666 break;
8feceb67 1667 default:
3800276a 1668 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT		 1669 }
1670
85ad181e
JB		 1671 local_bh_enable();
1672
8feceb67 1673 return ret;
f078f209
LR		 1674}
1675
62dad5b0
BP		 1676static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1677 struct survey_info *survey)
1678{
9ac58615 1679 struct ath_softc *sc = hw->priv;
3430098a 1680 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 1681 struct ieee80211_supported_band *sband;
3430098a
FF		 1682 struct ieee80211_channel *chan;
1683 unsigned long flags;
1684 int pos;
1685
1686 spin_lock_irqsave(&common->cc_lock, flags);
1687 if (idx == 0)
1688 ath_update_survey_stats(sc);
39162dbe
FF		 1689
1690 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1691 if (sband && idx >= sband->n_channels) {
1692 idx -= sband->n_channels;
1693 sband = NULL;
1694 }
62dad5b0 1695
39162dbe
FF		 1696 if (!sband)
1697 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 1698
3430098a
FF		 1699 if (!sband || idx >= sband->n_channels) {
1700 spin_unlock_irqrestore(&common->cc_lock, flags);
1701 return -ENOENT;
4f1a5a4b 1702 }
62dad5b0 1703
3430098a
FF		 1704 chan = &sband->channels[idx];
1705 pos = chan->hw_value;
1706 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1707 survey->channel = chan;
1708 spin_unlock_irqrestore(&common->cc_lock, flags);
1709
62dad5b0
BP		 1710 return 0;
1711}
1712
e239d859
FF		 1713static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1714{
9ac58615 1715 struct ath_softc *sc = hw->priv;
e239d859
FF		 1716 struct ath_hw *ah = sc->sc_ah;
1717
1718 mutex_lock(&sc->mutex);
1719 ah->coverage_class = coverage_class;
8b2a3827
MSS		 1720
1721 ath9k_ps_wakeup(sc);
e239d859 1722 ath9k_hw_init_global_settings(ah);
8b2a3827
MSS		 1723 ath9k_ps_restore(sc);
1724
e239d859
FF		 1725 mutex_unlock(&sc->mutex);
1726}
1727
69081624
VT		 1728static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
1729{
69081624 1730 struct ath_softc *sc = hw->priv;
99aa55b6
MSS		 1731 struct ath_hw *ah = sc->sc_ah;
1732 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF		 1733 int timeout = 200; /* ms */
1734 int i, j;
2f6fc351 1735 bool drain_txq;
69081624
VT		 1736
1737 mutex_lock(&sc->mutex);
69081624
VT		 1738 cancel_delayed_work_sync(&sc->tx_complete_work);
1739
6a6b3f3e 1740 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 1741 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS		 1742 mutex_unlock(&sc->mutex);
1743 return;
1744 }
1745
781b14a3 1746 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
d2182b69 1747 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS		 1748 mutex_unlock(&sc->mutex);
1749 return;
1750 }
1751
86271e46 1752 for (j = 0; j < timeout; j++) {
108697c4 1753 bool npend = false;
86271e46
FF		 1754
1755 if (j)
1756 usleep_range(1000, 2000);
69081624 1757
86271e46
FF		 1758 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1759 if (!ATH_TXQ_SETUP(sc, i))
1760 continue;
1761
108697c4
MSS		 1762 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1763
1764 if (npend)
1765 break;
69081624 1766 }
86271e46
FF		 1767
1768 if (!npend)
9df0d6a2 1769 break;
69081624
VT		 1770 }
1771
9df0d6a2
FF		 1772 if (drop) {
1773 ath9k_ps_wakeup(sc);
1774 spin_lock_bh(&sc->sc_pcu_lock);
1775 drain_txq = ath_drain_all_txq(sc, false);
1776 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 1777
9df0d6a2
FF		 1778 if (!drain_txq)
1779 ath_reset(sc, false);
9adcf440 1780
9df0d6a2
FF		 1781 ath9k_ps_restore(sc);
1782 ieee80211_wake_queues(hw);
1783 }
d78f4b3e 1784
69081624
VT		 1785 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1786 mutex_unlock(&sc->mutex);
1787}
1788
15b91e83
VN		 1789static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1790{
1791 struct ath_softc *sc = hw->priv;
1792 int i;
1793
1794 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1795 if (!ATH_TXQ_SETUP(sc, i))
1796 continue;
1797
1798 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1799 return true;
1800 }
1801 return false;
1802}
1803
5595f119 1804static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF		 1805{
1806 struct ath_softc *sc = hw->priv;
1807 struct ath_hw *ah = sc->sc_ah;
1808 struct ieee80211_vif *vif;
1809 struct ath_vif *avp;
1810 struct ath_buf *bf;
1811 struct ath_tx_status ts;
4286df60 1812 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF		 1813 int status;
1814
1815 vif = sc->beacon.bslot[0];
1816 if (!vif)
1817 return 0;
1818
aa45fe96 1819 if (!vif->bss_conf.enable_beacon)
ba4903f9
FF		 1820 return 0;
1821
aa45fe96
SM		 1822 avp = (void *)vif->drv_priv;
1823
4286df60 1824 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF		 1825 tasklet_disable(&sc->bcon_tasklet);
1826
1827 bf = avp->av_bcbuf;
1828 if (!bf || !bf->bf_mpdu)
1829 goto skip;
1830
1831 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1832 if (status == -EINPROGRESS)
1833 goto skip;
1834
1835 sc->beacon.tx_processed = true;
1836 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1837
1838skip:
1839 tasklet_enable(&sc->bcon_tasklet);
1840 }
1841
1842 return sc->beacon.tx_last;
1843}
1844
52c94f41
MSS		 1845static int ath9k_get_stats(struct ieee80211_hw *hw,
1846 struct ieee80211_low_level_stats *stats)
1847{
1848 struct ath_softc *sc = hw->priv;
1849 struct ath_hw *ah = sc->sc_ah;
1850 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1851
1852 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1853 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1854 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1855 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1856 return 0;
1857}
1858
43c35284
FF		 1859static u32 fill_chainmask(u32 cap, u32 new)
1860{
1861 u32 filled = 0;
1862 int i;
1863
1864 for (i = 0; cap && new; i++, cap >>= 1) {
1865 if (!(cap & BIT(0)))
1866 continue;
1867
1868 if (new & BIT(0))
1869 filled |= BIT(i);
1870
1871 new >>= 1;
1872 }
1873
1874 return filled;
1875}
1876
5d9c7e3c
FF		 1877static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
1878{
1879 switch (val & 0x7) {
1880 case 0x1:
1881 case 0x3:
1882 case 0x7:
1883 return true;
1884 case 0x2:
1885 return (ah->caps.rx_chainmask == 1);
1886 default:
1887 return false;
1888 }
1889}
1890
43c35284
FF		 1891static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1892{
1893 struct ath_softc *sc = hw->priv;
1894 struct ath_hw *ah = sc->sc_ah;
1895
5d9c7e3c
FF		 1896 if (ah->caps.rx_chainmask != 1)
1897 rx_ant |= tx_ant;
1898
1899 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
43c35284
FF		 1900 return -EINVAL;
1901
1902 sc->ant_rx = rx_ant;
1903 sc->ant_tx = tx_ant;
1904
1905 if (ah->caps.rx_chainmask == 1)
1906 return 0;
1907
1908 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1909 if (AR_SREV_9100(ah))
1910 ah->rxchainmask = 0x7;
1911 else
1912 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1913
1914 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1915 ath9k_reload_chainmask_settings(sc);
1916
1917 return 0;
1918}
1919
1920static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1921{
1922 struct ath_softc *sc = hw->priv;
1923
1924 *tx_ant = sc->ant_tx;
1925 *rx_ant = sc->ant_rx;
1926 return 0;
1927}
1928
b90bd9d1
BG		 1929#ifdef CONFIG_ATH9K_DEBUGFS
1930
1931/* Ethtool support for get-stats */
1932
1933#define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
1934static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
1935 "tx_pkts_nic",
1936 "tx_bytes_nic",
1937 "rx_pkts_nic",
1938 "rx_bytes_nic",
1939 AMKSTR(d_tx_pkts),
1940 AMKSTR(d_tx_bytes),
1941 AMKSTR(d_tx_mpdus_queued),
1942 AMKSTR(d_tx_mpdus_completed),
1943 AMKSTR(d_tx_mpdu_xretries),
1944 AMKSTR(d_tx_aggregates),
1945 AMKSTR(d_tx_ampdus_queued_hw),
1946 AMKSTR(d_tx_ampdus_queued_sw),
1947 AMKSTR(d_tx_ampdus_completed),
1948 AMKSTR(d_tx_ampdu_retries),
1949 AMKSTR(d_tx_ampdu_xretries),
1950 AMKSTR(d_tx_fifo_underrun),
1951 AMKSTR(d_tx_op_exceeded),
1952 AMKSTR(d_tx_timer_expiry),
1953 AMKSTR(d_tx_desc_cfg_err),
1954 AMKSTR(d_tx_data_underrun),
1955 AMKSTR(d_tx_delim_underrun),
1956
1957 "d_rx_decrypt_crc_err",
1958 "d_rx_phy_err",
1959 "d_rx_mic_err",
1960 "d_rx_pre_delim_crc_err",
1961 "d_rx_post_delim_crc_err",
1962 "d_rx_decrypt_busy_err",
1963
1964 "d_rx_phyerr_radar",
1965 "d_rx_phyerr_ofdm_timing",
1966 "d_rx_phyerr_cck_timing",
1967
1968};
1969#define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
1970
1971static void ath9k_get_et_strings(struct ieee80211_hw *hw,
1972 struct ieee80211_vif *vif,
1973 u32 sset, u8 *data)
1974{
1975 if (sset == ETH_SS_STATS)
1976 memcpy(data, *ath9k_gstrings_stats,
1977 sizeof(ath9k_gstrings_stats));
1978}
1979
1980static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
1981 struct ieee80211_vif *vif, int sset)
1982{
1983 if (sset == ETH_SS_STATS)
1984 return ATH9K_SSTATS_LEN;
1985 return 0;
1986}
1987
1988#define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
1989#define AWDATA(elem) \
1990 do { \
1991 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
1992 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
1993 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
1994 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
1995 } while (0)
1996
1997#define AWDATA_RX(elem) \
1998 do { \
1999 data[i++] = sc->debug.stats.rxstats.elem; \
2000 } while (0)
2001
2002static void ath9k_get_et_stats(struct ieee80211_hw *hw,
2003 struct ieee80211_vif *vif,
2004 struct ethtool_stats *stats, u64 *data)
2005{
2006 struct ath_softc *sc = hw->priv;
2007 int i = 0;
2008
2009 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
2010 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
2011 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
2012 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
2013 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
2014 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
2015 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
2016 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
2017 AWDATA_RX(rx_pkts_all);
2018 AWDATA_RX(rx_bytes_all);
2019
2020 AWDATA(tx_pkts_all);
2021 AWDATA(tx_bytes_all);
2022 AWDATA(queued);
2023 AWDATA(completed);
2024 AWDATA(xretries);
2025 AWDATA(a_aggr);
2026 AWDATA(a_queued_hw);
2027 AWDATA(a_queued_sw);
2028 AWDATA(a_completed);
2029 AWDATA(a_retries);
2030 AWDATA(a_xretries);
2031 AWDATA(fifo_underrun);
2032 AWDATA(xtxop);
2033 AWDATA(timer_exp);
2034 AWDATA(desc_cfg_err);
2035 AWDATA(data_underrun);
2036 AWDATA(delim_underrun);
2037
2038 AWDATA_RX(decrypt_crc_err);
2039 AWDATA_RX(phy_err);
2040 AWDATA_RX(mic_err);
2041 AWDATA_RX(pre_delim_crc_err);
2042 AWDATA_RX(post_delim_crc_err);
2043 AWDATA_RX(decrypt_busy_err);
2044
2045 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
2046 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
2047 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
2048
2049 WARN_ON(i != ATH9K_SSTATS_LEN);
2050}
2051
2052/* End of ethtool get-stats functions */
2053
2054#endif
2055
2056
b11e640a
MSS		 2057#ifdef CONFIG_PM_SLEEP
2058
2059static void ath9k_wow_map_triggers(struct ath_softc *sc,
2060 struct cfg80211_wowlan *wowlan,
2061 u32 *wow_triggers)
2062{
2063 if (wowlan->disconnect)
2064 *wow_triggers |= AH_WOW_LINK_CHANGE |
2065 AH_WOW_BEACON_MISS;
2066 if (wowlan->magic_pkt)
2067 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
2068
2069 if (wowlan->n_patterns)
2070 *wow_triggers |= AH_WOW_USER_PATTERN_EN;
2071
2072 sc->wow_enabled = *wow_triggers;
2073
2074}
2075
2076static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
2077{
2078 struct ath_hw *ah = sc->sc_ah;
2079 struct ath_common *common = ath9k_hw_common(ah);
2080 struct ath9k_hw_capabilities *pcaps = &ah->caps;
2081 int pattern_count = 0;
2082 int i, byte_cnt;
2083 u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
2084 u8 dis_deauth_mask[MAX_PATTERN_SIZE];
2085
2086 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
2087 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
2088
2089 /*
2090 * Create Dissassociate / Deauthenticate packet filter
2091 *
2092 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
2093 * +--------------+----------+---------+--------+--------+----
2094 * + Frame Control+ Duration + DA + SA + BSSID +
2095 * +--------------+----------+---------+--------+--------+----
2096 *
2097 * The above is the management frame format for disassociate/
2098 * deauthenticate pattern, from this we need to match the first byte
2099 * of 'Frame Control' and DA, SA, and BSSID fields
2100 * (skipping 2nd byte of FC and Duration feild.
2101 *
2102 * Disassociate pattern
2103 * --------------------
2104 * Frame control = 00 00 1010
2105 * DA, SA, BSSID = x:x:x:x:x:x
2106 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2107 * | x:x:x:x:x:x -- 22 bytes
2108 *
2109 * Deauthenticate pattern
2110 * ----------------------
2111 * Frame control = 00 00 1100
2112 * DA, SA, BSSID = x:x:x:x:x:x
2113 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2114 * | x:x:x:x:x:x -- 22 bytes
2115 */
2116
2117 /* Create Disassociate Pattern first */
2118
2119 byte_cnt = 0;
2120
2121 /* Fill out the mask with all FF's */
2122
2123 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2124 dis_deauth_mask[i] = 0xff;
2125
2126 /* copy the first byte of frame control field */
2127 dis_deauth_pattern[byte_cnt] = 0xa0;
2128 byte_cnt++;
2129
2130 /* skip 2nd byte of frame control and Duration field */
2131 byte_cnt += 3;
2132
2133 /*
2134 * need not match the destination mac address, it can be a broadcast
2135 * mac address or an unicast to this station
2136 */
2137 byte_cnt += 6;
2138
2139 /* copy the source mac address */
2140 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2141
2142 byte_cnt += 6;
2143
2144 /* copy the bssid, its same as the source mac address */
2145
2146 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2147
2148 /* Create Disassociate pattern mask */
2149
2150 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
2151
2152 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
2153 /*
2154 * for AR9280, because of hardware limitation, the
2155 * first 4 bytes have to be matched for all patterns.
2156 * the mask for disassociation and de-auth pattern
2157 * matching need to enable the first 4 bytes.
2158 * also the duration field needs to be filled.
2159 */
2160 dis_deauth_mask[0] = 0xf0;
2161
2162 /*
2163 * fill in duration field
2164 FIXME: what is the exact value ?
2165 */
2166 dis_deauth_pattern[2] = 0xff;
2167 dis_deauth_pattern[3] = 0xff;
2168 } else {
2169 dis_deauth_mask[0] = 0xfe;
2170 }
2171
2172 dis_deauth_mask[1] = 0x03;
2173 dis_deauth_mask[2] = 0xc0;
2174 } else {
2175 dis_deauth_mask[0] = 0xef;
2176 dis_deauth_mask[1] = 0x3f;
2177 dis_deauth_mask[2] = 0x00;
2178 dis_deauth_mask[3] = 0xfc;
2179 }
2180
2181 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2182
2183 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2184 pattern_count, byte_cnt);
2185
2186 pattern_count++;
2187 /*
2188 * for de-authenticate pattern, only the first byte of the frame
2189 * control field gets changed from 0xA0 to 0xC0
2190 */
2191 dis_deauth_pattern[0] = 0xC0;
2192
2193 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2194 pattern_count, byte_cnt);
2195
2196}
2197
2198static void ath9k_wow_add_pattern(struct ath_softc *sc,
2199 struct cfg80211_wowlan *wowlan)
2200{
2201 struct ath_hw *ah = sc->sc_ah;
2202 struct ath9k_wow_pattern *wow_pattern = NULL;
2203 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
2204 int mask_len;
2205 s8 i = 0;
2206
2207 if (!wowlan->n_patterns)
2208 return;
2209
2210 /*
2211 * Add the new user configured patterns
2212 */
2213 for (i = 0; i < wowlan->n_patterns; i++) {
2214
2215 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2216
2217 if (!wow_pattern)
2218 return;
2219
2220 /*
2221 * TODO: convert the generic user space pattern to
2222 * appropriate chip specific/802.11 pattern.
2223 */
2224
2225 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2226 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2227 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2228 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2229 patterns[i].pattern_len);
2230 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2231 wow_pattern->pattern_len = patterns[i].pattern_len;
2232
2233 /*
2234 * just need to take care of deauth and disssoc pattern,
2235 * make sure we don't overwrite them.
2236 */
2237
2238 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2239 wow_pattern->mask_bytes,
2240 i + 2,
2241 wow_pattern->pattern_len);
2242 kfree(wow_pattern);
2243
2244 }
2245
2246}
2247
2248static int ath9k_suspend(struct ieee80211_hw *hw,
2249 struct cfg80211_wowlan *wowlan)
2250{
2251 struct ath_softc *sc = hw->priv;
2252 struct ath_hw *ah = sc->sc_ah;
2253 struct ath_common *common = ath9k_hw_common(ah);
2254 u32 wow_triggers_enabled = 0;
2255 int ret = 0;
2256
2257 mutex_lock(&sc->mutex);
2258
2259 ath_cancel_work(sc);
2260 del_timer_sync(&common->ani.timer);
2261 del_timer_sync(&sc->rx_poll_timer);
2262
2263 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2264 ath_dbg(common, ANY, "Device not present\n");
2265 ret = -EINVAL;
2266 goto fail_wow;
2267 }
2268
2269 if (WARN_ON(!wowlan)) {
2270 ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2271 ret = -EINVAL;
2272 goto fail_wow;
2273 }
2274
2275 if (!device_can_wakeup(sc->dev)) {
2276 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2277 ret = 1;
2278 goto fail_wow;
2279 }
2280
2281 /*
2282 * none of the sta vifs are associated
2283 * and we are not currently handling multivif
2284 * cases, for instance we have to seperately
2285 * configure 'keep alive frame' for each
2286 * STA.
2287 */
2288
2289 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2290 ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2291 ret = 1;
2292 goto fail_wow;
2293 }
2294
2295 if (sc->nvifs > 1) {
2296 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2297 ret = 1;
2298 goto fail_wow;
2299 }
2300
2301 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2302
2303 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2304 wow_triggers_enabled);
2305
2306 ath9k_ps_wakeup(sc);
2307
2308 ath9k_stop_btcoex(sc);
2309
2310 /*
2311 * Enable wake up on recieving disassoc/deauth
2312 * frame by default.
2313 */
2314 ath9k_wow_add_disassoc_deauth_pattern(sc);
2315
2316 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2317 ath9k_wow_add_pattern(sc, wowlan);
2318
2319 spin_lock_bh(&sc->sc_pcu_lock);
2320 /*
2321 * To avoid false wake, we enable beacon miss interrupt only
2322 * when we go to sleep. We save the current interrupt mask
2323 * so we can restore it after the system wakes up
2324 */
2325 sc->wow_intr_before_sleep = ah->imask;
2326 ah->imask &= ~ATH9K_INT_GLOBAL;
2327 ath9k_hw_disable_interrupts(ah);
2328 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2329 ath9k_hw_set_interrupts(ah);
2330 ath9k_hw_enable_interrupts(ah);
2331
2332 spin_unlock_bh(&sc->sc_pcu_lock);
2333
2334 /*
2335 * we can now sync irq and kill any running tasklets, since we already
2336 * disabled interrupts and not holding a spin lock
2337 */
2338 synchronize_irq(sc->irq);
2339 tasklet_kill(&sc->intr_tq);
2340
2341 ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2342
2343 ath9k_ps_restore(sc);
2344 ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2345 atomic_inc(&sc->wow_sleep_proc_intr);
2346
2347fail_wow:
2348 mutex_unlock(&sc->mutex);
2349 return ret;
2350}
2351
2352static int ath9k_resume(struct ieee80211_hw *hw)
2353{
2354 struct ath_softc *sc = hw->priv;
2355 struct ath_hw *ah = sc->sc_ah;
2356 struct ath_common *common = ath9k_hw_common(ah);
2357 u32 wow_status;
2358
2359 mutex_lock(&sc->mutex);
2360
2361 ath9k_ps_wakeup(sc);
2362
2363 spin_lock_bh(&sc->sc_pcu_lock);
2364
2365 ath9k_hw_disable_interrupts(ah);
2366 ah->imask = sc->wow_intr_before_sleep;
2367 ath9k_hw_set_interrupts(ah);
2368 ath9k_hw_enable_interrupts(ah);
2369
2370 spin_unlock_bh(&sc->sc_pcu_lock);
2371
2372 wow_status = ath9k_hw_wow_wakeup(ah);
2373
2374 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2375 /*
2376 * some devices may not pick beacon miss
2377 * as the reason they woke up so we add
2378 * that here for that shortcoming.
2379 */
2380 wow_status |= AH_WOW_BEACON_MISS;
2381 atomic_dec(&sc->wow_got_bmiss_intr);
2382 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2383 }
2384
2385 atomic_dec(&sc->wow_sleep_proc_intr);
2386
2387 if (wow_status) {
2388 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2389 ath9k_hw_wow_event_to_string(wow_status), wow_status);
2390 }
2391
2392 ath_restart_work(sc);
2393 ath9k_start_btcoex(sc);
2394
2395 ath9k_ps_restore(sc);
2396 mutex_unlock(&sc->mutex);
2397
2398 return 0;
2399}
2400
2401static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2402{
2403 struct ath_softc *sc = hw->priv;
2404
2405 mutex_lock(&sc->mutex);
2406 device_init_wakeup(sc->dev, 1);
2407 device_set_wakeup_enable(sc->dev, enabled);
2408 mutex_unlock(&sc->mutex);
2409}
2410
2411#endif
2412
6baff7f9 2413struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2414 .tx = ath9k_tx,
2415 .start = ath9k_start,
2416 .stop = ath9k_stop,
2417 .add_interface = ath9k_add_interface,
6b3b991d 2418 .change_interface = ath9k_change_interface,
8feceb67
VT		 2419 .remove_interface = ath9k_remove_interface,
2420 .config = ath9k_config,
8feceb67 2421 .configure_filter = ath9k_configure_filter,
4ca77860
JB		 2422 .sta_add = ath9k_sta_add,
2423 .sta_remove = ath9k_sta_remove,
5519541d 2424 .sta_notify = ath9k_sta_notify,
8feceb67 2425 .conf_tx = ath9k_conf_tx,
8feceb67 2426 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2427 .set_key = ath9k_set_key,
8feceb67 2428 .get_tsf = ath9k_get_tsf,
3b5d665b 2429 .set_tsf = ath9k_set_tsf,
8feceb67 2430 .reset_tsf = ath9k_reset_tsf,
4233df6b 2431 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2432 .get_survey = ath9k_get_survey,
3b319aae 2433 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2434 .set_coverage_class = ath9k_set_coverage_class,
69081624 2435 .flush = ath9k_flush,
15b91e83 2436 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41
MSS		 2437 .tx_last_beacon = ath9k_tx_last_beacon,
2438 .get_stats = ath9k_get_stats,
43c35284
FF		 2439 .set_antenna = ath9k_set_antenna,
2440 .get_antenna = ath9k_get_antenna,
b90bd9d1 2441
b11e640a
MSS		 2442#ifdef CONFIG_PM_SLEEP
2443 .suspend = ath9k_suspend,
2444 .resume = ath9k_resume,
2445 .set_wakeup = ath9k_set_wakeup,
2446#endif
2447
b90bd9d1
BG		 2448#ifdef CONFIG_ATH9K_DEBUGFS
2449 .get_et_sset_count = ath9k_get_et_sset_count,
2450 .get_et_stats = ath9k_get_et_stats,
2451 .get_et_strings = ath9k_get_et_strings,
2452#endif
8feceb67 2453};
Linux kernel - Deliverables
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