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iwlwifi: remove rs_get_rate workaround
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
eeddfd9d 38 .max_power = 20, \
5f8e077c
LR		 39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
eeddfd9d 45 .max_power = 20, \
5f8e077c
LR		 46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
4f0fc7c3 192 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
82880a7c
VT		 234static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
236{
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
239 u8 chan_idx;
240
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
244 return channel;
245}
246
ff37e337
S		 247/*
248 * Set/change channels. If the channel is really being changed, it's done
249 * by reseting the chip. To accomplish this we must first cleanup any pending
250 * DMA, then restart stuff.
251*/
0e2dedf9
JM		 252int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
253 struct ath9k_channel *hchan)
ff37e337 254{
cbe61d8a 255 struct ath_hw *ah = sc->sc_ah;
ff37e337 256 bool fastcc = true, stopped;
ae8d2858
LR		 257 struct ieee80211_channel *channel = hw->conf.channel;
258 int r;
ff37e337
S		 259
260 if (sc->sc_flags & SC_OP_INVALID)
261 return -EIO;
262
3cbb5dd7
VN		 263 ath9k_ps_wakeup(sc);
264
c0d7c7af
LR		 265 /*
266 * This is only performed if the channel settings have
267 * actually changed.
268 *
269 * To switch channels clear any pending DMA operations;
270 * wait long enough for the RX fifo to drain, reset the
271 * hardware at the new frequency, and then re-enable
272 * the relevant bits of the h/w.
273 */
274 ath9k_hw_set_interrupts(ah, 0);
043a0405 275 ath_drain_all_txq(sc, false);
c0d7c7af 276 stopped = ath_stoprecv(sc);
ff37e337 277
c0d7c7af
LR		 278 /* XXX: do not flush receive queue here. We don't want
279 * to flush data frames already in queue because of
280 * changing channel. */
ff37e337 281
c0d7c7af
LR		 282 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
283 fastcc = false;
284
285 DPRINTF(sc, ATH_DBG_CONFIG,
286 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 287 sc->sc_ah->curchan->channel,
c0d7c7af 288 channel->center_freq, sc->tx_chan_width);
ff37e337 289
c0d7c7af
LR		 290 spin_lock_bh(&sc->sc_resetlock);
291
292 r = ath9k_hw_reset(ah, hchan, fastcc);
293 if (r) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to reset channel (%u Mhz) "
6b45784f 296 "reset status %d\n",
c0d7c7af
LR		 297 channel->center_freq, r);
298 spin_unlock_bh(&sc->sc_resetlock);
3989279c 299 goto ps_restore;
ff37e337 300 }
c0d7c7af
LR		 301 spin_unlock_bh(&sc->sc_resetlock);
302
c0d7c7af
LR		 303 sc->sc_flags &= ~SC_OP_FULL_RESET;
304
305 if (ath_startrecv(sc) != 0) {
306 DPRINTF(sc, ATH_DBG_FATAL,
307 "Unable to restart recv logic\n");
3989279c
GJ		 308 r = -EIO;
309 goto ps_restore;
c0d7c7af
LR		 310 }
311
312 ath_cache_conf_rate(sc, &hw->conf);
313 ath_update_txpow(sc);
17d7904d 314 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 315
316 ps_restore:
3cbb5dd7 317 ath9k_ps_restore(sc);
3989279c 318 return r;
ff37e337
S		 319}
320
321/*
322 * This routine performs the periodic noise floor calibration function
323 * that is used to adjust and optimize the chip performance. This
324 * takes environmental changes (location, temperature) into account.
325 * When the task is complete, it reschedules itself depending on the
326 * appropriate interval that was calculated.
327 */
328static void ath_ani_calibrate(unsigned long data)
329{
20977d3e
S		 330 struct ath_softc *sc = (struct ath_softc *)data;
331 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 332 bool longcal = false;
333 bool shortcal = false;
334 bool aniflag = false;
335 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 336 u32 cal_interval, short_cal_interval;
ff37e337 337
20977d3e
S		 338 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
339 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 340
341 /*
342 * don't calibrate when we're scanning.
343 * we are most likely not on our home channel.
344 */
e5f0921a 345 spin_lock(&sc->ani_lock);
0c98de65 346 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 347 goto set_timer;
ff37e337 348
1ffc1c61
JM		 349 /* Only calibrate if awake */
350 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
351 goto set_timer;
352
353 ath9k_ps_wakeup(sc);
354
ff37e337 355 /* Long calibration runs independently of short calibration. */
17d7904d 356 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 357 longcal = true;
04bd4638 358 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 359 sc->ani.longcal_timer = timestamp;
ff37e337
S		 360 }
361
17d7904d
S		 362 /* Short calibration applies only while caldone is false */
363 if (!sc->ani.caldone) {
20977d3e 364 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 365 shortcal = true;
04bd4638 366 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 367 sc->ani.shortcal_timer = timestamp;
368 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 369 }
370 } else {
17d7904d 371 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 372 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 373 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
374 if (sc->ani.caldone)
375 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 376 }
377 }
378
379 /* Verify whether we must check ANI */
20977d3e 380 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 381 aniflag = true;
17d7904d 382 sc->ani.checkani_timer = timestamp;
ff37e337
S		 383 }
384
385 /* Skip all processing if there's nothing to do. */
386 if (longcal || shortcal || aniflag) {
387 /* Call ANI routine if necessary */
388 if (aniflag)
20977d3e 389 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 390
391 /* Perform calibration if necessary */
392 if (longcal || shortcal) {
379f0440
S		 393 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
394 sc->rx_chainmask, longcal);
395
396 if (longcal)
397 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
398 ah->curchan);
399
400 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
401 ah->curchan->channel, ah->curchan->channelFlags,
402 sc->ani.noise_floor);
ff37e337
S		 403 }
404 }
405
1ffc1c61
JM		 406 ath9k_ps_restore(sc);
407
20977d3e 408set_timer:
e5f0921a 409 spin_unlock(&sc->ani_lock);
ff37e337
S		 410 /*
411 * Set timer interval based on previous results.
412 * The interval must be the shortest necessary to satisfy ANI,
413 * short calibration and long calibration.
414 */
aac9207e 415 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 416 if (sc->sc_ah->config.enable_ani)
aac9207e 417 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 418 if (!sc->ani.caldone)
20977d3e 419 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 420
17d7904d 421 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 422}
423
415f738e
S		 424static void ath_start_ani(struct ath_softc *sc)
425{
426 unsigned long timestamp = jiffies_to_msecs(jiffies);
427
428 sc->ani.longcal_timer = timestamp;
429 sc->ani.shortcal_timer = timestamp;
430 sc->ani.checkani_timer = timestamp;
431
432 mod_timer(&sc->ani.timer,
433 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
434}
435
ff37e337
S		 436/*
437 * Update tx/rx chainmask. For legacy association,
438 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 439 * the chainmask configuration, for bt coexistence, use
440 * the chainmask configuration even in legacy mode.
ff37e337 441 */
0e2dedf9 442void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 443{
c97c92d9 444 if (is_ht ||
2660b81a
S		 445 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
446 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
447 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 448 } else {
17d7904d
S		 449 sc->tx_chainmask = 1;
450 sc->rx_chainmask = 1;
ff37e337
S		 451 }
452
04bd4638 453 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 454 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 455}
456
457static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
458{
459 struct ath_node *an;
460
461 an = (struct ath_node *)sta->drv_priv;
462
87792efc 463 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 464 ath_tx_node_init(sc, an);
87792efc
S		 465 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
466 sta->ht_cap.ampdu_factor);
467 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
468 }
ff37e337
S		 469}
470
471static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
472{
473 struct ath_node *an = (struct ath_node *)sta->drv_priv;
474
475 if (sc->sc_flags & SC_OP_TXAGGR)
476 ath_tx_node_cleanup(sc, an);
477}
478
479static void ath9k_tasklet(unsigned long data)
480{
481 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 482 u32 status = sc->intrstatus;
ff37e337 483
153e080d
VT		 484 ath9k_ps_wakeup(sc);
485
ff37e337 486 if (status & ATH9K_INT_FATAL) {
ff37e337 487 ath_reset(sc, false);
153e080d 488 ath9k_ps_restore(sc);
ff37e337 489 return;
063d8be3 490 }
ff37e337 491
063d8be3
S		 492 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
493 spin_lock_bh(&sc->rx.rxflushlock);
494 ath_rx_tasklet(sc, 0);
495 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 496 }
497
063d8be3
S		 498 if (status & ATH9K_INT_TX)
499 ath_tx_tasklet(sc);
500
54ce846e
JM		 501 if ((status & ATH9K_INT_TSFOOR) &&
502 (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
503 /*
504 * TSF sync does not look correct; remain awake to sync with
505 * the next Beacon.
506 */
507 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 508 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 509 }
510
ff37e337 511 /* re-enable hardware interrupt */
17d7904d 512 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
153e080d 513 ath9k_ps_restore(sc);
ff37e337
S		 514}
515
6baff7f9 516irqreturn_t ath_isr(int irq, void *dev)
ff37e337 517{
063d8be3
S		 518#define SCHED_INTR ( \
519 ATH9K_INT_FATAL | \
520 ATH9K_INT_RXORN | \
521 ATH9K_INT_RXEOL | \
522 ATH9K_INT_RX | \
523 ATH9K_INT_TX | \
524 ATH9K_INT_BMISS | \
525 ATH9K_INT_CST | \
526 ATH9K_INT_TSFOOR)
527
ff37e337 528 struct ath_softc *sc = dev;
cbe61d8a 529 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 530 enum ath9k_int status;
531 bool sched = false;
532
063d8be3
S		 533 /*
534 * The hardware is not ready/present, don't
535 * touch anything. Note this can happen early
536 * on if the IRQ is shared.
537 */
538 if (sc->sc_flags & SC_OP_INVALID)
539 return IRQ_NONE;
ff37e337 540
063d8be3
S		 541
542 /* shared irq, not for us */
543
153e080d 544 if (!ath9k_hw_intrpend(ah))
063d8be3 545 return IRQ_NONE;
063d8be3
S		 546
547 /*
548 * Figure out the reason(s) for the interrupt. Note
549 * that the hal returns a pseudo-ISR that may include
550 * bits we haven't explicitly enabled so we mask the
551 * value to insure we only process bits we requested.
552 */
553 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
554 status &= sc->imask; /* discard unasked-for bits */
ff37e337 555
063d8be3
S		 556 /*
557 * If there are no status bits set, then this interrupt was not
558 * for me (should have been caught above).
559 */
153e080d 560 if (!status)
063d8be3 561 return IRQ_NONE;
ff37e337 562
063d8be3
S		 563 /* Cache the status */
564 sc->intrstatus = status;
565
566 if (status & SCHED_INTR)
567 sched = true;
568
569 /*
570 * If a FATAL or RXORN interrupt is received, we have to reset the
571 * chip immediately.
572 */
573 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
574 goto chip_reset;
575
576 if (status & ATH9K_INT_SWBA)
577 tasklet_schedule(&sc->bcon_tasklet);
578
579 if (status & ATH9K_INT_TXURN)
580 ath9k_hw_updatetxtriglevel(ah, true);
581
582 if (status & ATH9K_INT_MIB) {
ff37e337 583 /*
063d8be3
S		 584 * Disable interrupts until we service the MIB
585 * interrupt; otherwise it will continue to
586 * fire.
ff37e337 587 */
063d8be3
S		 588 ath9k_hw_set_interrupts(ah, 0);
589 /*
590 * Let the hal handle the event. We assume
591 * it will clear whatever condition caused
592 * the interrupt.
593 */
594 ath9k_hw_procmibevent(ah, &sc->nodestats);
595 ath9k_hw_set_interrupts(ah, sc->imask);
596 }
ff37e337 597
153e080d
VT		 598 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
599 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 600 /* Clear RxAbort bit so that we can
601 * receive frames */
602 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 603 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 604 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 605 }
063d8be3
S		 606
607chip_reset:
ff37e337 608
817e11de
S		 609 ath_debug_stat_interrupt(sc, status);
610
ff37e337
S		 611 if (sched) {
612 /* turn off every interrupt except SWBA */
17d7904d 613 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 614 tasklet_schedule(&sc->intr_tq);
615 }
616
617 return IRQ_HANDLED;
063d8be3
S		 618
619#undef SCHED_INTR
ff37e337
S		 620}
621
f078f209 622static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 623 struct ieee80211_channel *chan,
094d05dc 624 enum nl80211_channel_type channel_type)
f078f209
LR		 625{
626 u32 chanmode = 0;
f078f209
LR		 627
628 switch (chan->band) {
629 case IEEE80211_BAND_2GHZ:
094d05dc
S		 630 switch(channel_type) {
631 case NL80211_CHAN_NO_HT:
632 case NL80211_CHAN_HT20:
f078f209 633 chanmode = CHANNEL_G_HT20;
094d05dc
S		 634 break;
635 case NL80211_CHAN_HT40PLUS:
f078f209 636 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 637 break;
638 case NL80211_CHAN_HT40MINUS:
f078f209 639 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 640 break;
641 }
f078f209
LR		 642 break;
643 case IEEE80211_BAND_5GHZ:
094d05dc
S		 644 switch(channel_type) {
645 case NL80211_CHAN_NO_HT:
646 case NL80211_CHAN_HT20:
f078f209 647 chanmode = CHANNEL_A_HT20;
094d05dc
S		 648 break;
649 case NL80211_CHAN_HT40PLUS:
f078f209 650 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 651 break;
652 case NL80211_CHAN_HT40MINUS:
f078f209 653 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 654 break;
655 }
f078f209
LR		 656 break;
657 default:
658 break;
659 }
660
661 return chanmode;
662}
663
6ace2891 664static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 665 struct ath9k_keyval *hk, const u8 *addr,
666 bool authenticator)
f078f209 667{
6ace2891
JM		 668 const u8 *key_rxmic;
669 const u8 *key_txmic;
f078f209 670
6ace2891
JM		 671 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
672 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 673
674 if (addr == NULL) {
d216aaa6
JM		 675 /*
676 * Group key installation - only two key cache entries are used
677 * regardless of splitmic capability since group key is only
678 * used either for TX or RX.
679 */
3f53dd64
JM		 680 if (authenticator) {
681 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
682 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
683 } else {
684 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
685 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
686 }
d216aaa6 687 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 688 }
17d7904d 689 if (!sc->splitmic) {
d216aaa6 690 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 691 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
692 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 693 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 694 }
d216aaa6
JM		 695
696 /* Separate key cache entries for TX and RX */
697
698 /* TX key goes at first index, RX key at +32. */
f078f209 699 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 700 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
701 /* TX MIC entry failed. No need to proceed further */
d8baa939 702 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 703 "Setting TX MIC Key Failed\n");
f078f209
LR		 704 return 0;
705 }
706
707 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
708 /* XXX delete tx key on failure? */
d216aaa6 709 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 710}
711
712static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
713{
714 int i;
715
17d7904d
S		 716 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
717 if (test_bit(i, sc->keymap) ||
718 test_bit(i + 64, sc->keymap))
6ace2891 719 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 720 if (sc->splitmic &&
721 (test_bit(i + 32, sc->keymap) ||
722 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 723 continue; /* At least one part of TKIP key allocated */
724
725 /* Found a free slot for a TKIP key */
726 return i;
727 }
728 return -1;
729}
730
731static int ath_reserve_key_cache_slot(struct ath_softc *sc)
732{
733 int i;
734
735 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 736 if (sc->splitmic) {
737 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
738 if (!test_bit(i, sc->keymap) &&
739 (test_bit(i + 32, sc->keymap) ||
740 test_bit(i + 64, sc->keymap) ||
741 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 742 return i;
17d7904d
S		 743 if (!test_bit(i + 32, sc->keymap) &&
744 (test_bit(i, sc->keymap) ||
745 test_bit(i + 64, sc->keymap) ||
746 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 747 return i + 32;
17d7904d
S		 748 if (!test_bit(i + 64, sc->keymap) &&
749 (test_bit(i , sc->keymap) ||
750 test_bit(i + 32, sc->keymap) ||
751 test_bit(i + 64 + 32, sc->keymap)))
ea612132 752 return i + 64;
17d7904d
S		 753 if (!test_bit(i + 64 + 32, sc->keymap) &&
754 (test_bit(i, sc->keymap) ||
755 test_bit(i + 32, sc->keymap) ||
756 test_bit(i + 64, sc->keymap)))
ea612132 757 return i + 64 + 32;
6ace2891
JM		 758 }
759 } else {
17d7904d
S		 760 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
761 if (!test_bit(i, sc->keymap) &&
762 test_bit(i + 64, sc->keymap))
6ace2891 763 return i;
17d7904d
S		 764 if (test_bit(i, sc->keymap) &&
765 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 766 return i + 64;
767 }
768 }
769
770 /* No partially used TKIP slots, pick any available slot */
17d7904d 771 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 772 /* Do not allow slots that could be needed for TKIP group keys
773 * to be used. This limitation could be removed if we know that
774 * TKIP will not be used. */
775 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
776 continue;
17d7904d 777 if (sc->splitmic) {
be2864cf
JM		 778 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
779 continue;
780 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
781 continue;
782 }
783
17d7904d 784 if (!test_bit(i, sc->keymap))
6ace2891
JM		 785 return i; /* Found a free slot for a key */
786 }
787
788 /* No free slot found */
789 return -1;
f078f209
LR		 790}
791
792static int ath_key_config(struct ath_softc *sc,
3f53dd64 793 struct ieee80211_vif *vif,
dc822b5d 794 struct ieee80211_sta *sta,
f078f209
LR		 795 struct ieee80211_key_conf *key)
796{
f078f209
LR		 797 struct ath9k_keyval hk;
798 const u8 *mac = NULL;
799 int ret = 0;
6ace2891 800 int idx;
f078f209
LR		 801
802 memset(&hk, 0, sizeof(hk));
803
804 switch (key->alg) {
805 case ALG_WEP:
806 hk.kv_type = ATH9K_CIPHER_WEP;
807 break;
808 case ALG_TKIP:
809 hk.kv_type = ATH9K_CIPHER_TKIP;
810 break;
811 case ALG_CCMP:
812 hk.kv_type = ATH9K_CIPHER_AES_CCM;
813 break;
814 default:
ca470b29 815 return -EOPNOTSUPP;
f078f209
LR		 816 }
817
6ace2891 818 hk.kv_len = key->keylen;
f078f209
LR		 819 memcpy(hk.kv_val, key->key, key->keylen);
820
6ace2891
JM		 821 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
822 /* For now, use the default keys for broadcast keys. This may
823 * need to change with virtual interfaces. */
824 idx = key->keyidx;
825 } else if (key->keyidx) {
dc822b5d
JB		 826 if (WARN_ON(!sta))
827 return -EOPNOTSUPP;
828 mac = sta->addr;
829
6ace2891
JM		 830 if (vif->type != NL80211_IFTYPE_AP) {
831 /* Only keyidx 0 should be used with unicast key, but
832 * allow this for client mode for now. */
833 idx = key->keyidx;
834 } else
835 return -EIO;
f078f209 836 } else {
dc822b5d
JB		 837 if (WARN_ON(!sta))
838 return -EOPNOTSUPP;
839 mac = sta->addr;
840
6ace2891
JM		 841 if (key->alg == ALG_TKIP)
842 idx = ath_reserve_key_cache_slot_tkip(sc);
843 else
844 idx = ath_reserve_key_cache_slot(sc);
845 if (idx < 0)
ca470b29 846 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 847 }
848
849 if (key->alg == ALG_TKIP)
3f53dd64
JM		 850 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
851 vif->type == NL80211_IFTYPE_AP);
f078f209 852 else
d216aaa6 853 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 854
855 if (!ret)
856 return -EIO;
857
17d7904d 858 set_bit(idx, sc->keymap);
6ace2891 859 if (key->alg == ALG_TKIP) {
17d7904d
S		 860 set_bit(idx + 64, sc->keymap);
861 if (sc->splitmic) {
862 set_bit(idx + 32, sc->keymap);
863 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 864 }
865 }
866
867 return idx;
f078f209
LR		 868}
869
870static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
871{
6ace2891
JM		 872 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
873 if (key->hw_key_idx < IEEE80211_WEP_NKID)
874 return;
875
17d7904d 876 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 877 if (key->alg != ALG_TKIP)
878 return;
f078f209 879
17d7904d
S		 880 clear_bit(key->hw_key_idx + 64, sc->keymap);
881 if (sc->splitmic) {
882 clear_bit(key->hw_key_idx + 32, sc->keymap);
883 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 884 }
f078f209
LR		 885}
886
eb2599ca
S		 887static void setup_ht_cap(struct ath_softc *sc,
888 struct ieee80211_sta_ht_cap *ht_info)
f078f209 889{
60653678
S		 890#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
891#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
140add21 892 u8 tx_streams, rx_streams;
f078f209 893
d9fe60de
JB		 894 ht_info->ht_supported = true;
895 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
896 IEEE80211_HT_CAP_SM_PS |
897 IEEE80211_HT_CAP_SGI_40 |
898 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 899
60653678
S		 900 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
901 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 902
d9fe60de
JB		 903 /* set up supported mcs set */
904 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
140add21
SB		 905 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
906 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
907
908 if (tx_streams != rx_streams) {
909 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
910 tx_streams, rx_streams);
911 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
912 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
913 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
914 }
eb2599ca 915
140add21
SB		 916 ht_info->mcs.rx_mask[0] = 0xff;
917 if (rx_streams >= 2)
eb2599ca 918 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 919
140add21 920 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 921}
922
8feceb67 923static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 924 struct ieee80211_vif *vif,
8feceb67 925 struct ieee80211_bss_conf *bss_conf)
f078f209 926{
f078f209 927
8feceb67 928 if (bss_conf->assoc) {
094d05dc 929 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 930 bss_conf->aid, sc->curbssid);
f078f209 931
8feceb67 932 /* New association, store aid */
2664f201
SB		 933 sc->curaid = bss_conf->aid;
934 ath9k_hw_write_associd(sc);
935
936 /*
937 * Request a re-configuration of Beacon related timers
938 * on the receipt of the first Beacon frame (i.e.,
939 * after time sync with the AP).
940 */
941 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 942
8feceb67 943 /* Configure the beacon */
2c3db3d5 944 ath_beacon_config(sc, vif);
f078f209 945
8feceb67 946 /* Reset rssi stats */
17d7904d
S		 947 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
948 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
949 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
950 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 951
415f738e 952 ath_start_ani(sc);
8feceb67 953 } else {
1ffb0610 954 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 955 sc->curaid = 0;
f38faa31
SB		 956 /* Stop ANI */
957 del_timer_sync(&sc->ani.timer);
f078f209 958 }
8feceb67 959}
f078f209 960
8feceb67
VT		 961/********************************/
962/* LED functions */
963/********************************/
f078f209 964
f2bffa7e
VT		 965static void ath_led_blink_work(struct work_struct *work)
966{
967 struct ath_softc *sc = container_of(work, struct ath_softc,
968 ath_led_blink_work.work);
969
970 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
971 return;
85067c06
VT		 972
973 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
974 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
975 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
976 else
977 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
978 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 979
980 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
981 (sc->sc_flags & SC_OP_LED_ON) ?
982 msecs_to_jiffies(sc->led_off_duration) :
983 msecs_to_jiffies(sc->led_on_duration));
984
85067c06
VT		 985 sc->led_on_duration = sc->led_on_cnt ?
986 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
987 ATH_LED_ON_DURATION_IDLE;
988 sc->led_off_duration = sc->led_off_cnt ?
989 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
990 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 991 sc->led_on_cnt = sc->led_off_cnt = 0;
992 if (sc->sc_flags & SC_OP_LED_ON)
993 sc->sc_flags &= ~SC_OP_LED_ON;
994 else
995 sc->sc_flags |= SC_OP_LED_ON;
996}
997
8feceb67
VT		 998static void ath_led_brightness(struct led_classdev *led_cdev,
999 enum led_brightness brightness)
1000{
1001 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1002 struct ath_softc *sc = led->sc;
f078f209 1003
8feceb67
VT		 1004 switch (brightness) {
1005 case LED_OFF:
1006 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 1007 led->led_type == ATH_LED_RADIO) {
1008 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1009 (led->led_type == ATH_LED_RADIO));
8feceb67 1010 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1011 if (led->led_type == ATH_LED_RADIO)
1012 sc->sc_flags &= ~SC_OP_LED_ON;
1013 } else {
1014 sc->led_off_cnt++;
1015 }
8feceb67
VT		 1016 break;
1017 case LED_FULL:
f2bffa7e 1018 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1019 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1020 queue_delayed_work(sc->hw->workqueue,
1021 &sc->ath_led_blink_work, 0);
1022 } else if (led->led_type == ATH_LED_RADIO) {
1023 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1024 sc->sc_flags |= SC_OP_LED_ON;
1025 } else {
1026 sc->led_on_cnt++;
1027 }
8feceb67
VT		 1028 break;
1029 default:
1030 break;
f078f209 1031 }
8feceb67 1032}
f078f209 1033
8feceb67
VT		 1034static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1035 char *trigger)
1036{
1037 int ret;
f078f209 1038
8feceb67
VT		 1039 led->sc = sc;
1040 led->led_cdev.name = led->name;
1041 led->led_cdev.default_trigger = trigger;
1042 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1043
8feceb67
VT		 1044 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1045 if (ret)
1046 DPRINTF(sc, ATH_DBG_FATAL,
1047 "Failed to register led:%s", led->name);
1048 else
1049 led->registered = 1;
1050 return ret;
1051}
f078f209 1052
8feceb67
VT		 1053static void ath_unregister_led(struct ath_led *led)
1054{
1055 if (led->registered) {
1056 led_classdev_unregister(&led->led_cdev);
1057 led->registered = 0;
f078f209 1058 }
f078f209
LR		 1059}
1060
8feceb67 1061static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1062{
f2bffa7e 1063 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1064 ath_unregister_led(&sc->assoc_led);
1065 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1066 ath_unregister_led(&sc->tx_led);
1067 ath_unregister_led(&sc->rx_led);
1068 ath_unregister_led(&sc->radio_led);
1069 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1070}
f078f209 1071
8feceb67
VT		 1072static void ath_init_leds(struct ath_softc *sc)
1073{
1074 char *trigger;
1075 int ret;
f078f209 1076
8feceb67
VT		 1077 /* Configure gpio 1 for output */
1078 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1079 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1080 /* LED off, active low */
1081 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1082
f2bffa7e
VT		 1083 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1084
8feceb67
VT		 1085 trigger = ieee80211_get_radio_led_name(sc->hw);
1086 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1087 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1088 ret = ath_register_led(sc, &sc->radio_led, trigger);
1089 sc->radio_led.led_type = ATH_LED_RADIO;
1090 if (ret)
1091 goto fail;
7dcfdcd9 1092
8feceb67
VT		 1093 trigger = ieee80211_get_assoc_led_name(sc->hw);
1094 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1095 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1096 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1097 sc->assoc_led.led_type = ATH_LED_ASSOC;
1098 if (ret)
1099 goto fail;
f078f209 1100
8feceb67
VT		 1101 trigger = ieee80211_get_tx_led_name(sc->hw);
1102 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1103 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1104 ret = ath_register_led(sc, &sc->tx_led, trigger);
1105 sc->tx_led.led_type = ATH_LED_TX;
1106 if (ret)
1107 goto fail;
f078f209 1108
8feceb67
VT		 1109 trigger = ieee80211_get_rx_led_name(sc->hw);
1110 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1111 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1112 ret = ath_register_led(sc, &sc->rx_led, trigger);
1113 sc->rx_led.led_type = ATH_LED_RX;
1114 if (ret)
1115 goto fail;
f078f209 1116
8feceb67
VT		 1117 return;
1118
1119fail:
1120 ath_deinit_leds(sc);
f078f209
LR		 1121}
1122
7ec3e514 1123void ath_radio_enable(struct ath_softc *sc)
500c064d 1124{
cbe61d8a 1125 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1126 struct ieee80211_channel *channel = sc->hw->conf.channel;
1127 int r;
500c064d 1128
3cbb5dd7 1129 ath9k_ps_wakeup(sc);
d2f5b3a6 1130 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1131
159cd468
VT		 1132 if (!ah->curchan)
1133 ah->curchan = ath_get_curchannel(sc, sc->hw);
1134
d2f5b3a6 1135 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1136 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1137 if (r) {
500c064d 1138 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1139 "Unable to reset channel %u (%uMhz) ",
6b45784f 1140 "reset status %d\n",
ae8d2858 1141 channel->center_freq, r);
500c064d
VT		 1142 }
1143 spin_unlock_bh(&sc->sc_resetlock);
1144
1145 ath_update_txpow(sc);
1146 if (ath_startrecv(sc) != 0) {
1147 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1148 "Unable to restart recv logic\n");
500c064d
VT		 1149 return;
1150 }
1151
1152 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1153 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1154
1155 /* Re-Enable interrupts */
17d7904d 1156 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1157
1158 /* Enable LED */
1159 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1160 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1161 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1162
1163 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1164 ath9k_ps_restore(sc);
500c064d
VT		 1165}
1166
7ec3e514 1167void ath_radio_disable(struct ath_softc *sc)
500c064d 1168{
cbe61d8a 1169 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1170 struct ieee80211_channel *channel = sc->hw->conf.channel;
1171 int r;
500c064d 1172
3cbb5dd7 1173 ath9k_ps_wakeup(sc);
500c064d
VT		 1174 ieee80211_stop_queues(sc->hw);
1175
1176 /* Disable LED */
1177 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1178 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1179
1180 /* Disable interrupts */
1181 ath9k_hw_set_interrupts(ah, 0);
1182
043a0405 1183 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1184 ath_stoprecv(sc); /* turn off frame recv */
1185 ath_flushrecv(sc); /* flush recv queue */
1186
159cd468
VT		 1187 if (!ah->curchan)
1188 ah->curchan = ath_get_curchannel(sc, sc->hw);
1189
500c064d 1190 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1191 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1192 if (r) {
500c064d 1193 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1194 "Unable to reset channel %u (%uMhz) "
6b45784f 1195 "reset status %d\n",
ae8d2858 1196 channel->center_freq, r);
500c064d
VT		 1197 }
1198 spin_unlock_bh(&sc->sc_resetlock);
1199
1200 ath9k_hw_phy_disable(ah);
d2f5b3a6 1201 ath9k_hw_configpcipowersave(ah, 1);
3cbb5dd7 1202 ath9k_ps_restore(sc);
38ab422e 1203 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1204}
1205
5077fd35
GJ		 1206/*******************/
1207/* Rfkill */
1208/*******************/
1209
500c064d
VT		 1210static bool ath_is_rfkill_set(struct ath_softc *sc)
1211{
cbe61d8a 1212 struct ath_hw *ah = sc->sc_ah;
500c064d 1213
2660b81a
S		 1214 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1215 ah->rfkill_polarity;
500c064d
VT		 1216}
1217
3b319aae 1218static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1219{
3b319aae
JB		 1220 struct ath_wiphy *aphy = hw->priv;
1221 struct ath_softc *sc = aphy->sc;
19d337df 1222 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1223
3b319aae
JB		 1224 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1225
1226 if (blocked)
19d337df
JB		 1227 ath_radio_disable(sc);
1228 else
1229 ath_radio_enable(sc);
500c064d
VT		 1230}
1231
3b319aae 1232static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1233{
3b319aae 1234 struct ath_hw *ah = sc->sc_ah;
9c84b797 1235
3b319aae
JB		 1236 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1237 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1238}
500c064d 1239
6baff7f9 1240void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1241{
1242 ath_detach(sc);
1243 free_irq(sc->irq, sc);
1244 ath_bus_cleanup(sc);
c52f33d0 1245 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1246 ieee80211_free_hw(sc->hw);
1247}
1248
6baff7f9 1249void ath_detach(struct ath_softc *sc)
f078f209 1250{
8feceb67 1251 struct ieee80211_hw *hw = sc->hw;
9c84b797 1252 int i = 0;
f078f209 1253
3cbb5dd7
VN		 1254 ath9k_ps_wakeup(sc);
1255
04bd4638 1256 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1257
3fcdfb4b 1258 ath_deinit_leds(sc);
0e2dedf9 1259 cancel_work_sync(&sc->chan_work);
f98c3bd2 1260 cancel_delayed_work_sync(&sc->wiphy_work);
3fcdfb4b 1261
c52f33d0
JM		 1262 for (i = 0; i < sc->num_sec_wiphy; i++) {
1263 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1264 if (aphy == NULL)
1265 continue;
1266 sc->sec_wiphy[i] = NULL;
1267 ieee80211_unregister_hw(aphy->hw);
1268 ieee80211_free_hw(aphy->hw);
1269 }
3fcdfb4b 1270 ieee80211_unregister_hw(hw);
8feceb67
VT		 1271 ath_rx_cleanup(sc);
1272 ath_tx_cleanup(sc);
f078f209 1273
9c84b797
S		 1274 tasklet_kill(&sc->intr_tq);
1275 tasklet_kill(&sc->bcon_tasklet);
f078f209 1276
9c84b797
S		 1277 if (!(sc->sc_flags & SC_OP_INVALID))
1278 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1279
9c84b797
S		 1280 /* cleanup tx queues */
1281 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1282 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1283 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1284
1285 ath9k_hw_detach(sc->sc_ah);
826d2680 1286 ath9k_exit_debug(sc);
3cbb5dd7 1287 ath9k_ps_restore(sc);
f078f209
LR		 1288}
1289
e3bb249b
BC		 1290static int ath9k_reg_notifier(struct wiphy *wiphy,
1291 struct regulatory_request *request)
1292{
1293 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1294 struct ath_wiphy *aphy = hw->priv;
1295 struct ath_softc *sc = aphy->sc;
1296 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1297
1298 return ath_reg_notifier_apply(wiphy, request, reg);
1299}
1300
ff37e337
S		 1301static int ath_init(u16 devid, struct ath_softc *sc)
1302{
cbe61d8a 1303 struct ath_hw *ah = NULL;
ff37e337
S		 1304 int status;
1305 int error = 0, i;
1306 int csz = 0;
1307
1308 /* XXX: hardware will not be ready until ath_open() being called */
1309 sc->sc_flags |= SC_OP_INVALID;
88b126af 1310
826d2680
S		 1311 if (ath9k_init_debug(sc) < 0)
1312 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1313
c52f33d0 1314 spin_lock_init(&sc->wiphy_lock);
ff37e337 1315 spin_lock_init(&sc->sc_resetlock);
6158425b 1316 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1317 spin_lock_init(&sc->ani_lock);
aa33de09 1318 mutex_init(&sc->mutex);
ff37e337 1319 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1320 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1321 (unsigned long)sc);
1322
1323 /*
1324 * Cache line size is used to size and align various
1325 * structures used to communicate with the hardware.
1326 */
88d15707 1327 ath_read_cachesize(sc, &csz);
ff37e337 1328 /* XXX assert csz is non-zero */
17d7904d 1329 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1330
cbe61d8a 1331 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1332 if (ah == NULL) {
1333 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1334 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1335 error = -ENXIO;
1336 goto bad;
1337 }
1338 sc->sc_ah = ah;
1339
1340 /* Get the hardware key cache size. */
2660b81a 1341 sc->keymax = ah->caps.keycache_size;
17d7904d 1342 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1343 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1344 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1345 ATH_KEYMAX, sc->keymax);
1346 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1347 }
1348
1349 /*
1350 * Reset the key cache since some parts do not
1351 * reset the contents on initial power up.
1352 */
17d7904d 1353 for (i = 0; i < sc->keymax; i++)
ff37e337 1354 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1355
85efc86e 1356 if (error)
ff37e337
S		 1357 goto bad;
1358
1359 /* default to MONITOR mode */
2660b81a 1360 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1361
ff37e337
S		 1362 /* Setup rate tables */
1363
1364 ath_rate_attach(sc);
1365 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1366 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1367
1368 /*
1369 * Allocate hardware transmit queues: one queue for
1370 * beacon frames and one data queue for each QoS
1371 * priority. Note that the hal handles reseting
1372 * these queues at the needed time.
1373 */
b77f483f
S		 1374 sc->beacon.beaconq = ath_beaconq_setup(ah);
1375 if (sc->beacon.beaconq == -1) {
ff37e337 1376 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1377 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1378 error = -EIO;
1379 goto bad2;
1380 }
b77f483f
S		 1381 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1382 if (sc->beacon.cabq == NULL) {
ff37e337 1383 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1384 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1385 error = -EIO;
1386 goto bad2;
1387 }
1388
17d7904d 1389 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1390 ath_cabq_update(sc);
1391
b77f483f
S		 1392 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1393 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1394
1395 /* Setup data queues */
1396 /* NB: ensure BK queue is the lowest priority h/w queue */
1397 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1398 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1399 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1400 error = -EIO;
1401 goto bad2;
1402 }
1403
1404 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1405 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1406 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1407 error = -EIO;
1408 goto bad2;
1409 }
1410 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1411 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1412 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1413 error = -EIO;
1414 goto bad2;
1415 }
1416 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1417 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1418 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1419 error = -EIO;
1420 goto bad2;
1421 }
1422
1423 /* Initializes the noise floor to a reasonable default value.
1424 * Later on this will be updated during ANI processing. */
1425
17d7904d
S		 1426 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1427 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1428
1429 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1430 ATH9K_CIPHER_TKIP, NULL)) {
1431 /*
1432 * Whether we should enable h/w TKIP MIC.
1433 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1434 * report WMM capable, so it's always safe to turn on
1435 * TKIP MIC in this case.
1436 */
1437 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1438 0, 1, NULL);
1439 }
1440
1441 /*
1442 * Check whether the separate key cache entries
1443 * are required to handle both tx+rx MIC keys.
1444 * With split mic keys the number of stations is limited
1445 * to 27 otherwise 59.
1446 */
1447 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1448 ATH9K_CIPHER_TKIP, NULL)
1449 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1450 ATH9K_CIPHER_MIC, NULL)
1451 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1452 0, NULL))
17d7904d 1453 sc->splitmic = 1;
ff37e337
S		 1454
1455 /* turn on mcast key search if possible */
1456 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1457 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1458 1, NULL);
1459
17d7904d 1460 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1461
1462 /* 11n Capabilities */
2660b81a 1463 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1464 sc->sc_flags |= SC_OP_TXAGGR;
1465 sc->sc_flags |= SC_OP_RXAGGR;
1466 }
1467
2660b81a
S		 1468 sc->tx_chainmask = ah->caps.tx_chainmask;
1469 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1470
1471 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1472 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1473
8ca21f01 1474 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1475 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1476
b77f483f 1477 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1478
1479 /* initialize beacon slots */
c52f33d0 1480 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1481 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1482 sc->beacon.bslot_aphy[i] = NULL;
1483 }
ff37e337 1484
ff37e337
S		 1485 /* setup channels and rates */
1486
5f8e077c 1487 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1488 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1489 sc->rates[IEEE80211_BAND_2GHZ];
1490 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1491 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1492 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1493
2660b81a 1494 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1495 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1496 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1497 sc->rates[IEEE80211_BAND_5GHZ];
1498 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1499 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1500 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1501 }
1502
2660b81a 1503 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1504 ath9k_hw_btcoex_enable(sc->sc_ah);
1505
ff37e337
S		 1506 return 0;
1507bad2:
1508 /* cleanup tx queues */
1509 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1510 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1511 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1512bad:
1513 if (ah)
1514 ath9k_hw_detach(ah);
40b130a9 1515 ath9k_exit_debug(sc);
ff37e337
S		 1516
1517 return error;
1518}
1519
c52f33d0 1520void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1521{
9c84b797
S		 1522 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1523 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1524 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1525 IEEE80211_HW_AMPDU_AGGREGATION |
1526 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1527 IEEE80211_HW_PS_NULLFUNC_STACK |
1528 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1529
b3bd89ce 1530 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1531 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1532
9c84b797
S		 1533 hw->wiphy->interface_modes =
1534 BIT(NL80211_IFTYPE_AP) |
1535 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1536 BIT(NL80211_IFTYPE_ADHOC) |
1537 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1538
8feceb67 1539 hw->queues = 4;
e63835b0 1540 hw->max_rates = 4;
171387ef 1541 hw->channel_change_time = 5000;
465ca84d 1542 hw->max_listen_interval = 10;
e63835b0 1543 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1544 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1545 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1546
8feceb67 1547 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1548
c52f33d0
JM		 1549 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1550 &sc->sbands[IEEE80211_BAND_2GHZ];
1551 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1552 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1553 &sc->sbands[IEEE80211_BAND_5GHZ];
1554}
1555
1556int ath_attach(u16 devid, struct ath_softc *sc)
1557{
1558 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1559 int error = 0, i;
3a702e49 1560 struct ath_regulatory *reg;
c52f33d0
JM		 1561
1562 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1563
1564 error = ath_init(devid, sc);
1565 if (error != 0)
1566 return error;
1567
1568 /* get mac address from hardware and set in mac80211 */
1569
1570 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1571
1572 ath_set_hw_capab(sc, hw);
1573
c26c2e57
LR		 1574 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1575 ath9k_reg_notifier);
1576 if (error)
1577 return error;
1578
1579 reg = &sc->sc_ah->regulatory;
1580
2660b81a 1581 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1582 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1583 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1584 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1585 }
1586
db93e7b5
SB		 1587 /* initialize tx/rx engine */
1588 error = ath_tx_init(sc, ATH_TXBUF);
1589 if (error != 0)
40b130a9 1590 goto error_attach;
8feceb67 1591
db93e7b5
SB		 1592 error = ath_rx_init(sc, ATH_RXBUF);
1593 if (error != 0)
40b130a9 1594 goto error_attach;
8feceb67 1595
0e2dedf9 1596 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1597 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1598 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1599
db93e7b5 1600 error = ieee80211_register_hw(hw);
8feceb67 1601
3a702e49 1602 if (!ath_is_world_regd(reg)) {
c02cf373 1603 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1604 if (error)
1605 goto error_attach;
1606 }
5f8e077c 1607
db93e7b5
SB		 1608 /* Initialize LED control */
1609 ath_init_leds(sc);
8feceb67 1610
3b319aae 1611 ath_start_rfkill_poll(sc);
5f8e077c 1612
8feceb67 1613 return 0;
40b130a9
VT		 1614
1615error_attach:
1616 /* cleanup tx queues */
1617 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1618 if (ATH_TXQ_SETUP(sc, i))
1619 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1620
1621 ath9k_hw_detach(sc->sc_ah);
1622 ath9k_exit_debug(sc);
1623
8feceb67 1624 return error;
f078f209
LR		 1625}
1626
ff37e337
S		 1627int ath_reset(struct ath_softc *sc, bool retry_tx)
1628{
cbe61d8a 1629 struct ath_hw *ah = sc->sc_ah;
030bb495 1630 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1631 int r;
ff37e337
S		 1632
1633 ath9k_hw_set_interrupts(ah, 0);
043a0405 1634 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1635 ath_stoprecv(sc);
1636 ath_flushrecv(sc);
1637
1638 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1639 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1640 if (r)
ff37e337 1641 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1642 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1643 spin_unlock_bh(&sc->sc_resetlock);
1644
1645 if (ath_startrecv(sc) != 0)
04bd4638 1646 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1647
1648 /*
1649 * We may be doing a reset in response to a request
1650 * that changes the channel so update any state that
1651 * might change as a result.
1652 */
ce111bad 1653 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1654
1655 ath_update_txpow(sc);
1656
1657 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1658 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1659
17d7904d 1660 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1661
1662 if (retry_tx) {
1663 int i;
1664 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1665 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1666 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1667 ath_txq_schedule(sc, &sc->tx.txq[i]);
1668 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1669 }
1670 }
1671 }
1672
ae8d2858 1673 return r;
ff37e337
S		 1674}
1675
1676/*
1677 * This function will allocate both the DMA descriptor structure, and the
1678 * buffers it contains. These are used to contain the descriptors used
1679 * by the system.
1680*/
1681int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1682 struct list_head *head, const char *name,
1683 int nbuf, int ndesc)
1684{
1685#define DS2PHYS(_dd, _ds) \
1686 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1687#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1688#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1689
1690 struct ath_desc *ds;
1691 struct ath_buf *bf;
1692 int i, bsize, error;
1693
04bd4638
S		 1694 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1695 name, nbuf, ndesc);
ff37e337 1696
b03a9db9 1697 INIT_LIST_HEAD(head);
ff37e337
S		 1698 /* ath_desc must be a multiple of DWORDs */
1699 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1700 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1701 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1702 error = -ENOMEM;
1703 goto fail;
1704 }
1705
ff37e337
S		 1706 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1707
1708 /*
1709 * Need additional DMA memory because we can't use
1710 * descriptors that cross the 4K page boundary. Assume
1711 * one skipped descriptor per 4K page.
1712 */
2660b81a 1713 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1714 u32 ndesc_skipped =
1715 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1716 u32 dma_len;
1717
1718 while (ndesc_skipped) {
1719 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1720 dd->dd_desc_len += dma_len;
1721
1722 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1723 };
1724 }
1725
1726 /* allocate descriptors */
7da3c55c 1727 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1728 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1729 if (dd->dd_desc == NULL) {
1730 error = -ENOMEM;
1731 goto fail;
1732 }
1733 ds = dd->dd_desc;
04bd4638 1734 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1735 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1736 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1737
1738 /* allocate buffers */
1739 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1740 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1741 if (bf == NULL) {
1742 error = -ENOMEM;
1743 goto fail2;
1744 }
ff37e337
S		 1745 dd->dd_bufptr = bf;
1746
ff37e337
S		 1747 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1748 bf->bf_desc = ds;
1749 bf->bf_daddr = DS2PHYS(dd, ds);
1750
2660b81a 1751 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1752 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1753 /*
1754 * Skip descriptor addresses which can cause 4KB
1755 * boundary crossing (addr + length) with a 32 dword
1756 * descriptor fetch.
1757 */
1758 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1759 ASSERT((caddr_t) bf->bf_desc <
1760 ((caddr_t) dd->dd_desc +
1761 dd->dd_desc_len));
1762
1763 ds += ndesc;
1764 bf->bf_desc = ds;
1765 bf->bf_daddr = DS2PHYS(dd, ds);
1766 }
1767 }
1768 list_add_tail(&bf->list, head);
1769 }
1770 return 0;
1771fail2:
7da3c55c
GJ		 1772 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1773 dd->dd_desc_paddr);
ff37e337
S		 1774fail:
1775 memset(dd, 0, sizeof(*dd));
1776 return error;
1777#undef ATH_DESC_4KB_BOUND_CHECK
1778#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1779#undef DS2PHYS
1780}
1781
1782void ath_descdma_cleanup(struct ath_softc *sc,
1783 struct ath_descdma *dd,
1784 struct list_head *head)
1785{
7da3c55c
GJ		 1786 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1787 dd->dd_desc_paddr);
ff37e337
S		 1788
1789 INIT_LIST_HEAD(head);
1790 kfree(dd->dd_bufptr);
1791 memset(dd, 0, sizeof(*dd));
1792}
1793
1794int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1795{
1796 int qnum;
1797
1798 switch (queue) {
1799 case 0:
b77f483f 1800 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1801 break;
1802 case 1:
b77f483f 1803 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1804 break;
1805 case 2:
b77f483f 1806 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1807 break;
1808 case 3:
b77f483f 1809 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1810 break;
1811 default:
b77f483f 1812 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1813 break;
1814 }
1815
1816 return qnum;
1817}
1818
1819int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1820{
1821 int qnum;
1822
1823 switch (queue) {
1824 case ATH9K_WME_AC_VO:
1825 qnum = 0;
1826 break;
1827 case ATH9K_WME_AC_VI:
1828 qnum = 1;
1829 break;
1830 case ATH9K_WME_AC_BE:
1831 qnum = 2;
1832 break;
1833 case ATH9K_WME_AC_BK:
1834 qnum = 3;
1835 break;
1836 default:
1837 qnum = -1;
1838 break;
1839 }
1840
1841 return qnum;
1842}
1843
5f8e077c
LR		 1844/* XXX: Remove me once we don't depend on ath9k_channel for all
1845 * this redundant data */
0e2dedf9
JM		 1846void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1847 struct ath9k_channel *ichan)
5f8e077c 1848{
5f8e077c
LR		 1849 struct ieee80211_channel *chan = hw->conf.channel;
1850 struct ieee80211_conf *conf = &hw->conf;
1851
1852 ichan->channel = chan->center_freq;
1853 ichan->chan = chan;
1854
1855 if (chan->band == IEEE80211_BAND_2GHZ) {
1856 ichan->chanmode = CHANNEL_G;
1857 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1858 } else {
1859 ichan->chanmode = CHANNEL_A;
1860 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1861 }
1862
1863 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1864
1865 if (conf_is_ht(conf)) {
1866 if (conf_is_ht40(conf))
1867 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1868
1869 ichan->chanmode = ath_get_extchanmode(sc, chan,
1870 conf->channel_type);
1871 }
1872}
1873
ff37e337
S		 1874/**********************/
1875/* mac80211 callbacks */
1876/**********************/
1877
8feceb67 1878static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1879{
bce048d7
JM		 1880 struct ath_wiphy *aphy = hw->priv;
1881 struct ath_softc *sc = aphy->sc;
8feceb67 1882 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1883 struct ath9k_channel *init_channel;
82880a7c 1884 int r;
f078f209 1885
04bd4638
S		 1886 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1887 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1888
141b38b6
S		 1889 mutex_lock(&sc->mutex);
1890
9580a222
JM		 1891 if (ath9k_wiphy_started(sc)) {
1892 if (sc->chan_idx == curchan->hw_value) {
1893 /*
1894 * Already on the operational channel, the new wiphy
1895 * can be marked active.
1896 */
1897 aphy->state = ATH_WIPHY_ACTIVE;
1898 ieee80211_wake_queues(hw);
1899 } else {
1900 /*
1901 * Another wiphy is on another channel, start the new
1902 * wiphy in paused state.
1903 */
1904 aphy->state = ATH_WIPHY_PAUSED;
1905 ieee80211_stop_queues(hw);
1906 }
1907 mutex_unlock(&sc->mutex);
1908 return 0;
1909 }
1910 aphy->state = ATH_WIPHY_ACTIVE;
1911
8feceb67 1912 /* setup initial channel */
f078f209 1913
82880a7c 1914 sc->chan_idx = curchan->hw_value;
f078f209 1915
82880a7c 1916 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 1917
1918 /* Reset SERDES registers */
1919 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1920
1921 /*
1922 * The basic interface to setting the hardware in a good
1923 * state is ``reset''. On return the hardware is known to
1924 * be powered up and with interrupts disabled. This must
1925 * be followed by initialization of the appropriate bits
1926 * and then setup of the interrupt mask.
1927 */
1928 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1929 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1930 if (r) {
ff37e337 1931 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1932 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 1933 "(freq %u MHz)\n", r,
1934 curchan->center_freq);
ff37e337 1935 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1936 goto mutex_unlock;
ff37e337
S		 1937 }
1938 spin_unlock_bh(&sc->sc_resetlock);
1939
1940 /*
1941 * This is needed only to setup initial state
1942 * but it's best done after a reset.
1943 */
1944 ath_update_txpow(sc);
8feceb67 1945
ff37e337
S		 1946 /*
1947 * Setup the hardware after reset:
1948 * The receive engine is set going.
1949 * Frame transmit is handled entirely
1950 * in the frame output path; there's nothing to do
1951 * here except setup the interrupt mask.
1952 */
1953 if (ath_startrecv(sc) != 0) {
1ffb0610 1954 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 1955 r = -EIO;
1956 goto mutex_unlock;
f078f209 1957 }
8feceb67 1958
ff37e337 1959 /* Setup our intr mask. */
17d7904d 1960 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 1961 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1962 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1963
2660b81a 1964 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 1965 sc->imask |= ATH9K_INT_GTT;
ff37e337 1966
2660b81a 1967 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 1968 sc->imask |= ATH9K_INT_CST;
ff37e337 1969
ce111bad 1970 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1971
1972 sc->sc_flags &= ~SC_OP_INVALID;
1973
1974 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 1975 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1976 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 1977
bce048d7 1978 ieee80211_wake_queues(hw);
ff37e337 1979
141b38b6
S		 1980mutex_unlock:
1981 mutex_unlock(&sc->mutex);
1982
ae8d2858 1983 return r;
f078f209
LR		 1984}
1985
8feceb67
VT		 1986static int ath9k_tx(struct ieee80211_hw *hw,
1987 struct sk_buff *skb)
f078f209 1988{
528f0c6b 1989 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 1990 struct ath_wiphy *aphy = hw->priv;
1991 struct ath_softc *sc = aphy->sc;
528f0c6b 1992 struct ath_tx_control txctl;
8feceb67 1993 int hdrlen, padsize;
528f0c6b 1994
8089cc47 1995 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 1996 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
1997 "%d\n", wiphy_name(hw->wiphy), aphy->state);
1998 goto exit;
1999 }
2000
dc8c4585
JM		 2001 if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
2002 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2003 /*
2004 * mac80211 does not set PM field for normal data frames, so we
2005 * need to update that based on the current PS mode.
2006 */
2007 if (ieee80211_is_data(hdr->frame_control) &&
2008 !ieee80211_is_nullfunc(hdr->frame_control) &&
2009 !ieee80211_has_pm(hdr->frame_control)) {
2010 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2011 "while in PS mode\n");
2012 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2013 }
2014 }
2015
9a23f9ca
JM		 2016 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2017 /*
2018 * We are using PS-Poll and mac80211 can request TX while in
2019 * power save mode. Need to wake up hardware for the TX to be
2020 * completed and if needed, also for RX of buffered frames.
2021 */
2022 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2023 ath9k_ps_wakeup(sc);
2024 ath9k_hw_setrxabort(sc->sc_ah, 0);
2025 if (ieee80211_is_pspoll(hdr->frame_control)) {
2026 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2027 "buffered frame\n");
2028 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2029 } else {
2030 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2031 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2032 }
2033 /*
2034 * The actual restore operation will happen only after
2035 * the sc_flags bit is cleared. We are just dropping
2036 * the ps_usecount here.
2037 */
2038 ath9k_ps_restore(sc);
2039 }
2040
528f0c6b 2041 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2042
8feceb67
VT		 2043 /*
2044 * As a temporary workaround, assign seq# here; this will likely need
2045 * to be cleaned up to work better with Beacon transmission and virtual
2046 * BSSes.
2047 */
2048 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2049 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2050 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2051 sc->tx.seq_no += 0x10;
8feceb67 2052 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2053 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2054 }
f078f209 2055
8feceb67
VT		 2056 /* Add the padding after the header if this is not already done */
2057 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2058 if (hdrlen & 3) {
2059 padsize = hdrlen % 4;
2060 if (skb_headroom(skb) < padsize)
2061 return -1;
2062 skb_push(skb, padsize);
2063 memmove(skb->data, skb->data + padsize, hdrlen);
2064 }
2065
528f0c6b
S		 2066 /* Check if a tx queue is available */
2067
2068 txctl.txq = ath_test_get_txq(sc, skb);
2069 if (!txctl.txq)
2070 goto exit;
2071
04bd4638 2072 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2073
c52f33d0 2074 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2075 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2076 goto exit;
8feceb67
VT		 2077 }
2078
528f0c6b
S		 2079 return 0;
2080exit:
2081 dev_kfree_skb_any(skb);
8feceb67 2082 return 0;
f078f209
LR		 2083}
2084
8feceb67 2085static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2086{
bce048d7
JM		 2087 struct ath_wiphy *aphy = hw->priv;
2088 struct ath_softc *sc = aphy->sc;
f078f209 2089
9580a222
JM		 2090 aphy->state = ATH_WIPHY_INACTIVE;
2091
9c84b797 2092 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2093 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2094 return;
2095 }
8feceb67 2096
141b38b6 2097 mutex_lock(&sc->mutex);
ff37e337 2098
bce048d7 2099 ieee80211_stop_queues(hw);
ff37e337 2100
9580a222
JM		 2101 if (ath9k_wiphy_started(sc)) {
2102 mutex_unlock(&sc->mutex);
2103 return; /* another wiphy still in use */
2104 }
2105
ff37e337
S		 2106 /* make sure h/w will not generate any interrupt
2107 * before setting the invalid flag. */
2108 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2109
2110 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2111 ath_drain_all_txq(sc, false);
ff37e337
S		 2112 ath_stoprecv(sc);
2113 ath9k_hw_phy_disable(sc->sc_ah);
2114 } else
b77f483f 2115 sc->rx.rxlink = NULL;
ff37e337 2116
3b319aae 2117 wiphy_rfkill_stop_polling(sc->hw->wiphy);
19d337df 2118
ff37e337
S		 2119 /* disable HAL and put h/w to sleep */
2120 ath9k_hw_disable(sc->sc_ah);
2121 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2122
2123 sc->sc_flags |= SC_OP_INVALID;
500c064d 2124
141b38b6
S		 2125 mutex_unlock(&sc->mutex);
2126
04bd4638 2127 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2128}
2129
8feceb67
VT		 2130static int ath9k_add_interface(struct ieee80211_hw *hw,
2131 struct ieee80211_if_init_conf *conf)
f078f209 2132{
bce048d7
JM		 2133 struct ath_wiphy *aphy = hw->priv;
2134 struct ath_softc *sc = aphy->sc;
17d7904d 2135 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2136 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2137 int ret = 0;
8feceb67 2138
141b38b6
S		 2139 mutex_lock(&sc->mutex);
2140
8ca21f01
JM		 2141 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2142 sc->nvifs > 0) {
2143 ret = -ENOBUFS;
2144 goto out;
2145 }
2146
8feceb67 2147 switch (conf->type) {
05c914fe 2148 case NL80211_IFTYPE_STATION:
d97809db 2149 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2150 break;
05c914fe 2151 case NL80211_IFTYPE_ADHOC:
05c914fe 2152 case NL80211_IFTYPE_AP:
9cb5412b 2153 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2154 if (sc->nbcnvifs >= ATH_BCBUF) {
2155 ret = -ENOBUFS;
2156 goto out;
2157 }
9cb5412b 2158 ic_opmode = conf->type;
f078f209
LR		 2159 break;
2160 default:
2161 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2162 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2163 ret = -EOPNOTSUPP;
2164 goto out;
f078f209
LR		 2165 }
2166
17d7904d 2167 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2168
17d7904d 2169 /* Set the VIF opmode */
5640b08e
S		 2170 avp->av_opmode = ic_opmode;
2171 avp->av_bslot = -1;
2172
2c3db3d5 2173 sc->nvifs++;
8ca21f01
JM		 2174
2175 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2176 ath9k_set_bssid_mask(hw);
2177
2c3db3d5
JM		 2178 if (sc->nvifs > 1)
2179 goto out; /* skip global settings for secondary vif */
2180
b238e90e 2181 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2182 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2183 sc->sc_flags |= SC_OP_TSF_RESET;
2184 }
5640b08e 2185
5640b08e 2186 /* Set the device opmode */
2660b81a 2187 sc->sc_ah->opmode = ic_opmode;
5640b08e 2188
4e30ffa2
VN		 2189 /*
2190 * Enable MIB interrupts when there are hardware phy counters.
2191 * Note we only do this (at the moment) for station mode.
2192 */
4af9cf4f 2193 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2194 (conf->type == NL80211_IFTYPE_ADHOC) ||
2195 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2196 if (ath9k_hw_phycounters(sc->sc_ah))
2197 sc->imask |= ATH9K_INT_MIB;
2198 sc->imask |= ATH9K_INT_TSFOOR;
2199 }
2200
17d7904d 2201 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2202
f38faa31
SB		 2203 if (conf->type == NL80211_IFTYPE_AP ||
2204 conf->type == NL80211_IFTYPE_ADHOC ||
2205 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2206 ath_start_ani(sc);
6f255425 2207
2c3db3d5 2208out:
141b38b6 2209 mutex_unlock(&sc->mutex);
2c3db3d5 2210 return ret;
f078f209
LR		 2211}
2212
8feceb67
VT		 2213static void ath9k_remove_interface(struct ieee80211_hw *hw,
2214 struct ieee80211_if_init_conf *conf)
f078f209 2215{
bce048d7
JM		 2216 struct ath_wiphy *aphy = hw->priv;
2217 struct ath_softc *sc = aphy->sc;
17d7904d 2218 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2219 int i;
f078f209 2220
04bd4638 2221 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2222
141b38b6
S		 2223 mutex_lock(&sc->mutex);
2224
6f255425 2225 /* Stop ANI */
17d7904d 2226 del_timer_sync(&sc->ani.timer);
580f0b8a 2227
8feceb67 2228 /* Reclaim beacon resources */
9cb5412b
PE		 2229 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2230 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2231 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2232 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2233 ath_beacon_return(sc, avp);
580f0b8a 2234 }
f078f209 2235
8feceb67 2236 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2237
2c3db3d5
JM		 2238 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2239 if (sc->beacon.bslot[i] == conf->vif) {
2240 printk(KERN_DEBUG "%s: vif had allocated beacon "
2241 "slot\n", __func__);
2242 sc->beacon.bslot[i] = NULL;
c52f33d0 2243 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2244 }
2245 }
2246
17d7904d 2247 sc->nvifs--;
141b38b6
S		 2248
2249 mutex_unlock(&sc->mutex);
f078f209
LR		 2250}
2251
e8975581 2252static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2253{
bce048d7
JM		 2254 struct ath_wiphy *aphy = hw->priv;
2255 struct ath_softc *sc = aphy->sc;
e8975581 2256 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2257 struct ath_hw *ah = sc->sc_ah;
f078f209 2258
aa33de09 2259 mutex_lock(&sc->mutex);
141b38b6 2260
3cbb5dd7
VN		 2261 if (changed & IEEE80211_CONF_CHANGE_PS) {
2262 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2263 if (!(ah->caps.hw_caps &
2264 ATH9K_HW_CAP_AUTOSLEEP)) {
2265 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2266 sc->imask |= ATH9K_INT_TIM_TIMER;
2267 ath9k_hw_set_interrupts(sc->sc_ah,
2268 sc->imask);
2269 }
2270 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2271 }
3cbb5dd7
VN		 2272 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2273 } else {
2274 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2275 if (!(ah->caps.hw_caps &
2276 ATH9K_HW_CAP_AUTOSLEEP)) {
2277 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2278 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2279 SC_OP_WAIT_FOR_CAB |
2280 SC_OP_WAIT_FOR_PSPOLL_DATA |
2281 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2282 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2283 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2284 ath9k_hw_set_interrupts(sc->sc_ah,
2285 sc->imask);
2286 }
3cbb5dd7
VN		 2287 }
2288 }
2289 }
2290
4797938c 2291 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2292 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2293 int pos = curchan->hw_value;
ae5eb026 2294
0e2dedf9
JM		 2295 aphy->chan_idx = pos;
2296 aphy->chan_is_ht = conf_is_ht(conf);
2297
8089cc47
JM		 2298 if (aphy->state == ATH_WIPHY_SCAN ||
2299 aphy->state == ATH_WIPHY_ACTIVE)
2300 ath9k_wiphy_pause_all_forced(sc, aphy);
2301 else {
2302 /*
2303 * Do not change operational channel based on a paused
2304 * wiphy changes.
2305 */
2306 goto skip_chan_change;
2307 }
0e2dedf9 2308
04bd4638
S		 2309 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2310 curchan->center_freq);
f078f209 2311
5f8e077c 2312 /* XXX: remove me eventualy */
0e2dedf9 2313 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2314
ecf70441 2315 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2316
0e2dedf9 2317 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2318 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2319 mutex_unlock(&sc->mutex);
e11602b7
S		 2320 return -EINVAL;
2321 }
094d05dc 2322 }
f078f209 2323
8089cc47 2324skip_chan_change:
5c020dc6 2325 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2326 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2327
aa33de09 2328 mutex_unlock(&sc->mutex);
141b38b6 2329
f078f209
LR		 2330 return 0;
2331}
2332
8feceb67
VT		 2333#define SUPPORTED_FILTERS \
2334 (FIF_PROMISC_IN_BSS | \
2335 FIF_ALLMULTI | \
2336 FIF_CONTROL | \
2337 FIF_OTHER_BSS | \
2338 FIF_BCN_PRBRESP_PROMISC | \
2339 FIF_FCSFAIL)
c83be688 2340
8feceb67
VT		 2341/* FIXME: sc->sc_full_reset ? */
2342static void ath9k_configure_filter(struct ieee80211_hw *hw,
2343 unsigned int changed_flags,
2344 unsigned int *total_flags,
2345 int mc_count,
2346 struct dev_mc_list *mclist)
2347{
bce048d7
JM		 2348 struct ath_wiphy *aphy = hw->priv;
2349 struct ath_softc *sc = aphy->sc;
8feceb67 2350 u32 rfilt;
f078f209 2351
8feceb67
VT		 2352 changed_flags &= SUPPORTED_FILTERS;
2353 *total_flags &= SUPPORTED_FILTERS;
f078f209 2354
b77f483f 2355 sc->rx.rxfilter = *total_flags;
aa68aeaa 2356 ath9k_ps_wakeup(sc);
8feceb67
VT		 2357 rfilt = ath_calcrxfilter(sc);
2358 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2359 ath9k_ps_restore(sc);
f078f209 2360
b77f483f 2361 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2362}
f078f209 2363
8feceb67
VT		 2364static void ath9k_sta_notify(struct ieee80211_hw *hw,
2365 struct ieee80211_vif *vif,
2366 enum sta_notify_cmd cmd,
17741cdc 2367 struct ieee80211_sta *sta)
8feceb67 2368{
bce048d7
JM		 2369 struct ath_wiphy *aphy = hw->priv;
2370 struct ath_softc *sc = aphy->sc;
f078f209 2371
8feceb67
VT		 2372 switch (cmd) {
2373 case STA_NOTIFY_ADD:
5640b08e 2374 ath_node_attach(sc, sta);
8feceb67
VT		 2375 break;
2376 case STA_NOTIFY_REMOVE:
b5aa9bf9 2377 ath_node_detach(sc, sta);
8feceb67
VT		 2378 break;
2379 default:
2380 break;
2381 }
f078f209
LR		 2382}
2383
141b38b6 2384static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2385 const struct ieee80211_tx_queue_params *params)
f078f209 2386{
bce048d7
JM		 2387 struct ath_wiphy *aphy = hw->priv;
2388 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2389 struct ath9k_tx_queue_info qi;
2390 int ret = 0, qnum;
f078f209 2391
8feceb67
VT		 2392 if (queue >= WME_NUM_AC)
2393 return 0;
f078f209 2394
141b38b6
S		 2395 mutex_lock(&sc->mutex);
2396
1ffb0610
S		 2397 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2398
8feceb67
VT		 2399 qi.tqi_aifs = params->aifs;
2400 qi.tqi_cwmin = params->cw_min;
2401 qi.tqi_cwmax = params->cw_max;
2402 qi.tqi_burstTime = params->txop;
2403 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2404
8feceb67 2405 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2406 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2407 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2408 queue, qnum, params->aifs, params->cw_min,
2409 params->cw_max, params->txop);
f078f209 2410
8feceb67
VT		 2411 ret = ath_txq_update(sc, qnum, &qi);
2412 if (ret)
04bd4638 2413 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2414
141b38b6
S		 2415 mutex_unlock(&sc->mutex);
2416
8feceb67
VT		 2417 return ret;
2418}
f078f209 2419
8feceb67
VT		 2420static int ath9k_set_key(struct ieee80211_hw *hw,
2421 enum set_key_cmd cmd,
dc822b5d
JB		 2422 struct ieee80211_vif *vif,
2423 struct ieee80211_sta *sta,
8feceb67
VT		 2424 struct ieee80211_key_conf *key)
2425{
bce048d7
JM		 2426 struct ath_wiphy *aphy = hw->priv;
2427 struct ath_softc *sc = aphy->sc;
8feceb67 2428 int ret = 0;
f078f209 2429
b3bd89ce
JM		 2430 if (modparam_nohwcrypt)
2431 return -ENOSPC;
2432
141b38b6 2433 mutex_lock(&sc->mutex);
3cbb5dd7 2434 ath9k_ps_wakeup(sc);
d8baa939 2435 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2436
8feceb67
VT		 2437 switch (cmd) {
2438 case SET_KEY:
3f53dd64 2439 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2440 if (ret >= 0) {
2441 key->hw_key_idx = ret;
8feceb67
VT		 2442 /* push IV and Michael MIC generation to stack */
2443 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2444 if (key->alg == ALG_TKIP)
2445 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2446 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2447 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2448 ret = 0;
8feceb67
VT		 2449 }
2450 break;
2451 case DISABLE_KEY:
2452 ath_key_delete(sc, key);
8feceb67
VT		 2453 break;
2454 default:
2455 ret = -EINVAL;
2456 }
f078f209 2457
3cbb5dd7 2458 ath9k_ps_restore(sc);
141b38b6
S		 2459 mutex_unlock(&sc->mutex);
2460
8feceb67
VT		 2461 return ret;
2462}
f078f209 2463
8feceb67
VT		 2464static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2465 struct ieee80211_vif *vif,
2466 struct ieee80211_bss_conf *bss_conf,
2467 u32 changed)
2468{
bce048d7
JM		 2469 struct ath_wiphy *aphy = hw->priv;
2470 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2471 struct ath_hw *ah = sc->sc_ah;
2472 struct ath_vif *avp = (void *)vif->drv_priv;
2473 u32 rfilt = 0;
2474 int error, i;
f078f209 2475
141b38b6
S		 2476 mutex_lock(&sc->mutex);
2477
2d0ddec5
JB		 2478 /*
2479 * TODO: Need to decide which hw opmode to use for
2480 * multi-interface cases
2481 * XXX: This belongs into add_interface!
2482 */
2483 if (vif->type == NL80211_IFTYPE_AP &&
2484 ah->opmode != NL80211_IFTYPE_AP) {
2485 ah->opmode = NL80211_IFTYPE_STATION;
2486 ath9k_hw_setopmode(ah);
2487 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2488 sc->curaid = 0;
2489 ath9k_hw_write_associd(sc);
2490 /* Request full reset to get hw opmode changed properly */
2491 sc->sc_flags |= SC_OP_FULL_RESET;
2492 }
2493
2494 if ((changed & BSS_CHANGED_BSSID) &&
2495 !is_zero_ether_addr(bss_conf->bssid)) {
2496 switch (vif->type) {
2497 case NL80211_IFTYPE_STATION:
2498 case NL80211_IFTYPE_ADHOC:
2499 case NL80211_IFTYPE_MESH_POINT:
2500 /* Set BSSID */
2501 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2502 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2503 sc->curaid = 0;
2504 ath9k_hw_write_associd(sc);
2505
2506 /* Set aggregation protection mode parameters */
2507 sc->config.ath_aggr_prot = 0;
2508
2509 DPRINTF(sc, ATH_DBG_CONFIG,
2510 "RX filter 0x%x bssid %pM aid 0x%x\n",
2511 rfilt, sc->curbssid, sc->curaid);
2512
2513 /* need to reconfigure the beacon */
2514 sc->sc_flags &= ~SC_OP_BEACONS ;
2515
2516 break;
2517 default:
2518 break;
2519 }
2520 }
2521
2522 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2523 (vif->type == NL80211_IFTYPE_AP) ||
2524 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2525 if ((changed & BSS_CHANGED_BEACON) ||
2526 (changed & BSS_CHANGED_BEACON_ENABLED &&
2527 bss_conf->enable_beacon)) {
2528 /*
2529 * Allocate and setup the beacon frame.
2530 *
2531 * Stop any previous beacon DMA. This may be
2532 * necessary, for example, when an ibss merge
2533 * causes reconfiguration; we may be called
2534 * with beacon transmission active.
2535 */
2536 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2537
2538 error = ath_beacon_alloc(aphy, vif);
2539 if (!error)
2540 ath_beacon_config(sc, vif);
2541 }
2542 }
2543
2544 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2545 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2546 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2547 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2548 ath9k_hw_keysetmac(sc->sc_ah,
2549 (u16)i,
2550 sc->curbssid);
2551 }
2552
2553 /* Only legacy IBSS for now */
2554 if (vif->type == NL80211_IFTYPE_ADHOC)
2555 ath_update_chainmask(sc, 0);
2556
8feceb67 2557 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2558 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2559 bss_conf->use_short_preamble);
2560 if (bss_conf->use_short_preamble)
2561 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2562 else
2563 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2564 }
f078f209 2565
8feceb67 2566 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2567 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2568 bss_conf->use_cts_prot);
2569 if (bss_conf->use_cts_prot &&
2570 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2571 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2572 else
2573 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2574 }
f078f209 2575
8feceb67 2576 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2577 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2578 bss_conf->assoc);
5640b08e 2579 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2580 }
141b38b6 2581
57c4d7b4
JB		 2582 /*
2583 * The HW TSF has to be reset when the beacon interval changes.
2584 * We set the flag here, and ath_beacon_config_ap() would take this
2585 * into account when it gets called through the subsequent
2586 * config_interface() call - with IFCC_BEACON in the changed field.
2587 */
2588
2589 if (changed & BSS_CHANGED_BEACON_INT) {
2590 sc->sc_flags |= SC_OP_TSF_RESET;
2591 sc->beacon_interval = bss_conf->beacon_int;
2592 }
2593
141b38b6 2594 mutex_unlock(&sc->mutex);
8feceb67 2595}
f078f209 2596
8feceb67
VT		 2597static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2598{
2599 u64 tsf;
bce048d7
JM		 2600 struct ath_wiphy *aphy = hw->priv;
2601 struct ath_softc *sc = aphy->sc;
f078f209 2602
141b38b6
S		 2603 mutex_lock(&sc->mutex);
2604 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2605 mutex_unlock(&sc->mutex);
f078f209 2606
8feceb67
VT		 2607 return tsf;
2608}
f078f209 2609
3b5d665b
AF		 2610static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2611{
bce048d7
JM		 2612 struct ath_wiphy *aphy = hw->priv;
2613 struct ath_softc *sc = aphy->sc;
3b5d665b 2614
141b38b6
S		 2615 mutex_lock(&sc->mutex);
2616 ath9k_hw_settsf64(sc->sc_ah, tsf);
2617 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2618}
2619
8feceb67
VT		 2620static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2621{
bce048d7
JM		 2622 struct ath_wiphy *aphy = hw->priv;
2623 struct ath_softc *sc = aphy->sc;
c83be688 2624
141b38b6
S		 2625 mutex_lock(&sc->mutex);
2626 ath9k_hw_reset_tsf(sc->sc_ah);
2627 mutex_unlock(&sc->mutex);
8feceb67 2628}
f078f209 2629
8feceb67 2630static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2631 enum ieee80211_ampdu_mlme_action action,
2632 struct ieee80211_sta *sta,
2633 u16 tid, u16 *ssn)
8feceb67 2634{
bce048d7
JM		 2635 struct ath_wiphy *aphy = hw->priv;
2636 struct ath_softc *sc = aphy->sc;
8feceb67 2637 int ret = 0;
f078f209 2638
8feceb67
VT		 2639 switch (action) {
2640 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2641 if (!(sc->sc_flags & SC_OP_RXAGGR))
2642 ret = -ENOTSUPP;
8feceb67
VT		 2643 break;
2644 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2645 break;
2646 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2647 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2648 if (ret < 0)
2649 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2650 "Unable to start TX aggregation\n");
8feceb67 2651 else
17741cdc 2652 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2653 break;
2654 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2655 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2656 if (ret < 0)
2657 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2658 "Unable to stop TX aggregation\n");
f078f209 2659
17741cdc 2660 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2661 break;
b1720231 2662 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2663 ath_tx_aggr_resume(sc, sta, tid);
2664 break;
8feceb67 2665 default:
04bd4638 2666 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2667 }
2668
2669 return ret;
f078f209
LR		 2670}
2671
0c98de65
S		 2672static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2673{
bce048d7
JM		 2674 struct ath_wiphy *aphy = hw->priv;
2675 struct ath_softc *sc = aphy->sc;
0c98de65 2676
8089cc47
JM		 2677 if (ath9k_wiphy_scanning(sc)) {
2678 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2679 "same time\n");
2680 /*
2681 * Do not allow the concurrent scanning state for now. This
2682 * could be improved with scanning control moved into ath9k.
2683 */
2684 return;
2685 }
2686
2687 aphy->state = ATH_WIPHY_SCAN;
2688 ath9k_wiphy_pause_all_forced(sc, aphy);
2689
e5f0921a 2690 spin_lock_bh(&sc->ani_lock);
0c98de65 2691 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 2692 spin_unlock_bh(&sc->ani_lock);
0c98de65
S		 2693}
2694
2695static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2696{
bce048d7
JM		 2697 struct ath_wiphy *aphy = hw->priv;
2698 struct ath_softc *sc = aphy->sc;
0c98de65 2699
e5f0921a 2700 spin_lock_bh(&sc->ani_lock);
8089cc47 2701 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2702 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2703 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 2704 spin_unlock_bh(&sc->ani_lock);
0c98de65
S		 2705}
2706
6baff7f9 2707struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2708 .tx = ath9k_tx,
2709 .start = ath9k_start,
2710 .stop = ath9k_stop,
2711 .add_interface = ath9k_add_interface,
2712 .remove_interface = ath9k_remove_interface,
2713 .config = ath9k_config,
8feceb67 2714 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2715 .sta_notify = ath9k_sta_notify,
2716 .conf_tx = ath9k_conf_tx,
8feceb67 2717 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2718 .set_key = ath9k_set_key,
8feceb67 2719 .get_tsf = ath9k_get_tsf,
3b5d665b 2720 .set_tsf = ath9k_set_tsf,
8feceb67 2721 .reset_tsf = ath9k_reset_tsf,
4233df6b 2722 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2723 .sw_scan_start = ath9k_sw_scan_start,
2724 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2725 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 2726};
2727
392dff83
BP		 2728static struct {
2729 u32 version;
2730 const char * name;
2731} ath_mac_bb_names[] = {
2732 { AR_SREV_VERSION_5416_PCI, "5416" },
2733 { AR_SREV_VERSION_5416_PCIE, "5418" },
2734 { AR_SREV_VERSION_9100, "9100" },
2735 { AR_SREV_VERSION_9160, "9160" },
2736 { AR_SREV_VERSION_9280, "9280" },
2737 { AR_SREV_VERSION_9285, "9285" }
2738};
2739
2740static struct {
2741 u16 version;
2742 const char * name;
2743} ath_rf_names[] = {
2744 { 0, "5133" },
2745 { AR_RAD5133_SREV_MAJOR, "5133" },
2746 { AR_RAD5122_SREV_MAJOR, "5122" },
2747 { AR_RAD2133_SREV_MAJOR, "2133" },
2748 { AR_RAD2122_SREV_MAJOR, "2122" }
2749};
2750
2751/*
2752 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2753 */
6baff7f9 2754const char *
392dff83
BP		 2755ath_mac_bb_name(u32 mac_bb_version)
2756{
2757 int i;
2758
2759 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2760 if (ath_mac_bb_names[i].version == mac_bb_version) {
2761 return ath_mac_bb_names[i].name;
2762 }
2763 }
2764
2765 return "????";
2766}
2767
2768/*
2769 * Return the RF name. "????" is returned if the RF is unknown.
2770 */
6baff7f9 2771const char *
392dff83
BP		 2772ath_rf_name(u16 rf_version)
2773{
2774 int i;
2775
2776 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2777 if (ath_rf_names[i].version == rf_version) {
2778 return ath_rf_names[i].name;
2779 }
2780 }
2781
2782 return "????";
2783}
2784
6baff7f9 2785static int __init ath9k_init(void)
f078f209 2786{
ca8a8560
VT		 2787 int error;
2788
ca8a8560
VT		 2789 /* Register rate control algorithm */
2790 error = ath_rate_control_register();
2791 if (error != 0) {
2792 printk(KERN_ERR
b51bb3cd
LR		 2793 "ath9k: Unable to register rate control "
2794 "algorithm: %d\n",
ca8a8560 2795 error);
6baff7f9 2796 goto err_out;
ca8a8560
VT		 2797 }
2798
19d8bc22
GJ		 2799 error = ath9k_debug_create_root();
2800 if (error) {
2801 printk(KERN_ERR
2802 "ath9k: Unable to create debugfs root: %d\n",
2803 error);
2804 goto err_rate_unregister;
2805 }
2806
6baff7f9
GJ		 2807 error = ath_pci_init();
2808 if (error < 0) {
f078f209 2809 printk(KERN_ERR
b51bb3cd 2810 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2811 error = -ENODEV;
19d8bc22 2812 goto err_remove_root;
f078f209
LR		 2813 }
2814
09329d37
GJ		 2815 error = ath_ahb_init();
2816 if (error < 0) {
2817 error = -ENODEV;
2818 goto err_pci_exit;
2819 }
2820
f078f209 2821 return 0;
6baff7f9 2822
09329d37
GJ		 2823 err_pci_exit:
2824 ath_pci_exit();
2825
19d8bc22
GJ		 2826 err_remove_root:
2827 ath9k_debug_remove_root();
6baff7f9
GJ		 2828 err_rate_unregister:
2829 ath_rate_control_unregister();
2830 err_out:
2831 return error;
f078f209 2832}
6baff7f9 2833module_init(ath9k_init);
f078f209 2834
6baff7f9 2835static void __exit ath9k_exit(void)
f078f209 2836{
09329d37 2837 ath_ahb_exit();
6baff7f9 2838 ath_pci_exit();
19d8bc22 2839 ath9k_debug_remove_root();
ca8a8560 2840 ath_rate_control_unregister();
04bd4638 2841 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2842}
6baff7f9 2843module_exit(ath9k_exit);
Linux kernel - Deliverables
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