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ath9k: avoid usage of ath9k_hw_setpower() on hw.c
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
f078f209
LR		 21static char *dev_info = "ath9k";
22
23MODULE_AUTHOR("Atheros Communications");
24MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26MODULE_LICENSE("Dual BSD/GPL");
27
b3bd89ce
JM		 28static int modparam_nohwcrypt;
29module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
5f8e077c
LR		 32/* We use the hw_value as an index into our private channel structure */
33
34#define CHAN2G(_freq, _idx) { \
35 .center_freq = (_freq), \
36 .hw_value = (_idx), \
eeddfd9d 37 .max_power = 20, \
5f8e077c
LR		 38}
39
40#define CHAN5G(_freq, _idx) { \
41 .band = IEEE80211_BAND_5GHZ, \
42 .center_freq = (_freq), \
43 .hw_value = (_idx), \
eeddfd9d 44 .max_power = 20, \
5f8e077c
LR		 45}
46
47/* Some 2 GHz radios are actually tunable on 2312-2732
48 * on 5 MHz steps, we support the channels which we know
49 * we have calibration data for all cards though to make
50 * this static */
51static struct ieee80211_channel ath9k_2ghz_chantable[] = {
52 CHAN2G(2412, 0), /* Channel 1 */
53 CHAN2G(2417, 1), /* Channel 2 */
54 CHAN2G(2422, 2), /* Channel 3 */
55 CHAN2G(2427, 3), /* Channel 4 */
56 CHAN2G(2432, 4), /* Channel 5 */
57 CHAN2G(2437, 5), /* Channel 6 */
58 CHAN2G(2442, 6), /* Channel 7 */
59 CHAN2G(2447, 7), /* Channel 8 */
60 CHAN2G(2452, 8), /* Channel 9 */
61 CHAN2G(2457, 9), /* Channel 10 */
62 CHAN2G(2462, 10), /* Channel 11 */
63 CHAN2G(2467, 11), /* Channel 12 */
64 CHAN2G(2472, 12), /* Channel 13 */
65 CHAN2G(2484, 13), /* Channel 14 */
66};
67
68/* Some 5 GHz radios are actually tunable on XXXX-YYYY
69 * on 5 MHz steps, we support the channels which we know
70 * we have calibration data for all cards though to make
71 * this static */
72static struct ieee80211_channel ath9k_5ghz_chantable[] = {
73 /* _We_ call this UNII 1 */
74 CHAN5G(5180, 14), /* Channel 36 */
75 CHAN5G(5200, 15), /* Channel 40 */
76 CHAN5G(5220, 16), /* Channel 44 */
77 CHAN5G(5240, 17), /* Channel 48 */
78 /* _We_ call this UNII 2 */
79 CHAN5G(5260, 18), /* Channel 52 */
80 CHAN5G(5280, 19), /* Channel 56 */
81 CHAN5G(5300, 20), /* Channel 60 */
82 CHAN5G(5320, 21), /* Channel 64 */
83 /* _We_ call this "Middle band" */
84 CHAN5G(5500, 22), /* Channel 100 */
85 CHAN5G(5520, 23), /* Channel 104 */
86 CHAN5G(5540, 24), /* Channel 108 */
87 CHAN5G(5560, 25), /* Channel 112 */
88 CHAN5G(5580, 26), /* Channel 116 */
89 CHAN5G(5600, 27), /* Channel 120 */
90 CHAN5G(5620, 28), /* Channel 124 */
91 CHAN5G(5640, 29), /* Channel 128 */
92 CHAN5G(5660, 30), /* Channel 132 */
93 CHAN5G(5680, 31), /* Channel 136 */
94 CHAN5G(5700, 32), /* Channel 140 */
95 /* _We_ call this UNII 3 */
96 CHAN5G(5745, 33), /* Channel 149 */
97 CHAN5G(5765, 34), /* Channel 153 */
98 CHAN5G(5785, 35), /* Channel 157 */
99 CHAN5G(5805, 36), /* Channel 161 */
100 CHAN5G(5825, 37), /* Channel 165 */
101};
102
ce111bad
LR		 103static void ath_cache_conf_rate(struct ath_softc *sc,
104 struct ieee80211_conf *conf)
ff37e337 105{
030bb495
LR		 106 switch (conf->channel->band) {
107 case IEEE80211_BAND_2GHZ:
108 if (conf_is_ht20(conf))
109 sc->cur_rate_table =
110 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
111 else if (conf_is_ht40_minus(conf))
112 sc->cur_rate_table =
113 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
114 else if (conf_is_ht40_plus(conf))
115 sc->cur_rate_table =
116 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 117 else
030bb495
LR		 118 sc->cur_rate_table =
119 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 120 break;
121 case IEEE80211_BAND_5GHZ:
122 if (conf_is_ht20(conf))
123 sc->cur_rate_table =
124 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
125 else if (conf_is_ht40_minus(conf))
126 sc->cur_rate_table =
127 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
128 else if (conf_is_ht40_plus(conf))
129 sc->cur_rate_table =
130 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
131 else
96742256
LR		 132 sc->cur_rate_table =
133 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 134 break;
135 default:
ce111bad 136 BUG_ON(1);
030bb495
LR		 137 break;
138 }
ff37e337
S		 139}
140
141static void ath_update_txpow(struct ath_softc *sc)
142{
cbe61d8a 143 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 144 u32 txpow;
145
17d7904d
S		 146 if (sc->curtxpow != sc->config.txpowlimit) {
147 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 148 /* read back in case value is clamped */
149 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 150 sc->curtxpow = txpow;
ff37e337
S		 151 }
152}
153
154static u8 parse_mpdudensity(u8 mpdudensity)
155{
156 /*
157 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
158 * 0 for no restriction
159 * 1 for 1/4 us
160 * 2 for 1/2 us
161 * 3 for 1 us
162 * 4 for 2 us
163 * 5 for 4 us
164 * 6 for 8 us
165 * 7 for 16 us
166 */
167 switch (mpdudensity) {
168 case 0:
169 return 0;
170 case 1:
171 case 2:
172 case 3:
173 /* Our lower layer calculations limit our precision to
174 1 microsecond */
175 return 1;
176 case 4:
177 return 2;
178 case 5:
179 return 4;
180 case 6:
181 return 8;
182 case 7:
183 return 16;
184 default:
185 return 0;
186 }
187}
188
189static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
190{
4f0fc7c3 191 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 192 struct ieee80211_supported_band *sband;
193 struct ieee80211_rate *rate;
194 int i, maxrates;
195
196 switch (band) {
197 case IEEE80211_BAND_2GHZ:
198 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
199 break;
200 case IEEE80211_BAND_5GHZ:
201 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
202 break;
203 default:
204 break;
205 }
206
207 if (rate_table == NULL)
208 return;
209
210 sband = &sc->sbands[band];
211 rate = sc->rates[band];
212
213 if (rate_table->rate_cnt > ATH_RATE_MAX)
214 maxrates = ATH_RATE_MAX;
215 else
216 maxrates = rate_table->rate_cnt;
217
218 for (i = 0; i < maxrates; i++) {
219 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
220 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 221 if (rate_table->info[i].short_preamble) {
222 rate[i].hw_value_short = rate_table->info[i].ratecode |
223 rate_table->info[i].short_preamble;
224 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
225 }
ff37e337 226 sband->n_bitrates++;
f46730d1 227
4d6b228d 228 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
04bd4638 229 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 230 }
231}
232
82880a7c
VT		 233static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
234 struct ieee80211_hw *hw)
235{
236 struct ieee80211_channel *curchan = hw->conf.channel;
237 struct ath9k_channel *channel;
238 u8 chan_idx;
239
240 chan_idx = curchan->hw_value;
241 channel = &sc->sc_ah->channels[chan_idx];
242 ath9k_update_ichannel(sc, hw, channel);
243 return channel;
244}
245
a91d75ae
LR		 246void ath9k_ps_wakeup(struct ath_softc *sc)
247{
248 unsigned long flags;
249
250 spin_lock_irqsave(&sc->sc_pm_lock, flags);
251 if (++sc->ps_usecount != 1)
252 goto unlock;
253
254 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
255
256 unlock:
257 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
258}
259
260void ath9k_ps_restore(struct ath_softc *sc)
261{
262 unsigned long flags;
263
264 spin_lock_irqsave(&sc->sc_pm_lock, flags);
265 if (--sc->ps_usecount != 0)
266 goto unlock;
267
268 if (sc->ps_enabled &&
269 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
270 SC_OP_WAIT_FOR_CAB |
271 SC_OP_WAIT_FOR_PSPOLL_DATA |
272 SC_OP_WAIT_FOR_TX_ACK)))
273 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
274
275 unlock:
276 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
277}
278
ff37e337
S		 279/*
280 * Set/change channels. If the channel is really being changed, it's done
281 * by reseting the chip. To accomplish this we must first cleanup any pending
282 * DMA, then restart stuff.
283*/
0e2dedf9
JM		 284int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
285 struct ath9k_channel *hchan)
ff37e337 286{
cbe61d8a 287 struct ath_hw *ah = sc->sc_ah;
ff37e337 288 bool fastcc = true, stopped;
ae8d2858
LR		 289 struct ieee80211_channel *channel = hw->conf.channel;
290 int r;
ff37e337
S		 291
292 if (sc->sc_flags & SC_OP_INVALID)
293 return -EIO;
294
3cbb5dd7
VN		 295 ath9k_ps_wakeup(sc);
296
c0d7c7af
LR		 297 /*
298 * This is only performed if the channel settings have
299 * actually changed.
300 *
301 * To switch channels clear any pending DMA operations;
302 * wait long enough for the RX fifo to drain, reset the
303 * hardware at the new frequency, and then re-enable
304 * the relevant bits of the h/w.
305 */
306 ath9k_hw_set_interrupts(ah, 0);
043a0405 307 ath_drain_all_txq(sc, false);
c0d7c7af 308 stopped = ath_stoprecv(sc);
ff37e337 309
c0d7c7af
LR		 310 /* XXX: do not flush receive queue here. We don't want
311 * to flush data frames already in queue because of
312 * changing channel. */
ff37e337 313
c0d7c7af
LR		 314 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
315 fastcc = false;
316
4d6b228d 317 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
c0d7c7af 318 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 319 sc->sc_ah->curchan->channel,
c0d7c7af 320 channel->center_freq, sc->tx_chan_width);
ff37e337 321
c0d7c7af
LR		 322 spin_lock_bh(&sc->sc_resetlock);
323
324 r = ath9k_hw_reset(ah, hchan, fastcc);
325 if (r) {
4d6b228d 326 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
c0d7c7af 327 "Unable to reset channel (%u Mhz) "
6b45784f 328 "reset status %d\n",
c0d7c7af
LR		 329 channel->center_freq, r);
330 spin_unlock_bh(&sc->sc_resetlock);
3989279c 331 goto ps_restore;
ff37e337 332 }
c0d7c7af
LR		 333 spin_unlock_bh(&sc->sc_resetlock);
334
c0d7c7af
LR		 335 sc->sc_flags &= ~SC_OP_FULL_RESET;
336
337 if (ath_startrecv(sc) != 0) {
4d6b228d 338 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
c0d7c7af 339 "Unable to restart recv logic\n");
3989279c
GJ		 340 r = -EIO;
341 goto ps_restore;
c0d7c7af
LR		 342 }
343
344 ath_cache_conf_rate(sc, &hw->conf);
345 ath_update_txpow(sc);
17d7904d 346 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 347
348 ps_restore:
3cbb5dd7 349 ath9k_ps_restore(sc);
3989279c 350 return r;
ff37e337
S		 351}
352
353/*
354 * This routine performs the periodic noise floor calibration function
355 * that is used to adjust and optimize the chip performance. This
356 * takes environmental changes (location, temperature) into account.
357 * When the task is complete, it reschedules itself depending on the
358 * appropriate interval that was calculated.
359 */
360static void ath_ani_calibrate(unsigned long data)
361{
20977d3e
S		 362 struct ath_softc *sc = (struct ath_softc *)data;
363 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 364 bool longcal = false;
365 bool shortcal = false;
366 bool aniflag = false;
367 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 368 u32 cal_interval, short_cal_interval;
ff37e337 369
20977d3e
S		 370 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
371 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 372
373 /*
374 * don't calibrate when we're scanning.
375 * we are most likely not on our home channel.
376 */
e5f0921a 377 spin_lock(&sc->ani_lock);
0c98de65 378 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 379 goto set_timer;
ff37e337 380
1ffc1c61
JM		 381 /* Only calibrate if awake */
382 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
383 goto set_timer;
384
385 ath9k_ps_wakeup(sc);
386
ff37e337 387 /* Long calibration runs independently of short calibration. */
17d7904d 388 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 389 longcal = true;
4d6b228d 390 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 391 sc->ani.longcal_timer = timestamp;
ff37e337
S		 392 }
393
17d7904d
S		 394 /* Short calibration applies only while caldone is false */
395 if (!sc->ani.caldone) {
20977d3e 396 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 397 shortcal = true;
4d6b228d 398 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 399 sc->ani.shortcal_timer = timestamp;
400 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 401 }
402 } else {
17d7904d 403 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 404 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 405 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
406 if (sc->ani.caldone)
407 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 408 }
409 }
410
411 /* Verify whether we must check ANI */
20977d3e 412 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 413 aniflag = true;
17d7904d 414 sc->ani.checkani_timer = timestamp;
ff37e337
S		 415 }
416
417 /* Skip all processing if there's nothing to do. */
418 if (longcal || shortcal || aniflag) {
419 /* Call ANI routine if necessary */
420 if (aniflag)
22e66a4c 421 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S		 422
423 /* Perform calibration if necessary */
424 if (longcal || shortcal) {
379f0440
S		 425 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
426 sc->rx_chainmask, longcal);
427
428 if (longcal)
429 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
430 ah->curchan);
431
4d6b228d 432 DPRINTF(sc->sc_ah, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
379f0440
S		 433 ah->curchan->channel, ah->curchan->channelFlags,
434 sc->ani.noise_floor);
ff37e337
S		 435 }
436 }
437
1ffc1c61
JM		 438 ath9k_ps_restore(sc);
439
20977d3e 440set_timer:
e5f0921a 441 spin_unlock(&sc->ani_lock);
ff37e337
S		 442 /*
443 * Set timer interval based on previous results.
444 * The interval must be the shortest necessary to satisfy ANI,
445 * short calibration and long calibration.
446 */
aac9207e 447 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 448 if (sc->sc_ah->config.enable_ani)
aac9207e 449 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 450 if (!sc->ani.caldone)
20977d3e 451 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 452
17d7904d 453 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 454}
455
415f738e
S		 456static void ath_start_ani(struct ath_softc *sc)
457{
458 unsigned long timestamp = jiffies_to_msecs(jiffies);
459
460 sc->ani.longcal_timer = timestamp;
461 sc->ani.shortcal_timer = timestamp;
462 sc->ani.checkani_timer = timestamp;
463
464 mod_timer(&sc->ani.timer,
465 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
466}
467
ff37e337
S		 468/*
469 * Update tx/rx chainmask. For legacy association,
470 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 471 * the chainmask configuration, for bt coexistence, use
472 * the chainmask configuration even in legacy mode.
ff37e337 473 */
0e2dedf9 474void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 475{
af03abec
LR		 476 struct ath_hw *ah = sc->sc_ah;
477
3d832611 478 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
766ec4a9 479 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
2660b81a
S		 480 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
481 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 482 } else {
17d7904d
S		 483 sc->tx_chainmask = 1;
484 sc->rx_chainmask = 1;
ff37e337
S		 485 }
486
af03abec 487 DPRINTF(ah, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 488 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 489}
490
491static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
492{
493 struct ath_node *an;
494
495 an = (struct ath_node *)sta->drv_priv;
496
87792efc 497 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 498 ath_tx_node_init(sc, an);
9e98ac65 499 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 500 sta->ht_cap.ampdu_factor);
501 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 502 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 503 }
ff37e337
S		 504}
505
506static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
507{
508 struct ath_node *an = (struct ath_node *)sta->drv_priv;
509
510 if (sc->sc_flags & SC_OP_TXAGGR)
511 ath_tx_node_cleanup(sc, an);
512}
513
514static void ath9k_tasklet(unsigned long data)
515{
516 struct ath_softc *sc = (struct ath_softc *)data;
af03abec
LR		 517 struct ath_hw *ah = sc->sc_ah;
518
17d7904d 519 u32 status = sc->intrstatus;
ff37e337 520
153e080d
VT		 521 ath9k_ps_wakeup(sc);
522
ff37e337 523 if (status & ATH9K_INT_FATAL) {
ff37e337 524 ath_reset(sc, false);
153e080d 525 ath9k_ps_restore(sc);
ff37e337 526 return;
063d8be3 527 }
ff37e337 528
063d8be3
S		 529 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
530 spin_lock_bh(&sc->rx.rxflushlock);
531 ath_rx_tasklet(sc, 0);
532 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 533 }
534
063d8be3
S		 535 if (status & ATH9K_INT_TX)
536 ath_tx_tasklet(sc);
537
96148326 538 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 539 /*
540 * TSF sync does not look correct; remain awake to sync with
541 * the next Beacon.
542 */
af03abec 543 DPRINTF(ah, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 544 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 545 }
546
766ec4a9 547 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT		 548 if (status & ATH9K_INT_GENTIMER)
549 ath_gen_timer_isr(sc->sc_ah);
550
ff37e337 551 /* re-enable hardware interrupt */
af03abec 552 ath9k_hw_set_interrupts(ah, sc->imask);
153e080d 553 ath9k_ps_restore(sc);
ff37e337
S		 554}
555
6baff7f9 556irqreturn_t ath_isr(int irq, void *dev)
ff37e337 557{
063d8be3
S		 558#define SCHED_INTR ( \
559 ATH9K_INT_FATAL | \
560 ATH9K_INT_RXORN | \
561 ATH9K_INT_RXEOL | \
562 ATH9K_INT_RX | \
563 ATH9K_INT_TX | \
564 ATH9K_INT_BMISS | \
565 ATH9K_INT_CST | \
ebb8e1d7
VT		 566 ATH9K_INT_TSFOOR | \
567 ATH9K_INT_GENTIMER)
063d8be3 568
ff37e337 569 struct ath_softc *sc = dev;
cbe61d8a 570 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 571 enum ath9k_int status;
572 bool sched = false;
573
063d8be3
S		 574 /*
575 * The hardware is not ready/present, don't
576 * touch anything. Note this can happen early
577 * on if the IRQ is shared.
578 */
579 if (sc->sc_flags & SC_OP_INVALID)
580 return IRQ_NONE;
ff37e337 581
063d8be3
S		 582
583 /* shared irq, not for us */
584
153e080d 585 if (!ath9k_hw_intrpend(ah))
063d8be3 586 return IRQ_NONE;
063d8be3
S		 587
588 /*
589 * Figure out the reason(s) for the interrupt. Note
590 * that the hal returns a pseudo-ISR that may include
591 * bits we haven't explicitly enabled so we mask the
592 * value to insure we only process bits we requested.
593 */
594 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
595 status &= sc->imask; /* discard unasked-for bits */
ff37e337 596
063d8be3
S		 597 /*
598 * If there are no status bits set, then this interrupt was not
599 * for me (should have been caught above).
600 */
153e080d 601 if (!status)
063d8be3 602 return IRQ_NONE;
ff37e337 603
063d8be3
S		 604 /* Cache the status */
605 sc->intrstatus = status;
606
607 if (status & SCHED_INTR)
608 sched = true;
609
610 /*
611 * If a FATAL or RXORN interrupt is received, we have to reset the
612 * chip immediately.
613 */
614 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
615 goto chip_reset;
616
617 if (status & ATH9K_INT_SWBA)
618 tasklet_schedule(&sc->bcon_tasklet);
619
620 if (status & ATH9K_INT_TXURN)
621 ath9k_hw_updatetxtriglevel(ah, true);
622
623 if (status & ATH9K_INT_MIB) {
ff37e337 624 /*
063d8be3
S		 625 * Disable interrupts until we service the MIB
626 * interrupt; otherwise it will continue to
627 * fire.
ff37e337 628 */
063d8be3
S		 629 ath9k_hw_set_interrupts(ah, 0);
630 /*
631 * Let the hal handle the event. We assume
632 * it will clear whatever condition caused
633 * the interrupt.
634 */
22e66a4c 635 ath9k_hw_procmibevent(ah);
063d8be3
S		 636 ath9k_hw_set_interrupts(ah, sc->imask);
637 }
ff37e337 638
153e080d
VT		 639 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
640 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 641 /* Clear RxAbort bit so that we can
642 * receive frames */
643 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 644 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 645 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 646 }
063d8be3
S		 647
648chip_reset:
ff37e337 649
817e11de
S		 650 ath_debug_stat_interrupt(sc, status);
651
ff37e337
S		 652 if (sched) {
653 /* turn off every interrupt except SWBA */
17d7904d 654 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 655 tasklet_schedule(&sc->intr_tq);
656 }
657
658 return IRQ_HANDLED;
063d8be3
S		 659
660#undef SCHED_INTR
ff37e337
S		 661}
662
f078f209 663static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 664 struct ieee80211_channel *chan,
094d05dc 665 enum nl80211_channel_type channel_type)
f078f209
LR		 666{
667 u32 chanmode = 0;
f078f209
LR		 668
669 switch (chan->band) {
670 case IEEE80211_BAND_2GHZ:
094d05dc
S		 671 switch(channel_type) {
672 case NL80211_CHAN_NO_HT:
673 case NL80211_CHAN_HT20:
f078f209 674 chanmode = CHANNEL_G_HT20;
094d05dc
S		 675 break;
676 case NL80211_CHAN_HT40PLUS:
f078f209 677 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 678 break;
679 case NL80211_CHAN_HT40MINUS:
f078f209 680 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 681 break;
682 }
f078f209
LR		 683 break;
684 case IEEE80211_BAND_5GHZ:
094d05dc
S		 685 switch(channel_type) {
686 case NL80211_CHAN_NO_HT:
687 case NL80211_CHAN_HT20:
f078f209 688 chanmode = CHANNEL_A_HT20;
094d05dc
S		 689 break;
690 case NL80211_CHAN_HT40PLUS:
f078f209 691 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 692 break;
693 case NL80211_CHAN_HT40MINUS:
f078f209 694 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 695 break;
696 }
f078f209
LR		 697 break;
698 default:
699 break;
700 }
701
702 return chanmode;
703}
704
6ace2891 705static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 706 struct ath9k_keyval *hk, const u8 *addr,
707 bool authenticator)
f078f209 708{
6ace2891
JM		 709 const u8 *key_rxmic;
710 const u8 *key_txmic;
f078f209 711
6ace2891
JM		 712 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
713 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 714
715 if (addr == NULL) {
d216aaa6
JM		 716 /*
717 * Group key installation - only two key cache entries are used
718 * regardless of splitmic capability since group key is only
719 * used either for TX or RX.
720 */
3f53dd64
JM		 721 if (authenticator) {
722 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
723 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
724 } else {
725 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
726 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
727 }
d216aaa6 728 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 729 }
17d7904d 730 if (!sc->splitmic) {
d216aaa6 731 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 732 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
733 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 734 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 735 }
d216aaa6
JM		 736
737 /* Separate key cache entries for TX and RX */
738
739 /* TX key goes at first index, RX key at +32. */
f078f209 740 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 741 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
742 /* TX MIC entry failed. No need to proceed further */
4d6b228d 743 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
04bd4638 744 "Setting TX MIC Key Failed\n");
f078f209
LR		 745 return 0;
746 }
747
748 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
749 /* XXX delete tx key on failure? */
d216aaa6 750 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 751}
752
753static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
754{
755 int i;
756
17d7904d
S		 757 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
758 if (test_bit(i, sc->keymap) ||
759 test_bit(i + 64, sc->keymap))
6ace2891 760 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 761 if (sc->splitmic &&
762 (test_bit(i + 32, sc->keymap) ||
763 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 764 continue; /* At least one part of TKIP key allocated */
765
766 /* Found a free slot for a TKIP key */
767 return i;
768 }
769 return -1;
770}
771
772static int ath_reserve_key_cache_slot(struct ath_softc *sc)
773{
774 int i;
775
776 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 777 if (sc->splitmic) {
778 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
779 if (!test_bit(i, sc->keymap) &&
780 (test_bit(i + 32, sc->keymap) ||
781 test_bit(i + 64, sc->keymap) ||
782 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 783 return i;
17d7904d
S		 784 if (!test_bit(i + 32, sc->keymap) &&
785 (test_bit(i, sc->keymap) ||
786 test_bit(i + 64, sc->keymap) ||
787 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 788 return i + 32;
17d7904d
S		 789 if (!test_bit(i + 64, sc->keymap) &&
790 (test_bit(i , sc->keymap) ||
791 test_bit(i + 32, sc->keymap) ||
792 test_bit(i + 64 + 32, sc->keymap)))
ea612132 793 return i + 64;
17d7904d
S		 794 if (!test_bit(i + 64 + 32, sc->keymap) &&
795 (test_bit(i, sc->keymap) ||
796 test_bit(i + 32, sc->keymap) ||
797 test_bit(i + 64, sc->keymap)))
ea612132 798 return i + 64 + 32;
6ace2891
JM		 799 }
800 } else {
17d7904d
S		 801 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
802 if (!test_bit(i, sc->keymap) &&
803 test_bit(i + 64, sc->keymap))
6ace2891 804 return i;
17d7904d
S		 805 if (test_bit(i, sc->keymap) &&
806 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 807 return i + 64;
808 }
809 }
810
811 /* No partially used TKIP slots, pick any available slot */
17d7904d 812 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 813 /* Do not allow slots that could be needed for TKIP group keys
814 * to be used. This limitation could be removed if we know that
815 * TKIP will not be used. */
816 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
817 continue;
17d7904d 818 if (sc->splitmic) {
be2864cf
JM		 819 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
820 continue;
821 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
822 continue;
823 }
824
17d7904d 825 if (!test_bit(i, sc->keymap))
6ace2891
JM		 826 return i; /* Found a free slot for a key */
827 }
828
829 /* No free slot found */
830 return -1;
f078f209
LR		 831}
832
833static int ath_key_config(struct ath_softc *sc,
3f53dd64 834 struct ieee80211_vif *vif,
dc822b5d 835 struct ieee80211_sta *sta,
f078f209
LR		 836 struct ieee80211_key_conf *key)
837{
f078f209
LR		 838 struct ath9k_keyval hk;
839 const u8 *mac = NULL;
840 int ret = 0;
6ace2891 841 int idx;
f078f209
LR		 842
843 memset(&hk, 0, sizeof(hk));
844
845 switch (key->alg) {
846 case ALG_WEP:
847 hk.kv_type = ATH9K_CIPHER_WEP;
848 break;
849 case ALG_TKIP:
850 hk.kv_type = ATH9K_CIPHER_TKIP;
851 break;
852 case ALG_CCMP:
853 hk.kv_type = ATH9K_CIPHER_AES_CCM;
854 break;
855 default:
ca470b29 856 return -EOPNOTSUPP;
f078f209
LR		 857 }
858
6ace2891 859 hk.kv_len = key->keylen;
f078f209
LR		 860 memcpy(hk.kv_val, key->key, key->keylen);
861
6ace2891
JM		 862 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
863 /* For now, use the default keys for broadcast keys. This may
864 * need to change with virtual interfaces. */
865 idx = key->keyidx;
866 } else if (key->keyidx) {
dc822b5d
JB		 867 if (WARN_ON(!sta))
868 return -EOPNOTSUPP;
869 mac = sta->addr;
870
6ace2891
JM		 871 if (vif->type != NL80211_IFTYPE_AP) {
872 /* Only keyidx 0 should be used with unicast key, but
873 * allow this for client mode for now. */
874 idx = key->keyidx;
875 } else
876 return -EIO;
f078f209 877 } else {
dc822b5d
JB		 878 if (WARN_ON(!sta))
879 return -EOPNOTSUPP;
880 mac = sta->addr;
881
6ace2891
JM		 882 if (key->alg == ALG_TKIP)
883 idx = ath_reserve_key_cache_slot_tkip(sc);
884 else
885 idx = ath_reserve_key_cache_slot(sc);
886 if (idx < 0)
ca470b29 887 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 888 }
889
890 if (key->alg == ALG_TKIP)
3f53dd64
JM		 891 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
892 vif->type == NL80211_IFTYPE_AP);
f078f209 893 else
d216aaa6 894 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 895
896 if (!ret)
897 return -EIO;
898
17d7904d 899 set_bit(idx, sc->keymap);
6ace2891 900 if (key->alg == ALG_TKIP) {
17d7904d
S		 901 set_bit(idx + 64, sc->keymap);
902 if (sc->splitmic) {
903 set_bit(idx + 32, sc->keymap);
904 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 905 }
906 }
907
908 return idx;
f078f209
LR		 909}
910
911static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
912{
6ace2891
JM		 913 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
914 if (key->hw_key_idx < IEEE80211_WEP_NKID)
915 return;
916
17d7904d 917 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 918 if (key->alg != ALG_TKIP)
919 return;
f078f209 920
17d7904d
S		 921 clear_bit(key->hw_key_idx + 64, sc->keymap);
922 if (sc->splitmic) {
923 clear_bit(key->hw_key_idx + 32, sc->keymap);
924 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 925 }
f078f209
LR		 926}
927
eb2599ca
S		 928static void setup_ht_cap(struct ath_softc *sc,
929 struct ieee80211_sta_ht_cap *ht_info)
f078f209 930{
140add21 931 u8 tx_streams, rx_streams;
f078f209 932
d9fe60de
JB		 933 ht_info->ht_supported = true;
934 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
935 IEEE80211_HT_CAP_SM_PS |
936 IEEE80211_HT_CAP_SGI_40 |
937 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 938
9e98ac65
S		 939 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
940 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 941
d9fe60de
JB		 942 /* set up supported mcs set */
943 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
140add21
SB		 944 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
945 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
946
947 if (tx_streams != rx_streams) {
4d6b228d 948 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
140add21
SB		 949 tx_streams, rx_streams);
950 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
951 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
952 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
953 }
eb2599ca 954
140add21
SB		 955 ht_info->mcs.rx_mask[0] = 0xff;
956 if (rx_streams >= 2)
eb2599ca 957 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 958
140add21 959 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 960}
961
8feceb67 962static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 963 struct ieee80211_vif *vif,
8feceb67 964 struct ieee80211_bss_conf *bss_conf)
f078f209 965{
f078f209 966
8feceb67 967 if (bss_conf->assoc) {
4d6b228d 968 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 969 bss_conf->aid, sc->curbssid);
f078f209 970
8feceb67 971 /* New association, store aid */
2664f201
SB		 972 sc->curaid = bss_conf->aid;
973 ath9k_hw_write_associd(sc);
974
975 /*
976 * Request a re-configuration of Beacon related timers
977 * on the receipt of the first Beacon frame (i.e.,
978 * after time sync with the AP).
979 */
980 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 981
8feceb67 982 /* Configure the beacon */
2c3db3d5 983 ath_beacon_config(sc, vif);
f078f209 984
8feceb67 985 /* Reset rssi stats */
22e66a4c 986 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 987
415f738e 988 ath_start_ani(sc);
8feceb67 989 } else {
4d6b228d 990 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 991 sc->curaid = 0;
f38faa31
SB		 992 /* Stop ANI */
993 del_timer_sync(&sc->ani.timer);
f078f209 994 }
8feceb67 995}
f078f209 996
8feceb67
VT		 997/********************************/
998/* LED functions */
999/********************************/
f078f209 1000
f2bffa7e
VT		 1001static void ath_led_blink_work(struct work_struct *work)
1002{
1003 struct ath_softc *sc = container_of(work, struct ath_softc,
1004 ath_led_blink_work.work);
1005
1006 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1007 return;
85067c06
VT		 1008
1009 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1010 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
08fc5c1b 1011 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
85067c06 1012 else
08fc5c1b 1013 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
85067c06 1014 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e 1015
42935eca
LR		 1016 ieee80211_queue_delayed_work(sc->hw,
1017 &sc->ath_led_blink_work,
1018 (sc->sc_flags & SC_OP_LED_ON) ?
1019 msecs_to_jiffies(sc->led_off_duration) :
1020 msecs_to_jiffies(sc->led_on_duration));
f2bffa7e 1021
85067c06
VT		 1022 sc->led_on_duration = sc->led_on_cnt ?
1023 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1024 ATH_LED_ON_DURATION_IDLE;
1025 sc->led_off_duration = sc->led_off_cnt ?
1026 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1027 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 1028 sc->led_on_cnt = sc->led_off_cnt = 0;
1029 if (sc->sc_flags & SC_OP_LED_ON)
1030 sc->sc_flags &= ~SC_OP_LED_ON;
1031 else
1032 sc->sc_flags |= SC_OP_LED_ON;
1033}
1034
8feceb67
VT		 1035static void ath_led_brightness(struct led_classdev *led_cdev,
1036 enum led_brightness brightness)
1037{
1038 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1039 struct ath_softc *sc = led->sc;
f078f209 1040
8feceb67
VT		 1041 switch (brightness) {
1042 case LED_OFF:
1043 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e 1044 led->led_type == ATH_LED_RADIO) {
08fc5c1b 1045 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
f2bffa7e 1046 (led->led_type == ATH_LED_RADIO));
8feceb67 1047 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1048 if (led->led_type == ATH_LED_RADIO)
1049 sc->sc_flags &= ~SC_OP_LED_ON;
1050 } else {
1051 sc->led_off_cnt++;
1052 }
8feceb67
VT		 1053 break;
1054 case LED_FULL:
f2bffa7e 1055 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1056 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
42935eca
LR		 1057 ieee80211_queue_delayed_work(sc->hw,
1058 &sc->ath_led_blink_work, 0);
f2bffa7e 1059 } else if (led->led_type == ATH_LED_RADIO) {
08fc5c1b 1060 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
f2bffa7e
VT		 1061 sc->sc_flags |= SC_OP_LED_ON;
1062 } else {
1063 sc->led_on_cnt++;
1064 }
8feceb67
VT		 1065 break;
1066 default:
1067 break;
f078f209 1068 }
8feceb67 1069}
f078f209 1070
8feceb67
VT		 1071static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1072 char *trigger)
1073{
1074 int ret;
f078f209 1075
8feceb67
VT		 1076 led->sc = sc;
1077 led->led_cdev.name = led->name;
1078 led->led_cdev.default_trigger = trigger;
1079 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1080
8feceb67
VT		 1081 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1082 if (ret)
4d6b228d 1083 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
8feceb67
VT		 1084 "Failed to register led:%s", led->name);
1085 else
1086 led->registered = 1;
1087 return ret;
1088}
f078f209 1089
8feceb67
VT		 1090static void ath_unregister_led(struct ath_led *led)
1091{
1092 if (led->registered) {
1093 led_classdev_unregister(&led->led_cdev);
1094 led->registered = 0;
f078f209 1095 }
f078f209
LR		 1096}
1097
8feceb67 1098static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1099{
8feceb67
VT		 1100 ath_unregister_led(&sc->assoc_led);
1101 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1102 ath_unregister_led(&sc->tx_led);
1103 ath_unregister_led(&sc->rx_led);
1104 ath_unregister_led(&sc->radio_led);
08fc5c1b 1105 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
8feceb67 1106}
f078f209 1107
8feceb67
VT		 1108static void ath_init_leds(struct ath_softc *sc)
1109{
1110 char *trigger;
1111 int ret;
f078f209 1112
08fc5c1b
VN		 1113 if (AR_SREV_9287(sc->sc_ah))
1114 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1115 else
1116 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1117
8feceb67 1118 /* Configure gpio 1 for output */
08fc5c1b 1119 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
8feceb67
VT		 1120 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1121 /* LED off, active low */
08fc5c1b 1122 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
7dcfdcd9 1123
f2bffa7e
VT		 1124 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1125
8feceb67
VT		 1126 trigger = ieee80211_get_radio_led_name(sc->hw);
1127 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1128 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1129 ret = ath_register_led(sc, &sc->radio_led, trigger);
1130 sc->radio_led.led_type = ATH_LED_RADIO;
1131 if (ret)
1132 goto fail;
7dcfdcd9 1133
8feceb67
VT		 1134 trigger = ieee80211_get_assoc_led_name(sc->hw);
1135 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1136 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1137 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1138 sc->assoc_led.led_type = ATH_LED_ASSOC;
1139 if (ret)
1140 goto fail;
f078f209 1141
8feceb67
VT		 1142 trigger = ieee80211_get_tx_led_name(sc->hw);
1143 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1144 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1145 ret = ath_register_led(sc, &sc->tx_led, trigger);
1146 sc->tx_led.led_type = ATH_LED_TX;
1147 if (ret)
1148 goto fail;
f078f209 1149
8feceb67
VT		 1150 trigger = ieee80211_get_rx_led_name(sc->hw);
1151 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1152 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1153 ret = ath_register_led(sc, &sc->rx_led, trigger);
1154 sc->rx_led.led_type = ATH_LED_RX;
1155 if (ret)
1156 goto fail;
f078f209 1157
8feceb67
VT		 1158 return;
1159
1160fail:
35c95ab9 1161 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67 1162 ath_deinit_leds(sc);
f078f209
LR		 1163}
1164
7ec3e514 1165void ath_radio_enable(struct ath_softc *sc)
500c064d 1166{
cbe61d8a 1167 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1168 struct ieee80211_channel *channel = sc->hw->conf.channel;
1169 int r;
500c064d 1170
3cbb5dd7 1171 ath9k_ps_wakeup(sc);
93b1b37f 1172 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 1173
159cd468
VT		 1174 if (!ah->curchan)
1175 ah->curchan = ath_get_curchannel(sc, sc->hw);
1176
d2f5b3a6 1177 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1178 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1179 if (r) {
4d6b228d 1180 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
ae8d2858 1181 "Unable to reset channel %u (%uMhz) ",
6b45784f 1182 "reset status %d\n",
ae8d2858 1183 channel->center_freq, r);
500c064d
VT		 1184 }
1185 spin_unlock_bh(&sc->sc_resetlock);
1186
1187 ath_update_txpow(sc);
1188 if (ath_startrecv(sc) != 0) {
4d6b228d 1189 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
04bd4638 1190 "Unable to restart recv logic\n");
500c064d
VT		 1191 return;
1192 }
1193
1194 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1195 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1196
1197 /* Re-Enable interrupts */
17d7904d 1198 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1199
1200 /* Enable LED */
08fc5c1b 1201 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 1202 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 1203 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d
VT		 1204
1205 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1206 ath9k_ps_restore(sc);
500c064d
VT		 1207}
1208
7ec3e514 1209void ath_radio_disable(struct ath_softc *sc)
500c064d 1210{
cbe61d8a 1211 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1212 struct ieee80211_channel *channel = sc->hw->conf.channel;
1213 int r;
500c064d 1214
3cbb5dd7 1215 ath9k_ps_wakeup(sc);
500c064d
VT		 1216 ieee80211_stop_queues(sc->hw);
1217
1218 /* Disable LED */
08fc5c1b
VN		 1219 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1220 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT		 1221
1222 /* Disable interrupts */
1223 ath9k_hw_set_interrupts(ah, 0);
1224
043a0405 1225 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1226 ath_stoprecv(sc); /* turn off frame recv */
1227 ath_flushrecv(sc); /* flush recv queue */
1228
159cd468
VT		 1229 if (!ah->curchan)
1230 ah->curchan = ath_get_curchannel(sc, sc->hw);
1231
500c064d 1232 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1233 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1234 if (r) {
4d6b228d 1235 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
04bd4638 1236 "Unable to reset channel %u (%uMhz) "
6b45784f 1237 "reset status %d\n",
ae8d2858 1238 channel->center_freq, r);
500c064d
VT		 1239 }
1240 spin_unlock_bh(&sc->sc_resetlock);
1241
1242 ath9k_hw_phy_disable(ah);
93b1b37f 1243 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 1244 ath9k_ps_restore(sc);
38ab422e 1245 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1246}
1247
5077fd35
GJ		 1248/*******************/
1249/* Rfkill */
1250/*******************/
1251
500c064d
VT		 1252static bool ath_is_rfkill_set(struct ath_softc *sc)
1253{
cbe61d8a 1254 struct ath_hw *ah = sc->sc_ah;
500c064d 1255
2660b81a
S		 1256 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1257 ah->rfkill_polarity;
500c064d
VT		 1258}
1259
3b319aae 1260static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1261{
3b319aae
JB		 1262 struct ath_wiphy *aphy = hw->priv;
1263 struct ath_softc *sc = aphy->sc;
19d337df 1264 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1265
3b319aae 1266 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
500c064d
VT		 1267}
1268
3b319aae 1269static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1270{
3b319aae 1271 struct ath_hw *ah = sc->sc_ah;
9c84b797 1272
3b319aae
JB		 1273 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1274 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1275}
500c064d 1276
6baff7f9 1277void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1278{
1279 ath_detach(sc);
1280 free_irq(sc->irq, sc);
1281 ath_bus_cleanup(sc);
c52f33d0 1282 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1283 ieee80211_free_hw(sc->hw);
1284}
1285
6baff7f9 1286void ath_detach(struct ath_softc *sc)
f078f209 1287{
8feceb67 1288 struct ieee80211_hw *hw = sc->hw;
4d6b228d 1289 struct ath_hw *ah = sc->sc_ah;
9c84b797 1290 int i = 0;
f078f209 1291
3cbb5dd7
VN		 1292 ath9k_ps_wakeup(sc);
1293
4d6b228d 1294 dev_dbg(sc->dev, "Detach ATH hw\n");
f078f209 1295
35c95ab9 1296 ath_deinit_leds(sc);
e31f7b96 1297 wiphy_rfkill_stop_polling(sc->hw->wiphy);
35c95ab9 1298
c52f33d0
JM		 1299 for (i = 0; i < sc->num_sec_wiphy; i++) {
1300 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1301 if (aphy == NULL)
1302 continue;
1303 sc->sec_wiphy[i] = NULL;
1304 ieee80211_unregister_hw(aphy->hw);
1305 ieee80211_free_hw(aphy->hw);
1306 }
3fcdfb4b 1307 ieee80211_unregister_hw(hw);
8feceb67
VT		 1308 ath_rx_cleanup(sc);
1309 ath_tx_cleanup(sc);
f078f209 1310
9c84b797
S		 1311 tasklet_kill(&sc->intr_tq);
1312 tasklet_kill(&sc->bcon_tasklet);
f078f209 1313
9c84b797 1314 if (!(sc->sc_flags & SC_OP_INVALID))
4d6b228d 1315 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
8feceb67 1316
9c84b797
S		 1317 /* cleanup tx queues */
1318 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1319 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1320 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797 1321
75d7839f 1322 if ((sc->btcoex.no_stomp_timer) &&
766ec4a9 1323 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1324 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1773912b 1325
4d6b228d 1326 ath9k_hw_detach(ah);
af03abec 1327 ath9k_exit_debug(ah);
3ce1b1a9 1328 sc->sc_ah = NULL;
f078f209
LR		 1329}
1330
e3bb249b
BC		 1331static int ath9k_reg_notifier(struct wiphy *wiphy,
1332 struct regulatory_request *request)
1333{
1334 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1335 struct ath_wiphy *aphy = hw->priv;
1336 struct ath_softc *sc = aphy->sc;
608b88cb 1337 struct ath_regulatory *reg = &sc->common.regulatory;
e3bb249b
BC		 1338
1339 return ath_reg_notifier_apply(wiphy, request, reg);
1340}
1341
75d7839f
LR		 1342/*
1343 * Detects if there is any priority bt traffic
1344 */
1345static void ath_detect_bt_priority(struct ath_softc *sc)
1346{
1347 struct ath_btcoex *btcoex = &sc->btcoex;
1348 struct ath_hw *ah = sc->sc_ah;
1349
766ec4a9 1350 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
75d7839f
LR		 1351 btcoex->bt_priority_cnt++;
1352
1353 if (time_after(jiffies, btcoex->bt_priority_time +
1354 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1355 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1356 DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX,
1357 "BT priority traffic detected");
1358 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1359 } else {
1360 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1361 }
1362
1363 btcoex->bt_priority_cnt = 0;
1364 btcoex->bt_priority_time = jiffies;
1365 }
1366}
1367
75d7839f
LR		 1368/*
1369 * Configures appropriate weight based on stomp type.
1370 */
269ad812
LR		 1371static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1372 enum ath_stomp_type stomp_type)
75d7839f 1373{
269ad812 1374 struct ath_hw *ah = sc->sc_ah;
75d7839f
LR		 1375
1376 switch (stomp_type) {
1377 case ATH_BTCOEX_STOMP_ALL:
269ad812
LR		 1378 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1379 AR_STOMP_ALL_WLAN_WGHT);
75d7839f
LR		 1380 break;
1381 case ATH_BTCOEX_STOMP_LOW:
269ad812
LR		 1382 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1383 AR_STOMP_LOW_WLAN_WGHT);
75d7839f
LR		 1384 break;
1385 case ATH_BTCOEX_STOMP_NONE:
269ad812
LR		 1386 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1387 AR_STOMP_NONE_WLAN_WGHT);
75d7839f
LR		 1388 break;
1389 default:
269ad812 1390 DPRINTF(ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
75d7839f
LR		 1391 break;
1392 }
1393
269ad812 1394 ath9k_hw_btcoex_enable(ah);
75d7839f
LR		 1395}
1396
1397/*
1398 * This is the master bt coex timer which runs for every
1399 * 45ms, bt traffic will be given priority during 55% of this
1400 * period while wlan gets remaining 45%
1401 */
1402static void ath_btcoex_period_timer(unsigned long data)
1403{
1404 struct ath_softc *sc = (struct ath_softc *) data;
1405 struct ath_hw *ah = sc->sc_ah;
1406 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f
LR		 1407
1408 ath_detect_bt_priority(sc);
1409
1410 spin_lock_bh(&btcoex->btcoex_lock);
1411
269ad812 1412 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
75d7839f
LR		 1413
1414 spin_unlock_bh(&btcoex->btcoex_lock);
1415
1416 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1417 if (btcoex->hw_timer_enabled)
1418 ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
1419
1420 ath_gen_timer_start(ah,
1421 btcoex->no_stomp_timer,
1422 (ath9k_hw_gettsf32(ah) +
1423 btcoex->btcoex_no_stomp),
1424 btcoex->btcoex_no_stomp * 10);
1425 btcoex->hw_timer_enabled = true;
1426 }
1427
1428 mod_timer(&btcoex->period_timer, jiffies +
1429 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1430}
1431
1432/*
1433 * Generic tsf based hw timer which configures weight
1434 * registers to time slice between wlan and bt traffic
1435 */
1436static void ath_btcoex_no_stomp_timer(void *arg)
1437{
1438 struct ath_softc *sc = (struct ath_softc *)arg;
1439 struct ath_hw *ah = sc->sc_ah;
1440 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f
LR		 1441
1442 DPRINTF(ah, ATH_DBG_BTCOEX, "no stomp timer running \n");
1443
1444 spin_lock_bh(&btcoex->btcoex_lock);
1445
e08a6ace 1446 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
269ad812 1447 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
e08a6ace 1448 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
269ad812 1449 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
75d7839f
LR		 1450
1451 spin_unlock_bh(&btcoex->btcoex_lock);
1452}
1453
1454static int ath_init_btcoex_timer(struct ath_softc *sc)
1455{
1456 struct ath_btcoex *btcoex = &sc->btcoex;
1457
1458 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1459 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1460 btcoex->btcoex_period / 100;
1461
1462 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1463 (unsigned long) sc);
1464
1465 spin_lock_init(&btcoex->btcoex_lock);
1466
1467 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1468 ath_btcoex_no_stomp_timer,
1469 ath_btcoex_no_stomp_timer,
1470 (void *) sc, AR_FIRST_NDP_TIMER);
1471
1472 if (!btcoex->no_stomp_timer)
1473 return -ENOMEM;
1474
1475 return 0;
1476}
1477
1e40bcfa
LR		 1478/*
1479 * Initialize and fill ath_softc, ath_sofct is the
1480 * "Software Carrier" struct. Historically it has existed
1481 * to allow the separation between hardware specific
1482 * variables (now in ath_hw) and driver specific variables.
1483 */
aeac355d 1484static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
ff37e337 1485{
cbe61d8a 1486 struct ath_hw *ah = NULL;
4f3acf81 1487 int r = 0, i;
ff37e337 1488 int csz = 0;
75d7839f 1489 int qnum;
ff37e337
S		 1490
1491 /* XXX: hardware will not be ready until ath_open() being called */
1492 sc->sc_flags |= SC_OP_INVALID;
88b126af 1493
c52f33d0 1494 spin_lock_init(&sc->wiphy_lock);
ff37e337 1495 spin_lock_init(&sc->sc_resetlock);
6158425b 1496 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1497 spin_lock_init(&sc->ani_lock);
04717ccd 1498 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1499 mutex_init(&sc->mutex);
ff37e337 1500 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1501 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1502 (unsigned long)sc);
1503
1504 /*
1505 * Cache line size is used to size and align various
1506 * structures used to communicate with the hardware.
1507 */
88d15707 1508 ath_read_cachesize(sc, &csz);
ff37e337 1509 /* XXX assert csz is non-zero */
d15dd3e5 1510 sc->common.cachelsz = csz << 2; /* convert to bytes */
ff37e337 1511
4f3acf81
LR		 1512 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1513 if (!ah) {
4f3acf81
LR		 1514 r = -ENOMEM;
1515 goto bad_no_ah;
1516 }
1517
1518 ah->ah_sc = sc;
8df5d1b7 1519 ah->hw_version.devid = devid;
aeac355d 1520 ah->hw_version.subsysid = subsysid;
e1e2f93f 1521 sc->sc_ah = ah;
4f3acf81 1522
4d6b228d
LR		 1523 if (ath9k_init_debug(ah) < 0)
1524 dev_err(sc->dev, "Unable to create debugfs files\n");
1525
f637cfd6 1526 r = ath9k_hw_init(ah);
4f3acf81 1527 if (r) {
4d6b228d 1528 DPRINTF(ah, ATH_DBG_FATAL,
f637cfd6 1529 "Unable to initialize hardware; "
4f3acf81 1530 "initialization status: %d\n", r);
ff37e337
S		 1531 goto bad;
1532 }
ff37e337
S		 1533
1534 /* Get the hardware key cache size. */
2660b81a 1535 sc->keymax = ah->caps.keycache_size;
17d7904d 1536 if (sc->keymax > ATH_KEYMAX) {
4d6b228d 1537 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 1538 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1539 ATH_KEYMAX, sc->keymax);
1540 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1541 }
1542
1543 /*
1544 * Reset the key cache since some parts do not
1545 * reset the contents on initial power up.
1546 */
17d7904d 1547 for (i = 0; i < sc->keymax; i++)
ff37e337 1548 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1549
ff37e337 1550 /* default to MONITOR mode */
2660b81a 1551 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1552
ff37e337
S		 1553 /* Setup rate tables */
1554
1555 ath_rate_attach(sc);
1556 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1557 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1558
1559 /*
1560 * Allocate hardware transmit queues: one queue for
1561 * beacon frames and one data queue for each QoS
1562 * priority. Note that the hal handles reseting
1563 * these queues at the needed time.
1564 */
b77f483f
S		 1565 sc->beacon.beaconq = ath_beaconq_setup(ah);
1566 if (sc->beacon.beaconq == -1) {
4d6b228d 1567 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1568 "Unable to setup a beacon xmit queue\n");
4f3acf81 1569 r = -EIO;
ff37e337
S		 1570 goto bad2;
1571 }
b77f483f
S		 1572 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1573 if (sc->beacon.cabq == NULL) {
4d6b228d 1574 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1575 "Unable to setup CAB xmit queue\n");
4f3acf81 1576 r = -EIO;
ff37e337
S		 1577 goto bad2;
1578 }
1579
17d7904d 1580 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1581 ath_cabq_update(sc);
1582
b77f483f
S		 1583 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1584 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1585
1586 /* Setup data queues */
1587 /* NB: ensure BK queue is the lowest priority h/w queue */
1588 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
4d6b228d 1589 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1590 "Unable to setup xmit queue for BK traffic\n");
4f3acf81 1591 r = -EIO;
ff37e337
S		 1592 goto bad2;
1593 }
1594
1595 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
4d6b228d 1596 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1597 "Unable to setup xmit queue for BE traffic\n");
4f3acf81 1598 r = -EIO;
ff37e337
S		 1599 goto bad2;
1600 }
1601 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
4d6b228d 1602 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1603 "Unable to setup xmit queue for VI traffic\n");
4f3acf81 1604 r = -EIO;
ff37e337
S		 1605 goto bad2;
1606 }
1607 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
4d6b228d 1608 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1609 "Unable to setup xmit queue for VO traffic\n");
4f3acf81 1610 r = -EIO;
ff37e337
S		 1611 goto bad2;
1612 }
1613
1614 /* Initializes the noise floor to a reasonable default value.
1615 * Later on this will be updated during ANI processing. */
1616
17d7904d
S		 1617 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1618 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1619
1620 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1621 ATH9K_CIPHER_TKIP, NULL)) {
1622 /*
1623 * Whether we should enable h/w TKIP MIC.
1624 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1625 * report WMM capable, so it's always safe to turn on
1626 * TKIP MIC in this case.
1627 */
1628 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1629 0, 1, NULL);
1630 }
1631
1632 /*
1633 * Check whether the separate key cache entries
1634 * are required to handle both tx+rx MIC keys.
1635 * With split mic keys the number of stations is limited
1636 * to 27 otherwise 59.
1637 */
1638 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1639 ATH9K_CIPHER_TKIP, NULL)
1640 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1641 ATH9K_CIPHER_MIC, NULL)
1642 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1643 0, NULL))
17d7904d 1644 sc->splitmic = 1;
ff37e337
S		 1645
1646 /* turn on mcast key search if possible */
1647 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1648 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1649 1, NULL);
1650
17d7904d 1651 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1652
1653 /* 11n Capabilities */
2660b81a 1654 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1655 sc->sc_flags |= SC_OP_TXAGGR;
1656 sc->sc_flags |= SC_OP_RXAGGR;
1657 }
1658
2660b81a
S		 1659 sc->tx_chainmask = ah->caps.tx_chainmask;
1660 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1661
1662 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1663 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1664
8ca21f01 1665 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1666 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1667
b77f483f 1668 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1669
1670 /* initialize beacon slots */
c52f33d0 1671 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1672 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1673 sc->beacon.bslot_aphy[i] = NULL;
1674 }
ff37e337 1675
ff37e337
S		 1676 /* setup channels and rates */
1677
5f8e077c 1678 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1679 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1680 sc->rates[IEEE80211_BAND_2GHZ];
1681 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1682 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1683 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1684
2660b81a 1685 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1686 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1687 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1688 sc->rates[IEEE80211_BAND_5GHZ];
1689 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1690 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1691 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1692 }
1693
766ec4a9 1694 switch (ah->btcoex_hw.scheme) {
75d7839f
LR		 1695 case ATH_BTCOEX_CFG_NONE:
1696 break;
1697 case ATH_BTCOEX_CFG_2WIRE:
1698 ath9k_hw_btcoex_init_2wire(ah);
1699 break;
1700 case ATH_BTCOEX_CFG_3WIRE:
1701 ath9k_hw_btcoex_init_3wire(ah);
1702 r = ath_init_btcoex_timer(sc);
1773912b
VT		 1703 if (r)
1704 goto bad2;
75d7839f 1705 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
766ec4a9 1706 ath9k_hw_init_btcoex_hw(ah, qnum);
e08a6ace 1707 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
75d7839f
LR		 1708 break;
1709 default:
1710 WARN_ON(1);
1711 break;
1773912b 1712 }
c97c92d9 1713
ff37e337
S		 1714 return 0;
1715bad2:
1716 /* cleanup tx queues */
1717 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1718 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1719 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337 1720bad:
95fafca2 1721 ath9k_hw_detach(ah);
4f3acf81 1722bad_no_ah:
4d6b228d
LR		 1723 ath9k_exit_debug(sc->sc_ah);
1724 sc->sc_ah = NULL;
ff37e337 1725
4f3acf81 1726 return r;
ff37e337
S		 1727}
1728
c52f33d0 1729void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1730{
9c84b797
S		 1731 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1732 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1733 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1734 IEEE80211_HW_AMPDU_AGGREGATION |
1735 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1736 IEEE80211_HW_PS_NULLFUNC_STACK |
1737 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1738
b3bd89ce 1739 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1740 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1741
9c84b797
S		 1742 hw->wiphy->interface_modes =
1743 BIT(NL80211_IFTYPE_AP) |
1744 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1745 BIT(NL80211_IFTYPE_ADHOC) |
1746 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1747
8feceb67 1748 hw->queues = 4;
e63835b0 1749 hw->max_rates = 4;
171387ef 1750 hw->channel_change_time = 5000;
465ca84d 1751 hw->max_listen_interval = 10;
dd190183
LR		 1752 /* Hardware supports 10 but we use 4 */
1753 hw->max_rate_tries = 4;
528f0c6b 1754 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1755 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1756
8feceb67 1757 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1758
c52f33d0
JM		 1759 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1760 &sc->sbands[IEEE80211_BAND_2GHZ];
1761 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1762 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1763 &sc->sbands[IEEE80211_BAND_5GHZ];
1764}
1765
1e40bcfa 1766/* Device driver core initialization */
aeac355d 1767int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
c52f33d0
JM		 1768{
1769 struct ieee80211_hw *hw = sc->hw;
4d6b228d 1770 struct ath_hw *ah;
c52f33d0 1771 int error = 0, i;
3a702e49 1772 struct ath_regulatory *reg;
c52f33d0 1773
4d6b228d 1774 dev_dbg(sc->dev, "Attach ATH hw\n");
c52f33d0 1775
aeac355d 1776 error = ath_init_softc(devid, sc, subsysid);
c52f33d0
JM		 1777 if (error != 0)
1778 return error;
1779
4d6b228d
LR		 1780 ah = sc->sc_ah;
1781
c52f33d0
JM		 1782 /* get mac address from hardware and set in mac80211 */
1783
4d6b228d 1784 SET_IEEE80211_PERM_ADDR(hw, ah->macaddr);
c52f33d0
JM		 1785
1786 ath_set_hw_capab(sc, hw);
1787
608b88cb 1788 error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy,
c26c2e57
LR		 1789 ath9k_reg_notifier);
1790 if (error)
1791 return error;
1792
608b88cb 1793 reg = &sc->common.regulatory;
c26c2e57 1794
4d6b228d 1795 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1796 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
4d6b228d 1797 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
eb2599ca 1798 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1799 }
1800
db93e7b5
SB		 1801 /* initialize tx/rx engine */
1802 error = ath_tx_init(sc, ATH_TXBUF);
1803 if (error != 0)
40b130a9 1804 goto error_attach;
8feceb67 1805
db93e7b5
SB		 1806 error = ath_rx_init(sc, ATH_RXBUF);
1807 if (error != 0)
40b130a9 1808 goto error_attach;
8feceb67 1809
0e2dedf9 1810 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1811 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1812 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1813
db93e7b5 1814 error = ieee80211_register_hw(hw);
8feceb67 1815
3a702e49 1816 if (!ath_is_world_regd(reg)) {
c02cf373 1817 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1818 if (error)
1819 goto error_attach;
1820 }
5f8e077c 1821
db93e7b5
SB		 1822 /* Initialize LED control */
1823 ath_init_leds(sc);
8feceb67 1824
3b319aae 1825 ath_start_rfkill_poll(sc);
5f8e077c 1826
8feceb67 1827 return 0;
40b130a9
VT		 1828
1829error_attach:
1830 /* cleanup tx queues */
1831 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1832 if (ATH_TXQ_SETUP(sc, i))
1833 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1834
4d6b228d
LR		 1835 ath9k_hw_detach(ah);
1836 ath9k_exit_debug(ah);
3ce1b1a9 1837 sc->sc_ah = NULL;
40b130a9 1838
8feceb67 1839 return error;
f078f209
LR		 1840}
1841
ff37e337
S		 1842int ath_reset(struct ath_softc *sc, bool retry_tx)
1843{
cbe61d8a 1844 struct ath_hw *ah = sc->sc_ah;
030bb495 1845 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1846 int r;
ff37e337
S		 1847
1848 ath9k_hw_set_interrupts(ah, 0);
043a0405 1849 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1850 ath_stoprecv(sc);
1851 ath_flushrecv(sc);
1852
1853 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1854 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1855 if (r)
4d6b228d 1856 DPRINTF(ah, ATH_DBG_FATAL,
6b45784f 1857 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1858 spin_unlock_bh(&sc->sc_resetlock);
1859
1860 if (ath_startrecv(sc) != 0)
4d6b228d 1861 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1862
1863 /*
1864 * We may be doing a reset in response to a request
1865 * that changes the channel so update any state that
1866 * might change as a result.
1867 */
ce111bad 1868 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1869
1870 ath_update_txpow(sc);
1871
1872 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1873 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1874
17d7904d 1875 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1876
1877 if (retry_tx) {
1878 int i;
1879 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1880 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1881 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1882 ath_txq_schedule(sc, &sc->tx.txq[i]);
1883 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1884 }
1885 }
1886 }
1887
ae8d2858 1888 return r;
ff37e337
S		 1889}
1890
1891/*
1892 * This function will allocate both the DMA descriptor structure, and the
1893 * buffers it contains. These are used to contain the descriptors used
1894 * by the system.
1895*/
1896int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1897 struct list_head *head, const char *name,
1898 int nbuf, int ndesc)
1899{
1900#define DS2PHYS(_dd, _ds) \
1901 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1902#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1903#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1904
1905 struct ath_desc *ds;
1906 struct ath_buf *bf;
1907 int i, bsize, error;
1908
4d6b228d 1909 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
04bd4638 1910 name, nbuf, ndesc);
ff37e337 1911
b03a9db9 1912 INIT_LIST_HEAD(head);
ff37e337
S		 1913 /* ath_desc must be a multiple of DWORDs */
1914 if ((sizeof(struct ath_desc) % 4) != 0) {
4d6b228d 1915 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1916 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1917 error = -ENOMEM;
1918 goto fail;
1919 }
1920
ff37e337
S		 1921 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1922
1923 /*
1924 * Need additional DMA memory because we can't use
1925 * descriptors that cross the 4K page boundary. Assume
1926 * one skipped descriptor per 4K page.
1927 */
2660b81a 1928 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1929 u32 ndesc_skipped =
1930 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1931 u32 dma_len;
1932
1933 while (ndesc_skipped) {
1934 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1935 dd->dd_desc_len += dma_len;
1936
1937 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1938 };
1939 }
1940
1941 /* allocate descriptors */
7da3c55c 1942 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1943 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1944 if (dd->dd_desc == NULL) {
1945 error = -ENOMEM;
1946 goto fail;
1947 }
1948 ds = dd->dd_desc;
4d6b228d 1949 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1950 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1951 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1952
1953 /* allocate buffers */
1954 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1955 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1956 if (bf == NULL) {
1957 error = -ENOMEM;
1958 goto fail2;
1959 }
ff37e337
S		 1960 dd->dd_bufptr = bf;
1961
ff37e337
S		 1962 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1963 bf->bf_desc = ds;
1964 bf->bf_daddr = DS2PHYS(dd, ds);
1965
2660b81a 1966 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1967 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1968 /*
1969 * Skip descriptor addresses which can cause 4KB
1970 * boundary crossing (addr + length) with a 32 dword
1971 * descriptor fetch.
1972 */
1973 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1974 ASSERT((caddr_t) bf->bf_desc <
1975 ((caddr_t) dd->dd_desc +
1976 dd->dd_desc_len));
1977
1978 ds += ndesc;
1979 bf->bf_desc = ds;
1980 bf->bf_daddr = DS2PHYS(dd, ds);
1981 }
1982 }
1983 list_add_tail(&bf->list, head);
1984 }
1985 return 0;
1986fail2:
7da3c55c
GJ		 1987 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1988 dd->dd_desc_paddr);
ff37e337
S		 1989fail:
1990 memset(dd, 0, sizeof(*dd));
1991 return error;
1992#undef ATH_DESC_4KB_BOUND_CHECK
1993#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1994#undef DS2PHYS
1995}
1996
1997void ath_descdma_cleanup(struct ath_softc *sc,
1998 struct ath_descdma *dd,
1999 struct list_head *head)
2000{
7da3c55c
GJ		 2001 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2002 dd->dd_desc_paddr);
ff37e337
S		 2003
2004 INIT_LIST_HEAD(head);
2005 kfree(dd->dd_bufptr);
2006 memset(dd, 0, sizeof(*dd));
2007}
2008
2009int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2010{
2011 int qnum;
2012
2013 switch (queue) {
2014 case 0:
b77f483f 2015 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 2016 break;
2017 case 1:
b77f483f 2018 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 2019 break;
2020 case 2:
b77f483f 2021 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2022 break;
2023 case 3:
b77f483f 2024 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 2025 break;
2026 default:
b77f483f 2027 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2028 break;
2029 }
2030
2031 return qnum;
2032}
2033
2034int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2035{
2036 int qnum;
2037
2038 switch (queue) {
2039 case ATH9K_WME_AC_VO:
2040 qnum = 0;
2041 break;
2042 case ATH9K_WME_AC_VI:
2043 qnum = 1;
2044 break;
2045 case ATH9K_WME_AC_BE:
2046 qnum = 2;
2047 break;
2048 case ATH9K_WME_AC_BK:
2049 qnum = 3;
2050 break;
2051 default:
2052 qnum = -1;
2053 break;
2054 }
2055
2056 return qnum;
2057}
2058
5f8e077c
LR		 2059/* XXX: Remove me once we don't depend on ath9k_channel for all
2060 * this redundant data */
0e2dedf9
JM		 2061void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2062 struct ath9k_channel *ichan)
5f8e077c 2063{
5f8e077c
LR		 2064 struct ieee80211_channel *chan = hw->conf.channel;
2065 struct ieee80211_conf *conf = &hw->conf;
2066
2067 ichan->channel = chan->center_freq;
2068 ichan->chan = chan;
2069
2070 if (chan->band == IEEE80211_BAND_2GHZ) {
2071 ichan->chanmode = CHANNEL_G;
8813262e 2072 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR		 2073 } else {
2074 ichan->chanmode = CHANNEL_A;
2075 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2076 }
2077
2078 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2079
2080 if (conf_is_ht(conf)) {
2081 if (conf_is_ht40(conf))
2082 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2083
2084 ichan->chanmode = ath_get_extchanmode(sc, chan,
2085 conf->channel_type);
2086 }
2087}
2088
ff37e337
S		 2089/**********************/
2090/* mac80211 callbacks */
2091/**********************/
2092
75d7839f
LR		 2093/*
2094 * (Re)start btcoex timers
2095 */
2096static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2097{
2098 struct ath_btcoex *btcoex = &sc->btcoex;
2099 struct ath_hw *ah = sc->sc_ah;
2100
2101 DPRINTF(ah, ATH_DBG_BTCOEX, "Starting btcoex timers");
2102
2103 /* make sure duty cycle timer is also stopped when resuming */
2104 if (btcoex->hw_timer_enabled)
2105 ath_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2106
2107 btcoex->bt_priority_cnt = 0;
2108 btcoex->bt_priority_time = jiffies;
2109 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2110
2111 mod_timer(&btcoex->period_timer, jiffies);
2112}
2113
8feceb67 2114static int ath9k_start(struct ieee80211_hw *hw)
f078f209 2115{
bce048d7
JM		 2116 struct ath_wiphy *aphy = hw->priv;
2117 struct ath_softc *sc = aphy->sc;
af03abec 2118 struct ath_hw *ah = sc->sc_ah;
8feceb67 2119 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 2120 struct ath9k_channel *init_channel;
82880a7c 2121 int r;
f078f209 2122
af03abec 2123 DPRINTF(ah, ATH_DBG_CONFIG, "Starting driver with "
04bd4638 2124 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 2125
141b38b6
S		 2126 mutex_lock(&sc->mutex);
2127
9580a222
JM		 2128 if (ath9k_wiphy_started(sc)) {
2129 if (sc->chan_idx == curchan->hw_value) {
2130 /*
2131 * Already on the operational channel, the new wiphy
2132 * can be marked active.
2133 */
2134 aphy->state = ATH_WIPHY_ACTIVE;
2135 ieee80211_wake_queues(hw);
2136 } else {
2137 /*
2138 * Another wiphy is on another channel, start the new
2139 * wiphy in paused state.
2140 */
2141 aphy->state = ATH_WIPHY_PAUSED;
2142 ieee80211_stop_queues(hw);
2143 }
2144 mutex_unlock(&sc->mutex);
2145 return 0;
2146 }
2147 aphy->state = ATH_WIPHY_ACTIVE;
2148
8feceb67 2149 /* setup initial channel */
f078f209 2150
82880a7c 2151 sc->chan_idx = curchan->hw_value;
f078f209 2152
82880a7c 2153 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 2154
2155 /* Reset SERDES registers */
af03abec 2156 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S		 2157
2158 /*
2159 * The basic interface to setting the hardware in a good
2160 * state is ``reset''. On return the hardware is known to
2161 * be powered up and with interrupts disabled. This must
2162 * be followed by initialization of the appropriate bits
2163 * and then setup of the interrupt mask.
2164 */
2165 spin_lock_bh(&sc->sc_resetlock);
af03abec 2166 r = ath9k_hw_reset(ah, init_channel, false);
ae8d2858 2167 if (r) {
af03abec 2168 DPRINTF(ah, ATH_DBG_FATAL,
6b45784f 2169 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 2170 "(freq %u MHz)\n", r,
2171 curchan->center_freq);
ff37e337 2172 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2173 goto mutex_unlock;
ff37e337
S		 2174 }
2175 spin_unlock_bh(&sc->sc_resetlock);
2176
2177 /*
2178 * This is needed only to setup initial state
2179 * but it's best done after a reset.
2180 */
2181 ath_update_txpow(sc);
8feceb67 2182
ff37e337
S		 2183 /*
2184 * Setup the hardware after reset:
2185 * The receive engine is set going.
2186 * Frame transmit is handled entirely
2187 * in the frame output path; there's nothing to do
2188 * here except setup the interrupt mask.
2189 */
2190 if (ath_startrecv(sc) != 0) {
af03abec 2191 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 2192 r = -EIO;
2193 goto mutex_unlock;
f078f209 2194 }
8feceb67 2195
ff37e337 2196 /* Setup our intr mask. */
17d7904d 2197 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2198 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2199 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2200
af03abec 2201 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2202 sc->imask |= ATH9K_INT_GTT;
ff37e337 2203
af03abec 2204 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2205 sc->imask |= ATH9K_INT_CST;
ff37e337 2206
ce111bad 2207 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2208
2209 sc->sc_flags &= ~SC_OP_INVALID;
2210
2211 /* Disable BMISS interrupt when we're not associated */
17d7904d 2212 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
af03abec 2213 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337 2214
bce048d7 2215 ieee80211_wake_queues(hw);
ff37e337 2216
42935eca 2217 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 2218
766ec4a9
LR		 2219 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2220 !ah->btcoex_hw.enabled) {
5e197292
LR		 2221 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2222 AR_STOMP_LOW_WLAN_WGHT);
af03abec 2223 ath9k_hw_btcoex_enable(ah);
f985ad12 2224
7b6840ab 2225 ath_pcie_aspm_disable(sc);
766ec4a9 2226 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2227 ath9k_btcoex_timer_resume(sc);
1773912b
VT		 2228 }
2229
141b38b6
S		 2230mutex_unlock:
2231 mutex_unlock(&sc->mutex);
2232
ae8d2858 2233 return r;
f078f209
LR		 2234}
2235
8feceb67
VT		 2236static int ath9k_tx(struct ieee80211_hw *hw,
2237 struct sk_buff *skb)
f078f209 2238{
528f0c6b 2239 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2240 struct ath_wiphy *aphy = hw->priv;
2241 struct ath_softc *sc = aphy->sc;
528f0c6b 2242 struct ath_tx_control txctl;
8feceb67 2243 int hdrlen, padsize;
528f0c6b 2244
8089cc47 2245 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2246 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2247 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2248 goto exit;
2249 }
2250
96148326 2251 if (sc->ps_enabled) {
dc8c4585
JM		 2252 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2253 /*
2254 * mac80211 does not set PM field for normal data frames, so we
2255 * need to update that based on the current PS mode.
2256 */
2257 if (ieee80211_is_data(hdr->frame_control) &&
2258 !ieee80211_is_nullfunc(hdr->frame_control) &&
2259 !ieee80211_has_pm(hdr->frame_control)) {
4d6b228d 2260 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Add PM=1 for a TX frame "
dc8c4585
JM		 2261 "while in PS mode\n");
2262 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2263 }
2264 }
2265
9a23f9ca
JM		 2266 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2267 /*
2268 * We are using PS-Poll and mac80211 can request TX while in
2269 * power save mode. Need to wake up hardware for the TX to be
2270 * completed and if needed, also for RX of buffered frames.
2271 */
2272 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2273 ath9k_ps_wakeup(sc);
2274 ath9k_hw_setrxabort(sc->sc_ah, 0);
2275 if (ieee80211_is_pspoll(hdr->frame_control)) {
4d6b228d 2276 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Sending PS-Poll to pick a "
9a23f9ca
JM		 2277 "buffered frame\n");
2278 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2279 } else {
4d6b228d 2280 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Wake up to complete TX\n");
9a23f9ca
JM		 2281 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2282 }
2283 /*
2284 * The actual restore operation will happen only after
2285 * the sc_flags bit is cleared. We are just dropping
2286 * the ps_usecount here.
2287 */
2288 ath9k_ps_restore(sc);
2289 }
2290
528f0c6b 2291 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2292
8feceb67
VT		 2293 /*
2294 * As a temporary workaround, assign seq# here; this will likely need
2295 * to be cleaned up to work better with Beacon transmission and virtual
2296 * BSSes.
2297 */
2298 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2299 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2300 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2301 sc->tx.seq_no += 0x10;
8feceb67 2302 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2303 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2304 }
f078f209 2305
8feceb67
VT		 2306 /* Add the padding after the header if this is not already done */
2307 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2308 if (hdrlen & 3) {
2309 padsize = hdrlen % 4;
2310 if (skb_headroom(skb) < padsize)
2311 return -1;
2312 skb_push(skb, padsize);
2313 memmove(skb->data, skb->data + padsize, hdrlen);
2314 }
2315
528f0c6b
S		 2316 /* Check if a tx queue is available */
2317
2318 txctl.txq = ath_test_get_txq(sc, skb);
2319 if (!txctl.txq)
2320 goto exit;
2321
4d6b228d 2322 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2323
c52f33d0 2324 if (ath_tx_start(hw, skb, &txctl) != 0) {
4d6b228d 2325 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2326 goto exit;
8feceb67
VT		 2327 }
2328
528f0c6b
S		 2329 return 0;
2330exit:
2331 dev_kfree_skb_any(skb);
8feceb67 2332 return 0;
f078f209
LR		 2333}
2334
75d7839f
LR		 2335/*
2336 * Pause btcoex timer and bt duty cycle timer
2337 */
2338static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2339{
2340 struct ath_btcoex *btcoex = &sc->btcoex;
2341 struct ath_hw *ah = sc->sc_ah;
2342
2343 del_timer_sync(&btcoex->period_timer);
2344
2345 if (btcoex->hw_timer_enabled)
2346 ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
2347
2348 btcoex->hw_timer_enabled = false;
2349}
2350
8feceb67 2351static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2352{
bce048d7
JM		 2353 struct ath_wiphy *aphy = hw->priv;
2354 struct ath_softc *sc = aphy->sc;
af03abec 2355 struct ath_hw *ah = sc->sc_ah;
f078f209 2356
4c483817
S		 2357 mutex_lock(&sc->mutex);
2358
9580a222
JM		 2359 aphy->state = ATH_WIPHY_INACTIVE;
2360
c94dbff7
LR		 2361 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2362 cancel_delayed_work_sync(&sc->tx_complete_work);
2363
2364 if (!sc->num_sec_wiphy) {
2365 cancel_delayed_work_sync(&sc->wiphy_work);
2366 cancel_work_sync(&sc->chan_work);
2367 }
2368
9c84b797 2369 if (sc->sc_flags & SC_OP_INVALID) {
af03abec 2370 DPRINTF(ah, ATH_DBG_ANY, "Device not present\n");
4c483817 2371 mutex_unlock(&sc->mutex);
9c84b797
S		 2372 return;
2373 }
8feceb67 2374
9580a222
JM		 2375 if (ath9k_wiphy_started(sc)) {
2376 mutex_unlock(&sc->mutex);
2377 return; /* another wiphy still in use */
2378 }
2379
766ec4a9 2380 if (ah->btcoex_hw.enabled) {
af03abec 2381 ath9k_hw_btcoex_disable(ah);
766ec4a9 2382 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2383 ath9k_btcoex_timer_pause(sc);
1773912b
VT		 2384 }
2385
ff37e337
S		 2386 /* make sure h/w will not generate any interrupt
2387 * before setting the invalid flag. */
af03abec 2388 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S		 2389
2390 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2391 ath_drain_all_txq(sc, false);
ff37e337 2392 ath_stoprecv(sc);
af03abec 2393 ath9k_hw_phy_disable(ah);
ff37e337 2394 } else
b77f483f 2395 sc->rx.rxlink = NULL;
ff37e337 2396
ff37e337 2397 /* disable HAL and put h/w to sleep */
af03abec
LR		 2398 ath9k_hw_disable(ah);
2399 ath9k_hw_configpcipowersave(ah, 1, 1);
2400 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
ff37e337
S		 2401
2402 sc->sc_flags |= SC_OP_INVALID;
500c064d 2403
141b38b6
S		 2404 mutex_unlock(&sc->mutex);
2405
af03abec 2406 DPRINTF(ah, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2407}
2408
8feceb67
VT		 2409static int ath9k_add_interface(struct ieee80211_hw *hw,
2410 struct ieee80211_if_init_conf *conf)
f078f209 2411{
bce048d7
JM		 2412 struct ath_wiphy *aphy = hw->priv;
2413 struct ath_softc *sc = aphy->sc;
17d7904d 2414 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2415 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2416 int ret = 0;
8feceb67 2417
141b38b6
S		 2418 mutex_lock(&sc->mutex);
2419
8ca21f01
JM		 2420 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2421 sc->nvifs > 0) {
2422 ret = -ENOBUFS;
2423 goto out;
2424 }
2425
8feceb67 2426 switch (conf->type) {
05c914fe 2427 case NL80211_IFTYPE_STATION:
d97809db 2428 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2429 break;
05c914fe 2430 case NL80211_IFTYPE_ADHOC:
05c914fe 2431 case NL80211_IFTYPE_AP:
9cb5412b 2432 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2433 if (sc->nbcnvifs >= ATH_BCBUF) {
2434 ret = -ENOBUFS;
2435 goto out;
2436 }
9cb5412b 2437 ic_opmode = conf->type;
f078f209
LR		 2438 break;
2439 default:
4d6b228d 2440 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
04bd4638 2441 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2442 ret = -EOPNOTSUPP;
2443 goto out;
f078f209
LR		 2444 }
2445
4d6b228d 2446 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2447
17d7904d 2448 /* Set the VIF opmode */
5640b08e
S		 2449 avp->av_opmode = ic_opmode;
2450 avp->av_bslot = -1;
2451
2c3db3d5 2452 sc->nvifs++;
8ca21f01
JM		 2453
2454 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2455 ath9k_set_bssid_mask(hw);
2456
2c3db3d5
JM		 2457 if (sc->nvifs > 1)
2458 goto out; /* skip global settings for secondary vif */
2459
b238e90e 2460 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2461 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2462 sc->sc_flags |= SC_OP_TSF_RESET;
2463 }
5640b08e 2464
5640b08e 2465 /* Set the device opmode */
2660b81a 2466 sc->sc_ah->opmode = ic_opmode;
5640b08e 2467
4e30ffa2
VN		 2468 /*
2469 * Enable MIB interrupts when there are hardware phy counters.
2470 * Note we only do this (at the moment) for station mode.
2471 */
4af9cf4f 2472 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2473 (conf->type == NL80211_IFTYPE_ADHOC) ||
2474 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 2475 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S		 2476 sc->imask |= ATH9K_INT_TSFOOR;
2477 }
2478
17d7904d 2479 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2480
f38faa31
SB		 2481 if (conf->type == NL80211_IFTYPE_AP ||
2482 conf->type == NL80211_IFTYPE_ADHOC ||
2483 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2484 ath_start_ani(sc);
6f255425 2485
2c3db3d5 2486out:
141b38b6 2487 mutex_unlock(&sc->mutex);
2c3db3d5 2488 return ret;
f078f209
LR		 2489}
2490
8feceb67
VT		 2491static void ath9k_remove_interface(struct ieee80211_hw *hw,
2492 struct ieee80211_if_init_conf *conf)
f078f209 2493{
bce048d7
JM		 2494 struct ath_wiphy *aphy = hw->priv;
2495 struct ath_softc *sc = aphy->sc;
17d7904d 2496 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2497 int i;
f078f209 2498
4d6b228d 2499 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2500
141b38b6
S		 2501 mutex_lock(&sc->mutex);
2502
6f255425 2503 /* Stop ANI */
17d7904d 2504 del_timer_sync(&sc->ani.timer);
580f0b8a 2505
8feceb67 2506 /* Reclaim beacon resources */
9cb5412b
PE		 2507 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2508 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2509 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2510 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2511 ath_beacon_return(sc, avp);
580f0b8a 2512 }
f078f209 2513
8feceb67 2514 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2515
2c3db3d5
JM		 2516 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2517 if (sc->beacon.bslot[i] == conf->vif) {
2518 printk(KERN_DEBUG "%s: vif had allocated beacon "
2519 "slot\n", __func__);
2520 sc->beacon.bslot[i] = NULL;
c52f33d0 2521 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2522 }
2523 }
2524
17d7904d 2525 sc->nvifs--;
141b38b6
S		 2526
2527 mutex_unlock(&sc->mutex);
f078f209
LR		 2528}
2529
e8975581 2530static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2531{
bce048d7
JM		 2532 struct ath_wiphy *aphy = hw->priv;
2533 struct ath_softc *sc = aphy->sc;
e8975581 2534 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2535 struct ath_hw *ah = sc->sc_ah;
64839170 2536 bool all_wiphys_idle = false, disable_radio = false;
f078f209 2537
aa33de09 2538 mutex_lock(&sc->mutex);
141b38b6 2539
64839170
LR		 2540 /* Leave this as the first check */
2541 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2542
2543 spin_lock_bh(&sc->wiphy_lock);
2544 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2545 spin_unlock_bh(&sc->wiphy_lock);
2546
2547 if (conf->flags & IEEE80211_CONF_IDLE){
2548 if (all_wiphys_idle)
2549 disable_radio = true;
2550 }
2551 else if (all_wiphys_idle) {
2552 ath_radio_enable(sc);
4d6b228d 2553 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
64839170
LR		 2554 "not-idle: enabling radio\n");
2555 }
2556 }
2557
3cbb5dd7
VN		 2558 if (changed & IEEE80211_CONF_CHANGE_PS) {
2559 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2560 if (!(ah->caps.hw_caps &
2561 ATH9K_HW_CAP_AUTOSLEEP)) {
2562 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2563 sc->imask |= ATH9K_INT_TIM_TIMER;
2564 ath9k_hw_set_interrupts(sc->sc_ah,
2565 sc->imask);
2566 }
2567 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2568 }
96148326 2569 sc->ps_enabled = true;
3cbb5dd7 2570 } else {
96148326 2571 sc->ps_enabled = false;
3cbb5dd7 2572 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2573 if (!(ah->caps.hw_caps &
2574 ATH9K_HW_CAP_AUTOSLEEP)) {
2575 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2576 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2577 SC_OP_WAIT_FOR_CAB |
2578 SC_OP_WAIT_FOR_PSPOLL_DATA |
2579 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2580 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2581 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2582 ath9k_hw_set_interrupts(sc->sc_ah,
2583 sc->imask);
2584 }
3cbb5dd7
VN		 2585 }
2586 }
2587 }
2588
4797938c 2589 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2590 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2591 int pos = curchan->hw_value;
ae5eb026 2592
0e2dedf9
JM		 2593 aphy->chan_idx = pos;
2594 aphy->chan_is_ht = conf_is_ht(conf);
2595
8089cc47
JM		 2596 if (aphy->state == ATH_WIPHY_SCAN ||
2597 aphy->state == ATH_WIPHY_ACTIVE)
2598 ath9k_wiphy_pause_all_forced(sc, aphy);
2599 else {
2600 /*
2601 * Do not change operational channel based on a paused
2602 * wiphy changes.
2603 */
2604 goto skip_chan_change;
2605 }
0e2dedf9 2606
4d6b228d 2607 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
04bd4638 2608 curchan->center_freq);
f078f209 2609
5f8e077c 2610 /* XXX: remove me eventualy */
0e2dedf9 2611 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2612
ecf70441 2613 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2614
0e2dedf9 2615 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
4d6b228d 2616 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2617 mutex_unlock(&sc->mutex);
e11602b7
S		 2618 return -EINVAL;
2619 }
094d05dc 2620 }
f078f209 2621
8089cc47 2622skip_chan_change:
5c020dc6 2623 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2624 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2625
64839170 2626 if (disable_radio) {
4d6b228d 2627 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "idle: disabling radio\n");
64839170
LR		 2628 ath_radio_disable(sc);
2629 }
2630
aa33de09 2631 mutex_unlock(&sc->mutex);
141b38b6 2632
f078f209
LR		 2633 return 0;
2634}
2635
8feceb67
VT		 2636#define SUPPORTED_FILTERS \
2637 (FIF_PROMISC_IN_BSS | \
2638 FIF_ALLMULTI | \
2639 FIF_CONTROL | \
af6a3fc7 2640 FIF_PSPOLL | \
8feceb67
VT		 2641 FIF_OTHER_BSS | \
2642 FIF_BCN_PRBRESP_PROMISC | \
2643 FIF_FCSFAIL)
c83be688 2644
8feceb67
VT		 2645/* FIXME: sc->sc_full_reset ? */
2646static void ath9k_configure_filter(struct ieee80211_hw *hw,
2647 unsigned int changed_flags,
2648 unsigned int *total_flags,
3ac64bee 2649 u64 multicast)
8feceb67 2650{
bce048d7
JM		 2651 struct ath_wiphy *aphy = hw->priv;
2652 struct ath_softc *sc = aphy->sc;
8feceb67 2653 u32 rfilt;
f078f209 2654
8feceb67
VT		 2655 changed_flags &= SUPPORTED_FILTERS;
2656 *total_flags &= SUPPORTED_FILTERS;
f078f209 2657
b77f483f 2658 sc->rx.rxfilter = *total_flags;
aa68aeaa 2659 ath9k_ps_wakeup(sc);
8feceb67
VT		 2660 rfilt = ath_calcrxfilter(sc);
2661 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2662 ath9k_ps_restore(sc);
f078f209 2663
4d6b228d 2664 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 2665}
f078f209 2666
8feceb67
VT		 2667static void ath9k_sta_notify(struct ieee80211_hw *hw,
2668 struct ieee80211_vif *vif,
2669 enum sta_notify_cmd cmd,
17741cdc 2670 struct ieee80211_sta *sta)
8feceb67 2671{
bce048d7
JM		 2672 struct ath_wiphy *aphy = hw->priv;
2673 struct ath_softc *sc = aphy->sc;
f078f209 2674
8feceb67
VT		 2675 switch (cmd) {
2676 case STA_NOTIFY_ADD:
5640b08e 2677 ath_node_attach(sc, sta);
8feceb67
VT		 2678 break;
2679 case STA_NOTIFY_REMOVE:
b5aa9bf9 2680 ath_node_detach(sc, sta);
8feceb67
VT		 2681 break;
2682 default:
2683 break;
2684 }
f078f209
LR		 2685}
2686
141b38b6 2687static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2688 const struct ieee80211_tx_queue_params *params)
f078f209 2689{
bce048d7
JM		 2690 struct ath_wiphy *aphy = hw->priv;
2691 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2692 struct ath9k_tx_queue_info qi;
2693 int ret = 0, qnum;
f078f209 2694
8feceb67
VT		 2695 if (queue >= WME_NUM_AC)
2696 return 0;
f078f209 2697
141b38b6
S		 2698 mutex_lock(&sc->mutex);
2699
1ffb0610
S		 2700 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2701
8feceb67
VT		 2702 qi.tqi_aifs = params->aifs;
2703 qi.tqi_cwmin = params->cw_min;
2704 qi.tqi_cwmax = params->cw_max;
2705 qi.tqi_burstTime = params->txop;
2706 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2707
4d6b228d 2708 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
04bd4638 2709 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2710 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2711 queue, qnum, params->aifs, params->cw_min,
2712 params->cw_max, params->txop);
f078f209 2713
8feceb67
VT		 2714 ret = ath_txq_update(sc, qnum, &qi);
2715 if (ret)
4d6b228d 2716 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2717
141b38b6
S		 2718 mutex_unlock(&sc->mutex);
2719
8feceb67
VT		 2720 return ret;
2721}
f078f209 2722
8feceb67
VT		 2723static int ath9k_set_key(struct ieee80211_hw *hw,
2724 enum set_key_cmd cmd,
dc822b5d
JB		 2725 struct ieee80211_vif *vif,
2726 struct ieee80211_sta *sta,
8feceb67
VT		 2727 struct ieee80211_key_conf *key)
2728{
bce048d7
JM		 2729 struct ath_wiphy *aphy = hw->priv;
2730 struct ath_softc *sc = aphy->sc;
8feceb67 2731 int ret = 0;
f078f209 2732
b3bd89ce
JM		 2733 if (modparam_nohwcrypt)
2734 return -ENOSPC;
2735
141b38b6 2736 mutex_lock(&sc->mutex);
3cbb5dd7 2737 ath9k_ps_wakeup(sc);
4d6b228d 2738 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2739
8feceb67
VT		 2740 switch (cmd) {
2741 case SET_KEY:
3f53dd64 2742 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2743 if (ret >= 0) {
2744 key->hw_key_idx = ret;
8feceb67
VT		 2745 /* push IV and Michael MIC generation to stack */
2746 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2747 if (key->alg == ALG_TKIP)
2748 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2749 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2750 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2751 ret = 0;
8feceb67
VT		 2752 }
2753 break;
2754 case DISABLE_KEY:
2755 ath_key_delete(sc, key);
8feceb67
VT		 2756 break;
2757 default:
2758 ret = -EINVAL;
2759 }
f078f209 2760
3cbb5dd7 2761 ath9k_ps_restore(sc);
141b38b6
S		 2762 mutex_unlock(&sc->mutex);
2763
8feceb67
VT		 2764 return ret;
2765}
f078f209 2766
8feceb67
VT		 2767static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2768 struct ieee80211_vif *vif,
2769 struct ieee80211_bss_conf *bss_conf,
2770 u32 changed)
2771{
bce048d7
JM		 2772 struct ath_wiphy *aphy = hw->priv;
2773 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2774 struct ath_hw *ah = sc->sc_ah;
2775 struct ath_vif *avp = (void *)vif->drv_priv;
2776 u32 rfilt = 0;
2777 int error, i;
f078f209 2778
141b38b6
S		 2779 mutex_lock(&sc->mutex);
2780
2d0ddec5
JB		 2781 /*
2782 * TODO: Need to decide which hw opmode to use for
2783 * multi-interface cases
2784 * XXX: This belongs into add_interface!
2785 */
2786 if (vif->type == NL80211_IFTYPE_AP &&
2787 ah->opmode != NL80211_IFTYPE_AP) {
2788 ah->opmode = NL80211_IFTYPE_STATION;
2789 ath9k_hw_setopmode(ah);
2790 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2791 sc->curaid = 0;
2792 ath9k_hw_write_associd(sc);
2793 /* Request full reset to get hw opmode changed properly */
2794 sc->sc_flags |= SC_OP_FULL_RESET;
2795 }
2796
2797 if ((changed & BSS_CHANGED_BSSID) &&
2798 !is_zero_ether_addr(bss_conf->bssid)) {
2799 switch (vif->type) {
2800 case NL80211_IFTYPE_STATION:
2801 case NL80211_IFTYPE_ADHOC:
2802 case NL80211_IFTYPE_MESH_POINT:
2803 /* Set BSSID */
2804 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2805 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2806 sc->curaid = 0;
2807 ath9k_hw_write_associd(sc);
2808
2809 /* Set aggregation protection mode parameters */
2810 sc->config.ath_aggr_prot = 0;
2811
4d6b228d 2812 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2d0ddec5
JB		 2813 "RX filter 0x%x bssid %pM aid 0x%x\n",
2814 rfilt, sc->curbssid, sc->curaid);
2815
2816 /* need to reconfigure the beacon */
2817 sc->sc_flags &= ~SC_OP_BEACONS ;
2818
2819 break;
2820 default:
2821 break;
2822 }
2823 }
2824
2825 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2826 (vif->type == NL80211_IFTYPE_AP) ||
2827 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2828 if ((changed & BSS_CHANGED_BEACON) ||
2829 (changed & BSS_CHANGED_BEACON_ENABLED &&
2830 bss_conf->enable_beacon)) {
2831 /*
2832 * Allocate and setup the beacon frame.
2833 *
2834 * Stop any previous beacon DMA. This may be
2835 * necessary, for example, when an ibss merge
2836 * causes reconfiguration; we may be called
2837 * with beacon transmission active.
2838 */
2839 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2840
2841 error = ath_beacon_alloc(aphy, vif);
2842 if (!error)
2843 ath_beacon_config(sc, vif);
2844 }
2845 }
2846
2847 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2848 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2849 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2850 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2851 ath9k_hw_keysetmac(sc->sc_ah,
2852 (u16)i,
2853 sc->curbssid);
2854 }
2855
2856 /* Only legacy IBSS for now */
2857 if (vif->type == NL80211_IFTYPE_ADHOC)
2858 ath_update_chainmask(sc, 0);
2859
8feceb67 2860 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4d6b228d 2861 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2862 bss_conf->use_short_preamble);
2863 if (bss_conf->use_short_preamble)
2864 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2865 else
2866 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2867 }
f078f209 2868
8feceb67 2869 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
4d6b228d 2870 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2871 bss_conf->use_cts_prot);
2872 if (bss_conf->use_cts_prot &&
2873 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2874 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2875 else
2876 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2877 }
f078f209 2878
8feceb67 2879 if (changed & BSS_CHANGED_ASSOC) {
4d6b228d 2880 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2881 bss_conf->assoc);
5640b08e 2882 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2883 }
141b38b6 2884
57c4d7b4
JB		 2885 /*
2886 * The HW TSF has to be reset when the beacon interval changes.
2887 * We set the flag here, and ath_beacon_config_ap() would take this
2888 * into account when it gets called through the subsequent
2889 * config_interface() call - with IFCC_BEACON in the changed field.
2890 */
2891
2892 if (changed & BSS_CHANGED_BEACON_INT) {
2893 sc->sc_flags |= SC_OP_TSF_RESET;
2894 sc->beacon_interval = bss_conf->beacon_int;
2895 }
2896
141b38b6 2897 mutex_unlock(&sc->mutex);
8feceb67 2898}
f078f209 2899
8feceb67
VT		 2900static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2901{
2902 u64 tsf;
bce048d7
JM		 2903 struct ath_wiphy *aphy = hw->priv;
2904 struct ath_softc *sc = aphy->sc;
f078f209 2905
141b38b6
S		 2906 mutex_lock(&sc->mutex);
2907 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2908 mutex_unlock(&sc->mutex);
f078f209 2909
8feceb67
VT		 2910 return tsf;
2911}
f078f209 2912
3b5d665b
AF		 2913static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2914{
bce048d7
JM		 2915 struct ath_wiphy *aphy = hw->priv;
2916 struct ath_softc *sc = aphy->sc;
3b5d665b 2917
141b38b6
S		 2918 mutex_lock(&sc->mutex);
2919 ath9k_hw_settsf64(sc->sc_ah, tsf);
2920 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2921}
2922
8feceb67
VT		 2923static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2924{
bce048d7
JM		 2925 struct ath_wiphy *aphy = hw->priv;
2926 struct ath_softc *sc = aphy->sc;
c83be688 2927
141b38b6 2928 mutex_lock(&sc->mutex);
21526d57
LR		 2929
2930 ath9k_ps_wakeup(sc);
141b38b6 2931 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 2932 ath9k_ps_restore(sc);
2933
141b38b6 2934 mutex_unlock(&sc->mutex);
8feceb67 2935}
f078f209 2936
8feceb67 2937static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2938 enum ieee80211_ampdu_mlme_action action,
2939 struct ieee80211_sta *sta,
2940 u16 tid, u16 *ssn)
8feceb67 2941{
bce048d7
JM		 2942 struct ath_wiphy *aphy = hw->priv;
2943 struct ath_softc *sc = aphy->sc;
8feceb67 2944 int ret = 0;
f078f209 2945
8feceb67
VT		 2946 switch (action) {
2947 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2948 if (!(sc->sc_flags & SC_OP_RXAGGR))
2949 ret = -ENOTSUPP;
8feceb67
VT		 2950 break;
2951 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2952 break;
2953 case IEEE80211_AMPDU_TX_START:
f83da965
S		 2954 ath_tx_aggr_start(sc, sta, tid, ssn);
2955 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2956 break;
2957 case IEEE80211_AMPDU_TX_STOP:
f83da965 2958 ath_tx_aggr_stop(sc, sta, tid);
17741cdc 2959 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2960 break;
b1720231 2961 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2962 ath_tx_aggr_resume(sc, sta, tid);
2963 break;
8feceb67 2964 default:
4d6b228d 2965 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2966 }
2967
2968 return ret;
f078f209
LR		 2969}
2970
0c98de65
S		 2971static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2972{
bce048d7
JM		 2973 struct ath_wiphy *aphy = hw->priv;
2974 struct ath_softc *sc = aphy->sc;
0c98de65 2975
3d832611 2976 mutex_lock(&sc->mutex);
8089cc47
JM		 2977 if (ath9k_wiphy_scanning(sc)) {
2978 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2979 "same time\n");
2980 /*
2981 * Do not allow the concurrent scanning state for now. This
2982 * could be improved with scanning control moved into ath9k.
2983 */
3d832611 2984 mutex_unlock(&sc->mutex);
8089cc47
JM		 2985 return;
2986 }
2987
2988 aphy->state = ATH_WIPHY_SCAN;
2989 ath9k_wiphy_pause_all_forced(sc, aphy);
2990
e5f0921a 2991 spin_lock_bh(&sc->ani_lock);
0c98de65 2992 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 2993 spin_unlock_bh(&sc->ani_lock);
3d832611 2994 mutex_unlock(&sc->mutex);
0c98de65
S		 2995}
2996
2997static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2998{
bce048d7
JM		 2999 struct ath_wiphy *aphy = hw->priv;
3000 struct ath_softc *sc = aphy->sc;
0c98de65 3001
3d832611 3002 mutex_lock(&sc->mutex);
e5f0921a 3003 spin_lock_bh(&sc->ani_lock);
8089cc47 3004 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 3005 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 3006 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 3007 spin_unlock_bh(&sc->ani_lock);
d0bec342 3008 ath_beacon_config(sc, NULL);
3d832611 3009 mutex_unlock(&sc->mutex);
0c98de65
S		 3010}
3011
6baff7f9 3012struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 3013 .tx = ath9k_tx,
3014 .start = ath9k_start,
3015 .stop = ath9k_stop,
3016 .add_interface = ath9k_add_interface,
3017 .remove_interface = ath9k_remove_interface,
3018 .config = ath9k_config,
8feceb67 3019 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 3020 .sta_notify = ath9k_sta_notify,
3021 .conf_tx = ath9k_conf_tx,
8feceb67 3022 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 3023 .set_key = ath9k_set_key,
8feceb67 3024 .get_tsf = ath9k_get_tsf,
3b5d665b 3025 .set_tsf = ath9k_set_tsf,
8feceb67 3026 .reset_tsf = ath9k_reset_tsf,
4233df6b 3027 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 3028 .sw_scan_start = ath9k_sw_scan_start,
3029 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 3030 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 3031};
3032
392dff83
BP		 3033static struct {
3034 u32 version;
3035 const char * name;
3036} ath_mac_bb_names[] = {
3037 { AR_SREV_VERSION_5416_PCI, "5416" },
3038 { AR_SREV_VERSION_5416_PCIE, "5418" },
3039 { AR_SREV_VERSION_9100, "9100" },
3040 { AR_SREV_VERSION_9160, "9160" },
3041 { AR_SREV_VERSION_9280, "9280" },
ac88b6ec
VN		 3042 { AR_SREV_VERSION_9285, "9285" },
3043 { AR_SREV_VERSION_9287, "9287" }
392dff83
BP		 3044};
3045
3046static struct {
3047 u16 version;
3048 const char * name;
3049} ath_rf_names[] = {
3050 { 0, "5133" },
3051 { AR_RAD5133_SREV_MAJOR, "5133" },
3052 { AR_RAD5122_SREV_MAJOR, "5122" },
3053 { AR_RAD2133_SREV_MAJOR, "2133" },
3054 { AR_RAD2122_SREV_MAJOR, "2122" }
3055};
3056
3057/*
3058 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3059 */
6baff7f9 3060const char *
392dff83
BP		 3061ath_mac_bb_name(u32 mac_bb_version)
3062{
3063 int i;
3064
3065 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3066 if (ath_mac_bb_names[i].version == mac_bb_version) {
3067 return ath_mac_bb_names[i].name;
3068 }
3069 }
3070
3071 return "????";
3072}
3073
3074/*
3075 * Return the RF name. "????" is returned if the RF is unknown.
3076 */
6baff7f9 3077const char *
392dff83
BP		 3078ath_rf_name(u16 rf_version)
3079{
3080 int i;
3081
3082 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3083 if (ath_rf_names[i].version == rf_version) {
3084 return ath_rf_names[i].name;
3085 }
3086 }
3087
3088 return "????";
3089}
3090
6baff7f9 3091static int __init ath9k_init(void)
f078f209 3092{
ca8a8560
VT		 3093 int error;
3094
ca8a8560
VT		 3095 /* Register rate control algorithm */
3096 error = ath_rate_control_register();
3097 if (error != 0) {
3098 printk(KERN_ERR
b51bb3cd
LR		 3099 "ath9k: Unable to register rate control "
3100 "algorithm: %d\n",
ca8a8560 3101 error);
6baff7f9 3102 goto err_out;
ca8a8560
VT		 3103 }
3104
19d8bc22
GJ		 3105 error = ath9k_debug_create_root();
3106 if (error) {
3107 printk(KERN_ERR
3108 "ath9k: Unable to create debugfs root: %d\n",
3109 error);
3110 goto err_rate_unregister;
3111 }
3112
6baff7f9
GJ		 3113 error = ath_pci_init();
3114 if (error < 0) {
f078f209 3115 printk(KERN_ERR
b51bb3cd 3116 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 3117 error = -ENODEV;
19d8bc22 3118 goto err_remove_root;
f078f209
LR		 3119 }
3120
09329d37
GJ		 3121 error = ath_ahb_init();
3122 if (error < 0) {
3123 error = -ENODEV;
3124 goto err_pci_exit;
3125 }
3126
f078f209 3127 return 0;
6baff7f9 3128
09329d37
GJ		 3129 err_pci_exit:
3130 ath_pci_exit();
3131
19d8bc22
GJ		 3132 err_remove_root:
3133 ath9k_debug_remove_root();
6baff7f9
GJ		 3134 err_rate_unregister:
3135 ath_rate_control_unregister();
3136 err_out:
3137 return error;
f078f209 3138}
6baff7f9 3139module_init(ath9k_init);
f078f209 3140
6baff7f9 3141static void __exit ath9k_exit(void)
f078f209 3142{
09329d37 3143 ath_ahb_exit();
6baff7f9 3144 ath_pci_exit();
19d8bc22 3145 ath9k_debug_remove_root();
ca8a8560 3146 ath_rate_control_unregister();
04bd4638 3147 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 3148}
6baff7f9 3149module_exit(ath9k_exit);
Linux kernel - Deliverables
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