Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
ce111bad LR |
21 | static void ath_cache_conf_rate(struct ath_softc *sc, |
22 | struct ieee80211_conf *conf) | |
ff37e337 | 23 | { |
030bb495 LR |
24 | switch (conf->channel->band) { |
25 | case IEEE80211_BAND_2GHZ: | |
26 | if (conf_is_ht20(conf)) | |
545750d3 | 27 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT20; |
030bb495 | 28 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 29 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS; |
030bb495 | 30 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 31 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS; |
96742256 | 32 | else |
545750d3 | 33 | sc->cur_rate_mode = ATH9K_MODE_11G; |
030bb495 LR |
34 | break; |
35 | case IEEE80211_BAND_5GHZ: | |
36 | if (conf_is_ht20(conf)) | |
545750d3 | 37 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT20; |
030bb495 | 38 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 39 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS; |
030bb495 | 40 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 41 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS; |
030bb495 | 42 | else |
545750d3 | 43 | sc->cur_rate_mode = ATH9K_MODE_11A; |
030bb495 LR |
44 | break; |
45 | default: | |
ce111bad | 46 | BUG_ON(1); |
030bb495 LR |
47 | break; |
48 | } | |
ff37e337 S |
49 | } |
50 | ||
51 | static void ath_update_txpow(struct ath_softc *sc) | |
52 | { | |
cbe61d8a | 53 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
54 | u32 txpow; |
55 | ||
17d7904d S |
56 | if (sc->curtxpow != sc->config.txpowlimit) { |
57 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 S |
58 | /* read back in case value is clamped */ |
59 | ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow); | |
17d7904d | 60 | sc->curtxpow = txpow; |
ff37e337 S |
61 | } |
62 | } | |
63 | ||
64 | static u8 parse_mpdudensity(u8 mpdudensity) | |
65 | { | |
66 | /* | |
67 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
68 | * 0 for no restriction | |
69 | * 1 for 1/4 us | |
70 | * 2 for 1/2 us | |
71 | * 3 for 1 us | |
72 | * 4 for 2 us | |
73 | * 5 for 4 us | |
74 | * 6 for 8 us | |
75 | * 7 for 16 us | |
76 | */ | |
77 | switch (mpdudensity) { | |
78 | case 0: | |
79 | return 0; | |
80 | case 1: | |
81 | case 2: | |
82 | case 3: | |
83 | /* Our lower layer calculations limit our precision to | |
84 | 1 microsecond */ | |
85 | return 1; | |
86 | case 4: | |
87 | return 2; | |
88 | case 5: | |
89 | return 4; | |
90 | case 6: | |
91 | return 8; | |
92 | case 7: | |
93 | return 16; | |
94 | default: | |
95 | return 0; | |
96 | } | |
97 | } | |
98 | ||
82880a7c VT |
99 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
100 | struct ieee80211_hw *hw) | |
101 | { | |
102 | struct ieee80211_channel *curchan = hw->conf.channel; | |
103 | struct ath9k_channel *channel; | |
104 | u8 chan_idx; | |
105 | ||
106 | chan_idx = curchan->hw_value; | |
107 | channel = &sc->sc_ah->channels[chan_idx]; | |
108 | ath9k_update_ichannel(sc, hw, channel); | |
109 | return channel; | |
110 | } | |
111 | ||
55624204 | 112 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
113 | { |
114 | unsigned long flags; | |
115 | bool ret; | |
116 | ||
9ecdef4b LR |
117 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
118 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
119 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
120 | |
121 | return ret; | |
122 | } | |
123 | ||
a91d75ae LR |
124 | void ath9k_ps_wakeup(struct ath_softc *sc) |
125 | { | |
126 | unsigned long flags; | |
127 | ||
128 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
129 | if (++sc->ps_usecount != 1) | |
130 | goto unlock; | |
131 | ||
9ecdef4b | 132 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae LR |
133 | |
134 | unlock: | |
135 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
136 | } | |
137 | ||
138 | void ath9k_ps_restore(struct ath_softc *sc) | |
139 | { | |
140 | unsigned long flags; | |
141 | ||
142 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
143 | if (--sc->ps_usecount != 0) | |
144 | goto unlock; | |
145 | ||
1dbfd9d4 VN |
146 | if (sc->ps_idle) |
147 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
148 | else if (sc->ps_enabled && | |
149 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
150 | PS_WAIT_FOR_CAB | |
151 | PS_WAIT_FOR_PSPOLL_DATA | | |
152 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 153 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
154 | |
155 | unlock: | |
156 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
157 | } | |
158 | ||
ff37e337 S |
159 | /* |
160 | * Set/change channels. If the channel is really being changed, it's done | |
161 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
162 | * DMA, then restart stuff. | |
163 | */ | |
0e2dedf9 JM |
164 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
165 | struct ath9k_channel *hchan) | |
ff37e337 | 166 | { |
cbe61d8a | 167 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 168 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 169 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 170 | bool fastcc = true, stopped; |
ae8d2858 LR |
171 | struct ieee80211_channel *channel = hw->conf.channel; |
172 | int r; | |
ff37e337 S |
173 | |
174 | if (sc->sc_flags & SC_OP_INVALID) | |
175 | return -EIO; | |
176 | ||
3cbb5dd7 VN |
177 | ath9k_ps_wakeup(sc); |
178 | ||
c0d7c7af LR |
179 | /* |
180 | * This is only performed if the channel settings have | |
181 | * actually changed. | |
182 | * | |
183 | * To switch channels clear any pending DMA operations; | |
184 | * wait long enough for the RX fifo to drain, reset the | |
185 | * hardware at the new frequency, and then re-enable | |
186 | * the relevant bits of the h/w. | |
187 | */ | |
188 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 189 | ath_drain_all_txq(sc, false); |
c0d7c7af | 190 | stopped = ath_stoprecv(sc); |
ff37e337 | 191 | |
c0d7c7af LR |
192 | /* XXX: do not flush receive queue here. We don't want |
193 | * to flush data frames already in queue because of | |
194 | * changing channel. */ | |
ff37e337 | 195 | |
c0d7c7af LR |
196 | if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) |
197 | fastcc = false; | |
198 | ||
c46917bb | 199 | ath_print(common, ATH_DBG_CONFIG, |
25c56eec | 200 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n", |
c46917bb | 201 | sc->sc_ah->curchan->channel, |
25c56eec | 202 | channel->center_freq, conf_is_ht40(conf)); |
ff37e337 | 203 | |
c0d7c7af LR |
204 | spin_lock_bh(&sc->sc_resetlock); |
205 | ||
206 | r = ath9k_hw_reset(ah, hchan, fastcc); | |
207 | if (r) { | |
c46917bb | 208 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 209 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
210 | "reset status %d\n", |
211 | channel->center_freq, r); | |
c0d7c7af | 212 | spin_unlock_bh(&sc->sc_resetlock); |
3989279c | 213 | goto ps_restore; |
ff37e337 | 214 | } |
c0d7c7af LR |
215 | spin_unlock_bh(&sc->sc_resetlock); |
216 | ||
c0d7c7af LR |
217 | sc->sc_flags &= ~SC_OP_FULL_RESET; |
218 | ||
219 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
220 | ath_print(common, ATH_DBG_FATAL, |
221 | "Unable to restart recv logic\n"); | |
3989279c GJ |
222 | r = -EIO; |
223 | goto ps_restore; | |
c0d7c7af LR |
224 | } |
225 | ||
226 | ath_cache_conf_rate(sc, &hw->conf); | |
227 | ath_update_txpow(sc); | |
3069168c | 228 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c GJ |
229 | |
230 | ps_restore: | |
3cbb5dd7 | 231 | ath9k_ps_restore(sc); |
3989279c | 232 | return r; |
ff37e337 S |
233 | } |
234 | ||
235 | /* | |
236 | * This routine performs the periodic noise floor calibration function | |
237 | * that is used to adjust and optimize the chip performance. This | |
238 | * takes environmental changes (location, temperature) into account. | |
239 | * When the task is complete, it reschedules itself depending on the | |
240 | * appropriate interval that was calculated. | |
241 | */ | |
55624204 | 242 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 243 | { |
20977d3e S |
244 | struct ath_softc *sc = (struct ath_softc *)data; |
245 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 246 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
247 | bool longcal = false; |
248 | bool shortcal = false; | |
249 | bool aniflag = false; | |
250 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
20977d3e | 251 | u32 cal_interval, short_cal_interval; |
ff37e337 | 252 | |
20977d3e S |
253 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
254 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 255 | |
1ffc1c61 JM |
256 | /* Only calibrate if awake */ |
257 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
258 | goto set_timer; | |
259 | ||
260 | ath9k_ps_wakeup(sc); | |
261 | ||
ff37e337 | 262 | /* Long calibration runs independently of short calibration. */ |
3d536acf | 263 | if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { |
ff37e337 | 264 | longcal = true; |
c46917bb | 265 | ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 266 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
267 | } |
268 | ||
17d7904d | 269 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
270 | if (!common->ani.caldone) { |
271 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 272 | shortcal = true; |
c46917bb LR |
273 | ath_print(common, ATH_DBG_ANI, |
274 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
275 | common->ani.shortcal_timer = timestamp; |
276 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
277 | } |
278 | } else { | |
3d536acf | 279 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 280 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
281 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
282 | if (common->ani.caldone) | |
283 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
284 | } |
285 | } | |
286 | ||
287 | /* Verify whether we must check ANI */ | |
e36b27af LR |
288 | if ((timestamp - common->ani.checkani_timer) >= |
289 | ah->config.ani_poll_interval) { | |
ff37e337 | 290 | aniflag = true; |
3d536acf | 291 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
292 | } |
293 | ||
294 | /* Skip all processing if there's nothing to do. */ | |
295 | if (longcal || shortcal || aniflag) { | |
296 | /* Call ANI routine if necessary */ | |
297 | if (aniflag) | |
22e66a4c | 298 | ath9k_hw_ani_monitor(ah, ah->curchan); |
ff37e337 S |
299 | |
300 | /* Perform calibration if necessary */ | |
301 | if (longcal || shortcal) { | |
3d536acf | 302 | common->ani.caldone = |
43c27613 LR |
303 | ath9k_hw_calibrate(ah, |
304 | ah->curchan, | |
305 | common->rx_chainmask, | |
306 | longcal); | |
379f0440 S |
307 | |
308 | if (longcal) | |
3d536acf | 309 | common->ani.noise_floor = ath9k_hw_getchan_noise(ah, |
379f0440 S |
310 | ah->curchan); |
311 | ||
c46917bb LR |
312 | ath_print(common, ATH_DBG_ANI, |
313 | " calibrate chan %u/%x nf: %d\n", | |
314 | ah->curchan->channel, | |
315 | ah->curchan->channelFlags, | |
3d536acf | 316 | common->ani.noise_floor); |
ff37e337 S |
317 | } |
318 | } | |
319 | ||
1ffc1c61 JM |
320 | ath9k_ps_restore(sc); |
321 | ||
20977d3e | 322 | set_timer: |
ff37e337 S |
323 | /* |
324 | * Set timer interval based on previous results. | |
325 | * The interval must be the shortest necessary to satisfy ANI, | |
326 | * short calibration and long calibration. | |
327 | */ | |
aac9207e | 328 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 329 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
330 | cal_interval = min(cal_interval, |
331 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 332 | if (!common->ani.caldone) |
20977d3e | 333 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 334 | |
3d536acf | 335 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
ff37e337 S |
336 | } |
337 | ||
3d536acf | 338 | static void ath_start_ani(struct ath_common *common) |
415f738e | 339 | { |
e36b27af | 340 | struct ath_hw *ah = common->ah; |
415f738e S |
341 | unsigned long timestamp = jiffies_to_msecs(jiffies); |
342 | ||
3d536acf LR |
343 | common->ani.longcal_timer = timestamp; |
344 | common->ani.shortcal_timer = timestamp; | |
345 | common->ani.checkani_timer = timestamp; | |
415f738e | 346 | |
3d536acf | 347 | mod_timer(&common->ani.timer, |
e36b27af LR |
348 | jiffies + |
349 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
415f738e S |
350 | } |
351 | ||
ff37e337 S |
352 | /* |
353 | * Update tx/rx chainmask. For legacy association, | |
354 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
355 | * the chainmask configuration, for bt coexistence, use |
356 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 357 | */ |
0e2dedf9 | 358 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 359 | { |
af03abec | 360 | struct ath_hw *ah = sc->sc_ah; |
43c27613 | 361 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 362 | |
3d832611 | 363 | if ((sc->sc_flags & SC_OP_SCANNING) || is_ht || |
766ec4a9 | 364 | (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { |
43c27613 LR |
365 | common->tx_chainmask = ah->caps.tx_chainmask; |
366 | common->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 | 367 | } else { |
43c27613 LR |
368 | common->tx_chainmask = 1; |
369 | common->rx_chainmask = 1; | |
ff37e337 S |
370 | } |
371 | ||
43c27613 | 372 | ath_print(common, ATH_DBG_CONFIG, |
c46917bb | 373 | "tx chmask: %d, rx chmask: %d\n", |
43c27613 LR |
374 | common->tx_chainmask, |
375 | common->rx_chainmask); | |
ff37e337 S |
376 | } |
377 | ||
378 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
379 | { | |
380 | struct ath_node *an; | |
381 | ||
382 | an = (struct ath_node *)sta->drv_priv; | |
383 | ||
87792efc | 384 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 385 | ath_tx_node_init(sc, an); |
9e98ac65 | 386 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
387 | sta->ht_cap.ampdu_factor); |
388 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
a59b5a5e | 389 | an->last_rssi = ATH_RSSI_DUMMY_MARKER; |
87792efc | 390 | } |
ff37e337 S |
391 | } |
392 | ||
393 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
394 | { | |
395 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
396 | ||
397 | if (sc->sc_flags & SC_OP_TXAGGR) | |
398 | ath_tx_node_cleanup(sc, an); | |
399 | } | |
400 | ||
55624204 | 401 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
402 | { |
403 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 404 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 405 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 406 | |
17d7904d | 407 | u32 status = sc->intrstatus; |
b5c80475 | 408 | u32 rxmask; |
ff37e337 | 409 | |
153e080d VT |
410 | ath9k_ps_wakeup(sc); |
411 | ||
c9c99e5e FF |
412 | if ((status & ATH9K_INT_FATAL) || |
413 | !ath9k_hw_check_alive(ah)) { | |
ff37e337 | 414 | ath_reset(sc, false); |
153e080d | 415 | ath9k_ps_restore(sc); |
ff37e337 | 416 | return; |
063d8be3 | 417 | } |
ff37e337 | 418 | |
b5c80475 FF |
419 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
420 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
421 | ATH9K_INT_RXORN); | |
422 | else | |
423 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
424 | ||
425 | if (status & rxmask) { | |
063d8be3 | 426 | spin_lock_bh(&sc->rx.rxflushlock); |
b5c80475 FF |
427 | |
428 | /* Check for high priority Rx first */ | |
429 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
430 | (status & ATH9K_INT_RXHP)) | |
431 | ath_rx_tasklet(sc, 0, true); | |
432 | ||
433 | ath_rx_tasklet(sc, 0, false); | |
063d8be3 | 434 | spin_unlock_bh(&sc->rx.rxflushlock); |
ff37e337 S |
435 | } |
436 | ||
e5003249 VT |
437 | if (status & ATH9K_INT_TX) { |
438 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
439 | ath_tx_edma_tasklet(sc); | |
440 | else | |
441 | ath_tx_tasklet(sc); | |
442 | } | |
063d8be3 | 443 | |
96148326 | 444 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
445 | /* |
446 | * TSF sync does not look correct; remain awake to sync with | |
447 | * the next Beacon. | |
448 | */ | |
c46917bb LR |
449 | ath_print(common, ATH_DBG_PS, |
450 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 451 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
452 | } |
453 | ||
766ec4a9 | 454 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
455 | if (status & ATH9K_INT_GENTIMER) |
456 | ath_gen_timer_isr(sc->sc_ah); | |
457 | ||
ff37e337 | 458 | /* re-enable hardware interrupt */ |
3069168c | 459 | ath9k_hw_set_interrupts(ah, ah->imask); |
153e080d | 460 | ath9k_ps_restore(sc); |
ff37e337 S |
461 | } |
462 | ||
6baff7f9 | 463 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 464 | { |
063d8be3 S |
465 | #define SCHED_INTR ( \ |
466 | ATH9K_INT_FATAL | \ | |
467 | ATH9K_INT_RXORN | \ | |
468 | ATH9K_INT_RXEOL | \ | |
469 | ATH9K_INT_RX | \ | |
b5c80475 FF |
470 | ATH9K_INT_RXLP | \ |
471 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
472 | ATH9K_INT_TX | \ |
473 | ATH9K_INT_BMISS | \ | |
474 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
475 | ATH9K_INT_TSFOOR | \ |
476 | ATH9K_INT_GENTIMER) | |
063d8be3 | 477 | |
ff37e337 | 478 | struct ath_softc *sc = dev; |
cbe61d8a | 479 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
480 | enum ath9k_int status; |
481 | bool sched = false; | |
482 | ||
063d8be3 S |
483 | /* |
484 | * The hardware is not ready/present, don't | |
485 | * touch anything. Note this can happen early | |
486 | * on if the IRQ is shared. | |
487 | */ | |
488 | if (sc->sc_flags & SC_OP_INVALID) | |
489 | return IRQ_NONE; | |
ff37e337 | 490 | |
063d8be3 S |
491 | |
492 | /* shared irq, not for us */ | |
493 | ||
153e080d | 494 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 495 | return IRQ_NONE; |
063d8be3 S |
496 | |
497 | /* | |
498 | * Figure out the reason(s) for the interrupt. Note | |
499 | * that the hal returns a pseudo-ISR that may include | |
500 | * bits we haven't explicitly enabled so we mask the | |
501 | * value to insure we only process bits we requested. | |
502 | */ | |
503 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 504 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 505 | |
063d8be3 S |
506 | /* |
507 | * If there are no status bits set, then this interrupt was not | |
508 | * for me (should have been caught above). | |
509 | */ | |
153e080d | 510 | if (!status) |
063d8be3 | 511 | return IRQ_NONE; |
ff37e337 | 512 | |
063d8be3 S |
513 | /* Cache the status */ |
514 | sc->intrstatus = status; | |
515 | ||
516 | if (status & SCHED_INTR) | |
517 | sched = true; | |
518 | ||
519 | /* | |
520 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
521 | * chip immediately. | |
522 | */ | |
b5c80475 FF |
523 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
524 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
525 | goto chip_reset; |
526 | ||
08578b8f LR |
527 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
528 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
529 | ar9003_hw_bb_watchdog_dbg_info(ah); | |
530 | goto chip_reset; | |
531 | } | |
532 | ||
063d8be3 S |
533 | if (status & ATH9K_INT_SWBA) |
534 | tasklet_schedule(&sc->bcon_tasklet); | |
535 | ||
536 | if (status & ATH9K_INT_TXURN) | |
537 | ath9k_hw_updatetxtriglevel(ah, true); | |
538 | ||
b5c80475 FF |
539 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
540 | if (status & ATH9K_INT_RXEOL) { | |
541 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
542 | ath9k_hw_set_interrupts(ah, ah->imask); | |
543 | } | |
544 | } | |
545 | ||
063d8be3 | 546 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 547 | /* |
063d8be3 S |
548 | * Disable interrupts until we service the MIB |
549 | * interrupt; otherwise it will continue to | |
550 | * fire. | |
ff37e337 | 551 | */ |
063d8be3 S |
552 | ath9k_hw_set_interrupts(ah, 0); |
553 | /* | |
554 | * Let the hal handle the event. We assume | |
555 | * it will clear whatever condition caused | |
556 | * the interrupt. | |
557 | */ | |
22e66a4c | 558 | ath9k_hw_procmibevent(ah); |
3069168c | 559 | ath9k_hw_set_interrupts(ah, ah->imask); |
063d8be3 | 560 | } |
ff37e337 | 561 | |
153e080d VT |
562 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
563 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
564 | /* Clear RxAbort bit so that we can |
565 | * receive frames */ | |
9ecdef4b | 566 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 567 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 568 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 569 | } |
063d8be3 S |
570 | |
571 | chip_reset: | |
ff37e337 | 572 | |
817e11de S |
573 | ath_debug_stat_interrupt(sc, status); |
574 | ||
ff37e337 S |
575 | if (sched) { |
576 | /* turn off every interrupt except SWBA */ | |
3069168c | 577 | ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
578 | tasklet_schedule(&sc->intr_tq); |
579 | } | |
580 | ||
581 | return IRQ_HANDLED; | |
063d8be3 S |
582 | |
583 | #undef SCHED_INTR | |
ff37e337 S |
584 | } |
585 | ||
f078f209 | 586 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 587 | struct ieee80211_channel *chan, |
094d05dc | 588 | enum nl80211_channel_type channel_type) |
f078f209 LR |
589 | { |
590 | u32 chanmode = 0; | |
f078f209 LR |
591 | |
592 | switch (chan->band) { | |
593 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
594 | switch(channel_type) { |
595 | case NL80211_CHAN_NO_HT: | |
596 | case NL80211_CHAN_HT20: | |
f078f209 | 597 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
598 | break; |
599 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 600 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
601 | break; |
602 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 603 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
604 | break; |
605 | } | |
f078f209 LR |
606 | break; |
607 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
608 | switch(channel_type) { |
609 | case NL80211_CHAN_NO_HT: | |
610 | case NL80211_CHAN_HT20: | |
f078f209 | 611 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
612 | break; |
613 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 614 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
615 | break; |
616 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 617 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
618 | break; |
619 | } | |
f078f209 LR |
620 | break; |
621 | default: | |
622 | break; | |
623 | } | |
624 | ||
625 | return chanmode; | |
626 | } | |
627 | ||
8feceb67 | 628 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 629 | struct ieee80211_vif *vif, |
8feceb67 | 630 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 631 | { |
f2b2143e | 632 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 633 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 634 | |
8feceb67 | 635 | if (bss_conf->assoc) { |
c46917bb LR |
636 | ath_print(common, ATH_DBG_CONFIG, |
637 | "Bss Info ASSOC %d, bssid: %pM\n", | |
638 | bss_conf->aid, common->curbssid); | |
f078f209 | 639 | |
8feceb67 | 640 | /* New association, store aid */ |
1510718d | 641 | common->curaid = bss_conf->aid; |
f2b2143e | 642 | ath9k_hw_write_associd(ah); |
2664f201 SB |
643 | |
644 | /* | |
645 | * Request a re-configuration of Beacon related timers | |
646 | * on the receipt of the first Beacon frame (i.e., | |
647 | * after time sync with the AP). | |
648 | */ | |
1b04b930 | 649 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 650 | |
8feceb67 | 651 | /* Configure the beacon */ |
2c3db3d5 | 652 | ath_beacon_config(sc, vif); |
f078f209 | 653 | |
8feceb67 | 654 | /* Reset rssi stats */ |
22e66a4c | 655 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 656 | |
3d536acf | 657 | ath_start_ani(common); |
8feceb67 | 658 | } else { |
c46917bb | 659 | ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 660 | common->curaid = 0; |
f38faa31 | 661 | /* Stop ANI */ |
3d536acf | 662 | del_timer_sync(&common->ani.timer); |
f078f209 | 663 | } |
8feceb67 | 664 | } |
f078f209 | 665 | |
68a89116 | 666 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 667 | { |
cbe61d8a | 668 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 669 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 670 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 671 | int r; |
500c064d | 672 | |
3cbb5dd7 | 673 | ath9k_ps_wakeup(sc); |
93b1b37f | 674 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 675 | |
159cd468 VT |
676 | if (!ah->curchan) |
677 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
678 | ||
d2f5b3a6 | 679 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 680 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 681 | if (r) { |
c46917bb | 682 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 683 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
684 | "reset status %d\n", |
685 | channel->center_freq, r); | |
500c064d VT |
686 | } |
687 | spin_unlock_bh(&sc->sc_resetlock); | |
688 | ||
689 | ath_update_txpow(sc); | |
690 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
691 | ath_print(common, ATH_DBG_FATAL, |
692 | "Unable to restart recv logic\n"); | |
500c064d VT |
693 | return; |
694 | } | |
695 | ||
696 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 697 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
698 | |
699 | /* Re-Enable interrupts */ | |
3069168c | 700 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
701 | |
702 | /* Enable LED */ | |
08fc5c1b | 703 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 704 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 705 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 706 | |
68a89116 | 707 | ieee80211_wake_queues(hw); |
3cbb5dd7 | 708 | ath9k_ps_restore(sc); |
500c064d VT |
709 | } |
710 | ||
68a89116 | 711 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 712 | { |
cbe61d8a | 713 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 714 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 715 | int r; |
500c064d | 716 | |
3cbb5dd7 | 717 | ath9k_ps_wakeup(sc); |
68a89116 | 718 | ieee80211_stop_queues(hw); |
500c064d VT |
719 | |
720 | /* Disable LED */ | |
08fc5c1b VN |
721 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); |
722 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
500c064d VT |
723 | |
724 | /* Disable interrupts */ | |
725 | ath9k_hw_set_interrupts(ah, 0); | |
726 | ||
043a0405 | 727 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
500c064d VT |
728 | ath_stoprecv(sc); /* turn off frame recv */ |
729 | ath_flushrecv(sc); /* flush recv queue */ | |
730 | ||
159cd468 | 731 | if (!ah->curchan) |
68a89116 | 732 | ah->curchan = ath_get_curchannel(sc, hw); |
159cd468 | 733 | |
500c064d | 734 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 735 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 736 | if (r) { |
c46917bb | 737 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
f643e51d | 738 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
739 | "reset status %d\n", |
740 | channel->center_freq, r); | |
500c064d VT |
741 | } |
742 | spin_unlock_bh(&sc->sc_resetlock); | |
743 | ||
744 | ath9k_hw_phy_disable(ah); | |
93b1b37f | 745 | ath9k_hw_configpcipowersave(ah, 1, 1); |
3cbb5dd7 | 746 | ath9k_ps_restore(sc); |
9ecdef4b | 747 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
748 | } |
749 | ||
ff37e337 S |
750 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
751 | { | |
cbe61d8a | 752 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 753 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 754 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 755 | int r; |
ff37e337 | 756 | |
2ab81d4a S |
757 | /* Stop ANI */ |
758 | del_timer_sync(&common->ani.timer); | |
759 | ||
cc9c378a S |
760 | ieee80211_stop_queues(hw); |
761 | ||
ff37e337 | 762 | ath9k_hw_set_interrupts(ah, 0); |
043a0405 | 763 | ath_drain_all_txq(sc, retry_tx); |
ff37e337 S |
764 | ath_stoprecv(sc); |
765 | ath_flushrecv(sc); | |
766 | ||
767 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 768 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
ae8d2858 | 769 | if (r) |
c46917bb LR |
770 | ath_print(common, ATH_DBG_FATAL, |
771 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
772 | spin_unlock_bh(&sc->sc_resetlock); |
773 | ||
774 | if (ath_startrecv(sc) != 0) | |
c46917bb LR |
775 | ath_print(common, ATH_DBG_FATAL, |
776 | "Unable to start recv logic\n"); | |
ff37e337 S |
777 | |
778 | /* | |
779 | * We may be doing a reset in response to a request | |
780 | * that changes the channel so update any state that | |
781 | * might change as a result. | |
782 | */ | |
ce111bad | 783 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
784 | |
785 | ath_update_txpow(sc); | |
786 | ||
787 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 788 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 789 | |
3069168c | 790 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
791 | |
792 | if (retry_tx) { | |
793 | int i; | |
794 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
795 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
796 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
797 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
798 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
799 | } |
800 | } | |
801 | } | |
802 | ||
cc9c378a S |
803 | ieee80211_wake_queues(hw); |
804 | ||
2ab81d4a S |
805 | /* Start ANI */ |
806 | ath_start_ani(common); | |
807 | ||
ae8d2858 | 808 | return r; |
ff37e337 S |
809 | } |
810 | ||
ff37e337 S |
811 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) |
812 | { | |
813 | int qnum; | |
814 | ||
815 | switch (queue) { | |
816 | case 0: | |
1d2231e2 | 817 | qnum = sc->tx.hwq_map[WME_AC_VO]; |
ff37e337 S |
818 | break; |
819 | case 1: | |
1d2231e2 | 820 | qnum = sc->tx.hwq_map[WME_AC_VI]; |
ff37e337 S |
821 | break; |
822 | case 2: | |
1d2231e2 | 823 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
824 | break; |
825 | case 3: | |
1d2231e2 | 826 | qnum = sc->tx.hwq_map[WME_AC_BK]; |
ff37e337 S |
827 | break; |
828 | default: | |
1d2231e2 | 829 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
830 | break; |
831 | } | |
832 | ||
833 | return qnum; | |
834 | } | |
835 | ||
836 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
837 | { | |
838 | int qnum; | |
839 | ||
840 | switch (queue) { | |
1d2231e2 | 841 | case WME_AC_VO: |
ff37e337 S |
842 | qnum = 0; |
843 | break; | |
1d2231e2 | 844 | case WME_AC_VI: |
ff37e337 S |
845 | qnum = 1; |
846 | break; | |
1d2231e2 | 847 | case WME_AC_BE: |
ff37e337 S |
848 | qnum = 2; |
849 | break; | |
1d2231e2 | 850 | case WME_AC_BK: |
ff37e337 S |
851 | qnum = 3; |
852 | break; | |
853 | default: | |
854 | qnum = -1; | |
855 | break; | |
856 | } | |
857 | ||
858 | return qnum; | |
859 | } | |
860 | ||
5f8e077c LR |
861 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
862 | * this redundant data */ | |
0e2dedf9 JM |
863 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
864 | struct ath9k_channel *ichan) | |
5f8e077c | 865 | { |
5f8e077c LR |
866 | struct ieee80211_channel *chan = hw->conf.channel; |
867 | struct ieee80211_conf *conf = &hw->conf; | |
868 | ||
869 | ichan->channel = chan->center_freq; | |
870 | ichan->chan = chan; | |
871 | ||
872 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
873 | ichan->chanmode = CHANNEL_G; | |
8813262e | 874 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; |
5f8e077c LR |
875 | } else { |
876 | ichan->chanmode = CHANNEL_A; | |
877 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
878 | } | |
879 | ||
25c56eec | 880 | if (conf_is_ht(conf)) |
5f8e077c LR |
881 | ichan->chanmode = ath_get_extchanmode(sc, chan, |
882 | conf->channel_type); | |
5f8e077c LR |
883 | } |
884 | ||
ff37e337 S |
885 | /**********************/ |
886 | /* mac80211 callbacks */ | |
887 | /**********************/ | |
888 | ||
8feceb67 | 889 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 890 | { |
bce048d7 JM |
891 | struct ath_wiphy *aphy = hw->priv; |
892 | struct ath_softc *sc = aphy->sc; | |
af03abec | 893 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 894 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 895 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 896 | struct ath9k_channel *init_channel; |
82880a7c | 897 | int r; |
f078f209 | 898 | |
c46917bb LR |
899 | ath_print(common, ATH_DBG_CONFIG, |
900 | "Starting driver with initial channel: %d MHz\n", | |
901 | curchan->center_freq); | |
f078f209 | 902 | |
141b38b6 S |
903 | mutex_lock(&sc->mutex); |
904 | ||
9580a222 JM |
905 | if (ath9k_wiphy_started(sc)) { |
906 | if (sc->chan_idx == curchan->hw_value) { | |
907 | /* | |
908 | * Already on the operational channel, the new wiphy | |
909 | * can be marked active. | |
910 | */ | |
911 | aphy->state = ATH_WIPHY_ACTIVE; | |
912 | ieee80211_wake_queues(hw); | |
913 | } else { | |
914 | /* | |
915 | * Another wiphy is on another channel, start the new | |
916 | * wiphy in paused state. | |
917 | */ | |
918 | aphy->state = ATH_WIPHY_PAUSED; | |
919 | ieee80211_stop_queues(hw); | |
920 | } | |
921 | mutex_unlock(&sc->mutex); | |
922 | return 0; | |
923 | } | |
924 | aphy->state = ATH_WIPHY_ACTIVE; | |
925 | ||
8feceb67 | 926 | /* setup initial channel */ |
f078f209 | 927 | |
82880a7c | 928 | sc->chan_idx = curchan->hw_value; |
f078f209 | 929 | |
82880a7c | 930 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
931 | |
932 | /* Reset SERDES registers */ | |
af03abec | 933 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
934 | |
935 | /* | |
936 | * The basic interface to setting the hardware in a good | |
937 | * state is ``reset''. On return the hardware is known to | |
938 | * be powered up and with interrupts disabled. This must | |
939 | * be followed by initialization of the appropriate bits | |
940 | * and then setup of the interrupt mask. | |
941 | */ | |
942 | spin_lock_bh(&sc->sc_resetlock); | |
af03abec | 943 | r = ath9k_hw_reset(ah, init_channel, false); |
ae8d2858 | 944 | if (r) { |
c46917bb LR |
945 | ath_print(common, ATH_DBG_FATAL, |
946 | "Unable to reset hardware; reset status %d " | |
947 | "(freq %u MHz)\n", r, | |
948 | curchan->center_freq); | |
ff37e337 | 949 | spin_unlock_bh(&sc->sc_resetlock); |
141b38b6 | 950 | goto mutex_unlock; |
ff37e337 S |
951 | } |
952 | spin_unlock_bh(&sc->sc_resetlock); | |
953 | ||
954 | /* | |
955 | * This is needed only to setup initial state | |
956 | * but it's best done after a reset. | |
957 | */ | |
958 | ath_update_txpow(sc); | |
8feceb67 | 959 | |
ff37e337 S |
960 | /* |
961 | * Setup the hardware after reset: | |
962 | * The receive engine is set going. | |
963 | * Frame transmit is handled entirely | |
964 | * in the frame output path; there's nothing to do | |
965 | * here except setup the interrupt mask. | |
966 | */ | |
967 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
968 | ath_print(common, ATH_DBG_FATAL, |
969 | "Unable to start recv logic\n"); | |
141b38b6 S |
970 | r = -EIO; |
971 | goto mutex_unlock; | |
f078f209 | 972 | } |
8feceb67 | 973 | |
ff37e337 | 974 | /* Setup our intr mask. */ |
b5c80475 FF |
975 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
976 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
977 | ATH9K_INT_GLOBAL; | |
978 | ||
979 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
980 | ah->imask |= ATH9K_INT_RXHP | |
981 | ATH9K_INT_RXLP | | |
982 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
983 | else |
984 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 985 | |
af03abec | 986 | if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT) |
3069168c | 987 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 988 | |
af03abec | 989 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 990 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 991 | |
ce111bad | 992 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
993 | |
994 | sc->sc_flags &= ~SC_OP_INVALID; | |
995 | ||
996 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
997 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
998 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 999 | |
bce048d7 | 1000 | ieee80211_wake_queues(hw); |
ff37e337 | 1001 | |
42935eca | 1002 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1003 | |
766ec4a9 LR |
1004 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1005 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1006 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1007 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1008 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1009 | |
5bb12791 LR |
1010 | if (common->bus_ops->bt_coex_prep) |
1011 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1012 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1013 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1014 | } |
1015 | ||
141b38b6 S |
1016 | mutex_unlock: |
1017 | mutex_unlock(&sc->mutex); | |
1018 | ||
ae8d2858 | 1019 | return r; |
f078f209 LR |
1020 | } |
1021 | ||
8feceb67 VT |
1022 | static int ath9k_tx(struct ieee80211_hw *hw, |
1023 | struct sk_buff *skb) | |
f078f209 | 1024 | { |
528f0c6b | 1025 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
1026 | struct ath_wiphy *aphy = hw->priv; |
1027 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1028 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1029 | struct ath_tx_control txctl; |
1bc14880 BP |
1030 | int padpos, padsize; |
1031 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
84642d6b | 1032 | int qnum; |
528f0c6b | 1033 | |
8089cc47 | 1034 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
c46917bb LR |
1035 | ath_print(common, ATH_DBG_XMIT, |
1036 | "ath9k: %s: TX in unexpected wiphy state " | |
1037 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
ee166a0e JM |
1038 | goto exit; |
1039 | } | |
1040 | ||
96148326 | 1041 | if (sc->ps_enabled) { |
dc8c4585 JM |
1042 | /* |
1043 | * mac80211 does not set PM field for normal data frames, so we | |
1044 | * need to update that based on the current PS mode. | |
1045 | */ | |
1046 | if (ieee80211_is_data(hdr->frame_control) && | |
1047 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1048 | !ieee80211_has_pm(hdr->frame_control)) { | |
c46917bb LR |
1049 | ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " |
1050 | "while in PS mode\n"); | |
dc8c4585 JM |
1051 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1052 | } | |
1053 | } | |
1054 | ||
9a23f9ca JM |
1055 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1056 | /* | |
1057 | * We are using PS-Poll and mac80211 can request TX while in | |
1058 | * power save mode. Need to wake up hardware for the TX to be | |
1059 | * completed and if needed, also for RX of buffered frames. | |
1060 | */ | |
9a23f9ca | 1061 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1062 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1063 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1064 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
c46917bb LR |
1065 | ath_print(common, ATH_DBG_PS, |
1066 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1067 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1068 | } else { |
c46917bb LR |
1069 | ath_print(common, ATH_DBG_PS, |
1070 | "Wake up to complete TX\n"); | |
1b04b930 | 1071 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1072 | } |
1073 | /* | |
1074 | * The actual restore operation will happen only after | |
1075 | * the sc_flags bit is cleared. We are just dropping | |
1076 | * the ps_usecount here. | |
1077 | */ | |
1078 | ath9k_ps_restore(sc); | |
1079 | } | |
1080 | ||
528f0c6b | 1081 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 1082 | |
8feceb67 VT |
1083 | /* |
1084 | * As a temporary workaround, assign seq# here; this will likely need | |
1085 | * to be cleaned up to work better with Beacon transmission and virtual | |
1086 | * BSSes. | |
1087 | */ | |
1088 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
8feceb67 | 1089 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
b77f483f | 1090 | sc->tx.seq_no += 0x10; |
8feceb67 | 1091 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 1092 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 1093 | } |
f078f209 | 1094 | |
8feceb67 | 1095 | /* Add the padding after the header if this is not already done */ |
1bc14880 BP |
1096 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1097 | padsize = padpos & 3; | |
1098 | if (padsize && skb->len>padpos) { | |
8feceb67 VT |
1099 | if (skb_headroom(skb) < padsize) |
1100 | return -1; | |
1101 | skb_push(skb, padsize); | |
1bc14880 | 1102 | memmove(skb->data, skb->data + padsize, padpos); |
8feceb67 VT |
1103 | } |
1104 | ||
84642d6b FF |
1105 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
1106 | txctl.txq = &sc->tx.txq[qnum]; | |
528f0c6b | 1107 | |
c46917bb | 1108 | ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1109 | |
c52f33d0 | 1110 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1111 | ath_print(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1112 | goto exit; |
8feceb67 VT |
1113 | } |
1114 | ||
528f0c6b S |
1115 | return 0; |
1116 | exit: | |
1117 | dev_kfree_skb_any(skb); | |
8feceb67 | 1118 | return 0; |
f078f209 LR |
1119 | } |
1120 | ||
8feceb67 | 1121 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1122 | { |
bce048d7 JM |
1123 | struct ath_wiphy *aphy = hw->priv; |
1124 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1125 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1126 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1127 | |
4c483817 S |
1128 | mutex_lock(&sc->mutex); |
1129 | ||
9580a222 JM |
1130 | aphy->state = ATH_WIPHY_INACTIVE; |
1131 | ||
c94dbff7 LR |
1132 | cancel_delayed_work_sync(&sc->ath_led_blink_work); |
1133 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
1134 | ||
1135 | if (!sc->num_sec_wiphy) { | |
1136 | cancel_delayed_work_sync(&sc->wiphy_work); | |
1137 | cancel_work_sync(&sc->chan_work); | |
1138 | } | |
1139 | ||
9c84b797 | 1140 | if (sc->sc_flags & SC_OP_INVALID) { |
c46917bb | 1141 | ath_print(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1142 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1143 | return; |
1144 | } | |
8feceb67 | 1145 | |
9580a222 JM |
1146 | if (ath9k_wiphy_started(sc)) { |
1147 | mutex_unlock(&sc->mutex); | |
1148 | return; /* another wiphy still in use */ | |
1149 | } | |
1150 | ||
3867cf6a S |
1151 | /* Ensure HW is awake when we try to shut it down. */ |
1152 | ath9k_ps_wakeup(sc); | |
1153 | ||
766ec4a9 | 1154 | if (ah->btcoex_hw.enabled) { |
af03abec | 1155 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1156 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1157 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1158 | } |
1159 | ||
ff37e337 S |
1160 | /* make sure h/w will not generate any interrupt |
1161 | * before setting the invalid flag. */ | |
af03abec | 1162 | ath9k_hw_set_interrupts(ah, 0); |
ff37e337 S |
1163 | |
1164 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1165 | ath_drain_all_txq(sc, false); |
ff37e337 | 1166 | ath_stoprecv(sc); |
af03abec | 1167 | ath9k_hw_phy_disable(ah); |
ff37e337 | 1168 | } else |
b77f483f | 1169 | sc->rx.rxlink = NULL; |
ff37e337 | 1170 | |
ff37e337 | 1171 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1172 | ath9k_hw_disable(ah); |
1173 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
3867cf6a S |
1174 | ath9k_ps_restore(sc); |
1175 | ||
1176 | /* Finally, put the chip in FULL SLEEP mode */ | |
9ecdef4b | 1177 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
ff37e337 S |
1178 | |
1179 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1180 | |
141b38b6 S |
1181 | mutex_unlock(&sc->mutex); |
1182 | ||
c46917bb | 1183 | ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1184 | } |
1185 | ||
8feceb67 | 1186 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1187 | struct ieee80211_vif *vif) |
f078f209 | 1188 | { |
bce048d7 JM |
1189 | struct ath_wiphy *aphy = hw->priv; |
1190 | struct ath_softc *sc = aphy->sc; | |
3069168c PR |
1191 | struct ath_hw *ah = sc->sc_ah; |
1192 | struct ath_common *common = ath9k_hw_common(ah); | |
1ed32e4f | 1193 | struct ath_vif *avp = (void *)vif->drv_priv; |
d97809db | 1194 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 1195 | int ret = 0; |
8feceb67 | 1196 | |
141b38b6 S |
1197 | mutex_lock(&sc->mutex); |
1198 | ||
3069168c | 1199 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) && |
8ca21f01 JM |
1200 | sc->nvifs > 0) { |
1201 | ret = -ENOBUFS; | |
1202 | goto out; | |
1203 | } | |
1204 | ||
1ed32e4f | 1205 | switch (vif->type) { |
05c914fe | 1206 | case NL80211_IFTYPE_STATION: |
d97809db | 1207 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 1208 | break; |
05c914fe | 1209 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 1210 | case NL80211_IFTYPE_AP: |
9cb5412b | 1211 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
1212 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1213 | ret = -ENOBUFS; | |
1214 | goto out; | |
1215 | } | |
1ed32e4f | 1216 | ic_opmode = vif->type; |
f078f209 LR |
1217 | break; |
1218 | default: | |
c46917bb | 1219 | ath_print(common, ATH_DBG_FATAL, |
1ed32e4f | 1220 | "Interface type %d not yet supported\n", vif->type); |
2c3db3d5 JM |
1221 | ret = -EOPNOTSUPP; |
1222 | goto out; | |
f078f209 LR |
1223 | } |
1224 | ||
c46917bb LR |
1225 | ath_print(common, ATH_DBG_CONFIG, |
1226 | "Attach a VIF of type: %d\n", ic_opmode); | |
8feceb67 | 1227 | |
17d7904d | 1228 | /* Set the VIF opmode */ |
5640b08e S |
1229 | avp->av_opmode = ic_opmode; |
1230 | avp->av_bslot = -1; | |
1231 | ||
2c3db3d5 | 1232 | sc->nvifs++; |
8ca21f01 | 1233 | |
3069168c | 1234 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
8ca21f01 JM |
1235 | ath9k_set_bssid_mask(hw); |
1236 | ||
2c3db3d5 JM |
1237 | if (sc->nvifs > 1) |
1238 | goto out; /* skip global settings for secondary vif */ | |
1239 | ||
b238e90e | 1240 | if (ic_opmode == NL80211_IFTYPE_AP) { |
3069168c | 1241 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e S |
1242 | sc->sc_flags |= SC_OP_TSF_RESET; |
1243 | } | |
5640b08e | 1244 | |
5640b08e | 1245 | /* Set the device opmode */ |
3069168c | 1246 | ah->opmode = ic_opmode; |
5640b08e | 1247 | |
4e30ffa2 VN |
1248 | /* |
1249 | * Enable MIB interrupts when there are hardware phy counters. | |
1250 | * Note we only do this (at the moment) for station mode. | |
1251 | */ | |
1ed32e4f JB |
1252 | if ((vif->type == NL80211_IFTYPE_STATION) || |
1253 | (vif->type == NL80211_IFTYPE_ADHOC) || | |
1254 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
3448f912 LR |
1255 | if (ah->config.enable_ani) |
1256 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1257 | ah->imask |= ATH9K_INT_TSFOOR; |
4af9cf4f S |
1258 | } |
1259 | ||
3069168c | 1260 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1261 | |
1ed32e4f JB |
1262 | if (vif->type == NL80211_IFTYPE_AP || |
1263 | vif->type == NL80211_IFTYPE_ADHOC || | |
1264 | vif->type == NL80211_IFTYPE_MONITOR) | |
3d536acf | 1265 | ath_start_ani(common); |
6f255425 | 1266 | |
2c3db3d5 | 1267 | out: |
141b38b6 | 1268 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 1269 | return ret; |
f078f209 LR |
1270 | } |
1271 | ||
8feceb67 | 1272 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1273 | struct ieee80211_vif *vif) |
f078f209 | 1274 | { |
bce048d7 JM |
1275 | struct ath_wiphy *aphy = hw->priv; |
1276 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1277 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1ed32e4f | 1278 | struct ath_vif *avp = (void *)vif->drv_priv; |
2c3db3d5 | 1279 | int i; |
f078f209 | 1280 | |
c46917bb | 1281 | ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1282 | |
141b38b6 S |
1283 | mutex_lock(&sc->mutex); |
1284 | ||
6f255425 | 1285 | /* Stop ANI */ |
3d536acf | 1286 | del_timer_sync(&common->ani.timer); |
580f0b8a | 1287 | |
8feceb67 | 1288 | /* Reclaim beacon resources */ |
9cb5412b PE |
1289 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
1290 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
1291 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
5f70a88f | 1292 | ath9k_ps_wakeup(sc); |
b77f483f | 1293 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
5f70a88f | 1294 | ath9k_ps_restore(sc); |
580f0b8a | 1295 | } |
f078f209 | 1296 | |
74401773 | 1297 | ath_beacon_return(sc, avp); |
8feceb67 | 1298 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 1299 | |
2c3db3d5 | 1300 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
1ed32e4f | 1301 | if (sc->beacon.bslot[i] == vif) { |
2c3db3d5 JM |
1302 | printk(KERN_DEBUG "%s: vif had allocated beacon " |
1303 | "slot\n", __func__); | |
1304 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 1305 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
1306 | } |
1307 | } | |
1308 | ||
17d7904d | 1309 | sc->nvifs--; |
141b38b6 S |
1310 | |
1311 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1312 | } |
1313 | ||
3f7c5c10 SB |
1314 | void ath9k_enable_ps(struct ath_softc *sc) |
1315 | { | |
3069168c PR |
1316 | struct ath_hw *ah = sc->sc_ah; |
1317 | ||
3f7c5c10 | 1318 | sc->ps_enabled = true; |
3069168c PR |
1319 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1320 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1321 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1322 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1323 | } |
fdf76622 | 1324 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1325 | } |
3f7c5c10 SB |
1326 | } |
1327 | ||
e8975581 | 1328 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1329 | { |
bce048d7 JM |
1330 | struct ath_wiphy *aphy = hw->priv; |
1331 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1332 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8975581 | 1333 | struct ieee80211_conf *conf = &hw->conf; |
8782b41d | 1334 | struct ath_hw *ah = sc->sc_ah; |
194b7c13 | 1335 | bool disable_radio; |
f078f209 | 1336 | |
aa33de09 | 1337 | mutex_lock(&sc->mutex); |
141b38b6 | 1338 | |
194b7c13 LR |
1339 | /* |
1340 | * Leave this as the first check because we need to turn on the | |
1341 | * radio if it was disabled before prior to processing the rest | |
1342 | * of the changes. Likewise we must only disable the radio towards | |
1343 | * the end. | |
1344 | */ | |
64839170 | 1345 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
194b7c13 LR |
1346 | bool enable_radio; |
1347 | bool all_wiphys_idle; | |
1348 | bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); | |
64839170 LR |
1349 | |
1350 | spin_lock_bh(&sc->wiphy_lock); | |
1351 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
194b7c13 LR |
1352 | ath9k_set_wiphy_idle(aphy, idle); |
1353 | ||
11446011 | 1354 | enable_radio = (!idle && all_wiphys_idle); |
194b7c13 LR |
1355 | |
1356 | /* | |
1357 | * After we unlock here its possible another wiphy | |
1358 | * can be re-renabled so to account for that we will | |
1359 | * only disable the radio toward the end of this routine | |
1360 | * if by then all wiphys are still idle. | |
1361 | */ | |
64839170 LR |
1362 | spin_unlock_bh(&sc->wiphy_lock); |
1363 | ||
194b7c13 | 1364 | if (enable_radio) { |
1dbfd9d4 | 1365 | sc->ps_idle = false; |
68a89116 | 1366 | ath_radio_enable(sc, hw); |
c46917bb LR |
1367 | ath_print(common, ATH_DBG_CONFIG, |
1368 | "not-idle: enabling radio\n"); | |
64839170 LR |
1369 | } |
1370 | } | |
1371 | ||
e7824a50 LR |
1372 | /* |
1373 | * We just prepare to enable PS. We have to wait until our AP has | |
1374 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1375 | * those ACKs and end up retransmitting the same null data frames. | |
1376 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1377 | */ | |
3cbb5dd7 VN |
1378 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
1379 | if (conf->flags & IEEE80211_CONF_PS) { | |
1b04b930 | 1380 | sc->ps_flags |= PS_ENABLED; |
e7824a50 LR |
1381 | /* |
1382 | * At this point we know hardware has received an ACK | |
1383 | * of a previously sent null data frame. | |
1384 | */ | |
1b04b930 S |
1385 | if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) { |
1386 | sc->ps_flags &= ~PS_NULLFUNC_COMPLETED; | |
3f7c5c10 | 1387 | ath9k_enable_ps(sc); |
e7824a50 | 1388 | } |
3cbb5dd7 | 1389 | } else { |
96148326 | 1390 | sc->ps_enabled = false; |
1b04b930 S |
1391 | sc->ps_flags &= ~(PS_ENABLED | |
1392 | PS_NULLFUNC_COMPLETED); | |
9ecdef4b | 1393 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
8782b41d VN |
1394 | if (!(ah->caps.hw_caps & |
1395 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
1396 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
1b04b930 S |
1397 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | |
1398 | PS_WAIT_FOR_CAB | | |
1399 | PS_WAIT_FOR_PSPOLL_DATA | | |
1400 | PS_WAIT_FOR_TX_ACK); | |
3069168c PR |
1401 | if (ah->imask & ATH9K_INT_TIM_TIMER) { |
1402 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
8782b41d | 1403 | ath9k_hw_set_interrupts(sc->sc_ah, |
3069168c | 1404 | ah->imask); |
8782b41d | 1405 | } |
3cbb5dd7 VN |
1406 | } |
1407 | } | |
1408 | } | |
1409 | ||
199afd9d S |
1410 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1411 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
1412 | ath_print(common, ATH_DBG_CONFIG, | |
1413 | "HW opmode set to Monitor mode\n"); | |
1414 | sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; | |
1415 | } | |
1416 | } | |
1417 | ||
4797938c | 1418 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1419 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1420 | int pos = curchan->hw_value; |
ae5eb026 | 1421 | |
0e2dedf9 JM |
1422 | aphy->chan_idx = pos; |
1423 | aphy->chan_is_ht = conf_is_ht(conf); | |
1424 | ||
8089cc47 JM |
1425 | if (aphy->state == ATH_WIPHY_SCAN || |
1426 | aphy->state == ATH_WIPHY_ACTIVE) | |
1427 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
1428 | else { | |
1429 | /* | |
1430 | * Do not change operational channel based on a paused | |
1431 | * wiphy changes. | |
1432 | */ | |
1433 | goto skip_chan_change; | |
1434 | } | |
0e2dedf9 | 1435 | |
c46917bb LR |
1436 | ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1437 | curchan->center_freq); | |
f078f209 | 1438 | |
5f8e077c | 1439 | /* XXX: remove me eventualy */ |
0e2dedf9 | 1440 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 1441 | |
ecf70441 | 1442 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 1443 | |
0e2dedf9 | 1444 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
c46917bb LR |
1445 | ath_print(common, ATH_DBG_FATAL, |
1446 | "Unable to set channel\n"); | |
aa33de09 | 1447 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1448 | return -EINVAL; |
1449 | } | |
094d05dc | 1450 | } |
f078f209 | 1451 | |
8089cc47 | 1452 | skip_chan_change: |
c9f6a656 | 1453 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
17d7904d | 1454 | sc->config.txpowlimit = 2 * conf->power_level; |
c9f6a656 LR |
1455 | ath_update_txpow(sc); |
1456 | } | |
f078f209 | 1457 | |
194b7c13 LR |
1458 | spin_lock_bh(&sc->wiphy_lock); |
1459 | disable_radio = ath9k_all_wiphys_idle(sc); | |
1460 | spin_unlock_bh(&sc->wiphy_lock); | |
1461 | ||
64839170 | 1462 | if (disable_radio) { |
c46917bb | 1463 | ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
1dbfd9d4 | 1464 | sc->ps_idle = true; |
68a89116 | 1465 | ath_radio_disable(sc, hw); |
64839170 LR |
1466 | } |
1467 | ||
aa33de09 | 1468 | mutex_unlock(&sc->mutex); |
141b38b6 | 1469 | |
f078f209 LR |
1470 | return 0; |
1471 | } | |
1472 | ||
8feceb67 VT |
1473 | #define SUPPORTED_FILTERS \ |
1474 | (FIF_PROMISC_IN_BSS | \ | |
1475 | FIF_ALLMULTI | \ | |
1476 | FIF_CONTROL | \ | |
af6a3fc7 | 1477 | FIF_PSPOLL | \ |
8feceb67 VT |
1478 | FIF_OTHER_BSS | \ |
1479 | FIF_BCN_PRBRESP_PROMISC | \ | |
1480 | FIF_FCSFAIL) | |
c83be688 | 1481 | |
8feceb67 VT |
1482 | /* FIXME: sc->sc_full_reset ? */ |
1483 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1484 | unsigned int changed_flags, | |
1485 | unsigned int *total_flags, | |
3ac64bee | 1486 | u64 multicast) |
8feceb67 | 1487 | { |
bce048d7 JM |
1488 | struct ath_wiphy *aphy = hw->priv; |
1489 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1490 | u32 rfilt; |
f078f209 | 1491 | |
8feceb67 VT |
1492 | changed_flags &= SUPPORTED_FILTERS; |
1493 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1494 | |
b77f483f | 1495 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1496 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1497 | rfilt = ath_calcrxfilter(sc); |
1498 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1499 | ath9k_ps_restore(sc); |
f078f209 | 1500 | |
c46917bb LR |
1501 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1502 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1503 | } |
f078f209 | 1504 | |
4ca77860 JB |
1505 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1506 | struct ieee80211_vif *vif, | |
1507 | struct ieee80211_sta *sta) | |
8feceb67 | 1508 | { |
bce048d7 JM |
1509 | struct ath_wiphy *aphy = hw->priv; |
1510 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1511 | |
4ca77860 JB |
1512 | ath_node_attach(sc, sta); |
1513 | ||
1514 | return 0; | |
1515 | } | |
1516 | ||
1517 | static int ath9k_sta_remove(struct ieee80211_hw *hw, | |
1518 | struct ieee80211_vif *vif, | |
1519 | struct ieee80211_sta *sta) | |
1520 | { | |
1521 | struct ath_wiphy *aphy = hw->priv; | |
1522 | struct ath_softc *sc = aphy->sc; | |
1523 | ||
1524 | ath_node_detach(sc, sta); | |
1525 | ||
1526 | return 0; | |
f078f209 LR |
1527 | } |
1528 | ||
141b38b6 | 1529 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1530 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1531 | { |
bce048d7 JM |
1532 | struct ath_wiphy *aphy = hw->priv; |
1533 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1534 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 VT |
1535 | struct ath9k_tx_queue_info qi; |
1536 | int ret = 0, qnum; | |
f078f209 | 1537 | |
8feceb67 VT |
1538 | if (queue >= WME_NUM_AC) |
1539 | return 0; | |
f078f209 | 1540 | |
141b38b6 S |
1541 | mutex_lock(&sc->mutex); |
1542 | ||
1ffb0610 S |
1543 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1544 | ||
8feceb67 VT |
1545 | qi.tqi_aifs = params->aifs; |
1546 | qi.tqi_cwmin = params->cw_min; | |
1547 | qi.tqi_cwmax = params->cw_max; | |
1548 | qi.tqi_burstTime = params->txop; | |
1549 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 1550 | |
c46917bb LR |
1551 | ath_print(common, ATH_DBG_CONFIG, |
1552 | "Configure tx [queue/halq] [%d/%d], " | |
1553 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1554 | queue, qnum, params->aifs, params->cw_min, | |
1555 | params->cw_max, params->txop); | |
f078f209 | 1556 | |
8feceb67 VT |
1557 | ret = ath_txq_update(sc, qnum, &qi); |
1558 | if (ret) | |
c46917bb | 1559 | ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 1560 | |
94db2936 | 1561 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
1d2231e2 | 1562 | if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret) |
94db2936 VN |
1563 | ath_beaconq_config(sc); |
1564 | ||
141b38b6 S |
1565 | mutex_unlock(&sc->mutex); |
1566 | ||
8feceb67 VT |
1567 | return ret; |
1568 | } | |
f078f209 | 1569 | |
8feceb67 VT |
1570 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1571 | enum set_key_cmd cmd, | |
dc822b5d JB |
1572 | struct ieee80211_vif *vif, |
1573 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1574 | struct ieee80211_key_conf *key) |
1575 | { | |
bce048d7 JM |
1576 | struct ath_wiphy *aphy = hw->priv; |
1577 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1578 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1579 | int ret = 0; |
f078f209 | 1580 | |
b3bd89ce JM |
1581 | if (modparam_nohwcrypt) |
1582 | return -ENOSPC; | |
1583 | ||
141b38b6 | 1584 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1585 | ath9k_ps_wakeup(sc); |
c46917bb | 1586 | ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1587 | |
8feceb67 VT |
1588 | switch (cmd) { |
1589 | case SET_KEY: | |
1f03baad | 1590 | ret = ath9k_cmn_key_config(common, vif, sta, key); |
6ace2891 JM |
1591 | if (ret >= 0) { |
1592 | key->hw_key_idx = ret; | |
8feceb67 VT |
1593 | /* push IV and Michael MIC generation to stack */ |
1594 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
1595 | if (key->alg == ALG_TKIP) | |
1596 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
0ced0e17 JM |
1597 | if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP) |
1598 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; | |
6ace2891 | 1599 | ret = 0; |
8feceb67 VT |
1600 | } |
1601 | break; | |
1602 | case DISABLE_KEY: | |
1f03baad | 1603 | ath9k_cmn_key_delete(common, key); |
8feceb67 VT |
1604 | break; |
1605 | default: | |
1606 | ret = -EINVAL; | |
1607 | } | |
f078f209 | 1608 | |
3cbb5dd7 | 1609 | ath9k_ps_restore(sc); |
141b38b6 S |
1610 | mutex_unlock(&sc->mutex); |
1611 | ||
8feceb67 VT |
1612 | return ret; |
1613 | } | |
f078f209 | 1614 | |
8feceb67 VT |
1615 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1616 | struct ieee80211_vif *vif, | |
1617 | struct ieee80211_bss_conf *bss_conf, | |
1618 | u32 changed) | |
1619 | { | |
bce048d7 JM |
1620 | struct ath_wiphy *aphy = hw->priv; |
1621 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 | 1622 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1623 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1624 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1625 | int slottime; |
c6089ccc | 1626 | int error; |
f078f209 | 1627 | |
141b38b6 S |
1628 | mutex_lock(&sc->mutex); |
1629 | ||
c6089ccc S |
1630 | if (changed & BSS_CHANGED_BSSID) { |
1631 | /* Set BSSID */ | |
1632 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1633 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1634 | common->curaid = 0; |
f2b2143e | 1635 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1636 | |
c6089ccc S |
1637 | /* Set aggregation protection mode parameters */ |
1638 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1639 | |
c6089ccc S |
1640 | /* Only legacy IBSS for now */ |
1641 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
1642 | ath_update_chainmask(sc, 0); | |
2d0ddec5 | 1643 | |
c6089ccc S |
1644 | ath_print(common, ATH_DBG_CONFIG, |
1645 | "BSSID: %pM aid: 0x%x\n", | |
1646 | common->curbssid, common->curaid); | |
2d0ddec5 | 1647 | |
c6089ccc S |
1648 | /* need to reconfigure the beacon */ |
1649 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1650 | } | |
2d0ddec5 | 1651 | |
c6089ccc S |
1652 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1653 | if ((changed & BSS_CHANGED_BEACON) || | |
1654 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
1655 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1656 | error = ath_beacon_alloc(aphy, vif); | |
1657 | if (!error) | |
1658 | ath_beacon_config(sc, vif); | |
0005baf4 FF |
1659 | } |
1660 | ||
1661 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1662 | if (bss_conf->use_short_slot) | |
1663 | slottime = 9; | |
1664 | else | |
1665 | slottime = 20; | |
1666 | if (vif->type == NL80211_IFTYPE_AP) { | |
1667 | /* | |
1668 | * Defer update, so that connected stations can adjust | |
1669 | * their settings at the same time. | |
1670 | * See beacon.c for more details | |
1671 | */ | |
1672 | sc->beacon.slottime = slottime; | |
1673 | sc->beacon.updateslot = UPDATE; | |
1674 | } else { | |
1675 | ah->slottime = slottime; | |
1676 | ath9k_hw_init_global_settings(ah); | |
1677 | } | |
2d0ddec5 JB |
1678 | } |
1679 | ||
c6089ccc S |
1680 | /* Disable transmission of beacons */ |
1681 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) | |
1682 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 | 1683 | |
c6089ccc S |
1684 | if (changed & BSS_CHANGED_BEACON_INT) { |
1685 | sc->beacon_interval = bss_conf->beacon_int; | |
1686 | /* | |
1687 | * In case of AP mode, the HW TSF has to be reset | |
1688 | * when the beacon interval changes. | |
1689 | */ | |
1690 | if (vif->type == NL80211_IFTYPE_AP) { | |
1691 | sc->sc_flags |= SC_OP_TSF_RESET; | |
1692 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 JB |
1693 | error = ath_beacon_alloc(aphy, vif); |
1694 | if (!error) | |
1695 | ath_beacon_config(sc, vif); | |
c6089ccc S |
1696 | } else { |
1697 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1698 | } |
1699 | } | |
1700 | ||
8feceb67 | 1701 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
c46917bb LR |
1702 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1703 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1704 | if (bss_conf->use_short_preamble) |
1705 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1706 | else | |
1707 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1708 | } | |
f078f209 | 1709 | |
8feceb67 | 1710 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
c46917bb LR |
1711 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1712 | bss_conf->use_cts_prot); | |
8feceb67 VT |
1713 | if (bss_conf->use_cts_prot && |
1714 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1715 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1716 | else | |
1717 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1718 | } | |
f078f209 | 1719 | |
8feceb67 | 1720 | if (changed & BSS_CHANGED_ASSOC) { |
c46917bb | 1721 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 1722 | bss_conf->assoc); |
5640b08e | 1723 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 1724 | } |
141b38b6 S |
1725 | |
1726 | mutex_unlock(&sc->mutex); | |
8feceb67 | 1727 | } |
f078f209 | 1728 | |
8feceb67 VT |
1729 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
1730 | { | |
1731 | u64 tsf; | |
bce048d7 JM |
1732 | struct ath_wiphy *aphy = hw->priv; |
1733 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1734 | |
141b38b6 S |
1735 | mutex_lock(&sc->mutex); |
1736 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
1737 | mutex_unlock(&sc->mutex); | |
f078f209 | 1738 | |
8feceb67 VT |
1739 | return tsf; |
1740 | } | |
f078f209 | 1741 | |
3b5d665b AF |
1742 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
1743 | { | |
bce048d7 JM |
1744 | struct ath_wiphy *aphy = hw->priv; |
1745 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 1746 | |
141b38b6 S |
1747 | mutex_lock(&sc->mutex); |
1748 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
1749 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
1750 | } |
1751 | ||
8feceb67 VT |
1752 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
1753 | { | |
bce048d7 JM |
1754 | struct ath_wiphy *aphy = hw->priv; |
1755 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 1756 | |
141b38b6 | 1757 | mutex_lock(&sc->mutex); |
21526d57 LR |
1758 | |
1759 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1760 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1761 | ath9k_ps_restore(sc); |
1762 | ||
141b38b6 | 1763 | mutex_unlock(&sc->mutex); |
8feceb67 | 1764 | } |
f078f209 | 1765 | |
8feceb67 | 1766 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1767 | struct ieee80211_vif *vif, |
141b38b6 S |
1768 | enum ieee80211_ampdu_mlme_action action, |
1769 | struct ieee80211_sta *sta, | |
1770 | u16 tid, u16 *ssn) | |
8feceb67 | 1771 | { |
bce048d7 JM |
1772 | struct ath_wiphy *aphy = hw->priv; |
1773 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1774 | int ret = 0; |
f078f209 | 1775 | |
85ad181e JB |
1776 | local_bh_disable(); |
1777 | ||
8feceb67 VT |
1778 | switch (action) { |
1779 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
1780 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
1781 | ret = -ENOTSUPP; | |
8feceb67 VT |
1782 | break; |
1783 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1784 | break; |
1785 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1786 | ath9k_ps_wakeup(sc); |
f83da965 | 1787 | ath_tx_aggr_start(sc, sta, tid, ssn); |
c951ad35 | 1788 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1789 | ath9k_ps_restore(sc); |
8feceb67 VT |
1790 | break; |
1791 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 1792 | ath9k_ps_wakeup(sc); |
f83da965 | 1793 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 1794 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1795 | ath9k_ps_restore(sc); |
8feceb67 | 1796 | break; |
b1720231 | 1797 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1798 | ath9k_ps_wakeup(sc); |
8469cdef | 1799 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1800 | ath9k_ps_restore(sc); |
8469cdef | 1801 | break; |
8feceb67 | 1802 | default: |
c46917bb LR |
1803 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1804 | "Unknown AMPDU action\n"); | |
8feceb67 VT |
1805 | } |
1806 | ||
85ad181e JB |
1807 | local_bh_enable(); |
1808 | ||
8feceb67 | 1809 | return ret; |
f078f209 LR |
1810 | } |
1811 | ||
62dad5b0 BP |
1812 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1813 | struct survey_info *survey) | |
1814 | { | |
1815 | struct ath_wiphy *aphy = hw->priv; | |
1816 | struct ath_softc *sc = aphy->sc; | |
1817 | struct ath_hw *ah = sc->sc_ah; | |
1818 | struct ath_common *common = ath9k_hw_common(ah); | |
1819 | struct ieee80211_conf *conf = &hw->conf; | |
1820 | ||
1821 | if (idx != 0) | |
1822 | return -ENOENT; | |
1823 | ||
1824 | survey->channel = conf->channel; | |
1825 | survey->filled = SURVEY_INFO_NOISE_DBM; | |
1826 | survey->noise = common->ani.noise_floor; | |
1827 | ||
1828 | return 0; | |
1829 | } | |
1830 | ||
0c98de65 S |
1831 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
1832 | { | |
bce048d7 JM |
1833 | struct ath_wiphy *aphy = hw->priv; |
1834 | struct ath_softc *sc = aphy->sc; | |
05c78d6d | 1835 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
0c98de65 | 1836 | |
3d832611 | 1837 | mutex_lock(&sc->mutex); |
8089cc47 JM |
1838 | if (ath9k_wiphy_scanning(sc)) { |
1839 | printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the " | |
1840 | "same time\n"); | |
1841 | /* | |
1842 | * Do not allow the concurrent scanning state for now. This | |
1843 | * could be improved with scanning control moved into ath9k. | |
1844 | */ | |
3d832611 | 1845 | mutex_unlock(&sc->mutex); |
8089cc47 JM |
1846 | return; |
1847 | } | |
1848 | ||
1849 | aphy->state = ATH_WIPHY_SCAN; | |
1850 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
0c98de65 | 1851 | sc->sc_flags |= SC_OP_SCANNING; |
05c78d6d | 1852 | del_timer_sync(&common->ani.timer); |
b6ce5c33 | 1853 | cancel_delayed_work_sync(&sc->tx_complete_work); |
3d832611 | 1854 | mutex_unlock(&sc->mutex); |
0c98de65 S |
1855 | } |
1856 | ||
1857 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) | |
1858 | { | |
bce048d7 JM |
1859 | struct ath_wiphy *aphy = hw->priv; |
1860 | struct ath_softc *sc = aphy->sc; | |
05c78d6d | 1861 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
0c98de65 | 1862 | |
3d832611 | 1863 | mutex_lock(&sc->mutex); |
8089cc47 | 1864 | aphy->state = ATH_WIPHY_ACTIVE; |
0c98de65 | 1865 | sc->sc_flags &= ~SC_OP_SCANNING; |
9c07a777 | 1866 | sc->sc_flags |= SC_OP_FULL_RESET; |
05c78d6d | 1867 | ath_start_ani(common); |
b6ce5c33 | 1868 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
d0bec342 | 1869 | ath_beacon_config(sc, NULL); |
3d832611 | 1870 | mutex_unlock(&sc->mutex); |
0c98de65 S |
1871 | } |
1872 | ||
e239d859 FF |
1873 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
1874 | { | |
1875 | struct ath_wiphy *aphy = hw->priv; | |
1876 | struct ath_softc *sc = aphy->sc; | |
1877 | struct ath_hw *ah = sc->sc_ah; | |
1878 | ||
1879 | mutex_lock(&sc->mutex); | |
1880 | ah->coverage_class = coverage_class; | |
1881 | ath9k_hw_init_global_settings(ah); | |
1882 | mutex_unlock(&sc->mutex); | |
1883 | } | |
1884 | ||
6baff7f9 | 1885 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
1886 | .tx = ath9k_tx, |
1887 | .start = ath9k_start, | |
1888 | .stop = ath9k_stop, | |
1889 | .add_interface = ath9k_add_interface, | |
1890 | .remove_interface = ath9k_remove_interface, | |
1891 | .config = ath9k_config, | |
8feceb67 | 1892 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
1893 | .sta_add = ath9k_sta_add, |
1894 | .sta_remove = ath9k_sta_remove, | |
8feceb67 | 1895 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 1896 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 1897 | .set_key = ath9k_set_key, |
8feceb67 | 1898 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 1899 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 1900 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 1901 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 1902 | .get_survey = ath9k_get_survey, |
0c98de65 S |
1903 | .sw_scan_start = ath9k_sw_scan_start, |
1904 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 1905 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 1906 | .set_coverage_class = ath9k_set_coverage_class, |
8feceb67 | 1907 | }; |