mac80211_hwsim: convert to new station add/remove callbacks
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
ce111bad
LR
21static void ath_cache_conf_rate(struct ath_softc *sc,
22 struct ieee80211_conf *conf)
ff37e337 23{
030bb495
LR
24 switch (conf->channel->band) {
25 case IEEE80211_BAND_2GHZ:
26 if (conf_is_ht20(conf))
545750d3 27 sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
030bb495 28 else if (conf_is_ht40_minus(conf))
545750d3 29 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
030bb495 30 else if (conf_is_ht40_plus(conf))
545750d3 31 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
96742256 32 else
545750d3 33 sc->cur_rate_mode = ATH9K_MODE_11G;
030bb495
LR
34 break;
35 case IEEE80211_BAND_5GHZ:
36 if (conf_is_ht20(conf))
545750d3 37 sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
030bb495 38 else if (conf_is_ht40_minus(conf))
545750d3 39 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
030bb495 40 else if (conf_is_ht40_plus(conf))
545750d3 41 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
030bb495 42 else
545750d3 43 sc->cur_rate_mode = ATH9K_MODE_11A;
030bb495
LR
44 break;
45 default:
ce111bad 46 BUG_ON(1);
030bb495
LR
47 break;
48 }
ff37e337
S
49}
50
51static void ath_update_txpow(struct ath_softc *sc)
52{
cbe61d8a 53 struct ath_hw *ah = sc->sc_ah;
ff37e337
S
54 u32 txpow;
55
17d7904d
S
56 if (sc->curtxpow != sc->config.txpowlimit) {
57 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S
58 /* read back in case value is clamped */
59 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 60 sc->curtxpow = txpow;
ff37e337
S
61 }
62}
63
64static u8 parse_mpdudensity(u8 mpdudensity)
65{
66 /*
67 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
68 * 0 for no restriction
69 * 1 for 1/4 us
70 * 2 for 1/2 us
71 * 3 for 1 us
72 * 4 for 2 us
73 * 5 for 4 us
74 * 6 for 8 us
75 * 7 for 16 us
76 */
77 switch (mpdudensity) {
78 case 0:
79 return 0;
80 case 1:
81 case 2:
82 case 3:
83 /* Our lower layer calculations limit our precision to
84 1 microsecond */
85 return 1;
86 case 4:
87 return 2;
88 case 5:
89 return 4;
90 case 6:
91 return 8;
92 case 7:
93 return 16;
94 default:
95 return 0;
96 }
97}
98
82880a7c
VT
99static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
100 struct ieee80211_hw *hw)
101{
102 struct ieee80211_channel *curchan = hw->conf.channel;
103 struct ath9k_channel *channel;
104 u8 chan_idx;
105
106 chan_idx = curchan->hw_value;
107 channel = &sc->sc_ah->channels[chan_idx];
108 ath9k_update_ichannel(sc, hw, channel);
109 return channel;
110}
111
55624204 112bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
113{
114 unsigned long flags;
115 bool ret;
116
9ecdef4b
LR
117 spin_lock_irqsave(&sc->sc_pm_lock, flags);
118 ret = ath9k_hw_setpower(sc->sc_ah, mode);
119 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
120
121 return ret;
122}
123
a91d75ae
LR
124void ath9k_ps_wakeup(struct ath_softc *sc)
125{
126 unsigned long flags;
127
128 spin_lock_irqsave(&sc->sc_pm_lock, flags);
129 if (++sc->ps_usecount != 1)
130 goto unlock;
131
9ecdef4b 132 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae
LR
133
134 unlock:
135 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
136}
137
138void ath9k_ps_restore(struct ath_softc *sc)
139{
140 unsigned long flags;
141
142 spin_lock_irqsave(&sc->sc_pm_lock, flags);
143 if (--sc->ps_usecount != 0)
144 goto unlock;
145
1dbfd9d4
VN
146 if (sc->ps_idle)
147 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
148 else if (sc->ps_enabled &&
149 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
150 PS_WAIT_FOR_CAB |
151 PS_WAIT_FOR_PSPOLL_DATA |
152 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 153 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
154
155 unlock:
156 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
157}
158
ff37e337
S
159/*
160 * Set/change channels. If the channel is really being changed, it's done
161 * by reseting the chip. To accomplish this we must first cleanup any pending
162 * DMA, then restart stuff.
163*/
0e2dedf9
JM
164int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
165 struct ath9k_channel *hchan)
ff37e337 166{
cbe61d8a 167 struct ath_hw *ah = sc->sc_ah;
c46917bb 168 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 169 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 170 bool fastcc = true, stopped;
ae8d2858
LR
171 struct ieee80211_channel *channel = hw->conf.channel;
172 int r;
ff37e337
S
173
174 if (sc->sc_flags & SC_OP_INVALID)
175 return -EIO;
176
3cbb5dd7
VN
177 ath9k_ps_wakeup(sc);
178
c0d7c7af
LR
179 /*
180 * This is only performed if the channel settings have
181 * actually changed.
182 *
183 * To switch channels clear any pending DMA operations;
184 * wait long enough for the RX fifo to drain, reset the
185 * hardware at the new frequency, and then re-enable
186 * the relevant bits of the h/w.
187 */
188 ath9k_hw_set_interrupts(ah, 0);
043a0405 189 ath_drain_all_txq(sc, false);
c0d7c7af 190 stopped = ath_stoprecv(sc);
ff37e337 191
c0d7c7af
LR
192 /* XXX: do not flush receive queue here. We don't want
193 * to flush data frames already in queue because of
194 * changing channel. */
ff37e337 195
c0d7c7af
LR
196 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
197 fastcc = false;
198
c46917bb 199 ath_print(common, ATH_DBG_CONFIG,
25c56eec 200 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
c46917bb 201 sc->sc_ah->curchan->channel,
25c56eec 202 channel->center_freq, conf_is_ht40(conf));
ff37e337 203
c0d7c7af
LR
204 spin_lock_bh(&sc->sc_resetlock);
205
206 r = ath9k_hw_reset(ah, hchan, fastcc);
207 if (r) {
c46917bb 208 ath_print(common, ATH_DBG_FATAL,
f643e51d 209 "Unable to reset channel (%u MHz), "
c46917bb
LR
210 "reset status %d\n",
211 channel->center_freq, r);
c0d7c7af 212 spin_unlock_bh(&sc->sc_resetlock);
3989279c 213 goto ps_restore;
ff37e337 214 }
c0d7c7af
LR
215 spin_unlock_bh(&sc->sc_resetlock);
216
c0d7c7af
LR
217 sc->sc_flags &= ~SC_OP_FULL_RESET;
218
219 if (ath_startrecv(sc) != 0) {
c46917bb
LR
220 ath_print(common, ATH_DBG_FATAL,
221 "Unable to restart recv logic\n");
3989279c
GJ
222 r = -EIO;
223 goto ps_restore;
c0d7c7af
LR
224 }
225
226 ath_cache_conf_rate(sc, &hw->conf);
227 ath_update_txpow(sc);
17d7904d 228 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ
229
230 ps_restore:
3cbb5dd7 231 ath9k_ps_restore(sc);
3989279c 232 return r;
ff37e337
S
233}
234
235/*
236 * This routine performs the periodic noise floor calibration function
237 * that is used to adjust and optimize the chip performance. This
238 * takes environmental changes (location, temperature) into account.
239 * When the task is complete, it reschedules itself depending on the
240 * appropriate interval that was calculated.
241 */
55624204 242void ath_ani_calibrate(unsigned long data)
ff37e337 243{
20977d3e
S
244 struct ath_softc *sc = (struct ath_softc *)data;
245 struct ath_hw *ah = sc->sc_ah;
c46917bb 246 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
247 bool longcal = false;
248 bool shortcal = false;
249 bool aniflag = false;
250 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 251 u32 cal_interval, short_cal_interval;
ff37e337 252
20977d3e
S
253 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
254 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 255
1ffc1c61
JM
256 /* Only calibrate if awake */
257 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
258 goto set_timer;
259
260 ath9k_ps_wakeup(sc);
261
ff37e337 262 /* Long calibration runs independently of short calibration. */
3d536acf 263 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 264 longcal = true;
c46917bb 265 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 266 common->ani.longcal_timer = timestamp;
ff37e337
S
267 }
268
17d7904d 269 /* Short calibration applies only while caldone is false */
3d536acf
LR
270 if (!common->ani.caldone) {
271 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 272 shortcal = true;
c46917bb
LR
273 ath_print(common, ATH_DBG_ANI,
274 "shortcal @%lu\n", jiffies);
3d536acf
LR
275 common->ani.shortcal_timer = timestamp;
276 common->ani.resetcal_timer = timestamp;
ff37e337
S
277 }
278 } else {
3d536acf 279 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 280 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
281 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
282 if (common->ani.caldone)
283 common->ani.resetcal_timer = timestamp;
ff37e337
S
284 }
285 }
286
287 /* Verify whether we must check ANI */
3d536acf 288 if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 289 aniflag = true;
3d536acf 290 common->ani.checkani_timer = timestamp;
ff37e337
S
291 }
292
293 /* Skip all processing if there's nothing to do. */
294 if (longcal || shortcal || aniflag) {
295 /* Call ANI routine if necessary */
296 if (aniflag)
22e66a4c 297 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S
298
299 /* Perform calibration if necessary */
300 if (longcal || shortcal) {
3d536acf 301 common->ani.caldone =
43c27613
LR
302 ath9k_hw_calibrate(ah,
303 ah->curchan,
304 common->rx_chainmask,
305 longcal);
379f0440
S
306
307 if (longcal)
3d536acf 308 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
379f0440
S
309 ah->curchan);
310
c46917bb
LR
311 ath_print(common, ATH_DBG_ANI,
312 " calibrate chan %u/%x nf: %d\n",
313 ah->curchan->channel,
314 ah->curchan->channelFlags,
3d536acf 315 common->ani.noise_floor);
ff37e337
S
316 }
317 }
318
1ffc1c61
JM
319 ath9k_ps_restore(sc);
320
20977d3e 321set_timer:
ff37e337
S
322 /*
323 * Set timer interval based on previous results.
324 * The interval must be the shortest necessary to satisfy ANI,
325 * short calibration and long calibration.
326 */
aac9207e 327 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 328 if (sc->sc_ah->config.enable_ani)
aac9207e 329 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
3d536acf 330 if (!common->ani.caldone)
20977d3e 331 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 332
3d536acf 333 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S
334}
335
3d536acf 336static void ath_start_ani(struct ath_common *common)
415f738e
S
337{
338 unsigned long timestamp = jiffies_to_msecs(jiffies);
339
3d536acf
LR
340 common->ani.longcal_timer = timestamp;
341 common->ani.shortcal_timer = timestamp;
342 common->ani.checkani_timer = timestamp;
415f738e 343
3d536acf 344 mod_timer(&common->ani.timer,
415f738e
S
345 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
346}
347
ff37e337
S
348/*
349 * Update tx/rx chainmask. For legacy association,
350 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT
351 * the chainmask configuration, for bt coexistence, use
352 * the chainmask configuration even in legacy mode.
ff37e337 353 */
0e2dedf9 354void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 355{
af03abec 356 struct ath_hw *ah = sc->sc_ah;
43c27613 357 struct ath_common *common = ath9k_hw_common(ah);
af03abec 358
3d832611 359 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
766ec4a9 360 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
43c27613
LR
361 common->tx_chainmask = ah->caps.tx_chainmask;
362 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337 363 } else {
43c27613
LR
364 common->tx_chainmask = 1;
365 common->rx_chainmask = 1;
ff37e337
S
366 }
367
43c27613 368 ath_print(common, ATH_DBG_CONFIG,
c46917bb 369 "tx chmask: %d, rx chmask: %d\n",
43c27613
LR
370 common->tx_chainmask,
371 common->rx_chainmask);
ff37e337
S
372}
373
374static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
375{
376 struct ath_node *an;
377
378 an = (struct ath_node *)sta->drv_priv;
379
87792efc 380 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 381 ath_tx_node_init(sc, an);
9e98ac65 382 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
383 sta->ht_cap.ampdu_factor);
384 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 385 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 386 }
ff37e337
S
387}
388
389static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
390{
391 struct ath_node *an = (struct ath_node *)sta->drv_priv;
392
393 if (sc->sc_flags & SC_OP_TXAGGR)
394 ath_tx_node_cleanup(sc, an);
395}
396
55624204 397void ath9k_tasklet(unsigned long data)
ff37e337
S
398{
399 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 400 struct ath_hw *ah = sc->sc_ah;
c46917bb 401 struct ath_common *common = ath9k_hw_common(ah);
af03abec 402
17d7904d 403 u32 status = sc->intrstatus;
ff37e337 404
153e080d
VT
405 ath9k_ps_wakeup(sc);
406
ff37e337 407 if (status & ATH9K_INT_FATAL) {
ff37e337 408 ath_reset(sc, false);
153e080d 409 ath9k_ps_restore(sc);
ff37e337 410 return;
063d8be3 411 }
ff37e337 412
063d8be3
S
413 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
414 spin_lock_bh(&sc->rx.rxflushlock);
415 ath_rx_tasklet(sc, 0);
416 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S
417 }
418
063d8be3
S
419 if (status & ATH9K_INT_TX)
420 ath_tx_tasklet(sc);
421
96148326 422 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM
423 /*
424 * TSF sync does not look correct; remain awake to sync with
425 * the next Beacon.
426 */
c46917bb
LR
427 ath_print(common, ATH_DBG_PS,
428 "TSFOOR - Sync with next Beacon\n");
1b04b930 429 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
54ce846e
JM
430 }
431
766ec4a9 432 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
433 if (status & ATH9K_INT_GENTIMER)
434 ath_gen_timer_isr(sc->sc_ah);
435
ff37e337 436 /* re-enable hardware interrupt */
af03abec 437 ath9k_hw_set_interrupts(ah, sc->imask);
153e080d 438 ath9k_ps_restore(sc);
ff37e337
S
439}
440
6baff7f9 441irqreturn_t ath_isr(int irq, void *dev)
ff37e337 442{
063d8be3
S
443#define SCHED_INTR ( \
444 ATH9K_INT_FATAL | \
445 ATH9K_INT_RXORN | \
446 ATH9K_INT_RXEOL | \
447 ATH9K_INT_RX | \
448 ATH9K_INT_TX | \
449 ATH9K_INT_BMISS | \
450 ATH9K_INT_CST | \
ebb8e1d7
VT
451 ATH9K_INT_TSFOOR | \
452 ATH9K_INT_GENTIMER)
063d8be3 453
ff37e337 454 struct ath_softc *sc = dev;
cbe61d8a 455 struct ath_hw *ah = sc->sc_ah;
ff37e337
S
456 enum ath9k_int status;
457 bool sched = false;
458
063d8be3
S
459 /*
460 * The hardware is not ready/present, don't
461 * touch anything. Note this can happen early
462 * on if the IRQ is shared.
463 */
464 if (sc->sc_flags & SC_OP_INVALID)
465 return IRQ_NONE;
ff37e337 466
063d8be3
S
467
468 /* shared irq, not for us */
469
153e080d 470 if (!ath9k_hw_intrpend(ah))
063d8be3 471 return IRQ_NONE;
063d8be3
S
472
473 /*
474 * Figure out the reason(s) for the interrupt. Note
475 * that the hal returns a pseudo-ISR that may include
476 * bits we haven't explicitly enabled so we mask the
477 * value to insure we only process bits we requested.
478 */
479 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
480 status &= sc->imask; /* discard unasked-for bits */
ff37e337 481
063d8be3
S
482 /*
483 * If there are no status bits set, then this interrupt was not
484 * for me (should have been caught above).
485 */
153e080d 486 if (!status)
063d8be3 487 return IRQ_NONE;
ff37e337 488
063d8be3
S
489 /* Cache the status */
490 sc->intrstatus = status;
491
492 if (status & SCHED_INTR)
493 sched = true;
494
495 /*
496 * If a FATAL or RXORN interrupt is received, we have to reset the
497 * chip immediately.
498 */
499 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
500 goto chip_reset;
501
502 if (status & ATH9K_INT_SWBA)
503 tasklet_schedule(&sc->bcon_tasklet);
504
505 if (status & ATH9K_INT_TXURN)
506 ath9k_hw_updatetxtriglevel(ah, true);
507
508 if (status & ATH9K_INT_MIB) {
ff37e337 509 /*
063d8be3
S
510 * Disable interrupts until we service the MIB
511 * interrupt; otherwise it will continue to
512 * fire.
ff37e337 513 */
063d8be3
S
514 ath9k_hw_set_interrupts(ah, 0);
515 /*
516 * Let the hal handle the event. We assume
517 * it will clear whatever condition caused
518 * the interrupt.
519 */
22e66a4c 520 ath9k_hw_procmibevent(ah);
063d8be3
S
521 ath9k_hw_set_interrupts(ah, sc->imask);
522 }
ff37e337 523
153e080d
VT
524 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
525 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S
526 /* Clear RxAbort bit so that we can
527 * receive frames */
9ecdef4b 528 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 529 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 530 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 531 }
063d8be3
S
532
533chip_reset:
ff37e337 534
817e11de
S
535 ath_debug_stat_interrupt(sc, status);
536
ff37e337
S
537 if (sched) {
538 /* turn off every interrupt except SWBA */
17d7904d 539 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S
540 tasklet_schedule(&sc->intr_tq);
541 }
542
543 return IRQ_HANDLED;
063d8be3
S
544
545#undef SCHED_INTR
ff37e337
S
546}
547
f078f209 548static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 549 struct ieee80211_channel *chan,
094d05dc 550 enum nl80211_channel_type channel_type)
f078f209
LR
551{
552 u32 chanmode = 0;
f078f209
LR
553
554 switch (chan->band) {
555 case IEEE80211_BAND_2GHZ:
094d05dc
S
556 switch(channel_type) {
557 case NL80211_CHAN_NO_HT:
558 case NL80211_CHAN_HT20:
f078f209 559 chanmode = CHANNEL_G_HT20;
094d05dc
S
560 break;
561 case NL80211_CHAN_HT40PLUS:
f078f209 562 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S
563 break;
564 case NL80211_CHAN_HT40MINUS:
f078f209 565 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S
566 break;
567 }
f078f209
LR
568 break;
569 case IEEE80211_BAND_5GHZ:
094d05dc
S
570 switch(channel_type) {
571 case NL80211_CHAN_NO_HT:
572 case NL80211_CHAN_HT20:
f078f209 573 chanmode = CHANNEL_A_HT20;
094d05dc
S
574 break;
575 case NL80211_CHAN_HT40PLUS:
f078f209 576 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S
577 break;
578 case NL80211_CHAN_HT40MINUS:
f078f209 579 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S
580 break;
581 }
f078f209
LR
582 break;
583 default:
584 break;
585 }
586
587 return chanmode;
588}
589
7e86c104 590static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
3f53dd64
JM
591 struct ath9k_keyval *hk, const u8 *addr,
592 bool authenticator)
f078f209 593{
7e86c104 594 struct ath_hw *ah = common->ah;
6ace2891
JM
595 const u8 *key_rxmic;
596 const u8 *key_txmic;
f078f209 597
6ace2891
JM
598 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
599 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR
600
601 if (addr == NULL) {
d216aaa6
JM
602 /*
603 * Group key installation - only two key cache entries are used
604 * regardless of splitmic capability since group key is only
605 * used either for TX or RX.
606 */
3f53dd64
JM
607 if (authenticator) {
608 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
609 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
610 } else {
611 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
612 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
613 }
7e86c104 614 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
f078f209 615 }
7e86c104 616 if (!common->splitmic) {
d216aaa6 617 /* TX and RX keys share the same key cache entry. */
f078f209
LR
618 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
619 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
7e86c104 620 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
f078f209 621 }
d216aaa6
JM
622
623 /* Separate key cache entries for TX and RX */
624
625 /* TX key goes at first index, RX key at +32. */
f078f209 626 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
7e86c104 627 if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
d216aaa6 628 /* TX MIC entry failed. No need to proceed further */
7e86c104 629 ath_print(common, ATH_DBG_FATAL,
c46917bb 630 "Setting TX MIC Key Failed\n");
f078f209
LR
631 return 0;
632 }
633
634 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
635 /* XXX delete tx key on failure? */
7e86c104 636 return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
6ace2891
JM
637}
638
7e86c104 639static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
6ace2891
JM
640{
641 int i;
642
7e86c104
LR
643 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
644 if (test_bit(i, common->keymap) ||
645 test_bit(i + 64, common->keymap))
6ace2891 646 continue; /* At least one part of TKIP key allocated */
7e86c104
LR
647 if (common->splitmic &&
648 (test_bit(i + 32, common->keymap) ||
649 test_bit(i + 64 + 32, common->keymap)))
6ace2891
JM
650 continue; /* At least one part of TKIP key allocated */
651
652 /* Found a free slot for a TKIP key */
653 return i;
654 }
655 return -1;
656}
657
7e86c104 658static int ath_reserve_key_cache_slot(struct ath_common *common)
6ace2891
JM
659{
660 int i;
661
662 /* First, try to find slots that would not be available for TKIP. */
7e86c104
LR
663 if (common->splitmic) {
664 for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
665 if (!test_bit(i, common->keymap) &&
666 (test_bit(i + 32, common->keymap) ||
667 test_bit(i + 64, common->keymap) ||
668 test_bit(i + 64 + 32, common->keymap)))
6ace2891 669 return i;
7e86c104
LR
670 if (!test_bit(i + 32, common->keymap) &&
671 (test_bit(i, common->keymap) ||
672 test_bit(i + 64, common->keymap) ||
673 test_bit(i + 64 + 32, common->keymap)))
6ace2891 674 return i + 32;
7e86c104
LR
675 if (!test_bit(i + 64, common->keymap) &&
676 (test_bit(i , common->keymap) ||
677 test_bit(i + 32, common->keymap) ||
678 test_bit(i + 64 + 32, common->keymap)))
ea612132 679 return i + 64;
7e86c104
LR
680 if (!test_bit(i + 64 + 32, common->keymap) &&
681 (test_bit(i, common->keymap) ||
682 test_bit(i + 32, common->keymap) ||
683 test_bit(i + 64, common->keymap)))
ea612132 684 return i + 64 + 32;
6ace2891
JM
685 }
686 } else {
7e86c104
LR
687 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
688 if (!test_bit(i, common->keymap) &&
689 test_bit(i + 64, common->keymap))
6ace2891 690 return i;
7e86c104
LR
691 if (test_bit(i, common->keymap) &&
692 !test_bit(i + 64, common->keymap))
6ace2891
JM
693 return i + 64;
694 }
695 }
696
697 /* No partially used TKIP slots, pick any available slot */
7e86c104 698 for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
be2864cf
JM
699 /* Do not allow slots that could be needed for TKIP group keys
700 * to be used. This limitation could be removed if we know that
701 * TKIP will not be used. */
702 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
703 continue;
7e86c104 704 if (common->splitmic) {
be2864cf
JM
705 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
706 continue;
707 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
708 continue;
709 }
710
7e86c104 711 if (!test_bit(i, common->keymap))
6ace2891
JM
712 return i; /* Found a free slot for a key */
713 }
714
715 /* No free slot found */
716 return -1;
f078f209
LR
717}
718
7e86c104 719static int ath_key_config(struct ath_common *common,
3f53dd64 720 struct ieee80211_vif *vif,
dc822b5d 721 struct ieee80211_sta *sta,
f078f209
LR
722 struct ieee80211_key_conf *key)
723{
7e86c104 724 struct ath_hw *ah = common->ah;
f078f209
LR
725 struct ath9k_keyval hk;
726 const u8 *mac = NULL;
727 int ret = 0;
6ace2891 728 int idx;
f078f209
LR
729
730 memset(&hk, 0, sizeof(hk));
731
732 switch (key->alg) {
733 case ALG_WEP:
734 hk.kv_type = ATH9K_CIPHER_WEP;
735 break;
736 case ALG_TKIP:
737 hk.kv_type = ATH9K_CIPHER_TKIP;
738 break;
739 case ALG_CCMP:
740 hk.kv_type = ATH9K_CIPHER_AES_CCM;
741 break;
742 default:
ca470b29 743 return -EOPNOTSUPP;
f078f209
LR
744 }
745
6ace2891 746 hk.kv_len = key->keylen;
f078f209
LR
747 memcpy(hk.kv_val, key->key, key->keylen);
748
6ace2891
JM
749 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
750 /* For now, use the default keys for broadcast keys. This may
751 * need to change with virtual interfaces. */
752 idx = key->keyidx;
753 } else if (key->keyidx) {
dc822b5d
JB
754 if (WARN_ON(!sta))
755 return -EOPNOTSUPP;
756 mac = sta->addr;
757
6ace2891
JM
758 if (vif->type != NL80211_IFTYPE_AP) {
759 /* Only keyidx 0 should be used with unicast key, but
760 * allow this for client mode for now. */
761 idx = key->keyidx;
762 } else
763 return -EIO;
f078f209 764 } else {
dc822b5d
JB
765 if (WARN_ON(!sta))
766 return -EOPNOTSUPP;
767 mac = sta->addr;
768
6ace2891 769 if (key->alg == ALG_TKIP)
7e86c104 770 idx = ath_reserve_key_cache_slot_tkip(common);
6ace2891 771 else
7e86c104 772 idx = ath_reserve_key_cache_slot(common);
6ace2891 773 if (idx < 0)
ca470b29 774 return -ENOSPC; /* no free key cache entries */
f078f209
LR
775 }
776
777 if (key->alg == ALG_TKIP)
7e86c104 778 ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
3f53dd64 779 vif->type == NL80211_IFTYPE_AP);
f078f209 780 else
7e86c104 781 ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
f078f209
LR
782
783 if (!ret)
784 return -EIO;
785
7e86c104 786 set_bit(idx, common->keymap);
6ace2891 787 if (key->alg == ALG_TKIP) {
7e86c104
LR
788 set_bit(idx + 64, common->keymap);
789 if (common->splitmic) {
790 set_bit(idx + 32, common->keymap);
791 set_bit(idx + 64 + 32, common->keymap);
6ace2891
JM
792 }
793 }
794
795 return idx;
f078f209
LR
796}
797
7e86c104 798static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
f078f209 799{
7e86c104
LR
800 struct ath_hw *ah = common->ah;
801
802 ath9k_hw_keyreset(ah, key->hw_key_idx);
6ace2891
JM
803 if (key->hw_key_idx < IEEE80211_WEP_NKID)
804 return;
805
7e86c104 806 clear_bit(key->hw_key_idx, common->keymap);
6ace2891
JM
807 if (key->alg != ALG_TKIP)
808 return;
f078f209 809
7e86c104
LR
810 clear_bit(key->hw_key_idx + 64, common->keymap);
811 if (common->splitmic) {
733da37d 812 ath9k_hw_keyreset(ah, key->hw_key_idx + 32);
7e86c104
LR
813 clear_bit(key->hw_key_idx + 32, common->keymap);
814 clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
6ace2891 815 }
f078f209
LR
816}
817
8feceb67 818static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 819 struct ieee80211_vif *vif,
8feceb67 820 struct ieee80211_bss_conf *bss_conf)
f078f209 821{
f2b2143e 822 struct ath_hw *ah = sc->sc_ah;
1510718d 823 struct ath_common *common = ath9k_hw_common(ah);
f078f209 824
8feceb67 825 if (bss_conf->assoc) {
c46917bb
LR
826 ath_print(common, ATH_DBG_CONFIG,
827 "Bss Info ASSOC %d, bssid: %pM\n",
828 bss_conf->aid, common->curbssid);
f078f209 829
8feceb67 830 /* New association, store aid */
1510718d 831 common->curaid = bss_conf->aid;
f2b2143e 832 ath9k_hw_write_associd(ah);
2664f201
SB
833
834 /*
835 * Request a re-configuration of Beacon related timers
836 * on the receipt of the first Beacon frame (i.e.,
837 * after time sync with the AP).
838 */
1b04b930 839 sc->ps_flags |= PS_BEACON_SYNC;
f078f209 840
8feceb67 841 /* Configure the beacon */
2c3db3d5 842 ath_beacon_config(sc, vif);
f078f209 843
8feceb67 844 /* Reset rssi stats */
22e66a4c 845 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 846
3d536acf 847 ath_start_ani(common);
8feceb67 848 } else {
c46917bb 849 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 850 common->curaid = 0;
f38faa31 851 /* Stop ANI */
3d536acf 852 del_timer_sync(&common->ani.timer);
f078f209 853 }
8feceb67 854}
f078f209 855
68a89116 856void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 857{
cbe61d8a 858 struct ath_hw *ah = sc->sc_ah;
c46917bb 859 struct ath_common *common = ath9k_hw_common(ah);
68a89116 860 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 861 int r;
500c064d 862
3cbb5dd7 863 ath9k_ps_wakeup(sc);
93b1b37f 864 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 865
159cd468
VT
866 if (!ah->curchan)
867 ah->curchan = ath_get_curchannel(sc, sc->hw);
868
d2f5b3a6 869 spin_lock_bh(&sc->sc_resetlock);
2660b81a 870 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 871 if (r) {
c46917bb 872 ath_print(common, ATH_DBG_FATAL,
f643e51d 873 "Unable to reset channel (%u MHz), "
c46917bb
LR
874 "reset status %d\n",
875 channel->center_freq, r);
500c064d
VT
876 }
877 spin_unlock_bh(&sc->sc_resetlock);
878
879 ath_update_txpow(sc);
880 if (ath_startrecv(sc) != 0) {
c46917bb
LR
881 ath_print(common, ATH_DBG_FATAL,
882 "Unable to restart recv logic\n");
500c064d
VT
883 return;
884 }
885
886 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 887 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT
888
889 /* Re-Enable interrupts */
17d7904d 890 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT
891
892 /* Enable LED */
08fc5c1b 893 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 894 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 895 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 896
68a89116 897 ieee80211_wake_queues(hw);
3cbb5dd7 898 ath9k_ps_restore(sc);
500c064d
VT
899}
900
68a89116 901void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 902{
cbe61d8a 903 struct ath_hw *ah = sc->sc_ah;
68a89116 904 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 905 int r;
500c064d 906
3cbb5dd7 907 ath9k_ps_wakeup(sc);
68a89116 908 ieee80211_stop_queues(hw);
500c064d
VT
909
910 /* Disable LED */
08fc5c1b
VN
911 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
912 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT
913
914 /* Disable interrupts */
915 ath9k_hw_set_interrupts(ah, 0);
916
043a0405 917 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT
918 ath_stoprecv(sc); /* turn off frame recv */
919 ath_flushrecv(sc); /* flush recv queue */
920
159cd468 921 if (!ah->curchan)
68a89116 922 ah->curchan = ath_get_curchannel(sc, hw);
159cd468 923
500c064d 924 spin_lock_bh(&sc->sc_resetlock);
2660b81a 925 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 926 if (r) {
c46917bb 927 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
f643e51d 928 "Unable to reset channel (%u MHz), "
c46917bb
LR
929 "reset status %d\n",
930 channel->center_freq, r);
500c064d
VT
931 }
932 spin_unlock_bh(&sc->sc_resetlock);
933
934 ath9k_hw_phy_disable(ah);
93b1b37f 935 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 936 ath9k_ps_restore(sc);
9ecdef4b 937 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT
938}
939
ff37e337
S
940int ath_reset(struct ath_softc *sc, bool retry_tx)
941{
cbe61d8a 942 struct ath_hw *ah = sc->sc_ah;
c46917bb 943 struct ath_common *common = ath9k_hw_common(ah);
030bb495 944 struct ieee80211_hw *hw = sc->hw;
ae8d2858 945 int r;
ff37e337 946
2ab81d4a
S
947 /* Stop ANI */
948 del_timer_sync(&common->ani.timer);
949
cc9c378a
S
950 ieee80211_stop_queues(hw);
951
ff37e337 952 ath9k_hw_set_interrupts(ah, 0);
043a0405 953 ath_drain_all_txq(sc, retry_tx);
ff37e337
S
954 ath_stoprecv(sc);
955 ath_flushrecv(sc);
956
957 spin_lock_bh(&sc->sc_resetlock);
2660b81a 958 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 959 if (r)
c46917bb
LR
960 ath_print(common, ATH_DBG_FATAL,
961 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S
962 spin_unlock_bh(&sc->sc_resetlock);
963
964 if (ath_startrecv(sc) != 0)
c46917bb
LR
965 ath_print(common, ATH_DBG_FATAL,
966 "Unable to start recv logic\n");
ff37e337
S
967
968 /*
969 * We may be doing a reset in response to a request
970 * that changes the channel so update any state that
971 * might change as a result.
972 */
ce111bad 973 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S
974
975 ath_update_txpow(sc);
976
977 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 978 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 979
17d7904d 980 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S
981
982 if (retry_tx) {
983 int i;
984 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
985 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
986 spin_lock_bh(&sc->tx.txq[i].axq_lock);
987 ath_txq_schedule(sc, &sc->tx.txq[i]);
988 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
989 }
990 }
991 }
992
cc9c378a
S
993 ieee80211_wake_queues(hw);
994
2ab81d4a
S
995 /* Start ANI */
996 ath_start_ani(common);
997
ae8d2858 998 return r;
ff37e337
S
999}
1000
ff37e337
S
1001int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1002{
1003 int qnum;
1004
1005 switch (queue) {
1006 case 0:
b77f483f 1007 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S
1008 break;
1009 case 1:
b77f483f 1010 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S
1011 break;
1012 case 2:
b77f483f 1013 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S
1014 break;
1015 case 3:
b77f483f 1016 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S
1017 break;
1018 default:
b77f483f 1019 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S
1020 break;
1021 }
1022
1023 return qnum;
1024}
1025
1026int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1027{
1028 int qnum;
1029
1030 switch (queue) {
1031 case ATH9K_WME_AC_VO:
1032 qnum = 0;
1033 break;
1034 case ATH9K_WME_AC_VI:
1035 qnum = 1;
1036 break;
1037 case ATH9K_WME_AC_BE:
1038 qnum = 2;
1039 break;
1040 case ATH9K_WME_AC_BK:
1041 qnum = 3;
1042 break;
1043 default:
1044 qnum = -1;
1045 break;
1046 }
1047
1048 return qnum;
1049}
1050
5f8e077c
LR
1051/* XXX: Remove me once we don't depend on ath9k_channel for all
1052 * this redundant data */
0e2dedf9
JM
1053void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1054 struct ath9k_channel *ichan)
5f8e077c 1055{
5f8e077c
LR
1056 struct ieee80211_channel *chan = hw->conf.channel;
1057 struct ieee80211_conf *conf = &hw->conf;
1058
1059 ichan->channel = chan->center_freq;
1060 ichan->chan = chan;
1061
1062 if (chan->band == IEEE80211_BAND_2GHZ) {
1063 ichan->chanmode = CHANNEL_G;
8813262e 1064 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR
1065 } else {
1066 ichan->chanmode = CHANNEL_A;
1067 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1068 }
1069
25c56eec 1070 if (conf_is_ht(conf))
5f8e077c
LR
1071 ichan->chanmode = ath_get_extchanmode(sc, chan,
1072 conf->channel_type);
5f8e077c
LR
1073}
1074
ff37e337
S
1075/**********************/
1076/* mac80211 callbacks */
1077/**********************/
1078
8feceb67 1079static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1080{
bce048d7
JM
1081 struct ath_wiphy *aphy = hw->priv;
1082 struct ath_softc *sc = aphy->sc;
af03abec 1083 struct ath_hw *ah = sc->sc_ah;
c46917bb 1084 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1085 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1086 struct ath9k_channel *init_channel;
82880a7c 1087 int r;
f078f209 1088
c46917bb
LR
1089 ath_print(common, ATH_DBG_CONFIG,
1090 "Starting driver with initial channel: %d MHz\n",
1091 curchan->center_freq);
f078f209 1092
141b38b6
S
1093 mutex_lock(&sc->mutex);
1094
9580a222
JM
1095 if (ath9k_wiphy_started(sc)) {
1096 if (sc->chan_idx == curchan->hw_value) {
1097 /*
1098 * Already on the operational channel, the new wiphy
1099 * can be marked active.
1100 */
1101 aphy->state = ATH_WIPHY_ACTIVE;
1102 ieee80211_wake_queues(hw);
1103 } else {
1104 /*
1105 * Another wiphy is on another channel, start the new
1106 * wiphy in paused state.
1107 */
1108 aphy->state = ATH_WIPHY_PAUSED;
1109 ieee80211_stop_queues(hw);
1110 }
1111 mutex_unlock(&sc->mutex);
1112 return 0;
1113 }
1114 aphy->state = ATH_WIPHY_ACTIVE;
1115
8feceb67 1116 /* setup initial channel */
f078f209 1117
82880a7c 1118 sc->chan_idx = curchan->hw_value;
f078f209 1119
82880a7c 1120 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S
1121
1122 /* Reset SERDES registers */
af03abec 1123 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S
1124
1125 /*
1126 * The basic interface to setting the hardware in a good
1127 * state is ``reset''. On return the hardware is known to
1128 * be powered up and with interrupts disabled. This must
1129 * be followed by initialization of the appropriate bits
1130 * and then setup of the interrupt mask.
1131 */
1132 spin_lock_bh(&sc->sc_resetlock);
af03abec 1133 r = ath9k_hw_reset(ah, init_channel, false);
ae8d2858 1134 if (r) {
c46917bb
LR
1135 ath_print(common, ATH_DBG_FATAL,
1136 "Unable to reset hardware; reset status %d "
1137 "(freq %u MHz)\n", r,
1138 curchan->center_freq);
ff37e337 1139 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1140 goto mutex_unlock;
ff37e337
S
1141 }
1142 spin_unlock_bh(&sc->sc_resetlock);
1143
1144 /*
1145 * This is needed only to setup initial state
1146 * but it's best done after a reset.
1147 */
1148 ath_update_txpow(sc);
8feceb67 1149
ff37e337
S
1150 /*
1151 * Setup the hardware after reset:
1152 * The receive engine is set going.
1153 * Frame transmit is handled entirely
1154 * in the frame output path; there's nothing to do
1155 * here except setup the interrupt mask.
1156 */
1157 if (ath_startrecv(sc) != 0) {
c46917bb
LR
1158 ath_print(common, ATH_DBG_FATAL,
1159 "Unable to start recv logic\n");
141b38b6
S
1160 r = -EIO;
1161 goto mutex_unlock;
f078f209 1162 }
8feceb67 1163
ff37e337 1164 /* Setup our intr mask. */
17d7904d 1165 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S
1166 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1167 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1168
af03abec 1169 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 1170 sc->imask |= ATH9K_INT_GTT;
ff37e337 1171
af03abec 1172 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 1173 sc->imask |= ATH9K_INT_CST;
ff37e337 1174
ce111bad 1175 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S
1176
1177 sc->sc_flags &= ~SC_OP_INVALID;
1178
1179 /* Disable BMISS interrupt when we're not associated */
17d7904d 1180 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
af03abec 1181 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337 1182
bce048d7 1183 ieee80211_wake_queues(hw);
ff37e337 1184
42935eca 1185 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1186
766ec4a9
LR
1187 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1188 !ah->btcoex_hw.enabled) {
5e197292
LR
1189 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1190 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1191 ath9k_hw_btcoex_enable(ah);
f985ad12 1192
5bb12791
LR
1193 if (common->bus_ops->bt_coex_prep)
1194 common->bus_ops->bt_coex_prep(common);
766ec4a9 1195 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1196 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1197 }
1198
141b38b6
S
1199mutex_unlock:
1200 mutex_unlock(&sc->mutex);
1201
ae8d2858 1202 return r;
f078f209
LR
1203}
1204
8feceb67
VT
1205static int ath9k_tx(struct ieee80211_hw *hw,
1206 struct sk_buff *skb)
f078f209 1207{
528f0c6b 1208 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM
1209 struct ath_wiphy *aphy = hw->priv;
1210 struct ath_softc *sc = aphy->sc;
c46917bb 1211 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1212 struct ath_tx_control txctl;
1bc14880
BP
1213 int padpos, padsize;
1214 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1215
8089cc47 1216 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
c46917bb
LR
1217 ath_print(common, ATH_DBG_XMIT,
1218 "ath9k: %s: TX in unexpected wiphy state "
1219 "%d\n", wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM
1220 goto exit;
1221 }
1222
96148326 1223 if (sc->ps_enabled) {
dc8c4585
JM
1224 /*
1225 * mac80211 does not set PM field for normal data frames, so we
1226 * need to update that based on the current PS mode.
1227 */
1228 if (ieee80211_is_data(hdr->frame_control) &&
1229 !ieee80211_is_nullfunc(hdr->frame_control) &&
1230 !ieee80211_has_pm(hdr->frame_control)) {
c46917bb
LR
1231 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
1232 "while in PS mode\n");
dc8c4585
JM
1233 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1234 }
1235 }
1236
9a23f9ca
JM
1237 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1238 /*
1239 * We are using PS-Poll and mac80211 can request TX while in
1240 * power save mode. Need to wake up hardware for the TX to be
1241 * completed and if needed, also for RX of buffered frames.
1242 */
9a23f9ca
JM
1243 ath9k_ps_wakeup(sc);
1244 ath9k_hw_setrxabort(sc->sc_ah, 0);
1245 if (ieee80211_is_pspoll(hdr->frame_control)) {
c46917bb
LR
1246 ath_print(common, ATH_DBG_PS,
1247 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1248 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1249 } else {
c46917bb
LR
1250 ath_print(common, ATH_DBG_PS,
1251 "Wake up to complete TX\n");
1b04b930 1252 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1253 }
1254 /*
1255 * The actual restore operation will happen only after
1256 * the sc_flags bit is cleared. We are just dropping
1257 * the ps_usecount here.
1258 */
1259 ath9k_ps_restore(sc);
1260 }
1261
528f0c6b 1262 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1263
8feceb67
VT
1264 /*
1265 * As a temporary workaround, assign seq# here; this will likely need
1266 * to be cleaned up to work better with Beacon transmission and virtual
1267 * BSSes.
1268 */
1269 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
8feceb67 1270 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1271 sc->tx.seq_no += 0x10;
8feceb67 1272 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1273 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1274 }
f078f209 1275
8feceb67 1276 /* Add the padding after the header if this is not already done */
1bc14880
BP
1277 padpos = ath9k_cmn_padpos(hdr->frame_control);
1278 padsize = padpos & 3;
1279 if (padsize && skb->len>padpos) {
8feceb67
VT
1280 if (skb_headroom(skb) < padsize)
1281 return -1;
1282 skb_push(skb, padsize);
1bc14880 1283 memmove(skb->data, skb->data + padsize, padpos);
8feceb67
VT
1284 }
1285
528f0c6b
S
1286 /* Check if a tx queue is available */
1287
1288 txctl.txq = ath_test_get_txq(sc, skb);
1289 if (!txctl.txq)
1290 goto exit;
1291
c46917bb 1292 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1293
c52f33d0 1294 if (ath_tx_start(hw, skb, &txctl) != 0) {
c46917bb 1295 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1296 goto exit;
8feceb67
VT
1297 }
1298
528f0c6b
S
1299 return 0;
1300exit:
1301 dev_kfree_skb_any(skb);
8feceb67 1302 return 0;
f078f209
LR
1303}
1304
8feceb67 1305static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1306{
bce048d7
JM
1307 struct ath_wiphy *aphy = hw->priv;
1308 struct ath_softc *sc = aphy->sc;
af03abec 1309 struct ath_hw *ah = sc->sc_ah;
c46917bb 1310 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1311
4c483817
S
1312 mutex_lock(&sc->mutex);
1313
9580a222
JM
1314 aphy->state = ATH_WIPHY_INACTIVE;
1315
c94dbff7
LR
1316 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1317 cancel_delayed_work_sync(&sc->tx_complete_work);
1318
1319 if (!sc->num_sec_wiphy) {
1320 cancel_delayed_work_sync(&sc->wiphy_work);
1321 cancel_work_sync(&sc->chan_work);
1322 }
1323
9c84b797 1324 if (sc->sc_flags & SC_OP_INVALID) {
c46917bb 1325 ath_print(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1326 mutex_unlock(&sc->mutex);
9c84b797
S
1327 return;
1328 }
8feceb67 1329
9580a222
JM
1330 if (ath9k_wiphy_started(sc)) {
1331 mutex_unlock(&sc->mutex);
1332 return; /* another wiphy still in use */
1333 }
1334
3867cf6a
S
1335 /* Ensure HW is awake when we try to shut it down. */
1336 ath9k_ps_wakeup(sc);
1337
766ec4a9 1338 if (ah->btcoex_hw.enabled) {
af03abec 1339 ath9k_hw_btcoex_disable(ah);
766ec4a9 1340 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1341 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1342 }
1343
ff37e337
S
1344 /* make sure h/w will not generate any interrupt
1345 * before setting the invalid flag. */
af03abec 1346 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S
1347
1348 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1349 ath_drain_all_txq(sc, false);
ff37e337 1350 ath_stoprecv(sc);
af03abec 1351 ath9k_hw_phy_disable(ah);
ff37e337 1352 } else
b77f483f 1353 sc->rx.rxlink = NULL;
ff37e337 1354
ff37e337 1355 /* disable HAL and put h/w to sleep */
af03abec
LR
1356 ath9k_hw_disable(ah);
1357 ath9k_hw_configpcipowersave(ah, 1, 1);
3867cf6a
S
1358 ath9k_ps_restore(sc);
1359
1360 /* Finally, put the chip in FULL SLEEP mode */
9ecdef4b 1361 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ff37e337
S
1362
1363 sc->sc_flags |= SC_OP_INVALID;
500c064d 1364
141b38b6
S
1365 mutex_unlock(&sc->mutex);
1366
c46917bb 1367 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1368}
1369
8feceb67 1370static int ath9k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 1371 struct ieee80211_vif *vif)
f078f209 1372{
bce048d7
JM
1373 struct ath_wiphy *aphy = hw->priv;
1374 struct ath_softc *sc = aphy->sc;
c46917bb 1375 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1ed32e4f 1376 struct ath_vif *avp = (void *)vif->drv_priv;
d97809db 1377 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 1378 int ret = 0;
8feceb67 1379
141b38b6
S
1380 mutex_lock(&sc->mutex);
1381
8ca21f01
JM
1382 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
1383 sc->nvifs > 0) {
1384 ret = -ENOBUFS;
1385 goto out;
1386 }
1387
1ed32e4f 1388 switch (vif->type) {
05c914fe 1389 case NL80211_IFTYPE_STATION:
d97809db 1390 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 1391 break;
05c914fe 1392 case NL80211_IFTYPE_ADHOC:
05c914fe 1393 case NL80211_IFTYPE_AP:
9cb5412b 1394 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM
1395 if (sc->nbcnvifs >= ATH_BCBUF) {
1396 ret = -ENOBUFS;
1397 goto out;
1398 }
1ed32e4f 1399 ic_opmode = vif->type;
f078f209
LR
1400 break;
1401 default:
c46917bb 1402 ath_print(common, ATH_DBG_FATAL,
1ed32e4f 1403 "Interface type %d not yet supported\n", vif->type);
2c3db3d5
JM
1404 ret = -EOPNOTSUPP;
1405 goto out;
f078f209
LR
1406 }
1407
c46917bb
LR
1408 ath_print(common, ATH_DBG_CONFIG,
1409 "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 1410
17d7904d 1411 /* Set the VIF opmode */
5640b08e
S
1412 avp->av_opmode = ic_opmode;
1413 avp->av_bslot = -1;
1414
2c3db3d5 1415 sc->nvifs++;
8ca21f01
JM
1416
1417 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1418 ath9k_set_bssid_mask(hw);
1419
2c3db3d5
JM
1420 if (sc->nvifs > 1)
1421 goto out; /* skip global settings for secondary vif */
1422
b238e90e 1423 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 1424 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S
1425 sc->sc_flags |= SC_OP_TSF_RESET;
1426 }
5640b08e 1427
5640b08e 1428 /* Set the device opmode */
2660b81a 1429 sc->sc_ah->opmode = ic_opmode;
5640b08e 1430
4e30ffa2
VN
1431 /*
1432 * Enable MIB interrupts when there are hardware phy counters.
1433 * Note we only do this (at the moment) for station mode.
1434 */
1ed32e4f
JB
1435 if ((vif->type == NL80211_IFTYPE_STATION) ||
1436 (vif->type == NL80211_IFTYPE_ADHOC) ||
1437 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 1438 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S
1439 sc->imask |= ATH9K_INT_TSFOOR;
1440 }
1441
17d7904d 1442 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 1443
1ed32e4f
JB
1444 if (vif->type == NL80211_IFTYPE_AP ||
1445 vif->type == NL80211_IFTYPE_ADHOC ||
1446 vif->type == NL80211_IFTYPE_MONITOR)
3d536acf 1447 ath_start_ani(common);
6f255425 1448
2c3db3d5 1449out:
141b38b6 1450 mutex_unlock(&sc->mutex);
2c3db3d5 1451 return ret;
f078f209
LR
1452}
1453
8feceb67 1454static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1455 struct ieee80211_vif *vif)
f078f209 1456{
bce048d7
JM
1457 struct ath_wiphy *aphy = hw->priv;
1458 struct ath_softc *sc = aphy->sc;
c46917bb 1459 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1ed32e4f 1460 struct ath_vif *avp = (void *)vif->drv_priv;
2c3db3d5 1461 int i;
f078f209 1462
c46917bb 1463 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1464
141b38b6
S
1465 mutex_lock(&sc->mutex);
1466
6f255425 1467 /* Stop ANI */
3d536acf 1468 del_timer_sync(&common->ani.timer);
580f0b8a 1469
8feceb67 1470 /* Reclaim beacon resources */
9cb5412b
PE
1471 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
1472 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
1473 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
5f70a88f 1474 ath9k_ps_wakeup(sc);
b77f483f 1475 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
5f70a88f 1476 ath9k_ps_restore(sc);
580f0b8a 1477 }
f078f209 1478
74401773 1479 ath_beacon_return(sc, avp);
8feceb67 1480 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 1481
2c3db3d5 1482 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1ed32e4f 1483 if (sc->beacon.bslot[i] == vif) {
2c3db3d5
JM
1484 printk(KERN_DEBUG "%s: vif had allocated beacon "
1485 "slot\n", __func__);
1486 sc->beacon.bslot[i] = NULL;
c52f33d0 1487 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM
1488 }
1489 }
1490
17d7904d 1491 sc->nvifs--;
141b38b6
S
1492
1493 mutex_unlock(&sc->mutex);
f078f209
LR
1494}
1495
3f7c5c10
SB
1496void ath9k_enable_ps(struct ath_softc *sc)
1497{
1498 sc->ps_enabled = true;
1499 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1500 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
1501 sc->imask |= ATH9K_INT_TIM_TIMER;
1502 ath9k_hw_set_interrupts(sc->sc_ah,
1503 sc->imask);
1504 }
1505 }
1506 ath9k_hw_setrxabort(sc->sc_ah, 1);
1507}
1508
e8975581 1509static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1510{
bce048d7
JM
1511 struct ath_wiphy *aphy = hw->priv;
1512 struct ath_softc *sc = aphy->sc;
c46917bb 1513 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e8975581 1514 struct ieee80211_conf *conf = &hw->conf;
8782b41d 1515 struct ath_hw *ah = sc->sc_ah;
194b7c13 1516 bool disable_radio;
f078f209 1517
aa33de09 1518 mutex_lock(&sc->mutex);
141b38b6 1519
194b7c13
LR
1520 /*
1521 * Leave this as the first check because we need to turn on the
1522 * radio if it was disabled before prior to processing the rest
1523 * of the changes. Likewise we must only disable the radio towards
1524 * the end.
1525 */
64839170 1526 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
194b7c13
LR
1527 bool enable_radio;
1528 bool all_wiphys_idle;
1529 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
64839170
LR
1530
1531 spin_lock_bh(&sc->wiphy_lock);
1532 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
194b7c13
LR
1533 ath9k_set_wiphy_idle(aphy, idle);
1534
1535 if (!idle && all_wiphys_idle)
1536 enable_radio = true;
1537
1538 /*
1539 * After we unlock here its possible another wiphy
1540 * can be re-renabled so to account for that we will
1541 * only disable the radio toward the end of this routine
1542 * if by then all wiphys are still idle.
1543 */
64839170
LR
1544 spin_unlock_bh(&sc->wiphy_lock);
1545
194b7c13 1546 if (enable_radio) {
1dbfd9d4 1547 sc->ps_idle = false;
68a89116 1548 ath_radio_enable(sc, hw);
c46917bb
LR
1549 ath_print(common, ATH_DBG_CONFIG,
1550 "not-idle: enabling radio\n");
64839170
LR
1551 }
1552 }
1553
e7824a50
LR
1554 /*
1555 * We just prepare to enable PS. We have to wait until our AP has
1556 * ACK'd our null data frame to disable RX otherwise we'll ignore
1557 * those ACKs and end up retransmitting the same null data frames.
1558 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1559 */
3cbb5dd7
VN
1560 if (changed & IEEE80211_CONF_CHANGE_PS) {
1561 if (conf->flags & IEEE80211_CONF_PS) {
1b04b930 1562 sc->ps_flags |= PS_ENABLED;
e7824a50
LR
1563 /*
1564 * At this point we know hardware has received an ACK
1565 * of a previously sent null data frame.
1566 */
1b04b930
S
1567 if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
1568 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
3f7c5c10 1569 ath9k_enable_ps(sc);
e7824a50 1570 }
3cbb5dd7 1571 } else {
96148326 1572 sc->ps_enabled = false;
1b04b930
S
1573 sc->ps_flags &= ~(PS_ENABLED |
1574 PS_NULLFUNC_COMPLETED);
9ecdef4b 1575 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8782b41d
VN
1576 if (!(ah->caps.hw_caps &
1577 ATH9K_HW_CAP_AUTOSLEEP)) {
1578 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930
S
1579 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1580 PS_WAIT_FOR_CAB |
1581 PS_WAIT_FOR_PSPOLL_DATA |
1582 PS_WAIT_FOR_TX_ACK);
8782b41d
VN
1583 if (sc->imask & ATH9K_INT_TIM_TIMER) {
1584 sc->imask &= ~ATH9K_INT_TIM_TIMER;
1585 ath9k_hw_set_interrupts(sc->sc_ah,
1586 sc->imask);
1587 }
3cbb5dd7
VN
1588 }
1589 }
1590 }
1591
199afd9d
S
1592 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1593 if (conf->flags & IEEE80211_CONF_MONITOR) {
1594 ath_print(common, ATH_DBG_CONFIG,
1595 "HW opmode set to Monitor mode\n");
1596 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1597 }
1598 }
1599
4797938c 1600 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1601 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1602 int pos = curchan->hw_value;
ae5eb026 1603
0e2dedf9
JM
1604 aphy->chan_idx = pos;
1605 aphy->chan_is_ht = conf_is_ht(conf);
1606
8089cc47
JM
1607 if (aphy->state == ATH_WIPHY_SCAN ||
1608 aphy->state == ATH_WIPHY_ACTIVE)
1609 ath9k_wiphy_pause_all_forced(sc, aphy);
1610 else {
1611 /*
1612 * Do not change operational channel based on a paused
1613 * wiphy changes.
1614 */
1615 goto skip_chan_change;
1616 }
0e2dedf9 1617
c46917bb
LR
1618 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1619 curchan->center_freq);
f078f209 1620
5f8e077c 1621 /* XXX: remove me eventualy */
0e2dedf9 1622 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 1623
ecf70441 1624 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 1625
0e2dedf9 1626 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
c46917bb
LR
1627 ath_print(common, ATH_DBG_FATAL,
1628 "Unable to set channel\n");
aa33de09 1629 mutex_unlock(&sc->mutex);
e11602b7
S
1630 return -EINVAL;
1631 }
094d05dc 1632 }
f078f209 1633
8089cc47 1634skip_chan_change:
c9f6a656 1635 if (changed & IEEE80211_CONF_CHANGE_POWER) {
17d7904d 1636 sc->config.txpowlimit = 2 * conf->power_level;
c9f6a656
LR
1637 ath_update_txpow(sc);
1638 }
f078f209 1639
194b7c13
LR
1640 spin_lock_bh(&sc->wiphy_lock);
1641 disable_radio = ath9k_all_wiphys_idle(sc);
1642 spin_unlock_bh(&sc->wiphy_lock);
1643
64839170 1644 if (disable_radio) {
c46917bb 1645 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1dbfd9d4 1646 sc->ps_idle = true;
68a89116 1647 ath_radio_disable(sc, hw);
64839170
LR
1648 }
1649
aa33de09 1650 mutex_unlock(&sc->mutex);
141b38b6 1651
f078f209
LR
1652 return 0;
1653}
1654
8feceb67
VT
1655#define SUPPORTED_FILTERS \
1656 (FIF_PROMISC_IN_BSS | \
1657 FIF_ALLMULTI | \
1658 FIF_CONTROL | \
af6a3fc7 1659 FIF_PSPOLL | \
8feceb67
VT
1660 FIF_OTHER_BSS | \
1661 FIF_BCN_PRBRESP_PROMISC | \
1662 FIF_FCSFAIL)
c83be688 1663
8feceb67
VT
1664/* FIXME: sc->sc_full_reset ? */
1665static void ath9k_configure_filter(struct ieee80211_hw *hw,
1666 unsigned int changed_flags,
1667 unsigned int *total_flags,
3ac64bee 1668 u64 multicast)
8feceb67 1669{
bce048d7
JM
1670 struct ath_wiphy *aphy = hw->priv;
1671 struct ath_softc *sc = aphy->sc;
8feceb67 1672 u32 rfilt;
f078f209 1673
8feceb67
VT
1674 changed_flags &= SUPPORTED_FILTERS;
1675 *total_flags &= SUPPORTED_FILTERS;
f078f209 1676
b77f483f 1677 sc->rx.rxfilter = *total_flags;
aa68aeaa 1678 ath9k_ps_wakeup(sc);
8feceb67
VT
1679 rfilt = ath_calcrxfilter(sc);
1680 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1681 ath9k_ps_restore(sc);
f078f209 1682
c46917bb
LR
1683 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1684 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1685}
f078f209 1686
8feceb67
VT
1687static void ath9k_sta_notify(struct ieee80211_hw *hw,
1688 struct ieee80211_vif *vif,
1689 enum sta_notify_cmd cmd,
17741cdc 1690 struct ieee80211_sta *sta)
8feceb67 1691{
bce048d7
JM
1692 struct ath_wiphy *aphy = hw->priv;
1693 struct ath_softc *sc = aphy->sc;
f078f209 1694
8feceb67
VT
1695 switch (cmd) {
1696 case STA_NOTIFY_ADD:
5640b08e 1697 ath_node_attach(sc, sta);
8feceb67
VT
1698 break;
1699 case STA_NOTIFY_REMOVE:
b5aa9bf9 1700 ath_node_detach(sc, sta);
8feceb67
VT
1701 break;
1702 default:
1703 break;
1704 }
f078f209
LR
1705}
1706
141b38b6 1707static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1708 const struct ieee80211_tx_queue_params *params)
f078f209 1709{
bce048d7
JM
1710 struct ath_wiphy *aphy = hw->priv;
1711 struct ath_softc *sc = aphy->sc;
c46917bb 1712 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67
VT
1713 struct ath9k_tx_queue_info qi;
1714 int ret = 0, qnum;
f078f209 1715
8feceb67
VT
1716 if (queue >= WME_NUM_AC)
1717 return 0;
f078f209 1718
141b38b6
S
1719 mutex_lock(&sc->mutex);
1720
1ffb0610
S
1721 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1722
8feceb67
VT
1723 qi.tqi_aifs = params->aifs;
1724 qi.tqi_cwmin = params->cw_min;
1725 qi.tqi_cwmax = params->cw_max;
1726 qi.tqi_burstTime = params->txop;
1727 qnum = ath_get_hal_qnum(queue, sc);
f078f209 1728
c46917bb
LR
1729 ath_print(common, ATH_DBG_CONFIG,
1730 "Configure tx [queue/halq] [%d/%d], "
1731 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1732 queue, qnum, params->aifs, params->cw_min,
1733 params->cw_max, params->txop);
f078f209 1734
8feceb67
VT
1735 ret = ath_txq_update(sc, qnum, &qi);
1736 if (ret)
c46917bb 1737 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 1738
94db2936
VN
1739 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1740 if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret)
1741 ath_beaconq_config(sc);
1742
141b38b6
S
1743 mutex_unlock(&sc->mutex);
1744
8feceb67
VT
1745 return ret;
1746}
f078f209 1747
8feceb67
VT
1748static int ath9k_set_key(struct ieee80211_hw *hw,
1749 enum set_key_cmd cmd,
dc822b5d
JB
1750 struct ieee80211_vif *vif,
1751 struct ieee80211_sta *sta,
8feceb67
VT
1752 struct ieee80211_key_conf *key)
1753{
bce048d7
JM
1754 struct ath_wiphy *aphy = hw->priv;
1755 struct ath_softc *sc = aphy->sc;
c46917bb 1756 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1757 int ret = 0;
f078f209 1758
b3bd89ce
JM
1759 if (modparam_nohwcrypt)
1760 return -ENOSPC;
1761
141b38b6 1762 mutex_lock(&sc->mutex);
3cbb5dd7 1763 ath9k_ps_wakeup(sc);
c46917bb 1764 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1765
8feceb67
VT
1766 switch (cmd) {
1767 case SET_KEY:
7e86c104 1768 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1769 if (ret >= 0) {
1770 key->hw_key_idx = ret;
8feceb67
VT
1771 /* push IV and Michael MIC generation to stack */
1772 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1773 if (key->alg == ALG_TKIP)
1774 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM
1775 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
1776 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1777 ret = 0;
8feceb67
VT
1778 }
1779 break;
1780 case DISABLE_KEY:
7e86c104 1781 ath_key_delete(common, key);
8feceb67
VT
1782 break;
1783 default:
1784 ret = -EINVAL;
1785 }
f078f209 1786
3cbb5dd7 1787 ath9k_ps_restore(sc);
141b38b6
S
1788 mutex_unlock(&sc->mutex);
1789
8feceb67
VT
1790 return ret;
1791}
f078f209 1792
8feceb67
VT
1793static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1794 struct ieee80211_vif *vif,
1795 struct ieee80211_bss_conf *bss_conf,
1796 u32 changed)
1797{
bce048d7
JM
1798 struct ath_wiphy *aphy = hw->priv;
1799 struct ath_softc *sc = aphy->sc;
2d0ddec5 1800 struct ath_hw *ah = sc->sc_ah;
1510718d 1801 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1802 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1803 int slottime;
c6089ccc 1804 int error;
f078f209 1805
141b38b6
S
1806 mutex_lock(&sc->mutex);
1807
c6089ccc
S
1808 if (changed & BSS_CHANGED_BSSID) {
1809 /* Set BSSID */
1810 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1811 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 1812 common->curaid = 0;
f2b2143e 1813 ath9k_hw_write_associd(ah);
2d0ddec5 1814
c6089ccc
S
1815 /* Set aggregation protection mode parameters */
1816 sc->config.ath_aggr_prot = 0;
2d0ddec5 1817
c6089ccc
S
1818 /* Only legacy IBSS for now */
1819 if (vif->type == NL80211_IFTYPE_ADHOC)
1820 ath_update_chainmask(sc, 0);
2d0ddec5 1821
c6089ccc
S
1822 ath_print(common, ATH_DBG_CONFIG,
1823 "BSSID: %pM aid: 0x%x\n",
1824 common->curbssid, common->curaid);
2d0ddec5 1825
c6089ccc
S
1826 /* need to reconfigure the beacon */
1827 sc->sc_flags &= ~SC_OP_BEACONS ;
1828 }
2d0ddec5 1829
c6089ccc
S
1830 /* Enable transmission of beacons (AP, IBSS, MESH) */
1831 if ((changed & BSS_CHANGED_BEACON) ||
1832 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
1833 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1834 error = ath_beacon_alloc(aphy, vif);
1835 if (!error)
1836 ath_beacon_config(sc, vif);
0005baf4
FF
1837 }
1838
1839 if (changed & BSS_CHANGED_ERP_SLOT) {
1840 if (bss_conf->use_short_slot)
1841 slottime = 9;
1842 else
1843 slottime = 20;
1844 if (vif->type == NL80211_IFTYPE_AP) {
1845 /*
1846 * Defer update, so that connected stations can adjust
1847 * their settings at the same time.
1848 * See beacon.c for more details
1849 */
1850 sc->beacon.slottime = slottime;
1851 sc->beacon.updateslot = UPDATE;
1852 } else {
1853 ah->slottime = slottime;
1854 ath9k_hw_init_global_settings(ah);
1855 }
2d0ddec5
JB
1856 }
1857
c6089ccc
S
1858 /* Disable transmission of beacons */
1859 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
1860 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5 1861
c6089ccc
S
1862 if (changed & BSS_CHANGED_BEACON_INT) {
1863 sc->beacon_interval = bss_conf->beacon_int;
1864 /*
1865 * In case of AP mode, the HW TSF has to be reset
1866 * when the beacon interval changes.
1867 */
1868 if (vif->type == NL80211_IFTYPE_AP) {
1869 sc->sc_flags |= SC_OP_TSF_RESET;
1870 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5
JB
1871 error = ath_beacon_alloc(aphy, vif);
1872 if (!error)
1873 ath_beacon_config(sc, vif);
c6089ccc
S
1874 } else {
1875 ath_beacon_config(sc, vif);
2d0ddec5
JB
1876 }
1877 }
1878
8feceb67 1879 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
c46917bb
LR
1880 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
1881 bss_conf->use_short_preamble);
8feceb67
VT
1882 if (bss_conf->use_short_preamble)
1883 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1884 else
1885 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1886 }
f078f209 1887
8feceb67 1888 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
c46917bb
LR
1889 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
1890 bss_conf->use_cts_prot);
8feceb67
VT
1891 if (bss_conf->use_cts_prot &&
1892 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1893 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1894 else
1895 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1896 }
f078f209 1897
8feceb67 1898 if (changed & BSS_CHANGED_ASSOC) {
c46917bb 1899 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 1900 bss_conf->assoc);
5640b08e 1901 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 1902 }
141b38b6
S
1903
1904 mutex_unlock(&sc->mutex);
8feceb67 1905}
f078f209 1906
8feceb67
VT
1907static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1908{
1909 u64 tsf;
bce048d7
JM
1910 struct ath_wiphy *aphy = hw->priv;
1911 struct ath_softc *sc = aphy->sc;
f078f209 1912
141b38b6
S
1913 mutex_lock(&sc->mutex);
1914 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1915 mutex_unlock(&sc->mutex);
f078f209 1916
8feceb67
VT
1917 return tsf;
1918}
f078f209 1919
3b5d665b
AF
1920static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
1921{
bce048d7
JM
1922 struct ath_wiphy *aphy = hw->priv;
1923 struct ath_softc *sc = aphy->sc;
3b5d665b 1924
141b38b6
S
1925 mutex_lock(&sc->mutex);
1926 ath9k_hw_settsf64(sc->sc_ah, tsf);
1927 mutex_unlock(&sc->mutex);
3b5d665b
AF
1928}
1929
8feceb67
VT
1930static void ath9k_reset_tsf(struct ieee80211_hw *hw)
1931{
bce048d7
JM
1932 struct ath_wiphy *aphy = hw->priv;
1933 struct ath_softc *sc = aphy->sc;
c83be688 1934
141b38b6 1935 mutex_lock(&sc->mutex);
21526d57
LR
1936
1937 ath9k_ps_wakeup(sc);
141b38b6 1938 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
1939 ath9k_ps_restore(sc);
1940
141b38b6 1941 mutex_unlock(&sc->mutex);
8feceb67 1942}
f078f209 1943
8feceb67 1944static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1945 struct ieee80211_vif *vif,
141b38b6
S
1946 enum ieee80211_ampdu_mlme_action action,
1947 struct ieee80211_sta *sta,
1948 u16 tid, u16 *ssn)
8feceb67 1949{
bce048d7
JM
1950 struct ath_wiphy *aphy = hw->priv;
1951 struct ath_softc *sc = aphy->sc;
8feceb67 1952 int ret = 0;
f078f209 1953
8feceb67
VT
1954 switch (action) {
1955 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
1956 if (!(sc->sc_flags & SC_OP_RXAGGR))
1957 ret = -ENOTSUPP;
8feceb67
VT
1958 break;
1959 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
1960 break;
1961 case IEEE80211_AMPDU_TX_START:
8b685ba9 1962 ath9k_ps_wakeup(sc);
f83da965 1963 ath_tx_aggr_start(sc, sta, tid, ssn);
c951ad35 1964 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1965 ath9k_ps_restore(sc);
8feceb67
VT
1966 break;
1967 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 1968 ath9k_ps_wakeup(sc);
f83da965 1969 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 1970 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1971 ath9k_ps_restore(sc);
8feceb67 1972 break;
b1720231 1973 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1974 ath9k_ps_wakeup(sc);
8469cdef 1975 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1976 ath9k_ps_restore(sc);
8469cdef 1977 break;
8feceb67 1978 default:
c46917bb
LR
1979 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1980 "Unknown AMPDU action\n");
8feceb67
VT
1981 }
1982
1983 return ret;
f078f209
LR
1984}
1985
0c98de65
S
1986static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
1987{
bce048d7
JM
1988 struct ath_wiphy *aphy = hw->priv;
1989 struct ath_softc *sc = aphy->sc;
05c78d6d 1990 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0c98de65 1991
3d832611 1992 mutex_lock(&sc->mutex);
8089cc47
JM
1993 if (ath9k_wiphy_scanning(sc)) {
1994 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
1995 "same time\n");
1996 /*
1997 * Do not allow the concurrent scanning state for now. This
1998 * could be improved with scanning control moved into ath9k.
1999 */
3d832611 2000 mutex_unlock(&sc->mutex);
8089cc47
JM
2001 return;
2002 }
2003
2004 aphy->state = ATH_WIPHY_SCAN;
2005 ath9k_wiphy_pause_all_forced(sc, aphy);
0c98de65 2006 sc->sc_flags |= SC_OP_SCANNING;
05c78d6d 2007 del_timer_sync(&common->ani.timer);
b6ce5c33 2008 cancel_delayed_work_sync(&sc->tx_complete_work);
3d832611 2009 mutex_unlock(&sc->mutex);
0c98de65
S
2010}
2011
2012static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2013{
bce048d7
JM
2014 struct ath_wiphy *aphy = hw->priv;
2015 struct ath_softc *sc = aphy->sc;
05c78d6d 2016 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0c98de65 2017
3d832611 2018 mutex_lock(&sc->mutex);
8089cc47 2019 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2020 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2021 sc->sc_flags |= SC_OP_FULL_RESET;
05c78d6d 2022 ath_start_ani(common);
b6ce5c33 2023 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
d0bec342 2024 ath_beacon_config(sc, NULL);
3d832611 2025 mutex_unlock(&sc->mutex);
0c98de65
S
2026}
2027
e239d859
FF
2028static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2029{
2030 struct ath_wiphy *aphy = hw->priv;
2031 struct ath_softc *sc = aphy->sc;
2032 struct ath_hw *ah = sc->sc_ah;
2033
2034 mutex_lock(&sc->mutex);
2035 ah->coverage_class = coverage_class;
2036 ath9k_hw_init_global_settings(ah);
2037 mutex_unlock(&sc->mutex);
2038}
2039
6baff7f9 2040struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2041 .tx = ath9k_tx,
2042 .start = ath9k_start,
2043 .stop = ath9k_stop,
2044 .add_interface = ath9k_add_interface,
2045 .remove_interface = ath9k_remove_interface,
2046 .config = ath9k_config,
8feceb67 2047 .configure_filter = ath9k_configure_filter,
8feceb67
VT
2048 .sta_notify = ath9k_sta_notify,
2049 .conf_tx = ath9k_conf_tx,
8feceb67 2050 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2051 .set_key = ath9k_set_key,
8feceb67 2052 .get_tsf = ath9k_get_tsf,
3b5d665b 2053 .set_tsf = ath9k_set_tsf,
8feceb67 2054 .reset_tsf = ath9k_reset_tsf,
4233df6b 2055 .ampdu_action = ath9k_ampdu_action,
0c98de65
S
2056 .sw_scan_start = ath9k_sw_scan_start,
2057 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2058 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2059 .set_coverage_class = ath9k_set_coverage_class,
8feceb67 2060};
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