Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
ff37e337 S |
22 | static u8 parse_mpdudensity(u8 mpdudensity) |
23 | { | |
24 | /* | |
25 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
26 | * 0 for no restriction | |
27 | * 1 for 1/4 us | |
28 | * 2 for 1/2 us | |
29 | * 3 for 1 us | |
30 | * 4 for 2 us | |
31 | * 5 for 4 us | |
32 | * 6 for 8 us | |
33 | * 7 for 16 us | |
34 | */ | |
35 | switch (mpdudensity) { | |
36 | case 0: | |
37 | return 0; | |
38 | case 1: | |
39 | case 2: | |
40 | case 3: | |
41 | /* Our lower layer calculations limit our precision to | |
42 | 1 microsecond */ | |
43 | return 1; | |
44 | case 4: | |
45 | return 2; | |
46 | case 5: | |
47 | return 4; | |
48 | case 6: | |
49 | return 8; | |
50 | case 7: | |
51 | return 16; | |
52 | default: | |
53 | return 0; | |
54 | } | |
55 | } | |
56 | ||
69081624 VT |
57 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
58 | { | |
59 | bool pending = false; | |
60 | ||
61 | spin_lock_bh(&txq->axq_lock); | |
62 | ||
63 | if (txq->axq_depth || !list_empty(&txq->axq_acq)) | |
64 | pending = true; | |
69081624 VT |
65 | |
66 | spin_unlock_bh(&txq->axq_lock); | |
67 | return pending; | |
68 | } | |
69 | ||
6d79cb4c | 70 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
71 | { |
72 | unsigned long flags; | |
73 | bool ret; | |
74 | ||
9ecdef4b LR |
75 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
76 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
77 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
78 | |
79 | return ret; | |
80 | } | |
81 | ||
a91d75ae LR |
82 | void ath9k_ps_wakeup(struct ath_softc *sc) |
83 | { | |
898c914a | 84 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 85 | unsigned long flags; |
fbb078fc | 86 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
87 | |
88 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
89 | if (++sc->ps_usecount != 1) | |
90 | goto unlock; | |
91 | ||
fbb078fc | 92 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 93 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 94 | |
898c914a FF |
95 | /* |
96 | * While the hardware is asleep, the cycle counters contain no | |
97 | * useful data. Better clear them now so that they don't mess up | |
98 | * survey data results. | |
99 | */ | |
fbb078fc FF |
100 | if (power_mode != ATH9K_PM_AWAKE) { |
101 | spin_lock(&common->cc_lock); | |
102 | ath_hw_cycle_counters_update(common); | |
103 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
104 | spin_unlock(&common->cc_lock); | |
105 | } | |
898c914a | 106 | |
a91d75ae LR |
107 | unlock: |
108 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
109 | } | |
110 | ||
111 | void ath9k_ps_restore(struct ath_softc *sc) | |
112 | { | |
898c914a | 113 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c6c539f0 | 114 | enum ath9k_power_mode mode; |
a91d75ae LR |
115 | unsigned long flags; |
116 | ||
117 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
118 | if (--sc->ps_usecount != 0) | |
119 | goto unlock; | |
120 | ||
1dbfd9d4 | 121 | if (sc->ps_idle) |
c6c539f0 | 122 | mode = ATH9K_PM_FULL_SLEEP; |
1dbfd9d4 VN |
123 | else if (sc->ps_enabled && |
124 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
125 | PS_WAIT_FOR_CAB | |
126 | PS_WAIT_FOR_PSPOLL_DATA | | |
127 | PS_WAIT_FOR_TX_ACK))) | |
c6c539f0 FF |
128 | mode = ATH9K_PM_NETWORK_SLEEP; |
129 | else | |
130 | goto unlock; | |
131 | ||
132 | spin_lock(&common->cc_lock); | |
133 | ath_hw_cycle_counters_update(common); | |
134 | spin_unlock(&common->cc_lock); | |
135 | ||
1a8f0d39 | 136 | ath9k_hw_setpower(sc->sc_ah, mode); |
a91d75ae LR |
137 | |
138 | unlock: | |
139 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
140 | } | |
141 | ||
05c0be2f | 142 | void ath_start_ani(struct ath_common *common) |
5ee08656 FF |
143 | { |
144 | struct ath_hw *ah = common->ah; | |
145 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
146 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
147 | ||
148 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
149 | return; | |
150 | ||
151 | if (sc->sc_flags & SC_OP_OFFCHANNEL) | |
152 | return; | |
153 | ||
154 | common->ani.longcal_timer = timestamp; | |
155 | common->ani.shortcal_timer = timestamp; | |
156 | common->ani.checkani_timer = timestamp; | |
157 | ||
158 | mod_timer(&common->ani.timer, | |
159 | jiffies + | |
160 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
161 | } | |
162 | ||
3430098a FF |
163 | static void ath_update_survey_nf(struct ath_softc *sc, int channel) |
164 | { | |
165 | struct ath_hw *ah = sc->sc_ah; | |
166 | struct ath9k_channel *chan = &ah->channels[channel]; | |
167 | struct survey_info *survey = &sc->survey[channel]; | |
168 | ||
169 | if (chan->noisefloor) { | |
170 | survey->filled |= SURVEY_INFO_NOISE_DBM; | |
f749b946 | 171 | survey->noise = ath9k_hw_getchan_noise(ah, chan); |
3430098a FF |
172 | } |
173 | } | |
174 | ||
cb8d61de FF |
175 | /* |
176 | * Updates the survey statistics and returns the busy time since last | |
177 | * update in %, if the measurement duration was long enough for the | |
178 | * result to be useful, -1 otherwise. | |
179 | */ | |
180 | static int ath_update_survey_stats(struct ath_softc *sc) | |
3430098a FF |
181 | { |
182 | struct ath_hw *ah = sc->sc_ah; | |
183 | struct ath_common *common = ath9k_hw_common(ah); | |
184 | int pos = ah->curchan - &ah->channels[0]; | |
185 | struct survey_info *survey = &sc->survey[pos]; | |
186 | struct ath_cycle_counters *cc = &common->cc_survey; | |
187 | unsigned int div = common->clockrate * 1000; | |
cb8d61de | 188 | int ret = 0; |
3430098a | 189 | |
0845735e | 190 | if (!ah->curchan) |
cb8d61de | 191 | return -1; |
0845735e | 192 | |
898c914a FF |
193 | if (ah->power_mode == ATH9K_PM_AWAKE) |
194 | ath_hw_cycle_counters_update(common); | |
3430098a FF |
195 | |
196 | if (cc->cycles > 0) { | |
197 | survey->filled |= SURVEY_INFO_CHANNEL_TIME | | |
198 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
199 | SURVEY_INFO_CHANNEL_TIME_RX | | |
200 | SURVEY_INFO_CHANNEL_TIME_TX; | |
201 | survey->channel_time += cc->cycles / div; | |
202 | survey->channel_time_busy += cc->rx_busy / div; | |
203 | survey->channel_time_rx += cc->rx_frame / div; | |
204 | survey->channel_time_tx += cc->tx_frame / div; | |
205 | } | |
cb8d61de FF |
206 | |
207 | if (cc->cycles < div) | |
208 | return -1; | |
209 | ||
210 | if (cc->cycles > 0) | |
211 | ret = cc->rx_busy * 100 / cc->cycles; | |
212 | ||
3430098a FF |
213 | memset(cc, 0, sizeof(*cc)); |
214 | ||
215 | ath_update_survey_nf(sc, pos); | |
cb8d61de FF |
216 | |
217 | return ret; | |
3430098a FF |
218 | } |
219 | ||
9adcf440 | 220 | static void __ath_cancel_work(struct ath_softc *sc) |
ff37e337 | 221 | { |
5ee08656 FF |
222 | cancel_work_sync(&sc->paprd_work); |
223 | cancel_work_sync(&sc->hw_check_work); | |
224 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
181fb18d | 225 | cancel_delayed_work_sync(&sc->hw_pll_work); |
9adcf440 | 226 | } |
5ee08656 | 227 | |
9adcf440 FF |
228 | static void ath_cancel_work(struct ath_softc *sc) |
229 | { | |
230 | __ath_cancel_work(sc); | |
231 | cancel_work_sync(&sc->hw_reset_work); | |
232 | } | |
3cbb5dd7 | 233 | |
9adcf440 FF |
234 | static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) |
235 | { | |
236 | struct ath_hw *ah = sc->sc_ah; | |
237 | struct ath_common *common = ath9k_hw_common(ah); | |
238 | bool ret; | |
6a6733f2 | 239 | |
9adcf440 | 240 | ieee80211_stop_queues(sc->hw); |
5e848f78 | 241 | |
9adcf440 FF |
242 | sc->hw_busy_count = 0; |
243 | del_timer_sync(&common->ani.timer); | |
ff37e337 | 244 | |
9adcf440 FF |
245 | ath9k_debug_samp_bb_mac(sc); |
246 | ath9k_hw_disable_interrupts(ah); | |
8b3f4616 | 247 | |
9adcf440 | 248 | ret = ath_drain_all_txq(sc, retry_tx); |
ff37e337 | 249 | |
9adcf440 FF |
250 | if (!ath_stoprecv(sc)) |
251 | ret = false; | |
c0d7c7af | 252 | |
9adcf440 FF |
253 | if (!flush) { |
254 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
3483288c FF |
255 | ath_rx_tasklet(sc, 1, true); |
256 | ath_rx_tasklet(sc, 1, false); | |
9adcf440 FF |
257 | } else { |
258 | ath_flushrecv(sc); | |
259 | } | |
20bd2a09 | 260 | |
9adcf440 FF |
261 | return ret; |
262 | } | |
ff37e337 | 263 | |
9adcf440 FF |
264 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
265 | { | |
266 | struct ath_hw *ah = sc->sc_ah; | |
267 | struct ath_common *common = ath9k_hw_common(ah); | |
c0d7c7af | 268 | |
c0d7c7af | 269 | if (ath_startrecv(sc) != 0) { |
3800276a | 270 | ath_err(common, "Unable to restart recv logic\n"); |
9adcf440 | 271 | return false; |
c0d7c7af LR |
272 | } |
273 | ||
5048e8c3 RM |
274 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
275 | sc->config.txpowlimit, &sc->curtxpow); | |
3069168c | 276 | ath9k_hw_set_interrupts(ah, ah->imask); |
b037b693 | 277 | ath9k_hw_enable_interrupts(ah); |
3989279c | 278 | |
9adcf440 | 279 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) { |
1186488b | 280 | if (sc->sc_flags & SC_OP_BEACONS) |
99e4d43a | 281 | ath_set_beacon(sc); |
9adcf440 | 282 | |
5ee08656 | 283 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
181fb18d | 284 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2); |
05c0be2f MSS |
285 | if (!common->disable_ani) |
286 | ath_start_ani(common); | |
5ee08656 FF |
287 | } |
288 | ||
43c35284 FF |
289 | if (ath9k_hw_ops(ah)->antdiv_comb_conf_get && sc->ant_rx != 3) { |
290 | struct ath_hw_antcomb_conf div_ant_conf; | |
291 | u8 lna_conf; | |
292 | ||
293 | ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf); | |
294 | ||
295 | if (sc->ant_rx == 1) | |
296 | lna_conf = ATH_ANT_DIV_COMB_LNA1; | |
297 | else | |
298 | lna_conf = ATH_ANT_DIV_COMB_LNA2; | |
299 | div_ant_conf.main_lna_conf = lna_conf; | |
300 | div_ant_conf.alt_lna_conf = lna_conf; | |
301 | ||
302 | ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf); | |
303 | } | |
304 | ||
9adcf440 FF |
305 | ieee80211_wake_queues(sc->hw); |
306 | ||
307 | return true; | |
308 | } | |
309 | ||
310 | static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, | |
311 | bool retry_tx) | |
312 | { | |
313 | struct ath_hw *ah = sc->sc_ah; | |
314 | struct ath_common *common = ath9k_hw_common(ah); | |
315 | struct ath9k_hw_cal_data *caldata = NULL; | |
316 | bool fastcc = true; | |
317 | bool flush = false; | |
318 | int r; | |
319 | ||
320 | __ath_cancel_work(sc); | |
321 | ||
322 | spin_lock_bh(&sc->sc_pcu_lock); | |
92460412 | 323 | |
9adcf440 FF |
324 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) { |
325 | fastcc = false; | |
326 | caldata = &sc->caldata; | |
327 | } | |
328 | ||
329 | if (!hchan) { | |
330 | fastcc = false; | |
331 | flush = true; | |
332 | hchan = ah->curchan; | |
333 | } | |
334 | ||
335 | if (fastcc && !ath9k_hw_check_alive(ah)) | |
336 | fastcc = false; | |
337 | ||
338 | if (!ath_prepare_reset(sc, retry_tx, flush)) | |
339 | fastcc = false; | |
340 | ||
341 | ath_dbg(common, ATH_DBG_CONFIG, | |
342 | "Reset to %u MHz, HT40: %d fastcc: %d\n", | |
343 | hchan->channel, !!(hchan->channelFlags & (CHANNEL_HT40MINUS | | |
344 | CHANNEL_HT40PLUS)), | |
345 | fastcc); | |
346 | ||
347 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | |
348 | if (r) { | |
349 | ath_err(common, | |
350 | "Unable to reset channel, reset status %d\n", r); | |
351 | goto out; | |
352 | } | |
353 | ||
354 | if (!ath_complete_reset(sc, true)) | |
355 | r = -EIO; | |
356 | ||
357 | out: | |
6a6733f2 | 358 | spin_unlock_bh(&sc->sc_pcu_lock); |
9adcf440 FF |
359 | return r; |
360 | } | |
361 | ||
362 | ||
363 | /* | |
364 | * Set/change channels. If the channel is really being changed, it's done | |
365 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
366 | * DMA, then restart stuff. | |
367 | */ | |
368 | static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
369 | struct ath9k_channel *hchan) | |
370 | { | |
371 | int r; | |
372 | ||
373 | if (sc->sc_flags & SC_OP_INVALID) | |
374 | return -EIO; | |
375 | ||
376 | ath9k_ps_wakeup(sc); | |
377 | ||
378 | r = ath_reset_internal(sc, hchan, false); | |
6a6733f2 | 379 | |
3cbb5dd7 | 380 | ath9k_ps_restore(sc); |
9adcf440 | 381 | |
3989279c | 382 | return r; |
ff37e337 S |
383 | } |
384 | ||
9f42c2b6 FF |
385 | static void ath_paprd_activate(struct ath_softc *sc) |
386 | { | |
387 | struct ath_hw *ah = sc->sc_ah; | |
20bd2a09 | 388 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9f42c2b6 FF |
389 | int chain; |
390 | ||
20bd2a09 | 391 | if (!caldata || !caldata->paprd_done) |
9f42c2b6 FF |
392 | return; |
393 | ||
394 | ath9k_ps_wakeup(sc); | |
ddfef792 | 395 | ar9003_paprd_enable(ah, false); |
9f42c2b6 | 396 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
82b2d334 | 397 | if (!(ah->txchainmask & BIT(chain))) |
9f42c2b6 FF |
398 | continue; |
399 | ||
20bd2a09 | 400 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
9f42c2b6 FF |
401 | } |
402 | ||
403 | ar9003_paprd_enable(ah, true); | |
404 | ath9k_ps_restore(sc); | |
405 | } | |
406 | ||
7607cbe2 FF |
407 | static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain) |
408 | { | |
409 | struct ieee80211_hw *hw = sc->hw; | |
410 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
47960077 MSS |
411 | struct ath_hw *ah = sc->sc_ah; |
412 | struct ath_common *common = ath9k_hw_common(ah); | |
7607cbe2 FF |
413 | struct ath_tx_control txctl; |
414 | int time_left; | |
415 | ||
416 | memset(&txctl, 0, sizeof(txctl)); | |
417 | txctl.txq = sc->tx.txq_map[WME_AC_BE]; | |
418 | ||
419 | memset(tx_info, 0, sizeof(*tx_info)); | |
420 | tx_info->band = hw->conf.channel->band; | |
421 | tx_info->flags |= IEEE80211_TX_CTL_NO_ACK; | |
422 | tx_info->control.rates[0].idx = 0; | |
423 | tx_info->control.rates[0].count = 1; | |
424 | tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS; | |
425 | tx_info->control.rates[1].idx = -1; | |
426 | ||
427 | init_completion(&sc->paprd_complete); | |
7607cbe2 | 428 | txctl.paprd = BIT(chain); |
47960077 MSS |
429 | |
430 | if (ath_tx_start(hw, skb, &txctl) != 0) { | |
d4bb17c4 | 431 | ath_dbg(common, ATH_DBG_CALIBRATE, "PAPRD TX failed\n"); |
47960077 | 432 | dev_kfree_skb_any(skb); |
7607cbe2 | 433 | return false; |
47960077 | 434 | } |
7607cbe2 FF |
435 | |
436 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
437 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); | |
7607cbe2 FF |
438 | |
439 | if (!time_left) | |
d4bb17c4 | 440 | ath_dbg(common, ATH_DBG_CALIBRATE, |
7607cbe2 FF |
441 | "Timeout waiting for paprd training on TX chain %d\n", |
442 | chain); | |
443 | ||
444 | return !!time_left; | |
445 | } | |
446 | ||
9f42c2b6 FF |
447 | void ath_paprd_calibrate(struct work_struct *work) |
448 | { | |
449 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
450 | struct ieee80211_hw *hw = sc->hw; | |
451 | struct ath_hw *ah = sc->sc_ah; | |
452 | struct ieee80211_hdr *hdr; | |
453 | struct sk_buff *skb = NULL; | |
20bd2a09 | 454 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 455 | struct ath_common *common = ath9k_hw_common(ah); |
066dae93 | 456 | int ftype; |
9f42c2b6 FF |
457 | int chain_ok = 0; |
458 | int chain; | |
459 | int len = 1800; | |
9f42c2b6 | 460 | |
20bd2a09 FF |
461 | if (!caldata) |
462 | return; | |
463 | ||
b942471b MSS |
464 | ath9k_ps_wakeup(sc); |
465 | ||
1bf38661 | 466 | if (ar9003_paprd_init_table(ah) < 0) |
b942471b | 467 | goto fail_paprd; |
1bf38661 | 468 | |
9f42c2b6 FF |
469 | skb = alloc_skb(len, GFP_KERNEL); |
470 | if (!skb) | |
b942471b | 471 | goto fail_paprd; |
9f42c2b6 | 472 | |
9f42c2b6 FF |
473 | skb_put(skb, len); |
474 | memset(skb->data, 0, len); | |
475 | hdr = (struct ieee80211_hdr *)skb->data; | |
476 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
477 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 478 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
479 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
480 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
481 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
482 | ||
9f42c2b6 | 483 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
82b2d334 | 484 | if (!(ah->txchainmask & BIT(chain))) |
9f42c2b6 FF |
485 | continue; |
486 | ||
487 | chain_ok = 0; | |
9f42c2b6 | 488 | |
7607cbe2 FF |
489 | ath_dbg(common, ATH_DBG_CALIBRATE, |
490 | "Sending PAPRD frame for thermal measurement " | |
491 | "on chain %d\n", chain); | |
492 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
493 | goto fail_paprd; | |
9f42c2b6 | 494 | |
9f42c2b6 | 495 | ar9003_paprd_setup_gain_table(ah, chain); |
9f42c2b6 | 496 | |
7607cbe2 FF |
497 | ath_dbg(common, ATH_DBG_CALIBRATE, |
498 | "Sending PAPRD training frame on chain %d\n", chain); | |
499 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
ca369eb4 | 500 | goto fail_paprd; |
9f42c2b6 | 501 | |
d4bb17c4 MSS |
502 | if (!ar9003_paprd_is_done(ah)) { |
503 | ath_dbg(common, ATH_DBG_CALIBRATE, | |
504 | "PAPRD not yet done on chain %d\n", chain); | |
9f42c2b6 | 505 | break; |
d4bb17c4 | 506 | } |
9f42c2b6 | 507 | |
d4bb17c4 MSS |
508 | if (ar9003_paprd_create_curve(ah, caldata, chain)) { |
509 | ath_dbg(common, ATH_DBG_CALIBRATE, | |
510 | "PAPRD create curve failed on chain %d\n", | |
511 | chain); | |
9f42c2b6 | 512 | break; |
d4bb17c4 | 513 | } |
9f42c2b6 FF |
514 | |
515 | chain_ok = 1; | |
516 | } | |
517 | kfree_skb(skb); | |
518 | ||
519 | if (chain_ok) { | |
20bd2a09 | 520 | caldata->paprd_done = true; |
9f42c2b6 FF |
521 | ath_paprd_activate(sc); |
522 | } | |
523 | ||
ca369eb4 | 524 | fail_paprd: |
9f42c2b6 FF |
525 | ath9k_ps_restore(sc); |
526 | } | |
527 | ||
ff37e337 S |
528 | /* |
529 | * This routine performs the periodic noise floor calibration function | |
530 | * that is used to adjust and optimize the chip performance. This | |
531 | * takes environmental changes (location, temperature) into account. | |
532 | * When the task is complete, it reschedules itself depending on the | |
533 | * appropriate interval that was calculated. | |
534 | */ | |
55624204 | 535 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 536 | { |
20977d3e S |
537 | struct ath_softc *sc = (struct ath_softc *)data; |
538 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 539 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
540 | bool longcal = false; |
541 | bool shortcal = false; | |
542 | bool aniflag = false; | |
543 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
6044474e | 544 | u32 cal_interval, short_cal_interval, long_cal_interval; |
b5bfc568 | 545 | unsigned long flags; |
6044474e FF |
546 | |
547 | if (ah->caldata && ah->caldata->nfcal_interference) | |
548 | long_cal_interval = ATH_LONG_CALINTERVAL_INT; | |
549 | else | |
550 | long_cal_interval = ATH_LONG_CALINTERVAL; | |
ff37e337 | 551 | |
20977d3e S |
552 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
553 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 554 | |
1ffc1c61 JM |
555 | /* Only calibrate if awake */ |
556 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
557 | goto set_timer; | |
558 | ||
559 | ath9k_ps_wakeup(sc); | |
560 | ||
ff37e337 | 561 | /* Long calibration runs independently of short calibration. */ |
6044474e | 562 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
ff37e337 | 563 | longcal = true; |
226afe68 | 564 | ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 565 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
566 | } |
567 | ||
17d7904d | 568 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
569 | if (!common->ani.caldone) { |
570 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 571 | shortcal = true; |
226afe68 JP |
572 | ath_dbg(common, ATH_DBG_ANI, |
573 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
574 | common->ani.shortcal_timer = timestamp; |
575 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
576 | } |
577 | } else { | |
3d536acf | 578 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 579 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
580 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
581 | if (common->ani.caldone) | |
582 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
583 | } |
584 | } | |
585 | ||
586 | /* Verify whether we must check ANI */ | |
e36b27af LR |
587 | if ((timestamp - common->ani.checkani_timer) >= |
588 | ah->config.ani_poll_interval) { | |
ff37e337 | 589 | aniflag = true; |
3d536acf | 590 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
591 | } |
592 | ||
e62ddec9 MSS |
593 | /* Call ANI routine if necessary */ |
594 | if (aniflag) { | |
595 | spin_lock_irqsave(&common->cc_lock, flags); | |
596 | ath9k_hw_ani_monitor(ah, ah->curchan); | |
597 | ath_update_survey_stats(sc); | |
598 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
599 | } | |
ff37e337 | 600 | |
e62ddec9 MSS |
601 | /* Perform calibration if necessary */ |
602 | if (longcal || shortcal) { | |
603 | common->ani.caldone = | |
604 | ath9k_hw_calibrate(ah, ah->curchan, | |
82b2d334 | 605 | ah->rxchainmask, longcal); |
ff37e337 S |
606 | } |
607 | ||
1ffc1c61 JM |
608 | ath9k_ps_restore(sc); |
609 | ||
20977d3e | 610 | set_timer: |
ff37e337 S |
611 | /* |
612 | * Set timer interval based on previous results. | |
613 | * The interval must be the shortest necessary to satisfy ANI, | |
614 | * short calibration and long calibration. | |
615 | */ | |
cf3af748 | 616 | ath9k_debug_samp_bb_mac(sc); |
aac9207e | 617 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 618 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
619 | cal_interval = min(cal_interval, |
620 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 621 | if (!common->ani.caldone) |
20977d3e | 622 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 623 | |
3d536acf | 624 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
20bd2a09 FF |
625 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { |
626 | if (!ah->caldata->paprd_done) | |
9f42c2b6 | 627 | ieee80211_queue_work(sc->hw, &sc->paprd_work); |
45ef6a0b | 628 | else if (!ah->paprd_table_write_done) |
9f42c2b6 FF |
629 | ath_paprd_activate(sc); |
630 | } | |
ff37e337 S |
631 | } |
632 | ||
ff37e337 S |
633 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) |
634 | { | |
635 | struct ath_node *an; | |
ff37e337 S |
636 | an = (struct ath_node *)sta->drv_priv; |
637 | ||
7f010c93 BG |
638 | #ifdef CONFIG_ATH9K_DEBUGFS |
639 | spin_lock(&sc->nodes_lock); | |
640 | list_add(&an->list, &sc->nodes); | |
641 | spin_unlock(&sc->nodes_lock); | |
642 | an->sta = sta; | |
643 | #endif | |
87792efc | 644 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 645 | ath_tx_node_init(sc, an); |
9e98ac65 | 646 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
647 | sta->ht_cap.ampdu_factor); |
648 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
649 | } | |
ff37e337 S |
650 | } |
651 | ||
652 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
653 | { | |
654 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
655 | ||
7f010c93 BG |
656 | #ifdef CONFIG_ATH9K_DEBUGFS |
657 | spin_lock(&sc->nodes_lock); | |
658 | list_del(&an->list); | |
659 | spin_unlock(&sc->nodes_lock); | |
660 | an->sta = NULL; | |
661 | #endif | |
662 | ||
ff37e337 S |
663 | if (sc->sc_flags & SC_OP_TXAGGR) |
664 | ath_tx_node_cleanup(sc, an); | |
665 | } | |
666 | ||
9eab61c2 | 667 | |
55624204 | 668 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
669 | { |
670 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 671 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 672 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 673 | |
17d7904d | 674 | u32 status = sc->intrstatus; |
b5c80475 | 675 | u32 rxmask; |
ff37e337 | 676 | |
e3927007 FF |
677 | ath9k_ps_wakeup(sc); |
678 | spin_lock(&sc->sc_pcu_lock); | |
679 | ||
a4d86d95 RM |
680 | if ((status & ATH9K_INT_FATAL) || |
681 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
236de514 | 682 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
e3927007 | 683 | goto out; |
063d8be3 | 684 | } |
ff37e337 | 685 | |
8b3f4616 FF |
686 | /* |
687 | * Only run the baseband hang check if beacons stop working in AP or | |
688 | * IBSS mode, because it has a high false positive rate. For station | |
689 | * mode it should not be necessary, since the upper layers will detect | |
690 | * this through a beacon miss automatically and the following channel | |
691 | * change will trigger a hardware reset anyway | |
692 | */ | |
693 | if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 && | |
694 | !ath9k_hw_check_alive(ah)) | |
347809fc FF |
695 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); |
696 | ||
4105f807 RM |
697 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
698 | /* | |
699 | * TSF sync does not look correct; remain awake to sync with | |
700 | * the next Beacon. | |
701 | */ | |
702 | ath_dbg(common, ATH_DBG_PS, | |
703 | "TSFOOR - Sync with next Beacon\n"); | |
e8fe7336 | 704 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
4105f807 RM |
705 | } |
706 | ||
b5c80475 FF |
707 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
708 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
709 | ATH9K_INT_RXORN); | |
710 | else | |
711 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
712 | ||
713 | if (status & rxmask) { | |
b5c80475 FF |
714 | /* Check for high priority Rx first */ |
715 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
716 | (status & ATH9K_INT_RXHP)) | |
717 | ath_rx_tasklet(sc, 0, true); | |
718 | ||
719 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
720 | } |
721 | ||
e5003249 VT |
722 | if (status & ATH9K_INT_TX) { |
723 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
724 | ath_tx_edma_tasklet(sc); | |
725 | else | |
726 | ath_tx_tasklet(sc); | |
727 | } | |
063d8be3 | 728 | |
766ec4a9 | 729 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
730 | if (status & ATH9K_INT_GENTIMER) |
731 | ath_gen_timer_isr(sc->sc_ah); | |
732 | ||
e3927007 | 733 | out: |
ff37e337 | 734 | /* re-enable hardware interrupt */ |
4df3071e | 735 | ath9k_hw_enable_interrupts(ah); |
6a6733f2 | 736 | |
52671e43 | 737 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 738 | ath9k_ps_restore(sc); |
ff37e337 S |
739 | } |
740 | ||
6baff7f9 | 741 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 742 | { |
063d8be3 S |
743 | #define SCHED_INTR ( \ |
744 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 745 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
746 | ATH9K_INT_RXORN | \ |
747 | ATH9K_INT_RXEOL | \ | |
748 | ATH9K_INT_RX | \ | |
b5c80475 FF |
749 | ATH9K_INT_RXLP | \ |
750 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
751 | ATH9K_INT_TX | \ |
752 | ATH9K_INT_BMISS | \ | |
753 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
754 | ATH9K_INT_TSFOOR | \ |
755 | ATH9K_INT_GENTIMER) | |
063d8be3 | 756 | |
ff37e337 | 757 | struct ath_softc *sc = dev; |
cbe61d8a | 758 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 759 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
760 | enum ath9k_int status; |
761 | bool sched = false; | |
762 | ||
063d8be3 S |
763 | /* |
764 | * The hardware is not ready/present, don't | |
765 | * touch anything. Note this can happen early | |
766 | * on if the IRQ is shared. | |
767 | */ | |
768 | if (sc->sc_flags & SC_OP_INVALID) | |
769 | return IRQ_NONE; | |
ff37e337 | 770 | |
063d8be3 S |
771 | |
772 | /* shared irq, not for us */ | |
773 | ||
153e080d | 774 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 775 | return IRQ_NONE; |
063d8be3 S |
776 | |
777 | /* | |
778 | * Figure out the reason(s) for the interrupt. Note | |
779 | * that the hal returns a pseudo-ISR that may include | |
780 | * bits we haven't explicitly enabled so we mask the | |
781 | * value to insure we only process bits we requested. | |
782 | */ | |
783 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 784 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 785 | |
063d8be3 S |
786 | /* |
787 | * If there are no status bits set, then this interrupt was not | |
788 | * for me (should have been caught above). | |
789 | */ | |
153e080d | 790 | if (!status) |
063d8be3 | 791 | return IRQ_NONE; |
ff37e337 | 792 | |
063d8be3 S |
793 | /* Cache the status */ |
794 | sc->intrstatus = status; | |
795 | ||
796 | if (status & SCHED_INTR) | |
797 | sched = true; | |
798 | ||
799 | /* | |
800 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
801 | * chip immediately. | |
802 | */ | |
b5c80475 FF |
803 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
804 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
805 | goto chip_reset; |
806 | ||
08578b8f LR |
807 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
808 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
809 | |
810 | spin_lock(&common->cc_lock); | |
811 | ath_hw_cycle_counters_update(common); | |
08578b8f | 812 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
813 | spin_unlock(&common->cc_lock); |
814 | ||
08578b8f LR |
815 | goto chip_reset; |
816 | } | |
817 | ||
063d8be3 S |
818 | if (status & ATH9K_INT_SWBA) |
819 | tasklet_schedule(&sc->bcon_tasklet); | |
820 | ||
821 | if (status & ATH9K_INT_TXURN) | |
822 | ath9k_hw_updatetxtriglevel(ah, true); | |
823 | ||
0682c9b5 RM |
824 | if (status & ATH9K_INT_RXEOL) { |
825 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
826 | ath9k_hw_set_interrupts(ah, ah->imask); | |
b5c80475 FF |
827 | } |
828 | ||
063d8be3 | 829 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 830 | /* |
063d8be3 S |
831 | * Disable interrupts until we service the MIB |
832 | * interrupt; otherwise it will continue to | |
833 | * fire. | |
ff37e337 | 834 | */ |
4df3071e | 835 | ath9k_hw_disable_interrupts(ah); |
063d8be3 S |
836 | /* |
837 | * Let the hal handle the event. We assume | |
838 | * it will clear whatever condition caused | |
839 | * the interrupt. | |
840 | */ | |
88eac2da | 841 | spin_lock(&common->cc_lock); |
bfc472bb | 842 | ath9k_hw_proc_mib_event(ah); |
88eac2da | 843 | spin_unlock(&common->cc_lock); |
4df3071e | 844 | ath9k_hw_enable_interrupts(ah); |
063d8be3 | 845 | } |
ff37e337 | 846 | |
153e080d VT |
847 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
848 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
849 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
850 | goto chip_reset; | |
063d8be3 S |
851 | /* Clear RxAbort bit so that we can |
852 | * receive frames */ | |
9ecdef4b | 853 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 854 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 855 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 856 | } |
063d8be3 S |
857 | |
858 | chip_reset: | |
ff37e337 | 859 | |
817e11de S |
860 | ath_debug_stat_interrupt(sc, status); |
861 | ||
ff37e337 | 862 | if (sched) { |
4df3071e FF |
863 | /* turn off every interrupt */ |
864 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
865 | tasklet_schedule(&sc->intr_tq); |
866 | } | |
867 | ||
868 | return IRQ_HANDLED; | |
063d8be3 S |
869 | |
870 | #undef SCHED_INTR | |
ff37e337 S |
871 | } |
872 | ||
5595f119 | 873 | static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 874 | { |
cbe61d8a | 875 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 876 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 877 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 878 | int r; |
500c064d | 879 | |
3cbb5dd7 | 880 | ath9k_ps_wakeup(sc); |
6a6733f2 | 881 | spin_lock_bh(&sc->sc_pcu_lock); |
e8fe7336 | 882 | atomic_set(&ah->intr_ref_cnt, -1); |
6a6733f2 | 883 | |
84c87dc8 | 884 | ath9k_hw_configpcipowersave(ah, false); |
ae8d2858 | 885 | |
159cd468 | 886 | if (!ah->curchan) |
c344c9cb | 887 | ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah); |
159cd468 | 888 | |
20bd2a09 | 889 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 890 | if (r) { |
3800276a JP |
891 | ath_err(common, |
892 | "Unable to reset channel (%u MHz), reset status %d\n", | |
893 | channel->center_freq, r); | |
500c064d | 894 | } |
500c064d | 895 | |
9adcf440 | 896 | ath_complete_reset(sc, true); |
500c064d VT |
897 | |
898 | /* Enable LED */ | |
08fc5c1b | 899 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 900 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 901 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 902 | |
6a6733f2 LR |
903 | spin_unlock_bh(&sc->sc_pcu_lock); |
904 | ||
3cbb5dd7 | 905 | ath9k_ps_restore(sc); |
500c064d VT |
906 | } |
907 | ||
68a89116 | 908 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 909 | { |
cbe61d8a | 910 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 911 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 912 | int r; |
500c064d | 913 | |
3cbb5dd7 | 914 | ath9k_ps_wakeup(sc); |
7e3514fd | 915 | |
9adcf440 | 916 | ath_cancel_work(sc); |
6a6733f2 | 917 | |
9adcf440 | 918 | spin_lock_bh(&sc->sc_pcu_lock); |
500c064d | 919 | |
982723df VN |
920 | /* |
921 | * Keep the LED on when the radio is disabled | |
922 | * during idle unassociated state. | |
923 | */ | |
924 | if (!sc->ps_idle) { | |
925 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
926 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
927 | } | |
500c064d | 928 | |
9adcf440 | 929 | ath_prepare_reset(sc, false, true); |
500c064d | 930 | |
159cd468 | 931 | if (!ah->curchan) |
c344c9cb | 932 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); |
159cd468 | 933 | |
20bd2a09 | 934 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 935 | if (r) { |
3800276a JP |
936 | ath_err(ath9k_hw_common(sc->sc_ah), |
937 | "Unable to reset channel (%u MHz), reset status %d\n", | |
938 | channel->center_freq, r); | |
500c064d | 939 | } |
500c064d VT |
940 | |
941 | ath9k_hw_phy_disable(ah); | |
5e848f78 | 942 | |
84c87dc8 | 943 | ath9k_hw_configpcipowersave(ah, true); |
6a6733f2 LR |
944 | |
945 | spin_unlock_bh(&sc->sc_pcu_lock); | |
3cbb5dd7 | 946 | ath9k_ps_restore(sc); |
500c064d VT |
947 | } |
948 | ||
236de514 | 949 | static int ath_reset(struct ath_softc *sc, bool retry_tx) |
ff37e337 | 950 | { |
ae8d2858 | 951 | int r; |
ff37e337 | 952 | |
783cd01e | 953 | ath9k_ps_wakeup(sc); |
6a6733f2 | 954 | |
9adcf440 | 955 | r = ath_reset_internal(sc, NULL, retry_tx); |
ff37e337 S |
956 | |
957 | if (retry_tx) { | |
958 | int i; | |
959 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
960 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
961 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
962 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
963 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
964 | } |
965 | } | |
966 | } | |
967 | ||
783cd01e | 968 | ath9k_ps_restore(sc); |
2ab81d4a | 969 | |
ae8d2858 | 970 | return r; |
ff37e337 S |
971 | } |
972 | ||
236de514 FF |
973 | void ath_reset_work(struct work_struct *work) |
974 | { | |
975 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | |
976 | ||
236de514 | 977 | ath_reset(sc, true); |
236de514 FF |
978 | } |
979 | ||
e8cfe9f8 FF |
980 | void ath_hw_check(struct work_struct *work) |
981 | { | |
982 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
983 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
984 | unsigned long flags; | |
985 | int busy; | |
986 | ||
987 | ath9k_ps_wakeup(sc); | |
988 | if (ath9k_hw_check_alive(sc->sc_ah)) | |
989 | goto out; | |
990 | ||
991 | spin_lock_irqsave(&common->cc_lock, flags); | |
992 | busy = ath_update_survey_stats(sc); | |
993 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
994 | ||
995 | ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, " | |
996 | "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1); | |
997 | if (busy >= 99) { | |
9adcf440 FF |
998 | if (++sc->hw_busy_count >= 3) |
999 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | |
e8cfe9f8 FF |
1000 | |
1001 | } else if (busy >= 0) | |
1002 | sc->hw_busy_count = 0; | |
1003 | ||
1004 | out: | |
1005 | ath9k_ps_restore(sc); | |
1006 | } | |
1007 | ||
1008 | static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum) | |
1009 | { | |
1010 | static int count; | |
1011 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1012 | ||
1013 | if (pll_sqsum >= 0x40000) { | |
1014 | count++; | |
1015 | if (count == 3) { | |
1016 | /* Rx is hung for more than 500ms. Reset it */ | |
1017 | ath_dbg(common, ATH_DBG_RESET, | |
1018 | "Possible RX hang, resetting"); | |
9adcf440 | 1019 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
e8cfe9f8 FF |
1020 | count = 0; |
1021 | } | |
1022 | } else | |
1023 | count = 0; | |
1024 | } | |
1025 | ||
1026 | void ath_hw_pll_work(struct work_struct *work) | |
1027 | { | |
1028 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
1029 | hw_pll_work.work); | |
1030 | u32 pll_sqsum; | |
1031 | ||
1032 | if (AR_SREV_9485(sc->sc_ah)) { | |
1033 | ||
1034 | ath9k_ps_wakeup(sc); | |
1035 | pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah); | |
1036 | ath9k_ps_restore(sc); | |
1037 | ||
1038 | ath_hw_pll_rx_hang_check(sc, pll_sqsum); | |
1039 | ||
1040 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5); | |
1041 | } | |
1042 | } | |
1043 | ||
ff37e337 S |
1044 | /**********************/ |
1045 | /* mac80211 callbacks */ | |
1046 | /**********************/ | |
1047 | ||
8feceb67 | 1048 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1049 | { |
9ac58615 | 1050 | struct ath_softc *sc = hw->priv; |
af03abec | 1051 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1052 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1053 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1054 | struct ath9k_channel *init_channel; |
82880a7c | 1055 | int r; |
f078f209 | 1056 | |
226afe68 JP |
1057 | ath_dbg(common, ATH_DBG_CONFIG, |
1058 | "Starting driver with initial channel: %d MHz\n", | |
1059 | curchan->center_freq); | |
f078f209 | 1060 | |
f62d816f FF |
1061 | ath9k_ps_wakeup(sc); |
1062 | ||
141b38b6 S |
1063 | mutex_lock(&sc->mutex); |
1064 | ||
8feceb67 | 1065 | /* setup initial channel */ |
82880a7c | 1066 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1067 | |
c344c9cb | 1068 | init_channel = ath9k_cmn_get_curchannel(hw, ah); |
ff37e337 S |
1069 | |
1070 | /* Reset SERDES registers */ | |
84c87dc8 | 1071 | ath9k_hw_configpcipowersave(ah, false); |
ff37e337 S |
1072 | |
1073 | /* | |
1074 | * The basic interface to setting the hardware in a good | |
1075 | * state is ``reset''. On return the hardware is known to | |
1076 | * be powered up and with interrupts disabled. This must | |
1077 | * be followed by initialization of the appropriate bits | |
1078 | * and then setup of the interrupt mask. | |
1079 | */ | |
4bdd1e97 | 1080 | spin_lock_bh(&sc->sc_pcu_lock); |
20bd2a09 | 1081 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 1082 | if (r) { |
3800276a JP |
1083 | ath_err(common, |
1084 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
1085 | r, curchan->center_freq); | |
4bdd1e97 | 1086 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 1087 | goto mutex_unlock; |
ff37e337 | 1088 | } |
ff37e337 | 1089 | |
ff37e337 | 1090 | /* Setup our intr mask. */ |
b5c80475 FF |
1091 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1092 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1093 | ATH9K_INT_GLOBAL; | |
1094 | ||
1095 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1096 | ah->imask |= ATH9K_INT_RXHP | |
1097 | ATH9K_INT_RXLP | | |
1098 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1099 | else |
1100 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1101 | |
364734fa | 1102 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1103 | |
af03abec | 1104 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1105 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1106 | |
ff37e337 | 1107 | sc->sc_flags &= ~SC_OP_INVALID; |
5f841b41 | 1108 | sc->sc_ah->is_monitoring = false; |
ff37e337 S |
1109 | |
1110 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c | 1111 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
ff37e337 | 1112 | |
9adcf440 FF |
1113 | if (!ath_complete_reset(sc, false)) { |
1114 | r = -EIO; | |
1115 | spin_unlock_bh(&sc->sc_pcu_lock); | |
1116 | goto mutex_unlock; | |
1117 | } | |
ff37e337 | 1118 | |
9adcf440 | 1119 | spin_unlock_bh(&sc->sc_pcu_lock); |
164ace38 | 1120 | |
766ec4a9 LR |
1121 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1122 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1123 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1124 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1125 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1126 | |
766ec4a9 | 1127 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1128 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1129 | } |
1130 | ||
8060e169 VT |
1131 | if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) |
1132 | common->bus_ops->extn_synch_en(common); | |
1133 | ||
141b38b6 S |
1134 | mutex_unlock: |
1135 | mutex_unlock(&sc->mutex); | |
1136 | ||
f62d816f FF |
1137 | ath9k_ps_restore(sc); |
1138 | ||
ae8d2858 | 1139 | return r; |
f078f209 LR |
1140 | } |
1141 | ||
7bb45683 | 1142 | static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1143 | { |
9ac58615 | 1144 | struct ath_softc *sc = hw->priv; |
c46917bb | 1145 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1146 | struct ath_tx_control txctl; |
1bc14880 | 1147 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
528f0c6b | 1148 | |
96148326 | 1149 | if (sc->ps_enabled) { |
dc8c4585 JM |
1150 | /* |
1151 | * mac80211 does not set PM field for normal data frames, so we | |
1152 | * need to update that based on the current PS mode. | |
1153 | */ | |
1154 | if (ieee80211_is_data(hdr->frame_control) && | |
1155 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1156 | !ieee80211_has_pm(hdr->frame_control)) { | |
226afe68 JP |
1157 | ath_dbg(common, ATH_DBG_PS, |
1158 | "Add PM=1 for a TX frame while in PS mode\n"); | |
dc8c4585 JM |
1159 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1160 | } | |
1161 | } | |
1162 | ||
9a23f9ca JM |
1163 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1164 | /* | |
1165 | * We are using PS-Poll and mac80211 can request TX while in | |
1166 | * power save mode. Need to wake up hardware for the TX to be | |
1167 | * completed and if needed, also for RX of buffered frames. | |
1168 | */ | |
9a23f9ca | 1169 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1170 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1171 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1172 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
226afe68 JP |
1173 | ath_dbg(common, ATH_DBG_PS, |
1174 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1175 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1176 | } else { |
226afe68 JP |
1177 | ath_dbg(common, ATH_DBG_PS, |
1178 | "Wake up to complete TX\n"); | |
1b04b930 | 1179 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1180 | } |
1181 | /* | |
1182 | * The actual restore operation will happen only after | |
1183 | * the sc_flags bit is cleared. We are just dropping | |
1184 | * the ps_usecount here. | |
1185 | */ | |
1186 | ath9k_ps_restore(sc); | |
1187 | } | |
1188 | ||
528f0c6b | 1189 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 1190 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
528f0c6b | 1191 | |
226afe68 | 1192 | ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1193 | |
c52f33d0 | 1194 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
226afe68 | 1195 | ath_dbg(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1196 | goto exit; |
8feceb67 VT |
1197 | } |
1198 | ||
7bb45683 | 1199 | return; |
528f0c6b S |
1200 | exit: |
1201 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1202 | } |
1203 | ||
8feceb67 | 1204 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1205 | { |
9ac58615 | 1206 | struct ath_softc *sc = hw->priv; |
af03abec | 1207 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1208 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1209 | |
4c483817 S |
1210 | mutex_lock(&sc->mutex); |
1211 | ||
9adcf440 | 1212 | ath_cancel_work(sc); |
c94dbff7 | 1213 | |
9c84b797 | 1214 | if (sc->sc_flags & SC_OP_INVALID) { |
226afe68 | 1215 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1216 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1217 | return; |
1218 | } | |
8feceb67 | 1219 | |
3867cf6a S |
1220 | /* Ensure HW is awake when we try to shut it down. */ |
1221 | ath9k_ps_wakeup(sc); | |
1222 | ||
766ec4a9 | 1223 | if (ah->btcoex_hw.enabled) { |
af03abec | 1224 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1225 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1226 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1227 | } |
1228 | ||
6a6733f2 LR |
1229 | spin_lock_bh(&sc->sc_pcu_lock); |
1230 | ||
203043f5 SG |
1231 | /* prevent tasklets to enable interrupts once we disable them */ |
1232 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
1233 | ||
ff37e337 S |
1234 | /* make sure h/w will not generate any interrupt |
1235 | * before setting the invalid flag. */ | |
4df3071e | 1236 | ath9k_hw_disable_interrupts(ah); |
ff37e337 S |
1237 | |
1238 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1239 | ath_drain_all_txq(sc, false); |
ff37e337 | 1240 | ath_stoprecv(sc); |
af03abec | 1241 | ath9k_hw_phy_disable(ah); |
6a6733f2 | 1242 | } else |
b77f483f | 1243 | sc->rx.rxlink = NULL; |
ff37e337 | 1244 | |
0d95521e FF |
1245 | if (sc->rx.frag) { |
1246 | dev_kfree_skb_any(sc->rx.frag); | |
1247 | sc->rx.frag = NULL; | |
1248 | } | |
1249 | ||
ff37e337 | 1250 | /* disable HAL and put h/w to sleep */ |
af03abec | 1251 | ath9k_hw_disable(ah); |
6a6733f2 LR |
1252 | |
1253 | spin_unlock_bh(&sc->sc_pcu_lock); | |
1254 | ||
203043f5 SG |
1255 | /* we can now sync irq and kill any running tasklets, since we already |
1256 | * disabled interrupts and not holding a spin lock */ | |
1257 | synchronize_irq(sc->irq); | |
1258 | tasklet_kill(&sc->intr_tq); | |
1259 | tasklet_kill(&sc->bcon_tasklet); | |
1260 | ||
3867cf6a S |
1261 | ath9k_ps_restore(sc); |
1262 | ||
a08e7ade LR |
1263 | sc->ps_idle = true; |
1264 | ath_radio_disable(sc, hw); | |
ff37e337 S |
1265 | |
1266 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1267 | |
141b38b6 S |
1268 | mutex_unlock(&sc->mutex); |
1269 | ||
226afe68 | 1270 | ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1271 | } |
1272 | ||
4801416c BG |
1273 | bool ath9k_uses_beacons(int type) |
1274 | { | |
1275 | switch (type) { | |
1276 | case NL80211_IFTYPE_AP: | |
1277 | case NL80211_IFTYPE_ADHOC: | |
1278 | case NL80211_IFTYPE_MESH_POINT: | |
1279 | return true; | |
1280 | default: | |
1281 | return false; | |
1282 | } | |
1283 | } | |
1284 | ||
1285 | static void ath9k_reclaim_beacon(struct ath_softc *sc, | |
1286 | struct ieee80211_vif *vif) | |
f078f209 | 1287 | { |
1ed32e4f | 1288 | struct ath_vif *avp = (void *)vif->drv_priv; |
8feceb67 | 1289 | |
014cf3bb | 1290 | ath9k_set_beaconing_status(sc, false); |
4801416c | 1291 | ath_beacon_return(sc, avp); |
014cf3bb | 1292 | ath9k_set_beaconing_status(sc, true); |
4801416c | 1293 | sc->sc_flags &= ~SC_OP_BEACONS; |
4801416c BG |
1294 | } |
1295 | ||
1296 | static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) | |
1297 | { | |
1298 | struct ath9k_vif_iter_data *iter_data = data; | |
1299 | int i; | |
1300 | ||
1301 | if (iter_data->hw_macaddr) | |
1302 | for (i = 0; i < ETH_ALEN; i++) | |
1303 | iter_data->mask[i] &= | |
1304 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
141b38b6 | 1305 | |
1ed32e4f | 1306 | switch (vif->type) { |
4801416c BG |
1307 | case NL80211_IFTYPE_AP: |
1308 | iter_data->naps++; | |
f078f209 | 1309 | break; |
4801416c BG |
1310 | case NL80211_IFTYPE_STATION: |
1311 | iter_data->nstations++; | |
e51f3eff | 1312 | break; |
05c914fe | 1313 | case NL80211_IFTYPE_ADHOC: |
4801416c BG |
1314 | iter_data->nadhocs++; |
1315 | break; | |
9cb5412b | 1316 | case NL80211_IFTYPE_MESH_POINT: |
4801416c BG |
1317 | iter_data->nmeshes++; |
1318 | break; | |
1319 | case NL80211_IFTYPE_WDS: | |
1320 | iter_data->nwds++; | |
f078f209 LR |
1321 | break; |
1322 | default: | |
4801416c BG |
1323 | iter_data->nothers++; |
1324 | break; | |
f078f209 | 1325 | } |
4801416c | 1326 | } |
f078f209 | 1327 | |
4801416c BG |
1328 | /* Called with sc->mutex held. */ |
1329 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
1330 | struct ieee80211_vif *vif, | |
1331 | struct ath9k_vif_iter_data *iter_data) | |
1332 | { | |
9ac58615 | 1333 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1334 | struct ath_hw *ah = sc->sc_ah; |
1335 | struct ath_common *common = ath9k_hw_common(ah); | |
8feceb67 | 1336 | |
4801416c BG |
1337 | /* |
1338 | * Use the hardware MAC address as reference, the hardware uses it | |
1339 | * together with the BSSID mask when matching addresses. | |
1340 | */ | |
1341 | memset(iter_data, 0, sizeof(*iter_data)); | |
1342 | iter_data->hw_macaddr = common->macaddr; | |
1343 | memset(&iter_data->mask, 0xff, ETH_ALEN); | |
5640b08e | 1344 | |
4801416c BG |
1345 | if (vif) |
1346 | ath9k_vif_iter(iter_data, vif->addr, vif); | |
1347 | ||
1348 | /* Get list of all active MAC addresses */ | |
4801416c BG |
1349 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, |
1350 | iter_data); | |
4801416c | 1351 | } |
8ca21f01 | 1352 | |
4801416c BG |
1353 | /* Called with sc->mutex held. */ |
1354 | static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, | |
1355 | struct ieee80211_vif *vif) | |
1356 | { | |
9ac58615 | 1357 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1358 | struct ath_hw *ah = sc->sc_ah; |
1359 | struct ath_common *common = ath9k_hw_common(ah); | |
1360 | struct ath9k_vif_iter_data iter_data; | |
8ca21f01 | 1361 | |
4801416c | 1362 | ath9k_calculate_iter_data(hw, vif, &iter_data); |
2c3db3d5 | 1363 | |
4801416c BG |
1364 | /* Set BSSID mask. */ |
1365 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); | |
1366 | ath_hw_setbssidmask(common); | |
1367 | ||
1368 | /* Set op-mode & TSF */ | |
1369 | if (iter_data.naps > 0) { | |
3069168c | 1370 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e | 1371 | sc->sc_flags |= SC_OP_TSF_RESET; |
4801416c BG |
1372 | ah->opmode = NL80211_IFTYPE_AP; |
1373 | } else { | |
1374 | ath9k_hw_set_tsfadjust(ah, 0); | |
1375 | sc->sc_flags &= ~SC_OP_TSF_RESET; | |
5640b08e | 1376 | |
fd5999cf JC |
1377 | if (iter_data.nmeshes) |
1378 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
1379 | else if (iter_data.nwds) | |
4801416c BG |
1380 | ah->opmode = NL80211_IFTYPE_AP; |
1381 | else if (iter_data.nadhocs) | |
1382 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
1383 | else | |
1384 | ah->opmode = NL80211_IFTYPE_STATION; | |
1385 | } | |
5640b08e | 1386 | |
4e30ffa2 VN |
1387 | /* |
1388 | * Enable MIB interrupts when there are hardware phy counters. | |
4e30ffa2 | 1389 | */ |
4801416c | 1390 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) { |
3448f912 LR |
1391 | if (ah->config.enable_ani) |
1392 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1393 | ah->imask |= ATH9K_INT_TSFOOR; |
4801416c BG |
1394 | } else { |
1395 | ah->imask &= ~ATH9K_INT_MIB; | |
1396 | ah->imask &= ~ATH9K_INT_TSFOOR; | |
4af9cf4f S |
1397 | } |
1398 | ||
3069168c | 1399 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1400 | |
4801416c | 1401 | /* Set up ANI */ |
2e5ef459 | 1402 | if (iter_data.naps > 0) { |
729da390 | 1403 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
05c0be2f MSS |
1404 | |
1405 | if (!common->disable_ani) { | |
1406 | sc->sc_flags |= SC_OP_ANI_RUN; | |
1407 | ath_start_ani(common); | |
1408 | } | |
1409 | ||
f60c49b6 RM |
1410 | } else { |
1411 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
1412 | del_timer_sync(&common->ani.timer); | |
6c3118e2 | 1413 | } |
4801416c | 1414 | } |
6f255425 | 1415 | |
4801416c BG |
1416 | /* Called with sc->mutex held, vif counts set up properly. */ |
1417 | static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw, | |
1418 | struct ieee80211_vif *vif) | |
1419 | { | |
9ac58615 | 1420 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1421 | |
1422 | ath9k_calculate_summary_state(hw, vif); | |
1423 | ||
1424 | if (ath9k_uses_beacons(vif->type)) { | |
1425 | int error; | |
4801416c BG |
1426 | /* This may fail because upper levels do not have beacons |
1427 | * properly configured yet. That's OK, we assume it | |
1428 | * will be properly configured and then we will be notified | |
1429 | * in the info_changed method and set up beacons properly | |
1430 | * there. | |
1431 | */ | |
014cf3bb | 1432 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 1433 | error = ath_beacon_alloc(sc, vif); |
391bd1c4 | 1434 | if (!error) |
4801416c | 1435 | ath_beacon_config(sc, vif); |
014cf3bb | 1436 | ath9k_set_beaconing_status(sc, true); |
4801416c | 1437 | } |
f078f209 LR |
1438 | } |
1439 | ||
4801416c BG |
1440 | |
1441 | static int ath9k_add_interface(struct ieee80211_hw *hw, | |
1442 | struct ieee80211_vif *vif) | |
6b3b991d | 1443 | { |
9ac58615 | 1444 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1445 | struct ath_hw *ah = sc->sc_ah; |
1446 | struct ath_common *common = ath9k_hw_common(ah); | |
4801416c | 1447 | int ret = 0; |
6b3b991d | 1448 | |
96f372c9 | 1449 | ath9k_ps_wakeup(sc); |
4801416c | 1450 | mutex_lock(&sc->mutex); |
6b3b991d | 1451 | |
4801416c BG |
1452 | switch (vif->type) { |
1453 | case NL80211_IFTYPE_STATION: | |
1454 | case NL80211_IFTYPE_WDS: | |
1455 | case NL80211_IFTYPE_ADHOC: | |
1456 | case NL80211_IFTYPE_AP: | |
1457 | case NL80211_IFTYPE_MESH_POINT: | |
1458 | break; | |
1459 | default: | |
1460 | ath_err(common, "Interface type %d not yet supported\n", | |
1461 | vif->type); | |
1462 | ret = -EOPNOTSUPP; | |
1463 | goto out; | |
1464 | } | |
6b3b991d | 1465 | |
4801416c BG |
1466 | if (ath9k_uses_beacons(vif->type)) { |
1467 | if (sc->nbcnvifs >= ATH_BCBUF) { | |
1468 | ath_err(common, "Not enough beacon buffers when adding" | |
1469 | " new interface of type: %i\n", | |
1470 | vif->type); | |
1471 | ret = -ENOBUFS; | |
1472 | goto out; | |
1473 | } | |
1474 | } | |
1475 | ||
59575d1c RM |
1476 | if ((ah->opmode == NL80211_IFTYPE_ADHOC) || |
1477 | ((vif->type == NL80211_IFTYPE_ADHOC) && | |
1478 | sc->nvifs > 0)) { | |
4801416c BG |
1479 | ath_err(common, "Cannot create ADHOC interface when other" |
1480 | " interfaces already exist.\n"); | |
1481 | ret = -EINVAL; | |
1482 | goto out; | |
6b3b991d | 1483 | } |
4801416c BG |
1484 | |
1485 | ath_dbg(common, ATH_DBG_CONFIG, | |
1486 | "Attach a VIF of type: %d\n", vif->type); | |
1487 | ||
4801416c BG |
1488 | sc->nvifs++; |
1489 | ||
1490 | ath9k_do_vif_add_setup(hw, vif); | |
1491 | out: | |
1492 | mutex_unlock(&sc->mutex); | |
96f372c9 | 1493 | ath9k_ps_restore(sc); |
4801416c | 1494 | return ret; |
6b3b991d RM |
1495 | } |
1496 | ||
1497 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1498 | struct ieee80211_vif *vif, | |
1499 | enum nl80211_iftype new_type, | |
1500 | bool p2p) | |
1501 | { | |
9ac58615 | 1502 | struct ath_softc *sc = hw->priv; |
6b3b991d | 1503 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
6dab55bf | 1504 | int ret = 0; |
6b3b991d RM |
1505 | |
1506 | ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n"); | |
1507 | mutex_lock(&sc->mutex); | |
96f372c9 | 1508 | ath9k_ps_wakeup(sc); |
6b3b991d | 1509 | |
4801416c BG |
1510 | /* See if new interface type is valid. */ |
1511 | if ((new_type == NL80211_IFTYPE_ADHOC) && | |
1512 | (sc->nvifs > 1)) { | |
1513 | ath_err(common, "When using ADHOC, it must be the only" | |
1514 | " interface.\n"); | |
1515 | ret = -EINVAL; | |
1516 | goto out; | |
1517 | } | |
1518 | ||
1519 | if (ath9k_uses_beacons(new_type) && | |
1520 | !ath9k_uses_beacons(vif->type)) { | |
6b3b991d RM |
1521 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1522 | ath_err(common, "No beacon slot available\n"); | |
6dab55bf DC |
1523 | ret = -ENOBUFS; |
1524 | goto out; | |
6b3b991d | 1525 | } |
6b3b991d | 1526 | } |
4801416c BG |
1527 | |
1528 | /* Clean up old vif stuff */ | |
1529 | if (ath9k_uses_beacons(vif->type)) | |
1530 | ath9k_reclaim_beacon(sc, vif); | |
1531 | ||
1532 | /* Add new settings */ | |
6b3b991d RM |
1533 | vif->type = new_type; |
1534 | vif->p2p = p2p; | |
1535 | ||
4801416c | 1536 | ath9k_do_vif_add_setup(hw, vif); |
6dab55bf | 1537 | out: |
96f372c9 | 1538 | ath9k_ps_restore(sc); |
6b3b991d | 1539 | mutex_unlock(&sc->mutex); |
6dab55bf | 1540 | return ret; |
6b3b991d RM |
1541 | } |
1542 | ||
8feceb67 | 1543 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1544 | struct ieee80211_vif *vif) |
f078f209 | 1545 | { |
9ac58615 | 1546 | struct ath_softc *sc = hw->priv; |
c46917bb | 1547 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 | 1548 | |
226afe68 | 1549 | ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1550 | |
96f372c9 | 1551 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1552 | mutex_lock(&sc->mutex); |
1553 | ||
4801416c | 1554 | sc->nvifs--; |
580f0b8a | 1555 | |
8feceb67 | 1556 | /* Reclaim beacon resources */ |
4801416c | 1557 | if (ath9k_uses_beacons(vif->type)) |
6b3b991d | 1558 | ath9k_reclaim_beacon(sc, vif); |
2c3db3d5 | 1559 | |
4801416c | 1560 | ath9k_calculate_summary_state(hw, NULL); |
141b38b6 S |
1561 | |
1562 | mutex_unlock(&sc->mutex); | |
96f372c9 | 1563 | ath9k_ps_restore(sc); |
f078f209 LR |
1564 | } |
1565 | ||
fbab7390 | 1566 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1567 | { |
3069168c PR |
1568 | struct ath_hw *ah = sc->sc_ah; |
1569 | ||
3f7c5c10 | 1570 | sc->ps_enabled = true; |
3069168c PR |
1571 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1572 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1573 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1574 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1575 | } |
fdf76622 | 1576 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1577 | } |
3f7c5c10 SB |
1578 | } |
1579 | ||
845d708e SB |
1580 | static void ath9k_disable_ps(struct ath_softc *sc) |
1581 | { | |
1582 | struct ath_hw *ah = sc->sc_ah; | |
1583 | ||
1584 | sc->ps_enabled = false; | |
1585 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1586 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1587 | ath9k_hw_setrxabort(ah, 0); | |
1588 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1589 | PS_WAIT_FOR_CAB | | |
1590 | PS_WAIT_FOR_PSPOLL_DATA | | |
1591 | PS_WAIT_FOR_TX_ACK); | |
1592 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1593 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
1594 | ath9k_hw_set_interrupts(ah, ah->imask); | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | } | |
1599 | ||
e8975581 | 1600 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1601 | { |
9ac58615 | 1602 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1603 | struct ath_hw *ah = sc->sc_ah; |
1604 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1605 | struct ieee80211_conf *conf = &hw->conf; |
7545daf4 | 1606 | bool disable_radio = false; |
f078f209 | 1607 | |
aa33de09 | 1608 | mutex_lock(&sc->mutex); |
141b38b6 | 1609 | |
194b7c13 LR |
1610 | /* |
1611 | * Leave this as the first check because we need to turn on the | |
1612 | * radio if it was disabled before prior to processing the rest | |
1613 | * of the changes. Likewise we must only disable the radio towards | |
1614 | * the end. | |
1615 | */ | |
64839170 | 1616 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 FF |
1617 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
1618 | if (!sc->ps_idle) { | |
68a89116 | 1619 | ath_radio_enable(sc, hw); |
226afe68 JP |
1620 | ath_dbg(common, ATH_DBG_CONFIG, |
1621 | "not-idle: enabling radio\n"); | |
7545daf4 FF |
1622 | } else { |
1623 | disable_radio = true; | |
64839170 LR |
1624 | } |
1625 | } | |
1626 | ||
e7824a50 LR |
1627 | /* |
1628 | * We just prepare to enable PS. We have to wait until our AP has | |
1629 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1630 | * those ACKs and end up retransmitting the same null data frames. | |
1631 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1632 | */ | |
3cbb5dd7 | 1633 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1634 | unsigned long flags; |
1635 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1636 | if (conf->flags & IEEE80211_CONF_PS) |
1637 | ath9k_enable_ps(sc); | |
845d708e SB |
1638 | else |
1639 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1640 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1641 | } |
1642 | ||
199afd9d S |
1643 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1644 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
226afe68 JP |
1645 | ath_dbg(common, ATH_DBG_CONFIG, |
1646 | "Monitor mode is enabled\n"); | |
5f841b41 RM |
1647 | sc->sc_ah->is_monitoring = true; |
1648 | } else { | |
226afe68 JP |
1649 | ath_dbg(common, ATH_DBG_CONFIG, |
1650 | "Monitor mode is disabled\n"); | |
5f841b41 | 1651 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1652 | } |
1653 | } | |
1654 | ||
4797938c | 1655 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1656 | struct ieee80211_channel *curchan = hw->conf.channel; |
e338a85e | 1657 | struct ath9k_channel old_chan; |
5f8e077c | 1658 | int pos = curchan->hw_value; |
3430098a FF |
1659 | int old_pos = -1; |
1660 | unsigned long flags; | |
1661 | ||
1662 | if (ah->curchan) | |
1663 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1664 | |
5ee08656 FF |
1665 | if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
1666 | sc->sc_flags |= SC_OP_OFFCHANNEL; | |
1667 | else | |
1668 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | |
0e2dedf9 | 1669 | |
8c79a610 BG |
1670 | ath_dbg(common, ATH_DBG_CONFIG, |
1671 | "Set channel: %d MHz type: %d\n", | |
1672 | curchan->center_freq, conf->channel_type); | |
f078f209 | 1673 | |
3430098a FF |
1674 | /* update survey stats for the old channel before switching */ |
1675 | spin_lock_irqsave(&common->cc_lock, flags); | |
1676 | ath_update_survey_stats(sc); | |
1677 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1678 | ||
e338a85e RM |
1679 | /* |
1680 | * Preserve the current channel values, before updating | |
1681 | * the same channel | |
1682 | */ | |
1683 | if (old_pos == pos) { | |
1684 | memcpy(&old_chan, &sc->sc_ah->channels[pos], | |
1685 | sizeof(struct ath9k_channel)); | |
1686 | ah->curchan = &old_chan; | |
1687 | } | |
1688 | ||
1689 | ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], | |
1690 | curchan, conf->channel_type); | |
1691 | ||
3430098a FF |
1692 | /* |
1693 | * If the operating channel changes, change the survey in-use flags | |
1694 | * along with it. | |
1695 | * Reset the survey data for the new channel, unless we're switching | |
1696 | * back to the operating channel from an off-channel operation. | |
1697 | */ | |
1698 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1699 | sc->cur_survey != &sc->survey[pos]) { | |
1700 | ||
1701 | if (sc->cur_survey) | |
1702 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1703 | ||
1704 | sc->cur_survey = &sc->survey[pos]; | |
1705 | ||
1706 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1707 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1708 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1709 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1710 | } | |
1711 | ||
0e2dedf9 | 1712 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
3800276a | 1713 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1714 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1715 | return -EINVAL; |
1716 | } | |
3430098a FF |
1717 | |
1718 | /* | |
1719 | * The most recent snapshot of channel->noisefloor for the old | |
1720 | * channel is only available after the hardware reset. Copy it to | |
1721 | * the survey stats now. | |
1722 | */ | |
1723 | if (old_pos >= 0) | |
1724 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1725 | } |
f078f209 | 1726 | |
c9f6a656 | 1727 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
603b3eef BG |
1728 | ath_dbg(common, ATH_DBG_CONFIG, |
1729 | "Set power: %d\n", conf->power_level); | |
17d7904d | 1730 | sc->config.txpowlimit = 2 * conf->power_level; |
783cd01e | 1731 | ath9k_ps_wakeup(sc); |
5048e8c3 RM |
1732 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1733 | sc->config.txpowlimit, &sc->curtxpow); | |
783cd01e | 1734 | ath9k_ps_restore(sc); |
c9f6a656 | 1735 | } |
f078f209 | 1736 | |
64839170 | 1737 | if (disable_radio) { |
226afe68 | 1738 | ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
68a89116 | 1739 | ath_radio_disable(sc, hw); |
64839170 LR |
1740 | } |
1741 | ||
aa33de09 | 1742 | mutex_unlock(&sc->mutex); |
141b38b6 | 1743 | |
f078f209 LR |
1744 | return 0; |
1745 | } | |
1746 | ||
8feceb67 VT |
1747 | #define SUPPORTED_FILTERS \ |
1748 | (FIF_PROMISC_IN_BSS | \ | |
1749 | FIF_ALLMULTI | \ | |
1750 | FIF_CONTROL | \ | |
af6a3fc7 | 1751 | FIF_PSPOLL | \ |
8feceb67 VT |
1752 | FIF_OTHER_BSS | \ |
1753 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1754 | FIF_PROBE_REQ | \ |
8feceb67 | 1755 | FIF_FCSFAIL) |
c83be688 | 1756 | |
8feceb67 VT |
1757 | /* FIXME: sc->sc_full_reset ? */ |
1758 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1759 | unsigned int changed_flags, | |
1760 | unsigned int *total_flags, | |
3ac64bee | 1761 | u64 multicast) |
8feceb67 | 1762 | { |
9ac58615 | 1763 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1764 | u32 rfilt; |
f078f209 | 1765 | |
8feceb67 VT |
1766 | changed_flags &= SUPPORTED_FILTERS; |
1767 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1768 | |
b77f483f | 1769 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1770 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1771 | rfilt = ath_calcrxfilter(sc); |
1772 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1773 | ath9k_ps_restore(sc); |
f078f209 | 1774 | |
226afe68 JP |
1775 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1776 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1777 | } |
f078f209 | 1778 | |
4ca77860 JB |
1779 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1780 | struct ieee80211_vif *vif, | |
1781 | struct ieee80211_sta *sta) | |
8feceb67 | 1782 | { |
9ac58615 | 1783 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1784 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1785 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1786 | struct ieee80211_key_conf ps_key = { }; | |
f078f209 | 1787 | |
4ca77860 | 1788 | ath_node_attach(sc, sta); |
f59a59fe FF |
1789 | |
1790 | if (vif->type != NL80211_IFTYPE_AP && | |
1791 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1792 | return 0; | |
1793 | ||
93ae2dd2 | 1794 | an->ps_key = ath_key_config(common, vif, sta, &ps_key); |
4ca77860 JB |
1795 | |
1796 | return 0; | |
1797 | } | |
1798 | ||
93ae2dd2 FF |
1799 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1800 | struct ieee80211_vif *vif, | |
1801 | struct ieee80211_sta *sta) | |
1802 | { | |
1803 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1804 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1805 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1806 | ||
1807 | if (!an->ps_key) | |
1808 | return; | |
1809 | ||
1810 | ath_key_delete(common, &ps_key); | |
1811 | } | |
1812 | ||
4ca77860 JB |
1813 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1814 | struct ieee80211_vif *vif, | |
1815 | struct ieee80211_sta *sta) | |
1816 | { | |
9ac58615 | 1817 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1818 | |
93ae2dd2 | 1819 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1820 | ath_node_detach(sc, sta); |
1821 | ||
1822 | return 0; | |
f078f209 LR |
1823 | } |
1824 | ||
5519541d FF |
1825 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1826 | struct ieee80211_vif *vif, | |
1827 | enum sta_notify_cmd cmd, | |
1828 | struct ieee80211_sta *sta) | |
1829 | { | |
1830 | struct ath_softc *sc = hw->priv; | |
1831 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1832 | ||
1833 | switch (cmd) { | |
1834 | case STA_NOTIFY_SLEEP: | |
1835 | an->sleeping = true; | |
042ec453 | 1836 | ath_tx_aggr_sleep(sta, sc, an); |
5519541d FF |
1837 | break; |
1838 | case STA_NOTIFY_AWAKE: | |
1839 | an->sleeping = false; | |
1840 | ath_tx_aggr_wakeup(sc, an); | |
1841 | break; | |
1842 | } | |
1843 | } | |
1844 | ||
141b38b6 | 1845 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1846 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1847 | { |
9ac58615 | 1848 | struct ath_softc *sc = hw->priv; |
c46917bb | 1849 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1850 | struct ath_txq *txq; |
8feceb67 | 1851 | struct ath9k_tx_queue_info qi; |
066dae93 | 1852 | int ret = 0; |
f078f209 | 1853 | |
8feceb67 VT |
1854 | if (queue >= WME_NUM_AC) |
1855 | return 0; | |
f078f209 | 1856 | |
066dae93 FF |
1857 | txq = sc->tx.txq_map[queue]; |
1858 | ||
96f372c9 | 1859 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1860 | mutex_lock(&sc->mutex); |
1861 | ||
1ffb0610 S |
1862 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1863 | ||
8feceb67 VT |
1864 | qi.tqi_aifs = params->aifs; |
1865 | qi.tqi_cwmin = params->cw_min; | |
1866 | qi.tqi_cwmax = params->cw_max; | |
1867 | qi.tqi_burstTime = params->txop; | |
f078f209 | 1868 | |
226afe68 JP |
1869 | ath_dbg(common, ATH_DBG_CONFIG, |
1870 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1871 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1872 | params->cw_max, params->txop); | |
f078f209 | 1873 | |
066dae93 | 1874 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1875 | if (ret) |
3800276a | 1876 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1877 | |
94db2936 | 1878 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
066dae93 | 1879 | if (queue == WME_AC_BE && !ret) |
94db2936 VN |
1880 | ath_beaconq_config(sc); |
1881 | ||
141b38b6 | 1882 | mutex_unlock(&sc->mutex); |
96f372c9 | 1883 | ath9k_ps_restore(sc); |
141b38b6 | 1884 | |
8feceb67 VT |
1885 | return ret; |
1886 | } | |
f078f209 | 1887 | |
8feceb67 VT |
1888 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1889 | enum set_key_cmd cmd, | |
dc822b5d JB |
1890 | struct ieee80211_vif *vif, |
1891 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1892 | struct ieee80211_key_conf *key) |
1893 | { | |
9ac58615 | 1894 | struct ath_softc *sc = hw->priv; |
c46917bb | 1895 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1896 | int ret = 0; |
f078f209 | 1897 | |
3e6109c5 | 1898 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1899 | return -ENOSPC; |
1900 | ||
cfdc9a8b JM |
1901 | if (vif->type == NL80211_IFTYPE_ADHOC && |
1902 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || | |
1903 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1904 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1905 | /* | |
1906 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1907 | * could be optimized in the future to use a modified key cache | |
1908 | * design to support per-STA RX GTK, but until that gets | |
1909 | * implemented, use of software crypto for group addressed | |
1910 | * frames is a acceptable to allow RSN IBSS to be used. | |
1911 | */ | |
1912 | return -EOPNOTSUPP; | |
1913 | } | |
1914 | ||
141b38b6 | 1915 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1916 | ath9k_ps_wakeup(sc); |
226afe68 | 1917 | ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1918 | |
8feceb67 VT |
1919 | switch (cmd) { |
1920 | case SET_KEY: | |
93ae2dd2 FF |
1921 | if (sta) |
1922 | ath9k_del_ps_key(sc, vif, sta); | |
1923 | ||
040e539e | 1924 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1925 | if (ret >= 0) { |
1926 | key->hw_key_idx = ret; | |
8feceb67 VT |
1927 | /* push IV and Michael MIC generation to stack */ |
1928 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1929 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1930 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1931 | if (sc->sc_ah->sw_mgmt_crypto && |
1932 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1933 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1934 | ret = 0; |
8feceb67 VT |
1935 | } |
1936 | break; | |
1937 | case DISABLE_KEY: | |
040e539e | 1938 | ath_key_delete(common, key); |
8feceb67 VT |
1939 | break; |
1940 | default: | |
1941 | ret = -EINVAL; | |
1942 | } | |
f078f209 | 1943 | |
3cbb5dd7 | 1944 | ath9k_ps_restore(sc); |
141b38b6 S |
1945 | mutex_unlock(&sc->mutex); |
1946 | ||
8feceb67 VT |
1947 | return ret; |
1948 | } | |
4f5ef75b RM |
1949 | static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
1950 | { | |
1951 | struct ath_softc *sc = data; | |
1952 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1953 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
1954 | struct ath_vif *avp = (void *)vif->drv_priv; | |
1955 | ||
2e5ef459 RM |
1956 | /* |
1957 | * Skip iteration if primary station vif's bss info | |
1958 | * was not changed | |
1959 | */ | |
1960 | if (sc->sc_flags & SC_OP_PRIM_STA_VIF) | |
1961 | return; | |
1962 | ||
1963 | if (bss_conf->assoc) { | |
1964 | sc->sc_flags |= SC_OP_PRIM_STA_VIF; | |
1965 | avp->primary_sta_vif = true; | |
4f5ef75b RM |
1966 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1967 | common->curaid = bss_conf->aid; | |
1968 | ath9k_hw_write_associd(sc->sc_ah); | |
2e5ef459 | 1969 | ath_dbg(common, ATH_DBG_CONFIG, |
99e4d43a RM |
1970 | "Bss Info ASSOC %d, bssid: %pM\n", |
1971 | bss_conf->aid, common->curbssid); | |
2e5ef459 RM |
1972 | ath_beacon_config(sc, vif); |
1973 | /* | |
1974 | * Request a re-configuration of Beacon related timers | |
1975 | * on the receipt of the first Beacon frame (i.e., | |
1976 | * after time sync with the AP). | |
1977 | */ | |
1978 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
1979 | /* Reset rssi stats */ | |
1980 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; | |
1981 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
99e4d43a | 1982 | |
05c0be2f MSS |
1983 | if (!common->disable_ani) { |
1984 | sc->sc_flags |= SC_OP_ANI_RUN; | |
1985 | ath_start_ani(common); | |
1986 | } | |
1987 | ||
4f5ef75b RM |
1988 | } |
1989 | } | |
1990 | ||
1991 | static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif) | |
1992 | { | |
1993 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1994 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
1995 | struct ath_vif *avp = (void *)vif->drv_priv; | |
1996 | ||
2e5ef459 RM |
1997 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
1998 | return; | |
1999 | ||
4f5ef75b RM |
2000 | /* Reconfigure bss info */ |
2001 | if (avp->primary_sta_vif && !bss_conf->assoc) { | |
99e4d43a RM |
2002 | ath_dbg(common, ATH_DBG_CONFIG, |
2003 | "Bss Info DISASSOC %d, bssid %pM\n", | |
2004 | common->curaid, common->curbssid); | |
2005 | sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS); | |
4f5ef75b RM |
2006 | avp->primary_sta_vif = false; |
2007 | memset(common->curbssid, 0, ETH_ALEN); | |
2008 | common->curaid = 0; | |
2009 | } | |
2010 | ||
2011 | ieee80211_iterate_active_interfaces_atomic( | |
2012 | sc->hw, ath9k_bss_iter, sc); | |
2013 | ||
2014 | /* | |
2015 | * None of station vifs are associated. | |
2016 | * Clear bssid & aid | |
2017 | */ | |
2e5ef459 | 2018 | if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) { |
4f5ef75b | 2019 | ath9k_hw_write_associd(sc->sc_ah); |
99e4d43a RM |
2020 | /* Stop ANI */ |
2021 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
2022 | del_timer_sync(&common->ani.timer); | |
d2c71c20 | 2023 | memset(&sc->caldata, 0, sizeof(sc->caldata)); |
99e4d43a | 2024 | } |
4f5ef75b | 2025 | } |
f078f209 | 2026 | |
8feceb67 VT |
2027 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
2028 | struct ieee80211_vif *vif, | |
2029 | struct ieee80211_bss_conf *bss_conf, | |
2030 | u32 changed) | |
2031 | { | |
9ac58615 | 2032 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 2033 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 2034 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 2035 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 2036 | int slottime; |
c6089ccc | 2037 | int error; |
f078f209 | 2038 | |
96f372c9 | 2039 | ath9k_ps_wakeup(sc); |
141b38b6 S |
2040 | mutex_lock(&sc->mutex); |
2041 | ||
c6089ccc | 2042 | if (changed & BSS_CHANGED_BSSID) { |
4f5ef75b | 2043 | ath9k_config_bss(sc, vif); |
2d0ddec5 | 2044 | |
226afe68 JP |
2045 | ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n", |
2046 | common->curbssid, common->curaid); | |
c6089ccc | 2047 | } |
2d0ddec5 | 2048 | |
2e5ef459 RM |
2049 | if (changed & BSS_CHANGED_IBSS) { |
2050 | /* There can be only one vif available */ | |
2051 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
2052 | common->curaid = bss_conf->aid; | |
2053 | ath9k_hw_write_associd(sc->sc_ah); | |
2054 | ||
2055 | if (bss_conf->ibss_joined) { | |
2056 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
05c0be2f MSS |
2057 | |
2058 | if (!common->disable_ani) { | |
2059 | sc->sc_flags |= SC_OP_ANI_RUN; | |
2060 | ath_start_ani(common); | |
2061 | } | |
2062 | ||
2e5ef459 RM |
2063 | } else { |
2064 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
2065 | del_timer_sync(&common->ani.timer); | |
2066 | } | |
2067 | } | |
2068 | ||
c6089ccc S |
2069 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
2070 | if ((changed & BSS_CHANGED_BEACON) || | |
2071 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
014cf3bb | 2072 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 2073 | error = ath_beacon_alloc(sc, vif); |
c6089ccc S |
2074 | if (!error) |
2075 | ath_beacon_config(sc, vif); | |
014cf3bb | 2076 | ath9k_set_beaconing_status(sc, true); |
0005baf4 FF |
2077 | } |
2078 | ||
2079 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
2080 | if (bss_conf->use_short_slot) | |
2081 | slottime = 9; | |
2082 | else | |
2083 | slottime = 20; | |
2084 | if (vif->type == NL80211_IFTYPE_AP) { | |
2085 | /* | |
2086 | * Defer update, so that connected stations can adjust | |
2087 | * their settings at the same time. | |
2088 | * See beacon.c for more details | |
2089 | */ | |
2090 | sc->beacon.slottime = slottime; | |
2091 | sc->beacon.updateslot = UPDATE; | |
2092 | } else { | |
2093 | ah->slottime = slottime; | |
2094 | ath9k_hw_init_global_settings(ah); | |
2095 | } | |
2d0ddec5 JB |
2096 | } |
2097 | ||
c6089ccc | 2098 | /* Disable transmission of beacons */ |
014cf3bb RM |
2099 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && |
2100 | !bss_conf->enable_beacon) { | |
2101 | ath9k_set_beaconing_status(sc, false); | |
2102 | avp->is_bslot_active = false; | |
2103 | ath9k_set_beaconing_status(sc, true); | |
2104 | } | |
2d0ddec5 | 2105 | |
c6089ccc | 2106 | if (changed & BSS_CHANGED_BEACON_INT) { |
c6089ccc S |
2107 | /* |
2108 | * In case of AP mode, the HW TSF has to be reset | |
2109 | * when the beacon interval changes. | |
2110 | */ | |
2111 | if (vif->type == NL80211_IFTYPE_AP) { | |
2112 | sc->sc_flags |= SC_OP_TSF_RESET; | |
014cf3bb | 2113 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 2114 | error = ath_beacon_alloc(sc, vif); |
2d0ddec5 JB |
2115 | if (!error) |
2116 | ath_beacon_config(sc, vif); | |
014cf3bb | 2117 | ath9k_set_beaconing_status(sc, true); |
99e4d43a | 2118 | } else |
c6089ccc | 2119 | ath_beacon_config(sc, vif); |
2d0ddec5 JB |
2120 | } |
2121 | ||
8feceb67 | 2122 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
226afe68 JP |
2123 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
2124 | bss_conf->use_short_preamble); | |
8feceb67 VT |
2125 | if (bss_conf->use_short_preamble) |
2126 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
2127 | else | |
2128 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
2129 | } | |
f078f209 | 2130 | |
8feceb67 | 2131 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
226afe68 JP |
2132 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
2133 | bss_conf->use_cts_prot); | |
8feceb67 VT |
2134 | if (bss_conf->use_cts_prot && |
2135 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
2136 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
2137 | else | |
2138 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
2139 | } | |
f078f209 | 2140 | |
141b38b6 | 2141 | mutex_unlock(&sc->mutex); |
96f372c9 | 2142 | ath9k_ps_restore(sc); |
8feceb67 | 2143 | } |
f078f209 | 2144 | |
37a41b4a | 2145 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 2146 | { |
9ac58615 | 2147 | struct ath_softc *sc = hw->priv; |
8feceb67 | 2148 | u64 tsf; |
f078f209 | 2149 | |
141b38b6 | 2150 | mutex_lock(&sc->mutex); |
9abbfb27 | 2151 | ath9k_ps_wakeup(sc); |
141b38b6 | 2152 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 2153 | ath9k_ps_restore(sc); |
141b38b6 | 2154 | mutex_unlock(&sc->mutex); |
f078f209 | 2155 | |
8feceb67 VT |
2156 | return tsf; |
2157 | } | |
f078f209 | 2158 | |
37a41b4a EP |
2159 | static void ath9k_set_tsf(struct ieee80211_hw *hw, |
2160 | struct ieee80211_vif *vif, | |
2161 | u64 tsf) | |
3b5d665b | 2162 | { |
9ac58615 | 2163 | struct ath_softc *sc = hw->priv; |
3b5d665b | 2164 | |
141b38b6 | 2165 | mutex_lock(&sc->mutex); |
9abbfb27 | 2166 | ath9k_ps_wakeup(sc); |
141b38b6 | 2167 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 2168 | ath9k_ps_restore(sc); |
141b38b6 | 2169 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
2170 | } |
2171 | ||
37a41b4a | 2172 | static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 2173 | { |
9ac58615 | 2174 | struct ath_softc *sc = hw->priv; |
c83be688 | 2175 | |
141b38b6 | 2176 | mutex_lock(&sc->mutex); |
21526d57 LR |
2177 | |
2178 | ath9k_ps_wakeup(sc); | |
141b38b6 | 2179 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
2180 | ath9k_ps_restore(sc); |
2181 | ||
141b38b6 | 2182 | mutex_unlock(&sc->mutex); |
8feceb67 | 2183 | } |
f078f209 | 2184 | |
8feceb67 | 2185 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 2186 | struct ieee80211_vif *vif, |
141b38b6 S |
2187 | enum ieee80211_ampdu_mlme_action action, |
2188 | struct ieee80211_sta *sta, | |
0b01f030 | 2189 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 2190 | { |
9ac58615 | 2191 | struct ath_softc *sc = hw->priv; |
8feceb67 | 2192 | int ret = 0; |
f078f209 | 2193 | |
85ad181e JB |
2194 | local_bh_disable(); |
2195 | ||
8feceb67 VT |
2196 | switch (action) { |
2197 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2198 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2199 | ret = -ENOTSUPP; | |
8feceb67 VT |
2200 | break; |
2201 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2202 | break; |
2203 | case IEEE80211_AMPDU_TX_START: | |
71a3bf3e FF |
2204 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
2205 | return -EOPNOTSUPP; | |
2206 | ||
8b685ba9 | 2207 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
2208 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
2209 | if (!ret) | |
2210 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 2211 | ath9k_ps_restore(sc); |
8feceb67 VT |
2212 | break; |
2213 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 2214 | ath9k_ps_wakeup(sc); |
f83da965 | 2215 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 2216 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 2217 | ath9k_ps_restore(sc); |
8feceb67 | 2218 | break; |
b1720231 | 2219 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 2220 | ath9k_ps_wakeup(sc); |
8469cdef | 2221 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 2222 | ath9k_ps_restore(sc); |
8469cdef | 2223 | break; |
8feceb67 | 2224 | default: |
3800276a | 2225 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
2226 | } |
2227 | ||
85ad181e JB |
2228 | local_bh_enable(); |
2229 | ||
8feceb67 | 2230 | return ret; |
f078f209 LR |
2231 | } |
2232 | ||
62dad5b0 BP |
2233 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
2234 | struct survey_info *survey) | |
2235 | { | |
9ac58615 | 2236 | struct ath_softc *sc = hw->priv; |
3430098a | 2237 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 2238 | struct ieee80211_supported_band *sband; |
3430098a FF |
2239 | struct ieee80211_channel *chan; |
2240 | unsigned long flags; | |
2241 | int pos; | |
2242 | ||
2243 | spin_lock_irqsave(&common->cc_lock, flags); | |
2244 | if (idx == 0) | |
2245 | ath_update_survey_stats(sc); | |
39162dbe FF |
2246 | |
2247 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
2248 | if (sband && idx >= sband->n_channels) { | |
2249 | idx -= sband->n_channels; | |
2250 | sband = NULL; | |
2251 | } | |
62dad5b0 | 2252 | |
39162dbe FF |
2253 | if (!sband) |
2254 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 2255 | |
3430098a FF |
2256 | if (!sband || idx >= sband->n_channels) { |
2257 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2258 | return -ENOENT; | |
4f1a5a4b | 2259 | } |
62dad5b0 | 2260 | |
3430098a FF |
2261 | chan = &sband->channels[idx]; |
2262 | pos = chan->hw_value; | |
2263 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
2264 | survey->channel = chan; | |
2265 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2266 | ||
62dad5b0 BP |
2267 | return 0; |
2268 | } | |
2269 | ||
e239d859 FF |
2270 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2271 | { | |
9ac58615 | 2272 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
2273 | struct ath_hw *ah = sc->sc_ah; |
2274 | ||
2275 | mutex_lock(&sc->mutex); | |
2276 | ah->coverage_class = coverage_class; | |
8b2a3827 MSS |
2277 | |
2278 | ath9k_ps_wakeup(sc); | |
e239d859 | 2279 | ath9k_hw_init_global_settings(ah); |
8b2a3827 MSS |
2280 | ath9k_ps_restore(sc); |
2281 | ||
e239d859 FF |
2282 | mutex_unlock(&sc->mutex); |
2283 | } | |
2284 | ||
69081624 VT |
2285 | static void ath9k_flush(struct ieee80211_hw *hw, bool drop) |
2286 | { | |
69081624 | 2287 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
2288 | struct ath_hw *ah = sc->sc_ah; |
2289 | struct ath_common *common = ath9k_hw_common(ah); | |
86271e46 FF |
2290 | int timeout = 200; /* ms */ |
2291 | int i, j; | |
2f6fc351 | 2292 | bool drain_txq; |
69081624 VT |
2293 | |
2294 | mutex_lock(&sc->mutex); | |
69081624 VT |
2295 | cancel_delayed_work_sync(&sc->tx_complete_work); |
2296 | ||
6a6b3f3e MSS |
2297 | if (ah->ah_flags & AH_UNPLUGGED) { |
2298 | ath_dbg(common, ATH_DBG_ANY, "Device has been unplugged!\n"); | |
2299 | mutex_unlock(&sc->mutex); | |
2300 | return; | |
2301 | } | |
2302 | ||
99aa55b6 MSS |
2303 | if (sc->sc_flags & SC_OP_INVALID) { |
2304 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); | |
2305 | mutex_unlock(&sc->mutex); | |
2306 | return; | |
2307 | } | |
2308 | ||
86271e46 FF |
2309 | if (drop) |
2310 | timeout = 1; | |
69081624 | 2311 | |
86271e46 | 2312 | for (j = 0; j < timeout; j++) { |
108697c4 | 2313 | bool npend = false; |
86271e46 FF |
2314 | |
2315 | if (j) | |
2316 | usleep_range(1000, 2000); | |
69081624 | 2317 | |
86271e46 FF |
2318 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2319 | if (!ATH_TXQ_SETUP(sc, i)) | |
2320 | continue; | |
2321 | ||
108697c4 MSS |
2322 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); |
2323 | ||
2324 | if (npend) | |
2325 | break; | |
69081624 | 2326 | } |
86271e46 FF |
2327 | |
2328 | if (!npend) | |
2329 | goto out; | |
69081624 VT |
2330 | } |
2331 | ||
51513906 | 2332 | ath9k_ps_wakeup(sc); |
2f6fc351 RM |
2333 | spin_lock_bh(&sc->sc_pcu_lock); |
2334 | drain_txq = ath_drain_all_txq(sc, false); | |
9adcf440 FF |
2335 | spin_unlock_bh(&sc->sc_pcu_lock); |
2336 | ||
2f6fc351 | 2337 | if (!drain_txq) |
69081624 | 2338 | ath_reset(sc, false); |
9adcf440 | 2339 | |
51513906 | 2340 | ath9k_ps_restore(sc); |
d78f4b3e SB |
2341 | ieee80211_wake_queues(hw); |
2342 | ||
86271e46 | 2343 | out: |
69081624 VT |
2344 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
2345 | mutex_unlock(&sc->mutex); | |
2346 | } | |
2347 | ||
15b91e83 VN |
2348 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
2349 | { | |
2350 | struct ath_softc *sc = hw->priv; | |
2351 | int i; | |
2352 | ||
2353 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
2354 | if (!ATH_TXQ_SETUP(sc, i)) | |
2355 | continue; | |
2356 | ||
2357 | if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) | |
2358 | return true; | |
2359 | } | |
2360 | return false; | |
2361 | } | |
2362 | ||
5595f119 | 2363 | static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
ba4903f9 FF |
2364 | { |
2365 | struct ath_softc *sc = hw->priv; | |
2366 | struct ath_hw *ah = sc->sc_ah; | |
2367 | struct ieee80211_vif *vif; | |
2368 | struct ath_vif *avp; | |
2369 | struct ath_buf *bf; | |
2370 | struct ath_tx_status ts; | |
2371 | int status; | |
2372 | ||
2373 | vif = sc->beacon.bslot[0]; | |
2374 | if (!vif) | |
2375 | return 0; | |
2376 | ||
2377 | avp = (void *)vif->drv_priv; | |
2378 | if (!avp->is_bslot_active) | |
2379 | return 0; | |
2380 | ||
2381 | if (!sc->beacon.tx_processed) { | |
2382 | tasklet_disable(&sc->bcon_tasklet); | |
2383 | ||
2384 | bf = avp->av_bcbuf; | |
2385 | if (!bf || !bf->bf_mpdu) | |
2386 | goto skip; | |
2387 | ||
2388 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
2389 | if (status == -EINPROGRESS) | |
2390 | goto skip; | |
2391 | ||
2392 | sc->beacon.tx_processed = true; | |
2393 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
2394 | ||
2395 | skip: | |
2396 | tasklet_enable(&sc->bcon_tasklet); | |
2397 | } | |
2398 | ||
2399 | return sc->beacon.tx_last; | |
2400 | } | |
2401 | ||
52c94f41 MSS |
2402 | static int ath9k_get_stats(struct ieee80211_hw *hw, |
2403 | struct ieee80211_low_level_stats *stats) | |
2404 | { | |
2405 | struct ath_softc *sc = hw->priv; | |
2406 | struct ath_hw *ah = sc->sc_ah; | |
2407 | struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; | |
2408 | ||
2409 | stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; | |
2410 | stats->dot11RTSFailureCount = mib_stats->rts_bad; | |
2411 | stats->dot11FCSErrorCount = mib_stats->fcs_bad; | |
2412 | stats->dot11RTSSuccessCount = mib_stats->rts_good; | |
2413 | return 0; | |
2414 | } | |
2415 | ||
43c35284 FF |
2416 | static u32 fill_chainmask(u32 cap, u32 new) |
2417 | { | |
2418 | u32 filled = 0; | |
2419 | int i; | |
2420 | ||
2421 | for (i = 0; cap && new; i++, cap >>= 1) { | |
2422 | if (!(cap & BIT(0))) | |
2423 | continue; | |
2424 | ||
2425 | if (new & BIT(0)) | |
2426 | filled |= BIT(i); | |
2427 | ||
2428 | new >>= 1; | |
2429 | } | |
2430 | ||
2431 | return filled; | |
2432 | } | |
2433 | ||
2434 | static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) | |
2435 | { | |
2436 | struct ath_softc *sc = hw->priv; | |
2437 | struct ath_hw *ah = sc->sc_ah; | |
2438 | ||
2439 | if (!rx_ant || !tx_ant) | |
2440 | return -EINVAL; | |
2441 | ||
2442 | sc->ant_rx = rx_ant; | |
2443 | sc->ant_tx = tx_ant; | |
2444 | ||
2445 | if (ah->caps.rx_chainmask == 1) | |
2446 | return 0; | |
2447 | ||
2448 | /* AR9100 runs into calibration issues if not all rx chains are enabled */ | |
2449 | if (AR_SREV_9100(ah)) | |
2450 | ah->rxchainmask = 0x7; | |
2451 | else | |
2452 | ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); | |
2453 | ||
2454 | ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); | |
2455 | ath9k_reload_chainmask_settings(sc); | |
2456 | ||
2457 | return 0; | |
2458 | } | |
2459 | ||
2460 | static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | |
2461 | { | |
2462 | struct ath_softc *sc = hw->priv; | |
2463 | ||
2464 | *tx_ant = sc->ant_tx; | |
2465 | *rx_ant = sc->ant_rx; | |
2466 | return 0; | |
2467 | } | |
2468 | ||
6baff7f9 | 2469 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2470 | .tx = ath9k_tx, |
2471 | .start = ath9k_start, | |
2472 | .stop = ath9k_stop, | |
2473 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2474 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2475 | .remove_interface = ath9k_remove_interface, |
2476 | .config = ath9k_config, | |
8feceb67 | 2477 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2478 | .sta_add = ath9k_sta_add, |
2479 | .sta_remove = ath9k_sta_remove, | |
5519541d | 2480 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2481 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2482 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2483 | .set_key = ath9k_set_key, |
8feceb67 | 2484 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2485 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2486 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2487 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2488 | .get_survey = ath9k_get_survey, |
3b319aae | 2489 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2490 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2491 | .flush = ath9k_flush, |
15b91e83 | 2492 | .tx_frames_pending = ath9k_tx_frames_pending, |
52c94f41 MSS |
2493 | .tx_last_beacon = ath9k_tx_last_beacon, |
2494 | .get_stats = ath9k_get_stats, | |
43c35284 FF |
2495 | .set_antenna = ath9k_set_antenna, |
2496 | .get_antenna = ath9k_get_antenna, | |
8feceb67 | 2497 | }; |