Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
ff37e337 S |
22 | static u8 parse_mpdudensity(u8 mpdudensity) |
23 | { | |
24 | /* | |
25 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
26 | * 0 for no restriction | |
27 | * 1 for 1/4 us | |
28 | * 2 for 1/2 us | |
29 | * 3 for 1 us | |
30 | * 4 for 2 us | |
31 | * 5 for 4 us | |
32 | * 6 for 8 us | |
33 | * 7 for 16 us | |
34 | */ | |
35 | switch (mpdudensity) { | |
36 | case 0: | |
37 | return 0; | |
38 | case 1: | |
39 | case 2: | |
40 | case 3: | |
41 | /* Our lower layer calculations limit our precision to | |
42 | 1 microsecond */ | |
43 | return 1; | |
44 | case 4: | |
45 | return 2; | |
46 | case 5: | |
47 | return 4; | |
48 | case 6: | |
49 | return 8; | |
50 | case 7: | |
51 | return 16; | |
52 | default: | |
53 | return 0; | |
54 | } | |
55 | } | |
56 | ||
69081624 VT |
57 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
58 | { | |
59 | bool pending = false; | |
60 | ||
61 | spin_lock_bh(&txq->axq_lock); | |
62 | ||
63 | if (txq->axq_depth || !list_empty(&txq->axq_acq)) | |
64 | pending = true; | |
69081624 VT |
65 | |
66 | spin_unlock_bh(&txq->axq_lock); | |
67 | return pending; | |
68 | } | |
69 | ||
6d79cb4c | 70 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
71 | { |
72 | unsigned long flags; | |
73 | bool ret; | |
74 | ||
9ecdef4b LR |
75 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
76 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
77 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
78 | |
79 | return ret; | |
80 | } | |
81 | ||
a91d75ae LR |
82 | void ath9k_ps_wakeup(struct ath_softc *sc) |
83 | { | |
898c914a | 84 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 85 | unsigned long flags; |
fbb078fc | 86 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
87 | |
88 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
89 | if (++sc->ps_usecount != 1) | |
90 | goto unlock; | |
91 | ||
fbb078fc | 92 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 93 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 94 | |
898c914a FF |
95 | /* |
96 | * While the hardware is asleep, the cycle counters contain no | |
97 | * useful data. Better clear them now so that they don't mess up | |
98 | * survey data results. | |
99 | */ | |
fbb078fc FF |
100 | if (power_mode != ATH9K_PM_AWAKE) { |
101 | spin_lock(&common->cc_lock); | |
102 | ath_hw_cycle_counters_update(common); | |
103 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
104 | spin_unlock(&common->cc_lock); | |
105 | } | |
898c914a | 106 | |
a91d75ae LR |
107 | unlock: |
108 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
109 | } | |
110 | ||
111 | void ath9k_ps_restore(struct ath_softc *sc) | |
112 | { | |
898c914a | 113 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c6c539f0 | 114 | enum ath9k_power_mode mode; |
a91d75ae | 115 | unsigned long flags; |
ad128860 | 116 | bool reset; |
a91d75ae LR |
117 | |
118 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
119 | if (--sc->ps_usecount != 0) | |
120 | goto unlock; | |
121 | ||
ad128860 SM |
122 | if (sc->ps_idle) { |
123 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
124 | ath9k_hw_stopdmarecv(sc->sc_ah, &reset); | |
c6c539f0 | 125 | mode = ATH9K_PM_FULL_SLEEP; |
ad128860 SM |
126 | } else if (sc->ps_enabled && |
127 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
128 | PS_WAIT_FOR_CAB | | |
129 | PS_WAIT_FOR_PSPOLL_DATA | | |
130 | PS_WAIT_FOR_TX_ACK))) { | |
c6c539f0 | 131 | mode = ATH9K_PM_NETWORK_SLEEP; |
ad128860 | 132 | } else { |
c6c539f0 | 133 | goto unlock; |
ad128860 | 134 | } |
c6c539f0 FF |
135 | |
136 | spin_lock(&common->cc_lock); | |
137 | ath_hw_cycle_counters_update(common); | |
138 | spin_unlock(&common->cc_lock); | |
139 | ||
1a8f0d39 | 140 | ath9k_hw_setpower(sc->sc_ah, mode); |
a91d75ae LR |
141 | |
142 | unlock: | |
143 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
144 | } | |
145 | ||
05c0be2f | 146 | void ath_start_ani(struct ath_common *common) |
5ee08656 FF |
147 | { |
148 | struct ath_hw *ah = common->ah; | |
149 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
150 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
151 | ||
152 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
153 | return; | |
154 | ||
155 | if (sc->sc_flags & SC_OP_OFFCHANNEL) | |
156 | return; | |
157 | ||
158 | common->ani.longcal_timer = timestamp; | |
159 | common->ani.shortcal_timer = timestamp; | |
160 | common->ani.checkani_timer = timestamp; | |
161 | ||
162 | mod_timer(&common->ani.timer, | |
163 | jiffies + | |
164 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
165 | } | |
166 | ||
3430098a FF |
167 | static void ath_update_survey_nf(struct ath_softc *sc, int channel) |
168 | { | |
169 | struct ath_hw *ah = sc->sc_ah; | |
170 | struct ath9k_channel *chan = &ah->channels[channel]; | |
171 | struct survey_info *survey = &sc->survey[channel]; | |
172 | ||
173 | if (chan->noisefloor) { | |
174 | survey->filled |= SURVEY_INFO_NOISE_DBM; | |
f749b946 | 175 | survey->noise = ath9k_hw_getchan_noise(ah, chan); |
3430098a FF |
176 | } |
177 | } | |
178 | ||
cb8d61de FF |
179 | /* |
180 | * Updates the survey statistics and returns the busy time since last | |
181 | * update in %, if the measurement duration was long enough for the | |
182 | * result to be useful, -1 otherwise. | |
183 | */ | |
184 | static int ath_update_survey_stats(struct ath_softc *sc) | |
3430098a FF |
185 | { |
186 | struct ath_hw *ah = sc->sc_ah; | |
187 | struct ath_common *common = ath9k_hw_common(ah); | |
188 | int pos = ah->curchan - &ah->channels[0]; | |
189 | struct survey_info *survey = &sc->survey[pos]; | |
190 | struct ath_cycle_counters *cc = &common->cc_survey; | |
191 | unsigned int div = common->clockrate * 1000; | |
cb8d61de | 192 | int ret = 0; |
3430098a | 193 | |
0845735e | 194 | if (!ah->curchan) |
cb8d61de | 195 | return -1; |
0845735e | 196 | |
898c914a FF |
197 | if (ah->power_mode == ATH9K_PM_AWAKE) |
198 | ath_hw_cycle_counters_update(common); | |
3430098a FF |
199 | |
200 | if (cc->cycles > 0) { | |
201 | survey->filled |= SURVEY_INFO_CHANNEL_TIME | | |
202 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
203 | SURVEY_INFO_CHANNEL_TIME_RX | | |
204 | SURVEY_INFO_CHANNEL_TIME_TX; | |
205 | survey->channel_time += cc->cycles / div; | |
206 | survey->channel_time_busy += cc->rx_busy / div; | |
207 | survey->channel_time_rx += cc->rx_frame / div; | |
208 | survey->channel_time_tx += cc->tx_frame / div; | |
209 | } | |
cb8d61de FF |
210 | |
211 | if (cc->cycles < div) | |
212 | return -1; | |
213 | ||
214 | if (cc->cycles > 0) | |
215 | ret = cc->rx_busy * 100 / cc->cycles; | |
216 | ||
3430098a FF |
217 | memset(cc, 0, sizeof(*cc)); |
218 | ||
219 | ath_update_survey_nf(sc, pos); | |
cb8d61de FF |
220 | |
221 | return ret; | |
3430098a FF |
222 | } |
223 | ||
9adcf440 | 224 | static void __ath_cancel_work(struct ath_softc *sc) |
ff37e337 | 225 | { |
5ee08656 FF |
226 | cancel_work_sync(&sc->paprd_work); |
227 | cancel_work_sync(&sc->hw_check_work); | |
228 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
181fb18d | 229 | cancel_delayed_work_sync(&sc->hw_pll_work); |
9adcf440 | 230 | } |
5ee08656 | 231 | |
9adcf440 FF |
232 | static void ath_cancel_work(struct ath_softc *sc) |
233 | { | |
234 | __ath_cancel_work(sc); | |
235 | cancel_work_sync(&sc->hw_reset_work); | |
236 | } | |
3cbb5dd7 | 237 | |
9adcf440 FF |
238 | static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) |
239 | { | |
240 | struct ath_hw *ah = sc->sc_ah; | |
241 | struct ath_common *common = ath9k_hw_common(ah); | |
ceea2a51 | 242 | bool ret = true; |
6a6733f2 | 243 | |
9adcf440 | 244 | ieee80211_stop_queues(sc->hw); |
5e848f78 | 245 | |
9adcf440 FF |
246 | sc->hw_busy_count = 0; |
247 | del_timer_sync(&common->ani.timer); | |
01e18918 | 248 | del_timer_sync(&sc->rx_poll_timer); |
ff37e337 | 249 | |
9adcf440 FF |
250 | ath9k_debug_samp_bb_mac(sc); |
251 | ath9k_hw_disable_interrupts(ah); | |
8b3f4616 | 252 | |
9adcf440 FF |
253 | if (!ath_stoprecv(sc)) |
254 | ret = false; | |
c0d7c7af | 255 | |
ceea2a51 FF |
256 | if (!ath_drain_all_txq(sc, retry_tx)) |
257 | ret = false; | |
258 | ||
9adcf440 FF |
259 | if (!flush) { |
260 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
3483288c FF |
261 | ath_rx_tasklet(sc, 1, true); |
262 | ath_rx_tasklet(sc, 1, false); | |
9adcf440 FF |
263 | } else { |
264 | ath_flushrecv(sc); | |
265 | } | |
20bd2a09 | 266 | |
9adcf440 FF |
267 | return ret; |
268 | } | |
ff37e337 | 269 | |
9adcf440 FF |
270 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
271 | { | |
272 | struct ath_hw *ah = sc->sc_ah; | |
273 | struct ath_common *common = ath9k_hw_common(ah); | |
c0d7c7af | 274 | |
c0d7c7af | 275 | if (ath_startrecv(sc) != 0) { |
3800276a | 276 | ath_err(common, "Unable to restart recv logic\n"); |
9adcf440 | 277 | return false; |
c0d7c7af LR |
278 | } |
279 | ||
5048e8c3 RM |
280 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
281 | sc->config.txpowlimit, &sc->curtxpow); | |
72d874c6 | 282 | ath9k_hw_set_interrupts(ah); |
b037b693 | 283 | ath9k_hw_enable_interrupts(ah); |
3989279c | 284 | |
9adcf440 | 285 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) { |
1186488b | 286 | if (sc->sc_flags & SC_OP_BEACONS) |
99e4d43a | 287 | ath_set_beacon(sc); |
9adcf440 | 288 | |
5ee08656 | 289 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
181fb18d | 290 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2); |
01e18918 | 291 | ath_start_rx_poll(sc, 3); |
05c0be2f MSS |
292 | if (!common->disable_ani) |
293 | ath_start_ani(common); | |
5ee08656 FF |
294 | } |
295 | ||
162d12de | 296 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) { |
43c35284 FF |
297 | struct ath_hw_antcomb_conf div_ant_conf; |
298 | u8 lna_conf; | |
299 | ||
300 | ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf); | |
301 | ||
302 | if (sc->ant_rx == 1) | |
303 | lna_conf = ATH_ANT_DIV_COMB_LNA1; | |
304 | else | |
305 | lna_conf = ATH_ANT_DIV_COMB_LNA2; | |
306 | div_ant_conf.main_lna_conf = lna_conf; | |
307 | div_ant_conf.alt_lna_conf = lna_conf; | |
308 | ||
309 | ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf); | |
310 | } | |
311 | ||
9adcf440 FF |
312 | ieee80211_wake_queues(sc->hw); |
313 | ||
314 | return true; | |
315 | } | |
316 | ||
317 | static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, | |
318 | bool retry_tx) | |
319 | { | |
320 | struct ath_hw *ah = sc->sc_ah; | |
321 | struct ath_common *common = ath9k_hw_common(ah); | |
322 | struct ath9k_hw_cal_data *caldata = NULL; | |
323 | bool fastcc = true; | |
324 | bool flush = false; | |
325 | int r; | |
326 | ||
327 | __ath_cancel_work(sc); | |
328 | ||
329 | spin_lock_bh(&sc->sc_pcu_lock); | |
92460412 | 330 | |
9adcf440 FF |
331 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) { |
332 | fastcc = false; | |
333 | caldata = &sc->caldata; | |
334 | } | |
335 | ||
336 | if (!hchan) { | |
337 | fastcc = false; | |
338 | flush = true; | |
339 | hchan = ah->curchan; | |
340 | } | |
341 | ||
9adcf440 FF |
342 | if (!ath_prepare_reset(sc, retry_tx, flush)) |
343 | fastcc = false; | |
344 | ||
d2182b69 | 345 | ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", |
feced201 | 346 | hchan->channel, IS_CHAN_HT40(hchan), fastcc); |
9adcf440 FF |
347 | |
348 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | |
349 | if (r) { | |
350 | ath_err(common, | |
351 | "Unable to reset channel, reset status %d\n", r); | |
352 | goto out; | |
353 | } | |
354 | ||
355 | if (!ath_complete_reset(sc, true)) | |
356 | r = -EIO; | |
357 | ||
358 | out: | |
6a6733f2 | 359 | spin_unlock_bh(&sc->sc_pcu_lock); |
9adcf440 FF |
360 | return r; |
361 | } | |
362 | ||
363 | ||
364 | /* | |
365 | * Set/change channels. If the channel is really being changed, it's done | |
366 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
367 | * DMA, then restart stuff. | |
368 | */ | |
369 | static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
370 | struct ath9k_channel *hchan) | |
371 | { | |
372 | int r; | |
373 | ||
374 | if (sc->sc_flags & SC_OP_INVALID) | |
375 | return -EIO; | |
376 | ||
9adcf440 | 377 | r = ath_reset_internal(sc, hchan, false); |
6a6733f2 | 378 | |
3989279c | 379 | return r; |
ff37e337 S |
380 | } |
381 | ||
9f42c2b6 FF |
382 | static void ath_paprd_activate(struct ath_softc *sc) |
383 | { | |
384 | struct ath_hw *ah = sc->sc_ah; | |
20bd2a09 | 385 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9f42c2b6 FF |
386 | int chain; |
387 | ||
20bd2a09 | 388 | if (!caldata || !caldata->paprd_done) |
9f42c2b6 FF |
389 | return; |
390 | ||
391 | ath9k_ps_wakeup(sc); | |
ddfef792 | 392 | ar9003_paprd_enable(ah, false); |
9f42c2b6 | 393 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
82b2d334 | 394 | if (!(ah->txchainmask & BIT(chain))) |
9f42c2b6 FF |
395 | continue; |
396 | ||
20bd2a09 | 397 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
9f42c2b6 FF |
398 | } |
399 | ||
400 | ar9003_paprd_enable(ah, true); | |
401 | ath9k_ps_restore(sc); | |
402 | } | |
403 | ||
7607cbe2 FF |
404 | static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain) |
405 | { | |
406 | struct ieee80211_hw *hw = sc->hw; | |
407 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
47960077 MSS |
408 | struct ath_hw *ah = sc->sc_ah; |
409 | struct ath_common *common = ath9k_hw_common(ah); | |
7607cbe2 FF |
410 | struct ath_tx_control txctl; |
411 | int time_left; | |
412 | ||
413 | memset(&txctl, 0, sizeof(txctl)); | |
414 | txctl.txq = sc->tx.txq_map[WME_AC_BE]; | |
415 | ||
416 | memset(tx_info, 0, sizeof(*tx_info)); | |
417 | tx_info->band = hw->conf.channel->band; | |
418 | tx_info->flags |= IEEE80211_TX_CTL_NO_ACK; | |
419 | tx_info->control.rates[0].idx = 0; | |
420 | tx_info->control.rates[0].count = 1; | |
421 | tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS; | |
422 | tx_info->control.rates[1].idx = -1; | |
423 | ||
424 | init_completion(&sc->paprd_complete); | |
7607cbe2 | 425 | txctl.paprd = BIT(chain); |
47960077 MSS |
426 | |
427 | if (ath_tx_start(hw, skb, &txctl) != 0) { | |
d2182b69 | 428 | ath_dbg(common, CALIBRATE, "PAPRD TX failed\n"); |
47960077 | 429 | dev_kfree_skb_any(skb); |
7607cbe2 | 430 | return false; |
47960077 | 431 | } |
7607cbe2 FF |
432 | |
433 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
434 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); | |
7607cbe2 FF |
435 | |
436 | if (!time_left) | |
d2182b69 | 437 | ath_dbg(common, CALIBRATE, |
7607cbe2 FF |
438 | "Timeout waiting for paprd training on TX chain %d\n", |
439 | chain); | |
440 | ||
441 | return !!time_left; | |
442 | } | |
443 | ||
9f42c2b6 FF |
444 | void ath_paprd_calibrate(struct work_struct *work) |
445 | { | |
446 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
447 | struct ieee80211_hw *hw = sc->hw; | |
448 | struct ath_hw *ah = sc->sc_ah; | |
449 | struct ieee80211_hdr *hdr; | |
450 | struct sk_buff *skb = NULL; | |
20bd2a09 | 451 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 452 | struct ath_common *common = ath9k_hw_common(ah); |
066dae93 | 453 | int ftype; |
9f42c2b6 FF |
454 | int chain_ok = 0; |
455 | int chain; | |
456 | int len = 1800; | |
9f42c2b6 | 457 | |
20bd2a09 FF |
458 | if (!caldata) |
459 | return; | |
460 | ||
b942471b MSS |
461 | ath9k_ps_wakeup(sc); |
462 | ||
1bf38661 | 463 | if (ar9003_paprd_init_table(ah) < 0) |
b942471b | 464 | goto fail_paprd; |
1bf38661 | 465 | |
9f42c2b6 FF |
466 | skb = alloc_skb(len, GFP_KERNEL); |
467 | if (!skb) | |
b942471b | 468 | goto fail_paprd; |
9f42c2b6 | 469 | |
9f42c2b6 FF |
470 | skb_put(skb, len); |
471 | memset(skb->data, 0, len); | |
472 | hdr = (struct ieee80211_hdr *)skb->data; | |
473 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
474 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 475 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
476 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
477 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
478 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
479 | ||
9f42c2b6 | 480 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
82b2d334 | 481 | if (!(ah->txchainmask & BIT(chain))) |
9f42c2b6 FF |
482 | continue; |
483 | ||
484 | chain_ok = 0; | |
9f42c2b6 | 485 | |
d2182b69 JP |
486 | ath_dbg(common, CALIBRATE, |
487 | "Sending PAPRD frame for thermal measurement on chain %d\n", | |
488 | chain); | |
7607cbe2 FF |
489 | if (!ath_paprd_send_frame(sc, skb, chain)) |
490 | goto fail_paprd; | |
9f42c2b6 | 491 | |
9f42c2b6 | 492 | ar9003_paprd_setup_gain_table(ah, chain); |
9f42c2b6 | 493 | |
d2182b69 | 494 | ath_dbg(common, CALIBRATE, |
7607cbe2 FF |
495 | "Sending PAPRD training frame on chain %d\n", chain); |
496 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
ca369eb4 | 497 | goto fail_paprd; |
9f42c2b6 | 498 | |
d4bb17c4 | 499 | if (!ar9003_paprd_is_done(ah)) { |
d2182b69 | 500 | ath_dbg(common, CALIBRATE, |
d4bb17c4 | 501 | "PAPRD not yet done on chain %d\n", chain); |
9f42c2b6 | 502 | break; |
d4bb17c4 | 503 | } |
9f42c2b6 | 504 | |
d4bb17c4 | 505 | if (ar9003_paprd_create_curve(ah, caldata, chain)) { |
d2182b69 | 506 | ath_dbg(common, CALIBRATE, |
d4bb17c4 MSS |
507 | "PAPRD create curve failed on chain %d\n", |
508 | chain); | |
9f42c2b6 | 509 | break; |
d4bb17c4 | 510 | } |
9f42c2b6 FF |
511 | |
512 | chain_ok = 1; | |
513 | } | |
514 | kfree_skb(skb); | |
515 | ||
516 | if (chain_ok) { | |
20bd2a09 | 517 | caldata->paprd_done = true; |
9f42c2b6 FF |
518 | ath_paprd_activate(sc); |
519 | } | |
520 | ||
ca369eb4 | 521 | fail_paprd: |
9f42c2b6 FF |
522 | ath9k_ps_restore(sc); |
523 | } | |
524 | ||
ff37e337 S |
525 | /* |
526 | * This routine performs the periodic noise floor calibration function | |
527 | * that is used to adjust and optimize the chip performance. This | |
528 | * takes environmental changes (location, temperature) into account. | |
529 | * When the task is complete, it reschedules itself depending on the | |
530 | * appropriate interval that was calculated. | |
531 | */ | |
55624204 | 532 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 533 | { |
20977d3e S |
534 | struct ath_softc *sc = (struct ath_softc *)data; |
535 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 536 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
537 | bool longcal = false; |
538 | bool shortcal = false; | |
539 | bool aniflag = false; | |
540 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
6044474e | 541 | u32 cal_interval, short_cal_interval, long_cal_interval; |
b5bfc568 | 542 | unsigned long flags; |
6044474e FF |
543 | |
544 | if (ah->caldata && ah->caldata->nfcal_interference) | |
545 | long_cal_interval = ATH_LONG_CALINTERVAL_INT; | |
546 | else | |
547 | long_cal_interval = ATH_LONG_CALINTERVAL; | |
ff37e337 | 548 | |
20977d3e S |
549 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
550 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 551 | |
1ffc1c61 JM |
552 | /* Only calibrate if awake */ |
553 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
554 | goto set_timer; | |
555 | ||
556 | ath9k_ps_wakeup(sc); | |
557 | ||
ff37e337 | 558 | /* Long calibration runs independently of short calibration. */ |
6044474e | 559 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
ff37e337 | 560 | longcal = true; |
3d536acf | 561 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
562 | } |
563 | ||
17d7904d | 564 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
565 | if (!common->ani.caldone) { |
566 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 567 | shortcal = true; |
3d536acf LR |
568 | common->ani.shortcal_timer = timestamp; |
569 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
570 | } |
571 | } else { | |
3d536acf | 572 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 573 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
574 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
575 | if (common->ani.caldone) | |
576 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
577 | } |
578 | } | |
579 | ||
580 | /* Verify whether we must check ANI */ | |
4279425c NM |
581 | if (sc->sc_ah->config.enable_ani |
582 | && (timestamp - common->ani.checkani_timer) >= | |
583 | ah->config.ani_poll_interval) { | |
ff37e337 | 584 | aniflag = true; |
3d536acf | 585 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
586 | } |
587 | ||
e62ddec9 MSS |
588 | /* Call ANI routine if necessary */ |
589 | if (aniflag) { | |
590 | spin_lock_irqsave(&common->cc_lock, flags); | |
591 | ath9k_hw_ani_monitor(ah, ah->curchan); | |
592 | ath_update_survey_stats(sc); | |
593 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
594 | } | |
ff37e337 | 595 | |
e62ddec9 MSS |
596 | /* Perform calibration if necessary */ |
597 | if (longcal || shortcal) { | |
598 | common->ani.caldone = | |
599 | ath9k_hw_calibrate(ah, ah->curchan, | |
82b2d334 | 600 | ah->rxchainmask, longcal); |
ff37e337 S |
601 | } |
602 | ||
d2182b69 JP |
603 | ath_dbg(common, ANI, |
604 | "Calibration @%lu finished: %s %s %s, caldone: %s\n", | |
605 | jiffies, | |
86951359 NM |
606 | longcal ? "long" : "", shortcal ? "short" : "", |
607 | aniflag ? "ani" : "", common->ani.caldone ? "true" : "false"); | |
608 | ||
1ffc1c61 JM |
609 | ath9k_ps_restore(sc); |
610 | ||
20977d3e | 611 | set_timer: |
ff37e337 S |
612 | /* |
613 | * Set timer interval based on previous results. | |
614 | * The interval must be the shortest necessary to satisfy ANI, | |
615 | * short calibration and long calibration. | |
616 | */ | |
cf3af748 | 617 | ath9k_debug_samp_bb_mac(sc); |
aac9207e | 618 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 619 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
620 | cal_interval = min(cal_interval, |
621 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 622 | if (!common->ani.caldone) |
20977d3e | 623 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 624 | |
3d536acf | 625 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
20bd2a09 FF |
626 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { |
627 | if (!ah->caldata->paprd_done) | |
9f42c2b6 | 628 | ieee80211_queue_work(sc->hw, &sc->paprd_work); |
45ef6a0b | 629 | else if (!ah->paprd_table_write_done) |
9f42c2b6 FF |
630 | ath_paprd_activate(sc); |
631 | } | |
ff37e337 S |
632 | } |
633 | ||
7e1e3864 BG |
634 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, |
635 | struct ieee80211_vif *vif) | |
ff37e337 S |
636 | { |
637 | struct ath_node *an; | |
ff37e337 S |
638 | an = (struct ath_node *)sta->drv_priv; |
639 | ||
7f010c93 BG |
640 | #ifdef CONFIG_ATH9K_DEBUGFS |
641 | spin_lock(&sc->nodes_lock); | |
642 | list_add(&an->list, &sc->nodes); | |
643 | spin_unlock(&sc->nodes_lock); | |
156369fa | 644 | #endif |
7f010c93 | 645 | an->sta = sta; |
7e1e3864 | 646 | an->vif = vif; |
3d4e20f2 | 647 | |
a4d6367f | 648 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
ff37e337 | 649 | ath_tx_node_init(sc, an); |
9e98ac65 | 650 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
651 | sta->ht_cap.ampdu_factor); |
652 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
653 | } | |
ff37e337 S |
654 | } |
655 | ||
656 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
657 | { | |
658 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
659 | ||
7f010c93 BG |
660 | #ifdef CONFIG_ATH9K_DEBUGFS |
661 | spin_lock(&sc->nodes_lock); | |
662 | list_del(&an->list); | |
663 | spin_unlock(&sc->nodes_lock); | |
664 | an->sta = NULL; | |
665 | #endif | |
666 | ||
a4d6367f | 667 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
ff37e337 S |
668 | ath_tx_node_cleanup(sc, an); |
669 | } | |
670 | ||
9eab61c2 | 671 | |
55624204 | 672 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
673 | { |
674 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 675 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 676 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 677 | |
17d7904d | 678 | u32 status = sc->intrstatus; |
b5c80475 | 679 | u32 rxmask; |
ff37e337 | 680 | |
e3927007 FF |
681 | ath9k_ps_wakeup(sc); |
682 | spin_lock(&sc->sc_pcu_lock); | |
683 | ||
a4d86d95 RM |
684 | if ((status & ATH9K_INT_FATAL) || |
685 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
030d6294 FF |
686 | #ifdef CONFIG_ATH9K_DEBUGFS |
687 | enum ath_reset_type type; | |
688 | ||
689 | if (status & ATH9K_INT_FATAL) | |
690 | type = RESET_TYPE_FATAL_INT; | |
691 | else | |
692 | type = RESET_TYPE_BB_WATCHDOG; | |
693 | ||
694 | RESET_STAT_INC(sc, type); | |
695 | #endif | |
236de514 | 696 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
e3927007 | 697 | goto out; |
063d8be3 | 698 | } |
ff37e337 | 699 | |
4105f807 RM |
700 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
701 | /* | |
702 | * TSF sync does not look correct; remain awake to sync with | |
703 | * the next Beacon. | |
704 | */ | |
d2182b69 | 705 | ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); |
e8fe7336 | 706 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
4105f807 RM |
707 | } |
708 | ||
b5c80475 FF |
709 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
710 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
711 | ATH9K_INT_RXORN); | |
712 | else | |
713 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
714 | ||
715 | if (status & rxmask) { | |
b5c80475 FF |
716 | /* Check for high priority Rx first */ |
717 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
718 | (status & ATH9K_INT_RXHP)) | |
719 | ath_rx_tasklet(sc, 0, true); | |
720 | ||
721 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
722 | } |
723 | ||
e5003249 VT |
724 | if (status & ATH9K_INT_TX) { |
725 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
726 | ath_tx_edma_tasklet(sc); | |
727 | else | |
728 | ath_tx_tasklet(sc); | |
729 | } | |
063d8be3 | 730 | |
56ca0dba | 731 | ath9k_btcoex_handle_interrupt(sc, status); |
19686ddf | 732 | |
e3927007 | 733 | out: |
ff37e337 | 734 | /* re-enable hardware interrupt */ |
4df3071e | 735 | ath9k_hw_enable_interrupts(ah); |
6a6733f2 | 736 | |
52671e43 | 737 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 738 | ath9k_ps_restore(sc); |
ff37e337 S |
739 | } |
740 | ||
6baff7f9 | 741 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 742 | { |
063d8be3 S |
743 | #define SCHED_INTR ( \ |
744 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 745 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
746 | ATH9K_INT_RXORN | \ |
747 | ATH9K_INT_RXEOL | \ | |
748 | ATH9K_INT_RX | \ | |
b5c80475 FF |
749 | ATH9K_INT_RXLP | \ |
750 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
751 | ATH9K_INT_TX | \ |
752 | ATH9K_INT_BMISS | \ | |
753 | ATH9K_INT_CST | \ | |
ebb8e1d7 | 754 | ATH9K_INT_TSFOOR | \ |
40dc5392 MSS |
755 | ATH9K_INT_GENTIMER | \ |
756 | ATH9K_INT_MCI) | |
063d8be3 | 757 | |
ff37e337 | 758 | struct ath_softc *sc = dev; |
cbe61d8a | 759 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 760 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
761 | enum ath9k_int status; |
762 | bool sched = false; | |
763 | ||
063d8be3 S |
764 | /* |
765 | * The hardware is not ready/present, don't | |
766 | * touch anything. Note this can happen early | |
767 | * on if the IRQ is shared. | |
768 | */ | |
769 | if (sc->sc_flags & SC_OP_INVALID) | |
770 | return IRQ_NONE; | |
ff37e337 | 771 | |
063d8be3 S |
772 | |
773 | /* shared irq, not for us */ | |
774 | ||
153e080d | 775 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 776 | return IRQ_NONE; |
063d8be3 S |
777 | |
778 | /* | |
779 | * Figure out the reason(s) for the interrupt. Note | |
780 | * that the hal returns a pseudo-ISR that may include | |
781 | * bits we haven't explicitly enabled so we mask the | |
782 | * value to insure we only process bits we requested. | |
783 | */ | |
784 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 785 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 786 | |
063d8be3 S |
787 | /* |
788 | * If there are no status bits set, then this interrupt was not | |
789 | * for me (should have been caught above). | |
790 | */ | |
153e080d | 791 | if (!status) |
063d8be3 | 792 | return IRQ_NONE; |
ff37e337 | 793 | |
063d8be3 S |
794 | /* Cache the status */ |
795 | sc->intrstatus = status; | |
796 | ||
797 | if (status & SCHED_INTR) | |
798 | sched = true; | |
799 | ||
800 | /* | |
801 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
802 | * chip immediately. | |
803 | */ | |
b5c80475 FF |
804 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
805 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
806 | goto chip_reset; |
807 | ||
08578b8f LR |
808 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
809 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
810 | |
811 | spin_lock(&common->cc_lock); | |
812 | ath_hw_cycle_counters_update(common); | |
08578b8f | 813 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
814 | spin_unlock(&common->cc_lock); |
815 | ||
08578b8f LR |
816 | goto chip_reset; |
817 | } | |
818 | ||
063d8be3 S |
819 | if (status & ATH9K_INT_SWBA) |
820 | tasklet_schedule(&sc->bcon_tasklet); | |
821 | ||
822 | if (status & ATH9K_INT_TXURN) | |
823 | ath9k_hw_updatetxtriglevel(ah, true); | |
824 | ||
0682c9b5 RM |
825 | if (status & ATH9K_INT_RXEOL) { |
826 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 827 | ath9k_hw_set_interrupts(ah); |
b5c80475 FF |
828 | } |
829 | ||
063d8be3 | 830 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 831 | /* |
063d8be3 S |
832 | * Disable interrupts until we service the MIB |
833 | * interrupt; otherwise it will continue to | |
834 | * fire. | |
ff37e337 | 835 | */ |
4df3071e | 836 | ath9k_hw_disable_interrupts(ah); |
063d8be3 S |
837 | /* |
838 | * Let the hal handle the event. We assume | |
839 | * it will clear whatever condition caused | |
840 | * the interrupt. | |
841 | */ | |
88eac2da | 842 | spin_lock(&common->cc_lock); |
bfc472bb | 843 | ath9k_hw_proc_mib_event(ah); |
88eac2da | 844 | spin_unlock(&common->cc_lock); |
4df3071e | 845 | ath9k_hw_enable_interrupts(ah); |
063d8be3 | 846 | } |
ff37e337 | 847 | |
153e080d VT |
848 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
849 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
850 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
851 | goto chip_reset; | |
063d8be3 S |
852 | /* Clear RxAbort bit so that we can |
853 | * receive frames */ | |
9ecdef4b | 854 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 855 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 856 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 857 | } |
063d8be3 S |
858 | |
859 | chip_reset: | |
ff37e337 | 860 | |
817e11de S |
861 | ath_debug_stat_interrupt(sc, status); |
862 | ||
ff37e337 | 863 | if (sched) { |
4df3071e FF |
864 | /* turn off every interrupt */ |
865 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
866 | tasklet_schedule(&sc->intr_tq); |
867 | } | |
868 | ||
869 | return IRQ_HANDLED; | |
063d8be3 S |
870 | |
871 | #undef SCHED_INTR | |
ff37e337 S |
872 | } |
873 | ||
236de514 | 874 | static int ath_reset(struct ath_softc *sc, bool retry_tx) |
ff37e337 | 875 | { |
ae8d2858 | 876 | int r; |
ff37e337 | 877 | |
783cd01e | 878 | ath9k_ps_wakeup(sc); |
6a6733f2 | 879 | |
9adcf440 | 880 | r = ath_reset_internal(sc, NULL, retry_tx); |
ff37e337 S |
881 | |
882 | if (retry_tx) { | |
883 | int i; | |
884 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
885 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
886 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
887 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
888 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
889 | } |
890 | } | |
891 | } | |
892 | ||
783cd01e | 893 | ath9k_ps_restore(sc); |
2ab81d4a | 894 | |
ae8d2858 | 895 | return r; |
ff37e337 S |
896 | } |
897 | ||
236de514 FF |
898 | void ath_reset_work(struct work_struct *work) |
899 | { | |
900 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | |
901 | ||
236de514 | 902 | ath_reset(sc, true); |
236de514 FF |
903 | } |
904 | ||
e8cfe9f8 FF |
905 | void ath_hw_check(struct work_struct *work) |
906 | { | |
907 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
908 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
909 | unsigned long flags; | |
910 | int busy; | |
01e18918 | 911 | u8 is_alive, nbeacon = 1; |
e8cfe9f8 FF |
912 | |
913 | ath9k_ps_wakeup(sc); | |
01e18918 RM |
914 | is_alive = ath9k_hw_check_alive(sc->sc_ah); |
915 | ||
916 | if (is_alive && !AR_SREV_9300(sc->sc_ah)) | |
e8cfe9f8 | 917 | goto out; |
01e18918 RM |
918 | else if (!is_alive && AR_SREV_9300(sc->sc_ah)) { |
919 | ath_dbg(common, RESET, | |
920 | "DCU stuck is detected. Schedule chip reset\n"); | |
921 | RESET_STAT_INC(sc, RESET_TYPE_MAC_HANG); | |
922 | goto sched_reset; | |
923 | } | |
e8cfe9f8 FF |
924 | |
925 | spin_lock_irqsave(&common->cc_lock, flags); | |
926 | busy = ath_update_survey_stats(sc); | |
927 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
928 | ||
d2182b69 JP |
929 | ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n", |
930 | busy, sc->hw_busy_count + 1); | |
e8cfe9f8 | 931 | if (busy >= 99) { |
030d6294 FF |
932 | if (++sc->hw_busy_count >= 3) { |
933 | RESET_STAT_INC(sc, RESET_TYPE_BB_HANG); | |
01e18918 | 934 | goto sched_reset; |
030d6294 | 935 | } |
01e18918 | 936 | } else if (busy >= 0) { |
e8cfe9f8 | 937 | sc->hw_busy_count = 0; |
01e18918 RM |
938 | nbeacon = 3; |
939 | } | |
e8cfe9f8 | 940 | |
01e18918 RM |
941 | ath_start_rx_poll(sc, nbeacon); |
942 | goto out; | |
943 | ||
944 | sched_reset: | |
945 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | |
e8cfe9f8 FF |
946 | out: |
947 | ath9k_ps_restore(sc); | |
948 | } | |
949 | ||
950 | static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum) | |
951 | { | |
952 | static int count; | |
953 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
954 | ||
955 | if (pll_sqsum >= 0x40000) { | |
956 | count++; | |
957 | if (count == 3) { | |
958 | /* Rx is hung for more than 500ms. Reset it */ | |
d2182b69 | 959 | ath_dbg(common, RESET, "Possible RX hang, resetting\n"); |
030d6294 | 960 | RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG); |
9adcf440 | 961 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
e8cfe9f8 FF |
962 | count = 0; |
963 | } | |
964 | } else | |
965 | count = 0; | |
966 | } | |
967 | ||
968 | void ath_hw_pll_work(struct work_struct *work) | |
969 | { | |
970 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
971 | hw_pll_work.work); | |
972 | u32 pll_sqsum; | |
973 | ||
bcb7ad7b MSS |
974 | /* |
975 | * ensure that the PLL WAR is executed only | |
976 | * after the STA is associated (or) if the | |
977 | * beaconing had started in interfaces that | |
978 | * uses beacons. | |
979 | */ | |
980 | if (!(sc->sc_flags & SC_OP_BEACONS)) | |
981 | return; | |
982 | ||
e8cfe9f8 FF |
983 | if (AR_SREV_9485(sc->sc_ah)) { |
984 | ||
985 | ath9k_ps_wakeup(sc); | |
986 | pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah); | |
987 | ath9k_ps_restore(sc); | |
988 | ||
989 | ath_hw_pll_rx_hang_check(sc, pll_sqsum); | |
990 | ||
991 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5); | |
992 | } | |
993 | } | |
994 | ||
ff37e337 S |
995 | /**********************/ |
996 | /* mac80211 callbacks */ | |
997 | /**********************/ | |
998 | ||
8feceb67 | 999 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1000 | { |
9ac58615 | 1001 | struct ath_softc *sc = hw->priv; |
af03abec | 1002 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1003 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1004 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1005 | struct ath9k_channel *init_channel; |
82880a7c | 1006 | int r; |
f078f209 | 1007 | |
d2182b69 | 1008 | ath_dbg(common, CONFIG, |
226afe68 JP |
1009 | "Starting driver with initial channel: %d MHz\n", |
1010 | curchan->center_freq); | |
f078f209 | 1011 | |
f62d816f | 1012 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1013 | mutex_lock(&sc->mutex); |
1014 | ||
c344c9cb | 1015 | init_channel = ath9k_cmn_get_curchannel(hw, ah); |
ff37e337 S |
1016 | |
1017 | /* Reset SERDES registers */ | |
84c87dc8 | 1018 | ath9k_hw_configpcipowersave(ah, false); |
ff37e337 S |
1019 | |
1020 | /* | |
1021 | * The basic interface to setting the hardware in a good | |
1022 | * state is ``reset''. On return the hardware is known to | |
1023 | * be powered up and with interrupts disabled. This must | |
1024 | * be followed by initialization of the appropriate bits | |
1025 | * and then setup of the interrupt mask. | |
1026 | */ | |
4bdd1e97 | 1027 | spin_lock_bh(&sc->sc_pcu_lock); |
c0c11741 FF |
1028 | |
1029 | atomic_set(&ah->intr_ref_cnt, -1); | |
1030 | ||
20bd2a09 | 1031 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 1032 | if (r) { |
3800276a JP |
1033 | ath_err(common, |
1034 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
1035 | r, curchan->center_freq); | |
4bdd1e97 | 1036 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 1037 | goto mutex_unlock; |
ff37e337 | 1038 | } |
ff37e337 | 1039 | |
ff37e337 | 1040 | /* Setup our intr mask. */ |
b5c80475 FF |
1041 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1042 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1043 | ATH9K_INT_GLOBAL; | |
1044 | ||
1045 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1046 | ah->imask |= ATH9K_INT_RXHP | |
1047 | ATH9K_INT_RXLP | | |
1048 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1049 | else |
1050 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1051 | |
364734fa | 1052 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1053 | |
af03abec | 1054 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1055 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1056 | |
40dc5392 MSS |
1057 | if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) |
1058 | ah->imask |= ATH9K_INT_MCI; | |
1059 | ||
ff37e337 | 1060 | sc->sc_flags &= ~SC_OP_INVALID; |
5f841b41 | 1061 | sc->sc_ah->is_monitoring = false; |
ff37e337 | 1062 | |
9adcf440 FF |
1063 | if (!ath_complete_reset(sc, false)) { |
1064 | r = -EIO; | |
1065 | spin_unlock_bh(&sc->sc_pcu_lock); | |
1066 | goto mutex_unlock; | |
1067 | } | |
ff37e337 | 1068 | |
c0c11741 FF |
1069 | if (ah->led_pin >= 0) { |
1070 | ath9k_hw_cfg_output(ah, ah->led_pin, | |
1071 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
1072 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); | |
1073 | } | |
1074 | ||
1075 | /* | |
1076 | * Reset key cache to sane defaults (all entries cleared) instead of | |
1077 | * semi-random values after suspend/resume. | |
1078 | */ | |
1079 | ath9k_cmn_init_crypto(sc->sc_ah); | |
1080 | ||
9adcf440 | 1081 | spin_unlock_bh(&sc->sc_pcu_lock); |
164ace38 | 1082 | |
df198b17 | 1083 | ath9k_start_btcoex(sc); |
1773912b | 1084 | |
8060e169 VT |
1085 | if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) |
1086 | common->bus_ops->extn_synch_en(common); | |
1087 | ||
141b38b6 S |
1088 | mutex_unlock: |
1089 | mutex_unlock(&sc->mutex); | |
1090 | ||
f62d816f FF |
1091 | ath9k_ps_restore(sc); |
1092 | ||
ae8d2858 | 1093 | return r; |
f078f209 LR |
1094 | } |
1095 | ||
7bb45683 | 1096 | static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1097 | { |
9ac58615 | 1098 | struct ath_softc *sc = hw->priv; |
c46917bb | 1099 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1100 | struct ath_tx_control txctl; |
1bc14880 | 1101 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
528f0c6b | 1102 | |
96148326 | 1103 | if (sc->ps_enabled) { |
dc8c4585 JM |
1104 | /* |
1105 | * mac80211 does not set PM field for normal data frames, so we | |
1106 | * need to update that based on the current PS mode. | |
1107 | */ | |
1108 | if (ieee80211_is_data(hdr->frame_control) && | |
1109 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1110 | !ieee80211_has_pm(hdr->frame_control)) { | |
d2182b69 | 1111 | ath_dbg(common, PS, |
226afe68 | 1112 | "Add PM=1 for a TX frame while in PS mode\n"); |
dc8c4585 JM |
1113 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1114 | } | |
1115 | } | |
1116 | ||
ad128860 | 1117 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { |
9a23f9ca JM |
1118 | /* |
1119 | * We are using PS-Poll and mac80211 can request TX while in | |
1120 | * power save mode. Need to wake up hardware for the TX to be | |
1121 | * completed and if needed, also for RX of buffered frames. | |
1122 | */ | |
9a23f9ca | 1123 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1124 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1125 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1126 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
d2182b69 | 1127 | ath_dbg(common, PS, |
226afe68 | 1128 | "Sending PS-Poll to pick a buffered frame\n"); |
1b04b930 | 1129 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1130 | } else { |
d2182b69 | 1131 | ath_dbg(common, PS, "Wake up to complete TX\n"); |
1b04b930 | 1132 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1133 | } |
1134 | /* | |
1135 | * The actual restore operation will happen only after | |
ad128860 | 1136 | * the ps_flags bit is cleared. We are just dropping |
9a23f9ca JM |
1137 | * the ps_usecount here. |
1138 | */ | |
1139 | ath9k_ps_restore(sc); | |
1140 | } | |
1141 | ||
ad128860 SM |
1142 | /* |
1143 | * Cannot tx while the hardware is in full sleep, it first needs a full | |
1144 | * chip reset to recover from that | |
1145 | */ | |
1146 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { | |
1147 | ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); | |
1148 | goto exit; | |
1149 | } | |
1150 | ||
528f0c6b | 1151 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 1152 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
528f0c6b | 1153 | |
d2182b69 | 1154 | ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1155 | |
c52f33d0 | 1156 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
d2182b69 | 1157 | ath_dbg(common, XMIT, "TX failed\n"); |
a5a0bca1 | 1158 | TX_STAT_INC(txctl.txq->axq_qnum, txfailed); |
528f0c6b | 1159 | goto exit; |
8feceb67 VT |
1160 | } |
1161 | ||
7bb45683 | 1162 | return; |
528f0c6b S |
1163 | exit: |
1164 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1165 | } |
1166 | ||
8feceb67 | 1167 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1168 | { |
9ac58615 | 1169 | struct ath_softc *sc = hw->priv; |
af03abec | 1170 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1171 | struct ath_common *common = ath9k_hw_common(ah); |
c0c11741 | 1172 | bool prev_idle; |
f078f209 | 1173 | |
4c483817 S |
1174 | mutex_lock(&sc->mutex); |
1175 | ||
9adcf440 | 1176 | ath_cancel_work(sc); |
01e18918 | 1177 | del_timer_sync(&sc->rx_poll_timer); |
c94dbff7 | 1178 | |
9c84b797 | 1179 | if (sc->sc_flags & SC_OP_INVALID) { |
d2182b69 | 1180 | ath_dbg(common, ANY, "Device not present\n"); |
4c483817 | 1181 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1182 | return; |
1183 | } | |
8feceb67 | 1184 | |
3867cf6a S |
1185 | /* Ensure HW is awake when we try to shut it down. */ |
1186 | ath9k_ps_wakeup(sc); | |
1187 | ||
df198b17 | 1188 | ath9k_stop_btcoex(sc); |
1773912b | 1189 | |
6a6733f2 LR |
1190 | spin_lock_bh(&sc->sc_pcu_lock); |
1191 | ||
203043f5 SG |
1192 | /* prevent tasklets to enable interrupts once we disable them */ |
1193 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
1194 | ||
ff37e337 S |
1195 | /* make sure h/w will not generate any interrupt |
1196 | * before setting the invalid flag. */ | |
4df3071e | 1197 | ath9k_hw_disable_interrupts(ah); |
ff37e337 | 1198 | |
c0c11741 FF |
1199 | spin_unlock_bh(&sc->sc_pcu_lock); |
1200 | ||
1201 | /* we can now sync irq and kill any running tasklets, since we already | |
1202 | * disabled interrupts and not holding a spin lock */ | |
1203 | synchronize_irq(sc->irq); | |
1204 | tasklet_kill(&sc->intr_tq); | |
1205 | tasklet_kill(&sc->bcon_tasklet); | |
1206 | ||
1207 | prev_idle = sc->ps_idle; | |
1208 | sc->ps_idle = true; | |
1209 | ||
1210 | spin_lock_bh(&sc->sc_pcu_lock); | |
1211 | ||
1212 | if (ah->led_pin >= 0) { | |
1213 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
1214 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
1215 | } | |
1216 | ||
1217 | ath_prepare_reset(sc, false, true); | |
ff37e337 | 1218 | |
0d95521e FF |
1219 | if (sc->rx.frag) { |
1220 | dev_kfree_skb_any(sc->rx.frag); | |
1221 | sc->rx.frag = NULL; | |
1222 | } | |
1223 | ||
c0c11741 FF |
1224 | if (!ah->curchan) |
1225 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); | |
6a6733f2 | 1226 | |
c0c11741 FF |
1227 | ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
1228 | ath9k_hw_phy_disable(ah); | |
6a6733f2 | 1229 | |
c0c11741 | 1230 | ath9k_hw_configpcipowersave(ah, true); |
203043f5 | 1231 | |
c0c11741 | 1232 | spin_unlock_bh(&sc->sc_pcu_lock); |
3867cf6a | 1233 | |
c0c11741 | 1234 | ath9k_ps_restore(sc); |
ff37e337 S |
1235 | |
1236 | sc->sc_flags |= SC_OP_INVALID; | |
c0c11741 | 1237 | sc->ps_idle = prev_idle; |
500c064d | 1238 | |
141b38b6 S |
1239 | mutex_unlock(&sc->mutex); |
1240 | ||
d2182b69 | 1241 | ath_dbg(common, CONFIG, "Driver halt\n"); |
f078f209 LR |
1242 | } |
1243 | ||
4801416c BG |
1244 | bool ath9k_uses_beacons(int type) |
1245 | { | |
1246 | switch (type) { | |
1247 | case NL80211_IFTYPE_AP: | |
1248 | case NL80211_IFTYPE_ADHOC: | |
1249 | case NL80211_IFTYPE_MESH_POINT: | |
1250 | return true; | |
1251 | default: | |
1252 | return false; | |
1253 | } | |
1254 | } | |
1255 | ||
1256 | static void ath9k_reclaim_beacon(struct ath_softc *sc, | |
1257 | struct ieee80211_vif *vif) | |
f078f209 | 1258 | { |
1ed32e4f | 1259 | struct ath_vif *avp = (void *)vif->drv_priv; |
8feceb67 | 1260 | |
014cf3bb | 1261 | ath9k_set_beaconing_status(sc, false); |
4801416c | 1262 | ath_beacon_return(sc, avp); |
014cf3bb | 1263 | ath9k_set_beaconing_status(sc, true); |
4801416c BG |
1264 | } |
1265 | ||
1266 | static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) | |
1267 | { | |
1268 | struct ath9k_vif_iter_data *iter_data = data; | |
1269 | int i; | |
1270 | ||
1271 | if (iter_data->hw_macaddr) | |
1272 | for (i = 0; i < ETH_ALEN; i++) | |
1273 | iter_data->mask[i] &= | |
1274 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
141b38b6 | 1275 | |
1ed32e4f | 1276 | switch (vif->type) { |
4801416c BG |
1277 | case NL80211_IFTYPE_AP: |
1278 | iter_data->naps++; | |
f078f209 | 1279 | break; |
4801416c BG |
1280 | case NL80211_IFTYPE_STATION: |
1281 | iter_data->nstations++; | |
e51f3eff | 1282 | break; |
05c914fe | 1283 | case NL80211_IFTYPE_ADHOC: |
4801416c BG |
1284 | iter_data->nadhocs++; |
1285 | break; | |
9cb5412b | 1286 | case NL80211_IFTYPE_MESH_POINT: |
4801416c BG |
1287 | iter_data->nmeshes++; |
1288 | break; | |
1289 | case NL80211_IFTYPE_WDS: | |
1290 | iter_data->nwds++; | |
f078f209 LR |
1291 | break; |
1292 | default: | |
4801416c | 1293 | break; |
f078f209 | 1294 | } |
4801416c | 1295 | } |
f078f209 | 1296 | |
4801416c BG |
1297 | /* Called with sc->mutex held. */ |
1298 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
1299 | struct ieee80211_vif *vif, | |
1300 | struct ath9k_vif_iter_data *iter_data) | |
1301 | { | |
9ac58615 | 1302 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1303 | struct ath_hw *ah = sc->sc_ah; |
1304 | struct ath_common *common = ath9k_hw_common(ah); | |
8feceb67 | 1305 | |
4801416c BG |
1306 | /* |
1307 | * Use the hardware MAC address as reference, the hardware uses it | |
1308 | * together with the BSSID mask when matching addresses. | |
1309 | */ | |
1310 | memset(iter_data, 0, sizeof(*iter_data)); | |
1311 | iter_data->hw_macaddr = common->macaddr; | |
1312 | memset(&iter_data->mask, 0xff, ETH_ALEN); | |
5640b08e | 1313 | |
4801416c BG |
1314 | if (vif) |
1315 | ath9k_vif_iter(iter_data, vif->addr, vif); | |
1316 | ||
1317 | /* Get list of all active MAC addresses */ | |
4801416c BG |
1318 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, |
1319 | iter_data); | |
4801416c | 1320 | } |
8ca21f01 | 1321 | |
4801416c BG |
1322 | /* Called with sc->mutex held. */ |
1323 | static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, | |
1324 | struct ieee80211_vif *vif) | |
1325 | { | |
9ac58615 | 1326 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1327 | struct ath_hw *ah = sc->sc_ah; |
1328 | struct ath_common *common = ath9k_hw_common(ah); | |
1329 | struct ath9k_vif_iter_data iter_data; | |
8ca21f01 | 1330 | |
4801416c | 1331 | ath9k_calculate_iter_data(hw, vif, &iter_data); |
2c3db3d5 | 1332 | |
4801416c BG |
1333 | /* Set BSSID mask. */ |
1334 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); | |
1335 | ath_hw_setbssidmask(common); | |
1336 | ||
1337 | /* Set op-mode & TSF */ | |
1338 | if (iter_data.naps > 0) { | |
3069168c | 1339 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e | 1340 | sc->sc_flags |= SC_OP_TSF_RESET; |
4801416c BG |
1341 | ah->opmode = NL80211_IFTYPE_AP; |
1342 | } else { | |
1343 | ath9k_hw_set_tsfadjust(ah, 0); | |
1344 | sc->sc_flags &= ~SC_OP_TSF_RESET; | |
5640b08e | 1345 | |
fd5999cf JC |
1346 | if (iter_data.nmeshes) |
1347 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
1348 | else if (iter_data.nwds) | |
4801416c BG |
1349 | ah->opmode = NL80211_IFTYPE_AP; |
1350 | else if (iter_data.nadhocs) | |
1351 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
1352 | else | |
1353 | ah->opmode = NL80211_IFTYPE_STATION; | |
1354 | } | |
5640b08e | 1355 | |
4e30ffa2 VN |
1356 | /* |
1357 | * Enable MIB interrupts when there are hardware phy counters. | |
4e30ffa2 | 1358 | */ |
4801416c | 1359 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) { |
3448f912 LR |
1360 | if (ah->config.enable_ani) |
1361 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1362 | ah->imask |= ATH9K_INT_TSFOOR; |
4801416c BG |
1363 | } else { |
1364 | ah->imask &= ~ATH9K_INT_MIB; | |
1365 | ah->imask &= ~ATH9K_INT_TSFOOR; | |
4af9cf4f S |
1366 | } |
1367 | ||
72d874c6 | 1368 | ath9k_hw_set_interrupts(ah); |
4e30ffa2 | 1369 | |
4801416c | 1370 | /* Set up ANI */ |
2e5ef459 | 1371 | if (iter_data.naps > 0) { |
729da390 | 1372 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
05c0be2f MSS |
1373 | |
1374 | if (!common->disable_ani) { | |
1375 | sc->sc_flags |= SC_OP_ANI_RUN; | |
1376 | ath_start_ani(common); | |
1377 | } | |
1378 | ||
f60c49b6 RM |
1379 | } else { |
1380 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
1381 | del_timer_sync(&common->ani.timer); | |
6c3118e2 | 1382 | } |
4801416c | 1383 | } |
6f255425 | 1384 | |
4801416c BG |
1385 | /* Called with sc->mutex held, vif counts set up properly. */ |
1386 | static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw, | |
1387 | struct ieee80211_vif *vif) | |
1388 | { | |
9ac58615 | 1389 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1390 | |
1391 | ath9k_calculate_summary_state(hw, vif); | |
1392 | ||
1393 | if (ath9k_uses_beacons(vif->type)) { | |
ed2578cd | 1394 | /* Reserve a beacon slot for the vif */ |
014cf3bb | 1395 | ath9k_set_beaconing_status(sc, false); |
ed2578cd | 1396 | ath_beacon_alloc(sc, vif); |
014cf3bb | 1397 | ath9k_set_beaconing_status(sc, true); |
4801416c | 1398 | } |
f078f209 LR |
1399 | } |
1400 | ||
01e18918 RM |
1401 | void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon) |
1402 | { | |
1403 | if (!AR_SREV_9300(sc->sc_ah)) | |
1404 | return; | |
1405 | ||
1406 | if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) | |
1407 | return; | |
1408 | ||
1409 | mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies | |
1410 | (nbeacon * sc->cur_beacon_conf.beacon_interval)); | |
1411 | } | |
1412 | ||
1413 | void ath_rx_poll(unsigned long data) | |
1414 | { | |
1415 | struct ath_softc *sc = (struct ath_softc *)data; | |
1416 | ||
1417 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); | |
1418 | } | |
4801416c BG |
1419 | |
1420 | static int ath9k_add_interface(struct ieee80211_hw *hw, | |
1421 | struct ieee80211_vif *vif) | |
6b3b991d | 1422 | { |
9ac58615 | 1423 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1424 | struct ath_hw *ah = sc->sc_ah; |
1425 | struct ath_common *common = ath9k_hw_common(ah); | |
4801416c | 1426 | int ret = 0; |
6b3b991d | 1427 | |
96f372c9 | 1428 | ath9k_ps_wakeup(sc); |
4801416c | 1429 | mutex_lock(&sc->mutex); |
6b3b991d | 1430 | |
4801416c BG |
1431 | switch (vif->type) { |
1432 | case NL80211_IFTYPE_STATION: | |
1433 | case NL80211_IFTYPE_WDS: | |
1434 | case NL80211_IFTYPE_ADHOC: | |
1435 | case NL80211_IFTYPE_AP: | |
1436 | case NL80211_IFTYPE_MESH_POINT: | |
1437 | break; | |
1438 | default: | |
1439 | ath_err(common, "Interface type %d not yet supported\n", | |
1440 | vif->type); | |
1441 | ret = -EOPNOTSUPP; | |
1442 | goto out; | |
1443 | } | |
6b3b991d | 1444 | |
4801416c BG |
1445 | if (ath9k_uses_beacons(vif->type)) { |
1446 | if (sc->nbcnvifs >= ATH_BCBUF) { | |
1447 | ath_err(common, "Not enough beacon buffers when adding" | |
1448 | " new interface of type: %i\n", | |
1449 | vif->type); | |
1450 | ret = -ENOBUFS; | |
1451 | goto out; | |
1452 | } | |
1453 | } | |
1454 | ||
d2182b69 | 1455 | ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); |
4801416c | 1456 | |
4801416c BG |
1457 | sc->nvifs++; |
1458 | ||
1459 | ath9k_do_vif_add_setup(hw, vif); | |
1460 | out: | |
1461 | mutex_unlock(&sc->mutex); | |
96f372c9 | 1462 | ath9k_ps_restore(sc); |
4801416c | 1463 | return ret; |
6b3b991d RM |
1464 | } |
1465 | ||
1466 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1467 | struct ieee80211_vif *vif, | |
1468 | enum nl80211_iftype new_type, | |
1469 | bool p2p) | |
1470 | { | |
9ac58615 | 1471 | struct ath_softc *sc = hw->priv; |
6b3b991d | 1472 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
6dab55bf | 1473 | int ret = 0; |
6b3b991d | 1474 | |
d2182b69 | 1475 | ath_dbg(common, CONFIG, "Change Interface\n"); |
6b3b991d | 1476 | mutex_lock(&sc->mutex); |
96f372c9 | 1477 | ath9k_ps_wakeup(sc); |
6b3b991d | 1478 | |
4801416c BG |
1479 | if (ath9k_uses_beacons(new_type) && |
1480 | !ath9k_uses_beacons(vif->type)) { | |
6b3b991d RM |
1481 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1482 | ath_err(common, "No beacon slot available\n"); | |
6dab55bf DC |
1483 | ret = -ENOBUFS; |
1484 | goto out; | |
6b3b991d | 1485 | } |
6b3b991d | 1486 | } |
4801416c BG |
1487 | |
1488 | /* Clean up old vif stuff */ | |
1489 | if (ath9k_uses_beacons(vif->type)) | |
1490 | ath9k_reclaim_beacon(sc, vif); | |
1491 | ||
1492 | /* Add new settings */ | |
6b3b991d RM |
1493 | vif->type = new_type; |
1494 | vif->p2p = p2p; | |
1495 | ||
4801416c | 1496 | ath9k_do_vif_add_setup(hw, vif); |
6dab55bf | 1497 | out: |
96f372c9 | 1498 | ath9k_ps_restore(sc); |
6b3b991d | 1499 | mutex_unlock(&sc->mutex); |
6dab55bf | 1500 | return ret; |
6b3b991d RM |
1501 | } |
1502 | ||
8feceb67 | 1503 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1504 | struct ieee80211_vif *vif) |
f078f209 | 1505 | { |
9ac58615 | 1506 | struct ath_softc *sc = hw->priv; |
c46917bb | 1507 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 | 1508 | |
d2182b69 | 1509 | ath_dbg(common, CONFIG, "Detach Interface\n"); |
f078f209 | 1510 | |
96f372c9 | 1511 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1512 | mutex_lock(&sc->mutex); |
1513 | ||
4801416c | 1514 | sc->nvifs--; |
580f0b8a | 1515 | |
8feceb67 | 1516 | /* Reclaim beacon resources */ |
4801416c | 1517 | if (ath9k_uses_beacons(vif->type)) |
6b3b991d | 1518 | ath9k_reclaim_beacon(sc, vif); |
2c3db3d5 | 1519 | |
4801416c | 1520 | ath9k_calculate_summary_state(hw, NULL); |
141b38b6 S |
1521 | |
1522 | mutex_unlock(&sc->mutex); | |
96f372c9 | 1523 | ath9k_ps_restore(sc); |
f078f209 LR |
1524 | } |
1525 | ||
fbab7390 | 1526 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1527 | { |
3069168c | 1528 | struct ath_hw *ah = sc->sc_ah; |
ad128860 | 1529 | struct ath_common *common = ath9k_hw_common(ah); |
3069168c | 1530 | |
3f7c5c10 | 1531 | sc->ps_enabled = true; |
3069168c PR |
1532 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1533 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1534 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1535 | ath9k_hw_set_interrupts(ah); |
3f7c5c10 | 1536 | } |
fdf76622 | 1537 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1538 | } |
ad128860 | 1539 | ath_dbg(common, PS, "PowerSave enabled\n"); |
3f7c5c10 SB |
1540 | } |
1541 | ||
845d708e SB |
1542 | static void ath9k_disable_ps(struct ath_softc *sc) |
1543 | { | |
1544 | struct ath_hw *ah = sc->sc_ah; | |
ad128860 | 1545 | struct ath_common *common = ath9k_hw_common(ah); |
845d708e SB |
1546 | |
1547 | sc->ps_enabled = false; | |
1548 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1549 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1550 | ath9k_hw_setrxabort(ah, 0); | |
1551 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1552 | PS_WAIT_FOR_CAB | | |
1553 | PS_WAIT_FOR_PSPOLL_DATA | | |
1554 | PS_WAIT_FOR_TX_ACK); | |
1555 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1556 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1557 | ath9k_hw_set_interrupts(ah); |
845d708e SB |
1558 | } |
1559 | } | |
ad128860 | 1560 | ath_dbg(common, PS, "PowerSave disabled\n"); |
845d708e SB |
1561 | } |
1562 | ||
e8975581 | 1563 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1564 | { |
9ac58615 | 1565 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1566 | struct ath_hw *ah = sc->sc_ah; |
1567 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1568 | struct ieee80211_conf *conf = &hw->conf; |
75600abf | 1569 | bool reset_channel = false; |
f078f209 | 1570 | |
c0c11741 | 1571 | ath9k_ps_wakeup(sc); |
aa33de09 | 1572 | mutex_lock(&sc->mutex); |
141b38b6 | 1573 | |
daa1b6ee | 1574 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 | 1575 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
daa1b6ee FF |
1576 | if (sc->ps_idle) |
1577 | ath_cancel_work(sc); | |
75600abf FF |
1578 | else |
1579 | /* | |
1580 | * The chip needs a reset to properly wake up from | |
1581 | * full sleep | |
1582 | */ | |
1583 | reset_channel = ah->chip_fullsleep; | |
daa1b6ee | 1584 | } |
64839170 | 1585 | |
e7824a50 LR |
1586 | /* |
1587 | * We just prepare to enable PS. We have to wait until our AP has | |
1588 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1589 | * those ACKs and end up retransmitting the same null data frames. | |
1590 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1591 | */ | |
3cbb5dd7 | 1592 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1593 | unsigned long flags; |
1594 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1595 | if (conf->flags & IEEE80211_CONF_PS) |
1596 | ath9k_enable_ps(sc); | |
845d708e SB |
1597 | else |
1598 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1599 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1600 | } |
1601 | ||
199afd9d S |
1602 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1603 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
d2182b69 | 1604 | ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); |
5f841b41 RM |
1605 | sc->sc_ah->is_monitoring = true; |
1606 | } else { | |
d2182b69 | 1607 | ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); |
5f841b41 | 1608 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1609 | } |
1610 | } | |
1611 | ||
75600abf | 1612 | if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { |
99405f93 | 1613 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1614 | int pos = curchan->hw_value; |
3430098a FF |
1615 | int old_pos = -1; |
1616 | unsigned long flags; | |
1617 | ||
1618 | if (ah->curchan) | |
1619 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1620 | |
5ee08656 FF |
1621 | if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
1622 | sc->sc_flags |= SC_OP_OFFCHANNEL; | |
1623 | else | |
1624 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | |
0e2dedf9 | 1625 | |
d2182b69 | 1626 | ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", |
8c79a610 | 1627 | curchan->center_freq, conf->channel_type); |
f078f209 | 1628 | |
3430098a FF |
1629 | /* update survey stats for the old channel before switching */ |
1630 | spin_lock_irqsave(&common->cc_lock, flags); | |
1631 | ath_update_survey_stats(sc); | |
1632 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1633 | ||
e338a85e RM |
1634 | /* |
1635 | * Preserve the current channel values, before updating | |
1636 | * the same channel | |
1637 | */ | |
1a19f77f RM |
1638 | if (ah->curchan && (old_pos == pos)) |
1639 | ath9k_hw_getnf(ah, ah->curchan); | |
e338a85e RM |
1640 | |
1641 | ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], | |
1642 | curchan, conf->channel_type); | |
1643 | ||
3430098a FF |
1644 | /* |
1645 | * If the operating channel changes, change the survey in-use flags | |
1646 | * along with it. | |
1647 | * Reset the survey data for the new channel, unless we're switching | |
1648 | * back to the operating channel from an off-channel operation. | |
1649 | */ | |
1650 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1651 | sc->cur_survey != &sc->survey[pos]) { | |
1652 | ||
1653 | if (sc->cur_survey) | |
1654 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1655 | ||
1656 | sc->cur_survey = &sc->survey[pos]; | |
1657 | ||
1658 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1659 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1660 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1661 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1662 | } | |
1663 | ||
0e2dedf9 | 1664 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
3800276a | 1665 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1666 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1667 | return -EINVAL; |
1668 | } | |
3430098a FF |
1669 | |
1670 | /* | |
1671 | * The most recent snapshot of channel->noisefloor for the old | |
1672 | * channel is only available after the hardware reset. Copy it to | |
1673 | * the survey stats now. | |
1674 | */ | |
1675 | if (old_pos >= 0) | |
1676 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1677 | } |
f078f209 | 1678 | |
c9f6a656 | 1679 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
d2182b69 | 1680 | ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); |
17d7904d | 1681 | sc->config.txpowlimit = 2 * conf->power_level; |
5048e8c3 RM |
1682 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1683 | sc->config.txpowlimit, &sc->curtxpow); | |
64839170 LR |
1684 | } |
1685 | ||
aa33de09 | 1686 | mutex_unlock(&sc->mutex); |
c0c11741 | 1687 | ath9k_ps_restore(sc); |
141b38b6 | 1688 | |
f078f209 LR |
1689 | return 0; |
1690 | } | |
1691 | ||
8feceb67 VT |
1692 | #define SUPPORTED_FILTERS \ |
1693 | (FIF_PROMISC_IN_BSS | \ | |
1694 | FIF_ALLMULTI | \ | |
1695 | FIF_CONTROL | \ | |
af6a3fc7 | 1696 | FIF_PSPOLL | \ |
8feceb67 VT |
1697 | FIF_OTHER_BSS | \ |
1698 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1699 | FIF_PROBE_REQ | \ |
8feceb67 | 1700 | FIF_FCSFAIL) |
c83be688 | 1701 | |
8feceb67 VT |
1702 | /* FIXME: sc->sc_full_reset ? */ |
1703 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1704 | unsigned int changed_flags, | |
1705 | unsigned int *total_flags, | |
3ac64bee | 1706 | u64 multicast) |
8feceb67 | 1707 | { |
9ac58615 | 1708 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1709 | u32 rfilt; |
f078f209 | 1710 | |
8feceb67 VT |
1711 | changed_flags &= SUPPORTED_FILTERS; |
1712 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1713 | |
b77f483f | 1714 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1715 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1716 | rfilt = ath_calcrxfilter(sc); |
1717 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1718 | ath9k_ps_restore(sc); |
f078f209 | 1719 | |
d2182b69 JP |
1720 | ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", |
1721 | rfilt); | |
8feceb67 | 1722 | } |
f078f209 | 1723 | |
4ca77860 JB |
1724 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1725 | struct ieee80211_vif *vif, | |
1726 | struct ieee80211_sta *sta) | |
8feceb67 | 1727 | { |
9ac58615 | 1728 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1729 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1730 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1731 | struct ieee80211_key_conf ps_key = { }; | |
f078f209 | 1732 | |
7e1e3864 | 1733 | ath_node_attach(sc, sta, vif); |
f59a59fe FF |
1734 | |
1735 | if (vif->type != NL80211_IFTYPE_AP && | |
1736 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1737 | return 0; | |
1738 | ||
93ae2dd2 | 1739 | an->ps_key = ath_key_config(common, vif, sta, &ps_key); |
4ca77860 JB |
1740 | |
1741 | return 0; | |
1742 | } | |
1743 | ||
93ae2dd2 FF |
1744 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1745 | struct ieee80211_vif *vif, | |
1746 | struct ieee80211_sta *sta) | |
1747 | { | |
1748 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1749 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1750 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1751 | ||
1752 | if (!an->ps_key) | |
1753 | return; | |
1754 | ||
1755 | ath_key_delete(common, &ps_key); | |
1756 | } | |
1757 | ||
4ca77860 JB |
1758 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1759 | struct ieee80211_vif *vif, | |
1760 | struct ieee80211_sta *sta) | |
1761 | { | |
9ac58615 | 1762 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1763 | |
93ae2dd2 | 1764 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1765 | ath_node_detach(sc, sta); |
1766 | ||
1767 | return 0; | |
f078f209 LR |
1768 | } |
1769 | ||
5519541d FF |
1770 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1771 | struct ieee80211_vif *vif, | |
1772 | enum sta_notify_cmd cmd, | |
1773 | struct ieee80211_sta *sta) | |
1774 | { | |
1775 | struct ath_softc *sc = hw->priv; | |
1776 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1777 | ||
3d4e20f2 | 1778 | if (!sta->ht_cap.ht_supported) |
b25bfda3 MSS |
1779 | return; |
1780 | ||
5519541d FF |
1781 | switch (cmd) { |
1782 | case STA_NOTIFY_SLEEP: | |
1783 | an->sleeping = true; | |
042ec453 | 1784 | ath_tx_aggr_sleep(sta, sc, an); |
5519541d FF |
1785 | break; |
1786 | case STA_NOTIFY_AWAKE: | |
1787 | an->sleeping = false; | |
1788 | ath_tx_aggr_wakeup(sc, an); | |
1789 | break; | |
1790 | } | |
1791 | } | |
1792 | ||
8a3a3c85 EP |
1793 | static int ath9k_conf_tx(struct ieee80211_hw *hw, |
1794 | struct ieee80211_vif *vif, u16 queue, | |
8feceb67 | 1795 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1796 | { |
9ac58615 | 1797 | struct ath_softc *sc = hw->priv; |
c46917bb | 1798 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1799 | struct ath_txq *txq; |
8feceb67 | 1800 | struct ath9k_tx_queue_info qi; |
066dae93 | 1801 | int ret = 0; |
f078f209 | 1802 | |
8feceb67 VT |
1803 | if (queue >= WME_NUM_AC) |
1804 | return 0; | |
f078f209 | 1805 | |
066dae93 FF |
1806 | txq = sc->tx.txq_map[queue]; |
1807 | ||
96f372c9 | 1808 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1809 | mutex_lock(&sc->mutex); |
1810 | ||
1ffb0610 S |
1811 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1812 | ||
8feceb67 VT |
1813 | qi.tqi_aifs = params->aifs; |
1814 | qi.tqi_cwmin = params->cw_min; | |
1815 | qi.tqi_cwmax = params->cw_max; | |
1816 | qi.tqi_burstTime = params->txop; | |
f078f209 | 1817 | |
d2182b69 | 1818 | ath_dbg(common, CONFIG, |
226afe68 JP |
1819 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1820 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1821 | params->cw_max, params->txop); | |
f078f209 | 1822 | |
066dae93 | 1823 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1824 | if (ret) |
3800276a | 1825 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1826 | |
94db2936 | 1827 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
066dae93 | 1828 | if (queue == WME_AC_BE && !ret) |
94db2936 VN |
1829 | ath_beaconq_config(sc); |
1830 | ||
141b38b6 | 1831 | mutex_unlock(&sc->mutex); |
96f372c9 | 1832 | ath9k_ps_restore(sc); |
141b38b6 | 1833 | |
8feceb67 VT |
1834 | return ret; |
1835 | } | |
f078f209 | 1836 | |
8feceb67 VT |
1837 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1838 | enum set_key_cmd cmd, | |
dc822b5d JB |
1839 | struct ieee80211_vif *vif, |
1840 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1841 | struct ieee80211_key_conf *key) |
1842 | { | |
9ac58615 | 1843 | struct ath_softc *sc = hw->priv; |
c46917bb | 1844 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1845 | int ret = 0; |
f078f209 | 1846 | |
3e6109c5 | 1847 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1848 | return -ENOSPC; |
1849 | ||
5bd5e9a6 CYY |
1850 | if ((vif->type == NL80211_IFTYPE_ADHOC || |
1851 | vif->type == NL80211_IFTYPE_MESH_POINT) && | |
cfdc9a8b JM |
1852 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || |
1853 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1854 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1855 | /* | |
1856 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1857 | * could be optimized in the future to use a modified key cache | |
1858 | * design to support per-STA RX GTK, but until that gets | |
1859 | * implemented, use of software crypto for group addressed | |
1860 | * frames is a acceptable to allow RSN IBSS to be used. | |
1861 | */ | |
1862 | return -EOPNOTSUPP; | |
1863 | } | |
1864 | ||
141b38b6 | 1865 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1866 | ath9k_ps_wakeup(sc); |
d2182b69 | 1867 | ath_dbg(common, CONFIG, "Set HW Key\n"); |
f078f209 | 1868 | |
8feceb67 VT |
1869 | switch (cmd) { |
1870 | case SET_KEY: | |
93ae2dd2 FF |
1871 | if (sta) |
1872 | ath9k_del_ps_key(sc, vif, sta); | |
1873 | ||
040e539e | 1874 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1875 | if (ret >= 0) { |
1876 | key->hw_key_idx = ret; | |
8feceb67 VT |
1877 | /* push IV and Michael MIC generation to stack */ |
1878 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1879 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1880 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1881 | if (sc->sc_ah->sw_mgmt_crypto && |
1882 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1883 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1884 | ret = 0; |
8feceb67 VT |
1885 | } |
1886 | break; | |
1887 | case DISABLE_KEY: | |
040e539e | 1888 | ath_key_delete(common, key); |
8feceb67 VT |
1889 | break; |
1890 | default: | |
1891 | ret = -EINVAL; | |
1892 | } | |
f078f209 | 1893 | |
3cbb5dd7 | 1894 | ath9k_ps_restore(sc); |
141b38b6 S |
1895 | mutex_unlock(&sc->mutex); |
1896 | ||
8feceb67 VT |
1897 | return ret; |
1898 | } | |
4f5ef75b RM |
1899 | static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
1900 | { | |
1901 | struct ath_softc *sc = data; | |
1902 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1903 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
1904 | struct ath_vif *avp = (void *)vif->drv_priv; | |
1905 | ||
2e5ef459 RM |
1906 | /* |
1907 | * Skip iteration if primary station vif's bss info | |
1908 | * was not changed | |
1909 | */ | |
1910 | if (sc->sc_flags & SC_OP_PRIM_STA_VIF) | |
1911 | return; | |
1912 | ||
1913 | if (bss_conf->assoc) { | |
1914 | sc->sc_flags |= SC_OP_PRIM_STA_VIF; | |
1915 | avp->primary_sta_vif = true; | |
4f5ef75b RM |
1916 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1917 | common->curaid = bss_conf->aid; | |
1918 | ath9k_hw_write_associd(sc->sc_ah); | |
d2182b69 JP |
1919 | ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n", |
1920 | bss_conf->aid, common->curbssid); | |
2e5ef459 RM |
1921 | ath_beacon_config(sc, vif); |
1922 | /* | |
1923 | * Request a re-configuration of Beacon related timers | |
1924 | * on the receipt of the first Beacon frame (i.e., | |
1925 | * after time sync with the AP). | |
1926 | */ | |
1927 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
1928 | /* Reset rssi stats */ | |
1929 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; | |
1930 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
99e4d43a | 1931 | |
01e18918 RM |
1932 | ath_start_rx_poll(sc, 3); |
1933 | ||
05c0be2f MSS |
1934 | if (!common->disable_ani) { |
1935 | sc->sc_flags |= SC_OP_ANI_RUN; | |
1936 | ath_start_ani(common); | |
1937 | } | |
1938 | ||
4f5ef75b RM |
1939 | } |
1940 | } | |
1941 | ||
1942 | static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif) | |
1943 | { | |
1944 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1945 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
1946 | struct ath_vif *avp = (void *)vif->drv_priv; | |
1947 | ||
2e5ef459 RM |
1948 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
1949 | return; | |
1950 | ||
4f5ef75b RM |
1951 | /* Reconfigure bss info */ |
1952 | if (avp->primary_sta_vif && !bss_conf->assoc) { | |
d2182b69 | 1953 | ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n", |
99e4d43a RM |
1954 | common->curaid, common->curbssid); |
1955 | sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS); | |
4f5ef75b RM |
1956 | avp->primary_sta_vif = false; |
1957 | memset(common->curbssid, 0, ETH_ALEN); | |
1958 | common->curaid = 0; | |
1959 | } | |
1960 | ||
1961 | ieee80211_iterate_active_interfaces_atomic( | |
1962 | sc->hw, ath9k_bss_iter, sc); | |
1963 | ||
1964 | /* | |
1965 | * None of station vifs are associated. | |
1966 | * Clear bssid & aid | |
1967 | */ | |
2e5ef459 | 1968 | if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) { |
4f5ef75b | 1969 | ath9k_hw_write_associd(sc->sc_ah); |
99e4d43a RM |
1970 | /* Stop ANI */ |
1971 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
1972 | del_timer_sync(&common->ani.timer); | |
01e18918 | 1973 | del_timer_sync(&sc->rx_poll_timer); |
d2c71c20 | 1974 | memset(&sc->caldata, 0, sizeof(sc->caldata)); |
99e4d43a | 1975 | } |
4f5ef75b | 1976 | } |
f078f209 | 1977 | |
8feceb67 VT |
1978 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1979 | struct ieee80211_vif *vif, | |
1980 | struct ieee80211_bss_conf *bss_conf, | |
1981 | u32 changed) | |
1982 | { | |
9ac58615 | 1983 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 1984 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1985 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1986 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1987 | int slottime; |
f078f209 | 1988 | |
96f372c9 | 1989 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1990 | mutex_lock(&sc->mutex); |
1991 | ||
9f61903c | 1992 | if (changed & BSS_CHANGED_ASSOC) { |
4f5ef75b | 1993 | ath9k_config_bss(sc, vif); |
2d0ddec5 | 1994 | |
d2182b69 | 1995 | ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n", |
226afe68 | 1996 | common->curbssid, common->curaid); |
c6089ccc | 1997 | } |
2d0ddec5 | 1998 | |
2e5ef459 RM |
1999 | if (changed & BSS_CHANGED_IBSS) { |
2000 | /* There can be only one vif available */ | |
2001 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
2002 | common->curaid = bss_conf->aid; | |
2003 | ath9k_hw_write_associd(sc->sc_ah); | |
2004 | ||
2005 | if (bss_conf->ibss_joined) { | |
2006 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
05c0be2f MSS |
2007 | |
2008 | if (!common->disable_ani) { | |
2009 | sc->sc_flags |= SC_OP_ANI_RUN; | |
2010 | ath_start_ani(common); | |
2011 | } | |
2012 | ||
2e5ef459 RM |
2013 | } else { |
2014 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
2015 | del_timer_sync(&common->ani.timer); | |
01e18918 | 2016 | del_timer_sync(&sc->rx_poll_timer); |
2e5ef459 RM |
2017 | } |
2018 | } | |
2019 | ||
ed2578cd RM |
2020 | /* |
2021 | * In case of AP mode, the HW TSF has to be reset | |
2022 | * when the beacon interval changes. | |
2023 | */ | |
2024 | if ((changed & BSS_CHANGED_BEACON_INT) && | |
2025 | (vif->type == NL80211_IFTYPE_AP)) | |
2026 | sc->sc_flags |= SC_OP_TSF_RESET; | |
2027 | ||
2028 | /* Configure beaconing (AP, IBSS, MESH) */ | |
2029 | if (ath9k_uses_beacons(vif->type) && | |
2030 | ((changed & BSS_CHANGED_BEACON) || | |
2031 | (changed & BSS_CHANGED_BEACON_ENABLED) || | |
2032 | (changed & BSS_CHANGED_BEACON_INT))) { | |
014cf3bb | 2033 | ath9k_set_beaconing_status(sc, false); |
ed2578cd RM |
2034 | if (bss_conf->enable_beacon) |
2035 | ath_beacon_alloc(sc, vif); | |
2036 | else | |
2037 | avp->is_bslot_active = false; | |
2038 | ath_beacon_config(sc, vif); | |
014cf3bb | 2039 | ath9k_set_beaconing_status(sc, true); |
0005baf4 FF |
2040 | } |
2041 | ||
2042 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
2043 | if (bss_conf->use_short_slot) | |
2044 | slottime = 9; | |
2045 | else | |
2046 | slottime = 20; | |
2047 | if (vif->type == NL80211_IFTYPE_AP) { | |
2048 | /* | |
2049 | * Defer update, so that connected stations can adjust | |
2050 | * their settings at the same time. | |
2051 | * See beacon.c for more details | |
2052 | */ | |
2053 | sc->beacon.slottime = slottime; | |
2054 | sc->beacon.updateslot = UPDATE; | |
2055 | } else { | |
2056 | ah->slottime = slottime; | |
2057 | ath9k_hw_init_global_settings(ah); | |
2058 | } | |
2d0ddec5 JB |
2059 | } |
2060 | ||
141b38b6 | 2061 | mutex_unlock(&sc->mutex); |
96f372c9 | 2062 | ath9k_ps_restore(sc); |
8feceb67 | 2063 | } |
f078f209 | 2064 | |
37a41b4a | 2065 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 2066 | { |
9ac58615 | 2067 | struct ath_softc *sc = hw->priv; |
8feceb67 | 2068 | u64 tsf; |
f078f209 | 2069 | |
141b38b6 | 2070 | mutex_lock(&sc->mutex); |
9abbfb27 | 2071 | ath9k_ps_wakeup(sc); |
141b38b6 | 2072 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 2073 | ath9k_ps_restore(sc); |
141b38b6 | 2074 | mutex_unlock(&sc->mutex); |
f078f209 | 2075 | |
8feceb67 VT |
2076 | return tsf; |
2077 | } | |
f078f209 | 2078 | |
37a41b4a EP |
2079 | static void ath9k_set_tsf(struct ieee80211_hw *hw, |
2080 | struct ieee80211_vif *vif, | |
2081 | u64 tsf) | |
3b5d665b | 2082 | { |
9ac58615 | 2083 | struct ath_softc *sc = hw->priv; |
3b5d665b | 2084 | |
141b38b6 | 2085 | mutex_lock(&sc->mutex); |
9abbfb27 | 2086 | ath9k_ps_wakeup(sc); |
141b38b6 | 2087 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 2088 | ath9k_ps_restore(sc); |
141b38b6 | 2089 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
2090 | } |
2091 | ||
37a41b4a | 2092 | static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 2093 | { |
9ac58615 | 2094 | struct ath_softc *sc = hw->priv; |
c83be688 | 2095 | |
141b38b6 | 2096 | mutex_lock(&sc->mutex); |
21526d57 LR |
2097 | |
2098 | ath9k_ps_wakeup(sc); | |
141b38b6 | 2099 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
2100 | ath9k_ps_restore(sc); |
2101 | ||
141b38b6 | 2102 | mutex_unlock(&sc->mutex); |
8feceb67 | 2103 | } |
f078f209 | 2104 | |
8feceb67 | 2105 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 2106 | struct ieee80211_vif *vif, |
141b38b6 S |
2107 | enum ieee80211_ampdu_mlme_action action, |
2108 | struct ieee80211_sta *sta, | |
0b01f030 | 2109 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 2110 | { |
9ac58615 | 2111 | struct ath_softc *sc = hw->priv; |
8feceb67 | 2112 | int ret = 0; |
f078f209 | 2113 | |
85ad181e JB |
2114 | local_bh_disable(); |
2115 | ||
8feceb67 VT |
2116 | switch (action) { |
2117 | case IEEE80211_AMPDU_RX_START: | |
8feceb67 VT |
2118 | break; |
2119 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2120 | break; |
2121 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 2122 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
2123 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
2124 | if (!ret) | |
2125 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 2126 | ath9k_ps_restore(sc); |
8feceb67 VT |
2127 | break; |
2128 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 2129 | ath9k_ps_wakeup(sc); |
f83da965 | 2130 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 2131 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 2132 | ath9k_ps_restore(sc); |
8feceb67 | 2133 | break; |
b1720231 | 2134 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 2135 | ath9k_ps_wakeup(sc); |
8469cdef | 2136 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 2137 | ath9k_ps_restore(sc); |
8469cdef | 2138 | break; |
8feceb67 | 2139 | default: |
3800276a | 2140 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
2141 | } |
2142 | ||
85ad181e JB |
2143 | local_bh_enable(); |
2144 | ||
8feceb67 | 2145 | return ret; |
f078f209 LR |
2146 | } |
2147 | ||
62dad5b0 BP |
2148 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
2149 | struct survey_info *survey) | |
2150 | { | |
9ac58615 | 2151 | struct ath_softc *sc = hw->priv; |
3430098a | 2152 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 2153 | struct ieee80211_supported_band *sband; |
3430098a FF |
2154 | struct ieee80211_channel *chan; |
2155 | unsigned long flags; | |
2156 | int pos; | |
2157 | ||
2158 | spin_lock_irqsave(&common->cc_lock, flags); | |
2159 | if (idx == 0) | |
2160 | ath_update_survey_stats(sc); | |
39162dbe FF |
2161 | |
2162 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
2163 | if (sband && idx >= sband->n_channels) { | |
2164 | idx -= sband->n_channels; | |
2165 | sband = NULL; | |
2166 | } | |
62dad5b0 | 2167 | |
39162dbe FF |
2168 | if (!sband) |
2169 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 2170 | |
3430098a FF |
2171 | if (!sband || idx >= sband->n_channels) { |
2172 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2173 | return -ENOENT; | |
4f1a5a4b | 2174 | } |
62dad5b0 | 2175 | |
3430098a FF |
2176 | chan = &sband->channels[idx]; |
2177 | pos = chan->hw_value; | |
2178 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
2179 | survey->channel = chan; | |
2180 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2181 | ||
62dad5b0 BP |
2182 | return 0; |
2183 | } | |
2184 | ||
e239d859 FF |
2185 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2186 | { | |
9ac58615 | 2187 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
2188 | struct ath_hw *ah = sc->sc_ah; |
2189 | ||
2190 | mutex_lock(&sc->mutex); | |
2191 | ah->coverage_class = coverage_class; | |
8b2a3827 MSS |
2192 | |
2193 | ath9k_ps_wakeup(sc); | |
e239d859 | 2194 | ath9k_hw_init_global_settings(ah); |
8b2a3827 MSS |
2195 | ath9k_ps_restore(sc); |
2196 | ||
e239d859 FF |
2197 | mutex_unlock(&sc->mutex); |
2198 | } | |
2199 | ||
69081624 VT |
2200 | static void ath9k_flush(struct ieee80211_hw *hw, bool drop) |
2201 | { | |
69081624 | 2202 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
2203 | struct ath_hw *ah = sc->sc_ah; |
2204 | struct ath_common *common = ath9k_hw_common(ah); | |
86271e46 FF |
2205 | int timeout = 200; /* ms */ |
2206 | int i, j; | |
2f6fc351 | 2207 | bool drain_txq; |
69081624 VT |
2208 | |
2209 | mutex_lock(&sc->mutex); | |
69081624 VT |
2210 | cancel_delayed_work_sync(&sc->tx_complete_work); |
2211 | ||
6a6b3f3e | 2212 | if (ah->ah_flags & AH_UNPLUGGED) { |
d2182b69 | 2213 | ath_dbg(common, ANY, "Device has been unplugged!\n"); |
6a6b3f3e MSS |
2214 | mutex_unlock(&sc->mutex); |
2215 | return; | |
2216 | } | |
2217 | ||
99aa55b6 | 2218 | if (sc->sc_flags & SC_OP_INVALID) { |
d2182b69 | 2219 | ath_dbg(common, ANY, "Device not present\n"); |
99aa55b6 MSS |
2220 | mutex_unlock(&sc->mutex); |
2221 | return; | |
2222 | } | |
2223 | ||
86271e46 | 2224 | for (j = 0; j < timeout; j++) { |
108697c4 | 2225 | bool npend = false; |
86271e46 FF |
2226 | |
2227 | if (j) | |
2228 | usleep_range(1000, 2000); | |
69081624 | 2229 | |
86271e46 FF |
2230 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2231 | if (!ATH_TXQ_SETUP(sc, i)) | |
2232 | continue; | |
2233 | ||
108697c4 MSS |
2234 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); |
2235 | ||
2236 | if (npend) | |
2237 | break; | |
69081624 | 2238 | } |
86271e46 FF |
2239 | |
2240 | if (!npend) | |
9df0d6a2 | 2241 | break; |
69081624 VT |
2242 | } |
2243 | ||
9df0d6a2 FF |
2244 | if (drop) { |
2245 | ath9k_ps_wakeup(sc); | |
2246 | spin_lock_bh(&sc->sc_pcu_lock); | |
2247 | drain_txq = ath_drain_all_txq(sc, false); | |
2248 | spin_unlock_bh(&sc->sc_pcu_lock); | |
9adcf440 | 2249 | |
9df0d6a2 FF |
2250 | if (!drain_txq) |
2251 | ath_reset(sc, false); | |
9adcf440 | 2252 | |
9df0d6a2 FF |
2253 | ath9k_ps_restore(sc); |
2254 | ieee80211_wake_queues(hw); | |
2255 | } | |
d78f4b3e | 2256 | |
69081624 VT |
2257 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
2258 | mutex_unlock(&sc->mutex); | |
2259 | } | |
2260 | ||
15b91e83 VN |
2261 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
2262 | { | |
2263 | struct ath_softc *sc = hw->priv; | |
2264 | int i; | |
2265 | ||
2266 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
2267 | if (!ATH_TXQ_SETUP(sc, i)) | |
2268 | continue; | |
2269 | ||
2270 | if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) | |
2271 | return true; | |
2272 | } | |
2273 | return false; | |
2274 | } | |
2275 | ||
5595f119 | 2276 | static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
ba4903f9 FF |
2277 | { |
2278 | struct ath_softc *sc = hw->priv; | |
2279 | struct ath_hw *ah = sc->sc_ah; | |
2280 | struct ieee80211_vif *vif; | |
2281 | struct ath_vif *avp; | |
2282 | struct ath_buf *bf; | |
2283 | struct ath_tx_status ts; | |
4286df60 | 2284 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
ba4903f9 FF |
2285 | int status; |
2286 | ||
2287 | vif = sc->beacon.bslot[0]; | |
2288 | if (!vif) | |
2289 | return 0; | |
2290 | ||
2291 | avp = (void *)vif->drv_priv; | |
2292 | if (!avp->is_bslot_active) | |
2293 | return 0; | |
2294 | ||
4286df60 | 2295 | if (!sc->beacon.tx_processed && !edma) { |
ba4903f9 FF |
2296 | tasklet_disable(&sc->bcon_tasklet); |
2297 | ||
2298 | bf = avp->av_bcbuf; | |
2299 | if (!bf || !bf->bf_mpdu) | |
2300 | goto skip; | |
2301 | ||
2302 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
2303 | if (status == -EINPROGRESS) | |
2304 | goto skip; | |
2305 | ||
2306 | sc->beacon.tx_processed = true; | |
2307 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
2308 | ||
2309 | skip: | |
2310 | tasklet_enable(&sc->bcon_tasklet); | |
2311 | } | |
2312 | ||
2313 | return sc->beacon.tx_last; | |
2314 | } | |
2315 | ||
52c94f41 MSS |
2316 | static int ath9k_get_stats(struct ieee80211_hw *hw, |
2317 | struct ieee80211_low_level_stats *stats) | |
2318 | { | |
2319 | struct ath_softc *sc = hw->priv; | |
2320 | struct ath_hw *ah = sc->sc_ah; | |
2321 | struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; | |
2322 | ||
2323 | stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; | |
2324 | stats->dot11RTSFailureCount = mib_stats->rts_bad; | |
2325 | stats->dot11FCSErrorCount = mib_stats->fcs_bad; | |
2326 | stats->dot11RTSSuccessCount = mib_stats->rts_good; | |
2327 | return 0; | |
2328 | } | |
2329 | ||
43c35284 FF |
2330 | static u32 fill_chainmask(u32 cap, u32 new) |
2331 | { | |
2332 | u32 filled = 0; | |
2333 | int i; | |
2334 | ||
2335 | for (i = 0; cap && new; i++, cap >>= 1) { | |
2336 | if (!(cap & BIT(0))) | |
2337 | continue; | |
2338 | ||
2339 | if (new & BIT(0)) | |
2340 | filled |= BIT(i); | |
2341 | ||
2342 | new >>= 1; | |
2343 | } | |
2344 | ||
2345 | return filled; | |
2346 | } | |
2347 | ||
2348 | static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) | |
2349 | { | |
2350 | struct ath_softc *sc = hw->priv; | |
2351 | struct ath_hw *ah = sc->sc_ah; | |
2352 | ||
2353 | if (!rx_ant || !tx_ant) | |
2354 | return -EINVAL; | |
2355 | ||
2356 | sc->ant_rx = rx_ant; | |
2357 | sc->ant_tx = tx_ant; | |
2358 | ||
2359 | if (ah->caps.rx_chainmask == 1) | |
2360 | return 0; | |
2361 | ||
2362 | /* AR9100 runs into calibration issues if not all rx chains are enabled */ | |
2363 | if (AR_SREV_9100(ah)) | |
2364 | ah->rxchainmask = 0x7; | |
2365 | else | |
2366 | ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); | |
2367 | ||
2368 | ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); | |
2369 | ath9k_reload_chainmask_settings(sc); | |
2370 | ||
2371 | return 0; | |
2372 | } | |
2373 | ||
2374 | static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | |
2375 | { | |
2376 | struct ath_softc *sc = hw->priv; | |
2377 | ||
2378 | *tx_ant = sc->ant_tx; | |
2379 | *rx_ant = sc->ant_rx; | |
2380 | return 0; | |
2381 | } | |
2382 | ||
6baff7f9 | 2383 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2384 | .tx = ath9k_tx, |
2385 | .start = ath9k_start, | |
2386 | .stop = ath9k_stop, | |
2387 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2388 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2389 | .remove_interface = ath9k_remove_interface, |
2390 | .config = ath9k_config, | |
8feceb67 | 2391 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2392 | .sta_add = ath9k_sta_add, |
2393 | .sta_remove = ath9k_sta_remove, | |
5519541d | 2394 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2395 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2396 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2397 | .set_key = ath9k_set_key, |
8feceb67 | 2398 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2399 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2400 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2401 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2402 | .get_survey = ath9k_get_survey, |
3b319aae | 2403 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2404 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2405 | .flush = ath9k_flush, |
15b91e83 | 2406 | .tx_frames_pending = ath9k_tx_frames_pending, |
52c94f41 MSS |
2407 | .tx_last_beacon = ath9k_tx_last_beacon, |
2408 | .get_stats = ath9k_get_stats, | |
43c35284 FF |
2409 | .set_antenna = ath9k_set_antenna, |
2410 | .get_antenna = ath9k_get_antenna, | |
8feceb67 | 2411 | }; |