ath9k: update to DFS pattern detector interface
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
ff37e337
S
22static u8 parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
69081624
VT
65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68}
69
6d79cb4c 70static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
71{
72 unsigned long flags;
73 bool ret;
74
9ecdef4b
LR
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
78
79 return ret;
80}
81
a91d75ae
LR
82void ath9k_ps_wakeup(struct ath_softc *sc)
83{
898c914a 84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 85 unsigned long flags;
fbb078fc 86 enum ath9k_power_mode power_mode;
a91d75ae
LR
87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
fbb078fc 92 power_mode = sc->sc_ah->power_mode;
9ecdef4b 93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 94
898c914a
FF
95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
fbb078fc
FF
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 spin_unlock(&common->cc_lock);
105 }
898c914a 106
a91d75ae
LR
107 unlock:
108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
109}
110
111void ath9k_ps_restore(struct ath_softc *sc)
112{
898c914a 113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 114 enum ath9k_power_mode mode;
a91d75ae
LR
115 unsigned long flags;
116
117 spin_lock_irqsave(&sc->sc_pm_lock, flags);
118 if (--sc->ps_usecount != 0)
119 goto unlock;
120
c1afdaff
FF
121 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK)
122 goto unlock;
123
124 if (sc->ps_idle)
c6c539f0 125 mode = ATH9K_PM_FULL_SLEEP;
1dbfd9d4
VN
126 else if (sc->ps_enabled &&
127 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930 128 PS_WAIT_FOR_CAB |
c1afdaff 129 PS_WAIT_FOR_PSPOLL_DATA)))
c6c539f0
FF
130 mode = ATH9K_PM_NETWORK_SLEEP;
131 else
132 goto unlock;
133
134 spin_lock(&common->cc_lock);
135 ath_hw_cycle_counters_update(common);
136 spin_unlock(&common->cc_lock);
137
1a8f0d39 138 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR
139
140 unlock:
141 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
142}
143
05c0be2f 144void ath_start_ani(struct ath_common *common)
5ee08656
FF
145{
146 struct ath_hw *ah = common->ah;
147 unsigned long timestamp = jiffies_to_msecs(jiffies);
148 struct ath_softc *sc = (struct ath_softc *) common->priv;
149
150 if (!(sc->sc_flags & SC_OP_ANI_RUN))
151 return;
152
153 if (sc->sc_flags & SC_OP_OFFCHANNEL)
154 return;
155
156 common->ani.longcal_timer = timestamp;
157 common->ani.shortcal_timer = timestamp;
158 common->ani.checkani_timer = timestamp;
159
160 mod_timer(&common->ani.timer,
161 jiffies +
162 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
163}
164
3430098a
FF
165static void ath_update_survey_nf(struct ath_softc *sc, int channel)
166{
167 struct ath_hw *ah = sc->sc_ah;
168 struct ath9k_channel *chan = &ah->channels[channel];
169 struct survey_info *survey = &sc->survey[channel];
170
171 if (chan->noisefloor) {
172 survey->filled |= SURVEY_INFO_NOISE_DBM;
f749b946 173 survey->noise = ath9k_hw_getchan_noise(ah, chan);
3430098a
FF
174 }
175}
176
cb8d61de
FF
177/*
178 * Updates the survey statistics and returns the busy time since last
179 * update in %, if the measurement duration was long enough for the
180 * result to be useful, -1 otherwise.
181 */
182static int ath_update_survey_stats(struct ath_softc *sc)
3430098a
FF
183{
184 struct ath_hw *ah = sc->sc_ah;
185 struct ath_common *common = ath9k_hw_common(ah);
186 int pos = ah->curchan - &ah->channels[0];
187 struct survey_info *survey = &sc->survey[pos];
188 struct ath_cycle_counters *cc = &common->cc_survey;
189 unsigned int div = common->clockrate * 1000;
cb8d61de 190 int ret = 0;
3430098a 191
0845735e 192 if (!ah->curchan)
cb8d61de 193 return -1;
0845735e 194
898c914a
FF
195 if (ah->power_mode == ATH9K_PM_AWAKE)
196 ath_hw_cycle_counters_update(common);
3430098a
FF
197
198 if (cc->cycles > 0) {
199 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
200 SURVEY_INFO_CHANNEL_TIME_BUSY |
201 SURVEY_INFO_CHANNEL_TIME_RX |
202 SURVEY_INFO_CHANNEL_TIME_TX;
203 survey->channel_time += cc->cycles / div;
204 survey->channel_time_busy += cc->rx_busy / div;
205 survey->channel_time_rx += cc->rx_frame / div;
206 survey->channel_time_tx += cc->tx_frame / div;
207 }
cb8d61de
FF
208
209 if (cc->cycles < div)
210 return -1;
211
212 if (cc->cycles > 0)
213 ret = cc->rx_busy * 100 / cc->cycles;
214
3430098a
FF
215 memset(cc, 0, sizeof(*cc));
216
217 ath_update_survey_nf(sc, pos);
cb8d61de
FF
218
219 return ret;
3430098a
FF
220}
221
9adcf440 222static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 223{
5ee08656
FF
224 cancel_work_sync(&sc->paprd_work);
225 cancel_work_sync(&sc->hw_check_work);
226 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 227 cancel_delayed_work_sync(&sc->hw_pll_work);
9adcf440 228}
5ee08656 229
9adcf440
FF
230static void ath_cancel_work(struct ath_softc *sc)
231{
232 __ath_cancel_work(sc);
233 cancel_work_sync(&sc->hw_reset_work);
234}
3cbb5dd7 235
9adcf440
FF
236static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
237{
238 struct ath_hw *ah = sc->sc_ah;
239 struct ath_common *common = ath9k_hw_common(ah);
240 bool ret;
6a6733f2 241
9adcf440 242 ieee80211_stop_queues(sc->hw);
5e848f78 243
9adcf440
FF
244 sc->hw_busy_count = 0;
245 del_timer_sync(&common->ani.timer);
01e18918 246 del_timer_sync(&sc->rx_poll_timer);
ff37e337 247
9adcf440
FF
248 ath9k_debug_samp_bb_mac(sc);
249 ath9k_hw_disable_interrupts(ah);
8b3f4616 250
9adcf440 251 ret = ath_drain_all_txq(sc, retry_tx);
ff37e337 252
9adcf440
FF
253 if (!ath_stoprecv(sc))
254 ret = false;
c0d7c7af 255
9adcf440
FF
256 if (!flush) {
257 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
3483288c
FF
258 ath_rx_tasklet(sc, 1, true);
259 ath_rx_tasklet(sc, 1, false);
9adcf440
FF
260 } else {
261 ath_flushrecv(sc);
262 }
20bd2a09 263
9adcf440
FF
264 return ret;
265}
ff37e337 266
9adcf440
FF
267static bool ath_complete_reset(struct ath_softc *sc, bool start)
268{
269 struct ath_hw *ah = sc->sc_ah;
270 struct ath_common *common = ath9k_hw_common(ah);
c0d7c7af 271
c0d7c7af 272 if (ath_startrecv(sc) != 0) {
3800276a 273 ath_err(common, "Unable to restart recv logic\n");
9adcf440 274 return false;
c0d7c7af
LR
275 }
276
5048e8c3
RM
277 ath9k_cmn_update_txpow(ah, sc->curtxpow,
278 sc->config.txpowlimit, &sc->curtxpow);
72d874c6 279 ath9k_hw_set_interrupts(ah);
b037b693 280 ath9k_hw_enable_interrupts(ah);
3989279c 281
9adcf440 282 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
1186488b 283 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 284 ath_set_beacon(sc);
9adcf440 285
5ee08656 286 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
181fb18d 287 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
01e18918 288 ath_start_rx_poll(sc, 3);
05c0be2f
MSS
289 if (!common->disable_ani)
290 ath_start_ani(common);
5ee08656
FF
291 }
292
162d12de 293 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) {
43c35284
FF
294 struct ath_hw_antcomb_conf div_ant_conf;
295 u8 lna_conf;
296
297 ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
298
299 if (sc->ant_rx == 1)
300 lna_conf = ATH_ANT_DIV_COMB_LNA1;
301 else
302 lna_conf = ATH_ANT_DIV_COMB_LNA2;
303 div_ant_conf.main_lna_conf = lna_conf;
304 div_ant_conf.alt_lna_conf = lna_conf;
305
306 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
307 }
308
9adcf440
FF
309 ieee80211_wake_queues(sc->hw);
310
311 return true;
312}
313
314static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
315 bool retry_tx)
316{
317 struct ath_hw *ah = sc->sc_ah;
318 struct ath_common *common = ath9k_hw_common(ah);
319 struct ath9k_hw_cal_data *caldata = NULL;
320 bool fastcc = true;
321 bool flush = false;
322 int r;
323
324 __ath_cancel_work(sc);
325
326 spin_lock_bh(&sc->sc_pcu_lock);
92460412 327
9adcf440
FF
328 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) {
329 fastcc = false;
330 caldata = &sc->caldata;
331 }
332
333 if (!hchan) {
334 fastcc = false;
335 flush = true;
336 hchan = ah->curchan;
337 }
338
9adcf440
FF
339 if (!ath_prepare_reset(sc, retry_tx, flush))
340 fastcc = false;
341
d2182b69 342 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 343 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF
344
345 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
346 if (r) {
347 ath_err(common,
348 "Unable to reset channel, reset status %d\n", r);
349 goto out;
350 }
351
352 if (!ath_complete_reset(sc, true))
353 r = -EIO;
354
355out:
6a6733f2 356 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440
FF
357 return r;
358}
359
360
361/*
362 * Set/change channels. If the channel is really being changed, it's done
363 * by reseting the chip. To accomplish this we must first cleanup any pending
364 * DMA, then restart stuff.
365*/
366static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
367 struct ath9k_channel *hchan)
368{
369 int r;
370
371 if (sc->sc_flags & SC_OP_INVALID)
372 return -EIO;
373
9adcf440 374 r = ath_reset_internal(sc, hchan, false);
6a6733f2 375
3989279c 376 return r;
ff37e337
S
377}
378
9f42c2b6
FF
379static void ath_paprd_activate(struct ath_softc *sc)
380{
381 struct ath_hw *ah = sc->sc_ah;
20bd2a09 382 struct ath9k_hw_cal_data *caldata = ah->caldata;
9f42c2b6
FF
383 int chain;
384
20bd2a09 385 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
386 return;
387
388 ath9k_ps_wakeup(sc);
ddfef792 389 ar9003_paprd_enable(ah, false);
9f42c2b6 390 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
82b2d334 391 if (!(ah->txchainmask & BIT(chain)))
9f42c2b6
FF
392 continue;
393
20bd2a09 394 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
395 }
396
397 ar9003_paprd_enable(ah, true);
398 ath9k_ps_restore(sc);
399}
400
7607cbe2
FF
401static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
402{
403 struct ieee80211_hw *hw = sc->hw;
404 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
47960077
MSS
405 struct ath_hw *ah = sc->sc_ah;
406 struct ath_common *common = ath9k_hw_common(ah);
7607cbe2
FF
407 struct ath_tx_control txctl;
408 int time_left;
409
410 memset(&txctl, 0, sizeof(txctl));
411 txctl.txq = sc->tx.txq_map[WME_AC_BE];
412
413 memset(tx_info, 0, sizeof(*tx_info));
414 tx_info->band = hw->conf.channel->band;
415 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
416 tx_info->control.rates[0].idx = 0;
417 tx_info->control.rates[0].count = 1;
418 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
419 tx_info->control.rates[1].idx = -1;
420
421 init_completion(&sc->paprd_complete);
7607cbe2 422 txctl.paprd = BIT(chain);
47960077
MSS
423
424 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 425 ath_dbg(common, CALIBRATE, "PAPRD TX failed\n");
47960077 426 dev_kfree_skb_any(skb);
7607cbe2 427 return false;
47960077 428 }
7607cbe2
FF
429
430 time_left = wait_for_completion_timeout(&sc->paprd_complete,
431 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
7607cbe2
FF
432
433 if (!time_left)
d2182b69 434 ath_dbg(common, CALIBRATE,
7607cbe2
FF
435 "Timeout waiting for paprd training on TX chain %d\n",
436 chain);
437
438 return !!time_left;
439}
440
9f42c2b6
FF
441void ath_paprd_calibrate(struct work_struct *work)
442{
443 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
444 struct ieee80211_hw *hw = sc->hw;
445 struct ath_hw *ah = sc->sc_ah;
446 struct ieee80211_hdr *hdr;
447 struct sk_buff *skb = NULL;
20bd2a09 448 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 449 struct ath_common *common = ath9k_hw_common(ah);
066dae93 450 int ftype;
9f42c2b6
FF
451 int chain_ok = 0;
452 int chain;
453 int len = 1800;
9f42c2b6 454
20bd2a09
FF
455 if (!caldata)
456 return;
457
b942471b
MSS
458 ath9k_ps_wakeup(sc);
459
1bf38661 460 if (ar9003_paprd_init_table(ah) < 0)
b942471b 461 goto fail_paprd;
1bf38661 462
9f42c2b6
FF
463 skb = alloc_skb(len, GFP_KERNEL);
464 if (!skb)
b942471b 465 goto fail_paprd;
9f42c2b6 466
9f42c2b6
FF
467 skb_put(skb, len);
468 memset(skb->data, 0, len);
469 hdr = (struct ieee80211_hdr *)skb->data;
470 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
471 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 472 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
473 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
474 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
475 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
476
9f42c2b6 477 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
82b2d334 478 if (!(ah->txchainmask & BIT(chain)))
9f42c2b6
FF
479 continue;
480
481 chain_ok = 0;
9f42c2b6 482
d2182b69
JP
483 ath_dbg(common, CALIBRATE,
484 "Sending PAPRD frame for thermal measurement on chain %d\n",
485 chain);
7607cbe2
FF
486 if (!ath_paprd_send_frame(sc, skb, chain))
487 goto fail_paprd;
9f42c2b6 488
9f42c2b6 489 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 490
d2182b69 491 ath_dbg(common, CALIBRATE,
7607cbe2
FF
492 "Sending PAPRD training frame on chain %d\n", chain);
493 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 494 goto fail_paprd;
9f42c2b6 495
d4bb17c4 496 if (!ar9003_paprd_is_done(ah)) {
d2182b69 497 ath_dbg(common, CALIBRATE,
d4bb17c4 498 "PAPRD not yet done on chain %d\n", chain);
9f42c2b6 499 break;
d4bb17c4 500 }
9f42c2b6 501
d4bb17c4 502 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
d2182b69 503 ath_dbg(common, CALIBRATE,
d4bb17c4
MSS
504 "PAPRD create curve failed on chain %d\n",
505 chain);
9f42c2b6 506 break;
d4bb17c4 507 }
9f42c2b6
FF
508
509 chain_ok = 1;
510 }
511 kfree_skb(skb);
512
513 if (chain_ok) {
20bd2a09 514 caldata->paprd_done = true;
9f42c2b6
FF
515 ath_paprd_activate(sc);
516 }
517
ca369eb4 518fail_paprd:
9f42c2b6
FF
519 ath9k_ps_restore(sc);
520}
521
ff37e337
S
522/*
523 * This routine performs the periodic noise floor calibration function
524 * that is used to adjust and optimize the chip performance. This
525 * takes environmental changes (location, temperature) into account.
526 * When the task is complete, it reschedules itself depending on the
527 * appropriate interval that was calculated.
528 */
55624204 529void ath_ani_calibrate(unsigned long data)
ff37e337 530{
20977d3e
S
531 struct ath_softc *sc = (struct ath_softc *)data;
532 struct ath_hw *ah = sc->sc_ah;
c46917bb 533 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
534 bool longcal = false;
535 bool shortcal = false;
536 bool aniflag = false;
537 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 538 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 539 unsigned long flags;
6044474e
FF
540
541 if (ah->caldata && ah->caldata->nfcal_interference)
542 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
543 else
544 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 545
20977d3e
S
546 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
547 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 548
1ffc1c61
JM
549 /* Only calibrate if awake */
550 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
551 goto set_timer;
552
553 ath9k_ps_wakeup(sc);
554
ff37e337 555 /* Long calibration runs independently of short calibration. */
6044474e 556 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 557 longcal = true;
3d536acf 558 common->ani.longcal_timer = timestamp;
ff37e337
S
559 }
560
17d7904d 561 /* Short calibration applies only while caldone is false */
3d536acf
LR
562 if (!common->ani.caldone) {
563 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 564 shortcal = true;
3d536acf
LR
565 common->ani.shortcal_timer = timestamp;
566 common->ani.resetcal_timer = timestamp;
ff37e337
S
567 }
568 } else {
3d536acf 569 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 570 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
571 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
572 if (common->ani.caldone)
573 common->ani.resetcal_timer = timestamp;
ff37e337
S
574 }
575 }
576
577 /* Verify whether we must check ANI */
4279425c
NM
578 if (sc->sc_ah->config.enable_ani
579 && (timestamp - common->ani.checkani_timer) >=
580 ah->config.ani_poll_interval) {
ff37e337 581 aniflag = true;
3d536acf 582 common->ani.checkani_timer = timestamp;
ff37e337
S
583 }
584
e62ddec9
MSS
585 /* Call ANI routine if necessary */
586 if (aniflag) {
587 spin_lock_irqsave(&common->cc_lock, flags);
588 ath9k_hw_ani_monitor(ah, ah->curchan);
589 ath_update_survey_stats(sc);
590 spin_unlock_irqrestore(&common->cc_lock, flags);
591 }
ff37e337 592
e62ddec9
MSS
593 /* Perform calibration if necessary */
594 if (longcal || shortcal) {
595 common->ani.caldone =
596 ath9k_hw_calibrate(ah, ah->curchan,
82b2d334 597 ah->rxchainmask, longcal);
ff37e337
S
598 }
599
d2182b69
JP
600 ath_dbg(common, ANI,
601 "Calibration @%lu finished: %s %s %s, caldone: %s\n",
602 jiffies,
86951359
NM
603 longcal ? "long" : "", shortcal ? "short" : "",
604 aniflag ? "ani" : "", common->ani.caldone ? "true" : "false");
605
1ffc1c61
JM
606 ath9k_ps_restore(sc);
607
20977d3e 608set_timer:
ff37e337
S
609 /*
610 * Set timer interval based on previous results.
611 * The interval must be the shortest necessary to satisfy ANI,
612 * short calibration and long calibration.
613 */
cf3af748 614 ath9k_debug_samp_bb_mac(sc);
aac9207e 615 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 616 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
617 cal_interval = min(cal_interval,
618 (u32)ah->config.ani_poll_interval);
3d536acf 619 if (!common->ani.caldone)
20977d3e 620 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 621
3d536acf 622 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
623 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
624 if (!ah->caldata->paprd_done)
9f42c2b6 625 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 626 else if (!ah->paprd_table_write_done)
9f42c2b6
FF
627 ath_paprd_activate(sc);
628 }
ff37e337
S
629}
630
7e1e3864
BG
631static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
632 struct ieee80211_vif *vif)
ff37e337
S
633{
634 struct ath_node *an;
ff37e337
S
635 an = (struct ath_node *)sta->drv_priv;
636
7f010c93
BG
637#ifdef CONFIG_ATH9K_DEBUGFS
638 spin_lock(&sc->nodes_lock);
639 list_add(&an->list, &sc->nodes);
640 spin_unlock(&sc->nodes_lock);
156369fa 641#endif
7f010c93 642 an->sta = sta;
7e1e3864 643 an->vif = vif;
3d4e20f2
SM
644
645 if (sta->ht_cap.ht_supported) {
ff37e337 646 ath_tx_node_init(sc, an);
9e98ac65 647 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
648 sta->ht_cap.ampdu_factor);
649 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
650 }
ff37e337
S
651}
652
653static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
654{
655 struct ath_node *an = (struct ath_node *)sta->drv_priv;
656
7f010c93
BG
657#ifdef CONFIG_ATH9K_DEBUGFS
658 spin_lock(&sc->nodes_lock);
659 list_del(&an->list);
660 spin_unlock(&sc->nodes_lock);
661 an->sta = NULL;
662#endif
663
3d4e20f2 664 if (sta->ht_cap.ht_supported)
ff37e337
S
665 ath_tx_node_cleanup(sc, an);
666}
667
9eab61c2 668
55624204 669void ath9k_tasklet(unsigned long data)
ff37e337
S
670{
671 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 672 struct ath_hw *ah = sc->sc_ah;
c46917bb 673 struct ath_common *common = ath9k_hw_common(ah);
af03abec 674
17d7904d 675 u32 status = sc->intrstatus;
b5c80475 676 u32 rxmask;
ff37e337 677
e3927007
FF
678 ath9k_ps_wakeup(sc);
679 spin_lock(&sc->sc_pcu_lock);
680
a4d86d95
RM
681 if ((status & ATH9K_INT_FATAL) ||
682 (status & ATH9K_INT_BB_WATCHDOG)) {
030d6294
FF
683#ifdef CONFIG_ATH9K_DEBUGFS
684 enum ath_reset_type type;
685
686 if (status & ATH9K_INT_FATAL)
687 type = RESET_TYPE_FATAL_INT;
688 else
689 type = RESET_TYPE_BB_WATCHDOG;
690
691 RESET_STAT_INC(sc, type);
692#endif
236de514 693 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e3927007 694 goto out;
063d8be3 695 }
ff37e337 696
8b3f4616
FF
697 /*
698 * Only run the baseband hang check if beacons stop working in AP or
699 * IBSS mode, because it has a high false positive rate. For station
700 * mode it should not be necessary, since the upper layers will detect
701 * this through a beacon miss automatically and the following channel
702 * change will trigger a hardware reset anyway
703 */
704 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
705 !ath9k_hw_check_alive(ah))
347809fc
FF
706 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
707
4105f807
RM
708 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
709 /*
710 * TSF sync does not look correct; remain awake to sync with
711 * the next Beacon.
712 */
d2182b69 713 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 714 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807
RM
715 }
716
b5c80475
FF
717 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
718 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
719 ATH9K_INT_RXORN);
720 else
721 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
722
723 if (status & rxmask) {
b5c80475
FF
724 /* Check for high priority Rx first */
725 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
726 (status & ATH9K_INT_RXHP))
727 ath_rx_tasklet(sc, 0, true);
728
729 ath_rx_tasklet(sc, 0, false);
ff37e337
S
730 }
731
e5003249
VT
732 if (status & ATH9K_INT_TX) {
733 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
734 ath_tx_edma_tasklet(sc);
735 else
736 ath_tx_tasklet(sc);
737 }
063d8be3 738
56ca0dba 739 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 740
e3927007 741out:
ff37e337 742 /* re-enable hardware interrupt */
4df3071e 743 ath9k_hw_enable_interrupts(ah);
6a6733f2 744
52671e43 745 spin_unlock(&sc->sc_pcu_lock);
153e080d 746 ath9k_ps_restore(sc);
ff37e337
S
747}
748
6baff7f9 749irqreturn_t ath_isr(int irq, void *dev)
ff37e337 750{
063d8be3
S
751#define SCHED_INTR ( \
752 ATH9K_INT_FATAL | \
a4d86d95 753 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
754 ATH9K_INT_RXORN | \
755 ATH9K_INT_RXEOL | \
756 ATH9K_INT_RX | \
b5c80475
FF
757 ATH9K_INT_RXLP | \
758 ATH9K_INT_RXHP | \
063d8be3
S
759 ATH9K_INT_TX | \
760 ATH9K_INT_BMISS | \
761 ATH9K_INT_CST | \
ebb8e1d7 762 ATH9K_INT_TSFOOR | \
40dc5392
MSS
763 ATH9K_INT_GENTIMER | \
764 ATH9K_INT_MCI)
063d8be3 765
ff37e337 766 struct ath_softc *sc = dev;
cbe61d8a 767 struct ath_hw *ah = sc->sc_ah;
b5bfc568 768 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
769 enum ath9k_int status;
770 bool sched = false;
771
063d8be3
S
772 /*
773 * The hardware is not ready/present, don't
774 * touch anything. Note this can happen early
775 * on if the IRQ is shared.
776 */
777 if (sc->sc_flags & SC_OP_INVALID)
778 return IRQ_NONE;
ff37e337 779
063d8be3
S
780
781 /* shared irq, not for us */
782
153e080d 783 if (!ath9k_hw_intrpend(ah))
063d8be3 784 return IRQ_NONE;
063d8be3
S
785
786 /*
787 * Figure out the reason(s) for the interrupt. Note
788 * that the hal returns a pseudo-ISR that may include
789 * bits we haven't explicitly enabled so we mask the
790 * value to insure we only process bits we requested.
791 */
792 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 793 status &= ah->imask; /* discard unasked-for bits */
ff37e337 794
063d8be3
S
795 /*
796 * If there are no status bits set, then this interrupt was not
797 * for me (should have been caught above).
798 */
153e080d 799 if (!status)
063d8be3 800 return IRQ_NONE;
ff37e337 801
063d8be3
S
802 /* Cache the status */
803 sc->intrstatus = status;
804
805 if (status & SCHED_INTR)
806 sched = true;
807
808 /*
809 * If a FATAL or RXORN interrupt is received, we have to reset the
810 * chip immediately.
811 */
b5c80475
FF
812 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
813 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
814 goto chip_reset;
815
08578b8f
LR
816 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
817 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
818
819 spin_lock(&common->cc_lock);
820 ath_hw_cycle_counters_update(common);
08578b8f 821 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
822 spin_unlock(&common->cc_lock);
823
08578b8f
LR
824 goto chip_reset;
825 }
826
063d8be3
S
827 if (status & ATH9K_INT_SWBA)
828 tasklet_schedule(&sc->bcon_tasklet);
829
830 if (status & ATH9K_INT_TXURN)
831 ath9k_hw_updatetxtriglevel(ah, true);
832
0682c9b5
RM
833 if (status & ATH9K_INT_RXEOL) {
834 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 835 ath9k_hw_set_interrupts(ah);
b5c80475
FF
836 }
837
063d8be3 838 if (status & ATH9K_INT_MIB) {
ff37e337 839 /*
063d8be3
S
840 * Disable interrupts until we service the MIB
841 * interrupt; otherwise it will continue to
842 * fire.
ff37e337 843 */
4df3071e 844 ath9k_hw_disable_interrupts(ah);
063d8be3
S
845 /*
846 * Let the hal handle the event. We assume
847 * it will clear whatever condition caused
848 * the interrupt.
849 */
88eac2da 850 spin_lock(&common->cc_lock);
bfc472bb 851 ath9k_hw_proc_mib_event(ah);
88eac2da 852 spin_unlock(&common->cc_lock);
4df3071e 853 ath9k_hw_enable_interrupts(ah);
063d8be3 854 }
ff37e337 855
153e080d
VT
856 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
857 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
858 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
859 goto chip_reset;
063d8be3
S
860 /* Clear RxAbort bit so that we can
861 * receive frames */
9ecdef4b 862 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 863 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 864 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 865 }
063d8be3
S
866
867chip_reset:
ff37e337 868
817e11de
S
869 ath_debug_stat_interrupt(sc, status);
870
ff37e337 871 if (sched) {
4df3071e
FF
872 /* turn off every interrupt */
873 ath9k_hw_disable_interrupts(ah);
ff37e337
S
874 tasklet_schedule(&sc->intr_tq);
875 }
876
877 return IRQ_HANDLED;
063d8be3
S
878
879#undef SCHED_INTR
ff37e337
S
880}
881
236de514 882static int ath_reset(struct ath_softc *sc, bool retry_tx)
ff37e337 883{
ae8d2858 884 int r;
ff37e337 885
783cd01e 886 ath9k_ps_wakeup(sc);
6a6733f2 887
9adcf440 888 r = ath_reset_internal(sc, NULL, retry_tx);
ff37e337
S
889
890 if (retry_tx) {
891 int i;
892 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
893 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
894 spin_lock_bh(&sc->tx.txq[i].axq_lock);
895 ath_txq_schedule(sc, &sc->tx.txq[i]);
896 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
897 }
898 }
899 }
900
783cd01e 901 ath9k_ps_restore(sc);
2ab81d4a 902
ae8d2858 903 return r;
ff37e337
S
904}
905
236de514
FF
906void ath_reset_work(struct work_struct *work)
907{
908 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
909
236de514 910 ath_reset(sc, true);
236de514
FF
911}
912
e8cfe9f8
FF
913void ath_hw_check(struct work_struct *work)
914{
915 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
916 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
917 unsigned long flags;
918 int busy;
01e18918 919 u8 is_alive, nbeacon = 1;
e8cfe9f8
FF
920
921 ath9k_ps_wakeup(sc);
01e18918
RM
922 is_alive = ath9k_hw_check_alive(sc->sc_ah);
923
924 if (is_alive && !AR_SREV_9300(sc->sc_ah))
e8cfe9f8 925 goto out;
01e18918
RM
926 else if (!is_alive && AR_SREV_9300(sc->sc_ah)) {
927 ath_dbg(common, RESET,
928 "DCU stuck is detected. Schedule chip reset\n");
929 RESET_STAT_INC(sc, RESET_TYPE_MAC_HANG);
930 goto sched_reset;
931 }
e8cfe9f8
FF
932
933 spin_lock_irqsave(&common->cc_lock, flags);
934 busy = ath_update_survey_stats(sc);
935 spin_unlock_irqrestore(&common->cc_lock, flags);
936
d2182b69
JP
937 ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n",
938 busy, sc->hw_busy_count + 1);
e8cfe9f8 939 if (busy >= 99) {
030d6294
FF
940 if (++sc->hw_busy_count >= 3) {
941 RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
01e18918 942 goto sched_reset;
030d6294 943 }
01e18918 944 } else if (busy >= 0) {
e8cfe9f8 945 sc->hw_busy_count = 0;
01e18918
RM
946 nbeacon = 3;
947 }
e8cfe9f8 948
01e18918
RM
949 ath_start_rx_poll(sc, nbeacon);
950 goto out;
951
952sched_reset:
953 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e8cfe9f8
FF
954out:
955 ath9k_ps_restore(sc);
956}
957
958static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
959{
960 static int count;
961 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
962
963 if (pll_sqsum >= 0x40000) {
964 count++;
965 if (count == 3) {
966 /* Rx is hung for more than 500ms. Reset it */
d2182b69 967 ath_dbg(common, RESET, "Possible RX hang, resetting\n");
030d6294 968 RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
9adcf440 969 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e8cfe9f8
FF
970 count = 0;
971 }
972 } else
973 count = 0;
974}
975
976void ath_hw_pll_work(struct work_struct *work)
977{
978 struct ath_softc *sc = container_of(work, struct ath_softc,
979 hw_pll_work.work);
980 u32 pll_sqsum;
981
982 if (AR_SREV_9485(sc->sc_ah)) {
983
984 ath9k_ps_wakeup(sc);
985 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
986 ath9k_ps_restore(sc);
987
988 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
989
990 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
991 }
992}
993
ff37e337
S
994/**********************/
995/* mac80211 callbacks */
996/**********************/
997
8feceb67 998static int ath9k_start(struct ieee80211_hw *hw)
f078f209 999{
9ac58615 1000 struct ath_softc *sc = hw->priv;
af03abec 1001 struct ath_hw *ah = sc->sc_ah;
c46917bb 1002 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1003 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1004 struct ath9k_channel *init_channel;
82880a7c 1005 int r;
f078f209 1006
d2182b69 1007 ath_dbg(common, CONFIG,
226afe68
JP
1008 "Starting driver with initial channel: %d MHz\n",
1009 curchan->center_freq);
f078f209 1010
f62d816f 1011 ath9k_ps_wakeup(sc);
141b38b6
S
1012 mutex_lock(&sc->mutex);
1013
c344c9cb 1014 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
1015
1016 /* Reset SERDES registers */
84c87dc8 1017 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S
1018
1019 /*
1020 * The basic interface to setting the hardware in a good
1021 * state is ``reset''. On return the hardware is known to
1022 * be powered up and with interrupts disabled. This must
1023 * be followed by initialization of the appropriate bits
1024 * and then setup of the interrupt mask.
1025 */
4bdd1e97 1026 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF
1027
1028 atomic_set(&ah->intr_ref_cnt, -1);
1029
20bd2a09 1030 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1031 if (r) {
3800276a
JP
1032 ath_err(common,
1033 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1034 r, curchan->center_freq);
4bdd1e97 1035 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1036 goto mutex_unlock;
ff37e337 1037 }
ff37e337 1038
ff37e337 1039 /* Setup our intr mask. */
b5c80475
FF
1040 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1041 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1042 ATH9K_INT_GLOBAL;
1043
1044 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1045 ah->imask |= ATH9K_INT_RXHP |
1046 ATH9K_INT_RXLP |
1047 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1048 else
1049 ah->imask |= ATH9K_INT_RX;
ff37e337 1050
364734fa 1051 ah->imask |= ATH9K_INT_GTT;
ff37e337 1052
af03abec 1053 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1054 ah->imask |= ATH9K_INT_CST;
ff37e337 1055
40dc5392
MSS
1056 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1057 ah->imask |= ATH9K_INT_MCI;
1058
ff37e337 1059 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1060 sc->sc_ah->is_monitoring = false;
ff37e337 1061
9adcf440
FF
1062 if (!ath_complete_reset(sc, false)) {
1063 r = -EIO;
1064 spin_unlock_bh(&sc->sc_pcu_lock);
1065 goto mutex_unlock;
1066 }
ff37e337 1067
c0c11741
FF
1068 if (ah->led_pin >= 0) {
1069 ath9k_hw_cfg_output(ah, ah->led_pin,
1070 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1071 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1072 }
1073
1074 /*
1075 * Reset key cache to sane defaults (all entries cleared) instead of
1076 * semi-random values after suspend/resume.
1077 */
1078 ath9k_cmn_init_crypto(sc->sc_ah);
1079
9adcf440 1080 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 1081
df198b17 1082 ath9k_start_btcoex(sc);
1773912b 1083
8060e169
VT
1084 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1085 common->bus_ops->extn_synch_en(common);
1086
141b38b6
S
1087mutex_unlock:
1088 mutex_unlock(&sc->mutex);
1089
f62d816f
FF
1090 ath9k_ps_restore(sc);
1091
ae8d2858 1092 return r;
f078f209
LR
1093}
1094
7bb45683 1095static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 1096{
9ac58615 1097 struct ath_softc *sc = hw->priv;
c46917bb 1098 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1099 struct ath_tx_control txctl;
1bc14880 1100 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1101
96148326 1102 if (sc->ps_enabled) {
dc8c4585
JM
1103 /*
1104 * mac80211 does not set PM field for normal data frames, so we
1105 * need to update that based on the current PS mode.
1106 */
1107 if (ieee80211_is_data(hdr->frame_control) &&
1108 !ieee80211_is_nullfunc(hdr->frame_control) &&
1109 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 1110 ath_dbg(common, PS,
226afe68 1111 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
1112 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1113 }
1114 }
1115
c8e8868e
FF
1116 /*
1117 * Cannot tx while the hardware is in full sleep, it first needs a full
1118 * chip reset to recover from that
1119 */
1120 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP))
1121 goto exit;
1122
9a23f9ca
JM
1123 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1124 /*
1125 * We are using PS-Poll and mac80211 can request TX while in
1126 * power save mode. Need to wake up hardware for the TX to be
1127 * completed and if needed, also for RX of buffered frames.
1128 */
9a23f9ca 1129 ath9k_ps_wakeup(sc);
fdf76622
VT
1130 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1131 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1132 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 1133 ath_dbg(common, PS,
226afe68 1134 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1135 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1136 } else {
d2182b69 1137 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 1138 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1139 }
1140 /*
1141 * The actual restore operation will happen only after
1142 * the sc_flags bit is cleared. We are just dropping
1143 * the ps_usecount here.
1144 */
1145 ath9k_ps_restore(sc);
1146 }
1147
528f0c6b 1148 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1149 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1150
d2182b69 1151 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1152
c52f33d0 1153 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 1154 ath_dbg(common, XMIT, "TX failed\n");
528f0c6b 1155 goto exit;
8feceb67
VT
1156 }
1157
7bb45683 1158 return;
528f0c6b
S
1159exit:
1160 dev_kfree_skb_any(skb);
f078f209
LR
1161}
1162
8feceb67 1163static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1164{
9ac58615 1165 struct ath_softc *sc = hw->priv;
af03abec 1166 struct ath_hw *ah = sc->sc_ah;
c46917bb 1167 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 1168 bool prev_idle;
f078f209 1169
4c483817
S
1170 mutex_lock(&sc->mutex);
1171
9adcf440 1172 ath_cancel_work(sc);
01e18918 1173 del_timer_sync(&sc->rx_poll_timer);
c94dbff7 1174
9c84b797 1175 if (sc->sc_flags & SC_OP_INVALID) {
d2182b69 1176 ath_dbg(common, ANY, "Device not present\n");
4c483817 1177 mutex_unlock(&sc->mutex);
9c84b797
S
1178 return;
1179 }
8feceb67 1180
3867cf6a
S
1181 /* Ensure HW is awake when we try to shut it down. */
1182 ath9k_ps_wakeup(sc);
1183
df198b17 1184 ath9k_stop_btcoex(sc);
1773912b 1185
6a6733f2
LR
1186 spin_lock_bh(&sc->sc_pcu_lock);
1187
203043f5
SG
1188 /* prevent tasklets to enable interrupts once we disable them */
1189 ah->imask &= ~ATH9K_INT_GLOBAL;
1190
ff37e337
S
1191 /* make sure h/w will not generate any interrupt
1192 * before setting the invalid flag. */
4df3071e 1193 ath9k_hw_disable_interrupts(ah);
ff37e337 1194
c0c11741
FF
1195 spin_unlock_bh(&sc->sc_pcu_lock);
1196
1197 /* we can now sync irq and kill any running tasklets, since we already
1198 * disabled interrupts and not holding a spin lock */
1199 synchronize_irq(sc->irq);
1200 tasklet_kill(&sc->intr_tq);
1201 tasklet_kill(&sc->bcon_tasklet);
1202
1203 prev_idle = sc->ps_idle;
1204 sc->ps_idle = true;
1205
1206 spin_lock_bh(&sc->sc_pcu_lock);
1207
1208 if (ah->led_pin >= 0) {
1209 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1210 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1211 }
1212
1213 ath_prepare_reset(sc, false, true);
ff37e337 1214
0d95521e
FF
1215 if (sc->rx.frag) {
1216 dev_kfree_skb_any(sc->rx.frag);
1217 sc->rx.frag = NULL;
1218 }
1219
c0c11741
FF
1220 if (!ah->curchan)
1221 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
6a6733f2 1222
c0c11741
FF
1223 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
1224 ath9k_hw_phy_disable(ah);
6a6733f2 1225
c0c11741 1226 ath9k_hw_configpcipowersave(ah, true);
203043f5 1227
c0c11741 1228 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 1229
c0c11741 1230 ath9k_ps_restore(sc);
ff37e337
S
1231
1232 sc->sc_flags |= SC_OP_INVALID;
c0c11741 1233 sc->ps_idle = prev_idle;
500c064d 1234
141b38b6
S
1235 mutex_unlock(&sc->mutex);
1236
d2182b69 1237 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR
1238}
1239
4801416c
BG
1240bool ath9k_uses_beacons(int type)
1241{
1242 switch (type) {
1243 case NL80211_IFTYPE_AP:
1244 case NL80211_IFTYPE_ADHOC:
1245 case NL80211_IFTYPE_MESH_POINT:
1246 return true;
1247 default:
1248 return false;
1249 }
1250}
1251
1252static void ath9k_reclaim_beacon(struct ath_softc *sc,
1253 struct ieee80211_vif *vif)
f078f209 1254{
1ed32e4f 1255 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1256
014cf3bb 1257 ath9k_set_beaconing_status(sc, false);
4801416c 1258 ath_beacon_return(sc, avp);
014cf3bb 1259 ath9k_set_beaconing_status(sc, true);
4801416c 1260 sc->sc_flags &= ~SC_OP_BEACONS;
4801416c
BG
1261}
1262
1263static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1264{
1265 struct ath9k_vif_iter_data *iter_data = data;
1266 int i;
1267
1268 if (iter_data->hw_macaddr)
1269 for (i = 0; i < ETH_ALEN; i++)
1270 iter_data->mask[i] &=
1271 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1272
1ed32e4f 1273 switch (vif->type) {
4801416c
BG
1274 case NL80211_IFTYPE_AP:
1275 iter_data->naps++;
f078f209 1276 break;
4801416c
BG
1277 case NL80211_IFTYPE_STATION:
1278 iter_data->nstations++;
e51f3eff 1279 break;
05c914fe 1280 case NL80211_IFTYPE_ADHOC:
4801416c
BG
1281 iter_data->nadhocs++;
1282 break;
9cb5412b 1283 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
1284 iter_data->nmeshes++;
1285 break;
1286 case NL80211_IFTYPE_WDS:
1287 iter_data->nwds++;
f078f209
LR
1288 break;
1289 default:
4801416c 1290 break;
f078f209 1291 }
4801416c 1292}
f078f209 1293
4801416c
BG
1294/* Called with sc->mutex held. */
1295void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1296 struct ieee80211_vif *vif,
1297 struct ath9k_vif_iter_data *iter_data)
1298{
9ac58615 1299 struct ath_softc *sc = hw->priv;
4801416c
BG
1300 struct ath_hw *ah = sc->sc_ah;
1301 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1302
4801416c
BG
1303 /*
1304 * Use the hardware MAC address as reference, the hardware uses it
1305 * together with the BSSID mask when matching addresses.
1306 */
1307 memset(iter_data, 0, sizeof(*iter_data));
1308 iter_data->hw_macaddr = common->macaddr;
1309 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1310
4801416c
BG
1311 if (vif)
1312 ath9k_vif_iter(iter_data, vif->addr, vif);
1313
1314 /* Get list of all active MAC addresses */
4801416c
BG
1315 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1316 iter_data);
4801416c 1317}
8ca21f01 1318
4801416c
BG
1319/* Called with sc->mutex held. */
1320static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1321 struct ieee80211_vif *vif)
1322{
9ac58615 1323 struct ath_softc *sc = hw->priv;
4801416c
BG
1324 struct ath_hw *ah = sc->sc_ah;
1325 struct ath_common *common = ath9k_hw_common(ah);
1326 struct ath9k_vif_iter_data iter_data;
8ca21f01 1327
4801416c 1328 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1329
4801416c
BG
1330 /* Set BSSID mask. */
1331 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1332 ath_hw_setbssidmask(common);
1333
1334 /* Set op-mode & TSF */
1335 if (iter_data.naps > 0) {
3069168c 1336 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1337 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG
1338 ah->opmode = NL80211_IFTYPE_AP;
1339 } else {
1340 ath9k_hw_set_tsfadjust(ah, 0);
1341 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1342
fd5999cf
JC
1343 if (iter_data.nmeshes)
1344 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1345 else if (iter_data.nwds)
4801416c
BG
1346 ah->opmode = NL80211_IFTYPE_AP;
1347 else if (iter_data.nadhocs)
1348 ah->opmode = NL80211_IFTYPE_ADHOC;
1349 else
1350 ah->opmode = NL80211_IFTYPE_STATION;
1351 }
5640b08e 1352
4e30ffa2
VN
1353 /*
1354 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1355 */
4801416c 1356 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR
1357 if (ah->config.enable_ani)
1358 ah->imask |= ATH9K_INT_MIB;
3069168c 1359 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG
1360 } else {
1361 ah->imask &= ~ATH9K_INT_MIB;
1362 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S
1363 }
1364
72d874c6 1365 ath9k_hw_set_interrupts(ah);
4e30ffa2 1366
4801416c 1367 /* Set up ANI */
2e5ef459 1368 if (iter_data.naps > 0) {
729da390 1369 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
1370
1371 if (!common->disable_ani) {
1372 sc->sc_flags |= SC_OP_ANI_RUN;
1373 ath_start_ani(common);
1374 }
1375
f60c49b6
RM
1376 } else {
1377 sc->sc_flags &= ~SC_OP_ANI_RUN;
1378 del_timer_sync(&common->ani.timer);
6c3118e2 1379 }
4801416c 1380}
6f255425 1381
4801416c
BG
1382/* Called with sc->mutex held, vif counts set up properly. */
1383static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1384 struct ieee80211_vif *vif)
1385{
9ac58615 1386 struct ath_softc *sc = hw->priv;
4801416c
BG
1387
1388 ath9k_calculate_summary_state(hw, vif);
1389
1390 if (ath9k_uses_beacons(vif->type)) {
1391 int error;
4801416c
BG
1392 /* This may fail because upper levels do not have beacons
1393 * properly configured yet. That's OK, we assume it
1394 * will be properly configured and then we will be notified
1395 * in the info_changed method and set up beacons properly
1396 * there.
1397 */
014cf3bb 1398 ath9k_set_beaconing_status(sc, false);
9ac58615 1399 error = ath_beacon_alloc(sc, vif);
391bd1c4 1400 if (!error)
4801416c 1401 ath_beacon_config(sc, vif);
014cf3bb 1402 ath9k_set_beaconing_status(sc, true);
4801416c 1403 }
f078f209
LR
1404}
1405
01e18918
RM
1406void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon)
1407{
1408 if (!AR_SREV_9300(sc->sc_ah))
1409 return;
1410
1411 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF))
1412 return;
1413
1414 mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies
1415 (nbeacon * sc->cur_beacon_conf.beacon_interval));
1416}
1417
1418void ath_rx_poll(unsigned long data)
1419{
1420 struct ath_softc *sc = (struct ath_softc *)data;
1421
1422 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
1423}
4801416c
BG
1424
1425static int ath9k_add_interface(struct ieee80211_hw *hw,
1426 struct ieee80211_vif *vif)
6b3b991d 1427{
9ac58615 1428 struct ath_softc *sc = hw->priv;
4801416c
BG
1429 struct ath_hw *ah = sc->sc_ah;
1430 struct ath_common *common = ath9k_hw_common(ah);
4801416c 1431 int ret = 0;
6b3b991d 1432
96f372c9 1433 ath9k_ps_wakeup(sc);
4801416c 1434 mutex_lock(&sc->mutex);
6b3b991d 1435
4801416c
BG
1436 switch (vif->type) {
1437 case NL80211_IFTYPE_STATION:
1438 case NL80211_IFTYPE_WDS:
1439 case NL80211_IFTYPE_ADHOC:
1440 case NL80211_IFTYPE_AP:
1441 case NL80211_IFTYPE_MESH_POINT:
1442 break;
1443 default:
1444 ath_err(common, "Interface type %d not yet supported\n",
1445 vif->type);
1446 ret = -EOPNOTSUPP;
1447 goto out;
1448 }
6b3b991d 1449
4801416c
BG
1450 if (ath9k_uses_beacons(vif->type)) {
1451 if (sc->nbcnvifs >= ATH_BCBUF) {
1452 ath_err(common, "Not enough beacon buffers when adding"
1453 " new interface of type: %i\n",
1454 vif->type);
1455 ret = -ENOBUFS;
1456 goto out;
1457 }
1458 }
1459
59575d1c
RM
1460 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1461 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1462 sc->nvifs > 0)) {
4801416c
BG
1463 ath_err(common, "Cannot create ADHOC interface when other"
1464 " interfaces already exist.\n");
1465 ret = -EINVAL;
1466 goto out;
6b3b991d 1467 }
4801416c 1468
d2182b69 1469 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
4801416c 1470
4801416c
BG
1471 sc->nvifs++;
1472
1473 ath9k_do_vif_add_setup(hw, vif);
1474out:
1475 mutex_unlock(&sc->mutex);
96f372c9 1476 ath9k_ps_restore(sc);
4801416c 1477 return ret;
6b3b991d
RM
1478}
1479
1480static int ath9k_change_interface(struct ieee80211_hw *hw,
1481 struct ieee80211_vif *vif,
1482 enum nl80211_iftype new_type,
1483 bool p2p)
1484{
9ac58615 1485 struct ath_softc *sc = hw->priv;
6b3b991d 1486 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1487 int ret = 0;
6b3b991d 1488
d2182b69 1489 ath_dbg(common, CONFIG, "Change Interface\n");
6b3b991d 1490 mutex_lock(&sc->mutex);
96f372c9 1491 ath9k_ps_wakeup(sc);
6b3b991d 1492
4801416c
BG
1493 /* See if new interface type is valid. */
1494 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1495 (sc->nvifs > 1)) {
1496 ath_err(common, "When using ADHOC, it must be the only"
1497 " interface.\n");
1498 ret = -EINVAL;
1499 goto out;
1500 }
1501
1502 if (ath9k_uses_beacons(new_type) &&
1503 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1504 if (sc->nbcnvifs >= ATH_BCBUF) {
1505 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1506 ret = -ENOBUFS;
1507 goto out;
6b3b991d 1508 }
6b3b991d 1509 }
4801416c
BG
1510
1511 /* Clean up old vif stuff */
1512 if (ath9k_uses_beacons(vif->type))
1513 ath9k_reclaim_beacon(sc, vif);
1514
1515 /* Add new settings */
6b3b991d
RM
1516 vif->type = new_type;
1517 vif->p2p = p2p;
1518
4801416c 1519 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1520out:
96f372c9 1521 ath9k_ps_restore(sc);
6b3b991d 1522 mutex_unlock(&sc->mutex);
6dab55bf 1523 return ret;
6b3b991d
RM
1524}
1525
8feceb67 1526static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1527 struct ieee80211_vif *vif)
f078f209 1528{
9ac58615 1529 struct ath_softc *sc = hw->priv;
c46917bb 1530 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1531
d2182b69 1532 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1533
96f372c9 1534 ath9k_ps_wakeup(sc);
141b38b6
S
1535 mutex_lock(&sc->mutex);
1536
4801416c 1537 sc->nvifs--;
580f0b8a 1538
8feceb67 1539 /* Reclaim beacon resources */
4801416c 1540 if (ath9k_uses_beacons(vif->type))
6b3b991d 1541 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1542
4801416c 1543 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1544
1545 mutex_unlock(&sc->mutex);
96f372c9 1546 ath9k_ps_restore(sc);
f078f209
LR
1547}
1548
fbab7390 1549static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1550{
3069168c
PR
1551 struct ath_hw *ah = sc->sc_ah;
1552
3f7c5c10 1553 sc->ps_enabled = true;
3069168c
PR
1554 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1555 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1556 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1557 ath9k_hw_set_interrupts(ah);
3f7c5c10 1558 }
fdf76622 1559 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1560 }
3f7c5c10
SB
1561}
1562
845d708e
SB
1563static void ath9k_disable_ps(struct ath_softc *sc)
1564{
1565 struct ath_hw *ah = sc->sc_ah;
1566
1567 sc->ps_enabled = false;
1568 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1569 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1570 ath9k_hw_setrxabort(ah, 0);
1571 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1572 PS_WAIT_FOR_CAB |
1573 PS_WAIT_FOR_PSPOLL_DATA |
1574 PS_WAIT_FOR_TX_ACK);
1575 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1576 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1577 ath9k_hw_set_interrupts(ah);
845d708e
SB
1578 }
1579 }
1580
1581}
1582
e8975581 1583static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1584{
9ac58615 1585 struct ath_softc *sc = hw->priv;
3430098a
FF
1586 struct ath_hw *ah = sc->sc_ah;
1587 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1588 struct ieee80211_conf *conf = &hw->conf;
f078f209 1589
c0c11741 1590 ath9k_ps_wakeup(sc);
aa33de09 1591 mutex_lock(&sc->mutex);
141b38b6 1592
daa1b6ee 1593 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1594 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
daa1b6ee
FF
1595 if (sc->ps_idle)
1596 ath_cancel_work(sc);
1597 }
64839170 1598
e7824a50
LR
1599 /*
1600 * We just prepare to enable PS. We have to wait until our AP has
1601 * ACK'd our null data frame to disable RX otherwise we'll ignore
1602 * those ACKs and end up retransmitting the same null data frames.
1603 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1604 */
3cbb5dd7 1605 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1606 unsigned long flags;
1607 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1608 if (conf->flags & IEEE80211_CONF_PS)
1609 ath9k_enable_ps(sc);
845d708e
SB
1610 else
1611 ath9k_disable_ps(sc);
8ab2cd09 1612 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1613 }
1614
199afd9d
S
1615 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1616 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1617 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM
1618 sc->sc_ah->is_monitoring = true;
1619 } else {
d2182b69 1620 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1621 sc->sc_ah->is_monitoring = false;
199afd9d
S
1622 }
1623 }
1624
4797938c 1625 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1626 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1627 int pos = curchan->hw_value;
3430098a
FF
1628 int old_pos = -1;
1629 unsigned long flags;
1630
1631 if (ah->curchan)
1632 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1633
5ee08656
FF
1634 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1635 sc->sc_flags |= SC_OP_OFFCHANNEL;
1636 else
1637 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1638
d2182b69 1639 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
8c79a610 1640 curchan->center_freq, conf->channel_type);
f078f209 1641
3430098a
FF
1642 /* update survey stats for the old channel before switching */
1643 spin_lock_irqsave(&common->cc_lock, flags);
1644 ath_update_survey_stats(sc);
1645 spin_unlock_irqrestore(&common->cc_lock, flags);
1646
e338a85e
RM
1647 /*
1648 * Preserve the current channel values, before updating
1649 * the same channel
1650 */
1a19f77f
RM
1651 if (ah->curchan && (old_pos == pos))
1652 ath9k_hw_getnf(ah, ah->curchan);
e338a85e
RM
1653
1654 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1655 curchan, conf->channel_type);
1656
3430098a
FF
1657 /*
1658 * If the operating channel changes, change the survey in-use flags
1659 * along with it.
1660 * Reset the survey data for the new channel, unless we're switching
1661 * back to the operating channel from an off-channel operation.
1662 */
1663 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1664 sc->cur_survey != &sc->survey[pos]) {
1665
1666 if (sc->cur_survey)
1667 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1668
1669 sc->cur_survey = &sc->survey[pos];
1670
1671 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1672 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1673 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1674 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1675 }
1676
0e2dedf9 1677 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1678 ath_err(common, "Unable to set channel\n");
aa33de09 1679 mutex_unlock(&sc->mutex);
e11602b7
S
1680 return -EINVAL;
1681 }
3430098a
FF
1682
1683 /*
1684 * The most recent snapshot of channel->noisefloor for the old
1685 * channel is only available after the hardware reset. Copy it to
1686 * the survey stats now.
1687 */
1688 if (old_pos >= 0)
1689 ath_update_survey_nf(sc, old_pos);
094d05dc 1690 }
f078f209 1691
c9f6a656 1692 if (changed & IEEE80211_CONF_CHANGE_POWER) {
d2182b69 1693 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
17d7904d 1694 sc->config.txpowlimit = 2 * conf->power_level;
5048e8c3
RM
1695 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1696 sc->config.txpowlimit, &sc->curtxpow);
64839170
LR
1697 }
1698
aa33de09 1699 mutex_unlock(&sc->mutex);
c0c11741 1700 ath9k_ps_restore(sc);
141b38b6 1701
f078f209
LR
1702 return 0;
1703}
1704
8feceb67
VT
1705#define SUPPORTED_FILTERS \
1706 (FIF_PROMISC_IN_BSS | \
1707 FIF_ALLMULTI | \
1708 FIF_CONTROL | \
af6a3fc7 1709 FIF_PSPOLL | \
8feceb67
VT
1710 FIF_OTHER_BSS | \
1711 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1712 FIF_PROBE_REQ | \
8feceb67 1713 FIF_FCSFAIL)
c83be688 1714
8feceb67
VT
1715/* FIXME: sc->sc_full_reset ? */
1716static void ath9k_configure_filter(struct ieee80211_hw *hw,
1717 unsigned int changed_flags,
1718 unsigned int *total_flags,
3ac64bee 1719 u64 multicast)
8feceb67 1720{
9ac58615 1721 struct ath_softc *sc = hw->priv;
8feceb67 1722 u32 rfilt;
f078f209 1723
8feceb67
VT
1724 changed_flags &= SUPPORTED_FILTERS;
1725 *total_flags &= SUPPORTED_FILTERS;
f078f209 1726
b77f483f 1727 sc->rx.rxfilter = *total_flags;
aa68aeaa 1728 ath9k_ps_wakeup(sc);
8feceb67
VT
1729 rfilt = ath_calcrxfilter(sc);
1730 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1731 ath9k_ps_restore(sc);
f078f209 1732
d2182b69
JP
1733 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1734 rfilt);
8feceb67 1735}
f078f209 1736
4ca77860
JB
1737static int ath9k_sta_add(struct ieee80211_hw *hw,
1738 struct ieee80211_vif *vif,
1739 struct ieee80211_sta *sta)
8feceb67 1740{
9ac58615 1741 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1742 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1743 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1744 struct ieee80211_key_conf ps_key = { };
f078f209 1745
7e1e3864 1746 ath_node_attach(sc, sta, vif);
f59a59fe
FF
1747
1748 if (vif->type != NL80211_IFTYPE_AP &&
1749 vif->type != NL80211_IFTYPE_AP_VLAN)
1750 return 0;
1751
93ae2dd2 1752 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB
1753
1754 return 0;
1755}
1756
93ae2dd2
FF
1757static void ath9k_del_ps_key(struct ath_softc *sc,
1758 struct ieee80211_vif *vif,
1759 struct ieee80211_sta *sta)
1760{
1761 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1762 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1763 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1764
1765 if (!an->ps_key)
1766 return;
1767
1768 ath_key_delete(common, &ps_key);
1769}
1770
4ca77860
JB
1771static int ath9k_sta_remove(struct ieee80211_hw *hw,
1772 struct ieee80211_vif *vif,
1773 struct ieee80211_sta *sta)
1774{
9ac58615 1775 struct ath_softc *sc = hw->priv;
4ca77860 1776
93ae2dd2 1777 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1778 ath_node_detach(sc, sta);
1779
1780 return 0;
f078f209
LR
1781}
1782
5519541d
FF
1783static void ath9k_sta_notify(struct ieee80211_hw *hw,
1784 struct ieee80211_vif *vif,
1785 enum sta_notify_cmd cmd,
1786 struct ieee80211_sta *sta)
1787{
1788 struct ath_softc *sc = hw->priv;
1789 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1790
3d4e20f2 1791 if (!sta->ht_cap.ht_supported)
b25bfda3
MSS
1792 return;
1793
5519541d
FF
1794 switch (cmd) {
1795 case STA_NOTIFY_SLEEP:
1796 an->sleeping = true;
042ec453 1797 ath_tx_aggr_sleep(sta, sc, an);
5519541d
FF
1798 break;
1799 case STA_NOTIFY_AWAKE:
1800 an->sleeping = false;
1801 ath_tx_aggr_wakeup(sc, an);
1802 break;
1803 }
1804}
1805
8a3a3c85
EP
1806static int ath9k_conf_tx(struct ieee80211_hw *hw,
1807 struct ieee80211_vif *vif, u16 queue,
8feceb67 1808 const struct ieee80211_tx_queue_params *params)
f078f209 1809{
9ac58615 1810 struct ath_softc *sc = hw->priv;
c46917bb 1811 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1812 struct ath_txq *txq;
8feceb67 1813 struct ath9k_tx_queue_info qi;
066dae93 1814 int ret = 0;
f078f209 1815
8feceb67
VT
1816 if (queue >= WME_NUM_AC)
1817 return 0;
f078f209 1818
066dae93
FF
1819 txq = sc->tx.txq_map[queue];
1820
96f372c9 1821 ath9k_ps_wakeup(sc);
141b38b6
S
1822 mutex_lock(&sc->mutex);
1823
1ffb0610
S
1824 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1825
8feceb67
VT
1826 qi.tqi_aifs = params->aifs;
1827 qi.tqi_cwmin = params->cw_min;
1828 qi.tqi_cwmax = params->cw_max;
1829 qi.tqi_burstTime = params->txop;
f078f209 1830
d2182b69 1831 ath_dbg(common, CONFIG,
226afe68
JP
1832 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1833 queue, txq->axq_qnum, params->aifs, params->cw_min,
1834 params->cw_max, params->txop);
f078f209 1835
066dae93 1836 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1837 if (ret)
3800276a 1838 ath_err(common, "TXQ Update failed\n");
f078f209 1839
94db2936 1840 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1841 if (queue == WME_AC_BE && !ret)
94db2936
VN
1842 ath_beaconq_config(sc);
1843
141b38b6 1844 mutex_unlock(&sc->mutex);
96f372c9 1845 ath9k_ps_restore(sc);
141b38b6 1846
8feceb67
VT
1847 return ret;
1848}
f078f209 1849
8feceb67
VT
1850static int ath9k_set_key(struct ieee80211_hw *hw,
1851 enum set_key_cmd cmd,
dc822b5d
JB
1852 struct ieee80211_vif *vif,
1853 struct ieee80211_sta *sta,
8feceb67
VT
1854 struct ieee80211_key_conf *key)
1855{
9ac58615 1856 struct ath_softc *sc = hw->priv;
c46917bb 1857 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1858 int ret = 0;
f078f209 1859
3e6109c5 1860 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1861 return -ENOSPC;
1862
5bd5e9a6
CYY
1863 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1864 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM
1865 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1866 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1867 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1868 /*
1869 * For now, disable hw crypto for the RSN IBSS group keys. This
1870 * could be optimized in the future to use a modified key cache
1871 * design to support per-STA RX GTK, but until that gets
1872 * implemented, use of software crypto for group addressed
1873 * frames is a acceptable to allow RSN IBSS to be used.
1874 */
1875 return -EOPNOTSUPP;
1876 }
1877
141b38b6 1878 mutex_lock(&sc->mutex);
3cbb5dd7 1879 ath9k_ps_wakeup(sc);
d2182b69 1880 ath_dbg(common, CONFIG, "Set HW Key\n");
f078f209 1881
8feceb67
VT
1882 switch (cmd) {
1883 case SET_KEY:
93ae2dd2
FF
1884 if (sta)
1885 ath9k_del_ps_key(sc, vif, sta);
1886
040e539e 1887 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1888 if (ret >= 0) {
1889 key->hw_key_idx = ret;
8feceb67
VT
1890 /* push IV and Michael MIC generation to stack */
1891 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1892 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1893 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1894 if (sc->sc_ah->sw_mgmt_crypto &&
1895 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1896 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1897 ret = 0;
8feceb67
VT
1898 }
1899 break;
1900 case DISABLE_KEY:
040e539e 1901 ath_key_delete(common, key);
8feceb67
VT
1902 break;
1903 default:
1904 ret = -EINVAL;
1905 }
f078f209 1906
3cbb5dd7 1907 ath9k_ps_restore(sc);
141b38b6
S
1908 mutex_unlock(&sc->mutex);
1909
8feceb67
VT
1910 return ret;
1911}
4f5ef75b
RM
1912static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1913{
1914 struct ath_softc *sc = data;
1915 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1916 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1917 struct ath_vif *avp = (void *)vif->drv_priv;
1918
2e5ef459
RM
1919 /*
1920 * Skip iteration if primary station vif's bss info
1921 * was not changed
1922 */
1923 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1924 return;
1925
1926 if (bss_conf->assoc) {
1927 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1928 avp->primary_sta_vif = true;
4f5ef75b
RM
1929 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1930 common->curaid = bss_conf->aid;
1931 ath9k_hw_write_associd(sc->sc_ah);
d2182b69
JP
1932 ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
1933 bss_conf->aid, common->curbssid);
2e5ef459
RM
1934 ath_beacon_config(sc, vif);
1935 /*
1936 * Request a re-configuration of Beacon related timers
1937 * on the receipt of the first Beacon frame (i.e.,
1938 * after time sync with the AP).
1939 */
1940 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1941 /* Reset rssi stats */
1942 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1943 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1944
01e18918
RM
1945 ath_start_rx_poll(sc, 3);
1946
05c0be2f
MSS
1947 if (!common->disable_ani) {
1948 sc->sc_flags |= SC_OP_ANI_RUN;
1949 ath_start_ani(common);
1950 }
1951
4f5ef75b
RM
1952 }
1953}
1954
1955static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
1956{
1957 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1958 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1959 struct ath_vif *avp = (void *)vif->drv_priv;
1960
2e5ef459
RM
1961 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1962 return;
1963
4f5ef75b
RM
1964 /* Reconfigure bss info */
1965 if (avp->primary_sta_vif && !bss_conf->assoc) {
d2182b69 1966 ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
99e4d43a
RM
1967 common->curaid, common->curbssid);
1968 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
4f5ef75b
RM
1969 avp->primary_sta_vif = false;
1970 memset(common->curbssid, 0, ETH_ALEN);
1971 common->curaid = 0;
1972 }
1973
1974 ieee80211_iterate_active_interfaces_atomic(
1975 sc->hw, ath9k_bss_iter, sc);
1976
1977 /*
1978 * None of station vifs are associated.
1979 * Clear bssid & aid
1980 */
2e5ef459 1981 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
4f5ef75b 1982 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM
1983 /* Stop ANI */
1984 sc->sc_flags &= ~SC_OP_ANI_RUN;
1985 del_timer_sync(&common->ani.timer);
01e18918 1986 del_timer_sync(&sc->rx_poll_timer);
d2c71c20 1987 memset(&sc->caldata, 0, sizeof(sc->caldata));
99e4d43a 1988 }
4f5ef75b 1989}
f078f209 1990
8feceb67
VT
1991static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1992 struct ieee80211_vif *vif,
1993 struct ieee80211_bss_conf *bss_conf,
1994 u32 changed)
1995{
9ac58615 1996 struct ath_softc *sc = hw->priv;
2d0ddec5 1997 struct ath_hw *ah = sc->sc_ah;
1510718d 1998 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1999 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 2000 int slottime;
c6089ccc 2001 int error;
f078f209 2002
96f372c9 2003 ath9k_ps_wakeup(sc);
141b38b6
S
2004 mutex_lock(&sc->mutex);
2005
9f61903c 2006 if (changed & BSS_CHANGED_ASSOC) {
4f5ef75b 2007 ath9k_config_bss(sc, vif);
2d0ddec5 2008
d2182b69 2009 ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
226afe68 2010 common->curbssid, common->curaid);
c6089ccc 2011 }
2d0ddec5 2012
2e5ef459
RM
2013 if (changed & BSS_CHANGED_IBSS) {
2014 /* There can be only one vif available */
2015 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2016 common->curaid = bss_conf->aid;
2017 ath9k_hw_write_associd(sc->sc_ah);
2018
2019 if (bss_conf->ibss_joined) {
2020 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
2021
2022 if (!common->disable_ani) {
2023 sc->sc_flags |= SC_OP_ANI_RUN;
2024 ath_start_ani(common);
2025 }
2026
2e5ef459
RM
2027 } else {
2028 sc->sc_flags &= ~SC_OP_ANI_RUN;
2029 del_timer_sync(&common->ani.timer);
01e18918 2030 del_timer_sync(&sc->rx_poll_timer);
2e5ef459
RM
2031 }
2032 }
2033
c6089ccc
S
2034 /* Enable transmission of beacons (AP, IBSS, MESH) */
2035 if ((changed & BSS_CHANGED_BEACON) ||
2036 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
014cf3bb 2037 ath9k_set_beaconing_status(sc, false);
9ac58615 2038 error = ath_beacon_alloc(sc, vif);
c6089ccc
S
2039 if (!error)
2040 ath_beacon_config(sc, vif);
014cf3bb 2041 ath9k_set_beaconing_status(sc, true);
0005baf4
FF
2042 }
2043
2044 if (changed & BSS_CHANGED_ERP_SLOT) {
2045 if (bss_conf->use_short_slot)
2046 slottime = 9;
2047 else
2048 slottime = 20;
2049 if (vif->type == NL80211_IFTYPE_AP) {
2050 /*
2051 * Defer update, so that connected stations can adjust
2052 * their settings at the same time.
2053 * See beacon.c for more details
2054 */
2055 sc->beacon.slottime = slottime;
2056 sc->beacon.updateslot = UPDATE;
2057 } else {
2058 ah->slottime = slottime;
2059 ath9k_hw_init_global_settings(ah);
2060 }
2d0ddec5
JB
2061 }
2062
c6089ccc 2063 /* Disable transmission of beacons */
014cf3bb
RM
2064 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2065 !bss_conf->enable_beacon) {
2066 ath9k_set_beaconing_status(sc, false);
2067 avp->is_bslot_active = false;
2068 ath9k_set_beaconing_status(sc, true);
2069 }
2d0ddec5 2070
c6089ccc 2071 if (changed & BSS_CHANGED_BEACON_INT) {
c6089ccc
S
2072 /*
2073 * In case of AP mode, the HW TSF has to be reset
2074 * when the beacon interval changes.
2075 */
2076 if (vif->type == NL80211_IFTYPE_AP) {
2077 sc->sc_flags |= SC_OP_TSF_RESET;
014cf3bb 2078 ath9k_set_beaconing_status(sc, false);
9ac58615 2079 error = ath_beacon_alloc(sc, vif);
2d0ddec5
JB
2080 if (!error)
2081 ath_beacon_config(sc, vif);
014cf3bb 2082 ath9k_set_beaconing_status(sc, true);
99e4d43a 2083 } else
c6089ccc 2084 ath_beacon_config(sc, vif);
2d0ddec5
JB
2085 }
2086
141b38b6 2087 mutex_unlock(&sc->mutex);
96f372c9 2088 ath9k_ps_restore(sc);
8feceb67 2089}
f078f209 2090
37a41b4a 2091static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 2092{
9ac58615 2093 struct ath_softc *sc = hw->priv;
8feceb67 2094 u64 tsf;
f078f209 2095
141b38b6 2096 mutex_lock(&sc->mutex);
9abbfb27 2097 ath9k_ps_wakeup(sc);
141b38b6 2098 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2099 ath9k_ps_restore(sc);
141b38b6 2100 mutex_unlock(&sc->mutex);
f078f209 2101
8feceb67
VT
2102 return tsf;
2103}
f078f209 2104
37a41b4a
EP
2105static void ath9k_set_tsf(struct ieee80211_hw *hw,
2106 struct ieee80211_vif *vif,
2107 u64 tsf)
3b5d665b 2108{
9ac58615 2109 struct ath_softc *sc = hw->priv;
3b5d665b 2110
141b38b6 2111 mutex_lock(&sc->mutex);
9abbfb27 2112 ath9k_ps_wakeup(sc);
141b38b6 2113 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2114 ath9k_ps_restore(sc);
141b38b6 2115 mutex_unlock(&sc->mutex);
3b5d665b
AF
2116}
2117
37a41b4a 2118static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 2119{
9ac58615 2120 struct ath_softc *sc = hw->priv;
c83be688 2121
141b38b6 2122 mutex_lock(&sc->mutex);
21526d57
LR
2123
2124 ath9k_ps_wakeup(sc);
141b38b6 2125 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2126 ath9k_ps_restore(sc);
2127
141b38b6 2128 mutex_unlock(&sc->mutex);
8feceb67 2129}
f078f209 2130
8feceb67 2131static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2132 struct ieee80211_vif *vif,
141b38b6
S
2133 enum ieee80211_ampdu_mlme_action action,
2134 struct ieee80211_sta *sta,
0b01f030 2135 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2136{
9ac58615 2137 struct ath_softc *sc = hw->priv;
8feceb67 2138 int ret = 0;
f078f209 2139
85ad181e
JB
2140 local_bh_disable();
2141
8feceb67
VT
2142 switch (action) {
2143 case IEEE80211_AMPDU_RX_START:
8feceb67
VT
2144 break;
2145 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2146 break;
2147 case IEEE80211_AMPDU_TX_START:
8b685ba9 2148 ath9k_ps_wakeup(sc);
231c3a1f
FF
2149 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2150 if (!ret)
2151 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2152 ath9k_ps_restore(sc);
8feceb67
VT
2153 break;
2154 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2155 ath9k_ps_wakeup(sc);
f83da965 2156 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2157 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2158 ath9k_ps_restore(sc);
8feceb67 2159 break;
b1720231 2160 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2161 ath9k_ps_wakeup(sc);
8469cdef 2162 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2163 ath9k_ps_restore(sc);
8469cdef 2164 break;
8feceb67 2165 default:
3800276a 2166 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
2167 }
2168
85ad181e
JB
2169 local_bh_enable();
2170
8feceb67 2171 return ret;
f078f209
LR
2172}
2173
62dad5b0
BP
2174static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2175 struct survey_info *survey)
2176{
9ac58615 2177 struct ath_softc *sc = hw->priv;
3430098a 2178 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2179 struct ieee80211_supported_band *sband;
3430098a
FF
2180 struct ieee80211_channel *chan;
2181 unsigned long flags;
2182 int pos;
2183
2184 spin_lock_irqsave(&common->cc_lock, flags);
2185 if (idx == 0)
2186 ath_update_survey_stats(sc);
39162dbe
FF
2187
2188 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2189 if (sband && idx >= sband->n_channels) {
2190 idx -= sband->n_channels;
2191 sband = NULL;
2192 }
62dad5b0 2193
39162dbe
FF
2194 if (!sband)
2195 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2196
3430098a
FF
2197 if (!sband || idx >= sband->n_channels) {
2198 spin_unlock_irqrestore(&common->cc_lock, flags);
2199 return -ENOENT;
4f1a5a4b 2200 }
62dad5b0 2201
3430098a
FF
2202 chan = &sband->channels[idx];
2203 pos = chan->hw_value;
2204 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2205 survey->channel = chan;
2206 spin_unlock_irqrestore(&common->cc_lock, flags);
2207
62dad5b0
BP
2208 return 0;
2209}
2210
e239d859
FF
2211static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2212{
9ac58615 2213 struct ath_softc *sc = hw->priv;
e239d859
FF
2214 struct ath_hw *ah = sc->sc_ah;
2215
2216 mutex_lock(&sc->mutex);
2217 ah->coverage_class = coverage_class;
8b2a3827
MSS
2218
2219 ath9k_ps_wakeup(sc);
e239d859 2220 ath9k_hw_init_global_settings(ah);
8b2a3827
MSS
2221 ath9k_ps_restore(sc);
2222
e239d859
FF
2223 mutex_unlock(&sc->mutex);
2224}
2225
69081624
VT
2226static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2227{
69081624 2228 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
2229 struct ath_hw *ah = sc->sc_ah;
2230 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF
2231 int timeout = 200; /* ms */
2232 int i, j;
2f6fc351 2233 bool drain_txq;
69081624
VT
2234
2235 mutex_lock(&sc->mutex);
69081624
VT
2236 cancel_delayed_work_sync(&sc->tx_complete_work);
2237
6a6b3f3e 2238 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 2239 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS
2240 mutex_unlock(&sc->mutex);
2241 return;
2242 }
2243
99aa55b6 2244 if (sc->sc_flags & SC_OP_INVALID) {
d2182b69 2245 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS
2246 mutex_unlock(&sc->mutex);
2247 return;
2248 }
2249
86271e46 2250 for (j = 0; j < timeout; j++) {
108697c4 2251 bool npend = false;
86271e46
FF
2252
2253 if (j)
2254 usleep_range(1000, 2000);
69081624 2255
86271e46
FF
2256 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2257 if (!ATH_TXQ_SETUP(sc, i))
2258 continue;
2259
108697c4
MSS
2260 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2261
2262 if (npend)
2263 break;
69081624 2264 }
86271e46
FF
2265
2266 if (!npend)
9df0d6a2 2267 break;
69081624
VT
2268 }
2269
9df0d6a2
FF
2270 if (drop) {
2271 ath9k_ps_wakeup(sc);
2272 spin_lock_bh(&sc->sc_pcu_lock);
2273 drain_txq = ath_drain_all_txq(sc, false);
2274 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 2275
9df0d6a2
FF
2276 if (!drain_txq)
2277 ath_reset(sc, false);
9adcf440 2278
9df0d6a2
FF
2279 ath9k_ps_restore(sc);
2280 ieee80211_wake_queues(hw);
2281 }
d78f4b3e 2282
69081624
VT
2283 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2284 mutex_unlock(&sc->mutex);
2285}
2286
15b91e83
VN
2287static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2288{
2289 struct ath_softc *sc = hw->priv;
2290 int i;
2291
2292 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2293 if (!ATH_TXQ_SETUP(sc, i))
2294 continue;
2295
2296 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2297 return true;
2298 }
2299 return false;
2300}
2301
5595f119 2302static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
2303{
2304 struct ath_softc *sc = hw->priv;
2305 struct ath_hw *ah = sc->sc_ah;
2306 struct ieee80211_vif *vif;
2307 struct ath_vif *avp;
2308 struct ath_buf *bf;
2309 struct ath_tx_status ts;
4286df60 2310 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF
2311 int status;
2312
2313 vif = sc->beacon.bslot[0];
2314 if (!vif)
2315 return 0;
2316
2317 avp = (void *)vif->drv_priv;
2318 if (!avp->is_bslot_active)
2319 return 0;
2320
4286df60 2321 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF
2322 tasklet_disable(&sc->bcon_tasklet);
2323
2324 bf = avp->av_bcbuf;
2325 if (!bf || !bf->bf_mpdu)
2326 goto skip;
2327
2328 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2329 if (status == -EINPROGRESS)
2330 goto skip;
2331
2332 sc->beacon.tx_processed = true;
2333 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2334
2335skip:
2336 tasklet_enable(&sc->bcon_tasklet);
2337 }
2338
2339 return sc->beacon.tx_last;
2340}
2341
52c94f41
MSS
2342static int ath9k_get_stats(struct ieee80211_hw *hw,
2343 struct ieee80211_low_level_stats *stats)
2344{
2345 struct ath_softc *sc = hw->priv;
2346 struct ath_hw *ah = sc->sc_ah;
2347 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2348
2349 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2350 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2351 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2352 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2353 return 0;
2354}
2355
43c35284
FF
2356static u32 fill_chainmask(u32 cap, u32 new)
2357{
2358 u32 filled = 0;
2359 int i;
2360
2361 for (i = 0; cap && new; i++, cap >>= 1) {
2362 if (!(cap & BIT(0)))
2363 continue;
2364
2365 if (new & BIT(0))
2366 filled |= BIT(i);
2367
2368 new >>= 1;
2369 }
2370
2371 return filled;
2372}
2373
2374static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2375{
2376 struct ath_softc *sc = hw->priv;
2377 struct ath_hw *ah = sc->sc_ah;
2378
2379 if (!rx_ant || !tx_ant)
2380 return -EINVAL;
2381
2382 sc->ant_rx = rx_ant;
2383 sc->ant_tx = tx_ant;
2384
2385 if (ah->caps.rx_chainmask == 1)
2386 return 0;
2387
2388 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2389 if (AR_SREV_9100(ah))
2390 ah->rxchainmask = 0x7;
2391 else
2392 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2393
2394 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2395 ath9k_reload_chainmask_settings(sc);
2396
2397 return 0;
2398}
2399
2400static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2401{
2402 struct ath_softc *sc = hw->priv;
2403
2404 *tx_ant = sc->ant_tx;
2405 *rx_ant = sc->ant_rx;
2406 return 0;
2407}
2408
6baff7f9 2409struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2410 .tx = ath9k_tx,
2411 .start = ath9k_start,
2412 .stop = ath9k_stop,
2413 .add_interface = ath9k_add_interface,
6b3b991d 2414 .change_interface = ath9k_change_interface,
8feceb67
VT
2415 .remove_interface = ath9k_remove_interface,
2416 .config = ath9k_config,
8feceb67 2417 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2418 .sta_add = ath9k_sta_add,
2419 .sta_remove = ath9k_sta_remove,
5519541d 2420 .sta_notify = ath9k_sta_notify,
8feceb67 2421 .conf_tx = ath9k_conf_tx,
8feceb67 2422 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2423 .set_key = ath9k_set_key,
8feceb67 2424 .get_tsf = ath9k_get_tsf,
3b5d665b 2425 .set_tsf = ath9k_set_tsf,
8feceb67 2426 .reset_tsf = ath9k_reset_tsf,
4233df6b 2427 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2428 .get_survey = ath9k_get_survey,
3b319aae 2429 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2430 .set_coverage_class = ath9k_set_coverage_class,
69081624 2431 .flush = ath9k_flush,
15b91e83 2432 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41
MSS
2433 .tx_last_beacon = ath9k_tx_last_beacon,
2434 .get_stats = ath9k_get_stats,
43c35284
FF
2435 .set_antenna = ath9k_set_antenna,
2436 .get_antenna = ath9k_get_antenna,
8feceb67 2437};
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