Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
f078f209 | 19 | |
f078f209 LR |
20 | static char *dev_info = "ath9k"; |
21 | ||
22 | MODULE_AUTHOR("Atheros Communications"); | |
23 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
24 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
25 | MODULE_LICENSE("Dual BSD/GPL"); | |
26 | ||
b3bd89ce JM |
27 | static int modparam_nohwcrypt; |
28 | module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); | |
29 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); | |
30 | ||
5f8e077c LR |
31 | /* We use the hw_value as an index into our private channel structure */ |
32 | ||
33 | #define CHAN2G(_freq, _idx) { \ | |
34 | .center_freq = (_freq), \ | |
35 | .hw_value = (_idx), \ | |
eeddfd9d | 36 | .max_power = 20, \ |
5f8e077c LR |
37 | } |
38 | ||
39 | #define CHAN5G(_freq, _idx) { \ | |
40 | .band = IEEE80211_BAND_5GHZ, \ | |
41 | .center_freq = (_freq), \ | |
42 | .hw_value = (_idx), \ | |
eeddfd9d | 43 | .max_power = 20, \ |
5f8e077c LR |
44 | } |
45 | ||
46 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
47 | * on 5 MHz steps, we support the channels which we know | |
48 | * we have calibration data for all cards though to make | |
49 | * this static */ | |
50 | static struct ieee80211_channel ath9k_2ghz_chantable[] = { | |
51 | CHAN2G(2412, 0), /* Channel 1 */ | |
52 | CHAN2G(2417, 1), /* Channel 2 */ | |
53 | CHAN2G(2422, 2), /* Channel 3 */ | |
54 | CHAN2G(2427, 3), /* Channel 4 */ | |
55 | CHAN2G(2432, 4), /* Channel 5 */ | |
56 | CHAN2G(2437, 5), /* Channel 6 */ | |
57 | CHAN2G(2442, 6), /* Channel 7 */ | |
58 | CHAN2G(2447, 7), /* Channel 8 */ | |
59 | CHAN2G(2452, 8), /* Channel 9 */ | |
60 | CHAN2G(2457, 9), /* Channel 10 */ | |
61 | CHAN2G(2462, 10), /* Channel 11 */ | |
62 | CHAN2G(2467, 11), /* Channel 12 */ | |
63 | CHAN2G(2472, 12), /* Channel 13 */ | |
64 | CHAN2G(2484, 13), /* Channel 14 */ | |
65 | }; | |
66 | ||
67 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
68 | * on 5 MHz steps, we support the channels which we know | |
69 | * we have calibration data for all cards though to make | |
70 | * this static */ | |
71 | static struct ieee80211_channel ath9k_5ghz_chantable[] = { | |
72 | /* _We_ call this UNII 1 */ | |
73 | CHAN5G(5180, 14), /* Channel 36 */ | |
74 | CHAN5G(5200, 15), /* Channel 40 */ | |
75 | CHAN5G(5220, 16), /* Channel 44 */ | |
76 | CHAN5G(5240, 17), /* Channel 48 */ | |
77 | /* _We_ call this UNII 2 */ | |
78 | CHAN5G(5260, 18), /* Channel 52 */ | |
79 | CHAN5G(5280, 19), /* Channel 56 */ | |
80 | CHAN5G(5300, 20), /* Channel 60 */ | |
81 | CHAN5G(5320, 21), /* Channel 64 */ | |
82 | /* _We_ call this "Middle band" */ | |
83 | CHAN5G(5500, 22), /* Channel 100 */ | |
84 | CHAN5G(5520, 23), /* Channel 104 */ | |
85 | CHAN5G(5540, 24), /* Channel 108 */ | |
86 | CHAN5G(5560, 25), /* Channel 112 */ | |
87 | CHAN5G(5580, 26), /* Channel 116 */ | |
88 | CHAN5G(5600, 27), /* Channel 120 */ | |
89 | CHAN5G(5620, 28), /* Channel 124 */ | |
90 | CHAN5G(5640, 29), /* Channel 128 */ | |
91 | CHAN5G(5660, 30), /* Channel 132 */ | |
92 | CHAN5G(5680, 31), /* Channel 136 */ | |
93 | CHAN5G(5700, 32), /* Channel 140 */ | |
94 | /* _We_ call this UNII 3 */ | |
95 | CHAN5G(5745, 33), /* Channel 149 */ | |
96 | CHAN5G(5765, 34), /* Channel 153 */ | |
97 | CHAN5G(5785, 35), /* Channel 157 */ | |
98 | CHAN5G(5805, 36), /* Channel 161 */ | |
99 | CHAN5G(5825, 37), /* Channel 165 */ | |
100 | }; | |
101 | ||
ce111bad LR |
102 | static void ath_cache_conf_rate(struct ath_softc *sc, |
103 | struct ieee80211_conf *conf) | |
ff37e337 | 104 | { |
030bb495 LR |
105 | switch (conf->channel->band) { |
106 | case IEEE80211_BAND_2GHZ: | |
107 | if (conf_is_ht20(conf)) | |
108 | sc->cur_rate_table = | |
109 | sc->hw_rate_table[ATH9K_MODE_11NG_HT20]; | |
110 | else if (conf_is_ht40_minus(conf)) | |
111 | sc->cur_rate_table = | |
112 | sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS]; | |
113 | else if (conf_is_ht40_plus(conf)) | |
114 | sc->cur_rate_table = | |
115 | sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS]; | |
96742256 | 116 | else |
030bb495 LR |
117 | sc->cur_rate_table = |
118 | sc->hw_rate_table[ATH9K_MODE_11G]; | |
030bb495 LR |
119 | break; |
120 | case IEEE80211_BAND_5GHZ: | |
121 | if (conf_is_ht20(conf)) | |
122 | sc->cur_rate_table = | |
123 | sc->hw_rate_table[ATH9K_MODE_11NA_HT20]; | |
124 | else if (conf_is_ht40_minus(conf)) | |
125 | sc->cur_rate_table = | |
126 | sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS]; | |
127 | else if (conf_is_ht40_plus(conf)) | |
128 | sc->cur_rate_table = | |
129 | sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS]; | |
130 | else | |
96742256 LR |
131 | sc->cur_rate_table = |
132 | sc->hw_rate_table[ATH9K_MODE_11A]; | |
030bb495 LR |
133 | break; |
134 | default: | |
ce111bad | 135 | BUG_ON(1); |
030bb495 LR |
136 | break; |
137 | } | |
ff37e337 S |
138 | } |
139 | ||
140 | static void ath_update_txpow(struct ath_softc *sc) | |
141 | { | |
cbe61d8a | 142 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
143 | u32 txpow; |
144 | ||
17d7904d S |
145 | if (sc->curtxpow != sc->config.txpowlimit) { |
146 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 S |
147 | /* read back in case value is clamped */ |
148 | ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow); | |
17d7904d | 149 | sc->curtxpow = txpow; |
ff37e337 S |
150 | } |
151 | } | |
152 | ||
153 | static u8 parse_mpdudensity(u8 mpdudensity) | |
154 | { | |
155 | /* | |
156 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
157 | * 0 for no restriction | |
158 | * 1 for 1/4 us | |
159 | * 2 for 1/2 us | |
160 | * 3 for 1 us | |
161 | * 4 for 2 us | |
162 | * 5 for 4 us | |
163 | * 6 for 8 us | |
164 | * 7 for 16 us | |
165 | */ | |
166 | switch (mpdudensity) { | |
167 | case 0: | |
168 | return 0; | |
169 | case 1: | |
170 | case 2: | |
171 | case 3: | |
172 | /* Our lower layer calculations limit our precision to | |
173 | 1 microsecond */ | |
174 | return 1; | |
175 | case 4: | |
176 | return 2; | |
177 | case 5: | |
178 | return 4; | |
179 | case 6: | |
180 | return 8; | |
181 | case 7: | |
182 | return 16; | |
183 | default: | |
184 | return 0; | |
185 | } | |
186 | } | |
187 | ||
188 | static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band) | |
189 | { | |
4f0fc7c3 | 190 | const struct ath_rate_table *rate_table = NULL; |
ff37e337 S |
191 | struct ieee80211_supported_band *sband; |
192 | struct ieee80211_rate *rate; | |
193 | int i, maxrates; | |
194 | ||
195 | switch (band) { | |
196 | case IEEE80211_BAND_2GHZ: | |
197 | rate_table = sc->hw_rate_table[ATH9K_MODE_11G]; | |
198 | break; | |
199 | case IEEE80211_BAND_5GHZ: | |
200 | rate_table = sc->hw_rate_table[ATH9K_MODE_11A]; | |
201 | break; | |
202 | default: | |
203 | break; | |
204 | } | |
205 | ||
206 | if (rate_table == NULL) | |
207 | return; | |
208 | ||
209 | sband = &sc->sbands[band]; | |
210 | rate = sc->rates[band]; | |
211 | ||
212 | if (rate_table->rate_cnt > ATH_RATE_MAX) | |
213 | maxrates = ATH_RATE_MAX; | |
214 | else | |
215 | maxrates = rate_table->rate_cnt; | |
216 | ||
217 | for (i = 0; i < maxrates; i++) { | |
218 | rate[i].bitrate = rate_table->info[i].ratekbps / 100; | |
219 | rate[i].hw_value = rate_table->info[i].ratecode; | |
f46730d1 S |
220 | if (rate_table->info[i].short_preamble) { |
221 | rate[i].hw_value_short = rate_table->info[i].ratecode | | |
222 | rate_table->info[i].short_preamble; | |
223 | rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE; | |
224 | } | |
ff37e337 | 225 | sband->n_bitrates++; |
f46730d1 | 226 | |
04bd4638 S |
227 | DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n", |
228 | rate[i].bitrate / 10, rate[i].hw_value); | |
ff37e337 S |
229 | } |
230 | } | |
231 | ||
82880a7c VT |
232 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
233 | struct ieee80211_hw *hw) | |
234 | { | |
235 | struct ieee80211_channel *curchan = hw->conf.channel; | |
236 | struct ath9k_channel *channel; | |
237 | u8 chan_idx; | |
238 | ||
239 | chan_idx = curchan->hw_value; | |
240 | channel = &sc->sc_ah->channels[chan_idx]; | |
241 | ath9k_update_ichannel(sc, hw, channel); | |
242 | return channel; | |
243 | } | |
244 | ||
ff37e337 S |
245 | /* |
246 | * Set/change channels. If the channel is really being changed, it's done | |
247 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
248 | * DMA, then restart stuff. | |
249 | */ | |
0e2dedf9 JM |
250 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
251 | struct ath9k_channel *hchan) | |
ff37e337 | 252 | { |
cbe61d8a | 253 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 | 254 | bool fastcc = true, stopped; |
ae8d2858 LR |
255 | struct ieee80211_channel *channel = hw->conf.channel; |
256 | int r; | |
ff37e337 S |
257 | |
258 | if (sc->sc_flags & SC_OP_INVALID) | |
259 | return -EIO; | |
260 | ||
3cbb5dd7 VN |
261 | ath9k_ps_wakeup(sc); |
262 | ||
c0d7c7af LR |
263 | /* |
264 | * This is only performed if the channel settings have | |
265 | * actually changed. | |
266 | * | |
267 | * To switch channels clear any pending DMA operations; | |
268 | * wait long enough for the RX fifo to drain, reset the | |
269 | * hardware at the new frequency, and then re-enable | |
270 | * the relevant bits of the h/w. | |
271 | */ | |
272 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 273 | ath_drain_all_txq(sc, false); |
c0d7c7af | 274 | stopped = ath_stoprecv(sc); |
ff37e337 | 275 | |
c0d7c7af LR |
276 | /* XXX: do not flush receive queue here. We don't want |
277 | * to flush data frames already in queue because of | |
278 | * changing channel. */ | |
ff37e337 | 279 | |
c0d7c7af LR |
280 | if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) |
281 | fastcc = false; | |
282 | ||
283 | DPRINTF(sc, ATH_DBG_CONFIG, | |
284 | "(%u MHz) -> (%u MHz), chanwidth: %d\n", | |
2660b81a | 285 | sc->sc_ah->curchan->channel, |
c0d7c7af | 286 | channel->center_freq, sc->tx_chan_width); |
ff37e337 | 287 | |
c0d7c7af LR |
288 | spin_lock_bh(&sc->sc_resetlock); |
289 | ||
290 | r = ath9k_hw_reset(ah, hchan, fastcc); | |
291 | if (r) { | |
292 | DPRINTF(sc, ATH_DBG_FATAL, | |
293 | "Unable to reset channel (%u Mhz) " | |
6b45784f | 294 | "reset status %d\n", |
c0d7c7af LR |
295 | channel->center_freq, r); |
296 | spin_unlock_bh(&sc->sc_resetlock); | |
3989279c | 297 | goto ps_restore; |
ff37e337 | 298 | } |
c0d7c7af LR |
299 | spin_unlock_bh(&sc->sc_resetlock); |
300 | ||
c0d7c7af LR |
301 | sc->sc_flags &= ~SC_OP_FULL_RESET; |
302 | ||
303 | if (ath_startrecv(sc) != 0) { | |
304 | DPRINTF(sc, ATH_DBG_FATAL, | |
305 | "Unable to restart recv logic\n"); | |
3989279c GJ |
306 | r = -EIO; |
307 | goto ps_restore; | |
c0d7c7af LR |
308 | } |
309 | ||
310 | ath_cache_conf_rate(sc, &hw->conf); | |
311 | ath_update_txpow(sc); | |
17d7904d | 312 | ath9k_hw_set_interrupts(ah, sc->imask); |
3989279c GJ |
313 | |
314 | ps_restore: | |
3cbb5dd7 | 315 | ath9k_ps_restore(sc); |
3989279c | 316 | return r; |
ff37e337 S |
317 | } |
318 | ||
319 | /* | |
320 | * This routine performs the periodic noise floor calibration function | |
321 | * that is used to adjust and optimize the chip performance. This | |
322 | * takes environmental changes (location, temperature) into account. | |
323 | * When the task is complete, it reschedules itself depending on the | |
324 | * appropriate interval that was calculated. | |
325 | */ | |
326 | static void ath_ani_calibrate(unsigned long data) | |
327 | { | |
20977d3e S |
328 | struct ath_softc *sc = (struct ath_softc *)data; |
329 | struct ath_hw *ah = sc->sc_ah; | |
ff37e337 S |
330 | bool longcal = false; |
331 | bool shortcal = false; | |
332 | bool aniflag = false; | |
333 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
20977d3e | 334 | u32 cal_interval, short_cal_interval; |
ff37e337 | 335 | |
20977d3e S |
336 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
337 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 S |
338 | |
339 | /* | |
340 | * don't calibrate when we're scanning. | |
341 | * we are most likely not on our home channel. | |
342 | */ | |
e5f0921a | 343 | spin_lock(&sc->ani_lock); |
0c98de65 | 344 | if (sc->sc_flags & SC_OP_SCANNING) |
20977d3e | 345 | goto set_timer; |
ff37e337 | 346 | |
1ffc1c61 JM |
347 | /* Only calibrate if awake */ |
348 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
349 | goto set_timer; | |
350 | ||
351 | ath9k_ps_wakeup(sc); | |
352 | ||
ff37e337 | 353 | /* Long calibration runs independently of short calibration. */ |
17d7904d | 354 | if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { |
ff37e337 | 355 | longcal = true; |
04bd4638 | 356 | DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
17d7904d | 357 | sc->ani.longcal_timer = timestamp; |
ff37e337 S |
358 | } |
359 | ||
17d7904d S |
360 | /* Short calibration applies only while caldone is false */ |
361 | if (!sc->ani.caldone) { | |
20977d3e | 362 | if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) { |
ff37e337 | 363 | shortcal = true; |
04bd4638 | 364 | DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies); |
17d7904d S |
365 | sc->ani.shortcal_timer = timestamp; |
366 | sc->ani.resetcal_timer = timestamp; | |
ff37e337 S |
367 | } |
368 | } else { | |
17d7904d | 369 | if ((timestamp - sc->ani.resetcal_timer) >= |
ff37e337 | 370 | ATH_RESTART_CALINTERVAL) { |
17d7904d S |
371 | sc->ani.caldone = ath9k_hw_reset_calvalid(ah); |
372 | if (sc->ani.caldone) | |
373 | sc->ani.resetcal_timer = timestamp; | |
ff37e337 S |
374 | } |
375 | } | |
376 | ||
377 | /* Verify whether we must check ANI */ | |
20977d3e | 378 | if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) { |
ff37e337 | 379 | aniflag = true; |
17d7904d | 380 | sc->ani.checkani_timer = timestamp; |
ff37e337 S |
381 | } |
382 | ||
383 | /* Skip all processing if there's nothing to do. */ | |
384 | if (longcal || shortcal || aniflag) { | |
385 | /* Call ANI routine if necessary */ | |
386 | if (aniflag) | |
20977d3e | 387 | ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan); |
ff37e337 S |
388 | |
389 | /* Perform calibration if necessary */ | |
390 | if (longcal || shortcal) { | |
379f0440 S |
391 | sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan, |
392 | sc->rx_chainmask, longcal); | |
393 | ||
394 | if (longcal) | |
395 | sc->ani.noise_floor = ath9k_hw_getchan_noise(ah, | |
396 | ah->curchan); | |
397 | ||
398 | DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n", | |
399 | ah->curchan->channel, ah->curchan->channelFlags, | |
400 | sc->ani.noise_floor); | |
ff37e337 S |
401 | } |
402 | } | |
403 | ||
1ffc1c61 JM |
404 | ath9k_ps_restore(sc); |
405 | ||
20977d3e | 406 | set_timer: |
e5f0921a | 407 | spin_unlock(&sc->ani_lock); |
ff37e337 S |
408 | /* |
409 | * Set timer interval based on previous results. | |
410 | * The interval must be the shortest necessary to satisfy ANI, | |
411 | * short calibration and long calibration. | |
412 | */ | |
aac9207e | 413 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 414 | if (sc->sc_ah->config.enable_ani) |
aac9207e | 415 | cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); |
17d7904d | 416 | if (!sc->ani.caldone) |
20977d3e | 417 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 418 | |
17d7904d | 419 | mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
ff37e337 S |
420 | } |
421 | ||
415f738e S |
422 | static void ath_start_ani(struct ath_softc *sc) |
423 | { | |
424 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
425 | ||
426 | sc->ani.longcal_timer = timestamp; | |
427 | sc->ani.shortcal_timer = timestamp; | |
428 | sc->ani.checkani_timer = timestamp; | |
429 | ||
430 | mod_timer(&sc->ani.timer, | |
431 | jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); | |
432 | } | |
433 | ||
ff37e337 S |
434 | /* |
435 | * Update tx/rx chainmask. For legacy association, | |
436 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
437 | * the chainmask configuration, for bt coexistence, use |
438 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 439 | */ |
0e2dedf9 | 440 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 441 | { |
c97c92d9 | 442 | if (is_ht || |
2660b81a S |
443 | (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) { |
444 | sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask; | |
445 | sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask; | |
ff37e337 | 446 | } else { |
17d7904d S |
447 | sc->tx_chainmask = 1; |
448 | sc->rx_chainmask = 1; | |
ff37e337 S |
449 | } |
450 | ||
04bd4638 | 451 | DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n", |
17d7904d | 452 | sc->tx_chainmask, sc->rx_chainmask); |
ff37e337 S |
453 | } |
454 | ||
455 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
456 | { | |
457 | struct ath_node *an; | |
458 | ||
459 | an = (struct ath_node *)sta->drv_priv; | |
460 | ||
87792efc | 461 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 462 | ath_tx_node_init(sc, an); |
9e98ac65 | 463 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
464 | sta->ht_cap.ampdu_factor); |
465 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
a59b5a5e | 466 | an->last_rssi = ATH_RSSI_DUMMY_MARKER; |
87792efc | 467 | } |
ff37e337 S |
468 | } |
469 | ||
470 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
471 | { | |
472 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
473 | ||
474 | if (sc->sc_flags & SC_OP_TXAGGR) | |
475 | ath_tx_node_cleanup(sc, an); | |
476 | } | |
477 | ||
478 | static void ath9k_tasklet(unsigned long data) | |
479 | { | |
480 | struct ath_softc *sc = (struct ath_softc *)data; | |
17d7904d | 481 | u32 status = sc->intrstatus; |
ff37e337 | 482 | |
153e080d VT |
483 | ath9k_ps_wakeup(sc); |
484 | ||
ff37e337 | 485 | if (status & ATH9K_INT_FATAL) { |
ff37e337 | 486 | ath_reset(sc, false); |
153e080d | 487 | ath9k_ps_restore(sc); |
ff37e337 | 488 | return; |
063d8be3 | 489 | } |
ff37e337 | 490 | |
063d8be3 S |
491 | if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) { |
492 | spin_lock_bh(&sc->rx.rxflushlock); | |
493 | ath_rx_tasklet(sc, 0); | |
494 | spin_unlock_bh(&sc->rx.rxflushlock); | |
ff37e337 S |
495 | } |
496 | ||
063d8be3 S |
497 | if (status & ATH9K_INT_TX) |
498 | ath_tx_tasklet(sc); | |
499 | ||
96148326 | 500 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
501 | /* |
502 | * TSF sync does not look correct; remain awake to sync with | |
503 | * the next Beacon. | |
504 | */ | |
505 | DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n"); | |
ccdfeab6 | 506 | sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC; |
54ce846e JM |
507 | } |
508 | ||
ff37e337 | 509 | /* re-enable hardware interrupt */ |
17d7904d | 510 | ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); |
153e080d | 511 | ath9k_ps_restore(sc); |
ff37e337 S |
512 | } |
513 | ||
6baff7f9 | 514 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 515 | { |
063d8be3 S |
516 | #define SCHED_INTR ( \ |
517 | ATH9K_INT_FATAL | \ | |
518 | ATH9K_INT_RXORN | \ | |
519 | ATH9K_INT_RXEOL | \ | |
520 | ATH9K_INT_RX | \ | |
521 | ATH9K_INT_TX | \ | |
522 | ATH9K_INT_BMISS | \ | |
523 | ATH9K_INT_CST | \ | |
524 | ATH9K_INT_TSFOOR) | |
525 | ||
ff37e337 | 526 | struct ath_softc *sc = dev; |
cbe61d8a | 527 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
528 | enum ath9k_int status; |
529 | bool sched = false; | |
530 | ||
063d8be3 S |
531 | /* |
532 | * The hardware is not ready/present, don't | |
533 | * touch anything. Note this can happen early | |
534 | * on if the IRQ is shared. | |
535 | */ | |
536 | if (sc->sc_flags & SC_OP_INVALID) | |
537 | return IRQ_NONE; | |
ff37e337 | 538 | |
063d8be3 S |
539 | |
540 | /* shared irq, not for us */ | |
541 | ||
153e080d | 542 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 543 | return IRQ_NONE; |
063d8be3 S |
544 | |
545 | /* | |
546 | * Figure out the reason(s) for the interrupt. Note | |
547 | * that the hal returns a pseudo-ISR that may include | |
548 | * bits we haven't explicitly enabled so we mask the | |
549 | * value to insure we only process bits we requested. | |
550 | */ | |
551 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
552 | status &= sc->imask; /* discard unasked-for bits */ | |
ff37e337 | 553 | |
063d8be3 S |
554 | /* |
555 | * If there are no status bits set, then this interrupt was not | |
556 | * for me (should have been caught above). | |
557 | */ | |
153e080d | 558 | if (!status) |
063d8be3 | 559 | return IRQ_NONE; |
ff37e337 | 560 | |
063d8be3 S |
561 | /* Cache the status */ |
562 | sc->intrstatus = status; | |
563 | ||
564 | if (status & SCHED_INTR) | |
565 | sched = true; | |
566 | ||
567 | /* | |
568 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
569 | * chip immediately. | |
570 | */ | |
571 | if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN)) | |
572 | goto chip_reset; | |
573 | ||
574 | if (status & ATH9K_INT_SWBA) | |
575 | tasklet_schedule(&sc->bcon_tasklet); | |
576 | ||
577 | if (status & ATH9K_INT_TXURN) | |
578 | ath9k_hw_updatetxtriglevel(ah, true); | |
579 | ||
580 | if (status & ATH9K_INT_MIB) { | |
ff37e337 | 581 | /* |
063d8be3 S |
582 | * Disable interrupts until we service the MIB |
583 | * interrupt; otherwise it will continue to | |
584 | * fire. | |
ff37e337 | 585 | */ |
063d8be3 S |
586 | ath9k_hw_set_interrupts(ah, 0); |
587 | /* | |
588 | * Let the hal handle the event. We assume | |
589 | * it will clear whatever condition caused | |
590 | * the interrupt. | |
591 | */ | |
592 | ath9k_hw_procmibevent(ah, &sc->nodestats); | |
593 | ath9k_hw_set_interrupts(ah, sc->imask); | |
594 | } | |
ff37e337 | 595 | |
153e080d VT |
596 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
597 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
598 | /* Clear RxAbort bit so that we can |
599 | * receive frames */ | |
600 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
153e080d | 601 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
063d8be3 | 602 | sc->sc_flags |= SC_OP_WAIT_FOR_BEACON; |
ff37e337 | 603 | } |
063d8be3 S |
604 | |
605 | chip_reset: | |
ff37e337 | 606 | |
817e11de S |
607 | ath_debug_stat_interrupt(sc, status); |
608 | ||
ff37e337 S |
609 | if (sched) { |
610 | /* turn off every interrupt except SWBA */ | |
17d7904d | 611 | ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
612 | tasklet_schedule(&sc->intr_tq); |
613 | } | |
614 | ||
615 | return IRQ_HANDLED; | |
063d8be3 S |
616 | |
617 | #undef SCHED_INTR | |
ff37e337 S |
618 | } |
619 | ||
f078f209 | 620 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 621 | struct ieee80211_channel *chan, |
094d05dc | 622 | enum nl80211_channel_type channel_type) |
f078f209 LR |
623 | { |
624 | u32 chanmode = 0; | |
f078f209 LR |
625 | |
626 | switch (chan->band) { | |
627 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
628 | switch(channel_type) { |
629 | case NL80211_CHAN_NO_HT: | |
630 | case NL80211_CHAN_HT20: | |
f078f209 | 631 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
632 | break; |
633 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 634 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
635 | break; |
636 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 637 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
638 | break; |
639 | } | |
f078f209 LR |
640 | break; |
641 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
642 | switch(channel_type) { |
643 | case NL80211_CHAN_NO_HT: | |
644 | case NL80211_CHAN_HT20: | |
f078f209 | 645 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
646 | break; |
647 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 648 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
649 | break; |
650 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 651 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
652 | break; |
653 | } | |
f078f209 LR |
654 | break; |
655 | default: | |
656 | break; | |
657 | } | |
658 | ||
659 | return chanmode; | |
660 | } | |
661 | ||
6ace2891 | 662 | static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key, |
3f53dd64 JM |
663 | struct ath9k_keyval *hk, const u8 *addr, |
664 | bool authenticator) | |
f078f209 | 665 | { |
6ace2891 JM |
666 | const u8 *key_rxmic; |
667 | const u8 *key_txmic; | |
f078f209 | 668 | |
6ace2891 JM |
669 | key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY; |
670 | key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY; | |
f078f209 LR |
671 | |
672 | if (addr == NULL) { | |
d216aaa6 JM |
673 | /* |
674 | * Group key installation - only two key cache entries are used | |
675 | * regardless of splitmic capability since group key is only | |
676 | * used either for TX or RX. | |
677 | */ | |
3f53dd64 JM |
678 | if (authenticator) { |
679 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); | |
680 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic)); | |
681 | } else { | |
682 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
683 | memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic)); | |
684 | } | |
d216aaa6 | 685 | return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr); |
f078f209 | 686 | } |
17d7904d | 687 | if (!sc->splitmic) { |
d216aaa6 | 688 | /* TX and RX keys share the same key cache entry. */ |
f078f209 LR |
689 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); |
690 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic)); | |
d216aaa6 | 691 | return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr); |
f078f209 | 692 | } |
d216aaa6 JM |
693 | |
694 | /* Separate key cache entries for TX and RX */ | |
695 | ||
696 | /* TX key goes at first index, RX key at +32. */ | |
f078f209 | 697 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); |
d216aaa6 JM |
698 | if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) { |
699 | /* TX MIC entry failed. No need to proceed further */ | |
d8baa939 | 700 | DPRINTF(sc, ATH_DBG_FATAL, |
04bd4638 | 701 | "Setting TX MIC Key Failed\n"); |
f078f209 LR |
702 | return 0; |
703 | } | |
704 | ||
705 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
706 | /* XXX delete tx key on failure? */ | |
d216aaa6 | 707 | return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr); |
6ace2891 JM |
708 | } |
709 | ||
710 | static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc) | |
711 | { | |
712 | int i; | |
713 | ||
17d7904d S |
714 | for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) { |
715 | if (test_bit(i, sc->keymap) || | |
716 | test_bit(i + 64, sc->keymap)) | |
6ace2891 | 717 | continue; /* At least one part of TKIP key allocated */ |
17d7904d S |
718 | if (sc->splitmic && |
719 | (test_bit(i + 32, sc->keymap) || | |
720 | test_bit(i + 64 + 32, sc->keymap))) | |
6ace2891 JM |
721 | continue; /* At least one part of TKIP key allocated */ |
722 | ||
723 | /* Found a free slot for a TKIP key */ | |
724 | return i; | |
725 | } | |
726 | return -1; | |
727 | } | |
728 | ||
729 | static int ath_reserve_key_cache_slot(struct ath_softc *sc) | |
730 | { | |
731 | int i; | |
732 | ||
733 | /* First, try to find slots that would not be available for TKIP. */ | |
17d7904d S |
734 | if (sc->splitmic) { |
735 | for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) { | |
736 | if (!test_bit(i, sc->keymap) && | |
737 | (test_bit(i + 32, sc->keymap) || | |
738 | test_bit(i + 64, sc->keymap) || | |
739 | test_bit(i + 64 + 32, sc->keymap))) | |
6ace2891 | 740 | return i; |
17d7904d S |
741 | if (!test_bit(i + 32, sc->keymap) && |
742 | (test_bit(i, sc->keymap) || | |
743 | test_bit(i + 64, sc->keymap) || | |
744 | test_bit(i + 64 + 32, sc->keymap))) | |
6ace2891 | 745 | return i + 32; |
17d7904d S |
746 | if (!test_bit(i + 64, sc->keymap) && |
747 | (test_bit(i , sc->keymap) || | |
748 | test_bit(i + 32, sc->keymap) || | |
749 | test_bit(i + 64 + 32, sc->keymap))) | |
ea612132 | 750 | return i + 64; |
17d7904d S |
751 | if (!test_bit(i + 64 + 32, sc->keymap) && |
752 | (test_bit(i, sc->keymap) || | |
753 | test_bit(i + 32, sc->keymap) || | |
754 | test_bit(i + 64, sc->keymap))) | |
ea612132 | 755 | return i + 64 + 32; |
6ace2891 JM |
756 | } |
757 | } else { | |
17d7904d S |
758 | for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) { |
759 | if (!test_bit(i, sc->keymap) && | |
760 | test_bit(i + 64, sc->keymap)) | |
6ace2891 | 761 | return i; |
17d7904d S |
762 | if (test_bit(i, sc->keymap) && |
763 | !test_bit(i + 64, sc->keymap)) | |
6ace2891 JM |
764 | return i + 64; |
765 | } | |
766 | } | |
767 | ||
768 | /* No partially used TKIP slots, pick any available slot */ | |
17d7904d | 769 | for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) { |
be2864cf JM |
770 | /* Do not allow slots that could be needed for TKIP group keys |
771 | * to be used. This limitation could be removed if we know that | |
772 | * TKIP will not be used. */ | |
773 | if (i >= 64 && i < 64 + IEEE80211_WEP_NKID) | |
774 | continue; | |
17d7904d | 775 | if (sc->splitmic) { |
be2864cf JM |
776 | if (i >= 32 && i < 32 + IEEE80211_WEP_NKID) |
777 | continue; | |
778 | if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID) | |
779 | continue; | |
780 | } | |
781 | ||
17d7904d | 782 | if (!test_bit(i, sc->keymap)) |
6ace2891 JM |
783 | return i; /* Found a free slot for a key */ |
784 | } | |
785 | ||
786 | /* No free slot found */ | |
787 | return -1; | |
f078f209 LR |
788 | } |
789 | ||
790 | static int ath_key_config(struct ath_softc *sc, | |
3f53dd64 | 791 | struct ieee80211_vif *vif, |
dc822b5d | 792 | struct ieee80211_sta *sta, |
f078f209 LR |
793 | struct ieee80211_key_conf *key) |
794 | { | |
f078f209 LR |
795 | struct ath9k_keyval hk; |
796 | const u8 *mac = NULL; | |
797 | int ret = 0; | |
6ace2891 | 798 | int idx; |
f078f209 LR |
799 | |
800 | memset(&hk, 0, sizeof(hk)); | |
801 | ||
802 | switch (key->alg) { | |
803 | case ALG_WEP: | |
804 | hk.kv_type = ATH9K_CIPHER_WEP; | |
805 | break; | |
806 | case ALG_TKIP: | |
807 | hk.kv_type = ATH9K_CIPHER_TKIP; | |
808 | break; | |
809 | case ALG_CCMP: | |
810 | hk.kv_type = ATH9K_CIPHER_AES_CCM; | |
811 | break; | |
812 | default: | |
ca470b29 | 813 | return -EOPNOTSUPP; |
f078f209 LR |
814 | } |
815 | ||
6ace2891 | 816 | hk.kv_len = key->keylen; |
f078f209 LR |
817 | memcpy(hk.kv_val, key->key, key->keylen); |
818 | ||
6ace2891 JM |
819 | if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { |
820 | /* For now, use the default keys for broadcast keys. This may | |
821 | * need to change with virtual interfaces. */ | |
822 | idx = key->keyidx; | |
823 | } else if (key->keyidx) { | |
dc822b5d JB |
824 | if (WARN_ON(!sta)) |
825 | return -EOPNOTSUPP; | |
826 | mac = sta->addr; | |
827 | ||
6ace2891 JM |
828 | if (vif->type != NL80211_IFTYPE_AP) { |
829 | /* Only keyidx 0 should be used with unicast key, but | |
830 | * allow this for client mode for now. */ | |
831 | idx = key->keyidx; | |
832 | } else | |
833 | return -EIO; | |
f078f209 | 834 | } else { |
dc822b5d JB |
835 | if (WARN_ON(!sta)) |
836 | return -EOPNOTSUPP; | |
837 | mac = sta->addr; | |
838 | ||
6ace2891 JM |
839 | if (key->alg == ALG_TKIP) |
840 | idx = ath_reserve_key_cache_slot_tkip(sc); | |
841 | else | |
842 | idx = ath_reserve_key_cache_slot(sc); | |
843 | if (idx < 0) | |
ca470b29 | 844 | return -ENOSPC; /* no free key cache entries */ |
f078f209 LR |
845 | } |
846 | ||
847 | if (key->alg == ALG_TKIP) | |
3f53dd64 JM |
848 | ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac, |
849 | vif->type == NL80211_IFTYPE_AP); | |
f078f209 | 850 | else |
d216aaa6 | 851 | ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac); |
f078f209 LR |
852 | |
853 | if (!ret) | |
854 | return -EIO; | |
855 | ||
17d7904d | 856 | set_bit(idx, sc->keymap); |
6ace2891 | 857 | if (key->alg == ALG_TKIP) { |
17d7904d S |
858 | set_bit(idx + 64, sc->keymap); |
859 | if (sc->splitmic) { | |
860 | set_bit(idx + 32, sc->keymap); | |
861 | set_bit(idx + 64 + 32, sc->keymap); | |
6ace2891 JM |
862 | } |
863 | } | |
864 | ||
865 | return idx; | |
f078f209 LR |
866 | } |
867 | ||
868 | static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key) | |
869 | { | |
6ace2891 JM |
870 | ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx); |
871 | if (key->hw_key_idx < IEEE80211_WEP_NKID) | |
872 | return; | |
873 | ||
17d7904d | 874 | clear_bit(key->hw_key_idx, sc->keymap); |
6ace2891 JM |
875 | if (key->alg != ALG_TKIP) |
876 | return; | |
f078f209 | 877 | |
17d7904d S |
878 | clear_bit(key->hw_key_idx + 64, sc->keymap); |
879 | if (sc->splitmic) { | |
880 | clear_bit(key->hw_key_idx + 32, sc->keymap); | |
881 | clear_bit(key->hw_key_idx + 64 + 32, sc->keymap); | |
6ace2891 | 882 | } |
f078f209 LR |
883 | } |
884 | ||
eb2599ca S |
885 | static void setup_ht_cap(struct ath_softc *sc, |
886 | struct ieee80211_sta_ht_cap *ht_info) | |
f078f209 | 887 | { |
140add21 | 888 | u8 tx_streams, rx_streams; |
f078f209 | 889 | |
d9fe60de JB |
890 | ht_info->ht_supported = true; |
891 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
892 | IEEE80211_HT_CAP_SM_PS | | |
893 | IEEE80211_HT_CAP_SGI_40 | | |
894 | IEEE80211_HT_CAP_DSSSCCK40; | |
f078f209 | 895 | |
9e98ac65 S |
896 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
897 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
eb2599ca | 898 | |
d9fe60de JB |
899 | /* set up supported mcs set */ |
900 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
140add21 SB |
901 | tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2; |
902 | rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2; | |
903 | ||
904 | if (tx_streams != rx_streams) { | |
905 | DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n", | |
906 | tx_streams, rx_streams); | |
907 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; | |
908 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
909 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
910 | } | |
eb2599ca | 911 | |
140add21 SB |
912 | ht_info->mcs.rx_mask[0] = 0xff; |
913 | if (rx_streams >= 2) | |
eb2599ca | 914 | ht_info->mcs.rx_mask[1] = 0xff; |
eb2599ca | 915 | |
140add21 | 916 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; |
f078f209 LR |
917 | } |
918 | ||
8feceb67 | 919 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 920 | struct ieee80211_vif *vif, |
8feceb67 | 921 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 922 | { |
f078f209 | 923 | |
8feceb67 | 924 | if (bss_conf->assoc) { |
094d05dc | 925 | DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n", |
17d7904d | 926 | bss_conf->aid, sc->curbssid); |
f078f209 | 927 | |
8feceb67 | 928 | /* New association, store aid */ |
2664f201 SB |
929 | sc->curaid = bss_conf->aid; |
930 | ath9k_hw_write_associd(sc); | |
931 | ||
932 | /* | |
933 | * Request a re-configuration of Beacon related timers | |
934 | * on the receipt of the first Beacon frame (i.e., | |
935 | * after time sync with the AP). | |
936 | */ | |
937 | sc->sc_flags |= SC_OP_BEACON_SYNC; | |
f078f209 | 938 | |
8feceb67 | 939 | /* Configure the beacon */ |
2c3db3d5 | 940 | ath_beacon_config(sc, vif); |
f078f209 | 941 | |
8feceb67 | 942 | /* Reset rssi stats */ |
17d7904d S |
943 | sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; |
944 | sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; | |
945 | sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; | |
946 | sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER; | |
f078f209 | 947 | |
415f738e | 948 | ath_start_ani(sc); |
8feceb67 | 949 | } else { |
1ffb0610 | 950 | DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
17d7904d | 951 | sc->curaid = 0; |
f38faa31 SB |
952 | /* Stop ANI */ |
953 | del_timer_sync(&sc->ani.timer); | |
f078f209 | 954 | } |
8feceb67 | 955 | } |
f078f209 | 956 | |
8feceb67 VT |
957 | /********************************/ |
958 | /* LED functions */ | |
959 | /********************************/ | |
f078f209 | 960 | |
f2bffa7e VT |
961 | static void ath_led_blink_work(struct work_struct *work) |
962 | { | |
963 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
964 | ath_led_blink_work.work); | |
965 | ||
966 | if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED)) | |
967 | return; | |
85067c06 VT |
968 | |
969 | if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) || | |
970 | (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE)) | |
971 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0); | |
972 | else | |
973 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, | |
974 | (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0); | |
f2bffa7e | 975 | |
42935eca LR |
976 | ieee80211_queue_delayed_work(sc->hw, |
977 | &sc->ath_led_blink_work, | |
978 | (sc->sc_flags & SC_OP_LED_ON) ? | |
979 | msecs_to_jiffies(sc->led_off_duration) : | |
980 | msecs_to_jiffies(sc->led_on_duration)); | |
f2bffa7e | 981 | |
85067c06 VT |
982 | sc->led_on_duration = sc->led_on_cnt ? |
983 | max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) : | |
984 | ATH_LED_ON_DURATION_IDLE; | |
985 | sc->led_off_duration = sc->led_off_cnt ? | |
986 | max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) : | |
987 | ATH_LED_OFF_DURATION_IDLE; | |
f2bffa7e VT |
988 | sc->led_on_cnt = sc->led_off_cnt = 0; |
989 | if (sc->sc_flags & SC_OP_LED_ON) | |
990 | sc->sc_flags &= ~SC_OP_LED_ON; | |
991 | else | |
992 | sc->sc_flags |= SC_OP_LED_ON; | |
993 | } | |
994 | ||
8feceb67 VT |
995 | static void ath_led_brightness(struct led_classdev *led_cdev, |
996 | enum led_brightness brightness) | |
997 | { | |
998 | struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev); | |
999 | struct ath_softc *sc = led->sc; | |
f078f209 | 1000 | |
8feceb67 VT |
1001 | switch (brightness) { |
1002 | case LED_OFF: | |
1003 | if (led->led_type == ATH_LED_ASSOC || | |
f2bffa7e VT |
1004 | led->led_type == ATH_LED_RADIO) { |
1005 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, | |
1006 | (led->led_type == ATH_LED_RADIO)); | |
8feceb67 | 1007 | sc->sc_flags &= ~SC_OP_LED_ASSOCIATED; |
f2bffa7e VT |
1008 | if (led->led_type == ATH_LED_RADIO) |
1009 | sc->sc_flags &= ~SC_OP_LED_ON; | |
1010 | } else { | |
1011 | sc->led_off_cnt++; | |
1012 | } | |
8feceb67 VT |
1013 | break; |
1014 | case LED_FULL: | |
f2bffa7e | 1015 | if (led->led_type == ATH_LED_ASSOC) { |
8feceb67 | 1016 | sc->sc_flags |= SC_OP_LED_ASSOCIATED; |
42935eca LR |
1017 | ieee80211_queue_delayed_work(sc->hw, |
1018 | &sc->ath_led_blink_work, 0); | |
f2bffa7e VT |
1019 | } else if (led->led_type == ATH_LED_RADIO) { |
1020 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0); | |
1021 | sc->sc_flags |= SC_OP_LED_ON; | |
1022 | } else { | |
1023 | sc->led_on_cnt++; | |
1024 | } | |
8feceb67 VT |
1025 | break; |
1026 | default: | |
1027 | break; | |
f078f209 | 1028 | } |
8feceb67 | 1029 | } |
f078f209 | 1030 | |
8feceb67 VT |
1031 | static int ath_register_led(struct ath_softc *sc, struct ath_led *led, |
1032 | char *trigger) | |
1033 | { | |
1034 | int ret; | |
f078f209 | 1035 | |
8feceb67 VT |
1036 | led->sc = sc; |
1037 | led->led_cdev.name = led->name; | |
1038 | led->led_cdev.default_trigger = trigger; | |
1039 | led->led_cdev.brightness_set = ath_led_brightness; | |
f078f209 | 1040 | |
8feceb67 VT |
1041 | ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev); |
1042 | if (ret) | |
1043 | DPRINTF(sc, ATH_DBG_FATAL, | |
1044 | "Failed to register led:%s", led->name); | |
1045 | else | |
1046 | led->registered = 1; | |
1047 | return ret; | |
1048 | } | |
f078f209 | 1049 | |
8feceb67 VT |
1050 | static void ath_unregister_led(struct ath_led *led) |
1051 | { | |
1052 | if (led->registered) { | |
1053 | led_classdev_unregister(&led->led_cdev); | |
1054 | led->registered = 0; | |
f078f209 | 1055 | } |
f078f209 LR |
1056 | } |
1057 | ||
8feceb67 | 1058 | static void ath_deinit_leds(struct ath_softc *sc) |
f078f209 | 1059 | { |
8feceb67 VT |
1060 | ath_unregister_led(&sc->assoc_led); |
1061 | sc->sc_flags &= ~SC_OP_LED_ASSOCIATED; | |
1062 | ath_unregister_led(&sc->tx_led); | |
1063 | ath_unregister_led(&sc->rx_led); | |
1064 | ath_unregister_led(&sc->radio_led); | |
1065 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
1066 | } | |
f078f209 | 1067 | |
8feceb67 VT |
1068 | static void ath_init_leds(struct ath_softc *sc) |
1069 | { | |
1070 | char *trigger; | |
1071 | int ret; | |
f078f209 | 1072 | |
8feceb67 VT |
1073 | /* Configure gpio 1 for output */ |
1074 | ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN, | |
1075 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
1076 | /* LED off, active low */ | |
1077 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
7dcfdcd9 | 1078 | |
f2bffa7e VT |
1079 | INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work); |
1080 | ||
8feceb67 VT |
1081 | trigger = ieee80211_get_radio_led_name(sc->hw); |
1082 | snprintf(sc->radio_led.name, sizeof(sc->radio_led.name), | |
0818cb8a | 1083 | "ath9k-%s::radio", wiphy_name(sc->hw->wiphy)); |
8feceb67 VT |
1084 | ret = ath_register_led(sc, &sc->radio_led, trigger); |
1085 | sc->radio_led.led_type = ATH_LED_RADIO; | |
1086 | if (ret) | |
1087 | goto fail; | |
7dcfdcd9 | 1088 | |
8feceb67 VT |
1089 | trigger = ieee80211_get_assoc_led_name(sc->hw); |
1090 | snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name), | |
0818cb8a | 1091 | "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy)); |
8feceb67 VT |
1092 | ret = ath_register_led(sc, &sc->assoc_led, trigger); |
1093 | sc->assoc_led.led_type = ATH_LED_ASSOC; | |
1094 | if (ret) | |
1095 | goto fail; | |
f078f209 | 1096 | |
8feceb67 VT |
1097 | trigger = ieee80211_get_tx_led_name(sc->hw); |
1098 | snprintf(sc->tx_led.name, sizeof(sc->tx_led.name), | |
0818cb8a | 1099 | "ath9k-%s::tx", wiphy_name(sc->hw->wiphy)); |
8feceb67 VT |
1100 | ret = ath_register_led(sc, &sc->tx_led, trigger); |
1101 | sc->tx_led.led_type = ATH_LED_TX; | |
1102 | if (ret) | |
1103 | goto fail; | |
f078f209 | 1104 | |
8feceb67 VT |
1105 | trigger = ieee80211_get_rx_led_name(sc->hw); |
1106 | snprintf(sc->rx_led.name, sizeof(sc->rx_led.name), | |
0818cb8a | 1107 | "ath9k-%s::rx", wiphy_name(sc->hw->wiphy)); |
8feceb67 VT |
1108 | ret = ath_register_led(sc, &sc->rx_led, trigger); |
1109 | sc->rx_led.led_type = ATH_LED_RX; | |
1110 | if (ret) | |
1111 | goto fail; | |
f078f209 | 1112 | |
8feceb67 VT |
1113 | return; |
1114 | ||
1115 | fail: | |
35c95ab9 | 1116 | cancel_delayed_work_sync(&sc->ath_led_blink_work); |
8feceb67 | 1117 | ath_deinit_leds(sc); |
f078f209 LR |
1118 | } |
1119 | ||
7ec3e514 | 1120 | void ath_radio_enable(struct ath_softc *sc) |
500c064d | 1121 | { |
cbe61d8a | 1122 | struct ath_hw *ah = sc->sc_ah; |
ae8d2858 LR |
1123 | struct ieee80211_channel *channel = sc->hw->conf.channel; |
1124 | int r; | |
500c064d | 1125 | |
3cbb5dd7 | 1126 | ath9k_ps_wakeup(sc); |
d2f5b3a6 | 1127 | ath9k_hw_configpcipowersave(ah, 0); |
ae8d2858 | 1128 | |
159cd468 VT |
1129 | if (!ah->curchan) |
1130 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
1131 | ||
d2f5b3a6 | 1132 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 1133 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 1134 | if (r) { |
500c064d | 1135 | DPRINTF(sc, ATH_DBG_FATAL, |
ae8d2858 | 1136 | "Unable to reset channel %u (%uMhz) ", |
6b45784f | 1137 | "reset status %d\n", |
ae8d2858 | 1138 | channel->center_freq, r); |
500c064d VT |
1139 | } |
1140 | spin_unlock_bh(&sc->sc_resetlock); | |
1141 | ||
1142 | ath_update_txpow(sc); | |
1143 | if (ath_startrecv(sc) != 0) { | |
1144 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1145 | "Unable to restart recv logic\n"); |
500c064d VT |
1146 | return; |
1147 | } | |
1148 | ||
1149 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 1150 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
1151 | |
1152 | /* Re-Enable interrupts */ | |
17d7904d | 1153 | ath9k_hw_set_interrupts(ah, sc->imask); |
500c064d VT |
1154 | |
1155 | /* Enable LED */ | |
1156 | ath9k_hw_cfg_output(ah, ATH_LED_PIN, | |
1157 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
1158 | ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0); | |
1159 | ||
1160 | ieee80211_wake_queues(sc->hw); | |
3cbb5dd7 | 1161 | ath9k_ps_restore(sc); |
500c064d VT |
1162 | } |
1163 | ||
7ec3e514 | 1164 | void ath_radio_disable(struct ath_softc *sc) |
500c064d | 1165 | { |
cbe61d8a | 1166 | struct ath_hw *ah = sc->sc_ah; |
ae8d2858 LR |
1167 | struct ieee80211_channel *channel = sc->hw->conf.channel; |
1168 | int r; | |
500c064d | 1169 | |
3cbb5dd7 | 1170 | ath9k_ps_wakeup(sc); |
500c064d VT |
1171 | ieee80211_stop_queues(sc->hw); |
1172 | ||
1173 | /* Disable LED */ | |
1174 | ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1); | |
1175 | ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN); | |
1176 | ||
1177 | /* Disable interrupts */ | |
1178 | ath9k_hw_set_interrupts(ah, 0); | |
1179 | ||
043a0405 | 1180 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
500c064d VT |
1181 | ath_stoprecv(sc); /* turn off frame recv */ |
1182 | ath_flushrecv(sc); /* flush recv queue */ | |
1183 | ||
159cd468 VT |
1184 | if (!ah->curchan) |
1185 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
1186 | ||
500c064d | 1187 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 1188 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 1189 | if (r) { |
500c064d | 1190 | DPRINTF(sc, ATH_DBG_FATAL, |
04bd4638 | 1191 | "Unable to reset channel %u (%uMhz) " |
6b45784f | 1192 | "reset status %d\n", |
ae8d2858 | 1193 | channel->center_freq, r); |
500c064d VT |
1194 | } |
1195 | spin_unlock_bh(&sc->sc_resetlock); | |
1196 | ||
1197 | ath9k_hw_phy_disable(ah); | |
d2f5b3a6 | 1198 | ath9k_hw_configpcipowersave(ah, 1); |
3cbb5dd7 | 1199 | ath9k_ps_restore(sc); |
38ab422e | 1200 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
1201 | } |
1202 | ||
5077fd35 GJ |
1203 | /*******************/ |
1204 | /* Rfkill */ | |
1205 | /*******************/ | |
1206 | ||
500c064d VT |
1207 | static bool ath_is_rfkill_set(struct ath_softc *sc) |
1208 | { | |
cbe61d8a | 1209 | struct ath_hw *ah = sc->sc_ah; |
500c064d | 1210 | |
2660b81a S |
1211 | return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) == |
1212 | ah->rfkill_polarity; | |
500c064d VT |
1213 | } |
1214 | ||
3b319aae | 1215 | static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw) |
500c064d | 1216 | { |
3b319aae JB |
1217 | struct ath_wiphy *aphy = hw->priv; |
1218 | struct ath_softc *sc = aphy->sc; | |
19d337df | 1219 | bool blocked = !!ath_is_rfkill_set(sc); |
500c064d | 1220 | |
3b319aae JB |
1221 | wiphy_rfkill_set_hw_state(hw->wiphy, blocked); |
1222 | ||
1223 | if (blocked) | |
19d337df JB |
1224 | ath_radio_disable(sc); |
1225 | else | |
1226 | ath_radio_enable(sc); | |
500c064d VT |
1227 | } |
1228 | ||
3b319aae | 1229 | static void ath_start_rfkill_poll(struct ath_softc *sc) |
500c064d | 1230 | { |
3b319aae | 1231 | struct ath_hw *ah = sc->sc_ah; |
9c84b797 | 1232 | |
3b319aae JB |
1233 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
1234 | wiphy_rfkill_start_polling(sc->hw->wiphy); | |
9c84b797 | 1235 | } |
500c064d | 1236 | |
6baff7f9 | 1237 | void ath_cleanup(struct ath_softc *sc) |
39c3c2f2 GJ |
1238 | { |
1239 | ath_detach(sc); | |
1240 | free_irq(sc->irq, sc); | |
1241 | ath_bus_cleanup(sc); | |
c52f33d0 | 1242 | kfree(sc->sec_wiphy); |
39c3c2f2 GJ |
1243 | ieee80211_free_hw(sc->hw); |
1244 | } | |
1245 | ||
6baff7f9 | 1246 | void ath_detach(struct ath_softc *sc) |
f078f209 | 1247 | { |
8feceb67 | 1248 | struct ieee80211_hw *hw = sc->hw; |
9c84b797 | 1249 | int i = 0; |
f078f209 | 1250 | |
3cbb5dd7 VN |
1251 | ath9k_ps_wakeup(sc); |
1252 | ||
04bd4638 | 1253 | DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n"); |
f078f209 | 1254 | |
35c95ab9 LR |
1255 | ath_deinit_leds(sc); |
1256 | ||
c52f33d0 JM |
1257 | for (i = 0; i < sc->num_sec_wiphy; i++) { |
1258 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
1259 | if (aphy == NULL) | |
1260 | continue; | |
1261 | sc->sec_wiphy[i] = NULL; | |
1262 | ieee80211_unregister_hw(aphy->hw); | |
1263 | ieee80211_free_hw(aphy->hw); | |
1264 | } | |
3fcdfb4b | 1265 | ieee80211_unregister_hw(hw); |
8feceb67 VT |
1266 | ath_rx_cleanup(sc); |
1267 | ath_tx_cleanup(sc); | |
f078f209 | 1268 | |
9c84b797 S |
1269 | tasklet_kill(&sc->intr_tq); |
1270 | tasklet_kill(&sc->bcon_tasklet); | |
f078f209 | 1271 | |
9c84b797 S |
1272 | if (!(sc->sc_flags & SC_OP_INVALID)) |
1273 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); | |
8feceb67 | 1274 | |
9c84b797 S |
1275 | /* cleanup tx queues */ |
1276 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1277 | if (ATH_TXQ_SETUP(sc, i)) | |
b77f483f | 1278 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); |
9c84b797 S |
1279 | |
1280 | ath9k_hw_detach(sc->sc_ah); | |
3ce1b1a9 | 1281 | sc->sc_ah = NULL; |
826d2680 | 1282 | ath9k_exit_debug(sc); |
f078f209 LR |
1283 | } |
1284 | ||
e3bb249b BC |
1285 | static int ath9k_reg_notifier(struct wiphy *wiphy, |
1286 | struct regulatory_request *request) | |
1287 | { | |
1288 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
1289 | struct ath_wiphy *aphy = hw->priv; | |
1290 | struct ath_softc *sc = aphy->sc; | |
1291 | struct ath_regulatory *reg = &sc->sc_ah->regulatory; | |
1292 | ||
1293 | return ath_reg_notifier_apply(wiphy, request, reg); | |
1294 | } | |
1295 | ||
1e40bcfa LR |
1296 | /* |
1297 | * Initialize and fill ath_softc, ath_sofct is the | |
1298 | * "Software Carrier" struct. Historically it has existed | |
1299 | * to allow the separation between hardware specific | |
1300 | * variables (now in ath_hw) and driver specific variables. | |
1301 | */ | |
1302 | static int ath_init_softc(u16 devid, struct ath_softc *sc) | |
ff37e337 | 1303 | { |
cbe61d8a | 1304 | struct ath_hw *ah = NULL; |
4f3acf81 | 1305 | int r = 0, i; |
ff37e337 S |
1306 | int csz = 0; |
1307 | ||
1308 | /* XXX: hardware will not be ready until ath_open() being called */ | |
1309 | sc->sc_flags |= SC_OP_INVALID; | |
88b126af | 1310 | |
826d2680 S |
1311 | if (ath9k_init_debug(sc) < 0) |
1312 | printk(KERN_ERR "Unable to create debugfs files\n"); | |
ff37e337 | 1313 | |
c52f33d0 | 1314 | spin_lock_init(&sc->wiphy_lock); |
ff37e337 | 1315 | spin_lock_init(&sc->sc_resetlock); |
6158425b | 1316 | spin_lock_init(&sc->sc_serial_rw); |
e5f0921a | 1317 | spin_lock_init(&sc->ani_lock); |
04717ccd | 1318 | spin_lock_init(&sc->sc_pm_lock); |
aa33de09 | 1319 | mutex_init(&sc->mutex); |
ff37e337 | 1320 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); |
9fc9ab0a | 1321 | tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, |
ff37e337 S |
1322 | (unsigned long)sc); |
1323 | ||
1324 | /* | |
1325 | * Cache line size is used to size and align various | |
1326 | * structures used to communicate with the hardware. | |
1327 | */ | |
88d15707 | 1328 | ath_read_cachesize(sc, &csz); |
ff37e337 | 1329 | /* XXX assert csz is non-zero */ |
17d7904d | 1330 | sc->cachelsz = csz << 2; /* convert to bytes */ |
ff37e337 | 1331 | |
4f3acf81 LR |
1332 | ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); |
1333 | if (!ah) { | |
4f3acf81 LR |
1334 | r = -ENOMEM; |
1335 | goto bad_no_ah; | |
1336 | } | |
1337 | ||
1338 | ah->ah_sc = sc; | |
8df5d1b7 | 1339 | ah->hw_version.devid = devid; |
e1e2f93f | 1340 | sc->sc_ah = ah; |
4f3acf81 | 1341 | |
f637cfd6 | 1342 | r = ath9k_hw_init(ah); |
4f3acf81 | 1343 | if (r) { |
ff37e337 | 1344 | DPRINTF(sc, ATH_DBG_FATAL, |
f637cfd6 | 1345 | "Unable to initialize hardware; " |
4f3acf81 | 1346 | "initialization status: %d\n", r); |
ff37e337 S |
1347 | goto bad; |
1348 | } | |
ff37e337 S |
1349 | |
1350 | /* Get the hardware key cache size. */ | |
2660b81a | 1351 | sc->keymax = ah->caps.keycache_size; |
17d7904d | 1352 | if (sc->keymax > ATH_KEYMAX) { |
d8baa939 | 1353 | DPRINTF(sc, ATH_DBG_ANY, |
04bd4638 | 1354 | "Warning, using only %u entries in %u key cache\n", |
17d7904d S |
1355 | ATH_KEYMAX, sc->keymax); |
1356 | sc->keymax = ATH_KEYMAX; | |
ff37e337 S |
1357 | } |
1358 | ||
1359 | /* | |
1360 | * Reset the key cache since some parts do not | |
1361 | * reset the contents on initial power up. | |
1362 | */ | |
17d7904d | 1363 | for (i = 0; i < sc->keymax; i++) |
ff37e337 | 1364 | ath9k_hw_keyreset(ah, (u16) i); |
ff37e337 | 1365 | |
ff37e337 | 1366 | /* default to MONITOR mode */ |
2660b81a | 1367 | sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; |
d97809db | 1368 | |
ff37e337 S |
1369 | /* Setup rate tables */ |
1370 | ||
1371 | ath_rate_attach(sc); | |
1372 | ath_setup_rates(sc, IEEE80211_BAND_2GHZ); | |
1373 | ath_setup_rates(sc, IEEE80211_BAND_5GHZ); | |
1374 | ||
1375 | /* | |
1376 | * Allocate hardware transmit queues: one queue for | |
1377 | * beacon frames and one data queue for each QoS | |
1378 | * priority. Note that the hal handles reseting | |
1379 | * these queues at the needed time. | |
1380 | */ | |
b77f483f S |
1381 | sc->beacon.beaconq = ath_beaconq_setup(ah); |
1382 | if (sc->beacon.beaconq == -1) { | |
ff37e337 | 1383 | DPRINTF(sc, ATH_DBG_FATAL, |
04bd4638 | 1384 | "Unable to setup a beacon xmit queue\n"); |
4f3acf81 | 1385 | r = -EIO; |
ff37e337 S |
1386 | goto bad2; |
1387 | } | |
b77f483f S |
1388 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
1389 | if (sc->beacon.cabq == NULL) { | |
ff37e337 | 1390 | DPRINTF(sc, ATH_DBG_FATAL, |
04bd4638 | 1391 | "Unable to setup CAB xmit queue\n"); |
4f3acf81 | 1392 | r = -EIO; |
ff37e337 S |
1393 | goto bad2; |
1394 | } | |
1395 | ||
17d7904d | 1396 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; |
ff37e337 S |
1397 | ath_cabq_update(sc); |
1398 | ||
b77f483f S |
1399 | for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++) |
1400 | sc->tx.hwq_map[i] = -1; | |
ff37e337 S |
1401 | |
1402 | /* Setup data queues */ | |
1403 | /* NB: ensure BK queue is the lowest priority h/w queue */ | |
1404 | if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) { | |
1405 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1406 | "Unable to setup xmit queue for BK traffic\n"); |
4f3acf81 | 1407 | r = -EIO; |
ff37e337 S |
1408 | goto bad2; |
1409 | } | |
1410 | ||
1411 | if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) { | |
1412 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1413 | "Unable to setup xmit queue for BE traffic\n"); |
4f3acf81 | 1414 | r = -EIO; |
ff37e337 S |
1415 | goto bad2; |
1416 | } | |
1417 | if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) { | |
1418 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1419 | "Unable to setup xmit queue for VI traffic\n"); |
4f3acf81 | 1420 | r = -EIO; |
ff37e337 S |
1421 | goto bad2; |
1422 | } | |
1423 | if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) { | |
1424 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1425 | "Unable to setup xmit queue for VO traffic\n"); |
4f3acf81 | 1426 | r = -EIO; |
ff37e337 S |
1427 | goto bad2; |
1428 | } | |
1429 | ||
1430 | /* Initializes the noise floor to a reasonable default value. | |
1431 | * Later on this will be updated during ANI processing. */ | |
1432 | ||
17d7904d S |
1433 | sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR; |
1434 | setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc); | |
ff37e337 S |
1435 | |
1436 | if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | |
1437 | ATH9K_CIPHER_TKIP, NULL)) { | |
1438 | /* | |
1439 | * Whether we should enable h/w TKIP MIC. | |
1440 | * XXX: if we don't support WME TKIP MIC, then we wouldn't | |
1441 | * report WMM capable, so it's always safe to turn on | |
1442 | * TKIP MIC in this case. | |
1443 | */ | |
1444 | ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC, | |
1445 | 0, 1, NULL); | |
1446 | } | |
1447 | ||
1448 | /* | |
1449 | * Check whether the separate key cache entries | |
1450 | * are required to handle both tx+rx MIC keys. | |
1451 | * With split mic keys the number of stations is limited | |
1452 | * to 27 otherwise 59. | |
1453 | */ | |
1454 | if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | |
1455 | ATH9K_CIPHER_TKIP, NULL) | |
1456 | && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | |
1457 | ATH9K_CIPHER_MIC, NULL) | |
1458 | && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT, | |
1459 | 0, NULL)) | |
17d7904d | 1460 | sc->splitmic = 1; |
ff37e337 S |
1461 | |
1462 | /* turn on mcast key search if possible */ | |
1463 | if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL)) | |
1464 | (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1, | |
1465 | 1, NULL); | |
1466 | ||
17d7904d | 1467 | sc->config.txpowlimit = ATH_TXPOWER_MAX; |
ff37e337 S |
1468 | |
1469 | /* 11n Capabilities */ | |
2660b81a | 1470 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
ff37e337 S |
1471 | sc->sc_flags |= SC_OP_TXAGGR; |
1472 | sc->sc_flags |= SC_OP_RXAGGR; | |
1473 | } | |
1474 | ||
2660b81a S |
1475 | sc->tx_chainmask = ah->caps.tx_chainmask; |
1476 | sc->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 S |
1477 | |
1478 | ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); | |
b77f483f | 1479 | sc->rx.defant = ath9k_hw_getdefantenna(ah); |
ff37e337 | 1480 | |
8ca21f01 | 1481 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
ba52da58 | 1482 | memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); |
ff37e337 | 1483 | |
b77f483f | 1484 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */ |
ff37e337 S |
1485 | |
1486 | /* initialize beacon slots */ | |
c52f33d0 | 1487 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
2c3db3d5 | 1488 | sc->beacon.bslot[i] = NULL; |
c52f33d0 JM |
1489 | sc->beacon.bslot_aphy[i] = NULL; |
1490 | } | |
ff37e337 | 1491 | |
ff37e337 S |
1492 | /* setup channels and rates */ |
1493 | ||
5f8e077c | 1494 | sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable; |
ff37e337 S |
1495 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = |
1496 | sc->rates[IEEE80211_BAND_2GHZ]; | |
1497 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; | |
5f8e077c LR |
1498 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = |
1499 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
ff37e337 | 1500 | |
2660b81a | 1501 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) { |
5f8e077c | 1502 | sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable; |
ff37e337 S |
1503 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = |
1504 | sc->rates[IEEE80211_BAND_5GHZ]; | |
1505 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; | |
5f8e077c LR |
1506 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = |
1507 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
ff37e337 S |
1508 | } |
1509 | ||
2660b81a | 1510 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX) |
c97c92d9 VT |
1511 | ath9k_hw_btcoex_enable(sc->sc_ah); |
1512 | ||
ff37e337 S |
1513 | return 0; |
1514 | bad2: | |
1515 | /* cleanup tx queues */ | |
1516 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1517 | if (ATH_TXQ_SETUP(sc, i)) | |
b77f483f | 1518 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); |
ff37e337 | 1519 | bad: |
95fafca2 | 1520 | ath9k_hw_detach(ah); |
3ce1b1a9 | 1521 | sc->sc_ah = NULL; |
4f3acf81 | 1522 | bad_no_ah: |
40b130a9 | 1523 | ath9k_exit_debug(sc); |
ff37e337 | 1524 | |
4f3acf81 | 1525 | return r; |
ff37e337 S |
1526 | } |
1527 | ||
c52f33d0 | 1528 | void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
f078f209 | 1529 | { |
9c84b797 S |
1530 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
1531 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
1532 | IEEE80211_HW_SIGNAL_DBM | | |
3cbb5dd7 VN |
1533 | IEEE80211_HW_AMPDU_AGGREGATION | |
1534 | IEEE80211_HW_SUPPORTS_PS | | |
eeee1320 S |
1535 | IEEE80211_HW_PS_NULLFUNC_STACK | |
1536 | IEEE80211_HW_SPECTRUM_MGMT; | |
f078f209 | 1537 | |
b3bd89ce | 1538 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt) |
0ced0e17 JM |
1539 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; |
1540 | ||
9c84b797 S |
1541 | hw->wiphy->interface_modes = |
1542 | BIT(NL80211_IFTYPE_AP) | | |
1543 | BIT(NL80211_IFTYPE_STATION) | | |
9cb5412b PE |
1544 | BIT(NL80211_IFTYPE_ADHOC) | |
1545 | BIT(NL80211_IFTYPE_MESH_POINT); | |
f078f209 | 1546 | |
8feceb67 | 1547 | hw->queues = 4; |
e63835b0 | 1548 | hw->max_rates = 4; |
171387ef | 1549 | hw->channel_change_time = 5000; |
465ca84d | 1550 | hw->max_listen_interval = 10; |
dd190183 LR |
1551 | /* Hardware supports 10 but we use 4 */ |
1552 | hw->max_rate_tries = 4; | |
528f0c6b | 1553 | hw->sta_data_size = sizeof(struct ath_node); |
17d7904d | 1554 | hw->vif_data_size = sizeof(struct ath_vif); |
f078f209 | 1555 | |
8feceb67 | 1556 | hw->rate_control_algorithm = "ath9k_rate_control"; |
f078f209 | 1557 | |
c52f33d0 JM |
1558 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
1559 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
1560 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) | |
1561 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
1562 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
1563 | } | |
1564 | ||
1e40bcfa LR |
1565 | /* Device driver core initialization */ |
1566 | int ath_init_device(u16 devid, struct ath_softc *sc) | |
c52f33d0 JM |
1567 | { |
1568 | struct ieee80211_hw *hw = sc->hw; | |
c52f33d0 | 1569 | int error = 0, i; |
3a702e49 | 1570 | struct ath_regulatory *reg; |
c52f33d0 JM |
1571 | |
1572 | DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n"); | |
1573 | ||
1e40bcfa | 1574 | error = ath_init_softc(devid, sc); |
c52f33d0 JM |
1575 | if (error != 0) |
1576 | return error; | |
1577 | ||
1578 | /* get mac address from hardware and set in mac80211 */ | |
1579 | ||
1580 | SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr); | |
1581 | ||
1582 | ath_set_hw_capab(sc, hw); | |
1583 | ||
c26c2e57 LR |
1584 | error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy, |
1585 | ath9k_reg_notifier); | |
1586 | if (error) | |
1587 | return error; | |
1588 | ||
1589 | reg = &sc->sc_ah->regulatory; | |
1590 | ||
2660b81a | 1591 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
eb2599ca | 1592 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); |
2660b81a | 1593 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) |
eb2599ca | 1594 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); |
9c84b797 S |
1595 | } |
1596 | ||
db93e7b5 SB |
1597 | /* initialize tx/rx engine */ |
1598 | error = ath_tx_init(sc, ATH_TXBUF); | |
1599 | if (error != 0) | |
40b130a9 | 1600 | goto error_attach; |
8feceb67 | 1601 | |
db93e7b5 SB |
1602 | error = ath_rx_init(sc, ATH_RXBUF); |
1603 | if (error != 0) | |
40b130a9 | 1604 | goto error_attach; |
8feceb67 | 1605 | |
0e2dedf9 | 1606 | INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work); |
f98c3bd2 JM |
1607 | INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work); |
1608 | sc->wiphy_scheduler_int = msecs_to_jiffies(500); | |
0e2dedf9 | 1609 | |
db93e7b5 | 1610 | error = ieee80211_register_hw(hw); |
8feceb67 | 1611 | |
3a702e49 | 1612 | if (!ath_is_world_regd(reg)) { |
c02cf373 | 1613 | error = regulatory_hint(hw->wiphy, reg->alpha2); |
fe33eb39 LR |
1614 | if (error) |
1615 | goto error_attach; | |
1616 | } | |
5f8e077c | 1617 | |
db93e7b5 SB |
1618 | /* Initialize LED control */ |
1619 | ath_init_leds(sc); | |
8feceb67 | 1620 | |
3b319aae | 1621 | ath_start_rfkill_poll(sc); |
5f8e077c | 1622 | |
8feceb67 | 1623 | return 0; |
40b130a9 VT |
1624 | |
1625 | error_attach: | |
1626 | /* cleanup tx queues */ | |
1627 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1628 | if (ATH_TXQ_SETUP(sc, i)) | |
1629 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
1630 | ||
1631 | ath9k_hw_detach(sc->sc_ah); | |
3ce1b1a9 | 1632 | sc->sc_ah = NULL; |
40b130a9 VT |
1633 | ath9k_exit_debug(sc); |
1634 | ||
8feceb67 | 1635 | return error; |
f078f209 LR |
1636 | } |
1637 | ||
ff37e337 S |
1638 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
1639 | { | |
cbe61d8a | 1640 | struct ath_hw *ah = sc->sc_ah; |
030bb495 | 1641 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 1642 | int r; |
ff37e337 S |
1643 | |
1644 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 1645 | ath_drain_all_txq(sc, retry_tx); |
ff37e337 S |
1646 | ath_stoprecv(sc); |
1647 | ath_flushrecv(sc); | |
1648 | ||
1649 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 1650 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
ae8d2858 | 1651 | if (r) |
ff37e337 | 1652 | DPRINTF(sc, ATH_DBG_FATAL, |
6b45784f | 1653 | "Unable to reset hardware; reset status %d\n", r); |
ff37e337 S |
1654 | spin_unlock_bh(&sc->sc_resetlock); |
1655 | ||
1656 | if (ath_startrecv(sc) != 0) | |
04bd4638 | 1657 | DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n"); |
ff37e337 S |
1658 | |
1659 | /* | |
1660 | * We may be doing a reset in response to a request | |
1661 | * that changes the channel so update any state that | |
1662 | * might change as a result. | |
1663 | */ | |
ce111bad | 1664 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
1665 | |
1666 | ath_update_txpow(sc); | |
1667 | ||
1668 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 1669 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 1670 | |
17d7904d | 1671 | ath9k_hw_set_interrupts(ah, sc->imask); |
ff37e337 S |
1672 | |
1673 | if (retry_tx) { | |
1674 | int i; | |
1675 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1676 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
1677 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
1678 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
1679 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
1680 | } |
1681 | } | |
1682 | } | |
1683 | ||
ae8d2858 | 1684 | return r; |
ff37e337 S |
1685 | } |
1686 | ||
1687 | /* | |
1688 | * This function will allocate both the DMA descriptor structure, and the | |
1689 | * buffers it contains. These are used to contain the descriptors used | |
1690 | * by the system. | |
1691 | */ | |
1692 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
1693 | struct list_head *head, const char *name, | |
1694 | int nbuf, int ndesc) | |
1695 | { | |
1696 | #define DS2PHYS(_dd, _ds) \ | |
1697 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
1698 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
1699 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
1700 | ||
1701 | struct ath_desc *ds; | |
1702 | struct ath_buf *bf; | |
1703 | int i, bsize, error; | |
1704 | ||
04bd4638 S |
1705 | DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
1706 | name, nbuf, ndesc); | |
ff37e337 | 1707 | |
b03a9db9 | 1708 | INIT_LIST_HEAD(head); |
ff37e337 S |
1709 | /* ath_desc must be a multiple of DWORDs */ |
1710 | if ((sizeof(struct ath_desc) % 4) != 0) { | |
04bd4638 | 1711 | DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n"); |
ff37e337 S |
1712 | ASSERT((sizeof(struct ath_desc) % 4) == 0); |
1713 | error = -ENOMEM; | |
1714 | goto fail; | |
1715 | } | |
1716 | ||
ff37e337 S |
1717 | dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; |
1718 | ||
1719 | /* | |
1720 | * Need additional DMA memory because we can't use | |
1721 | * descriptors that cross the 4K page boundary. Assume | |
1722 | * one skipped descriptor per 4K page. | |
1723 | */ | |
2660b81a | 1724 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { |
ff37e337 S |
1725 | u32 ndesc_skipped = |
1726 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
1727 | u32 dma_len; | |
1728 | ||
1729 | while (ndesc_skipped) { | |
1730 | dma_len = ndesc_skipped * sizeof(struct ath_desc); | |
1731 | dd->dd_desc_len += dma_len; | |
1732 | ||
1733 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
1734 | }; | |
1735 | } | |
1736 | ||
1737 | /* allocate descriptors */ | |
7da3c55c | 1738 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, |
f0e6ce13 | 1739 | &dd->dd_desc_paddr, GFP_KERNEL); |
ff37e337 S |
1740 | if (dd->dd_desc == NULL) { |
1741 | error = -ENOMEM; | |
1742 | goto fail; | |
1743 | } | |
1744 | ds = dd->dd_desc; | |
04bd4638 | 1745 | DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
ae459af1 | 1746 | name, ds, (u32) dd->dd_desc_len, |
ff37e337 S |
1747 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); |
1748 | ||
1749 | /* allocate buffers */ | |
1750 | bsize = sizeof(struct ath_buf) * nbuf; | |
f0e6ce13 | 1751 | bf = kzalloc(bsize, GFP_KERNEL); |
ff37e337 S |
1752 | if (bf == NULL) { |
1753 | error = -ENOMEM; | |
1754 | goto fail2; | |
1755 | } | |
ff37e337 S |
1756 | dd->dd_bufptr = bf; |
1757 | ||
ff37e337 S |
1758 | for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { |
1759 | bf->bf_desc = ds; | |
1760 | bf->bf_daddr = DS2PHYS(dd, ds); | |
1761 | ||
2660b81a | 1762 | if (!(sc->sc_ah->caps.hw_caps & |
ff37e337 S |
1763 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { |
1764 | /* | |
1765 | * Skip descriptor addresses which can cause 4KB | |
1766 | * boundary crossing (addr + length) with a 32 dword | |
1767 | * descriptor fetch. | |
1768 | */ | |
1769 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
1770 | ASSERT((caddr_t) bf->bf_desc < | |
1771 | ((caddr_t) dd->dd_desc + | |
1772 | dd->dd_desc_len)); | |
1773 | ||
1774 | ds += ndesc; | |
1775 | bf->bf_desc = ds; | |
1776 | bf->bf_daddr = DS2PHYS(dd, ds); | |
1777 | } | |
1778 | } | |
1779 | list_add_tail(&bf->list, head); | |
1780 | } | |
1781 | return 0; | |
1782 | fail2: | |
7da3c55c GJ |
1783 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, |
1784 | dd->dd_desc_paddr); | |
ff37e337 S |
1785 | fail: |
1786 | memset(dd, 0, sizeof(*dd)); | |
1787 | return error; | |
1788 | #undef ATH_DESC_4KB_BOUND_CHECK | |
1789 | #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED | |
1790 | #undef DS2PHYS | |
1791 | } | |
1792 | ||
1793 | void ath_descdma_cleanup(struct ath_softc *sc, | |
1794 | struct ath_descdma *dd, | |
1795 | struct list_head *head) | |
1796 | { | |
7da3c55c GJ |
1797 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, |
1798 | dd->dd_desc_paddr); | |
ff37e337 S |
1799 | |
1800 | INIT_LIST_HEAD(head); | |
1801 | kfree(dd->dd_bufptr); | |
1802 | memset(dd, 0, sizeof(*dd)); | |
1803 | } | |
1804 | ||
1805 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) | |
1806 | { | |
1807 | int qnum; | |
1808 | ||
1809 | switch (queue) { | |
1810 | case 0: | |
b77f483f | 1811 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO]; |
ff37e337 S |
1812 | break; |
1813 | case 1: | |
b77f483f | 1814 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI]; |
ff37e337 S |
1815 | break; |
1816 | case 2: | |
b77f483f | 1817 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; |
ff37e337 S |
1818 | break; |
1819 | case 3: | |
b77f483f | 1820 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK]; |
ff37e337 S |
1821 | break; |
1822 | default: | |
b77f483f | 1823 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; |
ff37e337 S |
1824 | break; |
1825 | } | |
1826 | ||
1827 | return qnum; | |
1828 | } | |
1829 | ||
1830 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
1831 | { | |
1832 | int qnum; | |
1833 | ||
1834 | switch (queue) { | |
1835 | case ATH9K_WME_AC_VO: | |
1836 | qnum = 0; | |
1837 | break; | |
1838 | case ATH9K_WME_AC_VI: | |
1839 | qnum = 1; | |
1840 | break; | |
1841 | case ATH9K_WME_AC_BE: | |
1842 | qnum = 2; | |
1843 | break; | |
1844 | case ATH9K_WME_AC_BK: | |
1845 | qnum = 3; | |
1846 | break; | |
1847 | default: | |
1848 | qnum = -1; | |
1849 | break; | |
1850 | } | |
1851 | ||
1852 | return qnum; | |
1853 | } | |
1854 | ||
5f8e077c LR |
1855 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
1856 | * this redundant data */ | |
0e2dedf9 JM |
1857 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
1858 | struct ath9k_channel *ichan) | |
5f8e077c | 1859 | { |
5f8e077c LR |
1860 | struct ieee80211_channel *chan = hw->conf.channel; |
1861 | struct ieee80211_conf *conf = &hw->conf; | |
1862 | ||
1863 | ichan->channel = chan->center_freq; | |
1864 | ichan->chan = chan; | |
1865 | ||
1866 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
1867 | ichan->chanmode = CHANNEL_G; | |
1868 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM; | |
1869 | } else { | |
1870 | ichan->chanmode = CHANNEL_A; | |
1871 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
1872 | } | |
1873 | ||
1874 | sc->tx_chan_width = ATH9K_HT_MACMODE_20; | |
1875 | ||
1876 | if (conf_is_ht(conf)) { | |
1877 | if (conf_is_ht40(conf)) | |
1878 | sc->tx_chan_width = ATH9K_HT_MACMODE_2040; | |
1879 | ||
1880 | ichan->chanmode = ath_get_extchanmode(sc, chan, | |
1881 | conf->channel_type); | |
1882 | } | |
1883 | } | |
1884 | ||
ff37e337 S |
1885 | /**********************/ |
1886 | /* mac80211 callbacks */ | |
1887 | /**********************/ | |
1888 | ||
8feceb67 | 1889 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1890 | { |
bce048d7 JM |
1891 | struct ath_wiphy *aphy = hw->priv; |
1892 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1893 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1894 | struct ath9k_channel *init_channel; |
82880a7c | 1895 | int r; |
f078f209 | 1896 | |
04bd4638 S |
1897 | DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with " |
1898 | "initial channel: %d MHz\n", curchan->center_freq); | |
f078f209 | 1899 | |
141b38b6 S |
1900 | mutex_lock(&sc->mutex); |
1901 | ||
9580a222 JM |
1902 | if (ath9k_wiphy_started(sc)) { |
1903 | if (sc->chan_idx == curchan->hw_value) { | |
1904 | /* | |
1905 | * Already on the operational channel, the new wiphy | |
1906 | * can be marked active. | |
1907 | */ | |
1908 | aphy->state = ATH_WIPHY_ACTIVE; | |
1909 | ieee80211_wake_queues(hw); | |
1910 | } else { | |
1911 | /* | |
1912 | * Another wiphy is on another channel, start the new | |
1913 | * wiphy in paused state. | |
1914 | */ | |
1915 | aphy->state = ATH_WIPHY_PAUSED; | |
1916 | ieee80211_stop_queues(hw); | |
1917 | } | |
1918 | mutex_unlock(&sc->mutex); | |
1919 | return 0; | |
1920 | } | |
1921 | aphy->state = ATH_WIPHY_ACTIVE; | |
1922 | ||
8feceb67 | 1923 | /* setup initial channel */ |
f078f209 | 1924 | |
82880a7c | 1925 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1926 | |
82880a7c | 1927 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
1928 | |
1929 | /* Reset SERDES registers */ | |
1930 | ath9k_hw_configpcipowersave(sc->sc_ah, 0); | |
1931 | ||
1932 | /* | |
1933 | * The basic interface to setting the hardware in a good | |
1934 | * state is ``reset''. On return the hardware is known to | |
1935 | * be powered up and with interrupts disabled. This must | |
1936 | * be followed by initialization of the appropriate bits | |
1937 | * and then setup of the interrupt mask. | |
1938 | */ | |
1939 | spin_lock_bh(&sc->sc_resetlock); | |
ae8d2858 LR |
1940 | r = ath9k_hw_reset(sc->sc_ah, init_channel, false); |
1941 | if (r) { | |
ff37e337 | 1942 | DPRINTF(sc, ATH_DBG_FATAL, |
6b45784f | 1943 | "Unable to reset hardware; reset status %d " |
ae8d2858 LR |
1944 | "(freq %u MHz)\n", r, |
1945 | curchan->center_freq); | |
ff37e337 | 1946 | spin_unlock_bh(&sc->sc_resetlock); |
141b38b6 | 1947 | goto mutex_unlock; |
ff37e337 S |
1948 | } |
1949 | spin_unlock_bh(&sc->sc_resetlock); | |
1950 | ||
1951 | /* | |
1952 | * This is needed only to setup initial state | |
1953 | * but it's best done after a reset. | |
1954 | */ | |
1955 | ath_update_txpow(sc); | |
8feceb67 | 1956 | |
ff37e337 S |
1957 | /* |
1958 | * Setup the hardware after reset: | |
1959 | * The receive engine is set going. | |
1960 | * Frame transmit is handled entirely | |
1961 | * in the frame output path; there's nothing to do | |
1962 | * here except setup the interrupt mask. | |
1963 | */ | |
1964 | if (ath_startrecv(sc) != 0) { | |
1ffb0610 | 1965 | DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n"); |
141b38b6 S |
1966 | r = -EIO; |
1967 | goto mutex_unlock; | |
f078f209 | 1968 | } |
8feceb67 | 1969 | |
ff37e337 | 1970 | /* Setup our intr mask. */ |
17d7904d | 1971 | sc->imask = ATH9K_INT_RX | ATH9K_INT_TX |
ff37e337 S |
1972 | | ATH9K_INT_RXEOL | ATH9K_INT_RXORN |
1973 | | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; | |
1974 | ||
2660b81a | 1975 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT) |
17d7904d | 1976 | sc->imask |= ATH9K_INT_GTT; |
ff37e337 | 1977 | |
2660b81a | 1978 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
17d7904d | 1979 | sc->imask |= ATH9K_INT_CST; |
ff37e337 | 1980 | |
ce111bad | 1981 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
1982 | |
1983 | sc->sc_flags &= ~SC_OP_INVALID; | |
1984 | ||
1985 | /* Disable BMISS interrupt when we're not associated */ | |
17d7904d S |
1986 | sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1987 | ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); | |
ff37e337 | 1988 | |
bce048d7 | 1989 | ieee80211_wake_queues(hw); |
ff37e337 | 1990 | |
42935eca | 1991 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1992 | |
141b38b6 S |
1993 | mutex_unlock: |
1994 | mutex_unlock(&sc->mutex); | |
1995 | ||
ae8d2858 | 1996 | return r; |
f078f209 LR |
1997 | } |
1998 | ||
8feceb67 VT |
1999 | static int ath9k_tx(struct ieee80211_hw *hw, |
2000 | struct sk_buff *skb) | |
f078f209 | 2001 | { |
528f0c6b | 2002 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
2003 | struct ath_wiphy *aphy = hw->priv; |
2004 | struct ath_softc *sc = aphy->sc; | |
528f0c6b | 2005 | struct ath_tx_control txctl; |
8feceb67 | 2006 | int hdrlen, padsize; |
528f0c6b | 2007 | |
8089cc47 | 2008 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
ee166a0e JM |
2009 | printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state " |
2010 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
2011 | goto exit; | |
2012 | } | |
2013 | ||
96148326 | 2014 | if (sc->ps_enabled) { |
dc8c4585 JM |
2015 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
2016 | /* | |
2017 | * mac80211 does not set PM field for normal data frames, so we | |
2018 | * need to update that based on the current PS mode. | |
2019 | */ | |
2020 | if (ieee80211_is_data(hdr->frame_control) && | |
2021 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
2022 | !ieee80211_has_pm(hdr->frame_control)) { | |
2023 | DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame " | |
2024 | "while in PS mode\n"); | |
2025 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); | |
2026 | } | |
2027 | } | |
2028 | ||
9a23f9ca JM |
2029 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
2030 | /* | |
2031 | * We are using PS-Poll and mac80211 can request TX while in | |
2032 | * power save mode. Need to wake up hardware for the TX to be | |
2033 | * completed and if needed, also for RX of buffered frames. | |
2034 | */ | |
2035 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
2036 | ath9k_ps_wakeup(sc); | |
2037 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
2038 | if (ieee80211_is_pspoll(hdr->frame_control)) { | |
2039 | DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a " | |
2040 | "buffered frame\n"); | |
2041 | sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA; | |
2042 | } else { | |
2043 | DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n"); | |
2044 | sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK; | |
2045 | } | |
2046 | /* | |
2047 | * The actual restore operation will happen only after | |
2048 | * the sc_flags bit is cleared. We are just dropping | |
2049 | * the ps_usecount here. | |
2050 | */ | |
2051 | ath9k_ps_restore(sc); | |
2052 | } | |
2053 | ||
528f0c6b | 2054 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 2055 | |
8feceb67 VT |
2056 | /* |
2057 | * As a temporary workaround, assign seq# here; this will likely need | |
2058 | * to be cleaned up to work better with Beacon transmission and virtual | |
2059 | * BSSes. | |
2060 | */ | |
2061 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
2062 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
2063 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
b77f483f | 2064 | sc->tx.seq_no += 0x10; |
8feceb67 | 2065 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 2066 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 2067 | } |
f078f209 | 2068 | |
8feceb67 VT |
2069 | /* Add the padding after the header if this is not already done */ |
2070 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
2071 | if (hdrlen & 3) { | |
2072 | padsize = hdrlen % 4; | |
2073 | if (skb_headroom(skb) < padsize) | |
2074 | return -1; | |
2075 | skb_push(skb, padsize); | |
2076 | memmove(skb->data, skb->data + padsize, hdrlen); | |
2077 | } | |
2078 | ||
528f0c6b S |
2079 | /* Check if a tx queue is available */ |
2080 | ||
2081 | txctl.txq = ath_test_get_txq(sc, skb); | |
2082 | if (!txctl.txq) | |
2083 | goto exit; | |
2084 | ||
04bd4638 | 2085 | DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 2086 | |
c52f33d0 | 2087 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
04bd4638 | 2088 | DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 2089 | goto exit; |
8feceb67 VT |
2090 | } |
2091 | ||
528f0c6b S |
2092 | return 0; |
2093 | exit: | |
2094 | dev_kfree_skb_any(skb); | |
8feceb67 | 2095 | return 0; |
f078f209 LR |
2096 | } |
2097 | ||
8feceb67 | 2098 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 2099 | { |
bce048d7 JM |
2100 | struct ath_wiphy *aphy = hw->priv; |
2101 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 2102 | |
9580a222 JM |
2103 | aphy->state = ATH_WIPHY_INACTIVE; |
2104 | ||
c94dbff7 LR |
2105 | cancel_delayed_work_sync(&sc->ath_led_blink_work); |
2106 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
2107 | ||
2108 | if (!sc->num_sec_wiphy) { | |
2109 | cancel_delayed_work_sync(&sc->wiphy_work); | |
2110 | cancel_work_sync(&sc->chan_work); | |
2111 | } | |
2112 | ||
9c84b797 | 2113 | if (sc->sc_flags & SC_OP_INVALID) { |
04bd4638 | 2114 | DPRINTF(sc, ATH_DBG_ANY, "Device not present\n"); |
9c84b797 S |
2115 | return; |
2116 | } | |
8feceb67 | 2117 | |
141b38b6 | 2118 | mutex_lock(&sc->mutex); |
ff37e337 | 2119 | |
e48e3a2f LR |
2120 | cancel_delayed_work_sync(&sc->tx_complete_work); |
2121 | ||
9580a222 JM |
2122 | if (ath9k_wiphy_started(sc)) { |
2123 | mutex_unlock(&sc->mutex); | |
2124 | return; /* another wiphy still in use */ | |
2125 | } | |
2126 | ||
ff37e337 S |
2127 | /* make sure h/w will not generate any interrupt |
2128 | * before setting the invalid flag. */ | |
2129 | ath9k_hw_set_interrupts(sc->sc_ah, 0); | |
2130 | ||
2131 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 2132 | ath_drain_all_txq(sc, false); |
ff37e337 S |
2133 | ath_stoprecv(sc); |
2134 | ath9k_hw_phy_disable(sc->sc_ah); | |
2135 | } else | |
b77f483f | 2136 | sc->rx.rxlink = NULL; |
ff37e337 | 2137 | |
3b319aae | 2138 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
19d337df | 2139 | |
ff37e337 S |
2140 | /* disable HAL and put h/w to sleep */ |
2141 | ath9k_hw_disable(sc->sc_ah); | |
2142 | ath9k_hw_configpcipowersave(sc->sc_ah, 1); | |
2143 | ||
2144 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 2145 | |
141b38b6 S |
2146 | mutex_unlock(&sc->mutex); |
2147 | ||
04bd4638 | 2148 | DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
2149 | } |
2150 | ||
8feceb67 VT |
2151 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
2152 | struct ieee80211_if_init_conf *conf) | |
f078f209 | 2153 | { |
bce048d7 JM |
2154 | struct ath_wiphy *aphy = hw->priv; |
2155 | struct ath_softc *sc = aphy->sc; | |
17d7904d | 2156 | struct ath_vif *avp = (void *)conf->vif->drv_priv; |
d97809db | 2157 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 2158 | int ret = 0; |
8feceb67 | 2159 | |
141b38b6 S |
2160 | mutex_lock(&sc->mutex); |
2161 | ||
8ca21f01 JM |
2162 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) && |
2163 | sc->nvifs > 0) { | |
2164 | ret = -ENOBUFS; | |
2165 | goto out; | |
2166 | } | |
2167 | ||
8feceb67 | 2168 | switch (conf->type) { |
05c914fe | 2169 | case NL80211_IFTYPE_STATION: |
d97809db | 2170 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 2171 | break; |
05c914fe | 2172 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 2173 | case NL80211_IFTYPE_AP: |
9cb5412b | 2174 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
2175 | if (sc->nbcnvifs >= ATH_BCBUF) { |
2176 | ret = -ENOBUFS; | |
2177 | goto out; | |
2178 | } | |
9cb5412b | 2179 | ic_opmode = conf->type; |
f078f209 LR |
2180 | break; |
2181 | default: | |
2182 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 2183 | "Interface type %d not yet supported\n", conf->type); |
2c3db3d5 JM |
2184 | ret = -EOPNOTSUPP; |
2185 | goto out; | |
f078f209 LR |
2186 | } |
2187 | ||
17d7904d | 2188 | DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode); |
8feceb67 | 2189 | |
17d7904d | 2190 | /* Set the VIF opmode */ |
5640b08e S |
2191 | avp->av_opmode = ic_opmode; |
2192 | avp->av_bslot = -1; | |
2193 | ||
2c3db3d5 | 2194 | sc->nvifs++; |
8ca21f01 JM |
2195 | |
2196 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) | |
2197 | ath9k_set_bssid_mask(hw); | |
2198 | ||
2c3db3d5 JM |
2199 | if (sc->nvifs > 1) |
2200 | goto out; /* skip global settings for secondary vif */ | |
2201 | ||
b238e90e | 2202 | if (ic_opmode == NL80211_IFTYPE_AP) { |
5640b08e | 2203 | ath9k_hw_set_tsfadjust(sc->sc_ah, 1); |
b238e90e S |
2204 | sc->sc_flags |= SC_OP_TSF_RESET; |
2205 | } | |
5640b08e | 2206 | |
5640b08e | 2207 | /* Set the device opmode */ |
2660b81a | 2208 | sc->sc_ah->opmode = ic_opmode; |
5640b08e | 2209 | |
4e30ffa2 VN |
2210 | /* |
2211 | * Enable MIB interrupts when there are hardware phy counters. | |
2212 | * Note we only do this (at the moment) for station mode. | |
2213 | */ | |
4af9cf4f | 2214 | if ((conf->type == NL80211_IFTYPE_STATION) || |
9cb5412b PE |
2215 | (conf->type == NL80211_IFTYPE_ADHOC) || |
2216 | (conf->type == NL80211_IFTYPE_MESH_POINT)) { | |
4af9cf4f S |
2217 | if (ath9k_hw_phycounters(sc->sc_ah)) |
2218 | sc->imask |= ATH9K_INT_MIB; | |
2219 | sc->imask |= ATH9K_INT_TSFOOR; | |
2220 | } | |
2221 | ||
17d7904d | 2222 | ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); |
4e30ffa2 | 2223 | |
f38faa31 SB |
2224 | if (conf->type == NL80211_IFTYPE_AP || |
2225 | conf->type == NL80211_IFTYPE_ADHOC || | |
2226 | conf->type == NL80211_IFTYPE_MONITOR) | |
415f738e | 2227 | ath_start_ani(sc); |
6f255425 | 2228 | |
2c3db3d5 | 2229 | out: |
141b38b6 | 2230 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 2231 | return ret; |
f078f209 LR |
2232 | } |
2233 | ||
8feceb67 VT |
2234 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
2235 | struct ieee80211_if_init_conf *conf) | |
f078f209 | 2236 | { |
bce048d7 JM |
2237 | struct ath_wiphy *aphy = hw->priv; |
2238 | struct ath_softc *sc = aphy->sc; | |
17d7904d | 2239 | struct ath_vif *avp = (void *)conf->vif->drv_priv; |
2c3db3d5 | 2240 | int i; |
f078f209 | 2241 | |
04bd4638 | 2242 | DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 2243 | |
141b38b6 S |
2244 | mutex_lock(&sc->mutex); |
2245 | ||
6f255425 | 2246 | /* Stop ANI */ |
17d7904d | 2247 | del_timer_sync(&sc->ani.timer); |
580f0b8a | 2248 | |
8feceb67 | 2249 | /* Reclaim beacon resources */ |
9cb5412b PE |
2250 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
2251 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
2252 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
b77f483f | 2253 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
8feceb67 | 2254 | ath_beacon_return(sc, avp); |
580f0b8a | 2255 | } |
f078f209 | 2256 | |
8feceb67 | 2257 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 2258 | |
2c3db3d5 JM |
2259 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
2260 | if (sc->beacon.bslot[i] == conf->vif) { | |
2261 | printk(KERN_DEBUG "%s: vif had allocated beacon " | |
2262 | "slot\n", __func__); | |
2263 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 2264 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
2265 | } |
2266 | } | |
2267 | ||
17d7904d | 2268 | sc->nvifs--; |
141b38b6 S |
2269 | |
2270 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
2271 | } |
2272 | ||
e8975581 | 2273 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 2274 | { |
bce048d7 JM |
2275 | struct ath_wiphy *aphy = hw->priv; |
2276 | struct ath_softc *sc = aphy->sc; | |
e8975581 | 2277 | struct ieee80211_conf *conf = &hw->conf; |
8782b41d | 2278 | struct ath_hw *ah = sc->sc_ah; |
64839170 | 2279 | bool all_wiphys_idle = false, disable_radio = false; |
f078f209 | 2280 | |
aa33de09 | 2281 | mutex_lock(&sc->mutex); |
141b38b6 | 2282 | |
64839170 LR |
2283 | /* Leave this as the first check */ |
2284 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { | |
2285 | ||
2286 | spin_lock_bh(&sc->wiphy_lock); | |
2287 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
2288 | spin_unlock_bh(&sc->wiphy_lock); | |
2289 | ||
2290 | if (conf->flags & IEEE80211_CONF_IDLE){ | |
2291 | if (all_wiphys_idle) | |
2292 | disable_radio = true; | |
2293 | } | |
2294 | else if (all_wiphys_idle) { | |
2295 | ath_radio_enable(sc); | |
2296 | DPRINTF(sc, ATH_DBG_CONFIG, | |
2297 | "not-idle: enabling radio\n"); | |
2298 | } | |
2299 | } | |
2300 | ||
3cbb5dd7 VN |
2301 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
2302 | if (conf->flags & IEEE80211_CONF_PS) { | |
8782b41d VN |
2303 | if (!(ah->caps.hw_caps & |
2304 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
2305 | if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
2306 | sc->imask |= ATH9K_INT_TIM_TIMER; | |
2307 | ath9k_hw_set_interrupts(sc->sc_ah, | |
2308 | sc->imask); | |
2309 | } | |
2310 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
3cbb5dd7 | 2311 | } |
96148326 | 2312 | sc->ps_enabled = true; |
3cbb5dd7 | 2313 | } else { |
96148326 | 2314 | sc->ps_enabled = false; |
3cbb5dd7 | 2315 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
8782b41d VN |
2316 | if (!(ah->caps.hw_caps & |
2317 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
2318 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca JM |
2319 | sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON | |
2320 | SC_OP_WAIT_FOR_CAB | | |
2321 | SC_OP_WAIT_FOR_PSPOLL_DATA | | |
2322 | SC_OP_WAIT_FOR_TX_ACK); | |
8782b41d VN |
2323 | if (sc->imask & ATH9K_INT_TIM_TIMER) { |
2324 | sc->imask &= ~ATH9K_INT_TIM_TIMER; | |
2325 | ath9k_hw_set_interrupts(sc->sc_ah, | |
2326 | sc->imask); | |
2327 | } | |
3cbb5dd7 VN |
2328 | } |
2329 | } | |
2330 | } | |
2331 | ||
4797938c | 2332 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 2333 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 2334 | int pos = curchan->hw_value; |
ae5eb026 | 2335 | |
0e2dedf9 JM |
2336 | aphy->chan_idx = pos; |
2337 | aphy->chan_is_ht = conf_is_ht(conf); | |
2338 | ||
8089cc47 JM |
2339 | if (aphy->state == ATH_WIPHY_SCAN || |
2340 | aphy->state == ATH_WIPHY_ACTIVE) | |
2341 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
2342 | else { | |
2343 | /* | |
2344 | * Do not change operational channel based on a paused | |
2345 | * wiphy changes. | |
2346 | */ | |
2347 | goto skip_chan_change; | |
2348 | } | |
0e2dedf9 | 2349 | |
04bd4638 S |
2350 | DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
2351 | curchan->center_freq); | |
f078f209 | 2352 | |
5f8e077c | 2353 | /* XXX: remove me eventualy */ |
0e2dedf9 | 2354 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 2355 | |
ecf70441 | 2356 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 2357 | |
0e2dedf9 | 2358 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
04bd4638 | 2359 | DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n"); |
aa33de09 | 2360 | mutex_unlock(&sc->mutex); |
e11602b7 S |
2361 | return -EINVAL; |
2362 | } | |
094d05dc | 2363 | } |
f078f209 | 2364 | |
8089cc47 | 2365 | skip_chan_change: |
5c020dc6 | 2366 | if (changed & IEEE80211_CONF_CHANGE_POWER) |
17d7904d | 2367 | sc->config.txpowlimit = 2 * conf->power_level; |
f078f209 | 2368 | |
64839170 LR |
2369 | if (disable_radio) { |
2370 | DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n"); | |
2371 | ath_radio_disable(sc); | |
2372 | } | |
2373 | ||
aa33de09 | 2374 | mutex_unlock(&sc->mutex); |
141b38b6 | 2375 | |
f078f209 LR |
2376 | return 0; |
2377 | } | |
2378 | ||
8feceb67 VT |
2379 | #define SUPPORTED_FILTERS \ |
2380 | (FIF_PROMISC_IN_BSS | \ | |
2381 | FIF_ALLMULTI | \ | |
2382 | FIF_CONTROL | \ | |
2383 | FIF_OTHER_BSS | \ | |
2384 | FIF_BCN_PRBRESP_PROMISC | \ | |
2385 | FIF_FCSFAIL) | |
c83be688 | 2386 | |
8feceb67 VT |
2387 | /* FIXME: sc->sc_full_reset ? */ |
2388 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
2389 | unsigned int changed_flags, | |
2390 | unsigned int *total_flags, | |
2391 | int mc_count, | |
2392 | struct dev_mc_list *mclist) | |
2393 | { | |
bce048d7 JM |
2394 | struct ath_wiphy *aphy = hw->priv; |
2395 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2396 | u32 rfilt; |
f078f209 | 2397 | |
8feceb67 VT |
2398 | changed_flags &= SUPPORTED_FILTERS; |
2399 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 2400 | |
b77f483f | 2401 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 2402 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
2403 | rfilt = ath_calcrxfilter(sc); |
2404 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 2405 | ath9k_ps_restore(sc); |
f078f209 | 2406 | |
b77f483f | 2407 | DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter); |
8feceb67 | 2408 | } |
f078f209 | 2409 | |
8feceb67 VT |
2410 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
2411 | struct ieee80211_vif *vif, | |
2412 | enum sta_notify_cmd cmd, | |
17741cdc | 2413 | struct ieee80211_sta *sta) |
8feceb67 | 2414 | { |
bce048d7 JM |
2415 | struct ath_wiphy *aphy = hw->priv; |
2416 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 2417 | |
8feceb67 VT |
2418 | switch (cmd) { |
2419 | case STA_NOTIFY_ADD: | |
5640b08e | 2420 | ath_node_attach(sc, sta); |
8feceb67 VT |
2421 | break; |
2422 | case STA_NOTIFY_REMOVE: | |
b5aa9bf9 | 2423 | ath_node_detach(sc, sta); |
8feceb67 VT |
2424 | break; |
2425 | default: | |
2426 | break; | |
2427 | } | |
f078f209 LR |
2428 | } |
2429 | ||
141b38b6 | 2430 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 2431 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 2432 | { |
bce048d7 JM |
2433 | struct ath_wiphy *aphy = hw->priv; |
2434 | struct ath_softc *sc = aphy->sc; | |
8feceb67 VT |
2435 | struct ath9k_tx_queue_info qi; |
2436 | int ret = 0, qnum; | |
f078f209 | 2437 | |
8feceb67 VT |
2438 | if (queue >= WME_NUM_AC) |
2439 | return 0; | |
f078f209 | 2440 | |
141b38b6 S |
2441 | mutex_lock(&sc->mutex); |
2442 | ||
1ffb0610 S |
2443 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
2444 | ||
8feceb67 VT |
2445 | qi.tqi_aifs = params->aifs; |
2446 | qi.tqi_cwmin = params->cw_min; | |
2447 | qi.tqi_cwmax = params->cw_max; | |
2448 | qi.tqi_burstTime = params->txop; | |
2449 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 2450 | |
8feceb67 | 2451 | DPRINTF(sc, ATH_DBG_CONFIG, |
04bd4638 | 2452 | "Configure tx [queue/halq] [%d/%d], " |
8feceb67 | 2453 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
04bd4638 S |
2454 | queue, qnum, params->aifs, params->cw_min, |
2455 | params->cw_max, params->txop); | |
f078f209 | 2456 | |
8feceb67 VT |
2457 | ret = ath_txq_update(sc, qnum, &qi); |
2458 | if (ret) | |
04bd4638 | 2459 | DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 2460 | |
141b38b6 S |
2461 | mutex_unlock(&sc->mutex); |
2462 | ||
8feceb67 VT |
2463 | return ret; |
2464 | } | |
f078f209 | 2465 | |
8feceb67 VT |
2466 | static int ath9k_set_key(struct ieee80211_hw *hw, |
2467 | enum set_key_cmd cmd, | |
dc822b5d JB |
2468 | struct ieee80211_vif *vif, |
2469 | struct ieee80211_sta *sta, | |
8feceb67 VT |
2470 | struct ieee80211_key_conf *key) |
2471 | { | |
bce048d7 JM |
2472 | struct ath_wiphy *aphy = hw->priv; |
2473 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2474 | int ret = 0; |
f078f209 | 2475 | |
b3bd89ce JM |
2476 | if (modparam_nohwcrypt) |
2477 | return -ENOSPC; | |
2478 | ||
141b38b6 | 2479 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 2480 | ath9k_ps_wakeup(sc); |
d8baa939 | 2481 | DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 2482 | |
8feceb67 VT |
2483 | switch (cmd) { |
2484 | case SET_KEY: | |
3f53dd64 | 2485 | ret = ath_key_config(sc, vif, sta, key); |
6ace2891 JM |
2486 | if (ret >= 0) { |
2487 | key->hw_key_idx = ret; | |
8feceb67 VT |
2488 | /* push IV and Michael MIC generation to stack */ |
2489 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
2490 | if (key->alg == ALG_TKIP) | |
2491 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
0ced0e17 JM |
2492 | if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP) |
2493 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; | |
6ace2891 | 2494 | ret = 0; |
8feceb67 VT |
2495 | } |
2496 | break; | |
2497 | case DISABLE_KEY: | |
2498 | ath_key_delete(sc, key); | |
8feceb67 VT |
2499 | break; |
2500 | default: | |
2501 | ret = -EINVAL; | |
2502 | } | |
f078f209 | 2503 | |
3cbb5dd7 | 2504 | ath9k_ps_restore(sc); |
141b38b6 S |
2505 | mutex_unlock(&sc->mutex); |
2506 | ||
8feceb67 VT |
2507 | return ret; |
2508 | } | |
f078f209 | 2509 | |
8feceb67 VT |
2510 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
2511 | struct ieee80211_vif *vif, | |
2512 | struct ieee80211_bss_conf *bss_conf, | |
2513 | u32 changed) | |
2514 | { | |
bce048d7 JM |
2515 | struct ath_wiphy *aphy = hw->priv; |
2516 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 JB |
2517 | struct ath_hw *ah = sc->sc_ah; |
2518 | struct ath_vif *avp = (void *)vif->drv_priv; | |
2519 | u32 rfilt = 0; | |
2520 | int error, i; | |
f078f209 | 2521 | |
141b38b6 S |
2522 | mutex_lock(&sc->mutex); |
2523 | ||
2d0ddec5 JB |
2524 | /* |
2525 | * TODO: Need to decide which hw opmode to use for | |
2526 | * multi-interface cases | |
2527 | * XXX: This belongs into add_interface! | |
2528 | */ | |
2529 | if (vif->type == NL80211_IFTYPE_AP && | |
2530 | ah->opmode != NL80211_IFTYPE_AP) { | |
2531 | ah->opmode = NL80211_IFTYPE_STATION; | |
2532 | ath9k_hw_setopmode(ah); | |
2533 | memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN); | |
2534 | sc->curaid = 0; | |
2535 | ath9k_hw_write_associd(sc); | |
2536 | /* Request full reset to get hw opmode changed properly */ | |
2537 | sc->sc_flags |= SC_OP_FULL_RESET; | |
2538 | } | |
2539 | ||
2540 | if ((changed & BSS_CHANGED_BSSID) && | |
2541 | !is_zero_ether_addr(bss_conf->bssid)) { | |
2542 | switch (vif->type) { | |
2543 | case NL80211_IFTYPE_STATION: | |
2544 | case NL80211_IFTYPE_ADHOC: | |
2545 | case NL80211_IFTYPE_MESH_POINT: | |
2546 | /* Set BSSID */ | |
2547 | memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN); | |
2548 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
2549 | sc->curaid = 0; | |
2550 | ath9k_hw_write_associd(sc); | |
2551 | ||
2552 | /* Set aggregation protection mode parameters */ | |
2553 | sc->config.ath_aggr_prot = 0; | |
2554 | ||
2555 | DPRINTF(sc, ATH_DBG_CONFIG, | |
2556 | "RX filter 0x%x bssid %pM aid 0x%x\n", | |
2557 | rfilt, sc->curbssid, sc->curaid); | |
2558 | ||
2559 | /* need to reconfigure the beacon */ | |
2560 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
2561 | ||
2562 | break; | |
2563 | default: | |
2564 | break; | |
2565 | } | |
2566 | } | |
2567 | ||
2568 | if ((vif->type == NL80211_IFTYPE_ADHOC) || | |
2569 | (vif->type == NL80211_IFTYPE_AP) || | |
2570 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
2571 | if ((changed & BSS_CHANGED_BEACON) || | |
2572 | (changed & BSS_CHANGED_BEACON_ENABLED && | |
2573 | bss_conf->enable_beacon)) { | |
2574 | /* | |
2575 | * Allocate and setup the beacon frame. | |
2576 | * | |
2577 | * Stop any previous beacon DMA. This may be | |
2578 | * necessary, for example, when an ibss merge | |
2579 | * causes reconfiguration; we may be called | |
2580 | * with beacon transmission active. | |
2581 | */ | |
2582 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2583 | ||
2584 | error = ath_beacon_alloc(aphy, vif); | |
2585 | if (!error) | |
2586 | ath_beacon_config(sc, vif); | |
2587 | } | |
2588 | } | |
2589 | ||
2590 | /* Check for WLAN_CAPABILITY_PRIVACY ? */ | |
2591 | if ((avp->av_opmode != NL80211_IFTYPE_STATION)) { | |
2592 | for (i = 0; i < IEEE80211_WEP_NKID; i++) | |
2593 | if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i)) | |
2594 | ath9k_hw_keysetmac(sc->sc_ah, | |
2595 | (u16)i, | |
2596 | sc->curbssid); | |
2597 | } | |
2598 | ||
2599 | /* Only legacy IBSS for now */ | |
2600 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
2601 | ath_update_chainmask(sc, 0); | |
2602 | ||
8feceb67 | 2603 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
04bd4638 | 2604 | DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
8feceb67 VT |
2605 | bss_conf->use_short_preamble); |
2606 | if (bss_conf->use_short_preamble) | |
2607 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
2608 | else | |
2609 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
2610 | } | |
f078f209 | 2611 | |
8feceb67 | 2612 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
04bd4638 | 2613 | DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
8feceb67 VT |
2614 | bss_conf->use_cts_prot); |
2615 | if (bss_conf->use_cts_prot && | |
2616 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
2617 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
2618 | else | |
2619 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
2620 | } | |
f078f209 | 2621 | |
8feceb67 | 2622 | if (changed & BSS_CHANGED_ASSOC) { |
04bd4638 | 2623 | DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 2624 | bss_conf->assoc); |
5640b08e | 2625 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 2626 | } |
141b38b6 | 2627 | |
57c4d7b4 JB |
2628 | /* |
2629 | * The HW TSF has to be reset when the beacon interval changes. | |
2630 | * We set the flag here, and ath_beacon_config_ap() would take this | |
2631 | * into account when it gets called through the subsequent | |
2632 | * config_interface() call - with IFCC_BEACON in the changed field. | |
2633 | */ | |
2634 | ||
2635 | if (changed & BSS_CHANGED_BEACON_INT) { | |
2636 | sc->sc_flags |= SC_OP_TSF_RESET; | |
2637 | sc->beacon_interval = bss_conf->beacon_int; | |
2638 | } | |
2639 | ||
141b38b6 | 2640 | mutex_unlock(&sc->mutex); |
8feceb67 | 2641 | } |
f078f209 | 2642 | |
8feceb67 VT |
2643 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
2644 | { | |
2645 | u64 tsf; | |
bce048d7 JM |
2646 | struct ath_wiphy *aphy = hw->priv; |
2647 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 2648 | |
141b38b6 S |
2649 | mutex_lock(&sc->mutex); |
2650 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
2651 | mutex_unlock(&sc->mutex); | |
f078f209 | 2652 | |
8feceb67 VT |
2653 | return tsf; |
2654 | } | |
f078f209 | 2655 | |
3b5d665b AF |
2656 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
2657 | { | |
bce048d7 JM |
2658 | struct ath_wiphy *aphy = hw->priv; |
2659 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 2660 | |
141b38b6 S |
2661 | mutex_lock(&sc->mutex); |
2662 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
2663 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
2664 | } |
2665 | ||
8feceb67 VT |
2666 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
2667 | { | |
bce048d7 JM |
2668 | struct ath_wiphy *aphy = hw->priv; |
2669 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 2670 | |
141b38b6 S |
2671 | mutex_lock(&sc->mutex); |
2672 | ath9k_hw_reset_tsf(sc->sc_ah); | |
2673 | mutex_unlock(&sc->mutex); | |
8feceb67 | 2674 | } |
f078f209 | 2675 | |
8feceb67 | 2676 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
141b38b6 S |
2677 | enum ieee80211_ampdu_mlme_action action, |
2678 | struct ieee80211_sta *sta, | |
2679 | u16 tid, u16 *ssn) | |
8feceb67 | 2680 | { |
bce048d7 JM |
2681 | struct ath_wiphy *aphy = hw->priv; |
2682 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2683 | int ret = 0; |
f078f209 | 2684 | |
8feceb67 VT |
2685 | switch (action) { |
2686 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2687 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2688 | ret = -ENOTSUPP; | |
8feceb67 VT |
2689 | break; |
2690 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2691 | break; |
2692 | case IEEE80211_AMPDU_TX_START: | |
f83da965 S |
2693 | ath_tx_aggr_start(sc, sta, tid, ssn); |
2694 | ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid); | |
8feceb67 VT |
2695 | break; |
2696 | case IEEE80211_AMPDU_TX_STOP: | |
f83da965 | 2697 | ath_tx_aggr_stop(sc, sta, tid); |
17741cdc | 2698 | ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid); |
8feceb67 | 2699 | break; |
b1720231 | 2700 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8469cdef S |
2701 | ath_tx_aggr_resume(sc, sta, tid); |
2702 | break; | |
8feceb67 | 2703 | default: |
04bd4638 | 2704 | DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n"); |
8feceb67 VT |
2705 | } |
2706 | ||
2707 | return ret; | |
f078f209 LR |
2708 | } |
2709 | ||
0c98de65 S |
2710 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2711 | { | |
bce048d7 JM |
2712 | struct ath_wiphy *aphy = hw->priv; |
2713 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2714 | |
8089cc47 JM |
2715 | if (ath9k_wiphy_scanning(sc)) { |
2716 | printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the " | |
2717 | "same time\n"); | |
2718 | /* | |
2719 | * Do not allow the concurrent scanning state for now. This | |
2720 | * could be improved with scanning control moved into ath9k. | |
2721 | */ | |
2722 | return; | |
2723 | } | |
2724 | ||
2725 | aphy->state = ATH_WIPHY_SCAN; | |
2726 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
2727 | ||
e5f0921a | 2728 | spin_lock_bh(&sc->ani_lock); |
0c98de65 | 2729 | sc->sc_flags |= SC_OP_SCANNING; |
e5f0921a | 2730 | spin_unlock_bh(&sc->ani_lock); |
0c98de65 S |
2731 | } |
2732 | ||
2733 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) | |
2734 | { | |
bce048d7 JM |
2735 | struct ath_wiphy *aphy = hw->priv; |
2736 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2737 | |
e5f0921a | 2738 | spin_lock_bh(&sc->ani_lock); |
8089cc47 | 2739 | aphy->state = ATH_WIPHY_ACTIVE; |
0c98de65 | 2740 | sc->sc_flags &= ~SC_OP_SCANNING; |
9c07a777 | 2741 | sc->sc_flags |= SC_OP_FULL_RESET; |
e5f0921a | 2742 | spin_unlock_bh(&sc->ani_lock); |
0c98de65 S |
2743 | } |
2744 | ||
6baff7f9 | 2745 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2746 | .tx = ath9k_tx, |
2747 | .start = ath9k_start, | |
2748 | .stop = ath9k_stop, | |
2749 | .add_interface = ath9k_add_interface, | |
2750 | .remove_interface = ath9k_remove_interface, | |
2751 | .config = ath9k_config, | |
8feceb67 | 2752 | .configure_filter = ath9k_configure_filter, |
8feceb67 VT |
2753 | .sta_notify = ath9k_sta_notify, |
2754 | .conf_tx = ath9k_conf_tx, | |
8feceb67 | 2755 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2756 | .set_key = ath9k_set_key, |
8feceb67 | 2757 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2758 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2759 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2760 | .ampdu_action = ath9k_ampdu_action, |
0c98de65 S |
2761 | .sw_scan_start = ath9k_sw_scan_start, |
2762 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 2763 | .rfkill_poll = ath9k_rfkill_poll_state, |
8feceb67 VT |
2764 | }; |
2765 | ||
392dff83 BP |
2766 | static struct { |
2767 | u32 version; | |
2768 | const char * name; | |
2769 | } ath_mac_bb_names[] = { | |
2770 | { AR_SREV_VERSION_5416_PCI, "5416" }, | |
2771 | { AR_SREV_VERSION_5416_PCIE, "5418" }, | |
2772 | { AR_SREV_VERSION_9100, "9100" }, | |
2773 | { AR_SREV_VERSION_9160, "9160" }, | |
2774 | { AR_SREV_VERSION_9280, "9280" }, | |
ac88b6ec VN |
2775 | { AR_SREV_VERSION_9285, "9285" }, |
2776 | { AR_SREV_VERSION_9287, "9287" } | |
392dff83 BP |
2777 | }; |
2778 | ||
2779 | static struct { | |
2780 | u16 version; | |
2781 | const char * name; | |
2782 | } ath_rf_names[] = { | |
2783 | { 0, "5133" }, | |
2784 | { AR_RAD5133_SREV_MAJOR, "5133" }, | |
2785 | { AR_RAD5122_SREV_MAJOR, "5122" }, | |
2786 | { AR_RAD2133_SREV_MAJOR, "2133" }, | |
2787 | { AR_RAD2122_SREV_MAJOR, "2122" } | |
2788 | }; | |
2789 | ||
2790 | /* | |
2791 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. | |
2792 | */ | |
6baff7f9 | 2793 | const char * |
392dff83 BP |
2794 | ath_mac_bb_name(u32 mac_bb_version) |
2795 | { | |
2796 | int i; | |
2797 | ||
2798 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { | |
2799 | if (ath_mac_bb_names[i].version == mac_bb_version) { | |
2800 | return ath_mac_bb_names[i].name; | |
2801 | } | |
2802 | } | |
2803 | ||
2804 | return "????"; | |
2805 | } | |
2806 | ||
2807 | /* | |
2808 | * Return the RF name. "????" is returned if the RF is unknown. | |
2809 | */ | |
6baff7f9 | 2810 | const char * |
392dff83 BP |
2811 | ath_rf_name(u16 rf_version) |
2812 | { | |
2813 | int i; | |
2814 | ||
2815 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { | |
2816 | if (ath_rf_names[i].version == rf_version) { | |
2817 | return ath_rf_names[i].name; | |
2818 | } | |
2819 | } | |
2820 | ||
2821 | return "????"; | |
2822 | } | |
2823 | ||
6baff7f9 | 2824 | static int __init ath9k_init(void) |
f078f209 | 2825 | { |
ca8a8560 VT |
2826 | int error; |
2827 | ||
ca8a8560 VT |
2828 | /* Register rate control algorithm */ |
2829 | error = ath_rate_control_register(); | |
2830 | if (error != 0) { | |
2831 | printk(KERN_ERR | |
b51bb3cd LR |
2832 | "ath9k: Unable to register rate control " |
2833 | "algorithm: %d\n", | |
ca8a8560 | 2834 | error); |
6baff7f9 | 2835 | goto err_out; |
ca8a8560 VT |
2836 | } |
2837 | ||
19d8bc22 GJ |
2838 | error = ath9k_debug_create_root(); |
2839 | if (error) { | |
2840 | printk(KERN_ERR | |
2841 | "ath9k: Unable to create debugfs root: %d\n", | |
2842 | error); | |
2843 | goto err_rate_unregister; | |
2844 | } | |
2845 | ||
6baff7f9 GJ |
2846 | error = ath_pci_init(); |
2847 | if (error < 0) { | |
f078f209 | 2848 | printk(KERN_ERR |
b51bb3cd | 2849 | "ath9k: No PCI devices found, driver not installed.\n"); |
6baff7f9 | 2850 | error = -ENODEV; |
19d8bc22 | 2851 | goto err_remove_root; |
f078f209 LR |
2852 | } |
2853 | ||
09329d37 GJ |
2854 | error = ath_ahb_init(); |
2855 | if (error < 0) { | |
2856 | error = -ENODEV; | |
2857 | goto err_pci_exit; | |
2858 | } | |
2859 | ||
f078f209 | 2860 | return 0; |
6baff7f9 | 2861 | |
09329d37 GJ |
2862 | err_pci_exit: |
2863 | ath_pci_exit(); | |
2864 | ||
19d8bc22 GJ |
2865 | err_remove_root: |
2866 | ath9k_debug_remove_root(); | |
6baff7f9 GJ |
2867 | err_rate_unregister: |
2868 | ath_rate_control_unregister(); | |
2869 | err_out: | |
2870 | return error; | |
f078f209 | 2871 | } |
6baff7f9 | 2872 | module_init(ath9k_init); |
f078f209 | 2873 | |
6baff7f9 | 2874 | static void __exit ath9k_exit(void) |
f078f209 | 2875 | { |
09329d37 | 2876 | ath_ahb_exit(); |
6baff7f9 | 2877 | ath_pci_exit(); |
19d8bc22 | 2878 | ath9k_debug_remove_root(); |
ca8a8560 | 2879 | ath_rate_control_unregister(); |
04bd4638 | 2880 | printk(KERN_INFO "%s: Driver unloaded\n", dev_info); |
f078f209 | 2881 | } |
6baff7f9 | 2882 | module_exit(ath9k_exit); |