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at76c50x-usb: remove unneeded flush_workqueue() at usb disconnect
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209 19
f078f209
LR		 20static char *dev_info = "ath9k";
21
22MODULE_AUTHOR("Atheros Communications");
23MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
24MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
25MODULE_LICENSE("Dual BSD/GPL");
26
b3bd89ce
JM		 27static int modparam_nohwcrypt;
28module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
29MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
30
5f8e077c
LR		 31/* We use the hw_value as an index into our private channel structure */
32
33#define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
eeddfd9d 36 .max_power = 20, \
5f8e077c
LR		 37}
38
39#define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
eeddfd9d 43 .max_power = 20, \
5f8e077c
LR		 44}
45
46/* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65};
66
67/* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100};
101
ce111bad
LR		 102static void ath_cache_conf_rate(struct ath_softc *sc,
103 struct ieee80211_conf *conf)
ff37e337 104{
030bb495
LR		 105 switch (conf->channel->band) {
106 case IEEE80211_BAND_2GHZ:
107 if (conf_is_ht20(conf))
108 sc->cur_rate_table =
109 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110 else if (conf_is_ht40_minus(conf))
111 sc->cur_rate_table =
112 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113 else if (conf_is_ht40_plus(conf))
114 sc->cur_rate_table =
115 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 116 else
030bb495
LR		 117 sc->cur_rate_table =
118 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 119 break;
120 case IEEE80211_BAND_5GHZ:
121 if (conf_is_ht20(conf))
122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124 else if (conf_is_ht40_minus(conf))
125 sc->cur_rate_table =
126 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127 else if (conf_is_ht40_plus(conf))
128 sc->cur_rate_table =
129 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 else
96742256
LR		 131 sc->cur_rate_table =
132 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 133 break;
134 default:
ce111bad 135 BUG_ON(1);
030bb495
LR		 136 break;
137 }
ff37e337
S		 138}
139
140static void ath_update_txpow(struct ath_softc *sc)
141{
cbe61d8a 142 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 143 u32 txpow;
144
17d7904d
S		 145 if (sc->curtxpow != sc->config.txpowlimit) {
146 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 147 /* read back in case value is clamped */
148 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 149 sc->curtxpow = txpow;
ff37e337
S		 150 }
151}
152
153static u8 parse_mpdudensity(u8 mpdudensity)
154{
155 /*
156 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157 * 0 for no restriction
158 * 1 for 1/4 us
159 * 2 for 1/2 us
160 * 3 for 1 us
161 * 4 for 2 us
162 * 5 for 4 us
163 * 6 for 8 us
164 * 7 for 16 us
165 */
166 switch (mpdudensity) {
167 case 0:
168 return 0;
169 case 1:
170 case 2:
171 case 3:
172 /* Our lower layer calculations limit our precision to
173 1 microsecond */
174 return 1;
175 case 4:
176 return 2;
177 case 5:
178 return 4;
179 case 6:
180 return 8;
181 case 7:
182 return 16;
183 default:
184 return 0;
185 }
186}
187
188static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189{
4f0fc7c3 190 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 191 struct ieee80211_supported_band *sband;
192 struct ieee80211_rate *rate;
193 int i, maxrates;
194
195 switch (band) {
196 case IEEE80211_BAND_2GHZ:
197 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198 break;
199 case IEEE80211_BAND_5GHZ:
200 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201 break;
202 default:
203 break;
204 }
205
206 if (rate_table == NULL)
207 return;
208
209 sband = &sc->sbands[band];
210 rate = sc->rates[band];
211
212 if (rate_table->rate_cnt > ATH_RATE_MAX)
213 maxrates = ATH_RATE_MAX;
214 else
215 maxrates = rate_table->rate_cnt;
216
217 for (i = 0; i < maxrates; i++) {
218 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 220 if (rate_table->info[i].short_preamble) {
221 rate[i].hw_value_short = rate_table->info[i].ratecode |
222 rate_table->info[i].short_preamble;
223 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
224 }
ff37e337 225 sband->n_bitrates++;
f46730d1 226
04bd4638
S		 227 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 229 }
230}
231
82880a7c
VT		 232static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
233 struct ieee80211_hw *hw)
234{
235 struct ieee80211_channel *curchan = hw->conf.channel;
236 struct ath9k_channel *channel;
237 u8 chan_idx;
238
239 chan_idx = curchan->hw_value;
240 channel = &sc->sc_ah->channels[chan_idx];
241 ath9k_update_ichannel(sc, hw, channel);
242 return channel;
243}
244
ff37e337
S		 245/*
246 * Set/change channels. If the channel is really being changed, it's done
247 * by reseting the chip. To accomplish this we must first cleanup any pending
248 * DMA, then restart stuff.
249*/
0e2dedf9
JM		 250int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
251 struct ath9k_channel *hchan)
ff37e337 252{
cbe61d8a 253 struct ath_hw *ah = sc->sc_ah;
ff37e337 254 bool fastcc = true, stopped;
ae8d2858
LR		 255 struct ieee80211_channel *channel = hw->conf.channel;
256 int r;
ff37e337
S		 257
258 if (sc->sc_flags & SC_OP_INVALID)
259 return -EIO;
260
3cbb5dd7
VN		 261 ath9k_ps_wakeup(sc);
262
c0d7c7af
LR		 263 /*
264 * This is only performed if the channel settings have
265 * actually changed.
266 *
267 * To switch channels clear any pending DMA operations;
268 * wait long enough for the RX fifo to drain, reset the
269 * hardware at the new frequency, and then re-enable
270 * the relevant bits of the h/w.
271 */
272 ath9k_hw_set_interrupts(ah, 0);
043a0405 273 ath_drain_all_txq(sc, false);
c0d7c7af 274 stopped = ath_stoprecv(sc);
ff37e337 275
c0d7c7af
LR		 276 /* XXX: do not flush receive queue here. We don't want
277 * to flush data frames already in queue because of
278 * changing channel. */
ff37e337 279
c0d7c7af
LR		 280 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
281 fastcc = false;
282
283 DPRINTF(sc, ATH_DBG_CONFIG,
284 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 285 sc->sc_ah->curchan->channel,
c0d7c7af 286 channel->center_freq, sc->tx_chan_width);
ff37e337 287
c0d7c7af
LR		 288 spin_lock_bh(&sc->sc_resetlock);
289
290 r = ath9k_hw_reset(ah, hchan, fastcc);
291 if (r) {
292 DPRINTF(sc, ATH_DBG_FATAL,
293 "Unable to reset channel (%u Mhz) "
6b45784f 294 "reset status %d\n",
c0d7c7af
LR		 295 channel->center_freq, r);
296 spin_unlock_bh(&sc->sc_resetlock);
3989279c 297 goto ps_restore;
ff37e337 298 }
c0d7c7af
LR		 299 spin_unlock_bh(&sc->sc_resetlock);
300
c0d7c7af
LR		 301 sc->sc_flags &= ~SC_OP_FULL_RESET;
302
303 if (ath_startrecv(sc) != 0) {
304 DPRINTF(sc, ATH_DBG_FATAL,
305 "Unable to restart recv logic\n");
3989279c
GJ		 306 r = -EIO;
307 goto ps_restore;
c0d7c7af
LR		 308 }
309
310 ath_cache_conf_rate(sc, &hw->conf);
311 ath_update_txpow(sc);
17d7904d 312 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 313
314 ps_restore:
3cbb5dd7 315 ath9k_ps_restore(sc);
3989279c 316 return r;
ff37e337
S		 317}
318
319/*
320 * This routine performs the periodic noise floor calibration function
321 * that is used to adjust and optimize the chip performance. This
322 * takes environmental changes (location, temperature) into account.
323 * When the task is complete, it reschedules itself depending on the
324 * appropriate interval that was calculated.
325 */
326static void ath_ani_calibrate(unsigned long data)
327{
20977d3e
S		 328 struct ath_softc *sc = (struct ath_softc *)data;
329 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 330 bool longcal = false;
331 bool shortcal = false;
332 bool aniflag = false;
333 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 334 u32 cal_interval, short_cal_interval;
ff37e337 335
20977d3e
S		 336 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
337 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 338
339 /*
340 * don't calibrate when we're scanning.
341 * we are most likely not on our home channel.
342 */
e5f0921a 343 spin_lock(&sc->ani_lock);
0c98de65 344 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 345 goto set_timer;
ff37e337 346
1ffc1c61
JM		 347 /* Only calibrate if awake */
348 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
349 goto set_timer;
350
351 ath9k_ps_wakeup(sc);
352
ff37e337 353 /* Long calibration runs independently of short calibration. */
17d7904d 354 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 355 longcal = true;
04bd4638 356 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 357 sc->ani.longcal_timer = timestamp;
ff37e337
S		 358 }
359
17d7904d
S		 360 /* Short calibration applies only while caldone is false */
361 if (!sc->ani.caldone) {
20977d3e 362 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 363 shortcal = true;
04bd4638 364 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 365 sc->ani.shortcal_timer = timestamp;
366 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 367 }
368 } else {
17d7904d 369 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 370 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 371 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
372 if (sc->ani.caldone)
373 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 374 }
375 }
376
377 /* Verify whether we must check ANI */
20977d3e 378 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 379 aniflag = true;
17d7904d 380 sc->ani.checkani_timer = timestamp;
ff37e337
S		 381 }
382
383 /* Skip all processing if there's nothing to do. */
384 if (longcal || shortcal || aniflag) {
385 /* Call ANI routine if necessary */
386 if (aniflag)
20977d3e 387 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 388
389 /* Perform calibration if necessary */
390 if (longcal || shortcal) {
379f0440
S		 391 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
392 sc->rx_chainmask, longcal);
393
394 if (longcal)
395 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
396 ah->curchan);
397
398 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
399 ah->curchan->channel, ah->curchan->channelFlags,
400 sc->ani.noise_floor);
ff37e337
S		 401 }
402 }
403
1ffc1c61
JM		 404 ath9k_ps_restore(sc);
405
20977d3e 406set_timer:
e5f0921a 407 spin_unlock(&sc->ani_lock);
ff37e337
S		 408 /*
409 * Set timer interval based on previous results.
410 * The interval must be the shortest necessary to satisfy ANI,
411 * short calibration and long calibration.
412 */
aac9207e 413 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 414 if (sc->sc_ah->config.enable_ani)
aac9207e 415 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 416 if (!sc->ani.caldone)
20977d3e 417 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 418
17d7904d 419 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 420}
421
415f738e
S		 422static void ath_start_ani(struct ath_softc *sc)
423{
424 unsigned long timestamp = jiffies_to_msecs(jiffies);
425
426 sc->ani.longcal_timer = timestamp;
427 sc->ani.shortcal_timer = timestamp;
428 sc->ani.checkani_timer = timestamp;
429
430 mod_timer(&sc->ani.timer,
431 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432}
433
ff37e337
S		 434/*
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 437 * the chainmask configuration, for bt coexistence, use
438 * the chainmask configuration even in legacy mode.
ff37e337 439 */
0e2dedf9 440void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 441{
c97c92d9 442 if (is_ht ||
2660b81a
S		 443 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
444 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
445 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 446 } else {
17d7904d
S		 447 sc->tx_chainmask = 1;
448 sc->rx_chainmask = 1;
ff37e337
S		 449 }
450
04bd4638 451 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 452 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 453}
454
455static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
456{
457 struct ath_node *an;
458
459 an = (struct ath_node *)sta->drv_priv;
460
87792efc 461 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 462 ath_tx_node_init(sc, an);
9e98ac65 463 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 464 sta->ht_cap.ampdu_factor);
465 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 466 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 467 }
ff37e337
S		 468}
469
470static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
471{
472 struct ath_node *an = (struct ath_node *)sta->drv_priv;
473
474 if (sc->sc_flags & SC_OP_TXAGGR)
475 ath_tx_node_cleanup(sc, an);
476}
477
478static void ath9k_tasklet(unsigned long data)
479{
480 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 481 u32 status = sc->intrstatus;
ff37e337 482
153e080d
VT		 483 ath9k_ps_wakeup(sc);
484
ff37e337 485 if (status & ATH9K_INT_FATAL) {
ff37e337 486 ath_reset(sc, false);
153e080d 487 ath9k_ps_restore(sc);
ff37e337 488 return;
063d8be3 489 }
ff37e337 490
063d8be3
S		 491 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
492 spin_lock_bh(&sc->rx.rxflushlock);
493 ath_rx_tasklet(sc, 0);
494 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 495 }
496
063d8be3
S		 497 if (status & ATH9K_INT_TX)
498 ath_tx_tasklet(sc);
499
96148326 500 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 501 /*
502 * TSF sync does not look correct; remain awake to sync with
503 * the next Beacon.
504 */
505 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 507 }
508
ff37e337 509 /* re-enable hardware interrupt */
17d7904d 510 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
153e080d 511 ath9k_ps_restore(sc);
ff37e337
S		 512}
513
6baff7f9 514irqreturn_t ath_isr(int irq, void *dev)
ff37e337 515{
063d8be3
S		 516#define SCHED_INTR ( \
517 ATH9K_INT_FATAL | \
518 ATH9K_INT_RXORN | \
519 ATH9K_INT_RXEOL | \
520 ATH9K_INT_RX | \
521 ATH9K_INT_TX | \
522 ATH9K_INT_BMISS | \
523 ATH9K_INT_CST | \
524 ATH9K_INT_TSFOOR)
525
ff37e337 526 struct ath_softc *sc = dev;
cbe61d8a 527 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 528 enum ath9k_int status;
529 bool sched = false;
530
063d8be3
S		 531 /*
532 * The hardware is not ready/present, don't
533 * touch anything. Note this can happen early
534 * on if the IRQ is shared.
535 */
536 if (sc->sc_flags & SC_OP_INVALID)
537 return IRQ_NONE;
ff37e337 538
063d8be3
S		 539
540 /* shared irq, not for us */
541
153e080d 542 if (!ath9k_hw_intrpend(ah))
063d8be3 543 return IRQ_NONE;
063d8be3
S		 544
545 /*
546 * Figure out the reason(s) for the interrupt. Note
547 * that the hal returns a pseudo-ISR that may include
548 * bits we haven't explicitly enabled so we mask the
549 * value to insure we only process bits we requested.
550 */
551 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
552 status &= sc->imask; /* discard unasked-for bits */
ff37e337 553
063d8be3
S		 554 /*
555 * If there are no status bits set, then this interrupt was not
556 * for me (should have been caught above).
557 */
153e080d 558 if (!status)
063d8be3 559 return IRQ_NONE;
ff37e337 560
063d8be3
S		 561 /* Cache the status */
562 sc->intrstatus = status;
563
564 if (status & SCHED_INTR)
565 sched = true;
566
567 /*
568 * If a FATAL or RXORN interrupt is received, we have to reset the
569 * chip immediately.
570 */
571 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
572 goto chip_reset;
573
574 if (status & ATH9K_INT_SWBA)
575 tasklet_schedule(&sc->bcon_tasklet);
576
577 if (status & ATH9K_INT_TXURN)
578 ath9k_hw_updatetxtriglevel(ah, true);
579
580 if (status & ATH9K_INT_MIB) {
ff37e337 581 /*
063d8be3
S		 582 * Disable interrupts until we service the MIB
583 * interrupt; otherwise it will continue to
584 * fire.
ff37e337 585 */
063d8be3
S		 586 ath9k_hw_set_interrupts(ah, 0);
587 /*
588 * Let the hal handle the event. We assume
589 * it will clear whatever condition caused
590 * the interrupt.
591 */
592 ath9k_hw_procmibevent(ah, &sc->nodestats);
593 ath9k_hw_set_interrupts(ah, sc->imask);
594 }
ff37e337 595
153e080d
VT		 596 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
597 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 598 /* Clear RxAbort bit so that we can
599 * receive frames */
600 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 601 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 602 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 603 }
063d8be3
S		 604
605chip_reset:
ff37e337 606
817e11de
S		 607 ath_debug_stat_interrupt(sc, status);
608
ff37e337
S		 609 if (sched) {
610 /* turn off every interrupt except SWBA */
17d7904d 611 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 612 tasklet_schedule(&sc->intr_tq);
613 }
614
615 return IRQ_HANDLED;
063d8be3
S		 616
617#undef SCHED_INTR
ff37e337
S		 618}
619
f078f209 620static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 621 struct ieee80211_channel *chan,
094d05dc 622 enum nl80211_channel_type channel_type)
f078f209
LR		 623{
624 u32 chanmode = 0;
f078f209
LR		 625
626 switch (chan->band) {
627 case IEEE80211_BAND_2GHZ:
094d05dc
S		 628 switch(channel_type) {
629 case NL80211_CHAN_NO_HT:
630 case NL80211_CHAN_HT20:
f078f209 631 chanmode = CHANNEL_G_HT20;
094d05dc
S		 632 break;
633 case NL80211_CHAN_HT40PLUS:
f078f209 634 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 635 break;
636 case NL80211_CHAN_HT40MINUS:
f078f209 637 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 638 break;
639 }
f078f209
LR		 640 break;
641 case IEEE80211_BAND_5GHZ:
094d05dc
S		 642 switch(channel_type) {
643 case NL80211_CHAN_NO_HT:
644 case NL80211_CHAN_HT20:
f078f209 645 chanmode = CHANNEL_A_HT20;
094d05dc
S		 646 break;
647 case NL80211_CHAN_HT40PLUS:
f078f209 648 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 649 break;
650 case NL80211_CHAN_HT40MINUS:
f078f209 651 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 652 break;
653 }
f078f209
LR		 654 break;
655 default:
656 break;
657 }
658
659 return chanmode;
660}
661
6ace2891 662static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 663 struct ath9k_keyval *hk, const u8 *addr,
664 bool authenticator)
f078f209 665{
6ace2891
JM		 666 const u8 *key_rxmic;
667 const u8 *key_txmic;
f078f209 668
6ace2891
JM		 669 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
670 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 671
672 if (addr == NULL) {
d216aaa6
JM		 673 /*
674 * Group key installation - only two key cache entries are used
675 * regardless of splitmic capability since group key is only
676 * used either for TX or RX.
677 */
3f53dd64
JM		 678 if (authenticator) {
679 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
680 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
681 } else {
682 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
684 }
d216aaa6 685 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 686 }
17d7904d 687 if (!sc->splitmic) {
d216aaa6 688 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 689 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
690 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 691 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 692 }
d216aaa6
JM		 693
694 /* Separate key cache entries for TX and RX */
695
696 /* TX key goes at first index, RX key at +32. */
f078f209 697 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 698 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
699 /* TX MIC entry failed. No need to proceed further */
d8baa939 700 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 701 "Setting TX MIC Key Failed\n");
f078f209
LR		 702 return 0;
703 }
704
705 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
706 /* XXX delete tx key on failure? */
d216aaa6 707 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 708}
709
710static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
711{
712 int i;
713
17d7904d
S		 714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
715 if (test_bit(i, sc->keymap) ||
716 test_bit(i + 64, sc->keymap))
6ace2891 717 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 718 if (sc->splitmic &&
719 (test_bit(i + 32, sc->keymap) ||
720 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 721 continue; /* At least one part of TKIP key allocated */
722
723 /* Found a free slot for a TKIP key */
724 return i;
725 }
726 return -1;
727}
728
729static int ath_reserve_key_cache_slot(struct ath_softc *sc)
730{
731 int i;
732
733 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 734 if (sc->splitmic) {
735 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
736 if (!test_bit(i, sc->keymap) &&
737 (test_bit(i + 32, sc->keymap) ||
738 test_bit(i + 64, sc->keymap) ||
739 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 740 return i;
17d7904d
S		 741 if (!test_bit(i + 32, sc->keymap) &&
742 (test_bit(i, sc->keymap) ||
743 test_bit(i + 64, sc->keymap) ||
744 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 745 return i + 32;
17d7904d
S		 746 if (!test_bit(i + 64, sc->keymap) &&
747 (test_bit(i , sc->keymap) ||
748 test_bit(i + 32, sc->keymap) ||
749 test_bit(i + 64 + 32, sc->keymap)))
ea612132 750 return i + 64;
17d7904d
S		 751 if (!test_bit(i + 64 + 32, sc->keymap) &&
752 (test_bit(i, sc->keymap) ||
753 test_bit(i + 32, sc->keymap) ||
754 test_bit(i + 64, sc->keymap)))
ea612132 755 return i + 64 + 32;
6ace2891
JM		 756 }
757 } else {
17d7904d
S		 758 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
759 if (!test_bit(i, sc->keymap) &&
760 test_bit(i + 64, sc->keymap))
6ace2891 761 return i;
17d7904d
S		 762 if (test_bit(i, sc->keymap) &&
763 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 764 return i + 64;
765 }
766 }
767
768 /* No partially used TKIP slots, pick any available slot */
17d7904d 769 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 770 /* Do not allow slots that could be needed for TKIP group keys
771 * to be used. This limitation could be removed if we know that
772 * TKIP will not be used. */
773 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
774 continue;
17d7904d 775 if (sc->splitmic) {
be2864cf
JM		 776 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
777 continue;
778 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
779 continue;
780 }
781
17d7904d 782 if (!test_bit(i, sc->keymap))
6ace2891
JM		 783 return i; /* Found a free slot for a key */
784 }
785
786 /* No free slot found */
787 return -1;
f078f209
LR		 788}
789
790static int ath_key_config(struct ath_softc *sc,
3f53dd64 791 struct ieee80211_vif *vif,
dc822b5d 792 struct ieee80211_sta *sta,
f078f209
LR		 793 struct ieee80211_key_conf *key)
794{
f078f209
LR		 795 struct ath9k_keyval hk;
796 const u8 *mac = NULL;
797 int ret = 0;
6ace2891 798 int idx;
f078f209
LR		 799
800 memset(&hk, 0, sizeof(hk));
801
802 switch (key->alg) {
803 case ALG_WEP:
804 hk.kv_type = ATH9K_CIPHER_WEP;
805 break;
806 case ALG_TKIP:
807 hk.kv_type = ATH9K_CIPHER_TKIP;
808 break;
809 case ALG_CCMP:
810 hk.kv_type = ATH9K_CIPHER_AES_CCM;
811 break;
812 default:
ca470b29 813 return -EOPNOTSUPP;
f078f209
LR		 814 }
815
6ace2891 816 hk.kv_len = key->keylen;
f078f209
LR		 817 memcpy(hk.kv_val, key->key, key->keylen);
818
6ace2891
JM		 819 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
820 /* For now, use the default keys for broadcast keys. This may
821 * need to change with virtual interfaces. */
822 idx = key->keyidx;
823 } else if (key->keyidx) {
dc822b5d
JB		 824 if (WARN_ON(!sta))
825 return -EOPNOTSUPP;
826 mac = sta->addr;
827
6ace2891
JM		 828 if (vif->type != NL80211_IFTYPE_AP) {
829 /* Only keyidx 0 should be used with unicast key, but
830 * allow this for client mode for now. */
831 idx = key->keyidx;
832 } else
833 return -EIO;
f078f209 834 } else {
dc822b5d
JB		 835 if (WARN_ON(!sta))
836 return -EOPNOTSUPP;
837 mac = sta->addr;
838
6ace2891
JM		 839 if (key->alg == ALG_TKIP)
840 idx = ath_reserve_key_cache_slot_tkip(sc);
841 else
842 idx = ath_reserve_key_cache_slot(sc);
843 if (idx < 0)
ca470b29 844 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 845 }
846
847 if (key->alg == ALG_TKIP)
3f53dd64
JM		 848 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
849 vif->type == NL80211_IFTYPE_AP);
f078f209 850 else
d216aaa6 851 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 852
853 if (!ret)
854 return -EIO;
855
17d7904d 856 set_bit(idx, sc->keymap);
6ace2891 857 if (key->alg == ALG_TKIP) {
17d7904d
S		 858 set_bit(idx + 64, sc->keymap);
859 if (sc->splitmic) {
860 set_bit(idx + 32, sc->keymap);
861 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 862 }
863 }
864
865 return idx;
f078f209
LR		 866}
867
868static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
869{
6ace2891
JM		 870 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
871 if (key->hw_key_idx < IEEE80211_WEP_NKID)
872 return;
873
17d7904d 874 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 875 if (key->alg != ALG_TKIP)
876 return;
f078f209 877
17d7904d
S		 878 clear_bit(key->hw_key_idx + 64, sc->keymap);
879 if (sc->splitmic) {
880 clear_bit(key->hw_key_idx + 32, sc->keymap);
881 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 882 }
f078f209
LR		 883}
884
eb2599ca
S		 885static void setup_ht_cap(struct ath_softc *sc,
886 struct ieee80211_sta_ht_cap *ht_info)
f078f209 887{
140add21 888 u8 tx_streams, rx_streams;
f078f209 889
d9fe60de
JB		 890 ht_info->ht_supported = true;
891 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
892 IEEE80211_HT_CAP_SM_PS |
893 IEEE80211_HT_CAP_SGI_40 |
894 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 895
9e98ac65
S		 896 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
897 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 898
d9fe60de
JB		 899 /* set up supported mcs set */
900 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
140add21
SB		 901 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
902 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
903
904 if (tx_streams != rx_streams) {
905 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
906 tx_streams, rx_streams);
907 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
908 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
909 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
910 }
eb2599ca 911
140add21
SB		 912 ht_info->mcs.rx_mask[0] = 0xff;
913 if (rx_streams >= 2)
eb2599ca 914 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 915
140add21 916 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 917}
918
8feceb67 919static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 920 struct ieee80211_vif *vif,
8feceb67 921 struct ieee80211_bss_conf *bss_conf)
f078f209 922{
f078f209 923
8feceb67 924 if (bss_conf->assoc) {
094d05dc 925 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 926 bss_conf->aid, sc->curbssid);
f078f209 927
8feceb67 928 /* New association, store aid */
2664f201
SB		 929 sc->curaid = bss_conf->aid;
930 ath9k_hw_write_associd(sc);
931
932 /*
933 * Request a re-configuration of Beacon related timers
934 * on the receipt of the first Beacon frame (i.e.,
935 * after time sync with the AP).
936 */
937 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 938
8feceb67 939 /* Configure the beacon */
2c3db3d5 940 ath_beacon_config(sc, vif);
f078f209 941
8feceb67 942 /* Reset rssi stats */
17d7904d
S		 943 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
944 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
945 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
946 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 947
415f738e 948 ath_start_ani(sc);
8feceb67 949 } else {
1ffb0610 950 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 951 sc->curaid = 0;
f38faa31
SB		 952 /* Stop ANI */
953 del_timer_sync(&sc->ani.timer);
f078f209 954 }
8feceb67 955}
f078f209 956
8feceb67
VT		 957/********************************/
958/* LED functions */
959/********************************/
f078f209 960
f2bffa7e
VT		 961static void ath_led_blink_work(struct work_struct *work)
962{
963 struct ath_softc *sc = container_of(work, struct ath_softc,
964 ath_led_blink_work.work);
965
966 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
967 return;
85067c06
VT		 968
969 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
970 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
971 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
972 else
973 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
974 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 975
976 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
977 (sc->sc_flags & SC_OP_LED_ON) ?
978 msecs_to_jiffies(sc->led_off_duration) :
979 msecs_to_jiffies(sc->led_on_duration));
980
85067c06
VT		 981 sc->led_on_duration = sc->led_on_cnt ?
982 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
983 ATH_LED_ON_DURATION_IDLE;
984 sc->led_off_duration = sc->led_off_cnt ?
985 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
986 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 987 sc->led_on_cnt = sc->led_off_cnt = 0;
988 if (sc->sc_flags & SC_OP_LED_ON)
989 sc->sc_flags &= ~SC_OP_LED_ON;
990 else
991 sc->sc_flags |= SC_OP_LED_ON;
992}
993
8feceb67
VT		 994static void ath_led_brightness(struct led_classdev *led_cdev,
995 enum led_brightness brightness)
996{
997 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
998 struct ath_softc *sc = led->sc;
f078f209 999
8feceb67
VT		 1000 switch (brightness) {
1001 case LED_OFF:
1002 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 1003 led->led_type == ATH_LED_RADIO) {
1004 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1005 (led->led_type == ATH_LED_RADIO));
8feceb67 1006 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1007 if (led->led_type == ATH_LED_RADIO)
1008 sc->sc_flags &= ~SC_OP_LED_ON;
1009 } else {
1010 sc->led_off_cnt++;
1011 }
8feceb67
VT		 1012 break;
1013 case LED_FULL:
f2bffa7e 1014 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1015 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1016 queue_delayed_work(sc->hw->workqueue,
1017 &sc->ath_led_blink_work, 0);
1018 } else if (led->led_type == ATH_LED_RADIO) {
1019 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1020 sc->sc_flags |= SC_OP_LED_ON;
1021 } else {
1022 sc->led_on_cnt++;
1023 }
8feceb67
VT		 1024 break;
1025 default:
1026 break;
f078f209 1027 }
8feceb67 1028}
f078f209 1029
8feceb67
VT		 1030static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1031 char *trigger)
1032{
1033 int ret;
f078f209 1034
8feceb67
VT		 1035 led->sc = sc;
1036 led->led_cdev.name = led->name;
1037 led->led_cdev.default_trigger = trigger;
1038 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1039
8feceb67
VT		 1040 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1041 if (ret)
1042 DPRINTF(sc, ATH_DBG_FATAL,
1043 "Failed to register led:%s", led->name);
1044 else
1045 led->registered = 1;
1046 return ret;
1047}
f078f209 1048
8feceb67
VT		 1049static void ath_unregister_led(struct ath_led *led)
1050{
1051 if (led->registered) {
1052 led_classdev_unregister(&led->led_cdev);
1053 led->registered = 0;
f078f209 1054 }
f078f209
LR		 1055}
1056
8feceb67 1057static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1058{
8feceb67
VT		 1059 ath_unregister_led(&sc->assoc_led);
1060 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1061 ath_unregister_led(&sc->tx_led);
1062 ath_unregister_led(&sc->rx_led);
1063 ath_unregister_led(&sc->radio_led);
1064 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1065}
f078f209 1066
8feceb67
VT		 1067static void ath_init_leds(struct ath_softc *sc)
1068{
1069 char *trigger;
1070 int ret;
f078f209 1071
8feceb67
VT		 1072 /* Configure gpio 1 for output */
1073 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1074 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1075 /* LED off, active low */
1076 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1077
f2bffa7e
VT		 1078 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1079
8feceb67
VT		 1080 trigger = ieee80211_get_radio_led_name(sc->hw);
1081 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1082 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1083 ret = ath_register_led(sc, &sc->radio_led, trigger);
1084 sc->radio_led.led_type = ATH_LED_RADIO;
1085 if (ret)
1086 goto fail;
7dcfdcd9 1087
8feceb67
VT		 1088 trigger = ieee80211_get_assoc_led_name(sc->hw);
1089 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1090 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1091 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1092 sc->assoc_led.led_type = ATH_LED_ASSOC;
1093 if (ret)
1094 goto fail;
f078f209 1095
8feceb67
VT		 1096 trigger = ieee80211_get_tx_led_name(sc->hw);
1097 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1098 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1099 ret = ath_register_led(sc, &sc->tx_led, trigger);
1100 sc->tx_led.led_type = ATH_LED_TX;
1101 if (ret)
1102 goto fail;
f078f209 1103
8feceb67
VT		 1104 trigger = ieee80211_get_rx_led_name(sc->hw);
1105 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1106 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1107 ret = ath_register_led(sc, &sc->rx_led, trigger);
1108 sc->rx_led.led_type = ATH_LED_RX;
1109 if (ret)
1110 goto fail;
f078f209 1111
8feceb67
VT		 1112 return;
1113
1114fail:
35c95ab9 1115 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67 1116 ath_deinit_leds(sc);
f078f209
LR		 1117}
1118
7ec3e514 1119void ath_radio_enable(struct ath_softc *sc)
500c064d 1120{
cbe61d8a 1121 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1122 struct ieee80211_channel *channel = sc->hw->conf.channel;
1123 int r;
500c064d 1124
3cbb5dd7 1125 ath9k_ps_wakeup(sc);
d2f5b3a6 1126 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1127
159cd468
VT		 1128 if (!ah->curchan)
1129 ah->curchan = ath_get_curchannel(sc, sc->hw);
1130
d2f5b3a6 1131 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1132 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1133 if (r) {
500c064d 1134 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1135 "Unable to reset channel %u (%uMhz) ",
6b45784f 1136 "reset status %d\n",
ae8d2858 1137 channel->center_freq, r);
500c064d
VT		 1138 }
1139 spin_unlock_bh(&sc->sc_resetlock);
1140
1141 ath_update_txpow(sc);
1142 if (ath_startrecv(sc) != 0) {
1143 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1144 "Unable to restart recv logic\n");
500c064d
VT		 1145 return;
1146 }
1147
1148 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1149 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1150
1151 /* Re-Enable interrupts */
17d7904d 1152 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1153
1154 /* Enable LED */
1155 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1156 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1157 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1158
1159 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1160 ath9k_ps_restore(sc);
500c064d
VT		 1161}
1162
7ec3e514 1163void ath_radio_disable(struct ath_softc *sc)
500c064d 1164{
cbe61d8a 1165 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1166 struct ieee80211_channel *channel = sc->hw->conf.channel;
1167 int r;
500c064d 1168
3cbb5dd7 1169 ath9k_ps_wakeup(sc);
500c064d
VT		 1170 ieee80211_stop_queues(sc->hw);
1171
1172 /* Disable LED */
1173 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1174 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1175
1176 /* Disable interrupts */
1177 ath9k_hw_set_interrupts(ah, 0);
1178
043a0405 1179 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1180 ath_stoprecv(sc); /* turn off frame recv */
1181 ath_flushrecv(sc); /* flush recv queue */
1182
159cd468
VT		 1183 if (!ah->curchan)
1184 ah->curchan = ath_get_curchannel(sc, sc->hw);
1185
500c064d 1186 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1187 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1188 if (r) {
500c064d 1189 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1190 "Unable to reset channel %u (%uMhz) "
6b45784f 1191 "reset status %d\n",
ae8d2858 1192 channel->center_freq, r);
500c064d
VT		 1193 }
1194 spin_unlock_bh(&sc->sc_resetlock);
1195
1196 ath9k_hw_phy_disable(ah);
d2f5b3a6 1197 ath9k_hw_configpcipowersave(ah, 1);
3cbb5dd7 1198 ath9k_ps_restore(sc);
38ab422e 1199 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1200}
1201
5077fd35
GJ		 1202/*******************/
1203/* Rfkill */
1204/*******************/
1205
500c064d
VT		 1206static bool ath_is_rfkill_set(struct ath_softc *sc)
1207{
cbe61d8a 1208 struct ath_hw *ah = sc->sc_ah;
500c064d 1209
2660b81a
S		 1210 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1211 ah->rfkill_polarity;
500c064d
VT		 1212}
1213
3b319aae 1214static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1215{
3b319aae
JB		 1216 struct ath_wiphy *aphy = hw->priv;
1217 struct ath_softc *sc = aphy->sc;
19d337df 1218 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1219
3b319aae
JB		 1220 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1221
1222 if (blocked)
19d337df
JB		 1223 ath_radio_disable(sc);
1224 else
1225 ath_radio_enable(sc);
500c064d
VT		 1226}
1227
3b319aae 1228static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1229{
3b319aae 1230 struct ath_hw *ah = sc->sc_ah;
9c84b797 1231
3b319aae
JB		 1232 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1233 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1234}
500c064d 1235
6baff7f9 1236void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1237{
1238 ath_detach(sc);
1239 free_irq(sc->irq, sc);
1240 ath_bus_cleanup(sc);
c52f33d0 1241 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1242 ieee80211_free_hw(sc->hw);
1243}
1244
6baff7f9 1245void ath_detach(struct ath_softc *sc)
f078f209 1246{
8feceb67 1247 struct ieee80211_hw *hw = sc->hw;
9c84b797 1248 int i = 0;
f078f209 1249
3cbb5dd7
VN		 1250 ath9k_ps_wakeup(sc);
1251
04bd4638 1252 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1253
35c95ab9
LR		 1254 ath_deinit_leds(sc);
1255
c52f33d0
JM		 1256 for (i = 0; i < sc->num_sec_wiphy; i++) {
1257 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1258 if (aphy == NULL)
1259 continue;
1260 sc->sec_wiphy[i] = NULL;
1261 ieee80211_unregister_hw(aphy->hw);
1262 ieee80211_free_hw(aphy->hw);
1263 }
3fcdfb4b 1264 ieee80211_unregister_hw(hw);
8feceb67
VT		 1265 ath_rx_cleanup(sc);
1266 ath_tx_cleanup(sc);
f078f209 1267
9c84b797
S		 1268 tasklet_kill(&sc->intr_tq);
1269 tasklet_kill(&sc->bcon_tasklet);
f078f209 1270
9c84b797
S		 1271 if (!(sc->sc_flags & SC_OP_INVALID))
1272 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1273
9c84b797
S		 1274 /* cleanup tx queues */
1275 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1276 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1277 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1278
1279 ath9k_hw_detach(sc->sc_ah);
826d2680 1280 ath9k_exit_debug(sc);
f078f209
LR		 1281}
1282
e3bb249b
BC		 1283static int ath9k_reg_notifier(struct wiphy *wiphy,
1284 struct regulatory_request *request)
1285{
1286 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1287 struct ath_wiphy *aphy = hw->priv;
1288 struct ath_softc *sc = aphy->sc;
1289 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1290
1291 return ath_reg_notifier_apply(wiphy, request, reg);
1292}
1293
ff37e337
S		 1294static int ath_init(u16 devid, struct ath_softc *sc)
1295{
cbe61d8a 1296 struct ath_hw *ah = NULL;
ff37e337
S		 1297 int status;
1298 int error = 0, i;
1299 int csz = 0;
1300
1301 /* XXX: hardware will not be ready until ath_open() being called */
1302 sc->sc_flags |= SC_OP_INVALID;
88b126af 1303
826d2680
S		 1304 if (ath9k_init_debug(sc) < 0)
1305 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1306
c52f33d0 1307 spin_lock_init(&sc->wiphy_lock);
ff37e337 1308 spin_lock_init(&sc->sc_resetlock);
6158425b 1309 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1310 spin_lock_init(&sc->ani_lock);
04717ccd 1311 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1312 mutex_init(&sc->mutex);
ff37e337 1313 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1314 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1315 (unsigned long)sc);
1316
1317 /*
1318 * Cache line size is used to size and align various
1319 * structures used to communicate with the hardware.
1320 */
88d15707 1321 ath_read_cachesize(sc, &csz);
ff37e337 1322 /* XXX assert csz is non-zero */
17d7904d 1323 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1324
cbe61d8a 1325 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1326 if (ah == NULL) {
1327 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1328 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1329 error = -ENXIO;
1330 goto bad;
1331 }
1332 sc->sc_ah = ah;
1333
1334 /* Get the hardware key cache size. */
2660b81a 1335 sc->keymax = ah->caps.keycache_size;
17d7904d 1336 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1337 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1338 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1339 ATH_KEYMAX, sc->keymax);
1340 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1341 }
1342
1343 /*
1344 * Reset the key cache since some parts do not
1345 * reset the contents on initial power up.
1346 */
17d7904d 1347 for (i = 0; i < sc->keymax; i++)
ff37e337 1348 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1349
85efc86e 1350 if (error)
ff37e337
S		 1351 goto bad;
1352
1353 /* default to MONITOR mode */
2660b81a 1354 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1355
ff37e337
S		 1356 /* Setup rate tables */
1357
1358 ath_rate_attach(sc);
1359 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1360 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1361
1362 /*
1363 * Allocate hardware transmit queues: one queue for
1364 * beacon frames and one data queue for each QoS
1365 * priority. Note that the hal handles reseting
1366 * these queues at the needed time.
1367 */
b77f483f
S		 1368 sc->beacon.beaconq = ath_beaconq_setup(ah);
1369 if (sc->beacon.beaconq == -1) {
ff37e337 1370 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1371 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1372 error = -EIO;
1373 goto bad2;
1374 }
b77f483f
S		 1375 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1376 if (sc->beacon.cabq == NULL) {
ff37e337 1377 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1378 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1379 error = -EIO;
1380 goto bad2;
1381 }
1382
17d7904d 1383 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1384 ath_cabq_update(sc);
1385
b77f483f
S		 1386 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1387 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1388
1389 /* Setup data queues */
1390 /* NB: ensure BK queue is the lowest priority h/w queue */
1391 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1392 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1393 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1394 error = -EIO;
1395 goto bad2;
1396 }
1397
1398 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1399 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1400 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1401 error = -EIO;
1402 goto bad2;
1403 }
1404 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1405 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1406 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1407 error = -EIO;
1408 goto bad2;
1409 }
1410 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1411 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1412 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1413 error = -EIO;
1414 goto bad2;
1415 }
1416
1417 /* Initializes the noise floor to a reasonable default value.
1418 * Later on this will be updated during ANI processing. */
1419
17d7904d
S		 1420 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1421 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1422
1423 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1424 ATH9K_CIPHER_TKIP, NULL)) {
1425 /*
1426 * Whether we should enable h/w TKIP MIC.
1427 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1428 * report WMM capable, so it's always safe to turn on
1429 * TKIP MIC in this case.
1430 */
1431 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1432 0, 1, NULL);
1433 }
1434
1435 /*
1436 * Check whether the separate key cache entries
1437 * are required to handle both tx+rx MIC keys.
1438 * With split mic keys the number of stations is limited
1439 * to 27 otherwise 59.
1440 */
1441 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1442 ATH9K_CIPHER_TKIP, NULL)
1443 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1444 ATH9K_CIPHER_MIC, NULL)
1445 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1446 0, NULL))
17d7904d 1447 sc->splitmic = 1;
ff37e337
S		 1448
1449 /* turn on mcast key search if possible */
1450 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1451 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1452 1, NULL);
1453
17d7904d 1454 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1455
1456 /* 11n Capabilities */
2660b81a 1457 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1458 sc->sc_flags |= SC_OP_TXAGGR;
1459 sc->sc_flags |= SC_OP_RXAGGR;
1460 }
1461
2660b81a
S		 1462 sc->tx_chainmask = ah->caps.tx_chainmask;
1463 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1464
1465 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1466 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1467
8ca21f01 1468 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1469 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1470
b77f483f 1471 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1472
1473 /* initialize beacon slots */
c52f33d0 1474 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1475 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1476 sc->beacon.bslot_aphy[i] = NULL;
1477 }
ff37e337 1478
ff37e337
S		 1479 /* setup channels and rates */
1480
5f8e077c 1481 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1482 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1483 sc->rates[IEEE80211_BAND_2GHZ];
1484 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1485 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1486 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1487
2660b81a 1488 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1489 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1490 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1491 sc->rates[IEEE80211_BAND_5GHZ];
1492 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1493 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1494 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1495 }
1496
2660b81a 1497 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1498 ath9k_hw_btcoex_enable(sc->sc_ah);
1499
ff37e337
S		 1500 return 0;
1501bad2:
1502 /* cleanup tx queues */
1503 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1504 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1505 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1506bad:
1507 if (ah)
1508 ath9k_hw_detach(ah);
40b130a9 1509 ath9k_exit_debug(sc);
ff37e337
S		 1510
1511 return error;
1512}
1513
c52f33d0 1514void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1515{
9c84b797
S		 1516 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1517 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1518 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1519 IEEE80211_HW_AMPDU_AGGREGATION |
1520 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1521 IEEE80211_HW_PS_NULLFUNC_STACK |
1522 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1523
b3bd89ce 1524 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1525 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1526
9c84b797
S		 1527 hw->wiphy->interface_modes =
1528 BIT(NL80211_IFTYPE_AP) |
1529 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1530 BIT(NL80211_IFTYPE_ADHOC) |
1531 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1532
8feceb67 1533 hw->queues = 4;
e63835b0 1534 hw->max_rates = 4;
171387ef 1535 hw->channel_change_time = 5000;
465ca84d 1536 hw->max_listen_interval = 10;
dd190183
LR		 1537 /* Hardware supports 10 but we use 4 */
1538 hw->max_rate_tries = 4;
528f0c6b 1539 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1540 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1541
8feceb67 1542 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1543
c52f33d0
JM		 1544 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1545 &sc->sbands[IEEE80211_BAND_2GHZ];
1546 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1547 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1548 &sc->sbands[IEEE80211_BAND_5GHZ];
1549}
1550
1551int ath_attach(u16 devid, struct ath_softc *sc)
1552{
1553 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1554 int error = 0, i;
3a702e49 1555 struct ath_regulatory *reg;
c52f33d0
JM		 1556
1557 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1558
1559 error = ath_init(devid, sc);
1560 if (error != 0)
1561 return error;
1562
1563 /* get mac address from hardware and set in mac80211 */
1564
1565 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1566
1567 ath_set_hw_capab(sc, hw);
1568
c26c2e57
LR		 1569 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1570 ath9k_reg_notifier);
1571 if (error)
1572 return error;
1573
1574 reg = &sc->sc_ah->regulatory;
1575
2660b81a 1576 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1577 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1578 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1579 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1580 }
1581
db93e7b5
SB		 1582 /* initialize tx/rx engine */
1583 error = ath_tx_init(sc, ATH_TXBUF);
1584 if (error != 0)
40b130a9 1585 goto error_attach;
8feceb67 1586
db93e7b5
SB		 1587 error = ath_rx_init(sc, ATH_RXBUF);
1588 if (error != 0)
40b130a9 1589 goto error_attach;
8feceb67 1590
0e2dedf9 1591 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1592 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1593 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1594
db93e7b5 1595 error = ieee80211_register_hw(hw);
8feceb67 1596
3a702e49 1597 if (!ath_is_world_regd(reg)) {
c02cf373 1598 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1599 if (error)
1600 goto error_attach;
1601 }
5f8e077c 1602
db93e7b5
SB		 1603 /* Initialize LED control */
1604 ath_init_leds(sc);
8feceb67 1605
3b319aae 1606 ath_start_rfkill_poll(sc);
5f8e077c 1607
8feceb67 1608 return 0;
40b130a9
VT		 1609
1610error_attach:
1611 /* cleanup tx queues */
1612 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1613 if (ATH_TXQ_SETUP(sc, i))
1614 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1615
1616 ath9k_hw_detach(sc->sc_ah);
1617 ath9k_exit_debug(sc);
1618
8feceb67 1619 return error;
f078f209
LR		 1620}
1621
ff37e337
S		 1622int ath_reset(struct ath_softc *sc, bool retry_tx)
1623{
cbe61d8a 1624 struct ath_hw *ah = sc->sc_ah;
030bb495 1625 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1626 int r;
ff37e337
S		 1627
1628 ath9k_hw_set_interrupts(ah, 0);
043a0405 1629 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1630 ath_stoprecv(sc);
1631 ath_flushrecv(sc);
1632
1633 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1634 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1635 if (r)
ff37e337 1636 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1637 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1638 spin_unlock_bh(&sc->sc_resetlock);
1639
1640 if (ath_startrecv(sc) != 0)
04bd4638 1641 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1642
1643 /*
1644 * We may be doing a reset in response to a request
1645 * that changes the channel so update any state that
1646 * might change as a result.
1647 */
ce111bad 1648 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1649
1650 ath_update_txpow(sc);
1651
1652 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1653 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1654
17d7904d 1655 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1656
1657 if (retry_tx) {
1658 int i;
1659 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1660 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1661 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1662 ath_txq_schedule(sc, &sc->tx.txq[i]);
1663 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1664 }
1665 }
1666 }
1667
ae8d2858 1668 return r;
ff37e337
S		 1669}
1670
1671/*
1672 * This function will allocate both the DMA descriptor structure, and the
1673 * buffers it contains. These are used to contain the descriptors used
1674 * by the system.
1675*/
1676int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1677 struct list_head *head, const char *name,
1678 int nbuf, int ndesc)
1679{
1680#define DS2PHYS(_dd, _ds) \
1681 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1682#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1683#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1684
1685 struct ath_desc *ds;
1686 struct ath_buf *bf;
1687 int i, bsize, error;
1688
04bd4638
S		 1689 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1690 name, nbuf, ndesc);
ff37e337 1691
b03a9db9 1692 INIT_LIST_HEAD(head);
ff37e337
S		 1693 /* ath_desc must be a multiple of DWORDs */
1694 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1695 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1696 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1697 error = -ENOMEM;
1698 goto fail;
1699 }
1700
ff37e337
S		 1701 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1702
1703 /*
1704 * Need additional DMA memory because we can't use
1705 * descriptors that cross the 4K page boundary. Assume
1706 * one skipped descriptor per 4K page.
1707 */
2660b81a 1708 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1709 u32 ndesc_skipped =
1710 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1711 u32 dma_len;
1712
1713 while (ndesc_skipped) {
1714 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1715 dd->dd_desc_len += dma_len;
1716
1717 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1718 };
1719 }
1720
1721 /* allocate descriptors */
7da3c55c 1722 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1723 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1724 if (dd->dd_desc == NULL) {
1725 error = -ENOMEM;
1726 goto fail;
1727 }
1728 ds = dd->dd_desc;
04bd4638 1729 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1730 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1731 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1732
1733 /* allocate buffers */
1734 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1735 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1736 if (bf == NULL) {
1737 error = -ENOMEM;
1738 goto fail2;
1739 }
ff37e337
S		 1740 dd->dd_bufptr = bf;
1741
ff37e337
S		 1742 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1743 bf->bf_desc = ds;
1744 bf->bf_daddr = DS2PHYS(dd, ds);
1745
2660b81a 1746 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1747 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1748 /*
1749 * Skip descriptor addresses which can cause 4KB
1750 * boundary crossing (addr + length) with a 32 dword
1751 * descriptor fetch.
1752 */
1753 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1754 ASSERT((caddr_t) bf->bf_desc <
1755 ((caddr_t) dd->dd_desc +
1756 dd->dd_desc_len));
1757
1758 ds += ndesc;
1759 bf->bf_desc = ds;
1760 bf->bf_daddr = DS2PHYS(dd, ds);
1761 }
1762 }
1763 list_add_tail(&bf->list, head);
1764 }
1765 return 0;
1766fail2:
7da3c55c
GJ		 1767 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1768 dd->dd_desc_paddr);
ff37e337
S		 1769fail:
1770 memset(dd, 0, sizeof(*dd));
1771 return error;
1772#undef ATH_DESC_4KB_BOUND_CHECK
1773#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1774#undef DS2PHYS
1775}
1776
1777void ath_descdma_cleanup(struct ath_softc *sc,
1778 struct ath_descdma *dd,
1779 struct list_head *head)
1780{
7da3c55c
GJ		 1781 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1782 dd->dd_desc_paddr);
ff37e337
S		 1783
1784 INIT_LIST_HEAD(head);
1785 kfree(dd->dd_bufptr);
1786 memset(dd, 0, sizeof(*dd));
1787}
1788
1789int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1790{
1791 int qnum;
1792
1793 switch (queue) {
1794 case 0:
b77f483f 1795 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1796 break;
1797 case 1:
b77f483f 1798 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1799 break;
1800 case 2:
b77f483f 1801 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1802 break;
1803 case 3:
b77f483f 1804 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1805 break;
1806 default:
b77f483f 1807 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1808 break;
1809 }
1810
1811 return qnum;
1812}
1813
1814int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1815{
1816 int qnum;
1817
1818 switch (queue) {
1819 case ATH9K_WME_AC_VO:
1820 qnum = 0;
1821 break;
1822 case ATH9K_WME_AC_VI:
1823 qnum = 1;
1824 break;
1825 case ATH9K_WME_AC_BE:
1826 qnum = 2;
1827 break;
1828 case ATH9K_WME_AC_BK:
1829 qnum = 3;
1830 break;
1831 default:
1832 qnum = -1;
1833 break;
1834 }
1835
1836 return qnum;
1837}
1838
5f8e077c
LR		 1839/* XXX: Remove me once we don't depend on ath9k_channel for all
1840 * this redundant data */
0e2dedf9
JM		 1841void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1842 struct ath9k_channel *ichan)
5f8e077c 1843{
5f8e077c
LR		 1844 struct ieee80211_channel *chan = hw->conf.channel;
1845 struct ieee80211_conf *conf = &hw->conf;
1846
1847 ichan->channel = chan->center_freq;
1848 ichan->chan = chan;
1849
1850 if (chan->band == IEEE80211_BAND_2GHZ) {
1851 ichan->chanmode = CHANNEL_G;
1852 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1853 } else {
1854 ichan->chanmode = CHANNEL_A;
1855 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1856 }
1857
1858 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1859
1860 if (conf_is_ht(conf)) {
1861 if (conf_is_ht40(conf))
1862 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1863
1864 ichan->chanmode = ath_get_extchanmode(sc, chan,
1865 conf->channel_type);
1866 }
1867}
1868
ff37e337
S		 1869/**********************/
1870/* mac80211 callbacks */
1871/**********************/
1872
8feceb67 1873static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1874{
bce048d7
JM		 1875 struct ath_wiphy *aphy = hw->priv;
1876 struct ath_softc *sc = aphy->sc;
8feceb67 1877 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1878 struct ath9k_channel *init_channel;
82880a7c 1879 int r;
f078f209 1880
04bd4638
S		 1881 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1882 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1883
141b38b6
S		 1884 mutex_lock(&sc->mutex);
1885
9580a222
JM		 1886 if (ath9k_wiphy_started(sc)) {
1887 if (sc->chan_idx == curchan->hw_value) {
1888 /*
1889 * Already on the operational channel, the new wiphy
1890 * can be marked active.
1891 */
1892 aphy->state = ATH_WIPHY_ACTIVE;
1893 ieee80211_wake_queues(hw);
1894 } else {
1895 /*
1896 * Another wiphy is on another channel, start the new
1897 * wiphy in paused state.
1898 */
1899 aphy->state = ATH_WIPHY_PAUSED;
1900 ieee80211_stop_queues(hw);
1901 }
1902 mutex_unlock(&sc->mutex);
1903 return 0;
1904 }
1905 aphy->state = ATH_WIPHY_ACTIVE;
1906
8feceb67 1907 /* setup initial channel */
f078f209 1908
82880a7c 1909 sc->chan_idx = curchan->hw_value;
f078f209 1910
82880a7c 1911 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 1912
1913 /* Reset SERDES registers */
1914 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1915
1916 /*
1917 * The basic interface to setting the hardware in a good
1918 * state is ``reset''. On return the hardware is known to
1919 * be powered up and with interrupts disabled. This must
1920 * be followed by initialization of the appropriate bits
1921 * and then setup of the interrupt mask.
1922 */
1923 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1924 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1925 if (r) {
ff37e337 1926 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1927 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 1928 "(freq %u MHz)\n", r,
1929 curchan->center_freq);
ff37e337 1930 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1931 goto mutex_unlock;
ff37e337
S		 1932 }
1933 spin_unlock_bh(&sc->sc_resetlock);
1934
1935 /*
1936 * This is needed only to setup initial state
1937 * but it's best done after a reset.
1938 */
1939 ath_update_txpow(sc);
8feceb67 1940
ff37e337
S		 1941 /*
1942 * Setup the hardware after reset:
1943 * The receive engine is set going.
1944 * Frame transmit is handled entirely
1945 * in the frame output path; there's nothing to do
1946 * here except setup the interrupt mask.
1947 */
1948 if (ath_startrecv(sc) != 0) {
1ffb0610 1949 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 1950 r = -EIO;
1951 goto mutex_unlock;
f078f209 1952 }
8feceb67 1953
ff37e337 1954 /* Setup our intr mask. */
17d7904d 1955 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 1956 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1957 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1958
2660b81a 1959 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 1960 sc->imask |= ATH9K_INT_GTT;
ff37e337 1961
2660b81a 1962 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 1963 sc->imask |= ATH9K_INT_CST;
ff37e337 1964
ce111bad 1965 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1966
1967 sc->sc_flags &= ~SC_OP_INVALID;
1968
1969 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 1970 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1971 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 1972
bce048d7 1973 ieee80211_wake_queues(hw);
ff37e337 1974
164ace38
SB		 1975 queue_delayed_work(sc->hw->workqueue, &sc->tx_complete_work, 0);
1976
141b38b6
S		 1977mutex_unlock:
1978 mutex_unlock(&sc->mutex);
1979
ae8d2858 1980 return r;
f078f209
LR		 1981}
1982
8feceb67
VT		 1983static int ath9k_tx(struct ieee80211_hw *hw,
1984 struct sk_buff *skb)
f078f209 1985{
528f0c6b 1986 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 1987 struct ath_wiphy *aphy = hw->priv;
1988 struct ath_softc *sc = aphy->sc;
528f0c6b 1989 struct ath_tx_control txctl;
8feceb67 1990 int hdrlen, padsize;
528f0c6b 1991
8089cc47 1992 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 1993 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
1994 "%d\n", wiphy_name(hw->wiphy), aphy->state);
1995 goto exit;
1996 }
1997
96148326 1998 if (sc->ps_enabled) {
dc8c4585
JM		 1999 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2000 /*
2001 * mac80211 does not set PM field for normal data frames, so we
2002 * need to update that based on the current PS mode.
2003 */
2004 if (ieee80211_is_data(hdr->frame_control) &&
2005 !ieee80211_is_nullfunc(hdr->frame_control) &&
2006 !ieee80211_has_pm(hdr->frame_control)) {
2007 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2008 "while in PS mode\n");
2009 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2010 }
2011 }
2012
9a23f9ca
JM		 2013 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2014 /*
2015 * We are using PS-Poll and mac80211 can request TX while in
2016 * power save mode. Need to wake up hardware for the TX to be
2017 * completed and if needed, also for RX of buffered frames.
2018 */
2019 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2020 ath9k_ps_wakeup(sc);
2021 ath9k_hw_setrxabort(sc->sc_ah, 0);
2022 if (ieee80211_is_pspoll(hdr->frame_control)) {
2023 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2024 "buffered frame\n");
2025 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2026 } else {
2027 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2028 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2029 }
2030 /*
2031 * The actual restore operation will happen only after
2032 * the sc_flags bit is cleared. We are just dropping
2033 * the ps_usecount here.
2034 */
2035 ath9k_ps_restore(sc);
2036 }
2037
528f0c6b 2038 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2039
8feceb67
VT		 2040 /*
2041 * As a temporary workaround, assign seq# here; this will likely need
2042 * to be cleaned up to work better with Beacon transmission and virtual
2043 * BSSes.
2044 */
2045 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2046 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2047 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2048 sc->tx.seq_no += 0x10;
8feceb67 2049 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2050 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2051 }
f078f209 2052
8feceb67
VT		 2053 /* Add the padding after the header if this is not already done */
2054 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2055 if (hdrlen & 3) {
2056 padsize = hdrlen % 4;
2057 if (skb_headroom(skb) < padsize)
2058 return -1;
2059 skb_push(skb, padsize);
2060 memmove(skb->data, skb->data + padsize, hdrlen);
2061 }
2062
528f0c6b
S		 2063 /* Check if a tx queue is available */
2064
2065 txctl.txq = ath_test_get_txq(sc, skb);
2066 if (!txctl.txq)
2067 goto exit;
2068
04bd4638 2069 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2070
c52f33d0 2071 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2072 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2073 goto exit;
8feceb67
VT		 2074 }
2075
528f0c6b
S		 2076 return 0;
2077exit:
2078 dev_kfree_skb_any(skb);
8feceb67 2079 return 0;
f078f209
LR		 2080}
2081
8feceb67 2082static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2083{
bce048d7
JM		 2084 struct ath_wiphy *aphy = hw->priv;
2085 struct ath_softc *sc = aphy->sc;
f078f209 2086
9580a222
JM		 2087 aphy->state = ATH_WIPHY_INACTIVE;
2088
c94dbff7
LR		 2089 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2090 cancel_delayed_work_sync(&sc->tx_complete_work);
2091
2092 if (!sc->num_sec_wiphy) {
2093 cancel_delayed_work_sync(&sc->wiphy_work);
2094 cancel_work_sync(&sc->chan_work);
2095 }
2096
9c84b797 2097 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2098 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2099 return;
2100 }
8feceb67 2101
141b38b6 2102 mutex_lock(&sc->mutex);
ff37e337 2103
9580a222
JM		 2104 if (ath9k_wiphy_started(sc)) {
2105 mutex_unlock(&sc->mutex);
2106 return; /* another wiphy still in use */
2107 }
2108
ff37e337
S		 2109 /* make sure h/w will not generate any interrupt
2110 * before setting the invalid flag. */
2111 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2112
2113 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2114 ath_drain_all_txq(sc, false);
ff37e337
S		 2115 ath_stoprecv(sc);
2116 ath9k_hw_phy_disable(sc->sc_ah);
2117 } else
b77f483f 2118 sc->rx.rxlink = NULL;
ff37e337 2119
3b319aae 2120 wiphy_rfkill_stop_polling(sc->hw->wiphy);
19d337df 2121
ff37e337
S		 2122 /* disable HAL and put h/w to sleep */
2123 ath9k_hw_disable(sc->sc_ah);
2124 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2125
2126 sc->sc_flags |= SC_OP_INVALID;
500c064d 2127
141b38b6
S		 2128 mutex_unlock(&sc->mutex);
2129
04bd4638 2130 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2131}
2132
8feceb67
VT		 2133static int ath9k_add_interface(struct ieee80211_hw *hw,
2134 struct ieee80211_if_init_conf *conf)
f078f209 2135{
bce048d7
JM		 2136 struct ath_wiphy *aphy = hw->priv;
2137 struct ath_softc *sc = aphy->sc;
17d7904d 2138 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2139 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2140 int ret = 0;
8feceb67 2141
141b38b6
S		 2142 mutex_lock(&sc->mutex);
2143
8ca21f01
JM		 2144 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2145 sc->nvifs > 0) {
2146 ret = -ENOBUFS;
2147 goto out;
2148 }
2149
8feceb67 2150 switch (conf->type) {
05c914fe 2151 case NL80211_IFTYPE_STATION:
d97809db 2152 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2153 break;
05c914fe 2154 case NL80211_IFTYPE_ADHOC:
05c914fe 2155 case NL80211_IFTYPE_AP:
9cb5412b 2156 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2157 if (sc->nbcnvifs >= ATH_BCBUF) {
2158 ret = -ENOBUFS;
2159 goto out;
2160 }
9cb5412b 2161 ic_opmode = conf->type;
f078f209
LR		 2162 break;
2163 default:
2164 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2165 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2166 ret = -EOPNOTSUPP;
2167 goto out;
f078f209
LR		 2168 }
2169
17d7904d 2170 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2171
17d7904d 2172 /* Set the VIF opmode */
5640b08e
S		 2173 avp->av_opmode = ic_opmode;
2174 avp->av_bslot = -1;
2175
2c3db3d5 2176 sc->nvifs++;
8ca21f01
JM		 2177
2178 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2179 ath9k_set_bssid_mask(hw);
2180
2c3db3d5
JM		 2181 if (sc->nvifs > 1)
2182 goto out; /* skip global settings for secondary vif */
2183
b238e90e 2184 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2185 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2186 sc->sc_flags |= SC_OP_TSF_RESET;
2187 }
5640b08e 2188
5640b08e 2189 /* Set the device opmode */
2660b81a 2190 sc->sc_ah->opmode = ic_opmode;
5640b08e 2191
4e30ffa2
VN		 2192 /*
2193 * Enable MIB interrupts when there are hardware phy counters.
2194 * Note we only do this (at the moment) for station mode.
2195 */
4af9cf4f 2196 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2197 (conf->type == NL80211_IFTYPE_ADHOC) ||
2198 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2199 if (ath9k_hw_phycounters(sc->sc_ah))
2200 sc->imask |= ATH9K_INT_MIB;
2201 sc->imask |= ATH9K_INT_TSFOOR;
2202 }
2203
17d7904d 2204 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2205
f38faa31
SB		 2206 if (conf->type == NL80211_IFTYPE_AP ||
2207 conf->type == NL80211_IFTYPE_ADHOC ||
2208 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2209 ath_start_ani(sc);
6f255425 2210
2c3db3d5 2211out:
141b38b6 2212 mutex_unlock(&sc->mutex);
2c3db3d5 2213 return ret;
f078f209
LR		 2214}
2215
8feceb67
VT		 2216static void ath9k_remove_interface(struct ieee80211_hw *hw,
2217 struct ieee80211_if_init_conf *conf)
f078f209 2218{
bce048d7
JM		 2219 struct ath_wiphy *aphy = hw->priv;
2220 struct ath_softc *sc = aphy->sc;
17d7904d 2221 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2222 int i;
f078f209 2223
04bd4638 2224 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2225
141b38b6
S		 2226 mutex_lock(&sc->mutex);
2227
6f255425 2228 /* Stop ANI */
17d7904d 2229 del_timer_sync(&sc->ani.timer);
580f0b8a 2230
8feceb67 2231 /* Reclaim beacon resources */
9cb5412b
PE		 2232 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2233 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2234 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2235 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2236 ath_beacon_return(sc, avp);
580f0b8a 2237 }
f078f209 2238
8feceb67 2239 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2240
2c3db3d5
JM		 2241 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2242 if (sc->beacon.bslot[i] == conf->vif) {
2243 printk(KERN_DEBUG "%s: vif had allocated beacon "
2244 "slot\n", __func__);
2245 sc->beacon.bslot[i] = NULL;
c52f33d0 2246 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2247 }
2248 }
2249
17d7904d 2250 sc->nvifs--;
141b38b6
S		 2251
2252 mutex_unlock(&sc->mutex);
f078f209
LR		 2253}
2254
e8975581 2255static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2256{
bce048d7
JM		 2257 struct ath_wiphy *aphy = hw->priv;
2258 struct ath_softc *sc = aphy->sc;
e8975581 2259 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2260 struct ath_hw *ah = sc->sc_ah;
64839170 2261 bool all_wiphys_idle = false, disable_radio = false;
f078f209 2262
aa33de09 2263 mutex_lock(&sc->mutex);
141b38b6 2264
64839170
LR		 2265 /* Leave this as the first check */
2266 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2267
2268 spin_lock_bh(&sc->wiphy_lock);
2269 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2270 spin_unlock_bh(&sc->wiphy_lock);
2271
2272 if (conf->flags & IEEE80211_CONF_IDLE){
2273 if (all_wiphys_idle)
2274 disable_radio = true;
2275 }
2276 else if (all_wiphys_idle) {
2277 ath_radio_enable(sc);
2278 DPRINTF(sc, ATH_DBG_CONFIG,
2279 "not-idle: enabling radio\n");
2280 }
2281 }
2282
3cbb5dd7
VN		 2283 if (changed & IEEE80211_CONF_CHANGE_PS) {
2284 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2285 if (!(ah->caps.hw_caps &
2286 ATH9K_HW_CAP_AUTOSLEEP)) {
2287 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2288 sc->imask |= ATH9K_INT_TIM_TIMER;
2289 ath9k_hw_set_interrupts(sc->sc_ah,
2290 sc->imask);
2291 }
2292 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2293 }
96148326 2294 sc->ps_enabled = true;
3cbb5dd7 2295 } else {
96148326 2296 sc->ps_enabled = false;
3cbb5dd7 2297 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2298 if (!(ah->caps.hw_caps &
2299 ATH9K_HW_CAP_AUTOSLEEP)) {
2300 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2301 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2302 SC_OP_WAIT_FOR_CAB |
2303 SC_OP_WAIT_FOR_PSPOLL_DATA |
2304 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2305 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2306 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2307 ath9k_hw_set_interrupts(sc->sc_ah,
2308 sc->imask);
2309 }
3cbb5dd7
VN		 2310 }
2311 }
2312 }
2313
4797938c 2314 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2315 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2316 int pos = curchan->hw_value;
ae5eb026 2317
0e2dedf9
JM		 2318 aphy->chan_idx = pos;
2319 aphy->chan_is_ht = conf_is_ht(conf);
2320
8089cc47
JM		 2321 if (aphy->state == ATH_WIPHY_SCAN ||
2322 aphy->state == ATH_WIPHY_ACTIVE)
2323 ath9k_wiphy_pause_all_forced(sc, aphy);
2324 else {
2325 /*
2326 * Do not change operational channel based on a paused
2327 * wiphy changes.
2328 */
2329 goto skip_chan_change;
2330 }
0e2dedf9 2331
04bd4638
S		 2332 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2333 curchan->center_freq);
f078f209 2334
5f8e077c 2335 /* XXX: remove me eventualy */
0e2dedf9 2336 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2337
ecf70441 2338 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2339
0e2dedf9 2340 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2341 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2342 mutex_unlock(&sc->mutex);
e11602b7
S		 2343 return -EINVAL;
2344 }
094d05dc 2345 }
f078f209 2346
8089cc47 2347skip_chan_change:
5c020dc6 2348 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2349 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2350
64839170
LR		 2351 if (disable_radio) {
2352 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
2353 ath_radio_disable(sc);
2354 }
2355
aa33de09 2356 mutex_unlock(&sc->mutex);
141b38b6 2357
f078f209
LR		 2358 return 0;
2359}
2360
8feceb67
VT		 2361#define SUPPORTED_FILTERS \
2362 (FIF_PROMISC_IN_BSS | \
2363 FIF_ALLMULTI | \
2364 FIF_CONTROL | \
2365 FIF_OTHER_BSS | \
2366 FIF_BCN_PRBRESP_PROMISC | \
2367 FIF_FCSFAIL)
c83be688 2368
8feceb67
VT		 2369/* FIXME: sc->sc_full_reset ? */
2370static void ath9k_configure_filter(struct ieee80211_hw *hw,
2371 unsigned int changed_flags,
2372 unsigned int *total_flags,
2373 int mc_count,
2374 struct dev_mc_list *mclist)
2375{
bce048d7
JM		 2376 struct ath_wiphy *aphy = hw->priv;
2377 struct ath_softc *sc = aphy->sc;
8feceb67 2378 u32 rfilt;
f078f209 2379
8feceb67
VT		 2380 changed_flags &= SUPPORTED_FILTERS;
2381 *total_flags &= SUPPORTED_FILTERS;
f078f209 2382
b77f483f 2383 sc->rx.rxfilter = *total_flags;
aa68aeaa 2384 ath9k_ps_wakeup(sc);
8feceb67
VT		 2385 rfilt = ath_calcrxfilter(sc);
2386 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2387 ath9k_ps_restore(sc);
f078f209 2388
b77f483f 2389 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2390}
f078f209 2391
8feceb67
VT		 2392static void ath9k_sta_notify(struct ieee80211_hw *hw,
2393 struct ieee80211_vif *vif,
2394 enum sta_notify_cmd cmd,
17741cdc 2395 struct ieee80211_sta *sta)
8feceb67 2396{
bce048d7
JM		 2397 struct ath_wiphy *aphy = hw->priv;
2398 struct ath_softc *sc = aphy->sc;
f078f209 2399
8feceb67
VT		 2400 switch (cmd) {
2401 case STA_NOTIFY_ADD:
5640b08e 2402 ath_node_attach(sc, sta);
8feceb67
VT		 2403 break;
2404 case STA_NOTIFY_REMOVE:
b5aa9bf9 2405 ath_node_detach(sc, sta);
8feceb67
VT		 2406 break;
2407 default:
2408 break;
2409 }
f078f209
LR		 2410}
2411
141b38b6 2412static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2413 const struct ieee80211_tx_queue_params *params)
f078f209 2414{
bce048d7
JM		 2415 struct ath_wiphy *aphy = hw->priv;
2416 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2417 struct ath9k_tx_queue_info qi;
2418 int ret = 0, qnum;
f078f209 2419
8feceb67
VT		 2420 if (queue >= WME_NUM_AC)
2421 return 0;
f078f209 2422
141b38b6
S		 2423 mutex_lock(&sc->mutex);
2424
1ffb0610
S		 2425 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2426
8feceb67
VT		 2427 qi.tqi_aifs = params->aifs;
2428 qi.tqi_cwmin = params->cw_min;
2429 qi.tqi_cwmax = params->cw_max;
2430 qi.tqi_burstTime = params->txop;
2431 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2432
8feceb67 2433 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2434 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2435 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2436 queue, qnum, params->aifs, params->cw_min,
2437 params->cw_max, params->txop);
f078f209 2438
8feceb67
VT		 2439 ret = ath_txq_update(sc, qnum, &qi);
2440 if (ret)
04bd4638 2441 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2442
141b38b6
S		 2443 mutex_unlock(&sc->mutex);
2444
8feceb67
VT		 2445 return ret;
2446}
f078f209 2447
8feceb67
VT		 2448static int ath9k_set_key(struct ieee80211_hw *hw,
2449 enum set_key_cmd cmd,
dc822b5d
JB		 2450 struct ieee80211_vif *vif,
2451 struct ieee80211_sta *sta,
8feceb67
VT		 2452 struct ieee80211_key_conf *key)
2453{
bce048d7
JM		 2454 struct ath_wiphy *aphy = hw->priv;
2455 struct ath_softc *sc = aphy->sc;
8feceb67 2456 int ret = 0;
f078f209 2457
b3bd89ce
JM		 2458 if (modparam_nohwcrypt)
2459 return -ENOSPC;
2460
141b38b6 2461 mutex_lock(&sc->mutex);
3cbb5dd7 2462 ath9k_ps_wakeup(sc);
d8baa939 2463 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2464
8feceb67
VT		 2465 switch (cmd) {
2466 case SET_KEY:
3f53dd64 2467 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2468 if (ret >= 0) {
2469 key->hw_key_idx = ret;
8feceb67
VT		 2470 /* push IV and Michael MIC generation to stack */
2471 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2472 if (key->alg == ALG_TKIP)
2473 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2474 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2475 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2476 ret = 0;
8feceb67
VT		 2477 }
2478 break;
2479 case DISABLE_KEY:
2480 ath_key_delete(sc, key);
8feceb67
VT		 2481 break;
2482 default:
2483 ret = -EINVAL;
2484 }
f078f209 2485
3cbb5dd7 2486 ath9k_ps_restore(sc);
141b38b6
S		 2487 mutex_unlock(&sc->mutex);
2488
8feceb67
VT		 2489 return ret;
2490}
f078f209 2491
8feceb67
VT		 2492static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2493 struct ieee80211_vif *vif,
2494 struct ieee80211_bss_conf *bss_conf,
2495 u32 changed)
2496{
bce048d7
JM		 2497 struct ath_wiphy *aphy = hw->priv;
2498 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2499 struct ath_hw *ah = sc->sc_ah;
2500 struct ath_vif *avp = (void *)vif->drv_priv;
2501 u32 rfilt = 0;
2502 int error, i;
f078f209 2503
141b38b6
S		 2504 mutex_lock(&sc->mutex);
2505
2d0ddec5
JB		 2506 /*
2507 * TODO: Need to decide which hw opmode to use for
2508 * multi-interface cases
2509 * XXX: This belongs into add_interface!
2510 */
2511 if (vif->type == NL80211_IFTYPE_AP &&
2512 ah->opmode != NL80211_IFTYPE_AP) {
2513 ah->opmode = NL80211_IFTYPE_STATION;
2514 ath9k_hw_setopmode(ah);
2515 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2516 sc->curaid = 0;
2517 ath9k_hw_write_associd(sc);
2518 /* Request full reset to get hw opmode changed properly */
2519 sc->sc_flags |= SC_OP_FULL_RESET;
2520 }
2521
2522 if ((changed & BSS_CHANGED_BSSID) &&
2523 !is_zero_ether_addr(bss_conf->bssid)) {
2524 switch (vif->type) {
2525 case NL80211_IFTYPE_STATION:
2526 case NL80211_IFTYPE_ADHOC:
2527 case NL80211_IFTYPE_MESH_POINT:
2528 /* Set BSSID */
2529 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2530 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2531 sc->curaid = 0;
2532 ath9k_hw_write_associd(sc);
2533
2534 /* Set aggregation protection mode parameters */
2535 sc->config.ath_aggr_prot = 0;
2536
2537 DPRINTF(sc, ATH_DBG_CONFIG,
2538 "RX filter 0x%x bssid %pM aid 0x%x\n",
2539 rfilt, sc->curbssid, sc->curaid);
2540
2541 /* need to reconfigure the beacon */
2542 sc->sc_flags &= ~SC_OP_BEACONS ;
2543
2544 break;
2545 default:
2546 break;
2547 }
2548 }
2549
2550 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2551 (vif->type == NL80211_IFTYPE_AP) ||
2552 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2553 if ((changed & BSS_CHANGED_BEACON) ||
2554 (changed & BSS_CHANGED_BEACON_ENABLED &&
2555 bss_conf->enable_beacon)) {
2556 /*
2557 * Allocate and setup the beacon frame.
2558 *
2559 * Stop any previous beacon DMA. This may be
2560 * necessary, for example, when an ibss merge
2561 * causes reconfiguration; we may be called
2562 * with beacon transmission active.
2563 */
2564 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2565
2566 error = ath_beacon_alloc(aphy, vif);
2567 if (!error)
2568 ath_beacon_config(sc, vif);
2569 }
2570 }
2571
2572 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2573 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2574 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2575 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2576 ath9k_hw_keysetmac(sc->sc_ah,
2577 (u16)i,
2578 sc->curbssid);
2579 }
2580
2581 /* Only legacy IBSS for now */
2582 if (vif->type == NL80211_IFTYPE_ADHOC)
2583 ath_update_chainmask(sc, 0);
2584
8feceb67 2585 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2586 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2587 bss_conf->use_short_preamble);
2588 if (bss_conf->use_short_preamble)
2589 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2590 else
2591 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2592 }
f078f209 2593
8feceb67 2594 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2595 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2596 bss_conf->use_cts_prot);
2597 if (bss_conf->use_cts_prot &&
2598 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2599 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2600 else
2601 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2602 }
f078f209 2603
8feceb67 2604 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2605 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2606 bss_conf->assoc);
5640b08e 2607 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2608 }
141b38b6 2609
57c4d7b4
JB		 2610 /*
2611 * The HW TSF has to be reset when the beacon interval changes.
2612 * We set the flag here, and ath_beacon_config_ap() would take this
2613 * into account when it gets called through the subsequent
2614 * config_interface() call - with IFCC_BEACON in the changed field.
2615 */
2616
2617 if (changed & BSS_CHANGED_BEACON_INT) {
2618 sc->sc_flags |= SC_OP_TSF_RESET;
2619 sc->beacon_interval = bss_conf->beacon_int;
2620 }
2621
141b38b6 2622 mutex_unlock(&sc->mutex);
8feceb67 2623}
f078f209 2624
8feceb67
VT		 2625static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2626{
2627 u64 tsf;
bce048d7
JM		 2628 struct ath_wiphy *aphy = hw->priv;
2629 struct ath_softc *sc = aphy->sc;
f078f209 2630
141b38b6
S		 2631 mutex_lock(&sc->mutex);
2632 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2633 mutex_unlock(&sc->mutex);
f078f209 2634
8feceb67
VT		 2635 return tsf;
2636}
f078f209 2637
3b5d665b
AF		 2638static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2639{
bce048d7
JM		 2640 struct ath_wiphy *aphy = hw->priv;
2641 struct ath_softc *sc = aphy->sc;
3b5d665b 2642
141b38b6
S		 2643 mutex_lock(&sc->mutex);
2644 ath9k_hw_settsf64(sc->sc_ah, tsf);
2645 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2646}
2647
8feceb67
VT		 2648static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2649{
bce048d7
JM		 2650 struct ath_wiphy *aphy = hw->priv;
2651 struct ath_softc *sc = aphy->sc;
c83be688 2652
141b38b6
S		 2653 mutex_lock(&sc->mutex);
2654 ath9k_hw_reset_tsf(sc->sc_ah);
2655 mutex_unlock(&sc->mutex);
8feceb67 2656}
f078f209 2657
8feceb67 2658static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2659 enum ieee80211_ampdu_mlme_action action,
2660 struct ieee80211_sta *sta,
2661 u16 tid, u16 *ssn)
8feceb67 2662{
bce048d7
JM		 2663 struct ath_wiphy *aphy = hw->priv;
2664 struct ath_softc *sc = aphy->sc;
8feceb67 2665 int ret = 0;
f078f209 2666
8feceb67
VT		 2667 switch (action) {
2668 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2669 if (!(sc->sc_flags & SC_OP_RXAGGR))
2670 ret = -ENOTSUPP;
8feceb67
VT		 2671 break;
2672 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2673 break;
2674 case IEEE80211_AMPDU_TX_START:
f83da965
S		 2675 ath_tx_aggr_start(sc, sta, tid, ssn);
2676 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2677 break;
2678 case IEEE80211_AMPDU_TX_STOP:
f83da965 2679 ath_tx_aggr_stop(sc, sta, tid);
17741cdc 2680 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2681 break;
b1720231 2682 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2683 ath_tx_aggr_resume(sc, sta, tid);
2684 break;
8feceb67 2685 default:
04bd4638 2686 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2687 }
2688
2689 return ret;
f078f209
LR		 2690}
2691
0c98de65
S		 2692static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2693{
bce048d7
JM		 2694 struct ath_wiphy *aphy = hw->priv;
2695 struct ath_softc *sc = aphy->sc;
0c98de65 2696
8089cc47
JM		 2697 if (ath9k_wiphy_scanning(sc)) {
2698 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2699 "same time\n");
2700 /*
2701 * Do not allow the concurrent scanning state for now. This
2702 * could be improved with scanning control moved into ath9k.
2703 */
2704 return;
2705 }
2706
2707 aphy->state = ATH_WIPHY_SCAN;
2708 ath9k_wiphy_pause_all_forced(sc, aphy);
2709
e5f0921a 2710 spin_lock_bh(&sc->ani_lock);
0c98de65 2711 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 2712 spin_unlock_bh(&sc->ani_lock);
0c98de65
S		 2713}
2714
2715static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2716{
bce048d7
JM		 2717 struct ath_wiphy *aphy = hw->priv;
2718 struct ath_softc *sc = aphy->sc;
0c98de65 2719
e5f0921a 2720 spin_lock_bh(&sc->ani_lock);
8089cc47 2721 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2722 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2723 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 2724 spin_unlock_bh(&sc->ani_lock);
0c98de65
S		 2725}
2726
6baff7f9 2727struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2728 .tx = ath9k_tx,
2729 .start = ath9k_start,
2730 .stop = ath9k_stop,
2731 .add_interface = ath9k_add_interface,
2732 .remove_interface = ath9k_remove_interface,
2733 .config = ath9k_config,
8feceb67 2734 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2735 .sta_notify = ath9k_sta_notify,
2736 .conf_tx = ath9k_conf_tx,
8feceb67 2737 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2738 .set_key = ath9k_set_key,
8feceb67 2739 .get_tsf = ath9k_get_tsf,
3b5d665b 2740 .set_tsf = ath9k_set_tsf,
8feceb67 2741 .reset_tsf = ath9k_reset_tsf,
4233df6b 2742 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2743 .sw_scan_start = ath9k_sw_scan_start,
2744 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2745 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 2746};
2747
392dff83
BP		 2748static struct {
2749 u32 version;
2750 const char * name;
2751} ath_mac_bb_names[] = {
2752 { AR_SREV_VERSION_5416_PCI, "5416" },
2753 { AR_SREV_VERSION_5416_PCIE, "5418" },
2754 { AR_SREV_VERSION_9100, "9100" },
2755 { AR_SREV_VERSION_9160, "9160" },
2756 { AR_SREV_VERSION_9280, "9280" },
ac88b6ec
VN		 2757 { AR_SREV_VERSION_9285, "9285" },
2758 { AR_SREV_VERSION_9287, "9287" }
392dff83
BP		 2759};
2760
2761static struct {
2762 u16 version;
2763 const char * name;
2764} ath_rf_names[] = {
2765 { 0, "5133" },
2766 { AR_RAD5133_SREV_MAJOR, "5133" },
2767 { AR_RAD5122_SREV_MAJOR, "5122" },
2768 { AR_RAD2133_SREV_MAJOR, "2133" },
2769 { AR_RAD2122_SREV_MAJOR, "2122" }
2770};
2771
2772/*
2773 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2774 */
6baff7f9 2775const char *
392dff83
BP		 2776ath_mac_bb_name(u32 mac_bb_version)
2777{
2778 int i;
2779
2780 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2781 if (ath_mac_bb_names[i].version == mac_bb_version) {
2782 return ath_mac_bb_names[i].name;
2783 }
2784 }
2785
2786 return "????";
2787}
2788
2789/*
2790 * Return the RF name. "????" is returned if the RF is unknown.
2791 */
6baff7f9 2792const char *
392dff83
BP		 2793ath_rf_name(u16 rf_version)
2794{
2795 int i;
2796
2797 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2798 if (ath_rf_names[i].version == rf_version) {
2799 return ath_rf_names[i].name;
2800 }
2801 }
2802
2803 return "????";
2804}
2805
6baff7f9 2806static int __init ath9k_init(void)
f078f209 2807{
ca8a8560
VT		 2808 int error;
2809
ca8a8560
VT		 2810 /* Register rate control algorithm */
2811 error = ath_rate_control_register();
2812 if (error != 0) {
2813 printk(KERN_ERR
b51bb3cd
LR		 2814 "ath9k: Unable to register rate control "
2815 "algorithm: %d\n",
ca8a8560 2816 error);
6baff7f9 2817 goto err_out;
ca8a8560
VT		 2818 }
2819
19d8bc22
GJ		 2820 error = ath9k_debug_create_root();
2821 if (error) {
2822 printk(KERN_ERR
2823 "ath9k: Unable to create debugfs root: %d\n",
2824 error);
2825 goto err_rate_unregister;
2826 }
2827
6baff7f9
GJ		 2828 error = ath_pci_init();
2829 if (error < 0) {
f078f209 2830 printk(KERN_ERR
b51bb3cd 2831 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2832 error = -ENODEV;
19d8bc22 2833 goto err_remove_root;
f078f209
LR		 2834 }
2835
09329d37
GJ		 2836 error = ath_ahb_init();
2837 if (error < 0) {
2838 error = -ENODEV;
2839 goto err_pci_exit;
2840 }
2841
f078f209 2842 return 0;
6baff7f9 2843
09329d37
GJ		 2844 err_pci_exit:
2845 ath_pci_exit();
2846
19d8bc22
GJ		 2847 err_remove_root:
2848 ath9k_debug_remove_root();
6baff7f9
GJ		 2849 err_rate_unregister:
2850 ath_rate_control_unregister();
2851 err_out:
2852 return error;
f078f209 2853}
6baff7f9 2854module_init(ath9k_init);
f078f209 2855
6baff7f9 2856static void __exit ath9k_exit(void)
f078f209 2857{
09329d37 2858 ath_ahb_exit();
6baff7f9 2859 ath_pci_exit();
19d8bc22 2860 ath9k_debug_remove_root();
ca8a8560 2861 ath_rate_control_unregister();
04bd4638 2862 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2863}
6baff7f9 2864module_exit(ath9k_exit);
Linux kernel - Deliverables
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